JP2010239131A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2010239131A JP2010239131A JP2010052983A JP2010052983A JP2010239131A JP 2010239131 A JP2010239131 A JP 2010239131A JP 2010052983 A JP2010052983 A JP 2010052983A JP 2010052983 A JP2010052983 A JP 2010052983A JP 2010239131 A JP2010239131 A JP 2010239131A
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- insulating film
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- film
- heat treatment
- semiconductor layer
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Classifications
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
Abstract
【解決手段】酸化物半導体層成膜直後から酸化物半導体層上に接して酸化シリコンを含む無機絶縁膜を形成する直前までの間に1回も加熱処理を行わず、基板上の酸化物半導体層上に接して第2の絶縁膜を形成した後に加熱処理を行うプロセス順序とする。また、酸化シリコンを含む無機絶縁膜において、膜中に含まれる水素密度は、5×1020/cm3以上、または窒素密度は、1×1019/cm3以上とする。
【選択図】図1
Description
まず、絶縁表面を有する基板400上にゲート電極層401を形成し、ゲート電極層を覆うゲート絶縁層403を形成する。
本実施の形態では、加熱処理をランプ光源を用いて行う例を示す。
本実施の形態では、薄膜トランジスタ及びその作製工程について、図8乃至図14を用いて説明する。
本実施の形態では、半導体装置として発光表示装置の一例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、前者は有機EL素子、後者は無機EL素子と呼ばれている。
本実施の形態では、半導体装置として電子ペーパーの一例を示す。
酸化物半導体層を用いた薄膜トランジスタを含む半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
101 ゲート電極
102 ゲート絶縁層
103 半導体層
104a ソース領域
104b ドレイン領域
105a ソース電極層
105b ドレイン電極層
107 保護絶縁膜
108 容量配線
109 コンタクトホール
110 画素電極
111a、111b、111c In−Ga−Zn−O系非単結晶膜
121 端子
122 端子
123 In−Ga−Zn−O系非単結晶膜
124 容量電極層
125 コンタクトホール
126 コンタクトホール
127 コンタクトホール
128 透明導電膜
129 透明導電膜
150 端子
151 端子
152 ゲート絶縁層
153 接続電極
154 保護絶縁膜
155 透明導電膜
156 電極
170 薄膜トランジスタ
Claims (12)
- 絶縁表面を有する基板上に非晶質構造を有する酸化物半導体層を形成し、
前記酸化物半導体層上に接する酸化シリコンを含む無機絶縁膜を形成し、
前記酸化シリコンを含む無機絶縁膜を形成した後に、300℃以上の加熱処理を行い、
前記加熱処理は、前記酸化シリコンを含む無機絶縁膜の成膜時における基板温度よりも高く、且つ、加熱処理後の酸化物半導体層は、非晶質構造を有する半導体装置の作製方法。 - 絶縁表面を有する基板上にゲート電極を形成し、
前記ゲート電極上にゲート絶縁層を形成し、
前記ゲート絶縁層上に非晶質構造を有する酸化物半導体層を形成し、
前記酸化物半導体層上にソース電極及びドレイン電極を形成し、
前記酸化物半導体層上に接する酸化シリコンを含む無機絶縁膜を形成し、
前記酸化シリコンを含む無機絶縁膜の成膜後に300℃以上、且つ、前記絶縁表面を有する基板の歪み点以下の加熱処理を行う半導体装置の作製方法。 - 請求項2において、前記酸化シリコンを含む無機絶縁膜の成膜時における基板温度は、前記ゲート絶縁層の成膜時における基板温度よりも低い半導体装置の作製方法。
- 請求項2または請求項3において、前記加熱処理は、前記酸化シリコンを含む無機絶縁膜の成膜時における基板温度よりも高く、且つ、加熱処理後の酸化物半導体層は、非晶質構造を有する半導体装置の作製方法。
- 請求項1乃至4のいずれか一において、前記酸化シリコンを含む無機絶縁膜に含まれる水素濃度は、5×1020/cm3以上である半導体装置の作製方法。
- 請求項1乃至5のいずれか一において、前記酸化シリコンを含む無機絶縁膜に含まれる窒素濃度は、1×1019/cm3以上である半導体装置の作製方法。
- 請求項1乃至6のいずれか一において、前記加熱処理は大気雰囲気下或いは窒素雰囲気下での加熱処理である半導体装置の作製方法。
- 請求項1乃至7のいずれか一において、前記酸化シリコンを含む無機絶縁膜は、少なくともN2Oガスを用いて成膜する半導体装置の作製方法。
- 請求項2乃至8のいずれか一において、前記ゲート絶縁層は、酸化シリコンを含む無機絶縁膜であり、少なくともN2Oガスを用いて成膜する半導体装置の作製方法。
- 請求項1乃至9のいずれか一において、前記酸化物半導体層上に接する酸化シリコンを含む無機絶縁膜の成膜時における基板温度は100℃以上300℃以下である半導体装置の作製方法。
- 請求項1乃至10のいずれか一において、前記酸化物半導体層は、インジウム、ガリウム、または亜鉛を含むことを特徴とする半導体装置の作製方法。
- 請求項1乃至11のいずれか一において、さらに前記加熱処理後に前記酸化シリコンを含む無機絶縁膜上に接する配線を形成する半導体装置の作製方法。
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JP2012256870A (ja) * | 2011-05-13 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 表示装置 |
JP2013041260A (ja) * | 2011-07-15 | 2013-02-28 | Semiconductor Energy Lab Co Ltd | 表示装置及び表示装置の駆動方法 |
JP2022002320A (ja) * | 2012-06-29 | 2022-01-06 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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JP2014199918A (ja) * | 2013-01-21 | 2014-10-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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CN101894759B (zh) | 2014-08-20 |
JP5707046B2 (ja) | 2015-04-22 |
TWI485781B (zh) | 2015-05-21 |
KR20170032254A (ko) | 2017-03-22 |
KR101718753B1 (ko) | 2017-03-22 |
CN101894759A (zh) | 2010-11-24 |
US20100233848A1 (en) | 2010-09-16 |
CN104124280B (zh) | 2017-10-27 |
TW201104758A (en) | 2011-02-01 |
US8936963B2 (en) | 2015-01-20 |
KR20100103414A (ko) | 2010-09-27 |
CN104124280A (zh) | 2014-10-29 |
TWI556323B (zh) | 2016-11-01 |
TW201523742A (zh) | 2015-06-16 |
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