CN107768307A - 背沟道蚀刻型tft基板及其制作方法 - Google Patents

背沟道蚀刻型tft基板及其制作方法 Download PDF

Info

Publication number
CN107768307A
CN107768307A CN201711167386.5A CN201711167386A CN107768307A CN 107768307 A CN107768307 A CN 107768307A CN 201711167386 A CN201711167386 A CN 201711167386A CN 107768307 A CN107768307 A CN 107768307A
Authority
CN
China
Prior art keywords
drain electrode
source
layer
material layer
electrode material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711167386.5A
Other languages
English (en)
Inventor
姜春生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN201711167386.5A priority Critical patent/CN107768307A/zh
Priority to US15/749,105 priority patent/US10355035B2/en
Priority to PCT/CN2017/117327 priority patent/WO2019100492A1/zh
Publication of CN107768307A publication Critical patent/CN107768307A/zh
Priority to US16/460,973 priority patent/US10714514B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

本发明提供一种背沟道蚀刻型TFT基板及其制作方法。本发明的背沟道蚀刻型TFT基板的制作方法将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层出现鼓泡和翘起现象；另外，在源极与漏极的制作过程中采用无氟蚀刻液对源极与漏极之间的间隔区进行蚀刻去除，不会对有源层的沟道区造成损害。本发明的背沟道蚀刻型TFT基板将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层鼓泡和翘起的现象。

Description

背沟道蚀刻型TFT基板及其制作方法
技术领域
本发明涉及显示技术领域，尤其涉及一种背沟道蚀刻型TFT基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置和有源矩阵型OLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，非晶硅(a-Si)材料是比较常见的一种。
随着液晶显示装置和OLED显示装置向着大尺寸和高分辨率的方向发展，传统的a-Si仅有1cm2/(Vs)左右的迁移率已经无法满足要求，以铟镓锌氧化物(IGZO)为代表的金属氧化物材料具备超过10cm2/(Vs)以上的迁移率，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的产线的兼容性好，近年来迅速成为显示领域研发的重点。
相对于传统的a-Si TFT，IGZO TFT具有以下优势：
1、提高显示背板的分辨率，在保证相同透过率的前提下，IGZO TFT显示背板的分辨率可以做到a-Si TFT的2倍以上，IGZO材料中的载流子浓度高，迁移率大，可以缩小TFT的体积，保证分辨率的提升；
2、减少显示器件的能耗，IGZO TFT与a-Si TFT、LTPS TFT相比，漏电流小于1pA；驱动频率由原来的30-50Hz减少到2-5Hz，通过特殊工艺，甚至可以达到1Hz，虽然减少TFT的驱动次数，仍然可以维持液晶分子的配向，不影响画面的质量，从而减少显示背板的耗电量；另外，IGZO半导体材料的高迁移率使得较小尺寸的TFT即可提供足够的充电能力和较高的电容值，而且提高了液晶面板的开口率，光穿透的有效面积变大，可以用较少的背板组件或低功率消耗达到相同的亮度，减少能耗；
3、通过采用间歇式驱动等方式，能够降低液晶显示器驱动电路的噪点对触摸屏检测电路造成的影响，可以实现更高的灵敏度，甚至尖头的圆珠笔笔端也能够响应，而且由于画面无更新时可以切断电源，因此其在节能的效果上表现更为优秀。
目前，IGZO作为半导体有源层的TFT一般采用刻蚀阻挡(ESL)结构，由于有刻蚀阻挡层(Etch Stop Layer)存在，源漏极(Source/Drain)的蚀刻过程中，刻蚀阻挡层可以有效的保护IGZO不受到影响，保证TFT具有优异的半导体特性。但是ESL结构的IGZO TFT的制备过程较为复杂，需要经过6次黄光工艺，不利于降低成本，因此业界普遍追求黄光工艺更少的背沟道蚀刻(BCE)结构的IGZO TFT的开发。
无论是ESL结构的TFT还是BCE结构的TFT，源漏极金属上均覆盖有钝化层(PV)。与a-Si TFT不同，IGZO TFT的钝化层的材质通常为氧化硅(SiOx)，源漏极金属的材质为铜(Cu)，由于铜与氧化硅之间的结合力非常差，因此在TFT基板的制备过程中，源漏极金属上的钝化层薄膜会翘起，形成鼓泡(Bubble)，从而影响良率。
发明内容
本发明的目的在于提供一种背沟道蚀刻型TFT基板的制作方法，能够避免钝化层出现鼓泡和翘起现象，同时不会对有源层的沟道区造成损害。
本发明的目的还在于提供一种背沟道蚀刻型TFT基板，其钝化层不会出现鼓泡和翘起现象，具有优异的电学特性。
为实现上述目的，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上沉积金属材料并刻蚀形成栅极，在所述衬底基板及栅极上形成栅极绝缘层；
在所述栅极绝缘层上形成有源层；
在所述有源层与栅极绝缘层上沉积源漏极材料层，所述源漏极材料层包括设于所述有源层与栅极绝缘层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层；
在源漏极材料层上定义出源漏极图案区与设于所述源漏极图案区周围的非图案区，其中，所述源漏极图案区包括源极预定图案区、漏极预定图案区及位于源极预定图案区与漏极预定图案区之间的源漏极间隔区；
在所述源漏极材料层上形成光阻层，采用半色调掩膜板对所述光阻层进行图形化处理，去除所述光阻层上对应于非图案区的部分，使所述光阻层上对应于源漏极间隔区的部分的厚度减薄；
采用含氟蚀刻液对所述源漏极材料层的非图案区进行蚀刻去除；
对剩余的光阻层进行灰化处理，去除所述光阻层上对应于源漏极间隔区的部分，使所述光阻层上对应于所述源极预定图案区与漏极预定图案区的部分的厚度减薄；
采用无氟蚀刻液对所述源漏极材料层的源漏极间隔区进行蚀刻去除；
剥离剩余的光阻层，得到间隔设置的源极与漏极；
在所述源极、漏极、有源层及栅极绝缘层上形成钝化层。
所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜。
所述有源层的材料包括铟镓锌氧化物。
所述钝化层的材料包括氧化硅。
本发明还提供一种背沟道蚀刻型TFT基板，包括：衬底基板、设于所述衬底基板上的栅极、设于所述衬底基板及栅极上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层上且间隔设置的源极与漏极以及设于所述源极、漏极、有源层及栅极绝缘层上的钝化层；
所述源极与漏极由源漏极材料层图案化形成，所述源漏极材料层包括设于所述有源层上的第一源漏极材料层、设于所述第一源漏极材料层上的第二源漏极材料层以及设于所述第二源漏极材料层上的第三源漏极材料层，所述第一源漏极材料层的材料包括钼，所述第二源漏极材料层的材料包括铜，所述第三源漏极材料层为导体化IGZO膜层。
所述导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
所述栅极包括设于所述衬底基板上的第一栅极层与设于所述第一栅极层上的第二栅极层，所述第一栅极层的材料包括钼，所述第二栅极层的材料包括铜。
所述有源层的材料包括铟镓锌氧化物。
所述钝化层的材料包括氧化硅。
本发明的有益效果：本发明的背沟道蚀刻型TFT基板的制作方法将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层出现鼓泡和翘起现象；另外，在源极与漏极的制作过程中采用无氟蚀刻液对源极与漏极之间的间隔区进行蚀刻去除，不会对有源层的沟道区造成损害。本发明的背沟道蚀刻型TFT基板将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层鼓泡和翘起的现象。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的背沟道蚀刻型TFT基板的制作方法的流程图；
图2为本发明的背沟道蚀刻型TFT基板的制作方法的步骤1的示意图；
图3为本发明的背沟道蚀刻型TFT基板的制作方法的步骤2的示意图；
图4为本发明的背沟道蚀刻型TFT基板的制作方法的步骤3的示意图；
图5至图10为本发明的背沟道蚀刻型TFT基板的制作方法的步骤4的示意图；
图11为本发明的背沟道蚀刻型TFT基板的制作方法的步骤5的示意图及本发明的背沟道蚀刻型TFT基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种背沟道蚀刻型TFT基板的制作方法，包括如下步骤：
步骤1、如图2所示，提供衬底基板10，在所述衬底基板10上沉积金属材料并刻蚀形成栅极20，在所述衬底基板10及栅极20上形成栅极绝缘层30。
具体的，所述栅极20包括设于所述衬底基板10上的第一栅极层21与设于所述第一栅极层21上的第二栅极层22，所述第一栅极层21的材料包括钼，所述第二栅极层22的材料包括铜。
步骤2、如图3所示，在所述栅极绝缘层30上形成有源层40。
具体的，所述有源层40的材料包括铟镓锌氧化物(IGZO)。
具体的，所述有源层40通过溅射沉积制程与光刻图案化制程得到。
步骤3、如图4所示，在所述有源层40与栅极绝缘层30上沉积源漏极材料层70，所述源漏极材料层70包括设于所述有源层40与栅极绝缘层30上的第一源漏极材料层41、设于所述第一源漏极材料层41上的第二源漏极材料层42以及设于所述第二源漏极材料层42上的第三源漏极材料层43，所述第一源漏极材料层41的材料包括钼，所述第二源漏极材料层42的材料包括铜，所述第三源漏极材料层43为导体化IGZO膜层。
具体的，所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
正常情况下，IGZO的磁控溅射过程中，反应腔体内会通入氧气，保证得到的IGZO膜层中铟镓锌氧的比例为In：Ga：Zn：O＝1：1：1：4，从而保证IGZO膜层具有半导体特性。本发明通过去除磁控溅射过程中反应腔体内的氧气，使制得的导体化IGZO膜层中的氧含量降低，实现导体化功能。
步骤4、如图5至图6所示，在源漏极材料层70上定义出源漏极图案区71与设于所述源漏极图案区71周围的非图案区72，其中，所述源漏极图案区71包括源极预定图案区711、漏极预定图案区712及位于源极预定图案区711与漏极预定图案区712之间的源漏极间隔区713；
在所述源漏极材料层70上形成光阻层80，采用半色调掩膜板90对所述光阻层80进行图形化处理，去除所述光阻层80上对应于非图案区72的部分，使所述光阻层80上对应于源漏极间隔区713的部分的厚度减薄；
如图7所示，采用含氟蚀刻液对所述源漏极材料层70的非图案区72进行蚀刻去除；所述含氟蚀刻液能够同时对第三源漏极材料层43、第二源漏极材料层42及第一源漏极材料层41进行蚀刻，并且所述含氟蚀刻液对第三源漏极材料层43、第二源漏极材料层42及第一源漏极材料层41均具有较快的蚀刻速度。
具体的，所述含氟蚀刻液为含氟酸性铜蚀刻液，其具体成分为现有技术，此处不做介绍。
如图8所示，对剩余的光阻层80进行灰化处理，去除所述光阻层80上对应于源漏极间隔区713的部分，使所述光阻层80上对应于所述源极预定图案区711与漏极预定图案区712的部分的厚度减薄；
如图9所示，采用无氟蚀刻液对所述源漏极材料层70的源漏极间隔区713进行蚀刻去除；所述无氟蚀刻液能够同时对第三源漏极材料层43、第二源漏极材料层42及第一源漏极材料层41进行蚀刻，并且所述无氟蚀刻液对第二源漏极材料层42与第一源漏极材料层41具有较快的蚀刻速度，对第三源漏极材料层43具有较慢的蚀刻速度，即，所述无氟蚀刻液对IGZO的蚀刻速度小于所述含氟蚀刻液对IGZO的蚀刻速度。
由于无氟蚀刻液对IGZO的蚀刻速度较慢，因此采用无氟蚀刻液对所述源漏极材料层70的源漏极间隔区713进行蚀刻时，通过控制蚀刻时间可以保证由IGZO材料制备的有源层40的沟道区不受到损害，提升TFT器件稳定性。
具体的，所述无氟蚀刻液为无氟酸性铜蚀刻液，其具体成分为现有技术，此处不做介绍。
如图10所示，剥离剩余的光阻层80，得到间隔设置的源极51与漏极52。
本申请发明人试验过采用其它金属材料(如钛)代替导体化IGZO来制备第三源漏极材料层43，以增强源极51和漏极52与氧化硅之间的结合力，但是采用金属铜制备的第二源漏极材料层42往往与由其它金属材料制备的第三源漏极材料层43之间形成溶液电池，导致发生电化学反应，从而在源漏极材料层70的蚀刻过程中，由其它金属材料制备的第三源漏极材料层43层容易被腐蚀溶解掉，导致第三源漏极材料层43上方的光阻层80被剥离掉，进而导致源极51和漏极52的光刻制程失败。而本申请采用导体化IGZO材料来制备第三源漏极材料层43，以增强源极51和漏极52与氧化硅之间的结合力，导体化IGZO材料的第三源漏极材料层43与金属铜材料的第二源漏极材料层42之间不会形成溶液电池，不会发生电化学反应，因此在源漏极材料层70的蚀刻过程中，第三源漏极材料层43不会被溶解，其上方的光阻层80不会被剥离掉。
步骤5、如图11所示，在所述源极51、漏极52、有源层40及栅极绝缘层30上形成钝化层60。
具体的，所述钝化层60的材料包括氧化硅(SiOx)。
由于所述源极51与漏极52的表层即第三源漏极材料层43的材料为导体化IGZO，而导体化IGZO与氧化硅之间的结合力较强，因此可以避免钝化层60出现鼓泡和翘起现象。
本发明的背沟道蚀刻型TFT基板的制作方法将源极51与漏极52的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层60出现鼓泡和翘起现象；另外，在源极51与漏极52的制作过程中采用无氟蚀刻液对源极51与漏极52之间的间隔区进行蚀刻去除，不会对有源层40的沟道区造成损害。
请参阅图11，同时参阅图2至图10，基于上述背沟道蚀刻型TFT基板的制作方法，本发明提供一种背沟道蚀刻型TFT基板，包括：衬底基板10、设于所述衬底基板10上的栅极20、设于所述衬底基板10及栅极20上的栅极绝缘层30、设于所述栅极绝缘层30上的有源层40、设于所述有源层40上且间隔设置的源极51与漏极52以及设于所述源极51、漏极52、有源层40及栅极绝缘层30上的钝化层60；
所述源极51与漏极52由源漏极材料层70图案化形成，所述源漏极材料层70包括设于所述有源层40上的第一源漏极材料层41、设于所述第一源漏极材料层41上的第二源漏极材料层42以及设于所述第二源漏极材料层42上的第三源漏极材料层43，所述第一源漏极材料层41的材料包括钼，所述第二源漏极材料层42的材料包括铜，所述第三源漏极材料层43为导体化IGZO膜层。
具体的，所述导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
具体的，所述栅极20包括设于所述衬底基板上的第一栅极层21与设于所述第一栅极层21上的第二栅极层22，所述第一栅极层21的材料包括钼，所述第二栅极层22的材料包括铜。
具体的，所述有源层40的材料包括铟镓锌氧化物(IGZO)。
本发明的背沟道蚀刻型TFT基板将源极51与漏极52的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层60鼓泡和翘起的现象。
综上所述，本发明提供一种背沟道蚀刻型TFT基板及其制作方法。本发明的背沟道蚀刻型TFT基板的制作方法将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此可以避免钝化层出现鼓泡和翘起现象；另外，在源极与漏极的制作过程中采用无氟蚀刻液对源极与漏极之间的间隔区进行蚀刻去除，不会对有源层的沟道区造成损害。本发明的背沟道蚀刻型TFT基板将源极与漏极的表层设置为导体化IGZO膜层，由于导体化IGZO膜层与氧化硅之间的结合力较强，因此不会出现钝化层鼓泡和翘起的现象。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种背沟道蚀刻型TFT基板的制作方法，其特征在于，包括：
提供衬底基板(10)，在所述衬底基板(10)上沉积金属材料并刻蚀形成栅极(20)，在所述衬底基板(10)及栅极(20)上形成栅极绝缘层(30)；
在所述栅极绝缘层(30)上形成有源层(40)；
在所述有源层(40)与栅极绝缘层(30)上沉积源漏极材料层(70)，所述源漏极材料层(70)包括设于所述有源层(40)与栅极绝缘层(30)上的第一源漏极材料层(41)、设于所述第一源漏极材料层(41)上的第二源漏极材料层(42)以及设于所述第二源漏极材料层(42)上的第三源漏极材料层(43)，所述第一源漏极材料层(41)的材料包括钼，所述第二源漏极材料层(42)的材料包括铜，所述第三源漏极材料层(43)为导体化IGZO膜层；
在源漏极材料层(70)上定义出源漏极图案区(71)与设于所述源漏极图案区(71)周围的非图案区(72)，其中，所述源漏极图案区(71)包括源极预定图案区(711)、漏极预定图案区(712)及位于源极预定图案区(711)与漏极预定图案区(712)之间的源漏极间隔区(713)；
在所述源漏极材料层(70)上形成光阻层(80)，采用半色调掩膜板(90)对所述光阻层(80)进行图形化处理，去除所述光阻层(80)上对应于非图案区(72)的部分，使所述光阻层(80)上对应于源漏极间隔区(713)的部分的厚度减薄；
采用含氟蚀刻液对所述源漏极材料层(70)的非图案区(72)进行蚀刻去除；
对剩余的光阻层(80)进行灰化处理，去除所述光阻层(80)上对应于源漏极间隔区(713)的部分，使所述光阻层(80)上对应于所述源极预定图案区(711)与漏极预定图案区(712)的部分的厚度减薄；
采用无氟蚀刻液对所述源漏极材料层(70)的源漏极间隔区(713)进行蚀刻去除；所述无氟蚀刻液对IGZO的蚀刻速度小于所述含氟蚀刻液对IGZO的蚀刻速度；
剥离剩余的光阻层(80)，得到间隔设置的源极(51)与漏极(52)；
在所述源极(51)、漏极(52)、有源层(40)及栅极绝缘层(30)上形成钝化层(60)。
2.如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其特征在于，所述导体化IGZO膜层的制备方法为磁控溅射，磁控溅射过程中，反应腔体内不添加氧气，得到的导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
3.如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其特征在于，所述栅极(20)包括设于所述衬底基板(10)上的第一栅极层(21)与设于所述第一栅极层(21)上的第二栅极层(22)，所述第一栅极层(21)的材料包括钼，所述第二栅极层(22)的材料包括铜。
4.如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其特征在于，所述有源层(40)的材料包括铟镓锌氧化物。
5.如权利要求1所述的背沟道蚀刻型TFT基板的制作方法，其特征在于，所述钝化层(60)的材料包括氧化硅。
6.一种背沟道蚀刻型TFT基板，其特征在于，包括：衬底基板(10)、设于所述衬底基板(10)上的栅极(20)、设于所述衬底基板(10)及栅极(20)上的栅极绝缘层(30)、设于所述栅极绝缘层(30)上的有源层(40)、设于所述有源层(40)上且间隔设置的源极(51)与漏极(52)以及设于所述源极(51)、漏极(52)、有源层(40)及栅极绝缘层(30)上的钝化层(60)；
所述源极(51)与漏极(52)由源漏极材料层(70)图案化形成，所述源漏极材料层(70)包括设于所述有源层(40)上的第一源漏极材料层(41)、设于所述第一源漏极材料层(41)上的第二源漏极材料层(42)以及设于所述第二源漏极材料层(42)上的第三源漏极材料层(43)，所述第一源漏极材料层(41)的材料包括钼，所述第二源漏极材料层(42)的材料包括铜，所述第三源漏极材料层(43)为导体化IGZO膜层。
7.如权利要求6所述的背沟道蚀刻型TFT基板，其特征在于，所述导体化IGZO膜层中铟镓锌氧的摩尔比为In：Ga：Zn：O＝1：1：1：X，其中X小于4。
8.如权利要求6所述的背沟道蚀刻型TFT基板，其特征在于，所述栅极(20)包括设于所述衬底基板(10)上的第一栅极层(21)与设于所述第一栅极层(21)上的第二栅极层(22)，所述第一栅极层(21)的材料包括钼，所述第二栅极层(22)的材料包括铜。
9.如权利要求6所述的背沟道蚀刻型TFT基板，其特征在于，所述有源层(40)的材料包括铟镓锌氧化物。
10.如权利要求6所述的背沟道蚀刻型TFT基板，其特征在于，所述钝化层(60)的材料包括氧化硅。
CN201711167386.5A 2017-11-21 2017-11-21 背沟道蚀刻型tft基板及其制作方法 Pending CN107768307A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201711167386.5A CN107768307A (zh) 2017-11-21 2017-11-21 背沟道蚀刻型tft基板及其制作方法
US15/749,105 US10355035B2 (en) 2017-11-21 2017-12-20 Manufacturing method of back-channel-etched (BCE) thin film transistor (TFT) substrate
PCT/CN2017/117327 WO2019100492A1 (zh) 2017-11-21 2017-12-20 背沟道蚀刻型tft基板及其制作方法
US16/460,973 US10714514B2 (en) 2017-11-21 2019-07-02 Back-channel-etched TFT substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711167386.5A CN107768307A (zh) 2017-11-21 2017-11-21 背沟道蚀刻型tft基板及其制作方法

Publications (1)

Publication Number Publication Date
CN107768307A true CN107768307A (zh) 2018-03-06

Family

ID=61278613

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711167386.5A Pending CN107768307A (zh) 2017-11-21 2017-11-21 背沟道蚀刻型tft基板及其制作方法

Country Status (3)

Country Link
US (2) US10355035B2 (zh)
CN (1) CN107768307A (zh)
WO (1) WO2019100492A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020224013A1 (zh) * 2019-05-09 2020-11-12 深圳市华星光电技术有限公司 一种薄膜电晶体及其制作方法
CN113764282A (zh) * 2021-09-03 2021-12-07 深圳市华星光电半导体显示技术有限公司 一种背沟道蚀刻型的薄膜电晶体及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766891A (zh) * 2015-03-18 2015-07-08 华南理工大学 一种薄膜晶体管的源漏电极及制备方法、薄膜晶体管及制备方法
CN105140131A (zh) * 2015-07-15 2015-12-09 京东方科技集团股份有限公司 氧化物薄膜晶体管的制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4238956B2 (ja) 2000-01-12 2009-03-18 エルジー ディスプレイ カンパニー リミテッド 銅配線基板及びその製造方法並びに液晶表示装置
KR100412619B1 (ko) * 2001-12-27 2003-12-31 엘지.필립스 엘시디 주식회사 액정표시장치용 어레이 기판의 제조 방법
US7682882B2 (en) * 2007-06-20 2010-03-23 Samsung Electronics Co., Ltd. Method of manufacturing ZnO-based thin film transistor
KR20160063402A (ko) * 2008-09-12 2016-06-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 디스플레이 장치
KR101722913B1 (ko) * 2008-09-12 2017-04-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
US8492756B2 (en) * 2009-01-23 2013-07-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR101593443B1 (ko) * 2009-02-19 2016-02-12 엘지디스플레이 주식회사 어레이 기판의 제조방법
CN103489902B (zh) * 2013-09-30 2016-01-06 京东方科技集团股份有限公司 一种电极及其制作方法、阵列基板及显示装置
CN103715272A (zh) * 2014-01-16 2014-04-09 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法
CN104867959B (zh) * 2015-04-14 2017-09-26 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766891A (zh) * 2015-03-18 2015-07-08 华南理工大学 一种薄膜晶体管的源漏电极及制备方法、薄膜晶体管及制备方法
CN105140131A (zh) * 2015-07-15 2015-12-09 京东方科技集团股份有限公司 氧化物薄膜晶体管的制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020224013A1 (zh) * 2019-05-09 2020-11-12 深圳市华星光电技术有限公司 一种薄膜电晶体及其制作方法
CN113764282A (zh) * 2021-09-03 2021-12-07 深圳市华星光电半导体显示技术有限公司 一种背沟道蚀刻型的薄膜电晶体及其制作方法
CN113764282B (zh) * 2021-09-03 2023-09-05 深圳市华星光电半导体显示技术有限公司 一种背沟道蚀刻型的薄膜电晶体及其制作方法

Also Published As

Publication number Publication date
US20190326337A1 (en) 2019-10-24
US10714514B2 (en) 2020-07-14
US20190157318A1 (en) 2019-05-23
US10355035B2 (en) 2019-07-16
WO2019100492A1 (zh) 2019-05-31

Similar Documents

Publication Publication Date Title
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
CN107978560B (zh) 背沟道蚀刻型tft基板及其制作方法
CN103715228B (zh) 阵列基板及其制造方法、显示装置
CN107978607B (zh) 背沟道蚀刻型氧化物半导体tft基板的制作方法
CN103745955B (zh) 显示装置、阵列基板及其制造方法
CN107611085A (zh) Oled背板的制作方法
US10784287B2 (en) TFT substrate and manufacturing method thereof
US9142653B2 (en) Method for manufacturing thin-film transistor array substrate
CN103745954B (zh) 显示装置、阵列基板及其制造方法
CN104022079A (zh) 薄膜晶体管基板的制造方法
CN106449658A (zh) Tft基板及其制作方法
US10134765B2 (en) Oxide semiconductor TFT array substrate and method for manufacturing the same
WO2016026178A1 (zh) 氧化物半导体tft基板的制作方法及其结构
CN107768307A (zh) 背沟道蚀刻型tft基板及其制作方法
CN103022083A (zh) 一种阵列基板、显示装置及阵列基板的制备方法
WO2016026177A1 (zh) Tft基板的制作方法及其结构
CN107808885B (zh) 背沟道蚀刻型氧化物半导体tft基板及其制作方法
CN107968095A (zh) 背沟道蚀刻型tft基板及其制作方法
CN107919365B (zh) 背沟道蚀刻型tft基板及其制作方法
US20160260746A1 (en) Manufacture method of tft substrate and sturcture thereof
CN203312296U (zh) 一种阵列基板及显示装置
CN109873001A (zh) 阵列基板及其制作方法
CN112909028A (zh) 一种显示装置及其制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20180306

RJ01 Rejection of invention patent application after publication