WO2022083429A1 - 一种薄膜晶体管及其制作方法、驱动基板和电子设备 - Google Patents

一种薄膜晶体管及其制作方法、驱动基板和电子设备 Download PDF

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WO2022083429A1
WO2022083429A1 PCT/CN2021/121233 CN2021121233W WO2022083429A1 WO 2022083429 A1 WO2022083429 A1 WO 2022083429A1 CN 2021121233 W CN2021121233 W CN 2021121233W WO 2022083429 A1 WO2022083429 A1 WO 2022083429A1
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layer
contact electrode
electrode
film transistor
thin film
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PCT/CN2021/121233
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English (en)
French (fr)
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安亚斌
张帅
贺海明
刘洋
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present application relates to the technical field of semiconductor devices, and in particular, to a thin film transistor and a manufacturing method thereof, a driving substrate and an electronic device.
  • thin film transistors are the main electronic devices in driving substrates for driving displays.
  • the technology of thin film transistor mainly includes low temperature polysilicon, metal oxide, single crystal silicon and other semiconductor processes.
  • the electron mobility of the thin film transistor containing low temperature polysilicon is better than the other two, and the off-state leakage current of the transistor containing metal oxide is smaller than the other two.
  • Thin film transistors containing low temperature polysilicon and thin film transistors containing metal oxides have become the two main types of transistors currently used in driving substrates.
  • the thin film transistors in the driving substrate may be exposed to light, which may cause electrical deterioration of the transistors, thereby affecting the operation of the driving substrate.
  • the present application provides a thin film transistor and a method for fabricating the same, a driving substrate and an electronic device to solve the technical problem of electrical deterioration of the thin film transistor after being exposed to light.
  • an embodiment of the present application provides a thin film transistor, comprising: a source contact electrode and a drain contact electrode, the material for making the source contact electrode and the drain contact electrode includes a first metal oxide; a semiconductor active layer, The semiconductor active layer is connected to the source contact electrode and the drain contact electrode, and the semiconductor active layer includes a channel region; the barrier layer covers at least the channel region; the gate insulating layer is located on the side of the barrier layer away from the active layer , and cover the barrier layer; the gate is located on the side of the gate insulating layer away from the barrier layer, and the projection of the gate on the semiconductor active layer overlaps with the channel region; the interlayer dielectric layer is located on the side of the gate away from the gate One side of the insulating layer; the source electrode and the drain electrode are located on the side of the interlayer dielectric layer away from the gate electrode, the source electrode is connected to the source contact electrode through the first via hole, and the drain electrode is connected to the drain electrode contact electrode through the second via hole connect.
  • the embodiments of the present application provide that the thin film transistor is provided with a barrier layer between the semiconductor active layer and the gate insulating layer, which can avoid electrical deterioration of the thin film transistor after being exposed to light.
  • the material for making the source contact electrode and the drain contact electrode includes a first metal oxide, and the etching and punching process when making the first via hole and the second via hole causes less damage to the source contact electrode and the drain contact electrode. Or basically no damage, so as to ensure that the contact resistance between the source and the source contact electrode is small, and the contact resistance between the drain and the drain contact electrode is small, and the connection conductivity between the source and the drain electrode is improved to ensure the thin film transistor. Stable performance.
  • the material for the source contact electrode and the drain contact electrode includes a first metal oxide, and the first metal oxide has a larger work function, so that the source contact region and the drain contact region will not generate photoelectrons after being illuminated , can avoid the generation of photo-generated leakage current, thereby further ensuring the performance stability of the thin film transistor.
  • the manufacturing material of the barrier layer includes the second metal oxide.
  • the second metal oxide includes alumina.
  • the blocking layer has a large work function, and will not be excited by light to generate electrons, so it can block the transmission of holes or defect ions generated by the semiconductor active layer by light.
  • the barrier layer is fabricated by an atomic layer deposition process.
  • the atomic layer deposition process can make the thickness of the barrier layer thinner, then when the first via hole and the second via hole of the insulating layer are subsequently fabricated, the etching process can etch away the barrier layer at the position of the via hole to remove the barrier layer.
  • the contact performance between the source electrode and the source contact electrode and the contact performance between the drain electrode and the drain contact electrode are satisfied.
  • the thickness of the barrier layer is d, where, In the atomic layer deposition process, the deposition time of each single atomic film is relatively long, and the thickness of the barrier layer is small, which can also reduce the time required for the barrier layer process.
  • the blocking layer includes a hollow area, and the gate insulating layer fills the hollow area.
  • the first metal oxide includes indium tin oxide or indium zinc oxide.
  • the work function of indium tin oxide is about 3.8 eV. Both indium tin oxide or indium zinc oxide have good electrical conductivity and large work function.
  • the insulating layer is etched to form via holes in the production of thin film transistors. The damage to the source-drain contact electrodes by the process is small, and the contact resistance between the source electrode and the source contact electrode and the contact resistance between the drain electrode and the drain contact electrode can be reduced. At the same time, photoelectrons can be prevented from being generated after the source contact region and the drain contact region are illuminated, thereby avoiding the generation of photo-generated leakage current.
  • the work function of the first metal oxide is greater than 3.1 eV
  • the work function of the blocking layer is greater than 3.1 eV.
  • the first via hole penetrates the gate insulating layer, the interlayer dielectric layer and the barrier layer, and exposes the source contact electrode; the second via hole penetrates the gate insulating layer, the interlayer dielectric layer and the barrier layer, and exposes the drain electrode Contact electrodes.
  • an embodiment of the present application also provides a method for fabricating a thin film transistor, the fabrication method includes: fabricating a source contact electrode and a drain contact electrode, and the fabrication materials of the source contact electrode and the drain contact electrode include a first metal oxide make a semiconductor active layer, the semiconductor active layer is connected to the source contact electrode and the drain contact electrode, and the semiconductor active layer includes a channel region; a barrier layer is fabricated on the semiconductor active layer; a gate is fabricated on the barrier layer A very insulating layer; a gate is made on the gate insulating layer, the semiconductor active layer includes a channel region, and the projection of the gate on the semiconductor active layer overlaps with the channel region; an interlayer dielectric layer is made on the gate ; Etch the gate insulating layer, the interlayer dielectric layer and the barrier layer to form a first via hole and a second via hole, the first via hole exposes the source contact electrode, and the second via hole exposes the drain contact electrode; A source electrode and a drain electrode are formed on the intermediate dielectric
  • forming the blocking layer on the active layer includes: using an atomic layer deposition process to form the blocking layer on the active layer.
  • the atomic layer deposition process can make the thickness of the barrier layer thinner, then when the first via hole and the second via hole of the insulating layer are subsequently fabricated, the etching process can etch away the barrier layer at the position of the via hole to remove the barrier layer.
  • the contact performance between the source electrode and the source contact electrode and the contact performance between the drain electrode and the drain contact electrode are satisfied.
  • an embodiment of the present application further provides a driving substrate, including the thin film transistor provided by any embodiment of the present application.
  • the embodiments of the present application further provide an electronic device, including the driving substrate provided by the embodiments of the present application.
  • a barrier layer is arranged between the semiconductor active layer and the gate insulating layer, and the barrier layer can prevent the semiconductor from having a semiconductor after the thin film transistor receives light.
  • the photogenerated carriers and photogenerated defect ions generated by the source layer move toward the gate insulating layer and recombine, so as to avoid electrical deterioration of the thin film transistor after being exposed to light.
  • the source is connected to the source contact electrode through the first via hole, the source electrode is connected to the semiconductor active layer through the source contact electrode, the drain electrode is connected to the drain contact electrode through the second via hole, and the drain electrode is connected to the drain contact electrode through the drain contact electrode.
  • the semiconductor active layer is connected.
  • the material for making the source contact electrode and the drain contact electrode includes a first metal oxide, and the etching and punching process when making the first via hole and the second via hole causes less damage to the source contact electrode and the drain contact electrode. Or basically no damage, so as to ensure that the contact resistance between the source and the source contact electrode is small, and the contact resistance between the drain and the drain contact electrode is small, and the connection conductivity between the source and the drain electrode is improved to ensure the thin film transistor. Stable performance.
  • the material for the source contact electrode and the drain contact electrode includes a first metal oxide, and the first metal oxide has a larger work function, so that the source contact region and the drain contact region will not generate photoelectrons after being illuminated , can avoid the generation of photo-generated leakage current, thereby further ensuring the performance stability of the thin film transistor.
  • FIG. 1 is a schematic structural diagram of a thin film transistor in the related art
  • FIG. 2 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of another optional implementation manner of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 4 is a schematic top view of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 5 is another schematic top view of a thin film transistor provided by an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an application of the thin film transistor provided by the embodiment of the present application.
  • FIG. 7 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present application.
  • Organic self-luminous display technology has become the current mainstream display technology due to its advantages of self-luminescence, low power consumption, high brightness, and thinning.
  • ambient light can penetrate part of the film layer of the organic light-emitting display panel and irradiate on the thin film transistor in the driving substrate, or the light can penetrate the display panel and reflect on the back mechanism (such as the back case) of the electronic device and then irradiate On the thin film transistor in the driving substrate, ambient light will also irradiate on the thin film transistor when the transparent display device is applied.
  • the material of the active layer of the thin film transistor has a certain sensitivity to light. After the thin film transistor receives light, it will cause electrical deterioration due to light absorption, which will affect the normal operation of the circuit in the driving substrate and affect the product performance stability. .
  • FIG. 1 is a schematic diagram of the structure of a thin film transistor in the related art.
  • the semiconductor active layer 20 includes a source contact region 21, a drain contact region 22 and a channel region 23 , the gate electrode 30 overlaps the channel region 23 .
  • the source electrode 41 is connected to the source contact region 21 through the via hole (not shown) of the gate insulating layer 60 and the interlayer dielectric layer 70
  • the drain electrode 42 is connected to the source contact region 21 through the via hole (not shown) of the gate insulating layer 60 and the interlayer dielectric layer 70.
  • the semiconductor active layer 20 releases photoelectrons due to the illumination, and at the same time, holes or defect ions are generated, and the holes or defect ions will diffuse to the interface between the semiconductor active layer 20 and the gate insulating layer 60, Then, irreversible electrical damage occurs after being trapped by the defects at the interface.
  • an embodiment of the present application provides a thin film transistor, which solves the technical problem of electrical deterioration of the thin film transistor after being exposed to light by improving the structure of the thin film transistor.
  • FIG. 2 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present application.
  • a thin film transistor 00 includes: a source contact electrode 11 , a drain contact electrode 12 , a semiconductor active layer 20 , a gate electrode 30 , a source electrode 41 and drain 42, wherein, the semiconductor active layer 20 is connected to the source contact electrode 11 and the drain contact electrode 12, and the fabrication material of the semiconductor active layer 20 includes a low temperature polysilicon semiconductor or a metal oxide semiconductor, wherein the metal oxide semiconductor A typical one is indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the semiconductor active layer 20 includes a channel region (not shown in the figure), and in the thin film transistor device, the region of the semiconductor active layer 20 overlapping with the gate electrode 30 is the channel region.
  • the source electrode 41 is connected to the semiconductor active layer 20 through the source contact electrode 11
  • the drain electrode 42 is connected to the semiconductor active layer 20 through the drain contact electrode 12 .
  • the figure also shows a substrate 01 on which thin film transistors 00 are formed. Applied in the driving substrate structure, the substrate 01 may be a rigid substrate or a flexible substrate.
  • the material for making the source contact electrode 11 and the drain contact electrode 12 includes a first metal oxide; wherein, the first metal oxide has electrical conductivity.
  • the conductivity of the first metal oxide is greater than that of the semiconductor active layer.
  • the thin film transistor 00 further includes a barrier layer 50 and a gate insulating layer 60.
  • the barrier layer 50 is formed on the semiconductor active layer 20 and covers at least the channel region.
  • the gate insulating layer 60 is located on the side of the barrier layer 50 away from the semiconductor active layer, and covers the barrier layer 50 .
  • the fabrication material of the gate insulating layer 60 includes silicon oxide.
  • the blocking layer 50 is used to prevent photogenerated carriers and photogenerated defect ions generated by the semiconductor active layer 20 from moving and recombining in the direction of the gate insulating layer 60 after the thin film transistor 00 receives light, causing irreversible damage to the thin film transistor.
  • the photogenerated carriers are generally electrons
  • the photogenerated defects are mainly holes, O-ions, H ions, and the like.
  • the fabrication material of the semiconductor active layer in the thin film transistor provided by the embodiment of the present application includes low temperature polysilicon material, and the semiconductor active layer of the thin film transistor will generate free electrons and H ions when exposed to light. .
  • the H ions moving toward the gate insulating layer will be blocked by the blocking layer, and the H ions will not recombine with the interface of the gate insulating layer.
  • the voltage signal of the gate is reset, the H ions will combine with the free electrons, so that the semiconductor active layer returns to the initial state, thereby preventing the channel performance of the thin film transistor from changing.
  • the fabrication material of the semiconductor active layer in the thin film transistor provided by the embodiment of the present application includes an oxide semiconductor material, and the semiconductor active layer will generate free electrons and holes when exposed to light.
  • the holes migrating toward the gate insulating layer will be blocked by the blocking layer, so as to prevent the holes from neutralizing with O negative ions at the interface.
  • the voltage signal of the gate is reset, the holes will combine with free electrons, so that the semiconductor active layer returns to the initial state, thereby preventing the channel performance of the thin film transistor from changing.
  • the gate electrode 30 is located on the side of the gate insulating layer 60 away from the barrier layer 50 , and the projection of the gate electrode 30 on the semiconductor active layer 20 overlaps with the channel region.
  • the interlayer dielectric layer 70 is located on the side of the gate electrode 30 away from the gate insulating layer 60 ; the source electrode 41 and the drain electrode 42 are located on the side of the interlayer dielectric layer 70 away from the gate electrode 30 .
  • the fabrication materials of the interlayer dielectric layer 70 include silicon oxide and silicon nitride.
  • the first via hole 81 penetrates the gate insulating layer 60, the interlayer dielectric layer 70 and the barrier layer 50, and exposes the source contact electrode 11;
  • the second via hole 82 penetrates the gate insulating layer 60, the interlayer The dielectric layer 70 and the barrier layer 50 are exposed, and the drain contact electrode 12 is exposed.
  • the source electrode 41 is connected to the source contact electrode 11 through the first via hole 81
  • the drain electrode 42 is connected to the drain contact electrode 12 through the second via hole 82 .
  • the barrier layer may be etched away together in the punching process of the gate insulating layer and the interlayer dielectric layer to form the first via hole and the second via hole.
  • a barrier layer is arranged between the semiconductor active layer and the gate insulating layer, and the barrier layer can block photogenerated carriers and photogenerated defects generated by the semiconductor active layer after the thin film transistor receives light from the light.
  • the ions move and recombine in the direction of the gate insulating layer, so as to avoid electrical deterioration of the thin film transistor after being exposed to light.
  • the material for making the blocking layer has a large work function, thereby ensuring that the blocking layer is not easily excited by light to generate photoelectrons, and thus can block the migration of holes or defect ions generated by the semiconductor active layer by light.
  • the source and drain are respectively connected to the semiconductor active layer through via holes, and the semiconductor active layer is exposed through the via holes penetrating the gate insulating layer and the interlayer insulating layer.
  • the punching process will cause damage to the semiconductor active layer, resulting in source-drain and semiconductor
  • the contact resistance of the active layer increases.
  • the source electrode is connected to the source contact electrode through the first via hole, the source electrode is connected to the semiconductor active layer through the source electrode contact electrode, the drain electrode is connected to the drain contact electrode through the second via hole, and the drain electrode is connected to the drain contact electrode through the drain electrode.
  • the electrode is connected to the semiconductor active layer.
  • the material for making the source contact electrode and the drain contact electrode includes a first metal oxide, and the etching and punching process when making the first via hole and the second via hole causes less damage to the source contact electrode and the drain contact electrode. Or basically no damage, so as to ensure that the contact resistance between the source and the source contact electrode is small, and the contact resistance between the drain and the drain contact electrode is small, and the connection conductivity between the source and the drain electrode is improved to ensure the thin film transistor. Stable performance.
  • the semiconductor active layer includes a source contact region and a drain contact region, and both the source contact region and the drain contact region have certain sensitivity to light.
  • the semiconductor active layer includes a source contact region and a drain contact region, and both the source contact region and the drain contact region have certain sensitivity to light.
  • there is a voltage difference between the source and the drain and after the source contact area and the drain contact area are illuminated, a photocurrent will be generated between the source and the drain, which will affect the performance of the thin film transistor, such as in the When the thin film transistor is used as a switch tube, the thin film transistor may be turned on in advance, or the off-state leakage current may be too large to affect the node potential in the circuit.
  • the material for making the source contact electrode and the drain contact electrode includes a first metal oxide, and the first metal oxide has a larger work function, so the source contact region and the drain contact region will not be exposed to light after being exposed to light.
  • photoelectrons photo-generated leakage current can be avoided, thereby further ensuring the performance stability of the thin film transistor.
  • the work function of the first metal oxide is greater than 3.1 eV.
  • the light that can be irradiated on the thin film transistor is ambient light, or the light generated by the light emitting device in the display panel itself is emitted and then irradiated on the thin film transistor. That is, the light irradiated on the thin film transistor is visible light.
  • the wavelength range of visible light is 400 nm to 700 nm.
  • E electron energy
  • f frequency
  • c the speed of light, 3*10 17 nm/s
  • k is a constant, 1.6*10 -19 J/eV
  • the work function of the first metal oxide is set to be greater than 3.1 eV, which can ensure that the source contact region and the drain contact region will not be excited to generate photoelectrons after being illuminated.
  • the first metal oxide includes indium tin oxide or indium zinc oxide.
  • the work function of indium tin oxide is about 3.8eV. Both indium tin oxide or indium zinc oxide have good electrical conductivity and large work function. If indium tin oxide or indium zinc oxide is used to make source and drain contact electrodes, the insulating layer is etched to form via holes in the production of thin film transistors.
  • the damage to the source-drain contact electrodes by the process is small, and the contact resistance between the source electrode and the source contact electrode and the contact resistance between the drain electrode and the drain contact electrode can be reduced.
  • photoelectrons can be prevented from being generated after the source contact region and the drain contact region are illuminated, thereby avoiding the generation of photo-generated leakage current.
  • a material for fabricating the barrier layer includes a second metal oxide, and the work function of the second metal oxide is greater than 3.1 eV.
  • the second metal oxide is an insulating material with a high dielectric constant, and the second metal oxide is substantially non-conductive.
  • the second metal oxide can include aluminum oxide, the work function of aluminum oxide is about 8.4 eV, aluminum oxide will not be excited by light to generate electrons, and can block holes or defect ions generated by light in the semiconductor active layer. transfer.
  • the barrier layer 50 is fabricated by an atomic layer deposition process.
  • an atomic layer deposition process is used to fabricate aluminum oxide as the barrier layer.
  • the entire barrier layer 50 is fabricated by an atomic layer deposition process after the process of the semiconductor active layer 20 , that is to say, the barrier layer 50 will also be formed above the corresponding source contact electrodes 11 and drain contact electrodes 12 . .
  • the atomic layer deposition process can make the thickness of the barrier layer 50 thinner, when the first via hole and the second via hole of the insulating layer (gate insulating layer and interlayer insulating layer) are subsequently fabricated, the etching process
  • the barrier layer at the position of the via hole can be etched away to satisfy the contact performance between the source electrode and the source electrode contact electrode and the contact performance between the drain electrode and the drain electrode contact electrode.
  • the thickness of the barrier layer 50 is d, wherein, The barrier layer is fabricated by an atomic layer deposition process, and the thickness of the barrier layer is about 1-10 atoms thick.
  • the man-hour for the deposition of each single atomic film in the atomic layer deposition process is long, and the thickness of the barrier layer is small, which can also reduce the time-consuming of the barrier layer process.
  • FIG. 3 is a schematic diagram of another optional implementation manner of the thin film transistor provided by the embodiment of the present invention.
  • the barrier layer 50 of the thin film transistor includes a hollow region 51 , and the gate insulating layer 60 fills the hollow region 51 .
  • the barrier layer 50 is fabricated by an atomic layer deposition process.
  • the barrier layer fabrication material is formed layer by layer in the form of a single atomic film on the semiconductor active layer 50 to form a thinner barrier layer. 50. Since the deposition thickness of the barrier layer fabrication material is relatively thin, the fabricated barrier layer has a plurality of hollow regions.
  • the gate insulating layer 60 is formed on the barrier layer 50 , the hollow region 51 is filled with the gate insulating layer 60 .
  • the blocking layer 50 has a certain thickness, which can block the migration of photo-generated carriers, holes or defect ions generated by the semiconductor active layer by light to the gate insulating layer, so as to prevent holes or defect ions from being in the gate insulating layer.
  • the interface of the layers recombines.
  • the barrier layer above the semiconductor active layer mainly plays a role, and the barrier layer above the contact electrodes (source contact electrode and drain contact electrode) may affect the contact connection between the source and drain electrodes and the contact electrode.
  • the etching and punching process can easily etch the thinner barrier layer to ensure the source and drain electrodes are connected to the contact electrodes.
  • the contact connection between the electrodes reduces the contact resistance between the source and drain electrodes and the contact electrodes.
  • FIG. 4 is a schematic top view of a thin film transistor provided by an embodiment of the present invention.
  • the figure schematically shows the semiconductor active layer of the thin film transistor viewed from the gate side of the thin film transistor.
  • the barrier layer 50 includes a plurality of barrier portions 52 , and the plurality of barrier portions 52 are dispersedly arranged.
  • the barrier layer 50 is in the shape of an island, and the area between the adjacent barrier portions 52 is the hollow area 51 .
  • the material of the barrier layer is formed layer by layer in the form of a single atomic film on the semiconductor active layer.
  • the thin film transistor structure provided in the embodiment of FIG. 4, it is a barrier layer obtained by depositing a small number of single-atom films.
  • the barrier layer can block the holes or defect ions generated by the semiconductor active layer from being illuminated to the gate.
  • the migration of the insulating layer prevents the recombination of holes or defect ions at the interface of the gate insulating layer.
  • the thickness of the barrier layer is thin, and it is easy to be etched away during the insulating layer opening process.
  • island-shaped blocking portion 52 in FIG. 4 is only shown as a circle, which is only for illustrating the shape of the blocking layer in the embodiment of the present application.
  • the present application does not make any limitation on the specific shape of the island-shaped blocking portion.
  • FIG. 5 is another schematic top view of the thin film transistor provided by an embodiment of the present invention.
  • the barrier layer 50 includes a plurality of hollow regions 51 , and the barrier layer 50 is like a mesh.
  • the number of single-atom films deposited in the atomic layer deposition process in this embodiment is slightly larger, but the barrier layer still does not form a dense film layer on the entire surface, indicating that the thickness of the barrier layer 50 is still relatively thin.
  • the blocking layer 50 can block the migration of holes or defect ions generated in the semiconductor active layer by light to the gate insulating layer, and can be easily etched away in the insulating layer opening process.
  • the length of the hollow region 51 is greater than 1.5 ⁇ m.
  • the hollow area 51 in FIG. 5 is only shown as a circle, which is only for illustrating the appearance of the barrier layer in the embodiment of the present application.
  • the present application does not make any limitation on the specific shape of the hollow area.
  • FIG. 6 is a schematic diagram of an application of the thin film transistor provided by the embodiment of the present application.
  • the display panel includes a driving substrate 1 and a display layer 2 located on the driving substrate 1 .
  • the driving substrate 1 includes the thin film transistor 00 provided in the embodiment of the present application
  • the display layer 2 includes a light-emitting device 3
  • the light-emitting device 3 includes an anode a, a light-emitting layer b and a cathode c
  • the light-emitting layer b includes an organic light-emitting material.
  • the drain 42 of the thin film transistor 00 is connected to the anode a of the light emitting device 3 through a via hole.
  • the thin film transistor 00 is a transistor in a pixel circuit.
  • the driving substrate further includes a driving circuit
  • the driving circuit includes a plurality of thin film transistors
  • the thin film transistors in the driving circuit may adopt the structure of the thin film transistor provided in the embodiment of the present application.
  • FIG. 7 is a flowchart of the method for manufacturing a thin film transistor provided by an embodiment of the present application. As shown in FIG. 7 , the manufacturing method includes:
  • Step S101 Fabricate the source contact electrode 11 and the drain contact electrode 12, and the fabrication material of the source contact electrode 11 and the drain contact electrode 12 includes a first metal oxide; specifically, fabricate the source contact electrode on the substrate 01 and the drain contact electrode.
  • Step S102 fabricating a semiconductor active layer 20, the semiconductor active layer 20 is connected to the source contact electrode 11 and the drain contact electrode 12, and the semiconductor active layer 20 includes a channel region (not marked in the figure);
  • Step S103 forming the barrier layer 50 on the semiconductor active layer 20 .
  • Step S104 forming the gate insulating layer 60 on the barrier layer 50 ;
  • Step S105 forming a gate electrode 30 on the gate insulating layer 60 , and the projection of the gate electrode 30 on the semiconductor active layer 20 overlaps with the channel region;
  • Step S106 forming an interlayer dielectric layer 70 on the gate electrode 30;
  • Step S107 The gate insulating layer 60, the interlayer dielectric layer 70 and the barrier layer 50 are etched to form a first via hole 81 and a second via hole 82.
  • the first via hole 81 exposes the source contact electrode 11, and the second via hole 81 exposes the source contact electrode 11.
  • the hole 2 exposes the drain contact electrode 12;
  • Step S108 forming the source electrode 41 and the drain electrode 42 on the interlayer dielectric layer 70 , the source electrode 41 is connected to the source contact electrode 11 through the first via hole 81 , and the drain electrode 42 is connected to the drain electrode through the second via hole 82 Electrodes 42 are connected.
  • the barrier layer 50 is formed on the semiconductor active layer 20 by using an atomic layer deposition process.
  • the atomic layer deposition process can make the thickness of the barrier layer 50 thinner, then when the first via hole and the second via hole of the insulating layer (gate insulating layer and interlayer insulating layer) are subsequently fabricated, the etching process can make the thickness of the barrier layer 50 thinner.
  • the barrier layer at the position of the via hole is etched away to satisfy the contact performance between the source electrode and the source contact electrode and the contact performance between the drain electrode and the drain contact electrode.
  • the embodiment of the present application further provides a driving substrate, which includes the thin film transistor provided by any embodiment of the present application.
  • the embodiments of the present application further provide electronic devices, including the driving substrates provided by the embodiments of the present application.
  • the electronic device can be, for example, a mobile phone, a tablet computer, a notebook computer, an electronic paper book, a TV, a smart wearable product, a transparent display product, or any other device with a display function.

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Abstract

本申请实施例提供一种薄膜晶体管及其制作方法、驱动基板和电子设备。薄膜晶体管包括：源极接触电极和漏极接触电极，源极接触电极和漏极接触电极的制作材料包括第一金属氧化物；半导体有源层连接源极接触电极和漏极接触电极，半导体有源层包括沟道区；阻挡层至少覆盖沟道区；栅极绝缘层位于阻挡层远离有源层的一侧，且覆盖阻挡层；栅极位于栅极绝缘层远离阻挡层的一侧，且栅极在半导体有源层的投影与沟道区交叠；层间介质层位于栅极的远离栅极绝缘层的一侧；源极和漏极位于层间介质层远离栅极的一侧，源极通过第一过孔与源极接触电极连接，漏极通过第二过孔与漏极接触电极连接。本申请能够降低薄膜晶体管受光照后产生电性劣化的风险。

Description

一种薄膜晶体管及其制作方法、驱动基板和电子设备
本申请要求于2020年10月19日提交中国专利局、申请号为202011120951.4、申请名称为“一种薄膜晶体管及其制作方法、驱动基板和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，特别涉及一种薄膜晶体管及其制作方法、驱动基板和电子设备。
背景技术
目前显示技术领域，薄膜晶体管为驱动显示的驱动基板中主要的电子器件。其中，薄膜晶体管的技术主要包括低温多晶硅、金属氧化物、单晶硅等半导体工艺。其中，包含低温多晶硅的薄膜晶体管的电子迁移率优于其他两种，包含金属氧化物的晶体管的关态漏流小于其他两种。包含低温多晶硅的薄膜晶体管和包含金属氧化物的薄膜晶体管成为目前驱动基板中主要采用的两种晶体管。在实际应用中，驱动基板中的薄膜晶体管可能会受到光照，而导致晶体管的电性发生劣化，进而影响驱动基板的工作。
发明内容
有鉴于此，本申请提供一种薄膜晶体管及其制作方法、驱动基板和电子设备，以解决薄膜晶体管受光照后电性发生劣化的技术问题。
第一方面，本申请实施例提供一种薄膜晶体管，包括：源极接触电极和漏极接触电极，源极接触电极和漏极接触电极的制作材料包括第一金属氧化物；半导体有源层，半导体有源层连接源极接触电极和漏极接触电极，半导体有源层包括沟道区；阻挡层，阻挡层至少覆盖沟道区；栅极绝缘层，位于阻挡层远离有源层的一侧，且覆盖阻挡层；栅极，位于栅极绝缘层远离阻挡层的一侧，且栅极在半导体有源层的投影与沟道区交叠；层间介质层，位于栅极的远离栅极绝缘层的一侧；源极和漏极，位于层间介质层远离栅极的一侧，源极通过第一过孔与源极接触电极连接，漏极通过第二过孔与漏极接触电极连接。
本申请实施例提供薄膜晶体管在半导体有源层和栅极绝缘层之间设置阻挡层，能够避免薄膜晶体管受光照后电性发生劣化。源极接触电极和漏极接触电极的制作材料包括第一金属氧化物，制作第一过孔和第二过孔时的刻蚀打孔工艺对源极接触电极和漏极接触电极的损伤较小或者基本没有损伤，从而能够保证源极与源极接触电极的接触电阻较小、以及漏极与漏极接触电极的接触电阻较小，提升源漏极与接触电极的连接导电率，保证薄膜晶体管性能稳定。另外，源极接触电极和漏极接触电极的制作材料包括第一金属氧化物，第一金属氧化物具有较大的功函数，则源极接触区和漏极接 触区受光照之后不会产生光电子，能够避免产生光生漏电流，从而进一步确保薄膜晶体管性能稳定性。
具体的，阻挡层的制作材料包括第二金属氧化物。典型的，第二金属氧化物包括氧化铝。阻挡层具有较大的功函数，不会被光激发产生电子，则能够阻挡半导体有源层受光照产生的空穴或者缺陷离子的传递。
具体的，阻挡层采用原子层沉积工艺制作。原子层沉积工艺能够将阻挡层的厚度制作的较薄，则在后续制作绝缘层的第一过孔和第二过孔时，刻蚀工艺能够将过孔位置处的阻挡层刻蚀掉，以满足源极与源极接触电极接触性能、以及漏极与漏极接触电极的接触性能。
具体的，阻挡层的厚度为d，其中，
Figure PCTCN2021121233-appb-000001
原子层沉积工艺的每层单原子膜沉积的工时较长，阻挡层的厚度较小也能够减小阻挡层工艺制程的用时。
具体的，阻挡层包括镂空区，栅极绝缘层填充镂空区。
具体的，第一金属氧化物包括氧化铟锡或者氧化铟锌。氧化铟锡的功函数大约为3.8eV。氧化铟锡或者氧化铟锌均具有良好的导电性能和较大的功函数，采用氧化铟锡或者氧化铟锌制作源漏极接触电极，则薄膜晶体管制作中对绝缘层进行刻蚀形成过孔的工艺对源漏极接触电极的损伤均较小，能够降低源极与源极接触电极的接触电阻以及漏极与漏极接触电极的接触电阻。同时，能够防止源极接触区和漏极接触区受光照之后产生光电子，从而避免产生光生漏电流。
进一步的，第一金属氧化物的功函数大于3.1eV，阻挡层的功函数大于3.1eV。
具体的，第一过孔贯穿栅极绝缘层、层间介质层和阻挡层，并暴露源极接触电极；第二过孔贯穿栅极绝缘层、层间介质层和阻挡层，并暴露漏极接触电极。
第二方面，本申请实施例还提供一种薄膜晶体管的制作方法，制作方法包括：制作源极接触电极和漏极接触电极，源极接触电极和漏极接触电极的制作材料包括第一金属氧化物；制作半导体有源层，半导体有源层连接源极接触电极和漏极接触电极，半导体有源层包括沟道区；在半导体有源层之上制作阻挡层；在阻挡层之上制作栅极绝缘层；在栅极绝缘层之上制作栅极，半导体有源层包括沟道区，栅极在半导体有源层的投影与沟道区交叠；在栅极之上制作层间介质层；对栅极绝缘层、层间介质层和阻挡层进行刻蚀形成第一过孔和第二过孔，第一过孔暴露源极接触电极，第二过孔暴露漏极接触电极；在层间介质层之上制作源极和漏极，源极通过第一过孔与源极接触电极连接，漏极通过第二过孔与漏极接触电极连接。
具体的，在有源层之上制作阻挡层，包括：采用原子层沉积工艺在有源层之上制作阻挡层。原子层沉积工艺能够将阻挡层的厚度制作的较薄，则在后续制作绝缘层的第一过孔和第二过孔时，刻蚀工艺能够将过孔位置处的阻挡层刻蚀掉，以满足源极与源极接触电极接触性能、以及漏极与漏极接触电极的接触性能。采用原子层沉积工艺制作阻挡层后不需要再对阻挡层做额外的处理工艺，工艺相对简单。
第三方面，本申请实施例还提供一种驱动基板，包括本申请任意实施例提供的薄膜晶体管。
第四方面，本申请实施例还提供一种电子设备，包括本申请实施例提供的驱动基板。
本申请提供的薄膜晶体管及其制作方法、驱动基板和电子设备，具有如下有益效果：在半导体有源层和栅极绝缘层之间设置阻挡层，阻挡层能够阻挡薄膜晶体管接收到光照后半导体有源层产生的光生载流子以及光生缺陷离子向栅极绝缘层的方向移动并复合，从而避免薄膜晶体管受光照后电性发生劣化。而且设置源极通过第一过孔连接源极接触电极，源极通过源极接触电极与半导体有源层连接，漏极通过第二过孔连接漏极接触电极，漏极通过漏极接触电极与半导体有源层连接。源极接触电极和漏极接触电极的制作材料包括第一金属氧化物，制作第一过孔和第二过孔时的刻蚀打孔工艺对源极接触电极和漏极接触电极的损伤较小或者基本没有损伤，从而能够保证源极与源极接触电极的接触电阻较小、以及漏极与漏极接触电极的接触电阻较小，提升源漏极与接触电极的连接导电率，保证薄膜晶体管性能稳定。另外，源极接触电极和漏极接触电极的制作材料包括第一金属氧化物，第一金属氧化物具有较大的功函数，则源极接触区和漏极接触区受光照之后不会产生光电子，能够避免产生光生漏电流，从而进一步确保薄膜晶体管性能稳定性。
附图说明
图1为相关技术中薄膜晶体管的结构示意图；
图2为本申请实施例提供的薄膜晶体管的结构示意图；
图3为本发明实施例提供的薄膜晶体管的另一种可选实施方式示意图；
图4为本发明实施例提供的薄膜晶体管的一种俯视示意图；
图5为本发明实施例提供的薄膜晶体管的另一种俯视示意图；
图6为本申请实施例提供的薄膜晶体管的一种应用示意图；
图7为本申请实施例提供的薄膜晶体管的制作方法流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。在本发明实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
有机自发光显示技术由于其自发光、低功耗、高亮度、薄型化等优点，成为目前主流显示技术。在应用中，环境光能够穿透有机发光显示面板的部分膜层照射到驱动基板中的薄膜晶体管上，或者光线穿透显示面板后在电子设备的背面机构(比如背壳)上发生反射后照射到驱动基板中的薄膜晶体管上，在透明显示装置应用时也会有环境光照射到薄膜晶体管上。而薄膜晶体管的有源层的制作材料对光具有一定的敏感性， 在薄膜晶体管接收到光照之后，会由于吸光而导致电性劣化，进而影响驱动基板中电路的正常工作，影响产品性能稳定性。
图1为相关技术中薄膜晶体管的结构示意图，如图1所示，在常规的薄膜晶体管000的结构中，在半导体有源层20包括源极接触区21、漏极接触区22和沟道区23，栅极30与沟道区23交叠。源极41通过栅极绝缘层60和层间介质层70的过孔(未标示)与源极接触区21连接，漏极42通过栅极绝缘层60和层间介质层70的过孔(未标示)与漏极接触区22连接。当薄膜晶体管000受光照后，半导体有源层20由于光照释放光电子，同时还会产生空穴或者缺陷离子，空穴或者缺陷离子会向半导体有源层20与栅极绝缘层60的界面扩散，然后被界面的缺陷捕获后产生不可逆的电性损伤。
基于此，本申请实施例提供一种薄膜晶体管，通过对薄膜晶体管的结构进行改进以解决薄膜晶体管受光照后电性发生劣化的技术问题。
图2为本申请实施例提供的薄膜晶体管的结构示意图，如图2所示，薄膜晶体管00包括：源极接触电极11、漏极接触电极12、半导体有源层20、栅极30、源极41和漏极42，其中，半导体有源层20连接源极接触电极11和漏极接触电极12，半导体有源层20的制作材料包括低温多晶硅半导体或者金属氧化物半导体，其中，金属氧化物半导体典型的为氧化铟镓锌(indium gallium zinc oxide，IGZO)。半导体有源层20包括沟道区(图中未标示)，在薄膜晶体管器件中，半导体有源层20中与栅极30交叠的区域为沟道区。源极41通过源极接触电极11与半导体有源层20连接，漏极42通过漏极接触电极12与半导体有源层20连接。图中还示出了衬底01，薄膜晶体管00形成在衬底01之上。应用在驱动基板结构中，衬底01可以为刚性衬底或者柔性衬底。
在本申请实施例提供的薄膜晶体管00中，源极接触电极11和漏极接触电极12的制作材料包括第一金属氧化物；其中，第一金属氧化物具有导电性能。第一金属氧化物的导电性能大于半导体有源层的导电性能。
薄膜晶体管00还包括阻挡层50和栅极绝缘层60，阻挡层50制作在半导体有源层20之上，且至少覆盖沟道区。栅极绝缘层60位于阻挡层50远离半导体有源层的一侧，且覆盖阻挡层50。具体的，栅极绝缘层60的制作材料包括氧化硅。
阻挡层50用于阻挡薄膜晶体管00接收到光照后半导体有源层20产生的光生载流子以及光生缺陷离子向栅极绝缘层60的方向移动并复合，对薄膜晶体管造成不可逆的损伤。其中，光生载流子一般为电子，光生缺陷主要为空穴、O-离子、H离子等。
具体的，在一种实施例中，本申请实施例提供的薄膜晶体管中半导体有源层的制作材料包括低温多晶硅材料，则薄膜晶体管的半导体有源层在受到光照时会产生自由电子和H离子。在应用中当对栅极施加电压信号之后，向栅极绝缘层方向移动的H离子会被阻挡层阻挡，H离子不会与栅极绝缘层界面复合。当栅极的电压信号重置以后，H离子又会与自由电子进行结合，使得半导体有源层恢复到初始状态，从而防止薄膜晶体管的沟道性能发生变化。
具体的，在另一种实施例中，本申请实施例提供的薄膜晶体管中半导体有源层的制作材料包括氧化物半导体材料，则半导体有源层在受到光照时会产生自由电子和空穴。在应用中当对栅极施加电压信号之后，向栅极绝缘层的方向迁移的空穴会被阻挡层阻挡，从而避免空穴在界面处与O负离子中和。当栅极的电压信号重置以后，空穴 又会与自由电子进行结合，使得半导体有源层恢复到初始状态，从而防止薄膜晶体管的沟道性能发生变化。
如图2所示，栅极30位于栅极绝缘层60远离阻挡层50的一侧，且栅极30在半导体有源层20的投影与沟道区交叠。层间介质层70位于栅极30的远离栅极绝缘层60的一侧；源极41和漏极42位于层间介质层70远离栅极30的一侧。具体的，层间介质层70的制作材料包括氧化硅和氮化硅。如图中示意的，第一过孔81贯穿栅极绝缘层60、层间介质层70和阻挡层50，并暴露源极接触电极11；第二过孔82贯穿栅极绝缘层60、层间介质层70和阻挡层50，并暴露漏极接触电极12。源极41通过第一过孔81与源极接触电极11连接，漏极42通过第二过孔82与漏极接触电极12连接。可选的，本申请实施例提供的薄膜晶体管在制作过程中，可以在栅极绝缘层和层间介质层的打孔工艺中一同将阻挡层刻蚀掉以形成第一过孔和第二过孔，对于薄膜晶体管的具体的制作方法，将在下述关于制作方法的实施例中进行说明。本申请实施例提供的薄膜晶体管结构中，在半导体有源层和栅极绝缘层之间设置阻挡层，阻挡层能够阻挡薄膜晶体管接收到光照后半导体有源层产生的光生载流子以及光生缺陷离子向栅极绝缘层的方向移动并复合，从而避免薄膜晶体管受光照后电性发生劣化。具体的，阻挡层的制作材料具有较大的功函数，从而保证阻挡层不易受光照激发产生光电子，进而能够阻挡半导体有源层受光照产生的空穴或者缺陷离子的迁移。
另外，在相关技术中，源漏极分别通过过孔与半导体有源层接触连接，则贯穿栅极绝缘层和层间绝缘层的过孔暴露半导体有源层。在薄膜晶体管制作工艺中，在对半导体有源层之上的栅极绝缘层和层间绝缘层进行刻蚀打孔时，打孔工艺会对半导体有源层造成损伤，导致源漏极与半导体有源层的接触电阻变大。而本申请中源极通过第一过孔连接源极接触电极，源极通过源极接触电极与半导体有源层连接，漏极通过第二过孔连接漏极接触电极，漏极通过漏极接触电极与半导体有源层连接。源极接触电极和漏极接触电极的制作材料包括第一金属氧化物，制作第一过孔和第二过孔时的刻蚀打孔工艺对源极接触电极和漏极接触电极的损伤较小或者基本没有损伤，从而能够保证源极与源极接触电极的接触电阻较小、以及漏极与漏极接触电极的接触电阻较小，提升源漏极与接触电极的连接导电率，保证薄膜晶体管性能稳定。
而且，在相关技术中，半导体有源层包括源极接触区和漏极接触区，源极接触区和漏极接触区均对光具有一定的敏感性。在应用中源极和漏极之间存在压差，则源极接触区和漏极接触区受光照后，在源极和漏极之间会产生光电流，而影响薄膜晶体管的性能，比如在薄膜晶体管作为开关管使用时，会导致薄膜晶体管提前开启，或者会导致关态漏流过大而影响电路中的节点电位等。本申请中，源极接触电极和漏极接触电极的制作材料包括第一金属氧化物，第一金属氧化物具有较大的功函数，则源极接触区和漏极接触区受光照之后不会产生光电子，能够避免产生光生漏电流，从而进一步确保薄膜晶体管性能稳定性。
具体的，第一金属氧化物的功函数大于3.1eV。在应用中，能够照射到薄膜晶体管上的光为环境光，或者显示面板中发光器件自身发生的光经发射后照射到薄膜晶体管上。也就是说照射到薄膜晶体管上的光为可见光。可见光的波长范围为400nm～700nm。
根据电子能量公式，E＝h*f，以及频率的公式，f＝c/(k*λ)。其中，E为能量、单位为eV；h为普朗克常数、6.63*10 -34J·s；f为频率、单位为Hz。c为光速、3*10 17nm/s；k为常数、1.6*10 -19J/eV；λ为波长、单位为nm。可得到，E＝1240/λ。则薄膜晶体管中半导体有源层吸收可见光后产生的光电子的能量范围为1.78～3.1eV。本申请实施例中设置第一金属氧化物的功函数大于3.1eV，能够确保源极接触区和漏极接触区受光照之后不会受激发产生光电子。具体的，第一金属氧化物包括氧化铟锡或者氧化铟锌。其中，氧化铟锡的功函数大约为3.8eV。氧化铟锡或者氧化铟锌均具有良好的导电性能和较大的功函数，采用氧化铟锡或者氧化铟锌制作源漏极接触电极，则薄膜晶体管制作中对绝缘层进行刻蚀形成过孔的工艺对源漏极接触电极的损伤均较小，能够降低源极与源极接触电极的接触电阻以及漏极与漏极接触电极的接触电阻。同时，能够防止源极接触区和漏极接触区受光照之后产生光电子，从而避免产生光生漏电流。
具体的，本申请实施例中阻挡层的制作材料包括第二金属氧化物，第二金属氧化物的功函数大于3.1eV。第二金属氧化物为高介电常数的绝缘材料，第二金属氧化物基本不导电。典型性的，第二金属氧化物可以包括氧化铝，氧化铝的功函数大约为8.4eV，氧化铝不会被光激发产生电子，能够阻挡半导体有源层受光照产生的空穴或者缺陷离子的传递。
具体的，本申请实施中阻挡层50采用原子层沉积工艺制作。可选的，采用原子层沉积工艺制作氧化铝作为阻挡层。在制作时，在半导体有源层20的工艺之后采用原子层沉积工艺制作整面的阻挡层50，也就是说在源极接触电极11和漏极接触电极12对应的上方也会形成阻挡层50。而由于原子层沉积工艺能够将阻挡层50的厚度制作的较薄，则在后续制作绝缘层(栅极绝缘层和层间绝缘层)的第一过孔和第二过孔时，刻蚀工艺能够将过孔位置处的阻挡层刻蚀掉，以满足源极与源极接触电极接触性能、以及漏极与漏极接触电极的接触性能。
可选的，阻挡层50的厚度为d，其中，
Figure PCTCN2021121233-appb-000002
采用原子层沉积工艺制作阻挡层，阻挡层的厚度大约为1～10个原子的厚度。另外，原子层沉积工艺的每层单原子膜沉积的工时较长，阻挡层的厚度较小也能够减小阻挡层工艺制程的用时。
图3为本发明实施例提供的薄膜晶体管的另一种可选实施方式示意图。如图3所示，薄膜晶体管的阻挡层50包括镂空区51，栅极绝缘层60填充镂空区51。具体的，阻挡层50采用原子层沉积工艺制作，在制作时将阻挡层的制作材料以单原子膜的形式一层一层形成在半导体有源层50之上，以形成厚度较薄的阻挡层50。由于阻挡层的制作材料的沉积厚度较薄，则制作的阻挡层具有多个镂空区。在阻挡层50之上制作栅极绝缘层60时，镂空区51被栅极绝缘层60填充。该实施方式中，阻挡层50具有一定厚度，能够阻挡半导体有源层受光照产生的光生载流子、空穴或者缺陷离子向栅极绝缘层的迁移，避免空穴或者缺陷离子在栅极绝缘层的界面发生复合。则主要是在半导体有源层上方的阻挡层起到作用，而接触电极(源极接触电极和漏极接触电极)对应上方的阻挡层可能会对源漏极与接触电极的接触连接造成影响，而本申请中由于阻挡层的厚度较薄，在制作源漏极与接触电极连接的过孔时，刻蚀打孔工艺容易将厚度较薄的阻挡层刻蚀掉，以保证源漏极与接触电极之间的接触连接，降低源漏极与接触电极之间的接触电阻。在薄膜晶体管制作时采用原子层沉积工艺制作厚度较薄的阻挡 层，无需增加阻挡层的图案化工艺，工艺简单。
具体的，在一种实施例中，图4为本发明实施例提供的薄膜晶体管的一种俯视示意图。图中示意由薄膜晶体管的栅极一侧看向薄膜晶体管的半导体有源层。如图4所示，阻挡层50包括多个阻挡部52，多个阻挡部52分散设置，阻挡层50为岛状，在相邻的阻挡部52之间的区域即为镂空区51。在采用原子层沉积工艺制作阻挡层时，将阻挡层的制作材料以单原子膜的形式一层一层形成在半导体有源层之上，沉积的单原子膜的数量较少时，单原子仅局部聚集，形成的阻挡层中会存在空隙(也即镂空区)，而并不能形成整面密实的膜层；随着沉积的单原子膜的数量的增加，后续沉积的原子膜会逐渐覆盖住之前膜层中的空隙；当沉积的单原子膜的数量足够多时，最终能够形成整面密实的膜层。图4实施例提供的薄膜晶体管结构中，为沉积数量较少的单原子膜得到的阻挡层，该实施方式中阻挡层能够阻挡半导体有源层受光照产生的空穴或者缺陷离子的向栅极绝缘层的迁移，避免空穴或者缺陷离子在栅极绝缘层的界面发生复合，同时阻挡层的厚度较薄，容易在绝缘层打开工艺中被刻蚀掉，采用原子层沉积工艺制作阻挡层后不需要再对阻挡层做额外的处理工艺。
需要说明的是图4中的岛状阻挡部52仅以圆形进行示意，仅为了说明本申请实施例中阻挡层的形貌。本申请对于岛状阻挡部的具体形状不做任何限定。
进一步的，图5为本发明实施例提供的薄膜晶体管的另一种俯视示意图。如图5所示，阻挡层50包括多个镂空区51，阻挡层50类似筛孔状。该实施例与图4实施例相比，在原子层沉积工艺中沉积的单原子膜的数量稍多，但是阻挡层仍然没有形成整面密实的膜层，说明阻挡层50的厚度仍然较薄，阻挡层50能够阻挡半导体有源层受光照产生的空穴或者缺陷离子向栅极绝缘层的迁移，同时容易在绝缘层打开工艺中被刻蚀掉。可选的，该实施方式中，镂空区51的长度大于1.5μm。
另外，需要说明的是图5中的镂空区51仅以圆形进行示意，仅为了说明本申请实施例中阻挡层的形貌。本申请对于镂空区的具体形状不做任何限定。
图6为本申请实施例提供的薄膜晶体管的一种应用示意图，如图6所示，示意出了一种显示面板的结构，显示面板包括驱动基板1、位于驱动基板1之上的显示层2，其中驱动基板1包括本申请实施例提供的薄膜晶体管00，显示层2包括发光器件3，发光器件3包括阳极a、发光层b和阴极c，可选的，发光层b包括有机发光材料。薄膜晶体管00的漏极42通过过孔与发光器件3的阳极a连接。图6实施例中示意薄膜晶体管00为像素电路中的晶体管。
在另一种实施例中，驱动基板中还包括驱动电路，驱动电路包括多个薄膜晶体管，驱动电路中的薄膜晶体管可以采用本申请实施例提供的薄膜晶体管的结构。
本申请实施例还提供一种薄膜晶体管的制作方法，图7为本申请实施例提供的薄膜晶体管的制作方法流程图，如图7所示，制作方法包括：
步骤S101：制作源极接触电极11和漏极接触电极12，源极接触电极11和漏极接触电极12的制作材料包括第一金属氧化物；具体的，在衬底01上制作源极接触电极和漏极接触电极。
步骤S102：制作半导体有源层20，半导体有源层20连接源极接触电极11和漏极接触电极12，半导体有源层20包括沟道区(图中未标示)；
步骤S103：在半导体有源层20之上制作阻挡层50。
步骤S104：在阻挡层50之上制作栅极绝缘层60；
步骤S105：在栅极绝缘层60之上制作栅极30，栅极30在半导体有源层20的投影与沟道区交叠；
步骤S106：在栅极30之上制作层间介质层70；
步骤S107：对栅极绝缘层60、层间介质层70和阻挡层50进行刻蚀形成第一过孔81和第二过孔82，第一过孔81暴露源极接触电极11，第二过孔2暴露漏极接触电极12；
步骤S108：在层间介质层70之上制作源极41和漏极42，源极41通过第一过孔81与源极接触电极11连接，漏极42通过第二过孔82与漏极接触电极42连接。
具体的，采用原子层沉积工艺在半导体有源层20之上制作阻挡层50。原子层沉积工艺能够将阻挡层50的厚度制作的较薄，则在后续制作绝缘层(栅极绝缘层和层间绝缘层)的第一过孔和第二过孔时，刻蚀工艺能够将过孔位置处的阻挡层刻蚀掉，以满足源极与源极接触电极接触性能、以及漏极与漏极接触电极的接触性能。采用原子层沉积工艺制作阻挡层后不需要再对阻挡层做额外的处理工艺，工艺相对简单。
本申请实施例还提供一种驱动基板，包括本申请任意实施例提供的薄膜晶体管。
本申请实施例还提供电子设备，包括本申请实施例提供的驱动基板。电子设备可以是例如手机、平板计算机、笔记本电脑、电纸书、电视机、智能穿戴产品、透明显示产品等任何具有显示功能的设备。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (13)

  1. 一种薄膜晶体管，其特征在于，包括：
    源极接触电极和漏极接触电极，所述源极接触电极和所述漏极接触电极的制作材料包括第一金属氧化物；
    半导体有源层，所述半导体有源层连接所述源极接触电极和所述漏极接触电极，所述半导体有源层包括沟道区；
    阻挡层，所述阻挡层至少覆盖所述沟道区；
    栅极绝缘层，位于所述阻挡层远离所述有源层的一侧，且覆盖所述阻挡层；
    栅极，位于所述栅极绝缘层远离所述阻挡层的一侧，且所述栅极在所述半导体有源层的投影与所述沟道区交叠；
    层间介质层，位于所述栅极的远离所述栅极绝缘层的一侧；
    源极和漏极，位于所述层间介质层远离所述栅极的一侧，所述源极通过第一过孔与所述源极接触电极连接，所述漏极通过第二过孔与所述漏极接触电极连接。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述阻挡层的制作材料包括第二金属氧化物。
  3. 根据权利要求2所述的薄膜晶体管，其特征在于，
    所述第二金属氧化物包括氧化铝。
  4. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述阻挡层采用原子层沉积工艺制作。
  5. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述阻挡层的厚度为d，其中，
    Figure PCTCN2021121233-appb-100001
  6. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述阻挡层包括镂空区，所述栅极绝缘层填充所述镂空区。
  7. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述第一金属氧化物包括氧化铟锡或者氧化铟锌。
  8. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述第一金属氧化物的功函数大于3.1eV，所述阻挡层的功函数大于3.1eV。
  9. 根据权利要求1所述的薄膜晶体管，其特征在于，
    所述第一过孔贯穿所述栅极绝缘层、所述层间介质层和所述阻挡层，并暴露所述源极接触电极；
    所述第二过孔贯穿所述栅极绝缘层、所述层间介质层和所述阻挡层，并暴露所述漏极接触电极。
  10. 一种薄膜晶体管的制作方法，其特征在于，所述制作方法包括：
    制作源极接触电极和漏极接触电极，所述源极接触电极和所述漏极接触电极的制作材料包括第一金属氧化物；
    制作半导体有源层，所述半导体有源层连接所述源极接触电极和所述漏极接触电极，所述半导体有源层包括沟道区；
    在所述半导体有源层之上制作阻挡层；
    在所述阻挡层之上制作栅极绝缘层；
    在所述栅极绝缘层之上制作栅极，所述半导体有源层包括沟道区，所述栅极在所述半导体有源层的投影与所述沟道区交叠；
    在所述栅极之上制作层间介质层；
    对所述栅极绝缘层、所述层间介质层和所述阻挡层进行刻蚀形成第一过孔和第二过孔，所述第一过孔暴露所述源极接触电极，所述第二过孔暴露所述漏极接触电极；
    在所述层间介质层之上制作源极和漏极，所述源极通过第一过孔与所述源极接触电极连接，所述漏极通过第二过孔与所述漏极接触电极连接。
  11. 根据权利要求10所述的制作方法，其特征在于，在所述有源层之上制作阻挡层，包括：采用原子层沉积工艺在所述有源层之上制作阻挡层。
  12. 一种驱动基板，其特征在于，包括权利要求1至9任一项所述的薄膜晶体管。
  13. 一种电子设备，其特征在于，包括权利要求12所述的驱动基板。
PCT/CN2021/121233 2020-10-19 2021-09-28 一种薄膜晶体管及其制作方法、驱动基板和电子设备 WO2022083429A1 (zh)

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