WO2024026926A1 - 驱动基板及其制备方法、显示面板 - Google Patents

驱动基板及其制备方法、显示面板 Download PDF

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Publication number
WO2024026926A1
WO2024026926A1 PCT/CN2022/112537 CN2022112537W WO2024026926A1 WO 2024026926 A1 WO2024026926 A1 WO 2024026926A1 CN 2022112537 W CN2022112537 W CN 2022112537W WO 2024026926 A1 WO2024026926 A1 WO 2024026926A1
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Prior art keywords
electrode
substrate
source electrode
drain electrode
auxiliary
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PCT/CN2022/112537
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English (en)
French (fr)
Inventor
罗传宝
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/802,975 priority Critical patent/US20240194685A1/en
Publication of WO2024026926A1 publication Critical patent/WO2024026926A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of display technology, and in particular to a driving substrate, a preparation method thereof, and a display panel.
  • TFT Thin Film Transistor
  • the driving frequency also continues to increase.
  • the electron mobility in the channel region of the active layer affects the operating frequency of the device, and the increase in electron mobility is conducive to the improvement of device performance.
  • the semiconductor material can be changed or the channel width of the thin film transistor can be increased.
  • the increase in the channel width of the thin film transistor leads to an increase in the size of the entire thin film transistor, which is not conducive to achieving high performance. resolution monitor. This limits the improvement of electron mobility of thin film transistors.
  • the present application provides a driving substrate, a preparation method thereof, and a display panel to alleviate the technical problem of limited improvement in electron mobility of existing thin film transistors.
  • An embodiment of the present application provides a driving substrate, which includes:
  • a source electrode and a drain electrode arranged on the substrate, with a first spacing between the source electrode and the drain electrode;
  • An active layer is provided on the substrate, the source electrode and the drain electrode.
  • the active layer includes a channel and source and drain regions located on both sides of the channel.
  • the source area covers On at least part of the source electrode, the drain region covers at least part of the drain electrode, and the channel corresponds to the first interval;
  • a gate electrode is provided on a side of the active layer away from the source electrode and the drain electrode, and is provided corresponding to the active layer.
  • the orthographic projection of the gate on the substrate covers the orthographic projection of the channel of the active layer on the substrate, and also covers the active layer.
  • the driving substrate further includes an auxiliary source electrode located between the source electrode and the substrate and an auxiliary drain electrode located between the drain electrode and the substrate. , the auxiliary source electrode is electrically connected to the source electrode, and the auxiliary drain electrode is electrically connected to the drain electrode.
  • the driving substrate further includes a conductive layer located on a side of the gate away from the active layer and insulated from the gate.
  • the conductive layer includes spaced
  • the first electrode and the connecting wire are electrically connected to the source electrode and the auxiliary source electrode, and the connecting wire is electrically connected to the drain electrode and the auxiliary drain electrode.
  • the orthographic projection of the first electrode on the substrate at least covers the orthographic projection of the channel on the substrate.
  • the driving substrate further includes a buffer layer covering the auxiliary source electrode and the auxiliary drain electrode, and the source electrode and the drain electrode are located on the buffer layer. layer, and the source electrode and the drain electrode are electrically connected to the corresponding source auxiliary electrode and the drain auxiliary electrode through the via holes of the buffer layer.
  • the thickness of the source electrode is smaller than the thickness of the auxiliary source electrode
  • the thickness of the drain electrode is smaller than the thickness of the auxiliary drain electrode. thickness.
  • the orthographic projection of the auxiliary source on the substrate at least covers the orthographic projection of the channel on the substrate.
  • the driving substrate further includes an auxiliary source electrode and an auxiliary drain electrode located on a side of the gate electrode away from the active layer and insulated from the gate electrode.
  • the auxiliary source electrode is electrically connected to the source electrode
  • the auxiliary drain electrode is electrically connected to the drain electrode.
  • the material of the source electrode and the material of the drain electrode both include metal oxide.
  • An embodiment of the present application also provides a display panel, which includes the driving substrate of one of the foregoing embodiments.
  • Embodiments of the present application also provide a driving substrate preparation method, which includes:
  • An active layer is prepared on the substrate, the source electrode and the drain electrode.
  • the active layer includes a channel and source and drain regions located on both sides of the channel.
  • the source area covers On at least part of the source electrode, the drain region covers at least part of the drain electrode, and the channel corresponds to the first interval;
  • a gate electrode is prepared on the side of the active layer away from the substrate, and the orthographic projection of the gate electrode on the substrate covers the orthographic projection of the channel of the active layer on the substrate, And it also covers the orthographic projection of at least part of the source region of the active layer on the substrate and covers the orthographic projection of at least part of the drain region of the active layer on the substrate.
  • the step of preparing the source electrode and the drain electrode on the substrate further includes:
  • a source electrode and a drain electrode are prepared on the buffer layer, with a first space between the source electrode and the drain electrode.
  • the driving substrate preparation method further includes:
  • a conductive layer is prepared on the side of the gate away from the active layer.
  • the conductive layer includes first electrodes and connecting traces arranged at intervals.
  • the first electrode is electrically connected to the source electrode and the auxiliary electrode.
  • Source electrode, the connection trace is electrically connected to the drain electrode and the auxiliary drain electrode.
  • the driving substrate includes a substrate and a source electrode, a drain electrode and an active layer provided on the substrate, and there is a third layer between the source electrode and the drain electrode.
  • An interval the active layer is disposed on the source electrode and the drain electrode, the active layer includes a channel and source and drain regions located on both sides of the channel, the source area covers On at least part of the source electrode, the drain region covers at least part of the drain electrode, and the channel corresponds to the first interval, so that the interval between the source electrode and the drain electrode is Limiting the length of the active layer channel to reduce the length of the active layer channel, thereby improving the electron mobility of the active layer channel, solves the problem of improving the electron mobility of existing thin film transistors Restricted issues.
  • Figure 1 is a schematic cross-sectional structural diagram of a driving substrate provided by this application.
  • Figure 2 is another schematic cross-sectional structural diagram of the driving substrate provided by this application.
  • Figure 3 is another schematic cross-sectional structural diagram of a driving substrate provided by this application.
  • FIG. 4 is a schematic flowchart of the driving substrate preparation method provided by this application.
  • Figure 5 is a schematic cross-sectional structural diagram of the substrate provided by this application.
  • FIG. 6 is a schematic cross-sectional structural diagram of preparing an auxiliary source electrode and an auxiliary drain electrode on the substrate of FIG. 5 .
  • FIG. 7 is a schematic cross-sectional view of the source and drain electrodes prepared on the structure of FIG. 6 .
  • FIG. 8 is a schematic cross-sectional structural diagram of preparing an active layer on the structure of FIG. 7 .
  • FIG. 9 is a schematic cross-sectional structural diagram of a gate electrode prepared on the structure of FIG. 8 .
  • FIG. 10 is a schematic cross-sectional structural diagram of preparing a passivation layer on the structure of FIG. 9 .
  • the driving substrate 100 includes a substrate 10 and a source electrode 20, a drain electrode 30, an active layer 40 and a gate electrode 50 provided on the substrate 10. There is a gap between the source electrode 20 and the drain electrode 30. First interval.
  • the active layer 40 is provided on the substrate 10 and the source electrode 20 and the drain electrode 30 .
  • the active layer 40 includes a channel 41 and source regions 42 located on both sides of the channel 41 and a drain region 43.
  • the source region 42 covers at least part of the source electrode 20.
  • the drain region 43 covers at least part of the drain electrode 30.
  • the channel 41 corresponds to the first interval.
  • the gate electrode 50 is disposed on a side of the active layer 40 away from the source electrode 20 and the drain electrode 30 , and is disposed corresponding to the active layer 40 .
  • the length of the channel 41 of the active layer 40 is defined by the first spacing between the source electrode 20 and the drain electrode 30 to achieve a smaller channel 41 length, so that Reducing the length of the channel 41 of the active layer 40 thereby improves the electron mobility of the channel 41 of the active layer 40, thereby solving the problem of limited improvement in the electron mobility of existing thin film transistors.
  • the driving substrate 100 further includes an auxiliary source electrode 21 located between the source electrode 20 and the substrate 10 and an auxiliary source electrode 21 located between the drain electrode 30 and the substrate 10 Drain 31.
  • the auxiliary source electrode 21 is electrically connected to the source electrode 20 to reduce the resistance of the source electrode 20 ; the auxiliary drain electrode 31 is electrically connected to the drain electrode 30 to reduce the resistance of the drain electrode 30 .
  • the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it may include a glass substrate, a plastic substrate or other rigid substrate; when the substrate 10 is a flexible substrate, it may include Flexible substrates such as polyimide (PI) film and ultra-thin glass film.
  • PI polyimide
  • the auxiliary source electrode 21 and the auxiliary drain electrode 31 are disposed on the substrate 10 , there is an interval between the auxiliary source electrode 21 and the auxiliary drain electrode 31 , and the auxiliary source electrode 21 and the auxiliary drain electrode 31 are spaced apart.
  • the auxiliary drain electrodes 31 are insulated from each other.
  • the materials of the auxiliary source electrode 21 and the auxiliary drain electrode 31 include one or a combination of one or more low-resistivity metals such as Mo, Al, Cu, Ti, etc., such as Mo/Al or Combinations such as Mo/Cu or MoTi/Cu or MoTi/Cu/MoTi or Ti/Al/Ti or Ti/Cu/Ti or Mo/Cu/IZO or IZO/Cu/IZO or Mo/Cu/ITO.
  • one or more low-resistivity metals such as Mo, Al, Cu, Ti, etc., such as Mo/Al or Combinations such as Mo/Cu or MoTi/Cu or MoTi/Cu/MoTi or Ti/Al/Ti or Ti/Cu/Ti or Mo/Cu/IZO or IZO/Cu/IZO or Mo/Cu/ITO.
  • the auxiliary source electrode 21 and the auxiliary drain electrode 31 are covered with a buffer layer 11, and the source electrode 20 and the drain electrode 30 are disposed on a side of the buffer layer 11 away from the substrate 10.
  • the active layer 40 covers at least part of the source electrode 20 , at least part of the drain electrode 30 and the buffer layer 11 .
  • the buffer layer 11 covers the auxiliary source electrode 21 , the auxiliary drain electrode 31 and the substrate 10 .
  • the buffer layer 11 can prevent undesired impurities or contaminants (eg, moisture, oxygen, etc.) from diffusing from the substrate 10 into devices that may be damaged by these impurities or contaminants.
  • the material of the buffer layer 11 includes silicon oxide (SiO x ), silicon nitride (SiN x ), or a stack of silicon oxide and silicon nitride.
  • the buffer layer 11 can also provide a flat top surface to facilitate the formation of the source electrode 20 , the drain electrode 30 and the active layer 40 on the buffer layer 11 .
  • a flat top surface is more conducive to forming This enables the active layer 40 to form good interface characteristics.
  • the source electrode 20 and the drain electrode 30 are formed on the buffer layer 11 with a first interval therebetween.
  • the materials of the source electrode 20 and the drain electrode 30 include metals such as ITO, IZO, ANCL, or metal oxides with low resistivity.
  • the source electrode 20 and the drain electrode 30 are made of metal oxides such as ITO.
  • the etching size difference of metal oxides such as ITO in the yellow light process is small.
  • the source electrode can be made The distance between the first spacing between the electrode 20 and the drain electrode 30 is small, which further enables the active layer 40 to form a channel 41 with a smaller length, and improves the channel 41 of the active layer 40 electron mobility.
  • the thickness of the auxiliary source electrode 21 is greater than the thickness of the source electrode 20 , and the auxiliary drain electrode 21 is thicker than the source electrode 20 .
  • the thickness of the electrode 31 is greater than the thickness of the drain electrode 30 to further reduce the resistance of the auxiliary source electrode 21 and the auxiliary drain electrode 31 .
  • the active layer 40 covers at least part of the source electrode 20, at least part of the drain electrode 30 and the buffer layer 11, so that the source electrode 20 and the drain electrode are formed by using the active layer 40. on the electrode 30 to avoid the influence of the etching liquid on the active layer 40 when the source electrode 20 and the drain electrode 30 are etched.
  • the etching liquid comes into contact with the active layer 40, on the one hand, it will Etching the film layer of the active layer 40 will also cause changes in In, Ga, and Zn plasma concentrations on the surface of the active layer 40, affecting the stability and reliability of the device.
  • the material of the active layer 40 includes semiconductor metal oxides such as IGZO, IGZTO, IGTO, IGO, and AZTO.
  • the channels 41 of the active layer 40 are arranged corresponding to the first spacing. In a direction perpendicular to the substrate 10 and pointing from the substrate 10 to the source electrode 20 , the active layer 40 The thickness is greater than the thickness of the source electrode 20 or the thickness of the drain electrode 30 , so that the channel 41 of the active layer 40 is located within the first interval and exceeds the source electrode 20 or the drain electrode.
  • the source region 42 of the active layer 40 covers the source electrode 20
  • the drain region 43 of the active layer 40 covers the drain electrode 30 . In this way, the surfaces of the source region 42 , the channel 41 and the drain region 43 of the active layer 40 are horizontal on the side away from the buffer layer 11 , so that the active layer 40 is away from the buffer layer 11 .
  • One side surface of 11 is horizontal.
  • the orthographic projection of the channel 41 of the active layer 40 on the substrate 10 falls within the range of the orthographic projection of the auxiliary source 21 on the substrate 10 , so that the auxiliary source 21 is also It has a light-shielding function to prevent light from irradiating the channel 41 of the active layer 40 .
  • the orthographic projection of the auxiliary source electrode 21 on the substrate 10 can also cover the orthographic projection of the entire active layer 40 on the substrate 10 , that is, the source area of the active layer 40
  • the orthographic projections of 42 and the drain region 43 on the substrate 10 also fall within the range of the orthographic projection of the auxiliary source electrode 21 on the substrate 10 .
  • the orthographic projection of the source electrode 20 on the substrate 10 falls within the orthographic projection range of the auxiliary source electrode 21 on the substrate 10 , and the source electrode 20 is on the substrate 10 .
  • the orthographic projection area of the auxiliary source electrode 21 on the substrate 10 is smaller than the orthographic projection area of the auxiliary source electrode 21 on the substrate 10
  • the orthographic projection area of the drain electrode 30 on the substrate 10 is smaller than the auxiliary drain electrode 31 on the substrate 10 .
  • the orthographic projected area on the substrate 10 is provided.
  • the driving substrate 100 further includes a gate 50 located on the active layer 40 and insulated from the active layer 40 .
  • the gate 50 is provided corresponding to the active layer 40 .
  • a gate insulating layer 12 is provided between the gate electrode 50 and the active layer 40 , and the gate insulating layer 12 covers the active layer 40 .
  • the gate electrode 50 is disposed on the on the gate insulating layer 12.
  • the gate insulating layer 12 is also disposed corresponding to the active layer 40 , and the orthographic projection of the gate insulating layer 12 on the substrate 10 is the same as the orthogonal projection of the active layer 40 on the substrate 10 . Projections overlap.
  • the material of the gate insulating layer 12 includes one or a combination of one or more of SiO x , SiN x , and Al 2 O 3 , such as Al 2 O 3 /SiN x /SiO x , SiO x /SiN x /SiO x etc.
  • the gate electrode 50 is disposed on the gate insulating layer 12 .
  • the gate electrode 50 is made of the same material as the auxiliary source electrode 21 .
  • the orthographic projection of the gate 50 on the substrate 10 covers the orthographic projection of the channel 41 of the active layer 40 on the substrate 10 , and also covers at least part of the source of the active layer 40
  • the driving substrate 100 further includes a conductive layer 60 located on a side of the gate 50 away from the active layer 40 and insulated from the gate 50 .
  • the conductive layer 60 includes First electrodes 61 and connecting wires 62 are spaced apart.
  • the first electrode 61 is electrically connected to the source electrode 20 and the auxiliary source electrode 21 to realize the connection between the source electrode 20 and the auxiliary source electrode 21 . electrical connection, and at the same time realize the electrical connection between the first electrode 61 and the source electrode 20 .
  • the connecting wire 62 is electrically connected to the drain electrode 30 and the auxiliary drain electrode 31 to realize the electrical connection between the drain electrode 30 and the auxiliary drain electrode 31 .
  • the passivation layer 13 is provided between the conductive layer 60 and the gate electrode 50 , and the passivation layer 13 covers the gate electrode 50 , part of the source electrode 20 , and part of the gate electrode 50 . on the drain electrode 30 and the buffer layer 11 .
  • a plurality of first via holes 131 and a plurality of second via holes 132 are formed on the passivation layer 13 .
  • the first via holes 131 penetrate the passivation layer 13 , and a part of the first via holes 131 is exposed. Part of the source electrode 20 is exposed, and another part of the first via hole 131 is exposed to part of the drain electrode 30 .
  • the second via hole 132 penetrates the passivation layer 13 and the buffer layer 11 , part of the second via hole 132 exposes part of the auxiliary source electrode 21 , and another part of the second via hole 132 exposes Part of the auxiliary drain electrode 31 is exposed.
  • the first electrode 61 is electrically connected to the source electrode 20 through the conductive layer 60 in the first via hole 131 , and at the same time, the first electrode 61 also passes through the conductive layer 60 in the second via hole 132 A portion is electrically connected to the auxiliary source 21 .
  • the connection trace 62 is electrically connected to the drain electrode 30 through the conductive layer 60 in the first via hole 131 , and at the same time, the connection trace 62 also passes through the conductive layer 60 in the second via hole 132 A portion is electrically connected to the auxiliary drain electrode 31 .
  • the source electrode 20 and the drain electrode 30 can be electrically connected to the corresponding auxiliary source electrode 21 and the auxiliary drain electrode 31 respectively, and the first electrode 61 and the source electrode can be electrically connected through a photomask. Pole 20 electrical connection helps save costs.
  • the orthographic projection of the first electrode 61 on the substrate 10 at least covers the orthographic projection of the channel 41 on the substrate 10 , by arranging a larger area of the first electrode 61 on the substrate 10 .
  • An electrode 61 can block the diffusion of water vapor in the environment to the channel 41 region of the active layer 40, thereby improving the reliability of the device.
  • the orthographic projection of the first electrode 61 on the substrate 10 may also cover the entire orthographic projection of the gate electrode 50 on the substrate 10 . Projection to form a larger area of the first electrode 61 .
  • FIG. 2 is another schematic cross-sectional structural diagram of the driving substrate provided by the present application.
  • the driving substrate 101 also includes a buffer layer 11 covering the auxiliary source electrode 21 and the auxiliary drain electrode 31 , and the source electrode 20 and the drain electrode 30 are located between On the buffer layer 11 , the source electrode 20 and the drain electrode 30 are electrically connected to the corresponding auxiliary electrodes of the source electrode 20 and the drain electrode 30 through the via holes of the buffer layer 11 respectively.
  • a third via hole 111 and a fourth via hole 112 are formed on the buffer layer 11 .
  • the third via hole 111 penetrates the buffer layer 11 and exposes part of the auxiliary source electrode 21 .
  • the fourth via hole 112 penetrates the buffer layer 11 and exposes part of the auxiliary drain electrode 31 .
  • the source electrode 20 is electrically connected to the auxiliary source electrode 21 through the conductive material in the third via hole 111
  • the drain electrode 30 is connected to the auxiliary drain electrode through the conductive material in the fourth via hole 112 31 electrical connections. Please refer to the above embodiment for other descriptions, which will not be described again here.
  • FIG. 3 is another schematic cross-sectional structural diagram of the driving substrate provided by the present application.
  • the driving substrate 102 also includes an auxiliary source electrode 21 and an auxiliary drain electrode 31 located on a side of the gate electrode 50 away from the active layer 40 and insulated from the gate electrode 50 .
  • the auxiliary source electrode 21 is electrically connected to the source electrode 20
  • the auxiliary drain electrode 31 is electrically connected to the drain electrode 30 .
  • the auxiliary source electrode 21 and the auxiliary drain electrode 31 are provided on the passivation layer 13 , and a hole is formed on the passivation layer 13 that penetrates the passivation layer 13 and exposes part of the source electrode 20 and the via hole of the drain electrode 30 .
  • the auxiliary source electrode 21 is electrically connected to the source electrode 20 through the conductive material in the via hole on the passivation layer 13
  • the auxiliary drain electrode 31 is electrically connected to the source electrode 20 through the conductive material in the via hole on the passivation layer 13 .
  • the drain 30 is electrically connected.
  • the auxiliary source electrode 21 and the auxiliary drain electrode 31 are covered with a planarization layer 14, the first electrode 61 is provided on the planarization layer 14, and a planarization layer 14 is formed on the planarization layer 14 through the planarization layer 14.
  • the first electrode 61 is electrically connected to the auxiliary source electrode 21 through the conductive material in the via hole on the planarization layer 14 . Please refer to the above embodiment for other descriptions, which will not be described again here.
  • a driving substrate preparation method is also provided.
  • Figure 4 is a schematic flow chart of the driving substrate preparation method provided by the present application
  • Figure 5 is a cross-section of the substrate provided by the present application.
  • Structural diagram Figure 6 is a schematic cross-sectional structural diagram of the auxiliary source electrode and the auxiliary drain electrode prepared on the substrate of Figure 5
  • Figure 7 is a cross-sectional structural diagram of the source electrode and drain electrode prepared on the structure of Figure 6
  • Figure 8 is a schematic cross-sectional structural diagram of the source electrode and the drain electrode prepared on the structure of Figure 6.
  • Figure 7 is a schematic cross-sectional structural diagram of preparing an active layer on the structure of Figure 7.
  • Figure 9 is a schematic cross-sectional structural diagram of preparing a gate electrode on the structure of Figure 8.
  • Figure 10 is a schematic cross-sectional structural diagram of preparing a passivation layer on the structure of Figure 9.
  • the driving substrate preparation method includes the following steps:
  • the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it may include a glass substrate, a plastic substrate, or other rigid substrate; When the substrate 10 is a flexible substrate, it may include a polyimide (PI) film, an ultra-thin glass film, or other flexible substrate.
  • PI polyimide
  • S302 Prepare a source electrode 20 and a drain electrode 30 on the substrate 10, with a first interval between the source electrode 20 and the drain electrode 30;
  • the material of the first metal film includes one or a combination of one or more low-resistivity metals such as Mo, Al, Cu, Ti, etc., such as Mo/Al or Mo/Cu or MoTi/Cu or Combinations such as MoTi/Cu/MoTi or Ti/Al/Ti or Ti/Cu/Ti or Mo/Cu/IZO or IZO/Cu/IZO or Mo/Cu/ITO.
  • one or more low-resistivity metals such as Mo, Al, Cu, Ti, etc., such as Mo/Al or Mo/Cu or MoTi/Cu or Combinations such as MoTi/Cu/MoTi or Ti/Al/Ti or Ti/Cu/Ti or Mo/Cu/IZO or IZO/Cu/IZO or Mo/Cu/ITO.
  • the material of the buffer layer 11 includes silicon oxide (SiO x ), Silicon nitride (SiN x ) or a stack of silicon oxide and silicon nitride.
  • a source electrode 20 and a drain electrode 30 are prepared on the buffer layer 11 , with a first interval 201 between the source electrode 20 and the drain electrode 30 , as shown in FIG. 7 .
  • the materials of the source electrode 20 and the drain electrode 30 include metals such as ITO, IZO, ANCL, or metal oxides with low resistivity.
  • the source electrode 20 and the drain electrode 30 are made of metal oxides such as ITO. The etching size difference of metal oxides such as ITO in the yellow light process is small.
  • the source electrode can be made The distance between the first spacing between the electrode 20 and the drain electrode 30 is small, which further enables the active layer 40 to form a channel 41 with a smaller length, and improves the channel 41 of the active layer 40 electron mobility.
  • the active layer 40 includes a channel 41 and source regions 42 located on both sides of the channel 41. and a drain region 43, the source region 42 covers at least part of the source electrode 20, the drain region 43 covers at least part of the drain electrode 30, the channel 41 corresponds to the first interval;
  • a metal oxide semiconductor film is plated on the substrate 10 and the source electrode 20 and the drain electrode 30, and the metal oxide semiconductor film is patterned to form an active layer 40.
  • the active layer 40 It includes a channel 41 and a source region 42 and a drain region 43 located on both sides of the channel 41.
  • the source region 42 covers at least part of the source electrode 20, and the drain region 43 covers at least part of the drain electrode 20.
  • the channel 41 corresponds to the first interval, as shown in Figure 8.
  • the material of the active layer 40 includes semiconductor metal oxides such as IGZO, IGZTO, IGTO, IGO, and AZTO.
  • S304 Prepare a gate electrode 50 on the side of the active layer 40 away from the substrate 10.
  • the orthographic projection of the gate electrode 50 on the substrate 10 covers the channel 41 of the active layer 40.
  • a deposition process such as chemical vapor deposition is used to deposit an inorganic thin film on the active layer 40 , the source electrode 20 , the drain electrode 30 and the buffer layer 11 .
  • the material of the inorganic thin film includes SiO x , SiN x , Al 2 O 3 , one or more combinations, for example, it can be Al 2 O 3 /SiN x /SiO x , SiO x /SiN x /SiO x , etc.
  • a deposition process such as physical vapor deposition is used to deposit a second metal film on the inorganic film, and the second metal film is patterned to form a gate electrode 50 .
  • the gate electrode 50 is provided corresponding to the active layer 40 .
  • the material of the second metal film may be the same as the material of the first metal film.
  • the inorganic film is patterned using a self-alignment process using the gate 50 as a shield to form a gate insulating layer 12, as shown in FIG. 9 .
  • the driving substrate preparation method also includes the following steps:
  • a conductive layer 60 is prepared on the side of the gate 50 away from the active layer 40 .
  • the conductive layer 60 includes spaced apart first electrodes 61 and connecting wires 62 .
  • the first electrodes 61 are electrically connected to the
  • the source electrode 20 and the auxiliary source electrode 21 are electrically connected to the drain electrode 30 and the auxiliary drain electrode 31 by the connecting wire 62 .
  • a deposition process such as chemical vapor deposition is used to deposit a passivation layer 13 on the gate electrode 50 , the source electrode 20 , the drain electrode 30 and the buffer layer 11 .
  • the material of the passivation layer 13 is One of silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride.
  • the passivation layer 13 is patterned to form a plurality of first via holes 131 and a plurality of second via holes 132 on the passivation layer 13 , as shown in FIG. 10 .
  • the first via hole 131 penetrates the passivation layer 13 , part of the first via hole 131 exposes part of the source electrode 20 , and another part of the first via hole 131 exposes part of the drain electrode 30 .
  • the second via hole 132 penetrates the passivation layer 13 and the buffer layer 11 , part of the second via hole 132 exposes part of the auxiliary source electrode 21 , and another part of the second via hole 132 exposes Part of the auxiliary drain electrode 31 is exposed.
  • a conductive layer 60 is prepared on the passivation layer 13 , and the conductive layer 60 is patterned to form a first electrode 61 and a connecting trace 62 , as shown in FIG. 1 .
  • the first electrode 61 is electrically connected to the source electrode 20 through the conductive layer 60 in the first via hole 131 , and at the same time, the first electrode 61 also passes through the conductive layer 60 in the second via hole 132 A portion is electrically connected to the auxiliary source 21 .
  • connection trace 62 is electrically connected to the drain electrode 30 through the conductive layer 60 in the first via hole 131 , and at the same time, the connection trace 62 also passes through the conductive layer 60 in the second via hole 132 A portion is electrically connected to the auxiliary drain electrode 31 .
  • the source electrode 20 and the drain electrode 30 can be electrically connected to the auxiliary source electrode 21 and the auxiliary drain electrode 31 respectively, as well as the first electrode 61 and the source electrode 20 through a photomask. electrical connection, which helps save costs.
  • the conductive layer 60 is a layer formed of metal oxide electrode materials such as IZO and ITO.
  • a three-layer metal anti-reflection structure of IZO/Mo/Cu can also be used to reduce the effect of the light-emitting unit on the active Effect of layer 40 channel 41.
  • an embodiment of the present application also provides a display panel, which includes the driving substrate of one of the preceding embodiments.
  • the display panel may be a liquid crystal display panel, an OLED display panel or an LED direct display display panel.
  • the display panel when the display panel is an LED direct display display panel, the display panel further includes an LED chip, and the LED chip is bound to the on the driving substrate 100 .
  • the driving substrate 100 is also provided with a second electrode in the same layer as the first electrode 61 , and the LED chip is in contact with the first electrode 61 and the second electrode on the driving substrate 100 .
  • the electrodes are electrically connected to achieve binding of the LED chip and the driving substrate 100 .
  • the present application provides a driving substrate, a preparation method thereof, and a display panel.
  • the driving substrate includes a substrate, a source electrode, a drain electrode, and an active layer arranged on the substrate. There is a third electrode between the source electrode and the drain electrode.
  • the active layer is disposed on the source electrode and the drain electrode, the active layer includes a channel and source and drain regions located on both sides of the channel, the source area covers On at least part of the source electrode, the drain region covers at least part of the drain electrode, and the channel corresponds to the first interval, so that the interval between the source electrode and the drain electrode is Limiting the length of the active layer channel to reduce the length of the active layer channel, thereby improving the electron mobility of the active layer channel, solving the problem of increasing the electron mobility of existing thin film transistors Restricted issues.

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Abstract

本申请提供一种驱动基板及其制备方法、显示面板，该驱动基板的源极和漏极之间具有第一间隔，有源层设置在源极和漏极上，有源层的沟道对应于第一间隔，如此通过源极和漏极之间的间隔来限定有源层沟道的长度，以减小有源层沟道的长度，进而提升有源层沟道的电子迁移率，以缓解现有薄膜晶体管的电子迁移率的提升受限的问题。

Description

驱动基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种驱动基板及其制备方法、显示面板。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT）已广泛应用在主动式显示器的驱动上，而随着显示器尺寸的不断增大，驱动频率也不断提高。对于薄膜晶体管而言，有源层中沟道区的电子迁移率影响着器件的工作频率，电子迁移率的提升有利于器件性能的提升。
为了改善薄膜晶体管的电子迁移率，可以改变半导体的材料或者可以增大薄膜晶体管的沟道宽度，然而，薄膜晶体管的沟道宽度的增大导致整个薄膜晶体管的尺寸的增大，不利于实现高分辨率的显示器。如此使得薄膜晶体管的电子迁移率的提升受到限制。
 技术问题
本申请提供一种驱动基板及其制备方法、显示面板，以缓解现有薄膜晶体管的电子迁移率的提升受到限制的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种驱动基板，其包括：
衬底；
源极和漏极，设置在所述衬底上，所述源极和所述漏极之间具有第一间隔；
有源层，设置在所述衬底以及所述源极和所述漏极上，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔；
栅极，设置在所述有源层远离所述源极和所述漏极的一侧，并与所述有源层对应设置。
在本申请实施例提供的驱动基板中，所述栅极在所述衬底上的正投影覆盖所述有源层的沟道在所述衬底上的正投影，且还覆盖所述有源层的至少部分源区在所述衬底上的正投影以及覆盖所述有源层的至少部分漏区在所述衬底上的正投影。
在本申请实施例提供的驱动基板中，所述驱动基板还包括位于所述源极与所述衬底之间的辅助源极以及位于所述漏极与所述衬底之间的辅助漏极，所述辅助源极与所述源极电连接，所述辅助漏极与所述漏极电连接。
在本申请实施例提供的驱动基板中，所述驱动基板还包括位于所述栅极远离所述有源层的一侧且与所述栅极绝缘设置的导电层，所述导电层包括间隔设置的第一电极和连接走线，所述第一电极电连接于所述源极和所述辅助源极，所述连接走线电连接于所述漏极和所述辅助漏极。
在本申请实施例提供的驱动基板中，所述第一电极在所述衬底上的正投影至少覆盖所述沟道在所述衬底上的正投影。
在本申请实施例提供的驱动基板中，所述驱动基板还包括位于覆于所述辅助源极和所述辅助漏极之间的缓冲层，所述源极和所述漏极位于所述缓冲层上，且所述源极和所述漏极分别通过所述缓冲层的过孔与对应的所述源极辅助电极和所述漏极辅助电极电连接。
在本申请实施例提供的驱动基板中，在垂直于所述衬底的方向上，所述源极的厚度小于所述辅助源极的厚度，所述漏极的厚度小于所述辅助漏极的厚度。
在本申请实施例提供的驱动基板中，所述辅助源极在所述衬底上的正投影至少覆盖所述沟道在所述衬底上的正投影。
在本申请实施例提供的驱动基板中，所述驱动基板还包括位于所述栅极远离所述有源层的一侧且与所述栅极绝缘设置的辅助源极和辅助漏极，所述辅助源极与所述源极电连接，所述辅助漏极与所述漏极电连接。
在本申请实施例提供的驱动基板中，所述源极的材料和所述漏极的材料均包括金属氧化物。
本申请实施例还提供一种显示面板，其包括前述实施例其中之一的驱动基板。
本申请实施例还提供一种驱动基板制备方法，其包括：
提供衬底；
在所述衬底上制备源极和漏极，所述源极和所述漏极之间具有第一间隔；
在所述衬底以及所述源极和所述漏极上制备有源层，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔；
在所述有源层远离所述衬底的一侧制备栅极，所述栅极在所述衬底上的正投影覆盖所述有源层的沟道在所述衬底上的正投影，且还覆盖所述有源层的至少部分源区在所述衬底上的正投影以及覆盖所述有源层的至少部分漏区在所述衬底上的正投影。
在本申请实施例提供的驱动基板制备方法中，所述在在所述衬底上制备源极和漏极的步骤，还包括：
采用物理气相沉积法在所述衬底上制备第一金属薄膜，图案化所述第一金属薄膜形成辅助源极和辅助漏极；
采用化学气相沉积法在所述辅助源极、所述辅助漏极以及所述衬底上沉积缓冲层；
在所述缓冲层上制备源极和漏极，所述源极和所述漏极之间具有第一间隔。
在本申请实施例提供的驱动基板制备方法中，所述驱动基板制备方法还包括：
在所述栅极远离所述有源层的一侧制备导电层，所述导电层包括间隔设置的第一电极和连接走线，所述第一电极电连接于所述源极和所述辅助源极，所述连接走线电连接于所述漏极和所述辅助漏极。
 有益效果
本申请提供的驱动基板及其制备方法、显示面板中，驱动基板包括衬底以及设置在衬底上的源极、漏极以及有源层，所述源极和所述漏极之间具有第一间隔，所述有源层设置在所述源极和所述漏极上，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔，如此通过所述源极和所述漏极之间的间隔来限定所述有源层沟道的长度，以减小所述有源层沟道的长度，进而提升所述有源层沟道的电子迁移率，解决了现有薄膜晶体管的电子迁移率的提升受到限制的问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请提供的驱动基板的一种剖面结构示意图。
图2为本申请提供的驱动基板的另一种剖面结构示意图。
图3为本申请提供的驱动基板的又一种剖面结构示意图。
图4为本申请提供的驱动基板制备方法的流程示意图。
图5为本申请提供的衬底的剖面结构示意图。
图6为在图5的衬底上制备辅助源极和辅助漏极的剖面结构示意图。
图7为在图6的结构上制备源极和漏极的剖面结构示意图。
图8为在图7的结构上制备有源层的剖面结构示意图。
图9为在图8的结构上制备栅极的剖面结构示意图。
图10为在图9的结构上制备钝化层的剖面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请参照图1，图1为本申请提供的驱动基板的一种剖面结构示意图。所述驱动基板100包括衬底10以及设置在所述衬底10上的源极20、漏极30、有源层40和栅极50，所述源极20和所述漏极30之间具有第一间隔。所述有源层40设置在所述衬底10以及所述源极20和所述漏极30上，所述有源层40包括沟道41以及位于所述沟道41两侧的源区42和漏区43，所述源区42覆于至少部分所述源极20上，所述漏区43覆于至少部分所述漏极30上，所述沟道41对应于所述第一间隔。所述栅极50设置在所述有源层40远离所述源极20和所述漏极30的一侧，并与所述有源层40对应设置。
在本实施例中，通过所述源极20和所述漏极30之间的第一间隔来限定所述有源层40沟道41的长度，以实现较小的沟道41长度，如此可减小所述有源层40沟道41的长度，进而提升所述有源层40沟道41的电子迁移率，解决了现有薄膜晶体管的电子迁移率的提升受到限制的问题。
在一种实施例中，所述驱动基板100还包括位于所述源极20与所述衬底10之间的辅助源极21以及位于所述漏极30与所述衬底10之间的辅助漏极31。所述辅助源极21与所述源极20电连接，以降低所述源极20的电阻；所述辅助漏极31与所述漏极30电连接，以降低所述漏极30的电阻。
可选地，所述衬底10可以为刚性基板或柔性基板；所述衬底10为刚性基板时，可包括玻璃基板、塑料基板等硬性基板；所述衬底10为柔性基板时，可包括聚酰亚胺（Polyimide，PI）薄膜、超薄玻璃薄膜等柔性基板。
所述辅助源极21和所述辅助漏极31设置在所述衬底10上，所述辅助源极21和所述辅助漏极31之间具有间隔，且所述辅助源极21和所述辅助漏极31之间绝缘设置。可选地，所述辅助源极21和所述辅助漏极31的材料均包括Mo、Al、Cu、Ti等低电阻率金属中的一种或多种的组合，比如可以为Mo/Al或Mo/Cu或MoTi/Cu或MoTi/Cu/MoTi或Ti/Al/Ti或Ti/Cu/Ti或Mo/Cu/IZO或IZO/Cu/IZO或Mo/Cu/ITO等组合。
所述辅助源极21和所述辅助漏极31上覆盖有缓冲层11，所述源极20和所述漏极30设置在所述缓冲层11远离所述衬底10的一侧，所述有源层40覆于至少部分所述源极20、至少部分所述漏极30以及所述缓冲层11上。
具体而言，所述缓冲层11覆盖在所述辅助源极21、所述辅助漏极31以及所述衬底10上。所述缓冲层11可以防止不期望的杂质或污染物（例如湿气、氧气等）从所述衬底10扩散至可能因这些杂质或污染物而受损的器件中。可选地，所述缓冲层11的材料包括氧化硅（SiO x）、氮化硅（SiN x）或者氧化硅和氮化硅的叠层。
同时所述缓冲层11还可以提供平坦的顶表面，以便于在所述缓冲层11上形成所述源极20、所述漏极30以及所述有源层40，平坦的顶表面更有利于使所述有源层40形成良好的界面特性。
所述源极20和所述漏极30形成在所述缓冲层11上，所述源极20和所述漏极30之间具有第一间隔。所述源极20和所述漏极30的材料均包括ITO、IZO、ANCL等金属或电阻率低的金属氧化物。比如所述源极20和所述漏极30采用ITO等金属氧化物，ITO等金属氧化物在黄光制程的刻蚀尺寸差值较小，在曝光机极限的情形下，能够使所述源极20和所述漏极30之间的所述第一间隔的距离较小，进而能够进一步使所述有源层40形成较小长度的沟道41，提高所述有源层40沟道41的电子迁移率。
进一步地，在垂直于所述衬底10，且从所述衬底10指向所述源极20的方向上，所述辅助源极21的厚度大于所述源极20的厚度，所述辅助漏极31的厚度大于所述漏极30的厚度，以进一步减小所述辅助源极21以及所述辅助漏极31的电阻。
所述有源层40覆盖于至少部分所述源极20、至少部分所述漏极30以及所述缓冲层11上，如此通过把所述有源层40形成所述源极20和所述漏极30上，避免了在刻蚀形成所述源极20和所述漏极30时，蚀刻液对所述有源层40的影响，比如蚀刻液与所述有源层40接触，一方面会刻蚀所述有源层40的膜层，同时还会造成所述有源层40表面In、Ga、Zn等离子浓度的变化，影响器件的稳定性和可靠性。可选地，所述有源层40的材料包括IGZO、IGZTO、IGTO、IGO、AZTO等半导体金属氧化物。
所述有源层40的沟道41对应所述第一间隔设置，在垂直于所述衬底10，且从所述衬底10指向所述源极20的方向上，所述有源层40的厚度大于所述源极20的厚度或所述漏极30的厚度，使得所述有源层40的沟道41位于所述第一间隔内，且超出所述源极20或所述漏极30的高度，所述有源层40的源区42覆于所述源极20上，所述有源层40的漏区43覆于所述漏极30上。如此所述有源层40的源区42、所述沟道41以及所述漏区43在远离所述缓冲层11的一侧表面是水平的，使得所述有源层40远离所述缓冲层11的一侧表面是水平的。
所述有源层40的沟道41在所述衬底10上的正投影落在所述辅助源极21在所述衬底10上的正投影的范围内，使得所述辅助源极21还具有遮光的功能，以避免光线照射所述有源层40的沟道41。当然地，所述辅助源极21在所述衬底10上的正投影还可覆盖整个所述有源层40在所述衬底10上的正投影，即所述有源层40的源区42和漏区43在所述衬底10上的正投影也均落在所述辅助源极21在所述衬底10上的正投影的范围内。
进一步地，所述源极20在所述衬底10上的正投影落在所述辅助源极21在所述衬底10上的正投影范围内，且所述源极20在所述衬底10上的正投影面积小于所述辅助源极21在所述衬底10上的正投影面积，同时所述漏极30在所述衬底10上的正投影面积小于所述辅助漏极31在所述衬底10上的正投影面积。
下面将具体阐述如何使所述源极20和所述漏极30分别与所述辅助源极21和所述辅助漏极31电连接：
在一种实施例中，所述驱动基板100还包括位于所述有源层40上且与所述有源层40绝缘设置的栅极50，所述栅极50对应所述有源层40设置。具体而言，所述栅极50与所述有源层40之间设置有栅极绝缘层12，所述栅极绝缘层12覆于所述有源层40，所述栅极50设置在所述栅极绝缘层12上。
所述栅极绝缘层12也对应所述有源层40设置，所述栅极绝缘层12在所述衬底10上的正投影与所述有源层40在所述衬底10上的正投影重叠。可选地，所述栅极绝缘层12的材料包括SiO x、SiN x、Al 2O 3中的一种或多种的组合，比如可以为Al 2O 3/SiN x/SiO x、SiO x/SiN x/SiO x等。
所述栅极50设置在所述栅极绝缘层12上，可选地，所述栅极50的材料与所述辅助源极21的材料相同。所述栅极50在所述衬底10上的正投影覆盖所述有源层40的沟道41在所述衬底10上的正投影，且还覆盖所述有源层40的至少部分源区42在所述衬底10上的正投影以及覆盖所述有源层40的至少部分漏区43在所述衬底10上的正投影，以使得在垂直于所述衬底10的方向上，所述栅极50与所述源极20以及所述漏极30均存在重叠部分。
可以理解的是，当所述栅极50上有驱动电压时，所述栅极50与对应的所述源极20之间形成电场，该电场可使所述栅极50与所述源极20之间的所述有源层40的源区42由半导体变成导体。相应地，当所述栅极50上有驱动电压时，所述栅极50与对应的所述漏极30之间形成电场，该电场可使所述栅极50与所述漏极30之间的所述有源层40的漏区43由半导体变成导体。从而无需采用等离子体等导体化方式对所述有源层40的源区42以及漏区43进行导体化。
在一种实施例中，所述驱动基板100还包括位于所述栅极50远离所述有源层40的一侧且与所述栅极50绝缘设置的导电层60，所述导电层60包括间隔设置的第一电极61和连接走线62，所述第一电极61电连接于所述源极20和所述辅助源极21，以实现所述源极20和所述辅助源极21的电连接，并同时实现所述第一电极61与所述源极20的电连接。所述连接走线62电连接于所述漏极30和所述辅助漏极31，以实现所述漏极30与所述辅助漏极31的电连接。
可选地，所述导电层60与所述栅极50之间设置有所述钝化层13，所述钝化层13覆于所述栅极50、部分所述源极20、部分所述漏极30以及所述缓冲层11上。所述钝化层13上形成有多个第一过孔131和多个第二过孔132，所述第一过孔131贯穿所述钝化层13，其中一部分所述第一过孔131暴露出部分所述源极20，另外一部分所述第一过孔131暴露出部分所述漏极30。所述第二过孔132贯穿所述钝化层13以及所述缓冲层11，其中一部分所述第二过孔132暴露出部分所述辅助源极21，另外一部分所述第二过孔132暴露出部分所述辅助漏极31。
所述第一电极61通过所述第一过孔131内的导电层60部分与所述源极20电连接，同时所述第一电极61还通过所述第二过孔132内的导电层60部分与所述辅助源极21电连接。所述连接走线62通过所述第一过孔131内的导电层60部分与所述漏极30电连接，同时所述连接走线62还通过所述第二过孔132内的导电层60部分与所述辅助漏极31电连接。如此通过一道光罩即可实现所述源极20和所述漏极30分别与对应的所述辅助源极21和所述辅助漏极31的电连接以及所述第一电极61与所述源极20的电连接，有利于节省成本。
在一种实施例中，所述第一电极61在所述衬底10上的正投影至少覆盖所述沟道41在所述衬底10上的正投影，通过设置较大面积的所述第一电极61能够阻挡环境中水汽向所述有源层40的沟道41区域扩散，进而能够提升器件的可靠性。
可选地，为了实现更好的阻挡环境中水汽的效果，所述第一电极61在所述衬底10上的正投影还可覆盖整个所述栅极50在所述衬底10上的正投影，以形成更大面积的所述第一电极61。
在一种实施例中，请结合参照图1和图2，图2为本申请提供的驱动基板的另一种剖面结构示意图。与上述实施例不同的是，所述驱动基板101还包括位于覆于所述辅助源极21和所述辅助漏极31之间的缓冲层11，所述源极20和所述漏极30位于所述缓冲层11上，且所述源极20和所述漏极30分别通过所述缓冲层11的过孔与对应的所述源极20辅助电极和所述漏极30辅助电极电连接。
具体地，所述缓冲层11上形成有第三过孔111和第四过孔112，所述第三过孔111贯穿所述缓冲层11，并暴露出部分所述辅助源极21，所述第四过孔112贯穿所述缓冲层11，并暴露出部分所述辅助漏极31。所述源极20通过所述第三过孔111内的导电材料与所述辅助源极21电连接，所述漏极30通过所述第四过孔112内的导电材料与所述辅助漏极31电连接。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，请结合参照图1和图3，图3为本申请提供的驱动基板的又一种剖面结构示意图。与上述实施例不同的是，所述驱动基板102还包括位于所述栅极50远离所述有源层40的一侧且与所述栅极50绝缘设置的辅助源极21和辅助漏极31，所述辅助源极21与所述源极20电连接，所述辅助漏极31与所述漏极30电连接。
具体地，所述辅助源极21和所述辅助漏极31设置在所述钝化层13上，所述钝化层13上形成有贯穿所述钝化层13并暴露部分所述源极20和所述漏极30的过孔。所述辅助源极21通过所述钝化层13上过孔内的导电材料与所述源极20电连接，所述辅助漏极31通过所述钝化层13上过孔内的导电材料与所述漏极30电连接。
所述辅助源极21所述辅助漏极31上覆盖有平坦化层14，所述第一电极61设置在所述平坦化层14上，所述平坦化层14上形成有贯穿所述平坦化层14并暴露部分所述辅助源极21的过孔，所述第一电极61通过所述平坦化层14上过孔内的导电材料与所述辅助源极21电连接。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，还提供一种驱动基板制备方法，请参照图4至图10，图4为本申请提供的驱动基板制备方法的流程示意图，图5为本申请提供的衬底的剖面结构示意图，图6为在图5的衬底上制备辅助源极和辅助漏极的剖面结构示意图，图7为在图6的结构上制备源极和漏极的剖面结构示意图，图8为在图7的结构上制备有源层的剖面结构示意图，图9为在图8的结构上制备栅极的剖面结构示意图，图10为在图9的结构上制备钝化层的剖面结构示意图。所述驱动基板制备方法包括以下步骤：
S301：提供衬底10；
具体地，提供衬底10，如图5所示，所述衬底10可以为刚性基板或柔性基板；所述衬底10为刚性基板时，可包括玻璃基板、塑料基板等硬性基板；所述衬底10为柔性基板时，可包括聚酰亚胺（Polyimide，PI）薄膜、超薄玻璃薄膜等柔性基板。
S302：在所述衬底10上制备源极20和漏极30，所述源极20和所述漏极30之间具有第一间隔；
具体地，采用物理气相沉积法等沉积工艺在所述衬底10上制备第一金属薄膜，图案化所述第一金属薄膜形成辅助源极21和辅助漏极31，如图6所示。可选地，所述第一金属薄膜的材料包括Mo、Al、Cu、Ti等低电阻率金属中的一种或多种的组合，比如可以为Mo/Al或Mo/Cu或MoTi/Cu或MoTi/Cu/MoTi或Ti/Al/Ti或Ti/Cu/Ti或Mo/Cu/IZO或IZO/Cu/IZO或Mo/Cu/ITO等组合。
接着采用化学气相沉积法等沉积工艺在所述辅助源极21、所述辅助漏极31以及所述衬底10上沉积缓冲层11，所述缓冲层11的材料包括氧化硅（SiO x）、氮化硅（SiN x）或者氧化硅和氮化硅的叠层。
然后在所述缓冲层11上制备源极20和漏极30，所述源极20和所述漏极30之间具有第一间隔201，如图7所示。所述源极20和所述漏极30的材料均包括ITO、IZO、ANCL等金属或电阻率低的金属氧化物。比如所述源极20和所述漏极30采用ITO等金属氧化物，ITO等金属氧化物在黄光制程的刻蚀尺寸差值较小，在曝光机极限的情形下，能够使所述源极20和所述漏极30之间的所述第一间隔的距离较小，进而能够进一步使所述有源层40形成较小长度的沟道41，提高所述有源层40沟道41的电子迁移率。
S303：在所述衬底10以及所述源极20和所述漏极30上制备有源层40，所述有源层40包括沟道41以及位于所述沟道41两侧的源区42和漏区43，所述源区42覆于至少部分所述源极20上，所述漏区43覆于至少部分所述漏极30上，所述沟道41对应于所述第一间隔；
具体地，在所述衬底10以及所述源极20和所述漏极30上镀金属氧化物半导体薄膜，图案化所述金属氧化物半导体薄膜形成有源层40，所述有源层40包括沟道41以及位于所述沟道41两侧的源区42和漏区43，所述源区42覆于至少部分所述源极20上，所述漏区43覆于至少部分所述漏极30上，所述沟道41对应于所述第一间隔，如图8所示。
可选地，所述有源层40的材料包括IGZO、IGZTO、IGTO、IGO、AZTO等半导体金属氧化物。
S304：在所述有源层40远离所述衬底10的一侧制备栅极50，所述栅极50在所述衬底10上的正投影覆盖所述有源层40的沟道41在所述衬底10上的正投影，且还覆盖所述有源层40的至少部分源区42在所述衬底10上的正投影以及覆盖所述有源层40的至少部分漏区43在所述衬底上的正投影；
具体地，采用化学气相沉积法等沉积工艺在所述有源层40、所述源极20、所述漏极30以及所述缓冲层11上沉积无机薄膜，所述无机薄膜的材料包括SiO x、SiN x、Al 2O 3中的一种或多种的组合，比如可以为Al 2O 3/SiN x/SiO x、SiO x/SiN x/SiO x等。
接着采用物理气相沉积法等沉积工艺在所述无机薄膜上沉积第二金属薄膜，图案化所述第二金属薄膜形成栅极50，所述栅极50对应所述有源层40设置。可选地，所述第二金属薄膜的材料可与所述第一金属薄膜的材料相同。
然后以所述栅极50为遮挡采用自对准工艺对所述无机薄膜进行图案化，以形成栅极绝缘层12，如图9所示。
所述驱动基板制备方法还包括以下步骤：
在所述栅极50远离所述有源层40的一侧制备导电层60，所述导电层60包括间隔设置的第一电极61和连接走线62，所述第一电极61电连接于所述源极20和所述辅助源极21，所述连接走线62电连接于所述漏极30和所述辅助漏极31。
具体地，采用化学气相沉积法等沉积工艺在所述栅极50、所述源极20、所述漏极30以及所述缓冲层11上沉积钝化层13，所述钝化层13的材料包括氧化硅、氮化硅或者氧化硅和氮化硅的叠层中的一种。
图案化所述钝化层13以在所述钝化层13上形成多个第一过孔131和多个第二过孔132，如图10所示。所述第一过孔131贯穿所述钝化层13，其中一部分所述第一过孔131暴露出部分所述源极20，另外一部分所述第一过孔131暴露出部分所述漏极30。所述第二过孔132贯穿所述钝化层13以及所述缓冲层11，其中一部分所述第二过孔132暴露出部分所述辅助源极21，另外一部分所述第二过孔132暴露出部分所述辅助漏极31。
接着在所述钝化层13上制备导电层60，图案化所述导电层60形成第一电极61和连接走线62，如图1所示。所述第一电极61通过所述第一过孔131内的导电层60部分与所述源极20电连接，同时所述第一电极61还通过所述第二过孔132内的导电层60部分与所述辅助源极21电连接。所述连接走线62通过所述第一过孔131内的导电层60部分与所述漏极30电连接，同时所述连接走线62还通过所述第二过孔132内的导电层60部分与所述辅助漏极31电连接。如此通过一道光罩即可实现所述源极20和所述漏极30分别与所述辅助源极21和所述辅助漏极31的电连接以及所述第一电极61与所述源极20的电连接，有利于节省成本。
可选地，所述导电层60是由IZO、ITO等金属氧化物电极材料形成的层，也可采用IZO/Mo/Cu的三层金属的减反结构，以降低发光单元对所述有源层40沟道41的影响。
基于同一发明构思，本申请实施例还提供一种显示面板，所述显示面板包括前述实施例其中之一的驱动基板。所述显示面板可以为液晶显示面板、OLED显示面板或LED直显显示面板等，比如所述显示面板为LED直显显示面板时，所述显示面板还包括LED芯片，LED芯片绑定在所述驱动基板100上。具体而言，所述驱动基板100上还设置有与所述第一电极61同层的第二电极，所述LED芯片与所述驱动基板100上的所述第一电极61和所述第二电极电连接，以实现所述LED芯片与所述驱动基板100的绑定。
根据上述实施例可知：
本申请提供一种驱动基板及其制备方法、显示面板，驱动基板包括衬底以及设置在衬底上的源极、漏极以及有源层，所述源极和所述漏极之间具有第一间隔，所述有源层设置在所述源极和所述漏极上，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔，如此通过所述源极和所述漏极之间的间隔来限定所述有源层沟道的长度，以减小所述有源层沟道的长度，进而提升所述有源层沟道的电子迁移率，解决了现有薄膜晶体管的电子迁移率的提升受到限制的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种驱动基板，其包括：
    衬底；
    源极和漏极，设置在所述衬底上，所述源极和所述漏极之间具有第一间隔；
    有源层，设置在所述衬底以及所述源极和所述漏极上，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔；以及
    栅极，设置在所述有源层远离所述源极和所述漏极的一侧，并与所述有源层对应设置；
    其中，所述栅极在所述衬底上的正投影覆盖所述有源层的沟道在所述衬底上的正投影，且还覆盖所述有源层的至少部分源区在所述衬底上的正投影以及覆盖所述有源层的至少部分漏区在所述衬底上的正投影。
  2. 根据权利要求1所述的驱动基板，其中，所述驱动基板还包括位于所述源极与所述衬底之间的辅助源极以及位于所述漏极与所述衬底之间的辅助漏极，所述辅助源极与所述源极电连接，所述辅助漏极与所述漏极电连接。
  3. 根据权利要求2所述的驱动基板，其中，所述驱动基板还包括位于所述栅极远离所述有源层的一侧且与所述栅极绝缘设置的导电层，所述导电层包括间隔设置的第一电极和连接走线，所述第一电极电连接于所述源极和所述辅助源极，所述连接走线电连接于所述漏极和所述辅助漏极。
  4. 根据权利要求3所述的驱动基板，其中，所述第一电极在所述衬底上的正投影至少覆盖所述沟道在所述衬底上的正投影。
  5. 根据权利要求2所述的驱动基板，其中，所述驱动基板还包括位于覆于所述辅助源极和所述辅助漏极之间的缓冲层，所述源极和所述漏极位于所述缓冲层上，且所述源极和所述漏极分别通过所述缓冲层的过孔与对应的所述源极辅助电极和所述漏极辅助电极电连接。
  6. 根据权利要求2所述的驱动基板，其中，在垂直于所述衬底的方向上，所述源极的厚度小于所述辅助源极的厚度，所述漏极的厚度小于所述辅助漏极的厚度。
  7. 根据权利要求2所述的驱动基板，其中，所述辅助源极在所述衬底上的正投影至少覆盖所述沟道在所述衬底上的正投影。
  8. 根据权利要求1所述的驱动基板，其中，所述驱动基板还包括位于所述栅极远离所述有源层的一侧且与所述栅极绝缘设置的辅助源极和辅助漏极，所述辅助源极与所述源极电连接，所述辅助漏极与所述漏极电连接。
  9. 根据权利要求1所述的驱动基板，其中，所述源极的材料和所述漏极的材料均包括金属氧化物。
  10. 一种显示面板，其包括驱动基板，所述驱动基板包括：
    衬底；
    源极和漏极，设置在所述衬底上，所述源极和所述漏极之间具有第一间隔；
    有源层，设置在所述衬底以及所述源极和所述漏极上，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔；以及
    栅极，设置在所述有源层远离所述源极和所述漏极的一侧，并与所述有源层对应设置；
    其中，所述栅极在所述衬底上的正投影覆盖所述有源层的沟道在所述衬底上的正投影，且还覆盖所述有源层的至少部分源区在所述衬底上的正投影以及覆盖所述有源层的至少部分漏区在所述衬底上的正投影。
  11. 根据权利要求10所述的显示面板，其中，所述驱动基板还包括位于所述源极与所述衬底之间的辅助源极以及位于所述漏极与所述衬底之间的辅助漏极，所述辅助源极与所述源极电连接，所述辅助漏极与所述漏极电连接。
  12. 根据权利要求11所述的显示面板，其中，所述驱动基板还包括位于所述栅极远离所述有源层的一侧且与所述栅极绝缘设置的导电层，所述导电层包括间隔设置的第一电极和连接走线，所述第一电极电连接于所述源极和所述辅助源极，所述连接走线电连接于所述漏极和所述辅助漏极。
  13. 根据权利要求12所述的显示面板，其中，所述第一电极在所述衬底上的正投影至少覆盖所述沟道在所述衬底上的正投影。
  14. 根据权利要求11所述的显示面板，其中，所述驱动基板还包括位于覆于所述辅助源极和所述辅助漏极之间的缓冲层，所述源极和所述漏极位于所述缓冲层上，且所述源极和所述漏极分别通过所述缓冲层的过孔与对应的所述源极辅助电极和所述漏极辅助电极电连接。
  15. 根据权利要求11所述的显示面板，其中，在垂直于所述衬底的方向上，所述源极的厚度小于所述辅助源极的厚度，所述漏极的厚度小于所述辅助漏极的厚度。
  16. 根据权利要求11所述的显示面板，其中，所述辅助源极在所述衬底上的正投影至少覆盖所述沟道在所述衬底上的正投影。
  17. 根据权利要求10所述的显示面板，其中，所述源极的材料和所述漏极的材料均包括金属氧化物。
  18. 一种驱动基板制备方法，其包括：
    提供衬底；
    在所述衬底上制备源极和漏极，所述源极和所述漏极之间具有第一间隔；
    在所述衬底以及所述源极和所述漏极上制备有源层，所述有源层包括沟道以及位于所述沟道两侧的源区和漏区，所述源区覆于至少部分所述源极上，所述漏区覆于至少部分所述漏极上，所述沟道对应于所述第一间隔；
    在所述有源层远离所述衬底的一侧制备栅极，所述栅极在所述衬底上的正投影覆盖所述有源层的沟道在所述衬底上的正投影，且还覆盖所述有源层的至少部分源区在所述衬底上的正投影以及覆盖所述有源层的至少部分漏区在所述衬底上的正投影。
  19. 根据权利要求18所述的驱动基板制备方法，其中，所述在在所述衬底上制备源极和漏极的步骤，还包括：
    采用物理气相沉积法在所述衬底上制备第一金属薄膜，图案化所述第一金属薄膜形成辅助源极和辅助漏极；
    采用化学气相沉积法在所述辅助源极、所述辅助漏极以及所述衬底上沉积缓冲层；
    在所述缓冲层上制备源极和漏极，所述源极和所述漏极之间具有第一间隔。
  20. 根据权利要求19所述的驱动基板制备方法，其中，所述驱动基板制备方法还包括：
    在所述栅极远离所述有源层的一侧制备导电层，所述导电层包括间隔设置的第一电极和连接走线，所述第一电极电连接于所述源极和所述辅助源极，所述连接走线电连接于所述漏极和所述辅助漏极。
PCT/CN2022/112537 2022-08-05 2022-08-15 驱动基板及其制备方法、显示面板 WO2024026926A1 (zh)

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