WO2020215602A1 - Oled显示面板的制备方法及oled显示面板 - Google Patents

Oled显示面板的制备方法及oled显示面板 Download PDF

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Publication number
WO2020215602A1
WO2020215602A1 PCT/CN2019/106569 CN2019106569W WO2020215602A1 WO 2020215602 A1 WO2020215602 A1 WO 2020215602A1 CN 2019106569 W CN2019106569 W CN 2019106569W WO 2020215602 A1 WO2020215602 A1 WO 2020215602A1
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layer
oxide semiconductor
gate
semiconductor layer
light shielding
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PCT/CN2019/106569
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English (en)
French (fr)
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姜云龙
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020215602A1 publication Critical patent/WO2020215602A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This application relates to the field of display technology, and in particular to a method for manufacturing an OLED display panel and an OLED display panel.
  • AMOLED active matrix light-emitting diode panel
  • TFT Thin Film Transistor
  • its carrier concentration is ten times that of amorphous silicon.
  • the double-gate oxide semiconductor thin film transistor used in the TFT array substrate has better performance than the single-gate oxide semiconductor thin film transistor, such as higher electron mobility, larger on-state current, and greater subthreshold swing. Smaller, better threshold voltage stability and uniformity, better grid bias and illumination stability, etc.
  • the existing OLED display panel manufacturing method and OLED display panel because the pixel driving circuit adopts the double-gate oxide semiconductor thin film transistor structure, it is difficult for the pixel driving circuit to reach the saturation current, resulting in relatively low pixel driving voltage. It further affects the working stability of the OLED display device.
  • the present application provides a method for manufacturing an OLED display panel and an OLED display panel, which can accelerate the saturation current when the double-gate oxide semiconductor thin film transistor structure is adopted in the pixel driving circuit, so as to solve the problem of the existing manufacturing method and
  • the pixel drive circuit adopts a double-gate oxide semiconductor thin film transistor structure, it is difficult for the pixel drive circuit to reach the saturation current, resulting in a large pixel drive voltage, which further affects the technical problem of the working stability of the OLED display device .
  • the present application provides a method for manufacturing an OLED display panel, the method includes:
  • a passivation layer, a planarization layer, a pixel electrode, a pixel definition layer, an OLED light-emitting device, and a cathode metal layer are sequentially prepared on the interlayer insulating layer and the second metal layer, and the pixel electrode is located on the flat surface. On the chemical layer and in contact with the second drain electrode, and finally the OLED display panel is manufactured.
  • the physical vapor deposition method is used to deposit the first oxide semiconductor layer and the second oxide semiconductor layer in the S30.
  • the materials of the first oxide semiconductor layer and the second oxide semiconductor layer are IGZO or IZTO.
  • the S40 further includes:
  • S401 Perform ion doping on the regions on both sides of the first oxide semiconductor layer and the regions on both sides of the second oxide semiconductor layer, so that the regions on both sides of the first oxide semiconductor layer and the second oxide semiconductor layer The areas on both sides of the dioxide semiconductor layer are transformed into conductors.
  • the first source electrode and the first drain electrode respectively pass through the first via hole and the first oxide semiconductor
  • the regions on both sides of the layer are in contact with each other, the first source is in contact with the first bottom gate via the third via hole, and the second source and the second drain are in contact with the first bottom gate respectively.
  • Two via holes are in contact with regions on both sides of the second oxide semiconductor layer, and the second source electrode is in contact with the light shielding layer through the fourth via holes.
  • the materials of the first bottom gate, the light shielding layer, the first metal layer and the second metal layer are molybdenum, aluminum, One or more stack combinations of copper.
  • the materials of the buffer layer and the interlayer insulating layer are silicon nitride, silicon oxide or a combination of the two.
  • the application also provides an OLED display panel, including a glass substrate, a first bottom gate, a light shielding layer, a buffer layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a first gate insulating layer, and a second Gate insulating layer, first top gate, second top gate, interlayer insulating layer, first source, first drain, second source, second drain, passivation layer, planarization layer, Pixel electrode, pixel definition layer, OLED light emitting device and cathode metal layer;
  • the interlayer insulating layer and the buffer layer are respectively formed with first via holes located above both sides of the first oxide semiconductor layer, and second via holes located above both sides of the second oxide semiconductor layer.
  • the first source and the first drain are located on both sides of the first top gate and are in contact with the first oxide semiconductor layer through the first via hole
  • the second source and The second drain is located on both sides of the second top gate and contacts the second oxide semiconductor layer through the second via hole
  • the first source is connected to the second oxide semiconductor layer via the third via hole.
  • the first bottom gate is in contact
  • the second source is in contact with the light shielding layer through the fourth via hole.
  • the first oxide semiconductor layer and the second oxide semiconductor layer are deposited by physical vapor deposition, and the first oxide semiconductor layer and the The material of the second oxide semiconductor layer is IGZO or IZTO.
  • the first bottom gate, the light shielding layer, the first source, the first drain, the first top gate, and the second top The material of the gate electrode, the second source electrode and the second drain electrode is a stack combination of one or more of molybdenum, aluminum and copper; the material of the buffer layer and the interlayer insulating layer is nitrogen Silicon oxide, silicon oxide or a combination of the two.
  • the beneficial effects of the present application are: the method for preparing the OLED display panel and the OLED display panel provided by the present application, in the pixel driving circuit, the switching TFT adopts a double gate structure and the driving TFT adopts the top of the light shielding layer in contact with the source.
  • the gate structure improves the capacitor charging speed, further reduces the capacitor charging time, and further improves the display characteristics of the OLED display panel.
  • FIG. 1 is a flow chart of the manufacturing method of the OLED display panel of this application.
  • 2A-2G are schematic diagrams of the preparation method of the TFT array substrate of FIG. 1.
  • FIG. 3 is a schematic diagram of the structure of the OLED display panel of this application.
  • This application is directed to the existing OLED display panel manufacturing method and the OLED display panel. Because the pixel driving circuit is difficult to reach the saturation current when the double-gate oxide semiconductor thin film transistor structure is adopted in the pixel driving circuit, the pixel driving voltage is relatively large. The technical problem that further affects the working stability of the OLED display device can be solved by this embodiment.
  • the present application provides a process flow of a method for manufacturing an OLED display panel, the method includes:
  • a glass substrate 201 is provided, a bottom gate metal layer is deposited on the glass substrate 201, and the bottom gate metal layer is patterned through a photomask process to form spaced first bottom gates 202 and light Blocking layer 203.
  • the S10 further includes:
  • the glass substrate 201 is cleaned and baked, a metal film is formed on the glass substrate 201 by sputtering, and a photomask lithography process is used to make the first bottom grids arranged at intervals 202 and the light shielding layer 203; the material of the first bottom gate 202 and the light shielding layer 203 is a stack combination of one or more of molybdenum, aluminum, and copper, as shown in FIG. 2A.
  • the S20 further includes:
  • a vapor deposition method is used to deposit a buffer layer 204 on the first bottom gate 202, the light shielding layer 203 and the glass substrate 201, the material of the buffer layer 204 is silicon nitride, silicon oxide or both The combination is shown in Figure 2B.
  • the S30 further includes:
  • An oxide semiconductor layer (MOS) is deposited on the buffer layer 204 by physical vapor deposition, and the oxide semiconductor layer is patterned through a photomask process to define the active area patterns of the MOS TFT, which are respectively located
  • the material of the first oxide semiconductor layer and the second oxide semiconductor layer is a metal oxide semiconductor such as IGZO or IZTO, and the light shielding layer 203 is configured to shield the second oxide semiconductor
  • the light in the channel region of layer 206 is as shown in FIG. 2C.
  • the S40 further includes:
  • ion doping is performed on the regions on both sides of the first oxide semiconductor layer 205 and the regions on both sides of the second oxide semiconductor layer 206 to make the regions on both sides of the first oxide semiconductor layer 205 and The regions on both sides of the second oxide semiconductor layer 206 are converted into conductors, thereby obtaining a conductive first oxide semiconductor layer 2051 and a conductive second oxide semiconductor layer 2061.
  • a gate insulating layer 207 and a first metal layer 208 are sequentially deposited on the buffer layer 204, and the gate insulating layer 207 and the first metal layer 208 are patterned through a photomask process to obtain The first gate insulating layer 2071, the second gate insulating layer 2072, the first top gate 2081, and the second top gate 2082.
  • the material of the gate insulating layer 207 is silicon nitride, silicon oxide or a combination of the two.
  • the material of the first metal layer 208 is one or a stack combination of molybdenum, aluminum, and copper, as shown in FIG. 2D.
  • the layer 204 is dug to form first via holes 2101 located on both sides of the first oxide semiconductor layer 205, and second via holes 2102 located on both sides of the second oxide semiconductor layer 206.
  • the S50 further includes:
  • An interlayer insulating layer 209 is deposited on the gate insulating layer 207, the first metal layer 208, and the buffer layer 204, and the interlayer insulating layer 209 and the buffer layer 204 are respectively processed through two photomask processes. Perform a hole digging process to form first via holes 2101 located on both sides of the first oxide semiconductor layer 205, and second via holes 2102 located on both sides of the second oxide semiconductor layer 206. Above the first bottom gate 202 and exposing part of the third via 2103 of the first bottom gate 202, the fourth via 2104 which is located above the light shielding layer 203 and exposing part of the light shielding layer 203 .
  • the material of the interlayer insulating layer 209 is silicon nitride, silicon oxide or a combination of the two, as shown in FIG. 2E.
  • S60 Depositing a second metal layer 211 on the interlayer insulating layer 209, and patterning the second metal layer 211 through a photomask process to obtain the two sides of the first top gate 2081.
  • the S60 further includes:
  • a second metal layer 211 is deposited on the interlayer insulating layer 209, and the material of the second metal layer 211 is one or a stack combination of molybdenum, aluminum, and copper;
  • the second metal layer 211 is patterned to obtain a first source 2111 and a first drain 2112 located on both sides of the first top gate 2081, and a first source 2111 and a first drain 2112 located on both sides of the second top gate 2082.
  • first source 2111 and the first drain 2112 are in contact with regions on both sides of the first oxide semiconductor layer 205 through the first via 2101, respectively, and the first source 2111 Contact with the first bottom gate 202 through the third via 2103, the second source 2113 and the second drain 2114 through the second via 2102 and the second oxide, respectively.
  • the areas on both sides of the semiconductor layer 206 are in contact with each other, and the second source electrode 2113 is in contact with the light shielding layer 203 through the fourth via 2104.
  • the electrode 2112 constitutes the source and drain region of the switching TFT
  • the first bottom gate 202 is in contact with the first source 2111
  • the switching TFT forms a double gate driving connection.
  • the switching TFT can utilize the excellent electrical characteristics of the double-gate TFT structure to increase the charging speed of the capacitor and reduce the charging time of the capacitor, thereby improving the display characteristics of the panel.
  • the light shielding layer 203, the buffer layer 204, the second oxide semiconductor layer 206, the second top gate 2082, the second source 2113, and the second drain 2114 The source and drain regions of the driving TFT are formed, the light shielding layer 203 is in contact with the second source 2113, and the driving TFT has a top gate TFT structure, which can effectively reduce parasitic capacitance.
  • the driving TFT connects the light shielding layer 203 to the second source 2113 terminal, and forms a voltage difference between the light shielding layer 203 and the second source 2113 terminal, which can accelerate the device to reach a saturation current. Make the device work more stable.
  • a storage capacitor Cst is formed, as shown in FIG. 2F.
  • a passivation layer 212 a planarization layer 213, a pixel electrode 214, a pixel definition layer 215, an OLED light emitting device 216 and a cathode metal layer 217 are sequentially prepared on the interlayer insulating layer 209 and the second metal layer 211,
  • the pixel electrode 214 is located on the planarization layer 213 and is in contact with the second drain electrode 2114, and finally the OLED display panel is manufactured.
  • the S70 further includes:
  • a passivation layer 212, a planarization layer 213, a pixel electrode 214, a pixel definition layer 215, an OLED light emitting device 216, and a cathode metal layer 217 are sequentially prepared on the interlayer insulating layer 209 and the second metal layer 211.
  • the layer pattern completes the pattern definition; the material of the pixel electrode 214 is ITO (Indium Tin Oxide), and the pixel electrode 214 is located on the planarization layer 213 and is in contact with the second drain electrode 2114.
  • the OLED display panel is shown in Figure 2G.
  • the present application also provides an OLED display panel, including a glass substrate 301, a first bottom gate 302, a light shielding layer 303, a buffer layer 304, a first oxide semiconductor layer 305, and a second oxide semiconductor Layer 306, first gate insulating layer 3071, second gate insulating layer 3072, first top gate 3081, second top gate 3082, interlayer insulating layer 309, first source 3101, first drain 3102 , The second source electrode 3103, the second drain electrode 3104, the passivation layer 311, the planarization layer 312, the pixel electrode 313, the pixel definition layer 314, the OLED light emitting device 315, and the cathode metal layer 316;
  • the interlayer insulating layer 309 and the buffer layer 304 are respectively formed with first via holes located above both sides of the first oxide semiconductor layer 305, and located above both sides of the second oxide semiconductor layer 306.
  • the fourth via hole of the layer 303, the first source electrode 3101 and the first drain electrode 3102 are located on both sides of the first top gate 3081 and pass through the first via hole and the first oxide semiconductor
  • the second source electrode 3103 and the second drain electrode 3104 are located on both sides of the second top gate 3082 and communicate with the second oxide semiconductor layer 306 through the second via hole. Contact, the first source electrode 3101 is in contact with the first bottom gate 302 through the third via hole, and the second source electrode 3103 is in contact with the light shielding layer 303 via the fourth via hole. contact.
  • the first oxide semiconductor layer 305 and the second oxide semiconductor layer 306 are deposited by physical vapor deposition, and the first oxide semiconductor layer 305 and the second oxide semiconductor layer 306
  • the material is IGZO or IZTO.
  • the first bottom gate 302, the light shielding layer 303, the first source 3101, the first drain 3102, the first top gate 3081, the second top gate 3082, the The material of the second source electrode 3103 and the second drain electrode 3104 is one or a stack combination of molybdenum, aluminum, and copper; the material of the buffer layer 304 and the interlayer insulating layer 309 is nitrogen Silicon oxide, silicon oxide or a combination of the two.
  • the electrode 3102 constitutes the source and drain region of the switching TFT
  • the first bottom gate 302 is in contact with the first source 3101
  • the switching TFT forms a dual gate driving connection.
  • the switching TFT can utilize the excellent electrical characteristics of the double-gate TFT structure to increase the charging speed of the capacitor and reduce the charging time of the capacitor, thereby improving the display characteristics of the panel.
  • the light shielding layer 303, the buffer layer 304, the second oxide semiconductor layer 306, the second top gate 3082, the second source 3103, and the second drain 3104 The source and drain regions of the driving TFT are formed.
  • the light shielding layer 303 is in contact with the second source 3103.
  • the driving TFT has a top-gate TFT structure, which can effectively reduce parasitic capacitance.
  • the driving TFT connects the light shielding layer 303 to the second source 3103 terminal, and forms a voltage difference between the light shielding layer 303 and the second source 3103 terminal, which can accelerate the device to reach the saturation current. Make the device work more stable.
  • the drain electrode 3104 adjacent to the second side of the first metal layer 308, and close the second drain 3104 side of the second metal layer 310 and the interlayer insulating layer 309 form a storage capacitor C st;
  • the material of the first metal layer 308 and the second metal layer 310 is a stack combination of one or more of molybdenum, aluminum, and copper.
  • the beneficial effects of the present application are: the method for preparing the OLED display panel and the OLED display panel provided by the present application, in the pixel driving circuit, the switching TFT adopts a double gate structure and the driving TFT adopts the top of the light shielding layer in contact with the source.
  • the gate structure improves the capacitor charging speed, further reduces the capacitor charging time, and further improves the display characteristics of the OLED display panel.

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Abstract

一种OLED显示面板，至少包括玻璃基板、第一底栅极、光遮光层、缓冲层、氧化物半导体层、栅极绝缘层、第一顶栅极、第二顶栅极、层间绝缘层、第一源极、第一漏极、第二源极、第二漏极、钝化层、平坦化层以及像素电极；所述第一源极经由过孔与所述第一底栅极相接触，所述第二源极经由另一过孔与所述光遮挡层相接触。

Description

OLED显示面板的制备方法及OLED显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示面板的制备方法及OLED显示面板。
 背景技术
随着平面显示领域的发展，面板显示越来越趋于高频率、高解析度特性，对面板驱动就提出更高的要求。目前AMOLED(有源矩阵发光二极体面板)显示器的像素驱动电路通常采用TFT（薄膜晶体管）阵列基板，与非晶体相比，其载流子浓度是非晶硅的十倍。现有技术发现，TFT阵列基板采用双栅极氧化物半导体薄膜晶体管相比单栅极氧化物半导体薄膜晶体管具有更优的性能，如电子迁移率高，开态电流较大、亚阈值摆幅更小、阈值电压的稳定性及均匀性更好、栅极偏压及照光稳定性更好等。然而，其不容易达到饱和电流，用作驱动TFT需求的电压较高，不利于实际使用。
综上所述，现有的OLED显示面板的制备方法及OLED显示面板，由于在像素驱动电路中采用双栅极氧化物半导体薄膜晶体管结构时，像素驱动电路难以达到饱和电流，导致像素驱动电压较大，进一步影响了OLED显示装置的工作稳定性。
 技术问题
现有的OLED显示面板的制备方法及OLED显示面板，由于在像素驱动电路中采用双栅极氧化物半导体薄膜晶体管结构时，像素驱动电路难以达到饱和电流，导致像素驱动电压较大，进一步影响了OLED显示装置的工作稳定性。
 技术解决方案
本申请提供一种OLED显示面板的制备方法及OLED显示面板，能够在像素驱动电路中采用双栅极氧化物半导体薄膜晶体管结构时加速达到饱和电流，以解决现有的OLED显示面板的制备方法及OLED显示面板，由于在像素驱动电路中采用双栅极氧化物半导体薄膜晶体管结构时，像素驱动电路难以达到饱和电流，导致像素驱动电压较大，进一步影响了OLED显示装置的工作稳定性的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种OLED显示面板的制备方法，所述方法包括：
S10，提供一玻璃基板，在所述玻璃基板上沉积底栅金属层，通过一道光罩制程对所述底栅金属层进行图案化处理，形成间隔设置的第一底栅极以及光遮挡层；
S20，在所述第一底栅极、所述光遮挡层以及所述玻璃基板上沉积缓冲层；
S30，在所述缓冲层上沉积氧化物半导体层，通过一道光罩制程对所述氧化物半导体层进行图案化处理，得到分别位于所述第一底栅极、所述光遮挡层上方的第一氧化物半导体层、第二氧化物半导体层；
S40，在所述缓冲层上依次沉积栅极绝缘层以及第一金属层，通过一道光罩制程对所述栅极绝缘层以及所述第一金属层进行图案化处理，得到第一栅极绝缘层、第二栅极绝缘层、第一顶栅极以及第二顶栅极；
S50，在所述栅极绝缘层、所述第一金属层以及所述缓冲层上沉积层间绝缘层，分别通过两道光罩制程对所述层间绝缘层以及所述缓冲层进行挖孔处理，形成分别位于所述第一氧化物半导体层两侧上方的第一过孔、位于所述第二氧化物半导体层两侧上方的第二过孔、位于所述第一底栅极上方并暴露出部分所述第一底栅极的第三过孔、位于所述光遮光层上方并暴露出部分所述光遮光层的第四过孔；
S60，在所述层间绝缘层上沉积第二金属层，通过一道光罩制程对所述第二金属层进行图案化处理，分别得到位于所述第一顶栅极两侧的第一源极和第一漏极以及位于所述第二顶栅极两侧的第二源极和第二漏极；
S70，在所述层间绝缘层以及所述第二金属层上依次制备钝化层、平坦化层、像素电极、像素定义层、OLED发光器件以及阴极金属层，所述像素电极位于所述平坦化层上并与所述第二漏极相接触，最后制得所述OLED显示面板。
在本申请实施例所提供的OLED显示面板的制备方法中，所述S30中采用物理气相沉积法沉积所述第一氧化物半导体层以及所述第二氧化物半导体层。
在本申请实施例所提供的OLED显示面板的制备方法中，所述S30中，所述第一氧化物半导体层以及所述第二氧化物半导体层的材料为IGZO或IZTO。
在本申请实施例所提供的OLED显示面板的制备方法中，所述S40还包括：
S401，对所述第一氧化物半导体层的两侧区域和所述第二氧化物半导体层的两侧区域进行离子掺杂，使所述第一氧化物半导体层的两侧区域以及所述第二氧化物半导体层的两侧区域转变为导体。
在本申请实施例所提供的OLED显示面板的制备方法中，所述S60中，所述第一源极与所述第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触，所述第一源极经由所述第三过孔与所述第一底栅极相接触，所述第二源极与所述第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触，所述第二源极经由所述第四过孔与所述光遮挡层相接触。
在本申请实施例所提供的OLED显示面板的制备方法中，所述第一底栅极、所述光遮挡层、所述第一金属层以及所述第二金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
在本申请实施例所提供的OLED显示面板的制备方法中，所述缓冲层以及所述层间绝缘层的材料为氮化硅、氧化硅或二者的组合。
本申请还提供一种OLED显示面板，包括玻璃基板、第一底栅极、光遮光层、缓冲层、第一氧化物半导体层、第二氧化物半导体层、第一栅极绝缘层、第二栅极绝缘层、第一顶栅极、第二顶栅极、层间绝缘层、第一源极、第一漏极、第二源极、第二漏极、钝化层、平坦化层、像素电极、像素定义层、OLED发光器件以及阴极金属层；
其中，所述层间绝缘层以及所述缓冲层上分别形成位于所述第一氧化物半导体层两侧上方的第一过孔、位于所述第二氧化物半导体层两侧上方的第二过孔、位于所述第一底栅极上方并暴露出部分所述第一底栅极的第三过孔以及位于所述光遮光层上方并暴露出部分所述光遮光层的第四过孔，所述第一源极以及所述第一漏极位于所述第一顶栅极两侧并通过所述第一过孔与所述第一氧化物半导体层相接触，所述第二源极以及所述第二漏极位于所述第二顶栅极两侧并通过所述第二过孔与所述第二氧化物半导体层相接触，所述第一源极经由所述第三过孔与所述第一底栅极相接触，所述第二源极经由所述第四过孔与所述光遮挡层相接触。
在本申请实施例所提供的OLED显示面板中，所述第一氧化物半导体层以及所述第二氧化物半导体层经物理气相沉积法沉积而成，所述第一氧化物半导体层以及所述第二氧化物半导体层的材料为IGZO或IZTO。
在本申请实施例所提供的OLED显示面板中，所述第一底栅极、所述光遮挡层、所述第一源极、所述第一漏极、第一顶栅极、第二顶栅极、所述第二源极以及所述第二漏极的材料为钼、铝、铜中的一种或多种的堆栈组合；所述缓冲层以及所述层间绝缘层的材料为氮化硅、氧化硅或二者的组合。
 有益效果
本申请的有益效果为：本申请所提供的OLED显示面板的制备方法及OLED显示面板，在像素驱动电路中将开关TFT采用双栅极结构而驱动TFT采用光遮光层与源极相接触的顶栅结构，提高了电容充电速度，进一步减少了电容充电时间，更进一步提高了OLED显示面板的显示特性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请OLED显示面板的制备方法流程图。
图2A-2G为图1所述TFT阵列基板的制备方法示意图。
图3为本申请OLED显示面板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有的OLED显示面板的制备方法及OLED显示面板，由于在像素驱动电路中采用双栅极氧化物半导体薄膜晶体管结构时，像素驱动电路难以达到饱和电流，导致像素驱动电压较大，进一步影响了OLED显示装置的工作稳定性的技术问题，本实施例能够解决该缺陷。
如图1所示，本申请提供一种OLED显示面板的制备方法流程，所述方法包括：
S10，提供一玻璃基板201，在所述玻璃基板201上沉积底栅金属层，通过一道光罩制程对所述底栅金属层进行图案化处理，形成间隔设置的第一底栅极202以及光遮挡层203。
具体的，所述S10还包括：
首先将所述玻璃基板201进行清洗与烘烤，采用溅射法在所述玻璃基板201上形成一层金属薄膜，以一道光罩微影蚀刻制程来用于制作间隔设置的第一底栅极202与光遮挡层203；所述第一底栅极202与所述光遮挡层203的材料为钼、铝、铜中的一种或多种的堆栈组合，如图2A所示。
S20，在所述第一底栅极202、所述光遮挡层203以及所述玻璃基板201上沉积缓冲层204。
具体的，所述S20还包括：
使用气相沉积法方式在所述第一底栅极202、所述光遮挡层203以及所述玻璃基板201上沉积缓冲层204，所述缓冲层204的材料为氮化硅、氧化硅或二者的组合，如图2B所示。
S30，在所述缓冲层204上沉积氧化物半导体层，通过一道光罩制程对所述氧化物半导体层进行图案化处理，得到分别位于所述第一底栅极202、所述光遮挡层203上方的第一氧化物半导体层205、第二氧化物半导体层206。
具体的，所述S30还包括：
在所述缓冲层204上采用物理气相沉积法沉积氧化物半导体层（MOS），通过一道光罩制程对所述氧化物半导体层进行图案化处理，定义出了MOS TFT主动区图形，得到分别位于所述第一底栅极202、所述光遮挡层203上方的第一氧化物半导体层205、第二氧化物半导体层206。其中，所述第一氧化物半导体层以及所述第二氧化物半导体层的材料为IGZO或IZTO等金属氧化物半导体，所述光遮挡层203被配置来遮挡入射到所述第二氧化物半导体层206的沟道区域的光线，如图2C所示。
S40，在所述缓冲层204上依次沉积栅极绝缘层207以及第一金属层208，通过一道光罩制程对所述栅极绝缘层207以及所述第一金属层208进行图案化处理，得到第一栅极绝缘层2071、第二栅极绝缘层2072、第一顶栅极2081以及第二顶栅极2082。
具体的，所述S40还包括：
首先，对所述第一氧化物半导体层205的两侧区域和所述第二氧化物半导体层206的两侧区域进行离子掺杂，使所述第一氧化物半导体层205的两侧区域以及所述第二氧化物半导体层206的两侧区域转变为导体，得到导体化第一氧化物半导体层2051以及导体化第二氧化物半导体层2061。之后，在所述缓冲层204上依次沉积栅极绝缘层207以及第一金属层208，通过一道光罩制程对所述栅极绝缘层207以及所述第一金属层208进行图案化处理，得到第一栅极绝缘层2071、第二栅极绝缘层2072、第一顶栅极2081以及第二顶栅极2082。其中，所述栅极绝缘层207材料为氮化硅、氧化硅或二者的组合。所述第一金属层208的材料为钼、铝、铜中的一种或多种的堆栈组合，如图2D所示。
S50，在所述栅极绝缘层207、所述第一金属层208以及所述缓冲层204上沉积层间绝缘层209，分别通过两道光罩制程对所述层间绝缘层209以及所述缓冲层204进行挖孔处理，形成分别位于所述第一氧化物半导体层205两侧上方的第一过孔2101、位于所述第二氧化物半导体层206两侧上方的第二过孔2102、位于所述第一底栅极202上方并暴露出部分所述第一底栅极202的第三过孔2103、位于所述光遮光层203上方并暴露出部分所述光遮光层203的第四过孔2104。
具体的，所述S50还包括：
在所述栅极绝缘层207、所述第一金属层208以及所述缓冲层204上沉积层间绝缘层209，分别通过两道光罩制程对所述层间绝缘层209以及所述缓冲层204进行挖孔处理，形成分别位于所述第一氧化物半导体层205两侧上方的第一过孔2101、位于所述第二氧化物半导体层206两侧上方的第二过孔2102、位于所述第一底栅极202上方并暴露出部分所述第一底栅极202的第三过孔2103、位于所述光遮光层203上方并暴露出部分所述光遮光层203的第四过孔2104。其中，所述层间绝缘层209的材料为氮化硅、氧化硅或二者的组合，如图2E所示。
S60，在所述层间绝缘层209上沉积第二金属层211，通过一道光罩制程对所述第二金属层211进行图案化处理，分别得到位于所述第一顶栅极2081两侧的第一源极2111和第一漏极2112以及位于所述第二顶栅极2082两侧的第二源极2113和第二漏极2114。
具体的，所述S60还包括：
在所述层间绝缘层209上沉积第二金属层211，所述第二金属层211的材料为钼、铝、铜中的一种或多种的堆栈组合；之后通过一道光罩制程对所述第二金属层211进行图案化处理，分别得到位于所述第一顶栅极2081两侧的第一源极2111和第一漏极2112以及位于所述第二顶栅极2082两侧的第二源极2113和第二漏极2114。其中，所述第一源极2111与所述第一漏极2112分别经由所述第一过孔2101与所述第一氧化物半导体层205的两侧区域相接触，所述第一源极2111经由所述第三过孔2103与所述第一底栅极202相接触，所述第二源极2113与所述第二漏极2114分别经由所述第二过孔2102与所述第二氧化物半导体层206的两侧区域相接触，所述第二源极2113经由所述第四过孔2104与所述光遮挡层203相接触。
具体的，所述第一底栅极202、所述缓冲层204、所述第一氧化物半导体层205、所述第一顶栅极2081、所述第一源极2111以及所述第一漏极2112构成了开关TFT的源漏极区域，所述第一底栅极202与所述第一源极2111相接触，所述开关TFT形成双栅极驱动连接。所述开关TFT能够利用双栅极TFT结构优异的电学特性，提高电容充电速度，减少电容充电时间，从而提高面板显示特性。
具体的，所述光遮光层203、所述缓冲层204、所述第二氧化物半导体层206、所述第二顶栅极2082、所述第二源极2113以及所述第二漏极2114构成了驱动TFT的源漏极区域，所述光遮光层203与所述第二源极2113相接触，所述驱动TFT 为顶栅TFT结构，能够有效降低寄生电容。所述驱动TFT 将所述光遮光层203接到所述第二源极2113端，通过所述光遮光层203与所述第二源极2113端形成电压差，能使器件加速达到饱和电流，使器件工作更加稳定。
具体的，靠近所述第二漏极2114一侧的部分所述第一金属层208、靠近所述第二漏极2114一侧的部分所述第二金属层211与所述层间绝缘层209形成存储电容Cst，如图2F所示。
S70，在所述层间绝缘层209以及所述第二金属层211上依次制备钝化层212、平坦化层213、像素电极214、像素定义层215、OLED发光器件216以及阴极金属层217，所述像素电极214位于所述平坦化层213上并与所述第二漏极2114相接触，最后制得所述OLED显示面板。
具体的，所述S70还包括：
在所述层间绝缘层209以及所述第二金属层211上依次制备钝化层212、平坦化层213、像素电极214、像素定义层215、OLED发光器件216以及阴极金属层217，对每层图形完成图形定义；所述像素电极214的材料为ITO（氧化铟锡），所述像素电极214位于所述平坦化层213上并与所述第二漏极2114相接触，最后制得所述OLED显示面板，如图2G所示。
如图3所示，本申请还提供一种OLED显示面板，包括玻璃基板301、第一底栅极302、光遮光层303、缓冲层304、第一氧化物半导体层305、第二氧化物半导体层306、第一栅极绝缘层3071、第二栅极绝缘层3072、第一顶栅极3081、第二顶栅极3082、层间绝缘层309、第一源极3101、第一漏极3102、第二源极3103、第二漏极3104、钝化层311、平坦化层312、像素电极313、像素定义层314、OLED发光器件315以及阴极金属层316；
其中，所述层间绝缘层309以及所述缓冲层304上分别形成位于所述第一氧化物半导体层305两侧上方的第一过孔、位于所述第二氧化物半导体层306两侧上方的第二过孔、位于所述第一底栅极302上方并暴露出部分所述第一底栅极302的第三过孔以及位于所述光遮光层303上方并暴露出部分所述光遮光层303的第四过孔，所述第一源极3101以及所述第一漏极3102位于所述第一顶栅极3081两侧并通过所述第一过孔与所述第一氧化物半导体层305相接触，所述第二源极3103以及所述第二漏极3104位于所述第二顶栅极3082两侧并通过所述第二过孔与所述第二氧化物半导体层306相接触，所述第一源极3101经由所述第三过孔与所述第一底栅极302相接触，所述第二源极3103经由所述第四过孔与所述光遮挡层303相接触。
具体的，所述第一氧化物半导体层305以及所述第二氧化物半导体层306经物理气相沉积法沉积而成，所述第一氧化物半导体层305以及所述第二氧化物半导体层306的材料为IGZO或IZTO。
具体的，所述第一底栅极302、所述光遮挡层303、所述第一源极3101、所述第一漏极3102、第一顶栅极3081、第二顶栅极3082、所述第二源极3103以及所述第二漏极3104的材料为钼、铝、铜中的一种或多种的堆栈组合；所述缓冲层304以及所述层间绝缘层309的材料为氮化硅、氧化硅或二者的组合。
具体的，所述第一底栅极302、所述缓冲层304、所述第一氧化物半导体层305、所述第一顶栅极3081、所述第一源极3101以及所述第一漏极3102构成了开关TFT的源漏极区域，所述第一底栅极302与所述第一源极3101相接触，所述开关TFT形成双栅极驱动连接。所述开关TFT能够利用双栅极TFT结构优异的电学特性，提高电容充电速度，减少电容充电时间，从而提高面板显示特性。
具体的，所述光遮光层303、所述缓冲层304、所述第二氧化物半导体层306、所述第二顶栅极3082、所述第二源极3103以及所述第二漏极3104构成了驱动TFT的源漏极区域，所述光遮光层303与所述第二源极3103相接触，所述驱动TFT 为顶栅TFT结构，能够有效降低寄生电容。所述驱动TFT 将所述光遮光层303接到所述第二源极3103端，通过所述光遮光层303与所述第二源极3103端形成电压差，能使器件加速达到饱和电流，使器件工作更加稳定。
具体的，靠近所述第二漏极3104一侧的第一金属层308、靠近所述第二漏极3104一侧的第二金属层310与所述层间绝缘层309形成存储电容C st；所述第一金属层308与所述第二金属层310的材料为钼、铝、铜中的一种或多种的堆栈组合。
本申请的有益效果为：本申请所提供的OLED显示面板的制备方法及OLED显示面板，在像素驱动电路中将开关TFT采用双栅极结构而驱动TFT采用光遮光层与源极相接触的顶栅结构，提高了电容充电速度，进一步减少了电容充电时间，更进一步提高了OLED显示面板的显示特性。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (10)

  1. 一种OLED显示面板的制备方法，其中，所述方法包括：
    S10，提供一玻璃基板，在所述玻璃基板上沉积底栅金属层，通过一道光罩制程对所述底栅金属层进行图案化处理，形成间隔设置的第一底栅极以及光遮挡层；
    S20，在所述第一底栅极、所述光遮挡层以及所述玻璃基板上沉积缓冲层；
    S30，在所述缓冲层上沉积氧化物半导体层，通过一道光罩制程对所述氧化物半导体层进行图案化处理，得到分别位于所述第一底栅极、所述光遮挡层上方的第一氧化物半导体层、第二氧化物半导体层；
    S40，在所述缓冲层上依次沉积栅极绝缘层以及第一金属层，通过一道光罩制程对所述栅极绝缘层以及所述第一金属层进行图案化处理，得到第一栅极绝缘层、第二栅极绝缘层、第一顶栅极以及第二顶栅极；
    S50，在所述栅极绝缘层、所述第一金属层以及所述缓冲层上沉积层间绝缘层，分别通过两道光罩制程对所述层间绝缘层以及所述缓冲层进行挖孔处理，形成分别位于所述第一氧化物半导体层两侧上方的第一过孔、位于所述第二氧化物半导体层两侧上方的第二过孔、位于所述第一底栅极上方并暴露出部分所述第一底栅极的第三过孔、位于所述光遮光层上方并暴露出部分所述光遮光层的第四过孔；
    S60，在所述层间绝缘层上沉积第二金属层，通过一道光罩制程对所述第二金属层进行图案化处理，分别得到位于所述第一顶栅极两侧的第一源极和第一漏极以及位于所述第二顶栅极两侧的第二源极和第二漏极；
    S70，在所述层间绝缘层以及所述第二金属层上依次制备钝化层、平坦化层、像素电极、像素定义层、OLED发光器件以及阴极金属层，所述像素电极位于所述平坦化层上并与所述第二漏极相接触，最后制得所述OLED显示面板。
  2. 根据权利要求1所述的OLED显示面板的制备方法，其中，所述S30中采用物理气相沉积法沉积所述第一氧化物半导体层以及所述第二氧化物半导体层。
  3. 根据权利要求1所述的OLED显示面板的制备方法，其中，所述S30中，所述第一氧化物半导体层以及所述第二氧化物半导体层的材料为IGZO或IZTO。
  4. 根据权利要求1所述的OLED显示面板的制备方法，其中，所述S40还包括：
    S401，对所述第一氧化物半导体层的两侧区域和所述第二氧化物半导体层的两侧区域进行离子掺杂，使所述第一氧化物半导体层的两侧区域以及所述第二氧化物半导体层的两侧区域转变为导体。
  5. 根据权利要求1所述的OLED显示面板的制备方法，其中，所述S60中，所述第一源极与所述第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触，所述第一源极经由所述第三过孔与所述第一底栅极相接触，所述第二源极与所述第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触，所述第二源极经由所述第四过孔与所述光遮挡层相接触。
  6. 根据权利要求1所述的OLED显示面板的制备方法，其中，所述第一底栅极、所述光遮挡层、所述第一金属层以及所述第二金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
  7. 根据权利要求1所述的OLED显示面板的制备方法，其中，所述缓冲层以及所述层间绝缘层的材料为氮化硅、氧化硅或二者的组合。
  8. 一种OLED显示面板，其中，包括：
    玻璃基板；
    第一底栅极，设于所述玻璃基板上；
    光遮光层，设于所述玻璃基板上并与所述第一底栅极间隔设置；
    缓冲层，设于所述玻璃基板上并覆盖所述第一底栅极以及所述光遮光层；
    第一氧化物半导体层，设于所述缓冲层的表面并位于所述第一底栅极的上方；
    第二氧化物半导体层，设于所述缓冲层的表面并与所述第一氧化物半导体层间隔设置，所述第二氧化物半导体层位于所述光遮光层的上方；
    第一栅极绝缘层，设于所述第一氧化物半导体层上；
    第二栅极绝缘层，设于所述第二氧化物半导体层上并与所述第一栅极绝缘层间隔设置；
    第一顶栅极，设于所述第一栅极绝缘层上；
    第二顶栅极，设于所述第二栅极绝缘层上并与所述第一顶栅极间隔设置；
    层间绝缘层，设于所述缓冲层上并覆盖所述第一顶栅极以及所述第二顶栅极，所述层间绝缘层上开设有第一过孔以及第二过孔；
    第一源极以及第一漏极，位于所述第一顶栅极两侧并通过所述第一过孔与所述第一氧化物半导体层相接触；
    第二源极以及第二漏极，位于所述第二顶栅极两侧并通过所述第二过孔与所述第二氧化物半导体层相接触；
    钝化层，设于所述层间绝缘层上并覆盖第一源极、第一漏极、第二源极以及第二漏极；
    平坦化层，设于所述钝化层上；
    像素电极，设于所述平坦化层上并与所述第二漏极相接触；
    像素定义层，设于所述平坦化层上并与所述像素电极的边缘两侧相接触；
    OLED发光器件，设于所述像素电极上；
    阴极金属层，设于所述OLED发光器件上；
    其中，所述层间绝缘层以及所述缓冲层上分别形成位于所述第一底栅极上方并暴露出部分所述第一底栅极的第三过孔以及位于所述光遮光层上方并暴露出部分所述光遮光层的第四过孔，所述第一源极经由所述第三过孔与所述第一底栅极相接触，所述第二源极经由所述第四过孔与所述光遮挡层相接触。
  9. 根据权利要求8所述的OLED显示面板，其中，所述第一氧化物半导体层以及所述第二氧化物半导体层经物理气相沉积法沉积而成，所述第一氧化物半导体层以及所述第二氧化物半导体层的材料为IGZO或IZTO。
  10. 根据权利要求8所述的OLED显示面板的制备方法，其中，所述第一底栅极、所述光遮挡层、所述第一源极、所述第一漏极、第一顶栅极、第二顶栅极、所述第二源极以及所述第二漏极的材料为钼、铝、铜中的一种或多种的堆栈组合；所述缓冲层以及所述层间绝缘层的材料为氮化硅、氧化硅或二者的组合。
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