WO2016165186A1 - 双栅极氧化物半导体tft基板的制作方法及其结构 - Google Patents

双栅极氧化物半导体tft基板的制作方法及其结构 Download PDF

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WO2016165186A1
WO2016165186A1 PCT/CN2015/079476 CN2015079476W WO2016165186A1 WO 2016165186 A1 WO2016165186 A1 WO 2016165186A1 CN 2015079476 W CN2015079476 W CN 2015079476W WO 2016165186 A1 WO2016165186 A1 WO 2016165186A1
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layer
oxide semiconductor
gate
semiconductor layer
bottom gate
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PCT/CN2015/079476
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English (en)
French (fr)
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葛世民
张合静
曾志远
苏智昱
李文辉
石龙强
吕晓文
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深圳市华星光电技术有限公司
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Priority to US14/763,822 priority Critical patent/US9634032B2/en
Publication of WO2016165186A1 publication Critical patent/WO2016165186A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a structure for fabricating a dual gate oxide semiconductor TFT substrate suitable for an OLED.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • TFTs Thin film transistors
  • the TFT may be formed on a glass substrate or a plastic substrate, and is generally used as a switching member and a driving member on a flat display device such as an LCD or an OLED.
  • Oxide semiconductor TFT technology is currently a popular technology.
  • Oxide semiconductors have higher electron mobility, and compared with low temperature polysilicon (LTPS), oxide semiconductors are simple in process and highly compatible with amorphous silicon processes, and can be applied to LCD and OLED planar display devices, and the like. Compatible with high-generation production lines, it can be applied to large, medium and small size displays, and has good application prospects.
  • LTPS low temperature polysilicon
  • a TFT substrate is usually a single-gate oxide semiconductor thin film transistor (Single-Gate TFT).
  • Dual-gate oxide semiconductor thin film transistor has superior performance compared to single-gate oxide semiconductor thin film transistor, such as higher electron mobility, larger on-state current, smaller subthreshold swing, and threshold Better voltage stability and uniformity, better gate bias and illumination stability.
  • a dual gate oxide semiconductor TFT substrate structure suitable for an OLED which is commonly used in the prior art, includes a substrate 100, and a first bottom gate 210 and a second bottom gate 220 disposed on the substrate 100.
  • the gate insulating layer 300 on the substrate 100, the first bottom gate 210, and the second bottom gate 220 is respectively disposed on the gate insulating layer 300 over the first bottom gate 210 and the second bottom gate 220.
  • the first oxide semiconductor layer 410 and the second oxide semiconductor layer 420 are disposed on the first oxide semiconductor layer 410, the second oxide semiconductor layer 420, and the etch barrier layer 500 on the gate insulating layer 300.
  • the first source/drain 610 and the second source/drain 620 disposed on the etch stop layer 500 are disposed on the first source/drain 610, the second source/drain 620, and the etch stop layer 500.
  • Passivation layer 700 on the first source/drain a first top gate 810 disposed on the passivation layer 700, a second top gate 820 disposed on the passivation layer 700 above the second source/drain 620, disposed on the first top gate 810, a second top gate 820, an interlayer insulating layer 900 on the passivation layer 700, a first planar layer 910 disposed on the interlayer insulating layer 900, an ITO anode 1100 disposed on the first planar layer 910, and The ITO anode 1100 and the second planar layer 920 on the first planar layer 910.
  • the etch barrier layer 500 has two first via holes 510 formed corresponding to the first oxide semiconductor layer 410, and two second via holes 520 formed corresponding to the second oxide semiconductor layer 420, the first source/drain The pole 610 and the second source/drain 620 are respectively in contact with the first oxide semiconductor layer 410 and the second oxide semiconductor layer 420 via the first via 510 and the second via 520; the passivation layer 700 and the layer
  • the first insulating layer 900 and the first flat layer 910 are formed with a third via 530 formed over the first source/drain 610, and the ITO anode 1100 is in contact with the first source/drain 610 via the third via 530;
  • the flat layer 920 is formed with a fourth via 540 corresponding to the ITO anode 1100 to expose a portion of the ITO anode 1100.
  • the double-gate oxide semiconductor TFT substrate When the double-gate oxide semiconductor TFT substrate is fabricated, each of the other structural layers except the substrate 100 is patterned by a mask process, and the number of mask processes required is large. Obviously, the existing dual-gate oxide semiconductor TFT substrate suitable for OLED has a complicated structure, and the manufacturing method has a long process flow, low production efficiency, and high process cost.
  • An object of the present invention is to provide a method for fabricating a dual gate oxide semiconductor TFT substrate suitable for an OLED, which can reduce the number of photomask processes, shorten the manufacturing process flow, improve production efficiency, and reduce production cost.
  • Another object of the present invention is to provide a dual-gate oxide semiconductor TFT substrate structure suitable for an OLED, which can reduce the number of photomask processes, shorten the manufacturing process flow, improve production efficiency, and reduce production cost.
  • the present invention first provides a method for fabricating a dual gate oxide semiconductor TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, patterning the first metal layer by a first mask process to form a first bottom gate and a second bottom gate;
  • Step 2 depositing a bottom gate insulating layer on the first bottom gate, the second bottom gate, and the substrate;
  • Step 3 depositing an oxide semiconductor layer on the bottom gate insulating layer, coating a photoresist layer on the oxide semiconductor layer, and performing a second mask process using a halftone mask: first performing the photoresist layer Exposing and developing, obtaining a first photoresist layer, a second photoresist layer, and the first bottom gate respectively covering the oxide semiconductor layer above the first bottom gate and the second bottom gate Far a third photoresist layer covering the oxide semiconductor layer from a side of the second bottom gate; two side regions of the first photoresist layer, two side regions of the second photoresist layer, and a third photoresist The thickness of the layer is smaller than the intermediate portion of the first photoresist layer and the intermediate portion of the second photoresist layer;
  • Step 4 first removing the two side regions of the first photoresist layer, the two side regions of the second photoresist layer, and the third photoresist layer; the intermediate region of the remaining first photoresist layer, and the second light
  • the intermediate portion of the resist layer is a shielding layer, and ion doping is performed on both side regions of the first oxide semiconductor layer, both side regions of the second oxide semiconductor layer, and the third oxide semiconductor layer.
  • Both side regions of the oxide semiconductor layer and both side regions of the second oxide semiconductor layer are converted into conductors, and the third oxide semiconductor layer is converted into an oxide conductor layer; then the middle of the remaining first photoresist layer is removed a region, and an intermediate region of the second photoresist layer;
  • Step 5 depositing a top gate insulating layer on the first oxide semiconductor layer, the second oxide semiconductor layer, the oxide conductor layer, and the bottom gate insulating layer, and simultaneously insulating the top gate through a third mask process
  • the layer and the bottom gate insulating layer are patterned to form a first via hole respectively located above the two side regions of the first oxide semiconductor layer, and a second via hole above the two side regions of the second oxide semiconductor layer a third via located above the oxide conductor layer and a fourth via located between the first bottom gate and the second bottom gate to expose a portion of the first bottom gate;
  • Step 6 Depositing a second metal layer on the top gate insulating layer, and patterning the second and third metal layers by a fourth mask process to obtain the first oxide semiconductor layer. a first top gate on the upper side, a first source and a first drain on both sides of the first top gate, and a second top gate on the second oxide semiconductor layer. a second source and a second drain on both sides of the top gate;
  • the first source and the first drain are respectively in contact with both side regions of the first oxide semiconductor layer via the first via, and the second source and the second drain are respectively via the a second via is in contact with both side regions of the second oxide semiconductor layer, the first source is in contact with the oxide conductor layer via the third via, and the second source is via the second source
  • the fourth via is in contact with the first bottom gate
  • Step 7 depositing a passivation layer on the first top gate, the first source, the first drain, the second top gate, the second source, the second drain, and the top gate insulating layer;
  • Step 8 depositing a flat layer on the passivation layer, and simultaneously patterning the flat layer, the passivation layer, and the top gate insulating layer by a fifth mask process to obtain the oxide guide a fifth via above the bulk layer to expose a portion of the oxide conductor layer to define a shape of the light-emitting layer;
  • the first bottom gate, the first oxide semiconductor layer, the first source, the first drain, and the first top gate constitute a first dual gate TFT, and the second bottom gate and the second oxide
  • the material semiconductor layer, the second source, the second drain, and the second top gate constitute a second double gate TFT; the oxide conductor layer constitutes an anode of the OLED.
  • the step 3 deposits a transparent oxide semiconductor layer by physical vapor deposition.
  • the top gate insulating layer and the bottom gate insulating layer are simultaneously patterned by dry etching.
  • the material of the oxide semiconductor layer is IGZO.
  • the material of the flat layer is an organic photoresist.
  • the first bottom gate, the first top gate, the first source, the first drain, the second bottom gate, the second top gate, the second source, and the second drain are made of molybdenum A stack combination of one or more of titanium, aluminum, and copper.
  • the material of the bottom gate insulating layer and the top gate insulating layer is silicon nitride, silicon oxide, or a combination of the two.
  • the present invention also provides a dual gate oxide semiconductor TFT substrate structure, including a substrate, a first bottom gate and a second bottom gate disposed on the substrate, and the substrate, the first bottom gate, And a bottom gate insulating layer on the second bottom gate, a first oxide semiconductor layer disposed on the bottom gate insulating layer above the first bottom gate, and disposed on the bottom gate insulating layer a second oxide semiconductor layer above the second bottom gate, an oxide conductor layer disposed on the bottom gate insulating layer on a side of the first bottom gate away from the second bottom gate, and disposed on the first a top semiconductor insulating layer on the oxide semiconductor layer, the second oxide semiconductor layer, the oxide conductive layer, and the bottom gate insulating layer, and the first insulating oxide layer above the first oxide semiconductor layer a top gate, a first source disposed on the top gate insulating layer on both sides of the first top gate, and a first drain disposed above the second oxide semiconductor layer a second top gate on the top gate insulating layer is respectively disposed on both sides
  • Two side regions of the first oxide semiconductor layer and two side regions of the second oxide semiconductor layer are ion-doped conductor layers;
  • the top gate insulating layer corresponds to both sides of the first oxide semiconductor layer a first via hole is respectively disposed on the upper side of the second oxide semiconductor layer, and a second via hole is disposed on the upper side of the second oxide semiconductor layer, and a third via hole is disposed above the oxide conductor layer;
  • a fourth via is disposed between the gate insulating layer and the top gate insulating layer corresponding to the first bottom gate and the second bottom gate;
  • the top gate insulating layer, the passivation layer, and the flat layer correspond to the oxide conductor layer Above Have a fifth via;
  • the first source and the first drain are respectively in contact with both side regions of the first oxide semiconductor layer via the first via; the second source and the second drain are respectively via the a second via is in contact with both side regions of the second oxide semiconductor layer; the first source is in contact with the oxide conductor layer via the third via; the second source is via The fourth via is in contact with the first bottom gate; the fifth via exposes a portion of the oxide conductor layer;
  • the first bottom gate, the first oxide semiconductor layer, the first source, the first drain, and the first top gate constitute a first dual gate TFT, and the second bottom gate level and the second oxide
  • the material semiconductor layer, the second source, the second drain, and the second top gate constitute a second double gate TFT; the oxide conductor layer constitutes an anode of the OLED.
  • the material of the first oxide semiconductor layer and the second oxide semiconductor layer is IGZO, and the oxide conductor layer is obtained by ion doping the IGZO semiconductor layer.
  • the material of the flat layer is an organic photoresist; the material of the bottom gate insulating layer and the top gate insulating layer is silicon nitride, silicon oxide, or a combination of the two; the first bottom gate and the first top gate.
  • the material of the pole, the first source, the first drain, the second bottom gate, the second top gate, the second source, and the second drain is one or more of molybdenum, titanium, aluminum, and copper Kind of stack combination.
  • the present invention also provides a dual gate oxide semiconductor TFT substrate structure, including a substrate, a first bottom gate and a second bottom gate disposed on the substrate, and the substrate, the first bottom gate, And a bottom gate insulating layer on the second bottom gate, a first oxide semiconductor layer disposed on the bottom gate insulating layer above the first bottom gate, and disposed on the bottom gate insulating layer a second oxide semiconductor layer above the second bottom gate, an oxide conductor layer disposed on the bottom gate insulating layer on a side of the first bottom gate away from the second bottom gate, and disposed on the first a top semiconductor insulating layer on the oxide semiconductor layer, the second oxide semiconductor layer, the oxide conductive layer, and the bottom gate insulating layer, and the first insulating oxide layer above the first oxide semiconductor layer a top gate, a first source disposed on the top gate insulating layer on both sides of the first top gate, and a first drain disposed above the second oxide semiconductor layer a second top gate on the top gate insulating layer is respectively disposed on both sides
  • Two side regions of the first oxide semiconductor layer and two side regions of the second oxide semiconductor layer are ion-doped conductor layers;
  • the top gate insulating layer corresponds to both sides of the first oxide semiconductor layer a first via hole is respectively disposed on the upper side of the second oxide semiconductor layer, and a second via hole is disposed on the upper side of the second oxide semiconductor layer, and a third via hole is disposed above the oxide conductor layer;
  • a gate insulating layer and a top gate insulating layer corresponding to the first bottom gate and the second bottom gate are provided with a fourth a via hole;
  • the top gate insulating layer, the passivation layer, and the flat layer are respectively provided with a fifth via hole above the oxide conductor layer;
  • the first source and the first drain are respectively in contact with both side regions of the first oxide semiconductor layer via the first via; the second source and the second drain are respectively via the a second via is in contact with both side regions of the second oxide semiconductor layer; the first source is in contact with the oxide conductor layer via the third via; the second source is via The fourth via is in contact with the first bottom gate; the fifth via exposes a portion of the oxide conductor layer;
  • the first bottom gate, the first oxide semiconductor layer, the first source, the first drain, and the first top gate constitute a first dual gate TFT, and the second bottom gate and the second oxide
  • the semiconductor layer, the second source, the second drain, and the second top gate constitute a second double gate TFT;
  • the oxide conductor layer constitutes an anode of the OLED;
  • the material of the first oxide semiconductor layer and the second oxide semiconductor layer is IGZO, and the oxide conductor layer is obtained by ion doping the IGZO semiconductor layer;
  • the material of the flat layer is an organic photoresist;
  • the material of the bottom gate insulating layer and the top gate insulating layer is silicon nitride, silicon oxide, or a combination of the two;
  • the first bottom gate, the first The top gate, the first source, the first drain, the second bottom gate, the second top gate, the second source, and the second drain are made of one of molybdenum, titanium, aluminum, and copper. Or a variety of stack combinations.
  • the present invention provides a method for fabricating a dual-gate oxide semiconductor TFT substrate, which uses a halftone mask to perform a mask process, which can complete the patterning of the oxide semiconductor layer and pass through Ion doping to form an oxide conductor layer, which serves as an anode of the OLED to replace the ITO anode in the prior art; simultaneously patterning the bottom gate insulating layer and the top gate insulating layer through a mask process; a reticle process simultaneously produces a first source, a first drain, a second source, a second drain, a first top gate, and a second top gate; simultaneously through a mask process to the flat layer, The passivation layer and the top gate insulating layer are patterned, and the mask process is reduced to five channels, which shortens the manufacturing process flow, improves production efficiency, and reduces production cost.
  • the invention provides a dual gate oxide semiconductor TFT substrate structure, which is provided as an anode of an OLED by providing an oxide conductor layer, and the first source, the first drain, the second source, the second drain, The first top gate and the second top gate are both disposed on the top gate insulating layer, which can simplify the TFT substrate structure on the one hand, reduce the number of mask processes, shorten the manufacturing process flow, improve production efficiency, and reduce production cost. reduce.
  • FIG. 1 is a schematic cross-sectional view showing a conventional dual gate oxide semiconductor TFT substrate structure suitable for an OLED;
  • FIG. 2 is a flow chart showing a method of fabricating a dual gate oxide semiconductor TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step 1 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating a dual gate oxide semiconductor TFT substrate of the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention.
  • FIG. 9 is a schematic view showing a step 7 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention.
  • FIG. 10 is a schematic view showing the step 8 of the method for fabricating the double gate oxide semiconductor TFT substrate of the present invention and a cross-sectional view showing the structure of the double gate oxide semiconductor TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a dual gate oxide semiconductor TFT substrate suitable for an OLED, comprising the following steps:
  • Step 1 please refer to FIG. 3, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned by a first mask process to form a first bottom gate 21 And the second bottom gate 22.
  • the substrate 1 is a transparent substrate, and preferably, the substrate 1 is a glass substrate.
  • the material of the first metal layer is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu), that is, the first bottom gate 21, and
  • the material of the second bottom gate 22 is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • Step 2 Referring to FIG. 4, a bottom gate insulating layer 31 is deposited on the first bottom gate 21, the second bottom gate 22, and the substrate 1.
  • the material of the bottom gate insulating layer 31 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • Step 3 referring to FIG. 5, an oxide semiconductor layer is deposited on the bottom gate insulating layer 31, a photoresist layer is coated on the oxide semiconductor layer, and a second light is used using a halftone mask (Half-Tone).
  • a mask process first exposing and developing the photoresist layer to obtain a first photoresist layer 41 covering the oxide semiconductor layer above the first bottom gate 21 and the second bottom gate 22, respectively a second photoresist layer 42 and a third photoresist layer 43 covering the oxide semiconductor layer on a side of the first bottom gate 21 away from the second bottom gate 22; the first photoresist layer 41 The thickness of the two sides, the two sides of the second photoresist layer 42 and the third photoresist layer 43 are smaller than the intermediate portion of the first photoresist layer 41 and the intermediate portion of the second photoresist layer 42;
  • the step 3 deposits an oxide semiconductor layer by Physical Vapor Deposition (PVD).
  • PVD Physical Vapor Deposition
  • the material of the oxide semiconductor layer is Indium Gallium Zinc Oxide (IGZO).
  • Step 4 referring to FIG. 6, first removing the two side regions of the first photoresist layer 41, the two side regions of the second photoresist layer 42, and the third photoresist layer 43; the remaining first photoresist layer
  • the intermediate portion of 41 and the intermediate portion of the second photoresist layer 42 are shielding layers, both side regions of the first oxide semiconductor layer 51, both side regions of the second oxide semiconductor layer 52, and third oxidation
  • the semiconductor layer 53 is ion-doped, and both side regions of the first oxide semiconductor layer 51 and both side regions of the second oxide semiconductor layer 52 are converted into conductors, and the third oxide semiconductor layer 53 is converted into The oxide conductor layer 53'; then removes the intermediate portion of the remaining first photoresist layer 41 and the intermediate portion of the second photoresist layer 42.
  • Step 5 depositing a top gate insulating layer 32 on the first oxide semiconductor layer 51, the second oxide semiconductor layer 52, the oxide conductor layer 53', and the bottom gate insulating layer 31,
  • the three reticle processes simultaneously pattern the top gate insulating layer 32 and the bottom gate insulating layer 31 to form first vias 91 respectively located above the two side regions of the first oxide semiconductor layer 51, at the a second via 92 above the two side regions of the second oxide semiconductor layer 52 is located at the A third via 93 above the oxide conductor layer 53' and a fourth via 94 exposing a portion of the first bottom gate 21 between the first bottom gate 21 and the second bottom gate 22 are formed.
  • the top gate insulating layer 32 and the bottom gate insulating layer 31 are simultaneously patterned by dry etching.
  • the material of the top gate insulating layer 32 is silicon nitride, silicon oxide, or a combination of the two.
  • Step 6 referring to FIG. 8, depositing a second and third metal layer on the top gate insulating layer 32, and patterning the second and third metal layers through a fourth mask process, respectively, a first top gate 71 above the first oxide semiconductor layer 51, a first source 81 and a first drain 82 on both sides of the first top gate 71, and the second oxide semiconductor layer 52
  • the upper second top gate 72 and the second source 83 and the second drain 84 are located on opposite sides of the second top gate 72.
  • the first source 81 and the first drain 82 are respectively in contact with both side regions of the first oxide semiconductor layer 51 via the first via 91, and the second source 83 and the second drain
  • the poles 84 are respectively in contact with the two side regions of the second oxide semiconductor layer 52 via the second via 92, and the first source 81 is connected to the oxide conductor layer via the third via 93
  • the second source 83 is in contact with the first bottom gate 21 via the fourth via 94.
  • the material of the second and third metal layers is a stack combination of one or more of molybdenum, titanium, aluminum, and copper, that is, the first top gate 71, the first source 81,
  • the material of the first drain 82, the second top gate 72, the second source 83, and the second drain 84 is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • Step 7 as shown in FIG. 9, the first top gate 71, the first source 81, the first drain 82, the second top gate 72, the second source 83, the second drain 84, and A passivation layer 8 is deposited on the top gate insulating layer 32.
  • Step 8 referring to FIG. 10, a flat layer 9 is deposited on the passivation layer 8, and the flat layer 9, the passivation layer 8, and the top gate insulating layer 32 are simultaneously patterned by a fifth mask process.
  • a fifth via 95 located above the oxide conductor layer 53' is obtained to expose a portion of the oxide conductor layer 53', defining the shape of the light-emitting layer.
  • the first bottom gate 21, the first oxide semiconductor layer 51, the first source 81, the first drain 82, and the first top gate 71 constitute a first dual gate TFT T1
  • the second bottom The gate electrode 22, the second oxide semiconductor layer 52, the second source electrode 83, the second drain electrode 84, and the second top gate electrode 72 constitute a second double gate TFT T2
  • the oxide conductor layer 53' constitutes an OLED The anode.
  • a mask process is performed using a halftone mask to perform patterning of the oxide semiconductor layer and to form an oxide conductor layer 53' by ion doping.
  • the gate insulating layer 32 is patterned; the first top gate 71, the first source 81, the first drain 82, the second top gate 72, the second source 83, and The second drain 84; simultaneously planarizing the flat layer 9, the passivation layer 8, and the top gate insulating layer 32 by a mask process, the mask process is reduced to five, shortening the manufacturing process flow and improving the production Efficiency reduces production costs.
  • the present invention further provides a dual gate oxide semiconductor TFT substrate structure suitable for an OLED, comprising a substrate 1 , a first bottom gate 21 and a second bottom gate 22 disposed on the substrate 1 .
  • a bottom gate insulating layer 31 disposed on the substrate 1, the first bottom gate 21, and the second bottom gate 22, and disposed on the bottom gate insulating layer 31 above the first bottom gate 21 a first oxide semiconductor layer 51, a second oxide semiconductor layer 52 disposed on the bottom gate insulating layer 31 above the second bottom gate 22, and a second oxide semiconductor layer 52 disposed on the bottom gate insulating layer 31.
  • the pole 84 is disposed on the first top gate 71, the first source 81, the first drain 82, the second top gate 72, the second source 83, the second drain 84, and the top gate insulating layer A passivation layer 8 on 32, and a flat
  • Two side regions of the first oxide semiconductor layer 51 and two side regions of the second oxide semiconductor layer 52 are ion-doped conductor layers; the top gate insulating layer 32 corresponds to the first oxide semiconductor layer
  • a first via hole 91 is disposed above each of the two side regions, and a second via hole 92 is respectively disposed above the two side regions of the second oxide semiconductor layer 52, corresponding to the upper portion of the oxide conductor layer 53'.
  • a third via hole 93 is disposed between the bottom gate insulating layer 31 and the top gate insulating layer 32.
  • the top via insulating layer is disposed between the first bottom gate 21 and the second bottom gate 22; 32.
  • the passivation layer 8 and the flat layer 9 are provided with a fifth via hole 95 corresponding to the oxide conductor layer 53'.
  • the first source 81 and the first drain 82 are respectively in contact with both side regions of the first oxide semiconductor layer 51 via the first via 91; the second source 83 and the second drain
  • the poles 84 are in contact with the two side regions of the second oxide semiconductor layer 52 via the second via holes 92; the first source electrode 81 and the oxide conductor layer via the third via hole 93 53' is in contact; the second source 83 is in contact with the first bottom gate 21 via the fourth via 94; the fifth via 95 exposes a portion of the oxide conductor layer 53'.
  • the first bottom gate 21, the first oxide semiconductor layer 51, the first source 81, the first drain 82, and the first top gate 71 constitute a first dual gate TFT T1
  • the second bottom The gate electrode 22, the second oxide semiconductor layer 52, the second source electrode 83, the second drain electrode 84, and the second top gate electrode 72 constitute a second double gate TFT T2
  • the oxide conductor layer 53' constitutes an OLED The anode.
  • the material of the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 is IGZO, and the oxide conductor layer 53' is obtained by ion doping the IGZO semiconductor layer.
  • the material of the flat layer 9 is an organic photoresist; the material of the bottom gate insulating layer 31 and the top gate insulating layer 32 is silicon nitride, silicon oxide, or a combination of the two; the first bottom gate 21, The material of the first top gate 71, the first source 81, the first drain 82, the second bottom gate 22, the second top gate 72, the second source 83, and the second drain 84 is molybdenum, A stack combination of one or more of titanium, aluminum, and copper.
  • the double gate oxide semiconductor TFT substrate structure is provided with an oxide conductor layer 53' as an anode of the OLED, and the oxide conductor layer 53' is lighted with the first and second oxide semiconductor layers 51, 52 a mask manufacturing process; the first top gate 71, the first source 81, the first drain 82, the second top gate 72, the second source 83, and the second drain 84 are all disposed on the top gate insulating layer
  • the TFT substrate structure can be simplified, on the one hand, the number of times of the mask process can be reduced, the manufacturing process flow can be shortened, the production efficiency is improved, and the production cost is reduced.
  • the method for fabricating the dual-gate oxide semiconductor TFT substrate of the present invention uses a halftone mask to perform a mask process, which can complete the patterning of the oxide semiconductor layer and can be doped by ion doping.
  • An oxide conductor layer is used as an anode of the OLED to replace the ITO anode in the prior art; the bottom gate insulating layer and the top gate insulating layer are simultaneously patterned by a mask process; through a mask process Simultaneously preparing a first source, a first drain, a second source, a second drain, a first top gate, and a second top gate; simultaneously through a mask process, the flat layer, the passivation layer, The top gate insulating layer is patterned, and the mask process is reduced to five channels, which shortens the manufacturing process flow, improves production efficiency, and reduces production costs.
  • the dual gate oxide semiconductor TFT substrate structure of the present invention is provided as an anode of the OLED by providing an oxide conductor layer, and the first source, the first drain, the second source, the second drain, and the first top
  • the gate electrode and the second top gate are both disposed on the top gate insulating layer, which can simplify the TFT substrate structure on the one hand, reduce the number of photomask processes, shorten the manufacturing process flow, improve the production efficiency, and reduce the production cost.

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Abstract

一种双栅极氧化物半导体TFT基板的制作方法及其结构。该双栅极氧化物半导体TFT基板的制作方法使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层(53')的图案化、又能够通过离子掺杂制得氧化物导体层(53')；通过一道光罩制程同时对底栅绝缘层(31)与顶栅绝缘层(32)进行图案化处理；通过一道光罩制程同时制得第一顶栅极(71)、第一源极(81)、第一漏极(82)、第二顶栅极(72)、第二源极(83)、及第二漏极(84)；通过一道光罩制程同时对平坦层(9)、钝化层(8)、及顶栅绝缘层(32)进行图案化处理，光罩制程减少至五道，缩短了制作工序流程，提高了生产效率，降低了生产成本。

Description

双栅极氧化物半导体TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种适用于OLED的双栅极氧化物半导体TFT基板的制作方法及其结构。
背景技术
平面显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机发光二极管显示装置(Organic Light Emitting Display，OLED)。
薄膜晶体管(TFT)是平面显示装置的重要组成部分。TFT可形成在玻璃基板或塑料基板上，通常作为开关部件和驱动部件用在诸如LCD、OLED等平面显示装置上。
氧化物半导体TFT技术是当前的热门技术。由于氧化物半导体具有较高的电子迁移率，而且相比低温多晶硅(LTPS)，氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于LCD、OLED平面显示装置等，且与高世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景。
目前，在有源阵列平面显示装置中，TFT基板通常采用单栅极氧化物半导体薄膜晶体管(Single-Gate TFT)。双栅极氧化物半导体薄膜晶体管(Dual-Gate)相比单栅极氧化物半导体薄膜晶体管具有更优的性能，如电子迁移率更高，开态电流较大、亚阈值摆幅更小、阈值电压的稳定性及均匀性更好、栅极偏压及照光稳定性更好等。
在OLED显示装置中，阈值电压的重要性尤为突出，稳定、均匀的阈值电压能够使OLED的显示亮度较均匀，显示品质较高。如图1所示，现有技术中常见的适用于OLED的双栅极氧化物半导体TFT基板结构包括基板100，设于基板100上的第一底栅极210与第二底栅极220，设于基板100、第一底栅极210、与第二底栅极220上的栅极绝缘层300，分别位于第一底栅极210、与第二底栅极220上方设于栅极绝缘层300上的第一氧化物半导体层410、与第二氧化物半导体层420，设于第一氧化物半导体层410、第二氧化物半导体层420、与栅极绝缘层300上的刻蚀阻挡层500，设于刻蚀阻挡层500上的第一源/漏极610、及第二源/漏极620，设于第一源/漏极610、第二源/漏极620及刻蚀阻挡层500上的钝化层700，位于第一源/漏极 610上方设于钝化层700上的第一顶栅极810，位于第二源/漏极620上方设于钝化层700上的第二顶栅极820，设于第一顶栅极810、第二顶栅极820、与钝化层700上的层间绝缘层900，设于层间绝缘层900上的第一平坦层910，设于第一平坦层910上的ITO阳极1100，及设于ITO阳极1100、与第一平坦层910上的第二平坦层920。
所述刻蚀阻挡层500对应第一氧化物半导体层410上方形成有两第一过孔510，对应第二氧化物半导体层420上方形成有两第二过孔520，所述第一源/漏极610、第二源/漏极620分别经由第一过孔510、第二过孔520与第一氧化物半导体层410、第二氧化物半导体层420相接触；所述钝化层700、层间绝缘层900、及第一平坦层910对应第一源/漏极610上方形成有第三过孔530，ITO阳极1100经由第三过孔530与第一源/漏极610相接触；第二平坦层920对应ITO阳极1100上方形成有第四过孔540，暴露出部分ITO阳极1100。
制作上述双栅极氧化物半导体TFT基板时，除基板100外，其它的每一结构层均通过一道光罩制程来进行图案化处理，所需的光罩制程次数较多。显然，现有的适用于OLED的双栅极氧化物半导体TFT基板的结构较复杂，其制作方法的工序流程较长，生产效率较低，制程成本较高。
发明内容
本发明的目的在于提供一种适用于OLED的双栅极氧化物半导体TFT基板的制作方法，能够减少光罩制程次数，缩短制作工序流程，提高生产效率，降低生产成本。
本发明的另一目的在于提供一种适用于OLED的双栅极氧化物半导体TFT基板结构，能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
为实现上述目的，本发明首先提供一种双栅极氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩制程对所述第一金属层进行图案化处理，形成第一底栅极、与第二底栅极；
步骤2、在所述第一底栅极、第二底栅极、及基板上沉积底栅绝缘层；
步骤3、在所述底栅绝缘层上沉积氧化物半导体层，在氧化物半导体层上涂覆光阻层，使用半色调掩膜板进行第二道光罩制程：先对所述光阻层进行曝光、显影，得到分别位于所述第一底栅极、第二底栅极上方覆盖所述氧化物半导体层的第一光阻层、第二光阻层、及位于所述第一底栅极远 离第二底栅极一侧的覆盖所述氧化物半导体层的第三光阻层；所述第一光阻层的两侧区域、第二光阻层的两侧区域、及第三光阻层的厚度小于所述第一光阻层的中间区域、及第二光阻层的中间区域的厚度；
再利用所述第一光阻层、第二光阻层、及第三光阻层对所述氧化物半导体层进行刻蚀，使所述氧化物半导体层图案化，得到分别位于所述第一底栅极、第二底栅极上方的第一氧化物半导体层、第二氧化物半导体层、及位于所述第一底栅极远离第二底栅极一侧的第三氧化物半导体层；
步骤4、先去除所述第一光阻层的两侧区域、第二光阻层的两侧区域、及第三光阻层；以余下的第一光阻层的中间区域、及第二光阻层的中间区域为遮蔽层，对所述第一氧化物半导体层的两侧区域、第二氧化物半导体层的两侧区域、及第三氧化物半导体层进行离子掺杂，使所述第一氧化物半导体层的两侧区域、及第二氧化物半导体层的两侧区域转变为导体，使第三氧化物半导体层转变为氧化物导体层；然后去除余下的第一光阻层的中间区域、及第二光阻层的中间区域；
步骤5、在所述第一氧化物半导体层、第二氧化物半导体层、氧化物导体层、及底栅绝缘层上沉积顶栅绝缘层，通过第三道光罩制程同时对所述顶栅绝缘层与底栅绝缘层进行图案化处理，形成分别位于所述第一氧化物半导体层两侧区域上方的第一过孔、位于所述第二氧化物半导体层两侧区域上方的第二过孔、位于所述氧化物导体层上方的第三过孔、及位于所述第一底栅极与第二底栅极之间暴露出部分第一底栅极的第四过孔；
步骤6、在所述顶栅绝缘层上沉积第二、第三金属层，通过第四道光罩制程对第二、第三金属层进行图案化处理，分别得到位于所述第一氧化物半导体层上方的第一顶栅极、位于所述第一顶栅极两侧的第一源极与第一漏极、位于所述第二氧化物半导体层上方的第二顶栅极、位于所述第二顶栅极两侧的第二源极与第二漏极；
所述第一源极与第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触，所述第二源极与第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第三过孔与所述氧化物导体层相接触，所述第二源极经由所述第四过孔与所述第一底栅极相接触；
步骤7、在所述第一顶栅极、第一源极、第一漏极、第二顶栅极、第二源极、第二漏极、及顶栅绝缘层上沉积钝化层；
步骤8、在所述钝化层上沉积平坦层，通过第五道光罩制程对所述平坦层、钝化层、及顶栅绝缘层同时进行图案化处理，得到位于所述氧化物导 体层上方的第五过孔，以暴露出部分氧化物导体层，定义出发光层的形状；
所述第一底栅极、第一氧化物半导体层、第一源极、第一漏极、及第一顶栅极构成第一双栅极TFT，所述第二底栅极、第二氧化物半导体层、第二源极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述氧化物导体层构成OLED的阳极。
所述步骤3采用物理气相沉积法沉积透明的氧化物半导体层。
所述步骤5采用干法刻蚀对所述顶栅绝缘层与底栅绝缘层同时进行图案化处理。
所述氧化物半导体层的材料为IGZO。
所述平坦层的材料为有机光阻。
所述第一底栅极、第一顶栅极、第一源极、第一漏极、第二底栅极、第二顶栅极、第二源极、及第二漏的的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合。
本发明还提供一种双栅极氧化物半导体TFT基板结构，包括基板、设于所述基板上的第一底栅极与第二底栅极、设于所述基板、第一底栅极、及第二底栅极上的底栅绝缘层、设于所述底栅绝缘层上位于所述第一底栅极上方的第一氧化物半导体层、设于所述底栅绝缘层上位于所述第二底栅极上方的第二氧化物半导体层、设于所述底栅绝缘层上位于第一底栅极远离第二底栅极一侧的氧化物导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述第一氧化物半导体层上方设于所述顶栅绝缘层上的第一顶栅极、分别位于所述第一顶栅极两侧设于所述顶栅绝缘层上的第一源极、及第一漏极、位于所述第二氧化物半导体层上方设于所述顶栅绝缘层上的第二顶栅极、分别位于所述第二顶栅极两侧设于所述顶栅绝缘层上的第二源极、及第二漏极、设于所述第一顶栅极、第一源极、第一漏极、第二顶栅极、第二源极、第二漏极、与顶栅绝缘层上的钝化层、及设于钝化层上的平坦层；
所述第一氧化物半导体层的两侧区域、及第二氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应所述第一氧化物半导体层两侧区域的上方分别设有第一过孔，对应所述第二氧化物半导体层两侧区域的上方分别设有第二过孔，对应所述氧化物导体层上方设有第三过孔；所述底栅绝缘层与顶栅绝缘层对应第一底栅极与第二底栅极之间设有第四过孔；所述顶栅绝缘层、钝化层、及平坦层对应所述氧化物导体层上方设 有第五过孔；
所述第一源极与第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述第二源极与第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触；所述第一源极经由所述第三过孔与所述氧化物导体层相接触；所述第二源极经由所述第四过孔与所述第一底栅极相接触；所述第五过孔暴露出部分氧化物导体层；
所述第一底栅极、第一氧化物半导体层、第一源极、第一漏极、及第一顶栅极构成第一双栅极TFT，所述第二底栅级、第二氧化物半导体层、第二源极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述氧化物导体层构成OLED的阳极。
所述第一氧化物半导体层、与第二氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得。
所述平坦层的材料为有机光阻；所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一底栅极、第一顶栅极、第一源极、第一漏极、第二底栅极、第二顶栅极、第二源极、及第二漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种双栅极氧化物半导体TFT基板结构，包括基板、设于所述基板上的第一底栅极与第二底栅极、设于所述基板、第一底栅极、及第二底栅极上的底栅绝缘层、设于所述底栅绝缘层上位于所述第一底栅极上方的第一氧化物半导体层、设于所述底栅绝缘层上位于所述第二底栅极上方的第二氧化物半导体层、设于所述底栅绝缘层上位于第一底栅极远离第二底栅极一侧的氧化物导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述第一氧化物半导体层上方设于所述顶栅绝缘层上的第一顶栅极、分别位于所述第一顶栅极两侧设于所述顶栅绝缘层上的第一源极、及第一漏极、位于所述第二氧化物半导体层上方设于所述顶栅绝缘层上的第二顶栅极、分别位于所述第二顶栅极两侧设于所述顶栅绝缘层上的第二源极、及第二漏极、设于所述第一顶栅极、第一源极、第一漏极、第二顶栅极、第二源极、第二漏极、与顶栅绝缘层上的钝化层、及设于钝化层上的平坦层；
所述第一氧化物半导体层的两侧区域、及第二氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应所述第一氧化物半导体层两侧区域的上方分别设有第一过孔，对应所述第二氧化物半导体层两侧区域的上方分别设有第二过孔，对应所述氧化物导体层上方设有第三过孔；所述底栅绝缘层与顶栅绝缘层对应第一底栅极与第二底栅极之间设有第四 过孔；所述顶栅绝缘层、钝化层、及平坦层对应所述氧化物导体层上方设有第五过孔；
所述第一源极与第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述第二源极与第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触；所述第一源极经由所述第三过孔与所述氧化物导体层相接触；所述第二源极经由所述第四过孔与所述第一底栅极相接触；所述第五过孔暴露出部分氧化物导体层；
所述第一底栅极、第一氧化物半导体层、第一源极、第一漏极、及第一顶栅极构成第一双栅极TFT，所述第二底栅极、第二氧化物半导体层、第二源极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述氧化物导体层构成OLED的阳极；
其中，所述第一氧化物半导体层、与第二氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得；
其中，所述平坦层的材料为有机光阻；所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一底栅极、第一顶栅极、第一源极、第一漏极、第二底栅极、第二顶栅极、第二源极、及第二漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明提供的一种双栅极氧化物半导体TFT基板的制作方法，使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层，该氧化物导体层作为OLED的阳极替代现有技术中的ITO阳极；通过一道光罩制程同时对底栅绝缘层与顶栅绝缘层进行图案化处理；通过一道光罩制程同时制得第一源极、第一漏极、第二源极、第二漏极、第一顶栅极、与第二顶栅极；通过一道光罩制程同时对平坦层、钝化层、及顶栅绝缘层进行图案化处理，光罩制程减少至五道，缩短了制作工序流程，提高了生产效率，降低了生产成本。本发明提供的一种双栅极氧化物半导体TFT基板结构，通过设置氧化物导体层来作为OLED的阳极，并将第一源极、第一漏极、第二源极、第二漏极、第一顶栅极、与第二顶栅极均设置于顶栅绝缘层上，一方面能够简化TFT基板结构，一方面能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图中，
图1为现有的适用于OLED的双栅极氧化物半导体TFT基板结构的剖面示意图；
图2为本发明双栅极氧化物半导体TFT基板的制作方法的流程图；
图3为本发明双栅极氧化物半导体TFT基板的制作方法的步骤1的示意图；
图4为本发明双栅极氧化物半导体TFT基板的制作方法的步骤2的示意图；
图5为本发明双栅极氧化物半导体TFT基板的制作方法的步骤3的示意图；
图6为本发明双栅极氧化物半导体TFT基板的制作方法的步骤4的示意图；
图7为本发明双栅极氧化物半导体TFT基板的制作方法的步骤5的示意图；
图8为本发明双栅极氧化物半导体TFT基板的制作方法的步骤6的示意图；
图9为本发明双栅极氧化物半导体TFT基板的制作方法的步骤7的示意图；
图10为本发明双栅极氧化物半导体TFT基板的制作方法的步骤8的示意图暨本发明双栅极氧化物半导体TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种适用于OLED的双栅极氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、请参阅图3，提供一基板1，在该基板1上沉积第一金属层，通过第一道光罩制程对所述第一金属层进行图案化处理，形成第一底栅极21、与第二底栅极22。
具体地，所述基板1为透明基板，优选地，所述基板1为玻璃基板。
所述第一金属层的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合，即所述第一底栅极21、及第二底栅极22的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
步骤2、请参阅图4，在所述第一底栅极21、第二底栅极22、及基板1上沉积底栅绝缘层31。
具体地，所述底栅绝缘层31的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
步骤3、请参阅图5，在所述底栅绝缘层31上沉积氧化物半导体层，在氧化物半导体层上涂覆光阻层，使用半色调掩膜板(Half-Tone)进行第二道光罩制程：先对所述光阻层进行曝光、显影，得到分别位于所述第一底栅极21、第二底栅极22上方覆盖所述氧化物半导体层的第一光阻层41、第二光阻层42、及位于所述第一底栅极21远离第二底栅极22一侧的覆盖所述氧化物半导体层的第三光阻层43；所述第一光阻层41的两侧区域、第二光阻层42的两侧区域、及第三光阻层43的厚度小于所述第一光阻层41的中间区域、及第二光阻层42的中间区域的厚度；
再利用所述第一光阻层41、第二光阻层42、及第三光阻层43对所述氧化物半导体层进行刻蚀，使所述氧化物半导体层图案化，得到分别位于所述第一底栅极21、第二底栅极22上方的第一氧化物半导体层51、第二氧化物半导体层52、及位于所述第一底栅极21远离第二底栅极22一侧的第三氧化物半导体层53。
具体地，该步骤3采用物理气相沉积法(Physical Vapor Deposition，PVD)沉积氧化物半导体层。
所述氧化物半导体层的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
步骤4、请参阅图6，先去除所述第一光阻层41的两侧区域、第二光阻层42的两侧区域、及第三光阻层43；以余下的第一光阻层41的中间区域、及第二光阻层42的中间区域为遮蔽层，对所述第一氧化物半导体层51的两侧区域、第二氧化物半导体层52的两侧区域、及第三氧化物半导体层53进行离子掺杂，使所述第一氧化物半导体层51的两侧区域、及第二氧化物半导体层52的两侧区域转变为导体，使第三氧化物半导体层53转变为氧化物导体层53’；然后去除余下的第一光阻层41的中间区域、及第二光阻层42的中间区域。
步骤5、请参阅图7，在所述第一氧化物半导体层51、第二氧化物半导体层52、氧化物导体层53’、及底栅绝缘层31上沉积顶栅绝缘层32，通过第三道光罩制程同时对所述顶栅绝缘层32与底栅绝缘层31进行图案化处理，形成分别位于所述第一氧化物半导体层51两侧区域上方的第一过孔91、位于所述第二氧化物半导体层52两侧区域上方的第二过孔92、位于所 述氧化物导体层53’上方的第三过孔93、及位于所述第一底栅极21与第二底栅极22之间暴露出部分第一底栅极21的第四过孔94。
具体地，该步骤5采用干法刻蚀对所述顶栅绝缘层32与底栅绝缘层31同时进行图案化处理。
所述顶栅绝缘层32的材料为氮化硅、氧化硅、或二者的组合。
步骤6、请参阅图8，在所述顶栅绝缘层32上沉积第二、第三金属层，通过第四道光罩制程对第二、第三金属层进行图案化处理，分别得到位于所述第一氧化物半导体层51上方的第一顶栅极71、位于所述第一顶栅极71两侧的第一源极81与第一漏极82、位于所述第二氧化物半导体层52上方的第二顶栅极72、位于所述第二顶栅极72两侧的第二源极83与第二漏极84。
所述第一源极81与第一漏极82分别经由所述第一过孔91与所述第一氧化物半导体层51的两侧区域相接触，所述第二源极83与第二漏极84分别经由所述第二过孔92与所述第二氧化物半导体层52的两侧区域相接触，所述第一源极81经由所述第三过孔93与所述氧化物导体层53’相接触，所述第二源极83经由所述第四过孔94与所述第一底栅极21相接触。
具体地，所述第二、及第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，即所述第一顶栅极71、第一源极81、第一漏极82、第二顶栅极72、第二源极83、及第二漏极84的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
步骤7、请参阅图9，在所述第一顶栅极71、第一源极81、第一漏极82、第二顶栅极72、第二源极83、第二漏极84、及顶栅绝缘层32上沉积钝化层8。
步骤8、请参阅图10，在所述钝化层8上沉积平坦层9，通过第五道光罩制程对所述平坦层9、钝化层8、及顶栅绝缘层32同时进行图案化处理，得到位于所述氧化物导体层53’上方的第五过孔95，以暴露出部分氧化物导体层53’，定义出发光层的形状。
所述第一底栅极21、第一氧化物半导体层51、第一源极81、第一漏极82、及第一顶栅极71构成第一双栅极TFT T1，所述第二底栅极22、第二氧化物半导体层52、第二源极83、第二漏极84、及第二顶栅极72构成第二双栅极TFT T2；所述氧化物导体层53’构成OLED的阳极。
上述双栅极氧化物半导体TFT基板的制作方法，使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层53’；通过一道光罩制程同时对底栅绝缘层31与顶 栅绝缘层32进行图案化处理；通过一道光罩制程同时制得第一顶栅极71、第一源极81、第一漏极82、第二顶栅极72、第二源极83、及第二漏极84；通过一道光罩制程同时对平坦层9、钝化层8、及顶栅绝缘层32进行图案化处理，光罩制程减少至五道，缩短了制作工序流程，提高了生产效率，降低了生产成本。
请参阅图10，本发明还提供一种适用于OLED的双栅极氧化物半导体TFT基板结构，包括基板1、设于所述基板1上的第一底栅极21与第二底栅极22、设于所述基板1、第一底栅极21、及第二底栅极22上的底栅绝缘层31、设于所述底栅绝缘层31上位于所述第一底栅极21上方的第一氧化物半导体层51、设于所述底栅绝缘层31上位于所述第二底栅极22上方的第二氧化物半导体层52、设于所述底栅绝缘层31上位于第一底栅极21远离第二底栅极22一侧的氧化物导体层53’、设于所述第一氧化物半导体层51、第二氧化物半导体层52、氧化物导体层53’、及底栅绝缘层31上的顶栅绝缘层32、位于所述第一氧化物半导体层51上方设于所述顶栅绝缘层32上的第一顶栅极71、分别位于所述第一顶栅极71两侧设于所述顶栅绝缘层32上的第一源极81、及第一漏极82、位于所述第二氧化物半导体层52上方设于所述顶栅绝缘层32上的第二顶栅极72、分别位于所述第二顶栅极72两侧设于所述顶栅绝缘层32上的第二源极83、及第二漏极84、设于所述第一顶栅极71、第一源极81、第一漏极82、第二顶栅极72、第二源极83、第二漏极84、与顶栅绝缘层32上的钝化层8、及设于钝化层8上的平坦层9。
所述第一氧化物半导体层51的两侧区域、及第二氧化物半导体层52的两侧区域为离子掺杂的导体层；所述顶栅绝缘层32对应所述第一氧化物半导体层51两侧区域的上方分别设有第一过孔91，对应所述第二氧化物半导体层52两侧区域的上方分别设有第二过孔92，对应所述氧化物导体层53’上方设有第三过孔93；所述底栅绝缘层31与顶栅绝缘层32对应第一底栅极21与第二底栅极22之间设有第四过孔94；所述顶栅绝缘层32、钝化层8、及平坦层9对应所述氧化物导体层53’上方设有第五过孔95。
所述第一源极81与第一漏极82分别经由所述第一过孔91与所述第一氧化物半导体层51的两侧区域相接触；所述第二源极83与第二漏极84分别经由所述第二过孔92与所述第二氧化物半导体层52的两侧区域相接触；所述第一源极81经由所述第三过孔93与所述氧化物导体层53’相接触；所述第二源极83经由所述第四过孔94与所述第一底栅极21相接触；所述第五过孔95暴露出部分氧化物导体层53’。
所述第一底栅极21、第一氧化物半导体层51、第一源极81、第一漏极82、及第一顶栅极71构成第一双栅极TFT T1，所述第二底栅极22、第二氧化物半导体层52、第二源极83、第二漏极84、及第二顶栅极72构成第二双栅极TFT T2；所述氧化物导体层53’构成OLED的阳极。
具体地，所述第一氧化物半导体层51、与第二氧化物半导体层52的材料为IGZO，所述氧化物导体层53’通过对IGZO半导体层进行离子掺杂制得。
所述平坦层9的材料为有机光阻；所述底栅绝缘层31及顶栅绝缘层32的材料为氮化硅、氧化硅、或二者的组合；所述第一底栅极21、第一顶栅极71、第一源极81、第一漏极82、第二底栅极22、第二顶栅极72、第二源极83、及第二漏极84的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
上述双栅极氧化物半导体TFT基板结构，设置氧化物导体层53’来作为OLED的阳极，且该氧化物导体层53’与所述第一、第二氧化物半导体层51、52经一道光罩制程制作；将第一顶栅极71、第一源极81、第一漏极82、第二顶栅极72、第二源极83、及第二漏极84均设置于顶栅绝缘层32上，一方面能够简化TFT基板结构，一方面能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
综上所述，本发明的双栅极氧化物半导体TFT基板的制作方法，使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层，该氧化物导体层作为OLED的阳极替代现有技术中的ITO阳极；通过一道光罩制程同时对底栅绝缘层与顶栅绝缘层进行图案化处理；通过一道光罩制程同时制得第一源极、第一漏极、第二源极、第二漏极、第一顶栅极、与第二顶栅极；通过一道光罩制程同时对平坦层、钝化层、及顶栅绝缘层进行图案化处理，光罩制程减少至五道，缩短了制作工序流程，提高了生产效率，降低了生产成本。本发明的双栅极氧化物半导体TFT基板结构，通过设置氧化物导体层来作为OLED的阳极，并将第一源极、第一漏极、第二源极、第二漏极、第一顶栅极、与第二顶栅极均设置于顶栅绝缘层上，一方面能够简化TFT基板结构，一方面能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种双栅极氧化物半导体TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩制程对所述第一金属层进行图案化处理，形成第一底栅极、与第二底栅极；
    步骤2、在所述第一底栅极、第二底栅极、及基板上沉积底栅绝缘层；
    步骤3、在所述底栅绝缘层上沉积氧化物半导体层，在氧化物半导体层上涂覆光阻层，使用半色调掩膜板进行第二道光罩制程：先对所述光阻层进行曝光、显影，得到分别位于所述第一底栅极、第二底栅极上方覆盖所述氧化物半导体层的第一光阻层、第二光阻层、及位于所述第一底栅极远离第二底栅极一侧的覆盖所述氧化物半导体层的第三光阻层；所述第一光阻层的两侧区域、第二光阻层的两侧区域、及第三光阻层的厚度小于所述第一光阻层的中间区域、及第二光阻层的中间区域的厚度；
    再利用所述第一光阻层、第二光阻层、及第三光阻层对所述氧化物半导体层进行刻蚀，使所述氧化物半导体层图案化，得到分别位于所述第一底栅极、第二底栅极上方的第一氧化物半导体层、第二氧化物半导体层、及位于所述第一底栅极远离第二底栅极一侧的第三氧化物半导体层；
    步骤4、先去除所述第一光阻层的两侧区域、第二光阻层的两侧区域、及第三光阻层；以余下的第一光阻层的中间区域、及第二光阻层的中间区域为遮蔽层，对所述第一氧化物半导体层的两侧区域、第二氧化物半导体层的两侧区域、及第三氧化物半导体层进行离子掺杂，使所述第一氧化物半导体层的两侧区域、及第二氧化物半导体层的两侧区域转变为导体，使第三氧化物半导体层转变为氧化物导体层；然后去除余下的第一光阻层的中间区域、及第二光阻层的中间区域；
    步骤5、在所述第一氧化物半导体层、第二氧化物半导体层、氧化物导体层、及底栅绝缘层上沉积顶栅绝缘层，通过第三道光罩制程同时对所述顶栅绝缘层与底栅绝缘层进行图案化处理，形成分别位于所述第一氧化物半导体层两侧区域上方的第一过孔、位于所述第二氧化物半导体层两侧区域上方的第二过孔、位于所述氧化物导体层上方的第三过孔、及位于所述第一底栅极与第二底栅极之间暴露出部分第一底栅极的第四过孔；
    步骤6、在所述顶栅绝缘层上沉积第二、第三金属层，通过第四道光罩制程对第二、第三金属层进行图案化处理，分别得到位于所述第一氧化物半导体层上方的第一顶栅极、位于所述第一顶栅极两侧的第一源极与第一 漏极、位于所述第二氧化物半导体层上方的第二顶栅极、位于所述第二顶栅极两侧的第二源极与第二漏极；
    所述第一源极与第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触，所述第二源极与第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触，所述第一源极经由所述第三过孔与所述氧化物导体层相接触，所述第二源极经由所述第四过孔与所述第一底栅极相接触；
    步骤7、在所述第一顶栅极、第一源极、第一漏极、第二顶栅极、第二源极、第二漏极、及顶栅绝缘层上沉积钝化层；
    步骤8、在所述钝化层上沉积平坦层，通过第五道光罩制程对所述平坦层、钝化层、及顶栅绝缘层同时进行图案化处理，得到位于所述氧化物导体层上方的第五过孔，以暴露出部分氧化物导体层，定义出发光层的形状；
    所述第一底栅极、第一氧化物半导体层、第一源极、第一漏极、及第一顶栅极构成第一双栅极TFT，所述第二底栅极、第二氧化物半导体层、第二源极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述氧化物导体层构成OLED的阳极。
  2. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述步骤3采用物理气相沉积法沉积透明的氧化物半导体层。
  3. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述步骤5采用干法刻蚀对所述顶栅绝缘层与底栅绝缘层同时进行图案化处理。
  4. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述氧化物半导体层的材料为IGZO。
  5. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述平坦层的材料为有机光阻。
  6. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述第一底栅极、第一顶栅极、第一源极、第一漏极、第二底栅极、第二顶栅极、第二源极、及第二漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  7. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述底栅绝缘层、及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  8. 一种双栅极氧化物半导体TFT基板结构，包括基板、设于所述基板上的第一底栅极与第二底栅极、设于所述基板、第一底栅极、及第二底栅 极上的底栅绝缘层、设于所述底栅绝缘层上位于所述第一底栅极上方的第一氧化物半导体层、设于所述底栅绝缘层上位于所述第二底栅极上方的第二氧化物半导体层、设于所述底栅绝缘层上位于第一底栅极远离第二底栅极一侧的氧化物导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述第一氧化物半导体层上方设于所述顶栅绝缘层上的第一顶栅极、分别位于所述第一顶栅极两侧设于所述顶栅绝缘层上的第一源极、及第一漏极、位于所述第二氧化物半导体层上方设于所述顶栅绝缘层上的第二顶栅极、分别位于所述第二顶栅极两侧设于所述顶栅绝缘层上的第二源极、及第二漏极、设于所述第一顶栅极、第一源极、第一漏极、第二顶栅极、第二源极、第二漏极、与顶栅绝缘层上的钝化层、及设于钝化层上的平坦层；
    所述第一氧化物半导体层的两侧区域、及第二氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应所述第一氧化物半导体层两侧区域的上方分别设有第一过孔，对应所述第二氧化物半导体层两侧区域的上方分别设有第二过孔，对应所述氧化物导体层上方设有第三过孔；所述底栅绝缘层与顶栅绝缘层对应第一底栅极与第二底栅极之间设有第四过孔；所述顶栅绝缘层、钝化层、及平坦层对应所述氧化物导体层上方设有第五过孔；
    所述第一源极与第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述第二源极与第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触；所述第一源极经由所述第三过孔与所述氧化物导体层相接触；所述第二源极经由所述第四过孔与所述第一底栅极相接触；所述第五过孔暴露出部分氧化物导体层；
    所述第一底栅极、第一氧化物半导体层、第一源极、第一漏极、及第一顶栅极构成第一双栅极TFT，所述第二底栅极、第二氧化物半导体层、第二源极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述氧化物导体层构成OLED的阳极。
  9. 如权利要求8所述的双栅极氧化物半导体TFT基板结构，其中，所述第一氧化物半导体层、与第二氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得。
  10. 如权利要求8所述的双栅极氧化物半导体TFT基板结构，其中，所述平坦层的材料为有机光阻；所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一底栅极、第一顶栅极、第一源极、第一漏极、第二底栅极、第二顶栅极、第二源极、及第二漏极的材料为钼、 钛、铝、铜中的一种或多种的堆栈组合。
  11. 一种双栅极氧化物半导体TFT基板结构，包括基板、设于所述基板上的第一底栅极与第二底栅极、设于所述基板、第一底栅极、及第二底栅极上的底栅绝缘层、设于所述底栅绝缘层上位于所述第一底栅极上方的第一氧化物半导体层、设于所述底栅绝缘层上位于所述第二底栅极上方的第二氧化物半导体层、设于所述底栅绝缘层上位于第一底栅极远离第二底栅极一侧的氧化物导体层、设于所述第一氧化物半导体层、第二氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述第一氧化物半导体层上方设于所述顶栅绝缘层上的第一顶栅极、分别位于所述第一顶栅极两侧设于所述顶栅绝缘层上的第一源极、及第一漏极、位于所述第二氧化物半导体层上方设于所述顶栅绝缘层上的第二顶栅极、分别位于所述第二顶栅极两侧设于所述顶栅绝缘层上的第二源极、及第二漏极、设于所述第一顶栅极、第一源极、第一漏极、第二顶栅极、第二源极、第二漏极、与顶栅绝缘层上的钝化层、及设于钝化层上的平坦层；
    所述第一氧化物半导体层的两侧区域、及第二氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应所述第一氧化物半导体层两侧区域的上方分别设有第一过孔，对应所述第二氧化物半导体层两侧区域的上方分别设有第二过孔，对应所述氧化物导体层上方设有第三过孔；所述底栅绝缘层与顶栅绝缘层对应第一底栅极与第二底栅极之间设有第四过孔；所述顶栅绝缘层、钝化层、及平坦层对应所述氧化物导体层上方设有第五过孔；
    所述第一源极与第一漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述第二源极与第二漏极分别经由所述第二过孔与所述第二氧化物半导体层的两侧区域相接触；所述第一源极经由所述第三过孔与所述氧化物导体层相接触；所述第二源极经由所述第四过孔与所述第一底栅极相接触；所述第五过孔暴露出部分氧化物导体层；
    所述第一底栅极、第一氧化物半导体层、第一源极、第一漏极、及第一顶栅极构成第一双栅极TFT，所述第二底栅极、第二氧化物半导体层、第二源极、第二漏极、及第二顶栅极构成第二双栅极TFT；所述氧化物导体层构成OLED的阳极；
    其中，所述第一氧化物半导体层、与第二氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得；
    其中，所述平坦层的材料为有机光阻；所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述第一底栅极、第一顶栅极、 第一源极、第一漏极、第二底栅极、第二顶栅极、第二源极、及第二漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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