CN109585297A - 一种显示面板的制作方法和显示面板 - Google Patents

一种显示面板的制作方法和显示面板 Download PDF

Info

Publication number
CN109585297A
CN109585297A CN201811230471.6A CN201811230471A CN109585297A CN 109585297 A CN109585297 A CN 109585297A CN 201811230471 A CN201811230471 A CN 201811230471A CN 109585297 A CN109585297 A CN 109585297A
Authority
CN
China
Prior art keywords
layer
gate insulating
drain electrode
metal
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811230471.6A
Other languages
English (en)
Inventor
杨凤云
卓恩宗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to CN201811230471.6A priority Critical patent/CN109585297A/zh
Priority to US16/349,988 priority patent/US20200185431A1/en
Priority to PCT/CN2018/115609 priority patent/WO2020082459A1/zh
Publication of CN109585297A publication Critical patent/CN109585297A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种显示面板的制作方法和显示面板。一种显示面板的制作方法，包括：在基板上依次沉积一层金属、缓冲材料和氧化物；通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层；在栅极层、源极层和漏极层的上方依次形成钝化层和透明电极层。本发明由于通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层，因而至少减少了一道光罩,节省了曝光显影时间，达到节约成本及提升产能的目的。

Description

一种显示面板的制作方法和显示面板
技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板的制作方法和显示面板。
背景技术
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlightmodule)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
目前IGZO(铟镓锌氧化物)技术已得到广泛的研究及应用，常见的IGZO结构有三种，BCE(back channel etch，背沟道刻蚀)结构，ESL(etch stopper layer，刻蚀阻挡层)结构，Self-aligned Top Gate(自对准的顶栅)结构，其中，BCE结构因是背沟道蚀刻，会产生背沟道损坏,影响TFT器件稳定性，ESL结构可以对背沟道进行保护，但不适合做短沟道结构，并且有较大的寄生电容,顶栅型可以做短沟道结构并且有极小的寄生电容，但光罩会多一道。
发明内容
鉴于现有技术的上述问题，本发明所要解决的技术问题是提供一种减少光罩的显示面板的制作方法和显示面板。
为实现上述目的，本发明提供了一种显示面板的制作方法，包括：
在基板上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；
在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层；
在栅极层、源极层和漏极层的上方依次形成钝化层和透明电极层。
可选的，所述在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层的步骤包括：
在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度高于第二侧部的厚度；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层；
形成的所述源极层和漏极层通过所述氧化物膜层连接。
可选的，所述在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层的步骤包括：
在氧化物膜层上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层；
通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层和栅极层；
在氧化物膜层上通过一道光罩形成包括中部、第一侧部、第二侧部以及镂空部的互联层；
在互联层的上方形成第二层金属，并对第二层金属进行蚀刻得到漏极层和源极层；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间。
可选的，所述在基板上通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层的步骤包括：
在氧化物膜沉积层上方通过一道光罩形成预设图案的光阻层；
对所述氧化物膜沉积层的两侧部不重叠于光阻层的部分进行蚀刻得到氧化物膜层；
对所述缓冲层的两侧部且不重叠于氧化物膜层的部分进行蚀刻得到缓冲层；
对所述第一金属层的两侧部且不重叠于缓冲层的部分进行蚀刻，得到第一金属层；
剥离清除氧化物膜层上方的光阻层。
可选的，所述在栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻得到栅极层、源极层和漏极层的步骤中；
所述栅极层位于与栅极绝缘层中部的上方；
所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上方；
所述源极层、漏极层与栅极层绝缘。
本发明公开了一种显示面板的制作方法，包括：
在基板上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层；
在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度厚于第二侧部的厚度；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层，形成的所述源极层和漏极层通过所述氧化物膜层连接；
所述栅极层位于与栅极绝缘层中部的上方；
所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上方；
所述源极层、漏极层与栅极层绝缘；
在栅极层、源极层和漏极层的上方依次形成钝化层和透明电极层。
本发明还公开了一种显示面板，包括：
第一基板，所述第一基板的上方依次设置有第一金属层、缓冲层和氧化物膜层；
栅极绝缘层、栅极层、源极层和漏极层，形成在氧化物膜层的上方；
钝化层和透明电极层，依次形成在所述第二金属层的上方；
所述第一金属层、缓冲层和氧化物膜层通过同一道光罩制程形成。
可选的，所述栅极绝缘层，位于所述氧化物膜层的上方；
所述栅极绝缘层包括中部、第一侧部和第二侧部，所述中部的厚度大于所述第一侧部和第二侧部的厚度；
所述栅极绝缘层还包括形成在所述中部和第一侧部之间的第一镂空部，以及形成在所述中部和第二侧部之间的第二镂空部；
所述栅极层形成在所述中部上方；
所述源极层形成在所述第一侧部的上方，并通过所述第一镂空部连接于所述氧化物膜层；
所述漏极层形成在所述第二侧部的上方，并通过所述第二镂空部连接于所述氧化物膜层；
所述栅极层、源极层和漏极层由同一金属层，通过同一道光罩制程形成。
可选的，所述栅极绝缘层，位于所述氧化物膜层的中部的上方；
栅极层，位于所述栅极绝缘层的上方；
互联层，位于所述氧化物膜层的上方；
所述互联层包括中部、第一侧部和第二侧部，所述中部和第一侧部之间形成第一镂空部，所述中部和第二侧部之间形成第二镂空部；
所述源极层位于第一侧部和中部的上方，并通过所述第一镂空部连接于所述氧化物膜层；
所述漏极层位于第二侧部和中部的上方，并通过所述第二镂空部连接于所述氧化物膜层；
所述源极层和漏极层由同一金属层，通过同一道光罩制程形成。
可选的，所述栅极层的宽度小于栅极绝缘层中部的宽度，所述源极层、漏极层与栅极层绝缘，所述源极层和漏极层通过氧化物膜层连接。
本方案中，区别于一般性的设计，对顶栅结构进行改进，在基板上依次沉积一层金属、缓冲材料和氧化物,然后通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；相对于将第一金属层、缓冲层和氧化物膜层用不同的光罩分开形成的制程来说，至少减少一道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1a到图1g是本发明实施例一种显示面板七道光罩制程的示意图；
图2a到图2e是本发明实施例一种显示面板五道光罩制程的示意图；
图3a到图3f是本发明实施例一种显示面板六道光罩制程的示意图；
图4是本发明实施例一种显示面板的制作方法流程示意图(1)；
图5是本发明实施例一种显示面板的制作方法流程示意图(2)。
其中，100、显示面板；110、基板；120、第一金属层；130、缓冲层；140、氧化物膜层；150、栅极绝缘层；151、中部；152、第一侧部；153、第二侧部；154、第一镂空部；155、第二镂空部；160、互联层；161、栅极层；162、源极层；163、漏极层；170、钝化层；180、透明电极层。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本发明的示例性实施例的目的。但是本发明可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本发明的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
参考图1a，在玻璃基板110上通过一道光罩的制程形成第一金属层120；
参考图1b，在第一金属层120上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层，通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层120四周的缓冲层130和氧化物膜层140；
参考图1c，在氧化物膜层140上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层，通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层150和栅极层161；
参考图1d，在氧化物膜层140上通过一道光罩形成包括中部151、第一侧部152、第二侧部153以及镂空部的互联层160，所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
参考图1e，在互联层160的上方形成第二层金属，并对第二层金属通过同一道光罩制程进行蚀刻得到漏极层163和源极层162；
参考图1f，在漏极层163和源极层162的上方，通过一道光罩制程蚀刻得到钝化层170；
参考图1g，在钝化层170的上方，通过一道光罩蚀刻得到透明电极层180。
总共使用了七道光罩。
下面结合附图和实施例对本发明作进一步说明。
参考图2a至4所示，本发明实施例公开了一种显示面板100的制作方法，包括：
S41：在基板110上依次沉积一层金属、缓冲材料和氧化物，通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140；
S42：在所述氧化物膜层140上形成栅极绝缘层150、栅极层161、源极层162和漏极层163；
S43：在栅极层161、源极层162和漏极层163的上方依次形成钝化层170和透明电极层180。
其中，基板110为玻璃基板110。
本方案中，对自对准的顶栅结构进行改善在基板110上依次沉积一层金属、缓冲材料和氧化物,然后通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140；相对于将第一金属层120、缓冲层130和氧化物膜层140用不同的光罩分开形成的制程来说，减少一道光罩,由七道光罩变为六道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
其中，一般性的示例方案中，采用了七道光罩制程，而本发明由于通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140，因而，相对减少了一道光罩制程。
本实施例可选的，参考图2b至图2c所示，所述在所述氧化物膜层140上形成栅极绝缘层150、栅极层161、源极层162和漏极层163的步骤包括：
在所述氧化物膜层140上通过半色调掩膜形成包括中部151、第一侧部152、第二侧部153以及镂空部的栅极绝缘层150；
所述栅极绝缘层150的中部151的厚度厚于第一侧部152的厚度，所述栅极绝缘层150的中部151的厚度高于第二侧部153的厚度；
所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163；
形成的所述源极层162和漏极层163通过所述氧化物膜层140连接。
本方案中，在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163；再次减少光罩的使用，进一步减少制程，使得极大提高生产效率,达到节约成本及提升产能的目的。
其中，相对于一般性示例的七道光罩制程，本发明在通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140减少一道光罩制程的基础上，又通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，进一步减少了光罩制程，进一步提高了生产效率，达到了更好的节约成本及提升产能的目的。
本实施例可选的，参考图3b至图3d所示，所述在所述氧化物膜层140上形成栅极绝缘层150、栅极层161、源极层162和漏极层163的步骤包括：
在氧化物膜层140上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层；
通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层150和栅极层161；
在氧化物膜层140上通过一道光罩形成包括中部151、第一侧部152、第二侧部153以及镂空部的互联层160；
在互联层160的上方形成第二层金属，并对第二层金属进行蚀刻得到漏极层163和源极层162；
所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间。
本方案中，先形成栅极层161，再形成源极层162和漏极层163，源极层162和漏极层163是在同一层上形成的，与栅极层161不是再同一层，可以使得源极层162、漏极层163与栅极层161绝缘。在互联层160包括中部151、第一侧部152、第二侧部153以及镂空部，由于镂空部的设置，可以避免短路的问题，保证绝缘，保证了TFT的开关性能。
本实施例可选的，参考图2a所示，所述在基板110上通过同一道光罩蚀刻依次形成第一金属层120、缓冲层130和氧化物膜层140的步骤包括：
在氧化物膜沉积层上方通过一道光罩形成预设图案的光阻层；
对所述氧化物膜沉积层的两侧部不重叠于光阻层的部分进行蚀刻得到氧化物膜层140；
对所述缓冲层130的两侧部且不重叠于氧化物膜层140的部分进行蚀刻得到缓冲层130；
对所述第一金属层120的两侧部且不重叠于缓冲层130的部分进行蚀刻，得到第一金属层120；
剥离清除氧化物膜层140上方的光阻层。
实际上，由于蚀刻的问题，该缓冲层130会略大于氧化物膜层140，该第一金属层120会略大于该缓冲层130，这都是正常情况；甚至，本身就设计使得该缓冲层130大于氧化物膜层140，该第一金属层120大于该缓冲层130也是可以的。
第一金属层120、缓冲层130和氧化物膜层140通过同一光罩，在其上形成一阻挡层，然后便可以通过不同的蚀刻液分别蚀刻得到该第一金属层120、缓冲层130和氧化物膜层140，如此，完成蚀刻之后再清楚该阻挡层，这样做可以进一步的减少了光罩的使用，达到节约成本及提升产能的目的。
本实施例可选的，参考图2c所示，所述在栅极绝缘层150上形成第二层金属，并通过同一道光罩制程蚀刻得到栅极层161、源极层162和漏极层163的步骤中；
所述栅极层161位于与栅极绝缘层150中部151的上方；
所述栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上方；
所述源极层162、漏极层163与栅极层161绝缘。
本方案中，栅极层161位于与栅极绝缘层150中部151重叠的上方，栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上方的，可以减少栅极层161和漏极层163之间产生的寄生电容，以及栅极层161和源极层162之间产生的寄生电容。
作为本发明的另一实施例，参考图2a至图2e以及参考图4所示，公开了一种显示面板100的制作方法，包括：
S51：在基板110上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻依次形成第一金属层120、缓冲层130和氧化物膜层140；
S52：在所述氧化物膜层140上通过半色调掩膜形成包括中部151、第一侧部152、第二侧部153以及镂空部的栅极绝缘层150；
所述栅极绝缘层150的中部151的厚度厚于第一侧部152的厚度，所述栅极绝缘层150的中部151的厚度厚于第二侧部153的厚度；所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
S53：在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，形成的所述源极层162和漏极层163通过所述氧化物膜层140连接；
所述栅极层161位于与栅极绝缘层150中部151的上方；
所述栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上方；
所述源极层162、漏极层163与栅极层161绝缘；
S54：在栅极层161、源极层162和漏极层163的上方依次形成钝化层170和透明电极层180。
本方案中，在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，再次减少光罩的使用，进一步减少制程，使得本发明的方案可以通过五道光罩得到，极大提高生产效率,达到节约成本及提升产能的目的。并且源极层162和漏极层163，同栅极层161之前，由于断差结构和镂空部的设置，可以避免短路的问题，保证绝缘，保证了TFT的开关性能。
其中，相对于一般性示例的七道光罩制程，本发明在通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140减少一道光罩制程的基础上，又通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，进一步减少了光罩制程，进一步提高了生产效率，达到了更好的节约成本及提升产能的目的。
作为本发明的另一实施例，参考图3a所示，公开了一种显示面板100，包括：
第一基板110，所述第一基板110的上方依次设置有第一金属层120、缓冲层130和氧化物膜层140；
栅极绝缘层150、栅极层161、源极层162和漏极层163，形成在氧化物膜层140的上方；
钝化层170和透明电极层180，依次形成在所述第二金属层的上方；
所述第一金属层120、缓冲层130和氧化物膜层140通过同一道光罩制程形成。
本方案中，所述第一金属层120、缓冲层130和氧化物膜层140通过同一道光罩制程形成；相对于将第一金属层120、缓冲层130和氧化物膜层140用不同的光罩分开形成的制程来说，减少一道光罩,由七道光罩变为六道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
本实施例可选的，参考图2c所示，所述栅极绝缘层150，位于所述氧化物膜层140的上方；
所述栅极绝缘层150包括中部151、第一侧部152和第二侧部153，所述中部151的厚度大于所述第一侧部152和第二侧部153的厚度；
所述栅极绝缘层150还包括形成在所述中部151和第一侧部152之间的第一镂空部154，以及形成在所述中部151和第二侧部153之间的第二镂空部155；
所述栅极层161形成在所述中部151上方；
所述源极层162形成在所述第一侧部152的上方，并通过所述第一镂空部154连接于所述氧化物膜层140；
所述漏极层163形成在所述第二侧部153的上方，并通过所述第二镂空部155连接于所述氧化物膜层140；
所述栅极层161、源极层162和漏极层163由同一金属层，通过同一道光罩制程形成。
本方案中，在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，再次减少光罩的使用，进一步减少制程，使得本发明的方案可以通过五道光罩得到，极大提高生产效率,达到节约成本及提升产能的目的。
本实施例可选的，参考图3b至3d所示，所述栅极绝缘层150，位于所述氧化物膜层140的中部151的上方；
栅极层161，位于所述栅极绝缘层150的上方；
互联层160，位于所述氧化物膜层140的上方；
所述互联层160包括中部151、第一侧部152和第二侧部153，所述中部151和第一侧部152之间形成第一镂空部154，所述中部151和第二侧部153之间形成第二镂空部155；
所述源极层162位于第一侧部152和中部151的上方，并通过所述第一镂空部154连接于所述氧化物膜层140；
所述漏极层163位于第二侧部153和中部151的上方，并通过所述第二镂空部155连接于所述氧化物膜层140；
所述源极层162和漏极层163由同一金属层，通过同一道光罩制程形成。
本方案中，先形成栅极层161，再形成源极层162和漏极层163，源极层162和漏极层163是在同一层上形成的，与栅极层161不是再同一层，可以使得源极层162、漏极层163与栅极层161绝缘。在互联层160包括中部151、第一侧部152、第二侧部153以及镂空部，由于镂空部的设置，可以避免短路的问题，保证绝缘，保证了TFT的开关性能。
本实施例可选的，所述栅极层161的宽度小于栅极绝缘层150中部151的宽度，所述源极层162、漏极层163与栅极层161绝缘，所述源极层162和漏极层163通过氧化物膜层140连接。
本方案中，栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上方的，可以减少栅极层161和漏极层163之间产生的寄生电容，以及栅极层161和源极层162之间产生的寄生电容。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本发明的保护范围。
本发明的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-PlaneSwitching，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

1.一种显示面板的制作方法，其特征在于，包括：
在基板上依次沉积一层金属、缓冲材料和氧化物，通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；
在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层；
在栅极层、源极层和漏极层的上方依次形成钝化层和透明电极层。
2.如权利要求1所述的一种显示面板的制作方法，其特征在于，所述在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层的步骤包括：
在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度高于第二侧部的厚度；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层；
形成的所述源极层和漏极层通过所述氧化物膜层连接。
3.如权利要求1所述的一种显示面板的制作方法，其特征在于，所述在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层的步骤包括：
在氧化物膜层上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层；
通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层和栅极层；
在氧化物膜层上通过一道光罩形成包括中部、第一侧部、第二侧部以及镂空部的互联层；
在互联层的上方形成第二层金属，并对第二层金属进行蚀刻得到漏极层和源极层；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间。
4.如权利要求1所述的一种显示面板的制作方法，其特征在于，所述在基板上通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层的步骤包括：
在氧化物膜沉积层上方通过一道光罩形成预设图案的光阻层；
对所述氧化物膜沉积层的两侧部不重叠于光阻层的部分进行蚀刻得到氧化物膜层；
对所述缓冲层的两侧部且不重叠于氧化物膜层的部分进行蚀刻得到缓冲层；
对所述第一金属层的两侧部且不重叠于缓冲层的部分进行蚀刻，得到第一金属层；
剥离清除氧化物膜层上方的光阻层。
5.如权利要求2所述的一种显示面板的制作方法，其特征在于，所述在栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻得到栅极层、源极层和漏极层的步骤中；
所述栅极层位于与栅极绝缘层中部的上方；
所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上方；
所述源极层、漏极层与栅极层绝缘。
6.一种显示面板的制作方法，其特征在于，包括：
在基板上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层；
在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度厚于第二侧部的厚度；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层，形成的所述源极层和漏极层通过所述氧化物膜层连接；
所述栅极层位于与栅极绝缘层中部的上方；
所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上方；
所述源极层、漏极层与栅极层绝缘；
在栅极层、源极层和漏极层的上方依次形成钝化层和透明电极层。
7.一种显示面板，其特征在于，包括：
第一基板，所述第一基板的上方依次设置有第一金属层、缓冲层和氧化物膜层；
栅极绝缘层、栅极层、源极层和漏极层，形成在氧化物膜层的上方；
钝化层和透明电极层，依次形成在所述第二金属层的上方；
所述第一金属层、缓冲层和氧化物膜层通过同一道光罩制程形成。
8.如权利要求7所述的一种显示面板，其特征在于，所述栅极绝缘层，位于所述氧化物膜层的上方；
所述栅极绝缘层包括中部、第一侧部和第二侧部，所述中部的厚度大于所述第一侧部和第二侧部的厚度；
所述栅极绝缘层还包括形成在所述中部和第一侧部之间的第一镂空部，以及形成在所述中部和第二侧部之间的第二镂空部；
所述栅极层形成在所述中部上方；
所述源极层形成在所述第一侧部的上方，并通过所述第一镂空部连接于所述氧化物膜层；
所述漏极层形成在所述第二侧部的上方，并通过所述第二镂空部连接于所述氧化物膜层；
所述栅极层、源极层和漏极层由同一金属层，通过同一道光罩制程形成。
9.如权利要求7所述的一种显示面板，其特征在于，所述栅极绝缘层，位于所述氧化物膜层的中部的上方；
栅极层，位于所述栅极绝缘层的上方；
互联层，位于所述氧化物膜层的上方；
所述互联层包括中部、第一侧部和第二侧部，所述中部和第一侧部之间形成第一镂空部，所述中部和第二侧部之间形成第二镂空部；
所述源极层位于第一侧部和中部的上方，并通过所述第一镂空部连接于所述氧化物膜层；
所述漏极层位于第二侧部和中部的上方，并通过所述第二镂空部连接于所述氧化物膜层；
所述源极层和漏极层由同一金属层，通过同一道光罩制程形成。
10.如权利要求8所述的一种显示面板，其特征在于，所述栅极层的宽度小于栅极绝缘层中部的宽度，所述源极层、漏极层与栅极层绝缘，所述源极层和漏极层通过氧化物膜层连接。
CN201811230471.6A 2018-10-22 2018-10-22 一种显示面板的制作方法和显示面板 Pending CN109585297A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201811230471.6A CN109585297A (zh) 2018-10-22 2018-10-22 一种显示面板的制作方法和显示面板
US16/349,988 US20200185431A1 (en) 2018-10-22 2018-11-15 Display panel preparation method and display panel
PCT/CN2018/115609 WO2020082459A1 (zh) 2018-10-22 2018-11-15 一种显示面板的制作方法和显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811230471.6A CN109585297A (zh) 2018-10-22 2018-10-22 一种显示面板的制作方法和显示面板

Publications (1)

Publication Number Publication Date
CN109585297A true CN109585297A (zh) 2019-04-05

Family

ID=65920335

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811230471.6A Pending CN109585297A (zh) 2018-10-22 2018-10-22 一种显示面板的制作方法和显示面板

Country Status (3)

Country Link
US (1) US20200185431A1 (zh)
CN (1) CN109585297A (zh)
WO (1) WO2020082459A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020082460A1 (zh) * 2018-10-22 2020-04-30 惠科股份有限公司 一种显示面板的制作方法和显示面板
CN112530810A (zh) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 一种开关元件的制备方法、阵列基板的制备方法和显示面板
WO2021114398A1 (zh) * 2019-12-11 2021-06-17 深圳市华星光电半导体显示技术有限公司 显示面板的制造方法及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4887646B2 (ja) * 2005-03-31 2012-02-29 凸版印刷株式会社 薄膜トランジスタ装置及びその製造方法並びに薄膜トランジスタアレイ及び薄膜トランジスタディスプレイ
CN102683208A (zh) * 2011-03-10 2012-09-19 中国科学院宁波材料技术与工程研究所 一种钇铝氧复合氧化物高k介质薄膜晶体管的制备方法
CN103050626A (zh) * 2012-12-07 2013-04-17 上海交通大学 一种溶液法电解质薄膜晶体管及其制备方法
CN103219391A (zh) * 2013-04-07 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN104409512A (zh) * 2014-11-11 2015-03-11 深圳市华星光电技术有限公司 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法
CN106298883A (zh) * 2015-06-04 2017-01-04 昆山工研院新型平板显示技术中心有限公司 一种薄膜晶体管及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5336102B2 (ja) * 2008-04-03 2013-11-06 三菱電機株式会社 Ｔｆｔ基板
KR101953215B1 (ko) * 2012-10-05 2019-03-04 삼성디스플레이 주식회사 식각 조성물, 금속 배선 및 표시 기판의 제조방법
KR102442616B1 (ko) * 2015-04-08 2022-09-14 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN104752343B (zh) * 2015-04-14 2017-07-28 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构
CN105702687A (zh) * 2016-04-13 2016-06-22 武汉华星光电技术有限公司 Tft基板及其制作方法
CN106847744B (zh) * 2017-02-20 2020-10-02 合肥京东方光电科技有限公司 阵列基板的制备方法、阵列基板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4887646B2 (ja) * 2005-03-31 2012-02-29 凸版印刷株式会社 薄膜トランジスタ装置及びその製造方法並びに薄膜トランジスタアレイ及び薄膜トランジスタディスプレイ
CN102683208A (zh) * 2011-03-10 2012-09-19 中国科学院宁波材料技术与工程研究所 一种钇铝氧复合氧化物高k介质薄膜晶体管的制备方法
CN103050626A (zh) * 2012-12-07 2013-04-17 上海交通大学 一种溶液法电解质薄膜晶体管及其制备方法
CN103219391A (zh) * 2013-04-07 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN104409512A (zh) * 2014-11-11 2015-03-11 深圳市华星光电技术有限公司 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法
CN106298883A (zh) * 2015-06-04 2017-01-04 昆山工研院新型平板显示技术中心有限公司 一种薄膜晶体管及其制备方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020082460A1 (zh) * 2018-10-22 2020-04-30 惠科股份有限公司 一种显示面板的制作方法和显示面板
US11424348B2 (en) 2018-10-22 2022-08-23 HKC Corporation Limited Display panel preparation method and display panel
WO2021114398A1 (zh) * 2019-12-11 2021-06-17 深圳市华星光电半导体显示技术有限公司 显示面板的制造方法及显示面板
CN112530810A (zh) * 2020-11-24 2021-03-19 北海惠科光电技术有限公司 一种开关元件的制备方法、阵列基板的制备方法和显示面板
CN112530810B (zh) * 2020-11-24 2023-06-16 北海惠科光电技术有限公司 一种开关元件的制备方法、阵列基板的制备方法和显示面板

Also Published As

Publication number Publication date
US20200185431A1 (en) 2020-06-11
WO2020082459A1 (zh) 2020-04-30

Similar Documents

Publication Publication Date Title
US8760595B2 (en) Array substrate for fringe field switching mode liquid crystal display device and method for fabricating the same
CN105629612B (zh) 薄膜晶体管阵列基板及其制作方法
CN109585297A (zh) 一种显示面板的制作方法和显示面板
CN106483726B (zh) 薄膜晶体管阵列基板及制作方法和液晶显示面板
KR101096336B1 (ko) 에프에프에스 모드 액정표시장치 및 그 제조방법
CN108110010A (zh) 阵列基板及其制备方法、触控显示面板
US20060139552A1 (en) Liquid crystal display device and fabricating method thereof
CN102088025A (zh) 薄膜晶体管基板及其制造方法
US10495932B2 (en) Display substrate and display device comprising first and second sub-pixel electrodes each having a trunk portion and an opening structure and first and second light-shielding portions
CN103163701A (zh) 网状公共电极结构液晶显示器件及其制造方法
CN103730511B (zh) 薄膜晶体管及其制造方法、阵列基板、显示装置
CN106601754A (zh) 一种薄膜晶体管阵列基板及其制备方法、显示装置
CN103346159B (zh) 一种阵列基板及其制造方法、显示装置
CN102566178A (zh) 一种薄膜晶体管液晶显示器、基板及制造方法
CN109585298A (zh) 一种显示面板的制作方法和显示面板
CN109524357A (zh) 一种阵列基板的制程方法和显示面板
KR20110035531A (ko) 액정표시장치 및 그 제조 방법
KR100614323B1 (ko) 액정표시장치 및 그 제조방법
CN104617039A (zh) 阵列基板及其制作方法、显示装置
TWI490615B (zh) 用於邊緣電場切換模式液晶顯示裝置的陣列基板及其製造方法
CN101373299A (zh) Ffs 薄膜晶体管液晶显示器像素结构及其制造方法
CN103199112A (zh) 一种阵列基板及其制备方法和显示面板
CN106206615A (zh) 一种阵列基板及其制作方法、液晶显示面板
CN106024908A (zh) 一种薄膜晶体管制作方法和阵列基板制作方法
CN109637923A (zh) 一种显示基板及其制作方法和显示装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190405

RJ01 Rejection of invention patent application after publication