WO2020082460A1 - 一种显示面板的制作方法和显示面板 - Google Patents

一种显示面板的制作方法和显示面板 Download PDF

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Publication number
WO2020082460A1
WO2020082460A1 PCT/CN2018/115610 CN2018115610W WO2020082460A1 WO 2020082460 A1 WO2020082460 A1 WO 2020082460A1 CN 2018115610 W CN2018115610 W CN 2018115610W WO 2020082460 A1 WO2020082460 A1 WO 2020082460A1
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Prior art keywords
layer
metal
gate
oxide film
display panel
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PCT/CN2018/115610
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English (en)
French (fr)
Inventor
杨凤云
卓恩宗
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惠科股份有限公司
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Priority to US16/327,306 priority Critical patent/US11424348B2/en
Publication of WO2020082460A1 publication Critical patent/WO2020082460A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66515—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned selective metal deposition simultaneously on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the present application relates to the field of display technology, and in particular, to a method for manufacturing a display panel and a display panel.
  • liquid crystal displays which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light of the backlight module to generate a picture.
  • IGZO indium gallium zinc oxide
  • BCE back channel etching
  • ESL etch stopper layer, etching barrier layer
  • Self-aligned Top Gate self-aligned top gate
  • the ESL structure can protect the back channel
  • it is not suitable for short channel structure and has a large parasitic capacitance.
  • the top gate type can be used for short channel structure and has a small parasitic capacitance, but the photomask will have one more.
  • the purpose of this application is to provide a manufacturing method of a display panel and a display panel, so as to reduce the photomask manufacturing process of the display panel.
  • the present application provides a method for manufacturing a display panel, including:
  • a passivation layer and a transparent electrode layer are sequentially formed on the gate layer, source layer and drain layer.
  • the gate insulating layer is formed on the oxide film layer through a half-tone mask, a second layer of metal is formed on the gate insulating layer, and the second layer of metal is etched through the same photomask process
  • the steps of obtaining the gate layer and the source and drain layers connected by the oxide film layer include:
  • a gate insulating layer including a middle part, a first side part, a second side part and a hollow part on the oxide film layer through a half-tone mask, the middle part of the gate insulating layer is higher than the first side part And the height of the second side, the cutouts are formed between the middle and the first side, and between the middle and the second side, respectively;
  • the formed source and drain layers are insulated from the gate layer.
  • the gate layer is on the middle and the gate The width of the layer is smaller than the width of the middle.
  • the steps of sequentially forming the first metal layer, the buffer layer, and the oxide film layer on the substrate include:
  • the buffer deposition layer and the oxide film deposition layer are etched through the same mask process to obtain the buffer layer and the oxide film layer covering the first metal layer.
  • the sequentially forming the first metal layer, the buffer layer, and the oxide film layer on the substrate include:
  • the widths of the first metal layer, the buffer layer and the oxide film layer are equivalent.
  • This application discloses a method for manufacturing a display panel, including:
  • a gate insulating layer including a middle part, a first side part, a second side part and a hollow part on the oxide film layer through a half-tone mask, the middle part of the gate insulating layer is higher than the first side part And the height of the second side, the cutouts are formed between the middle and the first side, and between the middle and the second side, respectively;
  • the formed source and drain layers are insulated from the gate layer
  • the gate layer is located on the middle part, and the width of the gate layer is smaller than the width of the middle part;
  • a passivation layer and a transparent electrode layer are sequentially formed on the gate layer, source layer and drain layer.
  • the application also discloses a display panel, including:
  • a passivation layer and a transparent electrode layer are sequentially formed on the gate layer, source layer and drain layer;
  • the source layer and the drain layer are insulated from the gate layer; the source layer and the drain layer are connected through the oxide film layer;
  • the gate layer, the source layer and the drain layer are formed by the same mask process.
  • the gate insulating layer includes a middle portion, a first side portion, and a second side portion, and the thickness of the middle portion is greater than the thickness of the first side portion and the second side portion;
  • the gate insulating layer further includes a first hollow portion formed between the middle portion and the first side portion, and a second hollow portion formed between the middle portion and the second side portion;
  • the gate layer is formed on the middle
  • the source layer is formed on the first side portion, and is connected to the oxide film layer through the first hollow portion;
  • the drain layer is formed on the second side portion, and is connected to the oxide film layer through the second hollow portion;
  • the gate layer, the source layer and the drain layer are formed of the same metal layer through the same mask process.
  • the gate layer is located on the middle portion, and the width of the gate layer is smaller than the width of the middle portion.
  • the two sides of the first metal layer are hollowed out, and the buffer layer covers the upper surface of the first metal layer and the hollowed-out parts on both sides.
  • the self-aligned top gate structure is improved, and a half-tone mask is used to form a gate insulating layer.
  • a layer of metal is sputtered on the gate insulating layer as a second layer of metal and passes through the same mask During the etching process, the gate layer, the source layer and the drain layer can be formed at the same time. From seven masks to six masks, one mask is reduced, one exposure and development time is saved, and the purpose of saving costs and increasing productivity is achieved.
  • 1a to 1g are schematic diagrams of a manufacturing process of seven masks for a display panel according to an embodiment of the present application;
  • FIGS. 2a to 2f are schematic diagrams of a manufacturing process of six masks for a display panel according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a manufacturing process of six masks for a display panel according to an embodiment of the present application (2);
  • FIG. 4 is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of the application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • the term “including” and any variations thereof are intended to cover non-exclusive inclusions.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • a first metal layer 120 is formed on the glass substrate 110 through a mask process
  • a buffer deposition layer is deposited on the first metal layer 120, and an oxide film deposition layer is deposited on the buffer deposition layer, and the buffer deposition layer and the oxide film deposition layer are etched through the same photomask process to obtain a covering A buffer layer 130 and an oxide film layer 140 around a metal layer 120;
  • a gate insulating deposit layer is deposited on the oxide film layer 140, and a gate metal layer is deposited on the gate insulating deposit layer, and the gate insulating deposit layer and the gate metal layer are formed through a photomask process Etching to form the gate insulating layer 150 and the gate layer 161;
  • an interconnect layer including a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion is formed on the oxide film layer 140 by a mask, the hollow portion is formed on the middle portion 151 and the first side Part 152, and between the middle part 151 and the second side part 153;
  • a second layer of metal is formed on the interconnect layer, and the second layer of metal is etched through the same photomask process to obtain the drain layer 163 and the source layer 162;
  • a passivation layer 170 is obtained by etching through a photomask process
  • a transparent electrode layer 180 is obtained by etching with a photomask.
  • an embodiment of the present application discloses a method for manufacturing a display panel 100, including:
  • a second layer of metal is formed on the gate insulating layer 150, and the second layer of metal is etched through the same photomask process to obtain the gate layer 161, and the source layer 162 and the drain layer 163 connected by the oxide film layer 140 ;
  • a passivation layer 170 and a transparent electrode layer 180 are sequentially formed on the gate layer 161, the source layer 162, and the drain layer 163.
  • the substrate 110 is a glass substrate 110.
  • the self-aligned top gate structure is improved, and a gate insulating layer 150 is formed by using a halftone mask.
  • a layer of metal is sputtered on the gate insulating layer 150 as a second layer of metal
  • the etching process of the photo mask process can form the gate layer 161, the source layer 162 and the drain layer 163 at the same time, from seven masks to six masks, reducing one mask, saving one exposure and developing time, saving costs and The purpose of increasing production capacity.
  • the gate insulating layer 150 is formed on the oxide film layer 140 through a halftone mask, and a second layer of metal is formed on the gate insulating layer 150 And the second layer of metal is etched through the same photomask process to obtain the gate layer 161, and the source layer 162 and the drain layer 163 connected through the oxide film layer 140 include:
  • a gate insulating layer 150 including a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion is formed on the oxide film layer 140 through a half-tone mask.
  • the middle portion 151 of the gate insulating layer 150 The height is higher than the height of the first side portion 152 and the second side portion 153, and the hollow portion is formed between the middle portion 151 and the first side portion 152, and between the middle portion 151 and the second side portion 153, the first side The height of the portion 152 and the second side portion 153 are equivalent;
  • the source layer 162 on the first side 152 of the gate insulating layer 150 and the drain layer 163 on the second side 153 are obtained;
  • the formed source layer 162 and drain layer 163 are insulated from the gate layer 161.
  • the gate insulating layer 150 before the source layer 162, the gate layer 161, and the drain layer 163 are formed, the gate insulating layer 150 includes a middle portion 151, a first side portion 152, and a second side portion 153, the gate insulating layer 150
  • the height of the middle portion 151 is higher than the heights of the first side portion 152 and the second side portion 153, so that there is a step difference between the middle portion 151 of the gate insulating layer 150 and the first side portion 152 and the second side portion 153 to avoid short circuit
  • the hollow portion is formed between the middle portion 151 and the first side portion 152, and the middle portion 151 and the second side portion 153, due to the provision of the hollow portion, can avoid the short circuit situation, ensure insulation, guarantee TFT switching performance.
  • the drain layer 163 extends from one side of the middle portion 151 of the gate insulating layer 150 away from the gate layer 161, and the source layer 162 moves away from the gate layer from the other side of the middle portion 151 of the gate insulating layer 150 161 direction.
  • the gate layer 161 in the step of etching the second layer of metal through the same photomask process to obtain the gate layer 161 on the middle portion 151 of the gate insulating layer 150, the gate layer 161 is located on the middle portion 151 Above, and the width of the gate layer 161 is smaller than the width of the middle portion 151.
  • the gate layer 161 is located on the middle portion 151 of the gate insulating layer 150, the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, and the source layer 162 and the drain layer 163 are respectively located on the gate On both sides of the electrode insulating layer 150, the parasitic capacitance generated between the gate layer 161 and the drain layer 163 and the parasitic capacitance generated between the gate layer 161 and the source layer 162 can be reduced.
  • the steps of sequentially forming the first metal layer 120, the buffer layer 130, and the oxide film layer 140 on the substrate 110 include:
  • the buffer deposition layer and the oxide film deposition layer are etched through the same mask process to obtain the buffer layer 130 and the oxide film layer 140 covering the first metal layer 120.
  • a buffer layer 130 is formed on the first metal layer 120.
  • the buffer layer 130 covers the periphery of the first metal layer 120. Compared to when the buffer layer 130 does not completely cover the first metal layer 120, the buffer layer 130 Covering the periphery of the first metal layer 120 can provide better insulation.
  • the sequentially forming the first metal layer 120, the buffer layer 130, and the oxide film layer 140 on the substrate 110 include:
  • the widths of the first metal layer 120, the buffer layer 130 and the oxide film layer 140 are equivalent, which means that the width difference between the two is within a preset threshold, that is, the widths of the two are considered to be equivalent; in fact, The lower layer will be slightly larger than the upper layer.
  • the buffer layer 130 will be slightly larger than the oxide film layer 140, and the first metal layer 120 will be slightly larger than the buffer layer 130, which is normal; even, the design itself makes the buffer layer 130 is larger than the oxide film layer 140, and the first metal layer 120 may be larger than the buffer layer 130.
  • the widths of the first metal layer 120, the buffer layer 130 and the oxide film layer 140 are the same, and the etching is convenient during the manufacturing process.
  • a method for manufacturing the display panel 100 including:
  • S42 deposit a buffer deposit layer on the first metal layer 120, and deposit an oxide film deposit layer on the buffer deposit layer;
  • the height of the middle portion 151 is higher than the heights of the first side portion 152 and the second side portion 153, and the hollow portions are formed between the middle portion 151 and the first side portion 152, and between the middle portion 151 and the second side portion 153, respectively;
  • the source layer 162 on the first side 152 of the gate insulating layer 150 and the drain layer 163 on the second side 153 are obtained;
  • the formed source layer 162 and drain layer 163 are insulated from the gate layer 161;
  • the gate layer 161 is located on the middle portion 151, and the width of the gate layer 161 is smaller than the width of the middle portion 151;
  • a passivation layer 170 and a transparent electrode layer 180 are sequentially formed on the gate layer 161, the source layer 162, and the drain layer 163.
  • the self-aligned top gate structure is improved, and a half-tone mask is used to form a gate insulating layer 150 with a middle high side and a low side and a hollow part formed between the middle part 151 and the two sides.
  • a half-tone mask is used to form a gate insulating layer 150 with a middle high side and a low side and a hollow part formed between the middle part 151 and the two sides.
  • Sputtering a layer of metal on the gate insulating layer 150 as the second layer of metal, and etching through the same mask process the gate layer 161, the source layer 162 and the drain layer 163 can be formed at the same time, reducing one mask, by The seven masks are changed to six masks, saving one exposure and developing time, saving cost and increasing productivity; and the source layer 162 and the drain layer 163 are the same as the gate layer 161 before due to the break structure and hollowing
  • the setting of the part can avoid short circuit, ensure insulation, and ensure the switching performance of the TFT.
  • a display panel 100 including:
  • the gate insulating layer 150 is located on the oxide film layer 140;
  • the gate layer 161 is formed in the middle portion 151 on the gate insulating layer 150;
  • the source layer 162 and the drain layer 163 are formed on the gate insulating layer 150 and located on both sides of the gate layer 161;
  • the passivation layer 170 and the transparent electrode layer 180 are sequentially formed on the gate layer 161, the source layer 162, and the drain layer 163;
  • the source layer 162 and the drain layer 163 are insulated from the gate layer 161; the source layer 162 and the drain layer 163 are connected through the oxide film layer 140;
  • the gate layer 161, the source layer 162 and the drain layer 163 are formed by the same photomask process.
  • the self-aligned top gate structure is improved.
  • a layer of metal is sputtered on the gate insulating layer 150 as a second layer of metal, and the gate layer 161 can be formed simultaneously by etching through the same photomask process.
  • the source layer 162 and the drain layer 163, the gate layer 161, the source layer 162, and the drain layer 163 can be completed together on the structure of the gate insulating layer 150 formed by a half-tone mask, reducing one mask, by seven light
  • the mask is changed to six masks, saving one exposure and developing time, achieving the purpose of saving cost and increasing productivity.
  • the gate insulating layer 150 includes a middle portion 151, a first side portion 152, and a second side portion 153, the thickness of the middle portion 151 is greater than that of the first side portion 152 and the second side portion 153 thickness;
  • the gate insulating layer 150 further includes a first hollow portion 154 formed between the middle portion 151 and the first side portion 152, and a second hollow portion formed between the middle portion 151 and the second side portion 153 155;
  • the gate layer 161 is formed on the middle portion 151;
  • the source layer 162 is formed on the first side portion 152 and connected to the oxide film layer 140 through the first hollow portion 154;
  • the drain layer 163 is formed on the second side portion 153, and is connected to the oxide film layer 140 through the second hollow portion 155;
  • the gate layer 161, the source layer 162, and the drain layer 163 are formed of the same metal layer through the same mask process.
  • the gate insulating layer 150 includes a middle portion 151, a first side portion 152, and a second side portion 153, the gate insulating layer 150
  • the height of the middle portion 151 is higher than the heights of the first side portion 152 and the second side portion 153, so that there is a step difference between the middle portion 151 of the gate insulating layer 150 and the first side portion 152 and the second side portion 153 to avoid short circuit
  • the hollow portion is formed between the middle portion 151 and the first side portion 152, and the middle portion 151 and the second side portion 153, due to the provision of the hollow portion, can avoid the short circuit situation, ensure insulation, guarantee The switching performance of the thin film transistor is improved.
  • the gate layer 161 is located on the middle portion 151, and the width of the gate layer 161 is smaller than the width of the middle portion 151.
  • the gate layer 161 is located on the middle portion 151 of the gate insulating layer 150, the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, and the source layer 162 and the drain layer 163 are respectively located on the gate On both sides of the electrode insulating layer 150, the parasitic capacitance generated between the gate layer 161 and the drain layer 163 and the parasitic capacitance generated between the gate layer 161 and the source layer 162 can be reduced.
  • both sides of the first metal layer 120 are hollowed out, and the buffer layer 130 covers the upper surface of the first metal layer 120 and the hollowed-out portions on both sides.
  • a buffer layer 130 is formed on the first metal layer 120.
  • the buffer layer 130 covers the periphery of the first metal layer 120. Compared to when the buffer layer 130 does not completely cover the first metal layer 120, the buffer layer 130 covers the first The periphery of the metal layer 120 can be better insulated.
  • the panel of this application can be a TN panel (full name Twisted Nematic, ie twisted nematic panel), IPS panel (In-Plane Switching, plane switching), VA panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), Of course, other types of panels can also be used.
  • TN panel full name Twisted Nematic, ie twisted nematic panel
  • IPS panel In-Plane Switching, plane switching
  • VA panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology

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Abstract

一种显示面板（100）的制作方法和显示面板（100），包括：在基板（110）上形成第一金属层（120）、缓冲层（130）、氧化物膜层（140）和栅极绝缘层（150），通过同一道光罩制程蚀刻第二层金属得到栅极层（161）、源极层（162）和漏极层（163）。

Description

一种显示面板的制作方法和显示面板
本申请要求于2018年10月22日提交中国专利局、申请号为CN2018112304947、发明名称为“一种显示面板的制作方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的制作方法和显示面板。
背景技术
这里的陈述仅提供与本申请相关的背景信息，而不必然的构成现有技术。
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
目前IGZO(铟镓锌氧化物)技术已得到广泛的研究及应用，常见的IGZO结构有三种，BCE(back channel etch，背沟道刻蚀)结构，ESL(etch stopper layer，刻蚀阻挡层)结构，Self-aligned Top Gate(自对准的顶栅)结构，其中，BCE结构因是背沟道蚀刻，会产生背沟道损坏,影响TFT器件稳定性，ESL结构可以对背沟道进行保护，但不适合做短沟道结构，并且有较大的寄生电容,顶栅型可以做短沟道结构并且有极小的寄生电容，但光罩会多一道。
技术解决方案
本申请的目的在于提供一种显示面板的制作方法和显示面板，以减少显示面板的光罩制程。
为实现上述目的，本申请提供了一种显示面板的制作方法，包括：
在基板上依次形成第一金属层、缓冲层和氧化物膜层；
通过半色调掩膜在所述氧化物膜层上形成栅极绝缘层；
在所述栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻第二层金属得到栅极层、以及通过氧化物膜层连接的源极层和漏极层；
在所述栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
可选的，所述通过半色调掩膜在所述氧化物膜层上形成栅极绝缘层，在所述栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻第二层金属得到栅极层、以及通过氧化物膜层连接的源极层和漏极层的步骤包括：
通过半色调掩膜在所述氧化物膜层上形成包括中部、第一侧部、第二侧部和镂空部的栅极绝缘层，所述栅极绝缘层的中部高度高于第一侧部和第二侧部的高度，所述镂空部分别形成在中部和第一侧部，以及中部和第二侧部之间；
在栅极绝缘层上形成第二层金属；
通过同一道光罩制程蚀刻第二层金属，得到位于栅极绝缘层的中部上的栅极层；
同时，得到位于所述栅极绝缘层第一侧部上的源极层，以及第二侧部上的漏极层；
形成的所述源极层和漏极层，与所述栅极层绝缘。
可选的，所述通过同一道光罩制程蚀刻第二层金属，得到位于栅极绝缘层的中部上的栅极层的步骤中，所述栅极层位于所述中部上，且所述栅极层的宽度小于中部的宽度。
可选的，所述在基板上依次形成第一金属层、缓冲层和氧化物膜层的步骤包括：
在基板上形成第一层金属，并通过一道光罩蚀刻第一层金属形成第一金属层；
在所述第一金属层上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层；
通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层四周的缓冲层和氧化物膜层。
可选的，所述在基板上依次形成第一金属层、缓冲层和氧化物膜层包括：
在基板上得到第一层金属，并通过一道光罩蚀刻形成第一金属层；
在所述第一金属层上沉积形成缓冲沉积层，并在缓冲层上沉积形成氧化物膜沉积层；
通过一道光罩形成缓冲层和氧化物膜层；
所述第一金属层、缓冲层和氧化物膜层的宽度相当。
本申请公开了一种显示面板的制作方法，包括：
在基板上形成第一层金属，并通过一道光罩蚀刻形成第一层金属形成第一金属层；
在所述第一金属层上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层；
通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层四周的缓冲层和氧化物膜层；
通过半色调掩膜在所述氧化物膜层上形成包括中部、第一侧部、第二侧部和镂空部的栅极绝缘层，所述栅极绝缘层的中部高度高于第一侧部和第二侧部的高度，所述镂空部分别形成在中部和第一侧部，以及中部和第二侧部之间；
在栅极绝缘层上形成第二层金属；
通过同一道光罩蚀刻第二层金属，得到位于栅极绝缘层的中部上的栅极层；
同时，得到位于所述栅极绝缘层第一侧部上的源极层，以及第二侧部上的漏极层；
形成的所述源极层和漏极层，与所述栅极层绝缘；
所述栅极层位于所述中部上，且所述栅极层的宽度小于中部的宽度；
在所述栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
本申请还公开了一种显示面板，包括：
第一基板，所述第一基板上依次设置有第一金属层、缓冲层和氧化物膜层；
栅极绝缘层，位于所述氧化物膜层上；
栅极层，形成在所述栅极绝缘层上的中部；
源极层和漏极层，形成在所述栅极绝缘层上、位于所述栅极层的两侧；
钝化层和透明电极层，依次形成在所述栅极层、源极层和漏极层上；
所述源极层和漏极层，与所述栅极层绝缘；所述源极层和漏极层通过所述氧化物膜层连接；
所述栅极层、源极层和漏极层通过同一道光罩制程形成。
可选的，所述栅极绝缘层包括中部、第一侧部和第二侧部，所述中部的厚度大于所述第一侧部和第二侧部的厚度；
所述栅极绝缘层还包括形成在所述中部和第一侧部之间的第一镂空部，以及形成在所述中部和第二侧部之间的第二镂空部；
所述栅极层形成在所述中部上；
所述源极层形成在所述第一侧部上，并通过所述第一镂空部连接于所述氧化物膜层；
所述漏极层形成在所述第二侧部上，并通过所述第二镂空部连接于所述氧化物膜层；
所述栅极层、源极层和漏极层由同一金属层，通过同一道光罩制程形成。
可选的，所述栅极层位于所述中部上，且所述栅极层的宽度小于所述中部的宽度。
可选的，第一金属层的两侧镂空，缓冲层覆盖住第一金属层的上表面及两侧镂空的部分。
本方案中，对自对准的顶栅结构进行改善，利用半色调掩膜形成栅极绝缘层，如此，在栅极绝缘层上溅渡一层金属为第二层金属，并通过同一道光罩制程蚀刻，即可同时形成栅极层、源极层和漏极层，由七道光罩变为六道光罩,减少了一道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1a到图1g是本申请一实施例一种显示面板七道光罩制程的示意图；
图2a到图2f是本申请一实施例一种显示面板六道光罩制程的示意图；
图3是本申请一实施例一种显示面板六道光罩制程的示意图(2)；
图4是本申请一实施例一种显示面板的制作方法流程示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
参考图1a，在玻璃基板110上通过一道光罩的制程形成第一金属层120；
参考图1b，在第一金属层120上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层，通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖 第一金属层120四周的缓冲层130和氧化物膜层140；
参考图1c，在氧化物膜层140上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层，通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层150和栅极层161；
参考图1d，在氧化物膜层140上通过一道光罩形成包括中部151、第一侧部152、第二侧部153以及镂空部的互联层，所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
参考图1e，在互联层上形成第二层金属，并对第二层金属通过同一道光罩制程进行蚀刻得到漏极层163和源极层162；
参考图1f，在漏极层163和源极层162上，通过一道光罩制程蚀刻得到钝化层170；
参考图1g，在钝化层170上，通过一道光罩蚀刻得到透明电极层180。
总共使用了七道光罩。
下面结合附图和实施例对本申请作进一步说明。
参考图2a至图4所示，本申请实施例公开了一种显示面板100的制作方法，包括：
在基板110上依次形成第一金属层120、缓冲层130和氧化物膜层140；
通过半色调掩膜在所述氧化物膜层140上形成栅极绝缘层150；
在所述栅极绝缘层150上形成第二层金属，并通过同一道光罩制程蚀刻第二层金属得到栅极层161、以及通过氧化物膜层140连接的源极层162和漏极层163；
在所述栅极层161、源极层162和漏极层163上依次形成钝化层170和透明电极层180。
其中，基板110为玻璃基板110。
本方案中，对自对准的顶栅结构进行改善，利用半色调掩膜形成栅极绝缘层150，如此，在栅极绝缘层150上溅渡一层金属为第二层金属，并通过同一道光罩制程蚀刻，即可同时形成栅极层161、源极层162和漏极层163，由七道光罩变为六道光罩,减少了一道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
在一实施例中，参考图2c和图2d，所述通过半色调掩膜在所述氧化物膜层140上 形成栅极绝缘层150，在所述栅极绝缘层150上形成第二层金属，并通过同一道光罩制程蚀刻第二层金属得到栅极层161、以及通过氧化物膜层140连接的源极层162和漏极层163的步骤包括：
通过半色调掩膜在所述氧化物膜层140上形成包括中部151、第一侧部152、第二侧部153和镂空部的栅极绝缘层150，所述栅极绝缘层150的中部151高度高于第一侧部152和第二侧部153的高度，所述镂空部分别形成在中部151和第一侧部152，以及中部151和第二侧部153之间，所述第一侧部152和第二侧部153的高度是相当的；
在栅极绝缘层150上形成第二层金属；
通过同一道光罩制程蚀刻第二层金属，得到位于栅极绝缘层150的中部151上的栅极层161；
同时，得到位于所述栅极绝缘层150第一侧部152上的源极层162，以及第二侧部153上的漏极层163；
形成的所述源极层162和漏极层163，与所述栅极层161绝缘。
本方案中，在源极层162、栅极层161和漏极层163形成之前，栅极绝缘层150包括中部151、第一侧部152和第二侧部153，所述栅极绝缘层150的中部151的高度高于第一侧部152和第二侧部153的高度，使得栅极绝缘层150的中部151与第一侧部152和第二侧部153之间存在段差，可避免短路的情况发生；另外，所述镂空部分别形成在中部151和第一侧部152，以及中部151和第二侧部153之间，由于镂空部的设置，可以避免短路的情况，保证绝缘，保证了TFT的开关性能。
参考图2d，其中，所述在栅极绝缘层150上金属溅渡形成第二层金属，并蚀刻得到栅极层161、源极层162和漏极层163的步骤中，
所述漏极层163由栅极绝缘层150中部151的一侧往远离栅极层161的方向延伸，所述源极层162由栅极绝缘层150中部151的另一侧往远离栅极层161的方向延伸。
在一实施例中，所述通过同一道光罩制程蚀刻第二层金属，得到位于栅极绝缘层150的中部151上的栅极层161的步骤中，所述栅极层161位于所述中部151上，且所述栅极层161的宽度小于中部151的宽度。
本方案中，栅极层161位于与栅极绝缘层150的中部151上，栅极层161的宽度小于栅极绝缘层150的中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上，可以减少栅极层161和漏极层163之间产生的寄生电容，以及栅极层161和源极层162之间产生的寄生电容。
参考图2b，在一实施例中，所述在基板110上依次形成第一金属层120、缓冲层130和氧化物膜层140的步骤包括：
在基板110上形成第一层金属，并通过一道光罩蚀刻第一层金属形成第一金属层120；
在所述第一金属层120上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层；
通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层120四周的缓冲层130和氧化物膜层140。
本方案中，在第一金属层120上形成缓冲层130，缓冲层130覆盖住第一金属层120的四周，相对于缓冲层130未将第一金属层120全面覆盖时来说，缓冲层130覆盖住第一金属层120的四周可以更好的绝缘。
在一实施例中，参考图3，所述在基板110上依次形成第一金属层120、缓冲层130和氧化物膜层140包括：
在基板110上得到第一层金属，并通过一道光罩蚀刻形成第一金属层120；
在所述第一金属层120上沉积形成缓冲沉积层，并在缓冲层130上沉积形成氧化物膜沉积层；
通过一道光罩形成缓冲层130和氧化物膜层140；
所述第一金属层120、缓冲层130和氧化物膜层140的宽度相当，相当指的是，两者的宽度差在预设的阈值之内，即认为两者的宽度相当；实际上，位于下方的一层会比位于上方的一层稍微大一点点。
实际上，由于蚀刻的原因，该缓冲层130会略大于氧化物膜层140，该第一金属层120会略大于该缓冲层130，这都是正常情况；甚至，本身就设计使得该缓冲层130大 于氧化物膜层140，该第一金属层120大于该缓冲层130也是可以的。
本方案中，所述第一金属层120、缓冲层130和氧化物膜层140的宽度相当，在制程的过程，蚀刻方便。
作为本申请的另一实施例，参考图2a至图2f和图4所示，公开了一种显示面板100的制作方法，包括：
S41：在基板110上形成第一层金属，并通过一道光罩蚀刻形成第一层金属形成第一金属层120；
S42：在所述第一金属层120上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层；
通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层120四周的缓冲层130和氧化物膜层140；
S43：通过半色调掩膜在所述氧化物膜层140上形成包括中部151、第一侧部152、第二侧部153和镂空部的栅极绝缘层150，所述栅极绝缘层150的中部151高度高于第一侧部152和第二侧部153的高度，所述镂空部分别形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
S44：在栅极绝缘层150上形成第二层金属；
通过同一道光罩蚀刻第二层金属，得到位于栅极绝缘层150的中部151上的栅极层161；
同时，得到位于所述栅极绝缘层150第一侧部152上的源极层162，以及第二侧部153上的漏极层163；
形成的所述源极层162和漏极层163，与所述栅极层161绝缘；
所述栅极层161位于所述中部151上，且所述栅极层161的宽度小于中部151的宽度；
S45：在所述栅极层161、源极层162和漏极层163上依次形成钝化层170和透明电极层180。
本方案中，对自对准的顶栅结构进行改善，利用半色调掩膜形成中间高两侧部低且 中部151和两侧部之间分别形成镂空部的栅极绝缘层150，如此，在栅极绝缘层150上溅渡一层金属为第二层金属，并通过同一道光罩制程蚀刻，即可同时形成栅极层161、源极层162和漏极层163，减少一道光罩,由七道光罩变为六道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的；并且该源极层162和漏极层163，同该栅极层161之前，由于断差结构和镂空部的设置，可以避免短路的情况，保证绝缘，保证了TFT的开关性能。
作为本申请的另一实施例，参考图2a至图2f所示，公开了一种显示面板100，包括：
第一基板110，所述第一基板110上依次设置有第一金属层120、缓冲层130和氧化物膜层140；
栅极绝缘层150，位于所述氧化物膜层140上；
栅极层161，形成在所述栅极绝缘层150上的中部151；
源极层162和漏极层163，形成在所述栅极绝缘层150上、位于所述栅极层161的两侧；
钝化层170和透明电极层180，依次形成在所述栅极层161、源极层162和漏极层163上；
所述源极层162和漏极层163，与所述栅极层161绝缘；所述源极层162和漏极层163通过所述氧化物膜层140连接；
所述栅极层161、源极层162和漏极层163通过同一道光罩制程形成。
本方案中，对自对准的顶栅结构进行改善，在栅极绝缘层150上溅渡一层金属为第二层金属，并通过同一道光罩制程蚀刻，即可同时形成栅极层161、源极层162和漏极层163，栅极层161、源极层162和漏极层163可在半色调光罩形成的栅极绝缘层150结构上一起完成，减少一道光罩,由七道光罩变为六道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
在一实施例中，所述栅极绝缘层150包括中部151、第一侧部152和第二侧部153，所述中部151的厚度大于所述第一侧部152和第二侧部153的厚度；
所述栅极绝缘层150还包括形成在所述中部151和第一侧部152之间的第一镂空部154，以及形成在所述中部151和第二侧部153之间的第二镂空部155；
所述栅极层161形成在所述中部151上；
所述源极层162形成在所述第一侧部152上，并通过所述第一镂空部154连接于所述氧化物膜层140；
所述漏极层163形成在所述第二侧部153上，并通过所述第二镂空部155连接于所述氧化物膜层140；
所述栅极层161、源极层162和漏极层163由同一金属层，通过同一道光罩制程形成。
本方案中，在源极层162、栅极层161和漏极层163形成之前，栅极绝缘层150包括中部151、第一侧部152和第二侧部153，所述栅极绝缘层150的中部151的高度高于第一侧部152和第二侧部153的高度，使得栅极绝缘层150的中部151与第一侧部152和第二侧部153之间存在段差，可避免短路的情况发生；另外，所述镂空部分别形成在中部151和第一侧部152，以及中部151和第二侧部153之间，由于镂空部的设置，可以避免短路的情况，保证绝缘，保证了薄膜晶体管的开关性能。
在一实施例中，所述栅极层161位于所述中部151上，且所述栅极层161的宽度小于所述中部151的宽度。
本方案中，栅极层161位于与栅极绝缘层150的中部151上，栅极层161的宽度小于栅极绝缘层150的中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上，可以减少栅极层161和漏极层163之间产生的寄生电容，以及栅极层161和源极层162之间产生的寄生电容。
在一实施例中，第一金属层120的两侧镂空，缓冲层130覆盖住第一金属层120的上表面及两侧镂空的部分。
在第一金属层120上形成缓冲层130，缓冲层130覆盖住第一金属层120的四周，相对于缓冲层130未将第一金属层120全面覆盖时来说，缓冲层130覆盖住第一金属层120的四周可以更好的绝缘。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的可选的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示面板的制作方法，包括：
    在基板上依次形成第一金属层、缓冲层和氧化物膜层；
    通过半色调掩膜在所述氧化物膜层上形成栅极绝缘层；
    在所述栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻第二层金属得到栅极层、以及通过氧化物膜层连接的源极层和漏极层；以及
    在所述栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
  2. 如权利要求1所述的一种显示面板的制作方法，其中，所述通过半色调掩膜在所述氧化物膜层上形成栅极绝缘层，在所述栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻第二层金属得到栅极层、以及通过氧化物膜层连接的源极层和漏极层的步骤包括：
    通过半色调掩膜在所述氧化物膜层上形成包括中部、第一侧部、第二侧部和镂空部的栅极绝缘层，所述栅极绝缘层的中部高度高于第一侧部和第二侧部的高度，所述镂空部分别形成在中部和第一侧部，以及中部和第二侧部之间；
    在栅极绝缘层上形成第二层金属；
    通过同一道光罩制程蚀刻第二层金属，得到位于栅极绝缘层的中部上的栅极层；
    同时，得到位于所述栅极绝缘层第一侧部上的源极层，以及第二侧部上的漏极层；以及
    形成的所述源极层和漏极层，与所述栅极层绝缘。
  3. 如权利要求2所述的一种显示面板的制作方法，其中，所述通过同一道光罩制程蚀刻第二层金属，得到位于栅极绝缘层的中部上的栅极层的步骤中，
    所述栅极层位于所述中部上，且所述栅极层的宽度小于中部的宽度。
  4. 如权利要求1所述的一种显示面板的制作方法，其中，所述在基板上依次形成第一金属层、缓冲层和氧化物膜层的步骤包括：
    在基板上形成第一层金属，并通过一道光罩蚀刻第一层金属形成第一金属层；
    在所述第一金属层上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层；以及
    通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层四周的缓冲层和氧化物膜层。
  5. 如权利要求1所述的一种显示面板的制作方法，其中，所述在基板上依次形成第一金属层、缓冲层和氧化物膜层包括：
    在基板上得到第一层金属，并通过一道光罩蚀刻形成第一金属层；
    在所述第一金属层上沉积形成缓冲沉积层，并在缓冲层上沉积形成氧化物膜沉积层；
    通过一道光罩形成缓冲层和氧化物膜层；以及
    所述第一金属层、缓冲层和氧化物膜层的宽度相当。
  6. 如权利要求4所述的一种显示面板的制作方法，其中，所述缓冲层宽度大于所述氧化物膜层宽度。
  7. 如权利要求4所述的一种显示面板的制作方法，其中，所述第一金属层宽度大于所述缓冲层宽度。
  8. 如权利要求1所述的一种显示面板的制作方法，其中，所述基板为玻璃基板。
  9. 一种显示面板的制作方法，包括：
    在基板上形成第一层金属，并通过一道光罩蚀刻形成第一层金属形成第一金属层；
    在所述第一金属层上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层；
    通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层四周的缓冲层和氧化物膜层；
    通过半色调掩膜在所述氧化物膜层上形成包括中部、第一侧部、第二侧部和镂空部的栅极绝缘层，所述栅极绝缘层的中部高度高于第一侧部和第二侧部的高度，所述镂空部分别形成在中部和第一侧部，以及中部和第二侧部之间；
    在栅极绝缘层上形成第二层金属；
    通过同一道光罩蚀刻第二层金属，得到位于栅极绝缘层的中部上的栅极层；
    同时，得到位于所述栅极绝缘层第一侧部上的源极层，以及第二侧部上的漏极层；
    形成的所述源极层和漏极层，与所述栅极层绝缘；
    所述栅极层位于所述中部上，且所述栅极层的宽度小于中部的宽度；以及
    在所述栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
  10. 一种显示面板，包括：
    第一基板，所述第一基板上依次设置有第一金属层、缓冲层和氧化物膜层；
    栅极绝缘层，位于所述氧化物膜层上；
    栅极层，形成在所述栅极绝缘层上的中部；
    源极层和漏极层，形成在所述栅极绝缘层上、位于所述栅极层的两侧；
    钝化层和透明电极层，依次形成在所述栅极层、源极层和漏极层上；
    所述源极层和漏极层，与所述栅极层绝缘；所述源极层和漏极层通过所述氧化物膜层连接；以及
    所述栅极层、源极层和漏极层通过同一道光罩制程形成。
  11. 如权利要求10所述的一种显示面板，其中，所述第一基板为玻璃基板。
  12. 如权利要求10所述的一种显示面板，其中，所述缓冲层宽度大于所述氧化物膜层宽度。
  13. 如权利要求10所述的一种显示面板，其中，所述第一金属层宽度大于所述缓冲层宽度。
  14. 如权利要求10所述的一种显示面板，其中，所述栅极绝缘层包括中部、第一侧部和第二侧部，所述中部的厚度大于所述第一侧部和第二侧部的厚度；
    所述栅极绝缘层还包括形成在所述中部和第一侧部之间的第一镂空部，以及形成在所述中部和第二侧部之间的第二镂空部；
    所述栅极层形成在所述中部上；
    所述源极层形成在所述第一侧部上，并通过所述第一镂空部连接于所述氧化物膜层；
    所述漏极层形成在所述第二侧部上，并通过所述第二镂空部连接于所述氧化物膜层；以及
    所述栅极层、源极层和漏极层由同一金属层，通过同一道光罩制程形成。
  15. 如权利要求14所述的一种显示面板，其中，所述栅极层位于所述中部上，且所述栅极层的宽度小于所述中部的宽度。
  16. 如权利要求10所述的一种显示面板，其中，第一金属层的两侧镂空，缓冲层覆盖住第一金属层的上表面及两侧镂空的部分。
  17. 如权利要求10所述的一种显示面板，其中，所述显示面板为扭曲向列型显示面板、平面转换显示面板和多象限垂直配向显示面板中的一种。
PCT/CN2018/115610 2018-10-22 2018-11-15 一种显示面板的制作方法和显示面板 WO2020082460A1 (zh)

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