WO2013056617A1 - 像素单元、阵列基板、液晶面板及阵列基板的制造方法 - Google Patents

像素单元、阵列基板、液晶面板及阵列基板的制造方法 Download PDF

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Publication number
WO2013056617A1
WO2013056617A1 PCT/CN2012/082347 CN2012082347W WO2013056617A1 WO 2013056617 A1 WO2013056617 A1 WO 2013056617A1 CN 2012082347 W CN2012082347 W CN 2012082347W WO 2013056617 A1 WO2013056617 A1 WO 2013056617A1
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Prior art keywords
pixel
gate
thin film
pixel unit
film transistor
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PCT/CN2012/082347
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English (en)
French (fr)
Inventor
金熙哲
徐超
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020127032426A priority Critical patent/KR20130055622A/ko
Priority to US13/703,567 priority patent/US8982307B2/en
Priority to JP2014534929A priority patent/JP2014528598A/ja
Priority to EP12791677.3A priority patent/EP2770369B1/en
Publication of WO2013056617A1 publication Critical patent/WO2013056617A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134381—Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • Embodiments of the present invention relate to a pixel unit, an array substrate, a liquid crystal panel, a display device, and a method of fabricating the same. Background technique
  • LCDs Liquid crystal displays
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the liquid crystal panel of the liquid crystal display includes an array substrate and a color filter substrate.
  • a gate line is disposed on the array substrate, and a data line is disposed perpendicular to the gate line, wherein the gate line and the data line cross each other to define a pixel region; wherein the pixel region is provided with a thin film transistor and a pixel electrode;
  • the gate of the thin film transistor is connected to the gate line, the source is connected to the data line, and the drain is connected to the pixel electrode.
  • the array substrate is a key component of the liquid crystal display panel, and the pixel structure composed of the thin film transistor and the pixel electrode is an important component of the array substrate.
  • the conventional TN mode liquid crystal display has a relatively small viewing angle and cannot meet the requirements of high quality display.
  • Advanced Super Dimension Switch which forms a multi-dimensional electric field by an electric field generated at the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer. All the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the conventional ADS pixel unit structure is: including a thin film transistor and a pixel electrode and a common electrode.
  • the pixel electrode is located above the common electrode; the pixel electrode is located at the uppermost layer and is connected to the drain of the thin film transistor, and the common electrode is located at the lowest layer and is connected to the common electrode line.
  • the traditional ADS type LCD panel has high resolution, high transmittance, low power consumption, and wide viewing compared to the conventional TN type. Angle, high aperture ratio, low chromatic aberration, and no push mura, but the traditional ADS has a small aperture ratio due to its own characteristics, which cannot meet the requirements of high quality display. Summary of the invention
  • the embodiment of the present invention improves the conventional ADS, and it is desirable to provide a new pixel unit in the form of I-ADS, an array substrate, a liquid crystal panel, a display device, and a manufacturing method thereof to improve pixel aperture ratio and reduce power consumption. And improve the display quality.
  • An aspect of the invention provides a pixel unit including a thin film transistor, a pixel electrode, and a common electrode, the thin film transistor including a gate, a gate insulating layer disposed on the gate, and the gate insulating layer An active layer, a source and a drain disposed over the active layer, and a passivation layer disposed over the source and the drain, wherein the common electrode is directly disposed on the Above the passivation layer; the pixel electrode is disposed under the passivation layer and connected to a drain of the thin film transistor.
  • the pixel electrode is disposed in the same layer as the gate, a gate insulating layer is disposed between the passivation layer and the pixel electrode, and a metal in the same layer as the common electrode is respectively connected through two via holes. a drain of the thin film transistor and the pixel electrode.
  • the common electrode has a slit shape
  • the pixel electrode has a plate shape
  • connection electrode for connecting the drain electrode of the pixel electrode and the thin film transistor in the same layer as the common electrode is made of the same material as the common electrode.
  • the pixel electrode and/or the common electrode are transparent electrodes.
  • the common electrode is a single layer film of ITO or IZO, or a composite film composed of ITO and IZO.
  • the passivation layer is an oxide, a nitride, an oxynitride or an organic resin.
  • Another aspect of the present invention provides an array substrate including a base substrate, and a plurality of gate lines and a plurality of data lines disposed on the base substrate, wherein the plurality of data lines are perpendicular to the plurality of lines a gate line, the gate line and the data line intersecting each other to define a plurality of pixel regions, wherein each of the plurality of pixel regions includes any one of the pixel units described above, and the thin film transistor of each of the pixel units The gate is connected to the corresponding gate line, and the source of the thin film transistor is connected to the corresponding data line.
  • each row of the pixel unit is provided with a gate line above and below the pixel unit, and the pixel sheet is A data line is disposed on the left side and the right side of the element, and only one gate line is disposed between each adjacent two rows of pixel units, and one data line is disposed between each adjacent two columns of pixel units.
  • a pixel line is disposed above and below the pixel unit, and two gate lines are disposed between each adjacent two rows of the pixel unit; left or right side of each column of the pixel unit A data line is disposed, and two columns of the pixel units are included between each adjacent two data lines.
  • a gate of the thin film transistor of each of the pixel units is connected to a gate line above or below a pixel unit in which the pixel unit is located, and a source of the thin film transistor and a pixel on the left or right side of the pixel unit in which it is located Line connection, the Z-inversion pixel structure.
  • the Z-inverted pixel structure includes:
  • the source of the thin film transistor in the odd-numbered pixel unit of the same column is connected to one of the data lines on both sides of the column, and the source of the thin film transistor in the even-numbered pixel unit is connected to the data line on both sides of the column On the other data line, the source of the thin film transistor in the pixel unit of the same row in the adjacent two columns is connected to two different data lines;
  • Two or two sets of the pixel units of the same row are alternately connected to the two gate lines located above and below the row of pixel units through the gates of the thin film transistors included therein, and the pixel units connected to each of the gate lines Located on the same line;
  • the gates of the thin film transistors of two adjacent and adjacent pixel cells between two adjacent data lines are respectively connected to two gate lines, and the sources are respectively connected to the two data lines.
  • the array substrate further includes a common electrode line, and the common electrode and the common electrode line are connected through a via hole at a periphery of the array substrate.
  • the common electrode of each of the pixel units extends over a gate line above and/or below the pixel unit in which it is located, forming a storage capacitor with the one gate line.
  • a liquid crystal panel including a color filter substrate and any of the array substrates, wherein the color filter substrate includes a black matrix, wherein the color film substrate corresponds to the plurality of The position of the gate line, the position corresponding to the plurality of data lines, and the position of the boundary between the two columns of pixel units corresponding to the adjacent two data lines are all provided with a black matrix.
  • the width of the black matrix corresponding to the position of the data line is 17-23 um
  • the width of the black matrix corresponding to the position of the boundary between the two columns of pixel units between adjacent two data lines is 6-10 um.
  • the width of the black matrix corresponding to the position of the data line is 20 um, and the width of the black matrix corresponding to the position of the boundary between the two columns of pixel units between adjacent two data lines is 8 um.
  • Another embodiment of the present invention also provides a display device including the above liquid crystal panel.
  • the display device further includes a backlight disposed opposite to a light incident surface of the liquid crystal panel.
  • the backlight is, for example, an LED backlight.
  • Another aspect of the present invention provides a method of fabricating an array substrate, comprising: S101, forming a pattern including a pixel electrode by a first patterning process, and forming a plurality of gate lines and a plurality of pixels by a second patterning process a pattern of the thin film transistor gate of the cell;
  • the step S102 includes:
  • the photoresist in the semi-reserved region of the photoresist is completely removed by an ashing process, and the source-drain metal film in the region is exposed;
  • the source-drain metal film of the semi-reserved region of the photoresist is completely etched away by a second etching process to form a pattern including a pixel electrode, a data line, a source electrode, a drain electrode, and a channel region of the thin film transistor; removing the remaining photolithography gum.
  • the active layer film includes a semiconductor film and a doped semiconductor film
  • the pass The secondary etching process completely etches away the source-drain metal film of the semi-reserved region of the photoresist, and further includes completely etching away the doped semiconductor film of the channel region and etching away part of the semiconductor film.
  • the step S103 includes:
  • a via penetrating through the passivation layer and the gate insulating layer is formed over the pixel electrode by a halftone or gray tone mask, and a via hole penetrating the passivation layer is formed over the drain.
  • the step S104 includes:
  • a pattern of common electrodes is formed by ordinary masking.
  • the plurality of gate lines formed in the step S101 include: one gate line is formed above and below each row of pixel units, and only one gate line is formed between each adjacent two rows of pixel units.
  • the data line formed in the step S102 includes: one data line is formed on the left side and the right side of the pixel unit, and one data line is formed between each adjacent two columns of pixel units.
  • the gate line formed in the step S101 includes: one gate line is formed above and below each row of pixel units, and two gate lines are disposed between each adjacent two rows of pixel units.
  • the data line formed in the step S102 includes: one data line is disposed on the left side or the right side of each column of pixel units, and two columns of pixel units are included between each adjacent two data lines.
  • step S101 the gate of the thin film transistor of each pixel unit is connected to a gate line above or below the pixel unit in which it is located, and the source of the thin film transistor of each pixel unit and the pixel thereof are realized in step S102.
  • a data line is connected to the left or right side of the cell to achieve a Z-inverted pixel structure.
  • the Z-inverted pixel structure includes:
  • the source of the thin film transistor in the odd-numbered pixel unit of the same column is connected to one of the data lines on both sides of the column, and the source of the thin film transistor in the even-numbered pixel unit is connected to the data line on both sides of the column On the other data line, the source of the thin film transistor in the pixel unit of the same row in the adjacent two columns is connected to two different data lines;
  • Two pairs of pixel units of the same are alternately connected to the two gate lines above and below the pixel unit of the row through the gates of the thin film transistors included therein, and the pixel units connected to each of the gate lines are located in the same Row;
  • Grid of thin film transistors of two adjacent and adjacent pixel cells between two adjacent data lines The poles are respectively connected to two gate lines, and the sources are respectively connected to the two data lines.
  • a common electrode line is formed while forming a gate line and a gate electrode in step S101, and a common electrode and the common electrode line are connected to each other at a periphery of the array substrate through a via hole in step S104.
  • the formed common electrode extends over a gate line above and/or below the pixel unit in which it is located, forming a storage capacitor with the one gate line.
  • Another aspect of the present invention provides a method of fabricating a liquid crystal panel comprising the above-described method of fabricating an array substrate.
  • the method further includes a method of manufacturing a color filter substrate, where a position corresponding to the gate line, a position corresponding to the data line, and a boundary between two columns of pixel units corresponding to two adjacent data lines are formed on the color filter substrate The locations are all set with a black matrix.
  • the width of the black matrix corresponding to the position of the data line is 17-23 um
  • the width of the black matrix corresponding to the position where the two columns of pixel units between the adjacent two data lines meet is 6-10 um.
  • the width of the black matrix corresponding to the position of the data line is 20 um, and the width of the black matrix corresponding to the position of the boundary between the two columns of pixel units between the adjacent two data lines is 8 um.
  • Another aspect of the present invention provides a method of manufacturing a display device comprising the above-described method of manufacturing a liquid crystal panel.
  • the display device further includes a backlight disposed opposite to the light incident surface of the liquid crystal panel.
  • the backlight is an LED backlight.
  • the pixel unit structure provided by the embodiment of the invention has a larger viewing angle than the pixel unit structure of the ordinary TN mode; and has a higher aperture ratio and a more stable process than the pixel unit structure of the common ADS.
  • the 4Mask method using a two-tone mask is used to achieve advantages.
  • the dual gate structure realized by the common ADS can extend the common electrode to the top of the gate line, the influence of the signal on the shield gate line on the pixel electrode, reduce the width of the black matrix above the gate line, and increase the aperture ratio.
  • the obtained I-ADS array substrate has a larger viewing angle than the conventional TN mode array substrate, and realizes a double gate structure on the basis of I-ADS.
  • Z-inverted array substrate which is beneficial to reduce power consumption.
  • the dual gate structure realized by the common ADS can extend the common electrode to the top of the gate line, the influence of the signal on the shield gate line on the pixel electrode, thereby reducing the width of the black matrix above the gate line, and increasing the aperture ratio.
  • Liquid crystal panel provided by embodiment of the invention and manufacturer thereof
  • the display device and the method of fabricating the same, including the array substrate described above and a method of fabricating the same, can accordingly increase the aperture ratio while improving power consumption while improving display quality.
  • FIG. 1 is a plan view showing the planar structure of an array substrate (pixel unit) according to an embodiment of the present invention
  • FIG. 1A is a cross-sectional view taken along line A1-A1 of FIG. 1;
  • Figure 1B is a cross-sectional view taken along line B1-B1 of Figure 1;
  • FIG. 2 is a schematic plan view showing the planar structure of the array substrate after the first patterning process of the present invention
  • Figure 2A is a cross-sectional view taken along line A2-A2 of Figure 2;
  • FIG. 3 is a schematic plan view showing the planar structure of the array substrate after the second patterning process of the present invention.
  • Figure 3A is a cross-sectional view taken along line A3-A3 of Figure 3;
  • FIG. 4 is a schematic plan view showing the planar structure of the array substrate after the third patterning process
  • Figure 4A is a cross-sectional view taken along the line A4-A4 of Figure 4;
  • FIG. 5 is a schematic plan view showing a fourth structural patterning process of the array substrate of the present invention.
  • Figure 5A is a cross-sectional view taken along line A5-A5 of Figure 5;
  • FIG. 6 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic view of a liquid crystal panel according to an embodiment of the present invention.
  • FIG. 8 is still another schematic diagram of an array substrate according to an embodiment of the present invention.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel regions arranged in a matrix, each pixel region including a pixel unit, and the pixel unit includes A thin film transistor of a switching element and a pixel electrode and a common electrode for controlling alignment of the liquid crystal.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • the embodiment of the present invention provides a pixel unit.
  • the structure of the pixel unit in this embodiment will be described below with reference to FIG. 1 and FIG. It should be clarified that the pixel unit defined in this embodiment does not include a gate line and a data line.
  • the pixel unit may be used to form a common array substrate or to form an array substrate of a double gate structure after appropriately arranging the gate lines and the data lines.
  • FIG. 1 is a schematic plan view showing a planar structure of a pixel unit according to an embodiment of the present invention, showing two pixel units adjacent to each other;
  • FIG. 1A is a cross-sectional view taken along the line A1-A1 in FIG. 1
  • FIG. 1B is a cross-sectional view in FIG.
  • a schematic cross-sectional view of a B1-B1 that is, FIG. 1A and FIG. 1B are schematic cross-sectional views of different cutting directions of one pixel unit.
  • the pixel unit in this embodiment includes a thin film transistor 100, a pixel electrode 2, and a common electrode 9.
  • the thin film transistor 100 includes a gate 31, a gate insulating layer 4 disposed on the gate 31, an active layer 5 disposed on the gate insulating layer 4, and a source 61 disposed on the active layer 5. And a drain 62, and a passivation layer 7 disposed over the source 61 and the drain 62.
  • the common electrode 9 is disposed directly on the passivation layer 7; the pixel electrode 2 is disposed under the passivation layer 7 and is connected to the drain 62 of the thin film transistor 100.
  • the pixel electrode 2 may be disposed directly under the passivation layer 7, and the pixel electrode 2 is also disposed under the passivation layer 7, while another intermediate film layer exists between the passivation layer 7 and the pixel electrode 2, such as the gate insulating layer 4. .
  • the pixel electrode 2 When the pixel electrode 2 is disposed directly under the passivation layer 7, it may be directly overlapped under the drain or otherwise connected to the drain.
  • the pixel unit of this embodiment differs from the conventional ADS in that the upper and lower positional relationships of the pixel electrode and the common electrode are interchanged, and thus may be referred to as an I-ADS (Inverse-ADS) type pixel unit.
  • the pixel electrode 2 and the gate 3 are disposed in the same layer, and the gate insulating layer 4 is disposed between the passivation layer 7 and the pixel electrode 2, and the connection electrode in the same layer as the common electrode 9
  • the drain electrode 62 and the pixel electrode 2 of the thin film transistor 100 are connected through the via 81 and the via 82, respectively.
  • the pixel electrode 2 and the gate electrode 3 are disposed in the same layer, which refers to the positional relationship between the pixel electrode 2 and the gate line 3, and is not limited to being formed of the same material of the same layer.
  • the pixel electrode 2 and the gate electrode 3 may be the same material or different materials.
  • the common electrode 9 has a slit shape
  • the pixel electrode 2 has a plate shape
  • the common electrode 9 and the pixel electrode 2 may have slit shapes.
  • the common electrode 9 is slit-shaped
  • the pixel electrode 2 is plate-shaped, and the pixel electrode 2 and the common electrode 9 of this shape combination are more easily realized in the structure of the pixel unit of the present embodiment.
  • connection electrode 91 in the same layer as the common electrode 9 is the same material as the common electrode 9; preferably, the connection electrode 91 and the common electrode 9 are formed in the same layer and in the same process.
  • the pixel electrode 2 and/or the common electrode 9 are transparent electrodes.
  • the common electrode 9 may be a single layer film of indium tin oxide (ITO) or indium oxide (IZO), or a composite film composed of ITO and IZO.
  • ITO indium tin oxide
  • IZO indium oxide
  • the passivation layer 7 may be, for example, an oxide, a nitride, an oxynitride or an organic resin.
  • the passivation layer 7 is made of an organic resin material, and the good transparency and insulating properties of the organic resin itself will give the final display device a better aperture ratio and better display effect.
  • the common electrode 9 is directly disposed on the passivation layer 7, and the pixel electrode 2 is disposed under the passivation layer 7 and connected to the drain electrode 62 of the thin film transistor.
  • the pixel unit of the normal TN mode has a larger viewing angle.
  • the pixel unit provided by the embodiment of the present invention has a higher aperture ratio and a more stable process than the pixel unit of the common ADS, and can be selected by using a 4Mask method using a two-tone mask; and further, it is relatively common.
  • the double-gate structure realized by ADS can extend the common electrode to the top of the gate line, affect the influence of the signal on the shield line on the pixel electrode, thereby reducing the width of the black matrix above the gate line, increasing the aperture ratio, and improving the display quality.
  • the embodiment provides an array substrate, including a base substrate, a gate line disposed on the substrate, and a data line disposed perpendicular to the gate line. a pixel area is defined between the gate line and the data line, The pixel area includes the pixel unit described in the first embodiment (see FIG. 1). A gate of the thin film transistor is connected to the gate line, and a source of the thin film transistor is connected to the data line. It should be noted that the array substrate including the above pixel unit may be referred to as an I-ADS type array substrate; compared with the conventional ADS type array substrate, the upper and lower positional relationship of the pixel electrode 2 and the common electrode 9 is changed.
  • the gate lines and the data lines cross each other to define an array, and the gate lines are disposed above and below the plurality of pixel units of each row, and the left and right sides of each pixel unit A data line is disposed, and only one gate line is disposed between each adjacent two rows of pixel units, and one data line is disposed between each adjacent two columns of pixel units.
  • Each pixel unit is an I-ADS type pixel unit.
  • gate lines are disposed above and below a plurality of pixel units of each row, and two gate lines 321 and 322 are disposed between the adjacent two rows of the pixel units.
  • Fig. 1 shows only two pixel units adjacent to each other on the array substrate.
  • a data line is disposed on the left or right side of each column of pixel units, and two columns of the pixel units are included between each adjacent two data lines.
  • This is an array substrate that implements a dual-gate structure based on I-ADS.
  • Fig. 8 is only for illustration, and the specific pixel structure of each pixel unit is not shown.
  • a gate of the thin film transistor is connected to a gate line above or below a pixel unit where the thin film transistor is connected, and a source of the thin film transistor is connected to a data line on a left side or a right side of a pixel unit where the thin film transistor is located, thereby realizing Z inversion ( Z-inversion )
  • the pixel structure is connected to a gate line above or below a pixel unit where the thin film transistor is connected, and a source of the thin film transistor is connected to a data line on a left side or a right side of a pixel unit where the thin film transistor is located, thereby realizing Z inversion ( Z-inversion ) The pixel structure.
  • a schematic diagram of a pixel structure for realizing Z inversion in this embodiment is as shown in FIG. 8, and can be implemented in the following form.
  • the source of the thin film transistor in the odd-numbered pixel unit in the same column is connected to one of the data lines on both sides of the column, and the source of the thin film transistor in the even-numbered pixel unit is connected in the column two
  • the source of the thin film transistor in the pixel unit of the same row in the adjacent two columns is connected to two different data lines.
  • Two or two sets of the pixel units of the same row are alternately connected to the two gate lines located above and below the row of pixel units through the gates of the thin film transistors included therein, and the pixel units connected to each of the gate lines Located in the same row; and, the gates of the thin film transistors of two adjacent and adjacent pixel units between two adjacent data lines are respectively connected to two gate lines, and the sources are respectively connected to the two data on-line.
  • an exemplary specific structural design of the double gate structure is as shown in FIG.
  • the number 321 is the gate line 1 and the 322 is the gate line 2, which forms a double gate structure.
  • an array substrate having a double gate structure and a Z-inversion design can be understood with reference to FIG. Z-inversion can control the pixels on the left and right sides of the same data line to reduce power consumption and improve display.
  • each data line can affect the pixels of the two columns on the left and right.
  • the array substrate and the counter substrate are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material, thereby forming a liquid crystal panel.
  • the opposite substrate is, for example, a color filter substrate, and the color filter substrate includes a black matrix defining a plurality of pixel units arranged in a matrix.
  • the pixel unit of the color filter substrate corresponds to the pixel unit of the array substrate. Since the above double gate structure is used, the area of the black matrix (Black Matrix, ⁇ ) on the color filter substrate can be greatly reduced in the obtained liquid crystal panel (because the number of data lines is reduced on the corresponding array substrate), The aperture ratio is greatly increased.
  • Both of the above array substrates may further include a common electrode line (not shown), and the common electrode 9 and the common electrode line are connected through the via holes at the periphery of the array substrate.
  • the common electrode 9 may also extend above the gate lines above and/or below the pixel unit in which it is located. Such a design can shield the influence of the signal on the gate line on the pixel electrode, thereby reducing the width of the black matrix above the gate line and increasing the aperture ratio; the exemplary structure can be seen in FIG. 1 or FIG. 1 shows only two pixel units adjacent to each other on the array substrate. As shown in FIG. 1, the common electrode 9 of the lower pixel unit extends above the gate line 321, and the common electrode 9 of the upper pixel unit extends. Up to the top of the gate line 322; FIG. 1B is a schematic cross-sectional view of B1-B1 of FIG.
  • This embodiment provides a method for manufacturing an array substrate, including the following steps:
  • S101 forming a pattern including a pixel electrode by a first patterning process, forming a pattern including a gate line and a gate of a thin film transistor by a second patterning process; or forming a gate including a gate line and a thin film transistor by a first patterning process
  • the pattern is formed by a second patterning process including a pattern of pixel electrodes.
  • step S101 The two methods in step S101 are selectable.
  • the following is an example in which a pattern including a pixel electrode is formed by a first patterning process, and a pattern including a gate line and a gate of a thin film transistor is formed by a second patterning process.
  • FIG. 2 is a schematic plan view showing the first patterning process of the array substrate according to the embodiment of the present invention
  • FIG. 2A is a cross-sectional view taken along line A2-A2 of FIG.
  • a pixel electrode layer is deposited on the base substrate 1 of a blank glass substrate by sputtering or thermal evaporation.
  • the pixel electrode layer may be a transparent conductive film, and the transparent conductive film may be Indium Tin Oxide ( ⁇ ). Or indium oxide ( ⁇ ) and so on.
  • ⁇ Indium Tin Oxide
  • ⁇ indium oxide
  • FIG. 3 is a schematic plan view showing the second patterning process of the array substrate according to the embodiment of the present invention
  • FIG. 3B is a cross-sectional view in the direction of ⁇ 3- ⁇ 3 in FIG.
  • a gate metal film is deposited on the substrate 1 by sputtering or thermal evaporation.
  • the gate metal film a single layer film of a metal such as Cr, W, Ti, Ta, Mo, Al, Cu, or an alloy thereof may be used, and the gate metal film may also be composed of a plurality of metal thin films.
  • the gate metal film is etched by a second patterning process using a conventional mask to form a pattern of the gate line 321 and the gate line 322 and the gate 31 of the thin film transistor on the base substrate 1.
  • the gate electrode 31 of the thin film transistor is directly connected to the gate line 321 or 322, that is, integrally formed.
  • This step describes the process when implementing a dual gate structure design. It will be understood by those skilled in the art that when an array substrate of a normal (i.e., single gate structure) rather than a double gate structure is to be fabricated, it is only necessary to form a structure of a single gate line for one row of pixel cells.
  • step S102 a pattern including a gate insulating layer, an active layer, a data line, and a source and a drain of the thin film transistor is formed by a third patterning process.
  • the third patterning process may be, for example, a process of multiple etching in which a two-tone mask (e.g., a halftone or gray tone mask) may be used.
  • An example of the step S102 may include: sequentially forming a gate insulating layer 4, an active layer, and a source/drain metal film on the base substrate on which the step S101 is completed;
  • the photoresist in the semi-reserved region of the photoresist is completely removed by an ashing process, and the source-drain metal film in the region is exposed;
  • the source-drain metal film of the semi-reserved region of the photoresist is completely etched away by the second etching process to form a pattern including the source electrode 61, the drain electrode 62, the data line 63, and the channel region of the thin film transistor; removing the remaining photolithography gum.
  • FIG. 4 is a schematic plan view showing the third patterning process of the array substrate according to the embodiment of the present invention
  • FIG. 4A is a cross-sectional view taken along line A4-A4 of FIG.
  • the active layer film may be an oxide semiconductor film, an organic semiconductor film, or a laminate including a semiconductor film and a doped semiconductor film.
  • the active layer film includes the semiconductor film and the doped semiconductor film, the source/drain metal film of the semi-reserved region of the photoresist is completely etched by the second etching process, and the channel region is completely etched away. Doping the semiconductor film and etching away a portion of the thickness of the semiconductor film.
  • step S103 a pattern including a passivation layer is formed by a fourth patterning process.
  • FIG. 5 is a plan view showing a fourth patterning process of the array substrate according to an embodiment of the present invention
  • FIG. 5A is a cross-sectional view taken along line A5-A5 of FIG. 5.
  • An example of the step S103 includes: forming a passivation layer film on the base substrate completing step S102; forming a passivation layer and a gate insulating layer over the pixel electrode by a halftone or gray tone mask A via hole forms a via hole penetrating the passivation layer over the drain.
  • a passivation layer film may be deposited on the base substrate by a plasma enhanced chemical vapor deposition method, and the passivation layer film may be an oxide, a nitride or an oxynitride, and the corresponding reaction gas may be A mixed gas of SiH4, NH3, and N2 or a mixed gas of SiH2C12, NH3, and N2. Then use a halftone or gray tone mask, through the third patterning process, A via 82 penetrating the passivation layer and the gate insulating layer is formed over the pixel electrode, and a via 81 penetrating the passivation layer is formed over the drain as shown in FIG. 5A.
  • step S104 a pattern including a common electrode is formed by the fifth patterning process.
  • An example of the step S104 includes: forming a transparent conductive film on the base substrate completing the step S103; forming a pattern of the common electrode by a common masking method.
  • FIG. 1 is a plan view showing the fifth patterning process of the array substrate of the present invention
  • FIG. 1A is a cross-sectional view taken along line A1-A1 of FIG. 5
  • FIG. 1B is a cross-sectional view taken along line B1-B1 of FIG.
  • a transparent conductive film is deposited, for example, by sputtering or thermal evaporation.
  • the conductive film is filled into the via 81 and the via 82 for realizing the connection of the pixel electrode 2 and the drain 62 of the thin film transistor, and the portion of the pixel electrode 2 and the drain 62 connected via the vias 81 and 82 is electrically conductive.
  • the film may be referred to as a connection electrode 91.
  • a pattern of the common electrode 9 and the connection electrode 91 is formed by the fifth patterning using a normal mask.
  • the transparent conductive film may be a single layer film of Indium Tin Oxide (ITO) or Indium Tin Oxide (IZO), or may be a composite film of ITO and IZO.
  • ITO Indium Tin Oxide
  • IZO Indium Tin Oxide
  • connection electrode 91 and the common electrode 9 may be formed of the same material in the same patterning process as described above; or may be implemented in different patterning processes using the same or different materials.
  • step S101 gate lines are formed above and below the pixel unit, and only one gate line is formed between each adjacent two rows of pixel units.
  • step S102 data lines are formed on both the left and right sides of the pixel unit, and one data line is formed between each adjacent two columns of pixel units.
  • gate lines are formed above and below the pixel unit, and two gate lines are disposed between each adjacent two rows of pixel units.
  • a data line is disposed on the left side or the right side of the pixel unit, and two columns of pixel units are included between each adjacent two data lines.
  • step S101 the gate of the thin film transistor is connected to the gate line above or below the pixel unit in which it is located, and in step S102, the source of the thin film transistor and the pixel unit on the left or right side thereof are realized.
  • the data lines are connected to achieve a Z-inverted pixel structure.
  • forming a pixel structure of z-inversion in this embodiment may include:
  • the source of the thin film transistor in the odd-numbered pixel unit of the same column is connected to one of the data lines on both sides of the column, and the source of the thin film transistor in the even-numbered pixel unit is connected to the data line on both sides of the column On the other data line, the source of the thin film transistor in the pixel unit of the same row in the adjacent two columns is connected to two different data lines;
  • Two pairs of pixel units of the same are alternately connected to the two gate lines above and below the pixel unit of the row through the gates of the thin film transistors included therein, and the pixel units connected to each of the gate lines are located in the same Row;
  • the gates of the thin film transistors of two adjacent and adjacent pixel cells between two adjacent data lines are respectively connected to two gate lines, and the sources are respectively connected to the two data lines.
  • a common electrode line may be formed while forming a gate line and a gate, and then the common electrode and the common electrode line are at the periphery of the array substrate in step S104. Connected through vias.
  • the formed common electrode may be extended over the gate line above and/or below the pixel unit where it is located to form a storage capacitor with the gate line.
  • the specific structure formed can be seen in Figure 1 or Figure 1B. 1 shows only two pixel units adjacent to each other on the array substrate. As shown in FIG. 1, the common electrode 9 of the lower pixel unit extends above the gate line 321, and the common electrode 9 of the upper pixel unit extends. Up to the top of the gate line 322; FIG. 1B is a schematic cross-sectional view of B1-B1 of FIG. 1, and also shows that the common electrode 9 of the upper pixel unit extends above the gate line 322. Since the common electrode extends above the gate line, the overlapping structure can shield the influence of the signal on the gate line on the pixel electrode, thereby reducing the width of the black matrix above the gate line and increasing the aperture ratio.
  • This embodiment provides a liquid crystal panel, as shown in FIG. 7, comprising an array substrate 11, a color filter substrate 14, and a liquid crystal 12 filled therebetween.
  • the array substrate 11 and the color filter substrate 14 are opposed to each other to form a liquid crystal cell, and a plurality of spacers (not shown) are used to maintain the spacing therebetween.
  • the array substrate used is the array substrate provided in the above embodiment.
  • the color film substrate 14 includes a black matrix 10 and a color resin 13.
  • the black matrix 10 defines pixel regions of the color filter substrate 14, which correspond to pixel regions on the array substrate 11.
  • a position corresponding to the gate line, a position corresponding to the data line, and two columns of images between adjacent two data lines The positions of the element cell boundaries are each provided with a black matrix including a black matrix 101, a black matrix 102, and a black matrix 103, as shown in FIG.
  • the width of the black matrix 102 corresponding to the position of the data line is 17-23 um
  • the width of the black matrix 103 corresponding to the position where the two columns of pixel units between the adjacent two data lines meet is 6-10 um.
  • the width of the black matrix 102 corresponding to the position of the data line is 20 um
  • the width of the black matrix 103 corresponding to the position where the two columns of pixel units between the adjacent two data lines meet is 8 um.
  • the aperture ratio can be maximized while ensuring the display effect (such as avoiding light leakage and ensuring display uniformity).
  • the width of the black matrix 101 it is not limited herein, and any width that can achieve its function is acceptable.
  • the overlapping structure can shield the influence of the signal on the gate line on the pixel electrode, thereby reducing the width of the black matrix 101 above the gate line and further increasing the opening ratio.
  • the embodiment provides a method of manufacturing a liquid crystal panel, which comprises the method of fabricating the array substrate described in the above embodiments.
  • the liquid crystal panel manufactured is, for example, as shown in Figs. 6 and 7.
  • the method for manufacturing a liquid crystal panel further includes a method of manufacturing a color filter substrate, wherein a position of the gate line, a position corresponding to the data line, and corresponding two adjacent data are on the color filter substrate
  • a black matrix 10 is disposed at a position where two columns of pixel units are in a boundary between the lines.
  • the width of the black matrix 102 corresponding to the position of the data line is 17-23 um
  • the width of the black matrix 103 corresponding to the position where the two columns of pixel units between the adjacent two data lines meet is 6-10 um.
  • the width of the black matrix 102 corresponding to the position of the data line is 20 um
  • the width of the black matrix 103 corresponding to the position where the two columns of pixel units between the adjacent two data lines meet is 8 um.
  • the aperture ratio can be maximized while ensuring the display effect (such as avoiding light leakage and ensuring display uniformity).
  • the width of the black matrix 101 it is not limited herein, and any width that can achieve its function is acceptable.
  • the overlapping structure can shield the influence of the signal on the gate line on the pixel electrode, thereby reducing the width of the black matrix 101 above the gate line and further increasing the opening ratio.
  • the present embodiment provides a display device using the liquid crystal panel described in the above embodiments.
  • the display device can be a mobile phone, a tablet, a monitor, a television, a laptop, a netbook, and the like.
  • the display device further includes a backlight disposed opposite to a light incident surface of the liquid crystal panel.
  • the backlight may be a CCFL backlight or an LED backlight, preferably an LED backlight. LED backlights have lower power consumption and better image color display.
  • Embodiments of the present invention provide a method of fabricating a display device, including the method of fabricating a liquid crystal panel described in the above embodiments.
  • the display device may be a mobile phone, a tablet computer, a monitor, a television, a notebook computer, a netbook, or the like.
  • the backlight is further disposed on the light incident surface of the liquid crystal panel, and the backlight may be a CCFL backlight or an LED backlight, preferably an LED backlight.
  • LED backlights can have lower power consumption and better image color display.
  • the pixel unit structure provided by the embodiment of the invention has a larger viewing angle than the pixel unit structure of the ordinary TN mode; and has a higher aperture ratio and a more stable process than the pixel unit structure of the common ADS.
  • the 4Mask method using a two-tone mask is used to realize the advantages; further, the dual gate structure realized by the common ADS can also extend the common electrode to the top of the gate line, and the influence of the signal on the shield gate line on the pixel electrode. Further, the width of the black matrix above the gate line is reduced to increase the aperture ratio.
  • the I-ADS array substrate has a larger viewing angle than the conventional TN mode array substrate, and further realizes the double gate structure on the basis of I-ADS.
  • the Z-inversion array substrate is advantageous for reducing power consumption; further, the double gate structure realized by the common ADS can extend the common electrode to the top of the gate line, and the signal pair on the shielded gate line The influence of the pixel electrode further reduces the width of the black matrix above the gate line, increases the aperture ratio, and improves the display quality.
  • the liquid crystal panel and the manufacturing method thereof, the display device and the manufacturing method thereof include the above array substrate and a manufacturing method thereof, and correspondingly, the aperture ratio can be improved while the power consumption is reduced, thereby improving the display. quality.

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Abstract

一种像素单元、阵列基板、液晶面板及阵列基板的制造方法，该像素单元包括薄膜晶体管（100）、像素电极（2）和公共电极（9），薄膜晶体管（100）包括栅极（31）、设置于栅极（31）之上的栅绝缘层（4）、设置于栅绝缘层（4）之上有源层（5）、设置于有源层（5）之上的源极（61）和漏极（62）、以及设置于源极（61）和漏极（62）之上的钝化层（7）。公共电极（9）直接设置在钝化层（7）之上；像素电极（2）设置在钝化层（7）之下，并与薄膜晶体管（100）的漏极（62）相连接。还提供了一种包括该像素单元的阵列基板的制造方法。包括该像素单元的阵列基板及液晶面板均可以提高可视角度，并降低功耗，提高开口率，进而提升显示品质。

Description

像素单元、 阵列基板、 液晶面板及阵列基板的制造方法 技术领域
本发明的实施例涉及一种像素单元、 阵列基板、 液晶面板、 显示装置及 其制造方法。 背景技术
液晶显示器（Liquid Crystal Display, LCD )具有体积小、 功耗低、 无辐 射等特点， 现已占据了平面显示领域的主导地位。 薄膜晶体管液晶显示器 ( Thin Film Transistor-Liquid Crystal Display, TFT-LCD )是目前主流的液晶 显示器。
液晶显示器的液晶面板包括阵列基板和彩膜基板。阵列基板上设有栅线， 垂直于所述栅线设有数据线， 所述栅线和所述数据线彼此交叉限定有像素区 域； 所述像素区域内设有薄膜晶体管和像素电极； 所述薄膜晶体管的栅极与 所述栅线连接、 源极与所述数据线连接、 漏极与所述像素电极连接。
阵列基板是液晶显示面板的关键部件， 而由薄膜晶体管和像素电极等构 成的像素结构则是阵列基板的重要组成部分。 传统的 TN模式的液晶显示器 具有视角相对较小， 无法满足高品质显示需求等特点。
高级超维场转换技术（Advanced Super Dimension Switch, ADS ), 通过 在同一平面内于狭缝电极的边缘所产生的电场以及狭缝电极层与板状电极层 之间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取 向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超维场转换技术可以提高 TFT-LCD产品的画面品质， 具有高分辨率、 高透过率、低功耗、 宽视角、 高开口率、低色差、 无挤压水波紋（push Mura ) 等优点。
传统的 ADS 的像素单元结构为： 包括一个薄膜晶体管和像素电极以及 公共电极。 像素电极位于公共电极之上； 像素电极位于最上层与薄膜晶体管 的漏极相连接， 公共电极位于最底层， 与公共电极线相连。 虽然传统的 ADS 型液晶面板相对于传统的 TN型， 具有高分辨率、 高透过率、 低功耗、 宽视 角、 高开口率、 低色差、 无挤压水波紋（push Mura )等优点， 但是传统的 ADS由于自身的特点， 其开口率仍然较小， 无法满足高品质显示的需求。 发明内容
本发明的实施例对传统的 ADS进行了改进， 希望提供一种新的 I-ADS 形式的像素单元， 阵列基板、 液晶面板、 显示装置及其制造方法， 以提高像 素开口率、 降低功耗、 并提高显示品质。
本发明的一个方面提供了一种像素单元， 包括薄膜晶体管、 像素电极和 公共电极， 所述薄膜晶体管包括栅极、 设置于所述栅极之上的栅绝缘层、 设 置于所述栅绝缘层之上有源层、 设置于所述有源层之上的源极和漏极、 以及 设置于所述源极和漏极之上的钝化层， 其中， 所述公共电极直接设置在所述 钝化层之上； 所述像素电极设置在所述钝化层之下， 并与所述薄膜晶体管的 漏极相连接。
例如， 所述像素电极与所述栅极设置在同一层， 所述钝化层和所述像素 电极之间设置有栅绝缘层， 与所述公共电极同层的金属通过两个过孔分别连 接所述薄膜晶体管的漏极和所述像素电极。
例如， 所述公共电极为狭缝状， 所述像素电极为板状。
例如， 所述与所述公共电极同层的用于连接像素电极和薄膜晶体管的漏 极的连接电极与所述公共电极为同一材料。
例如， 所述像素电极和 /或所述公共电极为透明电极。
例如， 所述公共电极为 ITO或 IZO的单层膜， 或者为 ITO和 IZO组成 的复合膜。
例如， 所述钝化层为氧化物、 氮化物、 氮氧化物或有机树脂。
本发明的另一方面还提供了一种阵列基板， 包括基底基板， 和所述基底 基板上设置的多条栅线和多条数据线， 其中， 所述多条数据线垂直于所述多 条栅线， 所述栅线和所述数据线彼此交叉限定了多个像素区域， 其中， 所述 多个像素区域每个包括上述任一所述的像素单元， 所述像素单元每个的薄膜 晶体管的栅极与相应的栅线连接， 所述薄膜晶体管的源极与相应的数据线连 接。。
例如， 每行所述像素单元的上方和下方均设置有一条栅线， 所述像素单 元的左侧和右侧均设置有一条数据线， 且每相邻两行的像素单元之间仅设置 有一条栅线， 每相邻两列像素单元之间设置有一条数据线。
或者， 例如， 所述像素单元的上方和下方均设置有一条栅线， 且每相邻 两行所述像素单元之间设置有两条栅线； 每列所述像素单元的左侧或右侧设 置有一条数据线， 且每相邻两条数据线之间包括两列所述像素单元。
例如， 每个所述像素单元的所述薄膜晶体管的栅极与其所在的像素单元 上方或下方的一条栅线连接， 所述薄膜晶体管的源极与其所在的像素单元左 侧或右侧的一条数据线连接， 实现 Z反转 ( Z-inversion ) 的像素结构。
例如， 所述 Z反转的像素结构包括：
同列的奇数个像素单元中的薄膜晶体管的源极连接在该列两侧的数据线 中的一条数据线上， 偶数个像素单元中的薄膜晶体管的源极连接在该列两侧 的数据线中另一条数据线上， 且相邻两列中处于同一行的像素单元中的薄膜 晶体管的源极连接不同的两条数据线；
同行的所述像素单元两两一组通过其包括的薄膜晶体管的栅极交替地分 别连接在位于该行像素单元上方和下方的两条栅线上， 且每条所述栅线连接 的像素单元位于同一行；
两条相邻数据线之间的、 两个同行且相邻的像素单元的薄膜晶体管的栅 极分别连接在两条栅线上， 源极分别连接在所述两条数据线上。
例如， 所述阵列基板还包括公共电极线， 所述公共电极与所述公共电极 线在阵列基板的周边通过过孔相连接。
例如， 每个所述像素单元的所述公共电极延伸至其所在像素单元的上方 和 /或下方的一条栅线的上方， 与所述一条栅线形成存储电容。
本发明的另一个方面还提供了一种液晶面板， 包括彩膜基板和上述任一 的阵列基板， 所述彩膜基板上包括黑矩阵， 其中， 在所述彩膜基板上， 对应 所述多条栅线的位置、 对应所述多条数据线的位置以及对应相邻两条数据线 之间的两列像素单元交界的位置， 均设置有黑矩阵。
例如， 对应所述数据线的位置的黑矩阵的宽度为 17-23um, 对应相邻两 条数据线之间的两列像素单元交界的位置的黑矩阵的宽度为 6-10um。
优选地， 对应所述数据线的位置的黑矩阵的宽度为 20um, 对应相邻两 条数据线之间的两列像素单元交界的位置的黑矩阵的宽度为 8um。 本发明的另一个实施例还提供了一种显示装置， 包括上述的液晶面板。 例如， 该显示装置还包括与所述液晶面板的入光面相对设置的背光源。 所述背光源例如为 LED背光源。
本发明的另一个方面还提供了一种阵列基板的制造方法， 包括： S101、 通过第一次构图工艺形成包括像素电极的图形， 通过第二次构图 工艺形成包括多条栅线和多个像素单元的薄膜晶体管栅极的图形；
或者 , 通过第一次构图工艺形成包括多条栅线和多个像素单元的薄膜晶 体管栅极的图形， 通过第二次构图工艺形成包括像素电极的图形，
5102、 通过第三次构图工艺形成包括栅绝缘层、 有源层、 多条数据线以 及所述薄膜晶体管的源极和漏极的图形；
5103、 通过第四次构图工艺形成包括钝化层的图形；
5104、 通过第五次构图工艺形成包括公共电极的图形。
例如， 所述步骤 S102包括：
在完成步骤 S101 的基底基板上依次形成栅绝缘层、 有源层和源漏金属 薄膜；
在源漏金属薄膜上涂敷一层光刻胶；
釆用半色调或灰色调掩模板对光刻胶进行曝光， 使光刻胶形成光刻胶完 全去除区域、 光刻胶完全保留区域和光刻胶半保留区域， 其中光刻胶完全保 留区域对应于数据线、 源电极和漏电极的图形所在区域， 光刻胶半保留区域 对应于薄膜晶体管的沟道区域， 光刻胶完全去除区域对应于上述图形以外区 域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶完全 去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 漏金属薄膜；
通过灰化工艺完全去除光刻胶半保留区域的光刻胶， 暴露出该区域的源 漏金属薄膜；
通过第二次刻蚀工艺完全刻蚀掉光刻胶半保留区域的源漏金属薄膜， 形 成包括像素电极、 数据线、 源电极、 漏电极和薄膜晶体管沟道区域的图形； 去除剩余的光刻胶。
例如， 所述有源层薄膜包括半导体薄膜和掺杂半导体薄膜， 所述通过第 二次刻蚀工艺完全刻蚀掉光刻胶半保留区域的源漏金属薄膜， 还包括完全刻 蚀掉沟道区域的掺杂半导体薄膜和刻蚀掉部分半导体薄膜。
例如， 所述步骤 S103包括：
在完成步骤 S102的基板上形成钝化层薄膜；
通过半色调或灰色调掩模的方式， 在像素电极的上方形成穿透钝化层和 栅绝缘层的过孔， 在漏极的上方形成穿透钝化层的过孔。
例如， 所述步骤 S104包括：
在完成步骤 S103的基板上形成透明导电薄膜；
通过普通掩摸的方式， 形成公共电极的图形。
例如， 所述步骤 S101 中形成的多条栅线包括： 在每行像素单元的上方 和下方均形成有一条栅线，且每相邻两行的像素单元之间仅形成有一条栅线。
例如， 所述步骤 S102 中形成的数据线包括： 在像素单元的左侧和右侧 均形成有一条数据线， 且每相邻两列像素单元之间均形成有一条数据线。
例如， 或者所述步骤 S101 中形成的栅线包括： 在每行像素单元的上方 和下方均形成有一条栅线， 且每相邻两行像素单元之间设置有两条栅线。
例如， 或者所述步骤 S102 中形成的数据线包括： 在每列像素单元的左 侧或右侧设置有一条数据线， 且每相邻两条数据线之间包括两列像素单元。
例如， 在步骤 S101 中实现每个像素单元的薄膜晶体管的栅极与其所在 的像素单元上方或下方的一条栅线连接， 在步骤 S102 中实现每个像素单元 的薄膜晶体管的源极与其所在的像素单元左侧或右侧的一条数据线连接， 以 实现 Z反转的像素结构。
同样例如， 所述 Z反转的像素结构包括：
同列的奇数个像素单元中的薄膜晶体管的源极连接在该列两侧的数据线 中的一条数据线上， 偶数个像素单元中的薄膜晶体管的源极连接在该列两侧 的数据线中另一条数据线上， 且相邻两列中处于同一行的像素单元中的薄膜 晶体管的源极连接不同的两条数据线；
同行的像素单元两两一组通过其包括的薄膜晶体管的栅极交替地分别连 接在位于该行像素单元上方和下方的两条栅线上， 且每条所述栅线连接的像 素单元位于同一行；
两条相邻数据线之间的、 两个同行且相邻的像素单元的薄膜晶体管的栅 极分别连接在两条栅线上， 源极分别连接在所述两条数据线上。
例如， 在步骤 S101 中形成栅线和栅极的同时还形成公共电极线， 在步 骤 S104中使公共电极与所述公共电极线在阵列基板的周边通过过孔相连接。
例如， 在步骤 S104 中， 形成的公共电极延伸至其所在像素单元的上方 和 /或下方的一条栅线的上方， 与所述一条栅线形成存储电容。
本发明的另一方面还提供了一种液晶面板的制造方法， 包括上述的阵列 基板的制造方法。
例如， 还包括制造彩膜基板的方法， 在所述彩膜基板上， 对应所述栅线 的位置、 对应所述数据线的位置以及对应相邻两条数据线之间的两列像素单 元交界的位置， 均设置有黑矩阵。
同样地， 例如， 对应所述数据线的位置的黑矩阵的宽度为 17-23um, 对 应相邻两条数据线之间的两列像素单元交界的位置的黑矩阵的宽度为 6-10um。
优选地， 对应所述数据线的位置的黑矩阵的宽度为 20um, 对应相邻两 条数据线之间的两列像素单元交界的位置的黑矩阵的宽度为 8um。
本发明的另一方面还提供了一种显示装置的制造方法， 包括上述的液晶 面板的制造方法。
例如， 该显示装置还包括在所述液晶面板的入光面相对设置背光源。 例 如， 所述背光源为 LED背光源。
本发明实施例提供的像素单元结构， 相对于普通 TN模式的像素单元结 构， 具有更大的可视角度； 相对于普通 ADS 的像素单元结构， 则具有开口 率更高、工艺过程更加稳定及可选用使用双色调掩膜的 4Mask方式来实现等 优点。 例如， 其相对普通 ADS 实现的双栅结构， 可使公共电极延伸到栅线 上方， 屏蔽栅线上的信号对像素电极的影响， 减小栅线上方黑矩阵的宽度， 提高开口率。 根据本发明实施例提供的阵列基板及其制造方法， 所得到的 I-ADS阵列基板， 相对传统 TN模式的阵列基板， 具有更大的可视角度， 而 在 I-ADS基础上实现双栅结构和 Z反转的阵列基板， 则有利于降低功耗。 例 如， 其相对普通 ADS 实现的双栅结构， 可以使公共电极延伸到栅线上方， 屏蔽栅线上的信号对像素电极的影响， 进而减小栅线上方黑矩阵的宽度， 提 高开口率， 进而提升了显示品质。 本发明实施例提供的液晶面板及其制造方 法， 显示装置及其制造方法， 包括了上述的阵列基板及其制造方法，相应地， 均可以在降低功耗的同时， 提高开口率， 进而提升显示品质。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例阵列基板（像素单元） 的平面结构示意图； 图 1A为图 1中 A1-A1方向的截面图；
图 1B为图 1中 B1-B1方向的截面图；
图 2为本发明阵列基板第一次构图工艺后的平面结构示意图；
图 2A为图 2中 A2-A2方向的截面图；
图 3为本发明阵列基板第二次构图工艺后的平面结构示意图；
图 3A为图 3中 A3-A3方向的截面图；
图 4为本发明阵列基板第三次构图工艺后的平面结构示意图；
图 4A为图 4中 A4-A4方向的截面图；
图 5为本发明阵列基板第四次构图工艺后的平面结构示意图；
图 5A为图 5中 A5-A5方向的截面图；
图 6为本发明实施例的阵列基板的一种示意图；
图 7为本发明实施例的液晶面板的示意图；
图 8为本发明实施例的阵列基板的又一种示意图。
附图标记：
1-基板； 2-像素电极； 31-栅极； 321-栅线 1 ; 322-栅线 2; 4-栅绝缘层； 5-有源层； 61-源极； 62-漏极； 63-数据线； 7-钝化层； 81-过孔 1 ; 82-过孔 2; 9-公共电极； 91-连接电极； 10-黑矩阵； 11-阵列基板； 12-液晶； 13-彩色树脂； 14-彩膜基板； 100-薄膜晶体管。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素区域,每个像素区域包括像素单元， 而像素单元包括作为开关元件的薄膜晶体管和用于控制液晶的排列的像素电 极和公共电极。 每个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形 成， 源极与相应的数据线电连接或一体形成， 漏极与相应的像素电极电连接 或一体形成。 下面的描述主要针对单个或多个像素单元进行， 但是其他像素 单元可以相同地形成。
实施例一
本发明实施例提供了一种像素单元，下面参照图 1和图 la来说明本实施 例中像素单元的结构。 需要明确的是， 本实施例中定义的像素单元， 并不包 括栅线和数据线。 所述像素单元， 在适当地设置栅线和数据线之后， 可以用 于形成普通的阵列基板， 或者形成双栅结构的阵列基板。
图 1所示为本发明实施例像素单元的平面结构示意图， 其示出了上下相 邻的两个像素单元； 图 1A所示为图 1中 A1-A1方向的截面图， 图 1B为图 1 中 B1-B1截面示意图， 即图 1A和图 1B为一个像素单元的不同切割方向的 截面示意图。
本实施例中的像素单元包括薄膜晶体管 100、 像素电极 2和公共电极 9。 所述薄膜晶体管 100包括栅极 31、设置于栅极 31之上的栅绝缘层 4、设置于 栅绝缘层 4之上有源层 5、设置于所述有源层 5之上的源极 61和漏极 62、以 及设置于源极 61和漏极 62之上的钝化层 7。公共电极 9直接设置在钝化层 7 之上； 像素电极 2设置在钝化层 7之下， 并与所述薄膜晶体管 100的漏极 62 相连接。 像素电极 2可以直接设置在钝化层 7之下， 像素电极 2也设置在钝 化层 7之下， 同时钝化层 7和像素电极 2之间还存在其他中间膜层， 比如栅 绝缘层 4。 当像素电极 2直接设置在钝化层 7之下时， 其可以直接搭接在漏 极的下面， 或者通过其他方式与漏极连接。 本实施例的像素单元， 与传统的 ADS的区别在于， 像素电极和公共电极的上下位置关系发生了互换， 因此可 称为 I-ADS ( Inverse-ADS )型的像素单元。 优选地，在本实施例的一个示例中，像素电极 2与栅极 3设置在同一层， 钝化层 7和像素电极 2之间设置有栅绝缘层 4, 与公共电极 9同层的连接电 极 91通过过孔 81和过孔 82分别连接薄膜晶体管 100的漏极 62和像素电极 2。 本实施例中，像素电极 2与栅极 3设置在同一层，是指像素电极 2与栅线 3的位置关系，并非限定两者由同层的同一种材料形成。像素电极 2与栅极 3 可以为相同材料， 也可以为不同材料。
在本实施例中， 公共电极 9为狭缝状、 像素电极 2为板状， 也可以是公 共电极 9和像素电极 2均为狭缝状。 优选地， 公共电极 9为狭缝状， 像素电 极 2为板状， 这一形状组合的像素电极 2和公共电极 9在本实施例的像素单 元的结构中更容易实现。
进一步地，与所述公共电极 9同层的连接电极 91与公共电极 9为同一材 料；优选地，连接电极 91与公共电极 9为在同一层并且在相同的工序中形成。
优选地， 像素电极 2和 /或公共电极 9为透明电极。
在本实施例中， 公共电极 9可以为氧化铟锡（ ITO )或氧化铟辞（ IZO ) 的单层膜， 或者为 ITO和 IZO组成的复合膜。
在本实施例中， 钝化层 7可以例如为氧化物、 氮化物、 氮氧化物或有机 树脂。 优选地， 在本实施例中， 钝化层 7釆用有机树脂材料， 有机树脂本身 的良好的透明度和绝缘特性， 将使最终的显示器件具有更好的开口率及更好 的显示效果。
本发明实施例提供的像素单元，将公共电极 9直接设置在钝化层 7之上， 将像素电极 2设置在钝化层 7之下并与所述薄膜晶体管的漏极 62相连接,相 对于普通 TN模式的像素单元具有更大的可视角度。 并且， 本发明实施例提 供的像素单元相对于普通 ADS 的像素单元， 具有开口率更高、 工艺过程更 加稳定， 可以选用使用双色调掩膜的 4Mask方式来制备等优点； 进一步地， 其相对普通 ADS 实现的双栅结构， 可以使公共电极延伸到栅线上方， 屏蔽 栅线上的信号对像素电极的影响， 进而减小栅线上方黑矩阵的宽度， 提高开 口率， 进而提高显示品质。
实施例二
本实施例提供一种阵列基板， 包括基底基板、 所述基板上设有栅线、 垂 直于所述栅线设有数据线。 所述栅线和所述数据线之间限定有像素区域， 所 述像素区域包括上述实施例一中所述的像素单元（可参见图 1 )。 所述薄膜晶 体管的栅极与所述栅线连接， 所述薄膜晶体管的源极与所述数据线连接。 需 要指出的是，包括了上述像素单元的阵列基板，可以称为 I-ADS型阵列基板； 其与传统的 ADS型阵列基板相比， 像素电极 2和公共电极 9的上下位置关 系发生了变化。
本实施例的阵列基板的一个示例中， 栅线和数据线彼此交叉限定了一个 阵列， 每行的多个像素单元的上方和下方均设置有栅线， 每个像素单元的左 侧和右侧均设置有数据线，且每相邻两行的像素单元之间仅设置有一条栅线， 每相邻两列像素单元之间设置有一条数据线。每个像素单元为 I-ADS型的像 素单元。
本实施例的阵列基板的另一个示例中， 每行的多个像素单元的上方和下 方均设置有栅线， 且每相邻两行所述像素单元之间设置有两条栅线 321 和 322,如图 1所示。 图 1只示出了阵列基板上的上下相邻的两个像素单元。在 每列像素单元的左侧或右侧设置有数据线， 且每相邻两条数据线之间包括两 列所述像素单元。 此为在 I-ADS基础上实现双栅 ( Dual-gate )结构的阵列基 板。 关于实现双栅结构后整个基板的像素排布情况， 可参见图 8所示的示意 图； 需要指出的是， 图 8仅为示意， 并未画出每个像素单元的具体像素结构。
进一步地， 所述薄膜晶体管的栅极与其所在的像素单元上方或下方的栅 线连接， 所述薄膜晶体管的源极与其所在的像素单元左侧或右侧的数据线连 接， 实现 Z反转 ( Z-inversion ) 的像素结构。
本实施例中实现 Z反转的像素结构的示意图如图 8所示， 可以通过下面 的形式实现。 在阵列基板中， 同列的奇数个像素单元中的薄膜晶体管的源极 连接在该列两侧的数据线中的一条数据线上， 偶数个像素单元中的薄膜晶体 管的源极连接在该列两侧的数据线中另一条数据线上， 且相邻两列中处于同 一行的像素单元中的薄膜晶体管的源极连接不同的两条数据线。 同行的所述 像素单元两两一组通过其包括的薄膜晶体管的栅极交替地分别连接在位于该 行像素单元上方和下方的两条栅线上， 且每条所述栅线连接的像素单元位于 同一行； 并且， 两条相邻数据线之间的、 两个同行且相邻的像素单元的薄膜 晶体管的栅极分别连接在两条栅线上， 源极分别连接在所述两条数据线上。
在本实施例中， 双栅结构的示例性的具体结构设计如图 1所示， 其中标 号 321为栅线 1 , 322为栅线 2, 这形成了双栅结构。 在本实施例中釆用双栅 结构和 Z-反转设计的阵列基板， 可以参考图 8来理解。 Z-反转可以通过控制 同一根数据线控制其左右两边的像素， 来达到降低功耗及提高显示效果的目 的。 结合双栅结构设计后， 每一根数据线， 可影响到其左右各两列的像素。
阵列基板与对置基板彼此对置以形成液晶盒， 在液晶盒中填充有液晶材 料， 由此形成液晶面板。该对置基板例如为彩膜基板，彩膜基板包括黑矩阵， 该黑矩阵定义了排列为矩阵的多个像素单元。 彩膜基板的像素单元对应于阵 列基板的像素单元。 由于釆用了上述双栅结构， 所得到的液晶面板中， 彩膜 基板上的黑矩阵（ Black Matrix , ΒΜ ) 的面积可得以大大减少 （因为对应的 阵列基板上减少了数据线的数量）， 使得开口率大大增加。
上述两种阵列基板，还都可以包括公共电极线（图中未示出 ), 所述公共 电极 9与所述公共电极线在阵列基板的周边通过过孔相连接。
进一步地， 在本实施例提供的两种阵列基板中， 公共电极 9还可以延伸 至其所在像素单元的上方和 /或下方的栅线的上方。此种设计可以屏蔽栅线上 的信号对像素电极的影响， 进而减小栅线上方黑矩阵的宽度， 提高开口率； 该示例性的结构可参见图 1或者图 1Β。图 1只示出了阵列基板上的上下相邻 的两个像素单元， 如图 1所示， 下方的像素单元的公共电极 9延伸到了栅线 321的上方， 上方的像素单元的公共电极 9延伸到了栅线 322的上方； 图 1B 为图 1中 B1-B1截面示意图，也示出了上方的像素单元的公共电极 9延伸到 了栅线 322的上方。 由于公共电极 9延伸到了栅线的上方， 可以屏蔽栅线上 的信号对像素电极的影响。 这进而可以减小彩膜基板上对应于栅线的黑矩阵 的宽度， 从而提高开口率。
实施例三
本实施例提供一种阵列基板的制造方法， 包括如下步骤：
S101、 通过第一次构图工艺形成包括像素电极的图形， 通过第二次构图 工艺形成包括栅线和薄膜晶体管栅极的图形； 或者， 通过第一次构图工艺形 成包括栅线和薄膜晶体管栅极的图形， 通过第二次构图工艺形成包括像素电 极的图形。
S102、 通过第三次构图工艺形成包括栅绝缘层、 有源层、 数据线以及薄 膜晶体管的源极和漏极的图形。 5103、 通过第四次构图工艺形成包括钝化层的图形。
5104、 通过第五次构图工艺形成包括公共电极的图形。
下面， 结合图 2-图 5具体介绍本实施例的阵列基板的一个示例的制造方 法。
步骤 S101 中的两种方式是可以选择的， 下面以通过第一次构图工艺形 成包括像素电极的图形， 通过第二次构图工艺形成包括栅线和薄膜晶体管栅 极的图形为例， 进行阐述。
如图 2所示为本发明实施例阵列基板第一次构图工艺后的平面示意图， 图 2A为图 2中 A2-A2方向的截面图。 例如通过溅射或者热蒸发的方法在例 如空白玻璃基板的基底基板 1上沉积像素电极层， 所述像素电极层可以为透 明导电薄膜， 透明导电薄膜可以为氧化铟锡（ Indium Tin Oxide , ΙΤΟ )或氧 化铟辞（ΙΖΟ )等。 所形成的形状请参考图 2。 这可以为釆用普通掩模板， 通 过第一次构图工艺形成需要的像素电极 2的图案。
如图 3所示为本发明实施例阵列基板第二次构图工艺后的平面示意图， 图 3Α为图 3中 Α3-Α3方向的截面图。 例如釆用溅射或热蒸发的方法在基底 基板 1上沉积一层栅金属薄膜。 栅金属薄膜可以使用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属或其合金的单层膜， 栅金属薄膜也可以由多层金属薄膜组成。 然后， 釆用普通掩模板， 通过第二次构图工艺对栅金属薄膜进行刻蚀， 在基 底基板 1上形成栅线 321和栅线 322和薄膜晶体管的栅极 31的图形。薄膜晶 体管的栅极 31直接和栅线 321或 322连接， 即一体形成。
本步骤描述的是实现双栅结构设计时的工艺方法。 本领域的技术人员可 以理解， 当拟制造的为普通的 （即单栅结构） 而非双栅结构的阵列基板时， 只需形成用于一行像素单元的单根栅线的结构即可。
在步骤 S102 中， 通过第三次构图工艺形成包括栅绝缘层、 有源层、 数 据线以及薄膜晶体管的源极和漏极的图形。
第三次构图工艺例如可以是一个多次刻蚀的工艺， 其中可以使用双色调 掩模板 (例如半色调或灰色调掩模板 )。 步骤 S102的一个示例可以包括： 在完成步骤 S101的基底基板上依次形成栅绝缘层 4、有源层和源漏金属 薄膜；
在源漏金属薄膜上涂敷一层光刻胶； 釆用半色调或灰色调掩模板对光刻胶进行曝光， 使光刻胶形成光刻胶完 全去除区域、 光刻胶完全保留区域和光刻胶半保留区域， 其中光刻胶完全保 留区域对应于数据线、 源电极和漏电极的图形所在区域， 光刻胶半保留区域 对应于薄膜晶体管的沟道区域， 光刻胶完全去除区域对应于上述图形以外区 域； 显影处理后， 光刻胶完全保留区域的光刻胶厚度没有变化， 光刻胶完全 去除区域的光刻胶被完全去除， 光刻胶半保留区域的光刻胶厚度变薄； 漏金属薄膜；
通过灰化工艺完全去除光刻胶半保留区域的光刻胶， 暴露出该区域的源 漏金属薄膜；
通过第二次刻蚀工艺完全刻蚀掉光刻胶半保留区域的源漏金属薄膜， 形 成包括源电极 61、 漏电极 62、 数据线 63和薄膜晶体管沟道区域的图形； 去除剩余的光刻胶。
如图 4所示为本发明实施例阵列基板第三次构图工艺后的平面示意图， 图 4A为图 4中 A4-A4方向的截面图。
在本实施例中， 有源层薄膜可以是氧化物半导体薄膜， 可以是有机半导 体薄膜， 也可以是包括半导体薄膜和掺杂半导体薄膜的叠层。 当有源层薄膜 包括半导体薄膜和掺杂半导体薄膜时， 所述通过第二次刻蚀工艺完全刻蚀掉 光刻胶半保留区域的源漏金属薄膜， 还包括完全刻蚀掉沟道区域中的掺杂半 导体薄膜和刻蚀掉部分厚度的半导体薄膜。
在步骤 S103中， 通过第四次构图工艺形成包括钝化层的图形。
如图 5所示为本发明实施例阵列基板第四次构图工艺后的平面示意图， 图 5A为图 5中 A5-A5方向的截面图。 所述步骤 S103的一个示例包括： 在 完成步骤 S102 的基底基板上形成钝化层薄膜； 通过半色调或灰色调掩模的 方式， 在像素电极的上方形成穿透钝化层和栅绝缘层的过孔， 在漏极的上方 形成穿透钝化层的过孔。
进一步地， 本实施例中， 可以在基底基板上通过等离子体增强化学气相 沉积方法沉积钝化层薄膜， 钝化层薄膜可以釆用氧化物、 氮化物或者氮氧化 合物，对应的反应气体可以为 SiH4、 NH3、 N2的混合气体或 SiH2C12、 NH3、 N2的混合气体。 然后釆用半色调或灰色调掩模板， 通过第三次构图工艺， 在 像素电极的上方形成穿透钝化层和栅绝缘层的过孔 82,在漏极的上方形成穿 透钝化层的过孔 81 , 如图 5A所示。
在步骤 S104 中， 通过第五次构图工艺形成包括公共电极的图形。 所述 步骤 S104的一个示例包括： 在完成步骤 S103的基底基板上形成透明导电薄 膜； 通过普通掩摸的方式， 形成公共电极的图形。
如图 1 所示为本发明阵列基板第五次构图工艺后的平面示意图， 图 1A 为图 5中 A1-A1方向的截面图， 图 1B为图 1中 B1-B1方向的截面图。
在形成过孔 81和 82之后的基底基板上， 例如通过溅射或者热蒸发的方 法沉积透明导电薄膜。 此时， 导电薄膜填充到过孔 81和过孔 82中， 用于实 现像素电极 2与薄膜晶体管的漏极 62的连接，通过过孔 81和 82连接像素电 极 2和漏极 62的该部分导电薄膜可以称为连接电极 91。 例如釆用普通掩模 板， 通过第五次构图形成公共电极 9和连接电极 91的图形。本实施例中，透 明导电薄膜可以为氧化铟锡（Indium Tin Oxide, ITO )或氧化铟辞（IZO )的 单层膜， 也可以为 ITO和 IZO的复合膜。 本领域的技术人员可以理解， 连接 电极 91和公共电极 9可以如上所述在同一次构图工艺中，通过相同的材料形 成； 也可以釆用相同或不同材料， 在不同的构图工艺中实现。
以上， 仅为本实施例的一种典型的实现方法， 本领域的技术人员， 还可 以在其基础上， 结合公知常识和现有技术， 进行变形和改变， 或者根据需要 进行具体的像素结构设计。
例如， 在本实施例中， 在步骤 S101 中， 在像素单元的上方和下方均形 成有栅线， 且每相邻两行的像素单元之间仅形成有一条栅线。
例如， 在步骤 S102 中， 在像素单元的左侧和右侧均形成有数据线， 且 每相邻两列像素单元之间均形成有一条数据线。
或者， 例如， 在步骤 S101中， 在像素单元的上方和下方均形成有栅线， 且每相邻两行像素单元之间设置有两条栅线。
或者， 例如， 所述步骤 S102 中， 在像素单元的左侧或右侧设置有数据 线， 且每相邻两条数据线之间包括两列像素单元。
更进一步地， 例如， 在步骤 S101 中实现薄膜晶体管的栅极与其所在的 像素单元上方或下方的栅线连接， 在步骤 S102 中实现薄膜晶体管的源极与 其所在的像素单元左侧或右侧的数据线连接， 以实现 Z反转的像素结构。 例如， 在本实施中形成 z反转的像素结构， 可以包括：
同列的奇数个像素单元中的薄膜晶体管的源极连接在该列两侧的数据线 中的一条数据线上， 偶数个像素单元中的薄膜晶体管的源极连接在该列两侧 的数据线中另一条数据线上， 且相邻两列中处于同一行的像素单元中的薄膜 晶体管的源极连接不同的两条数据线；
同行的像素单元两两一组通过其包括的薄膜晶体管的栅极交替地分别连 接在位于该行像素单元上方和下方的两条栅线上， 且每条所述栅线连接的像 素单元位于同一行；
两条相邻数据线之间的、 两个同行且相邻的像素单元的薄膜晶体管的栅 极分别连接在两条栅线上， 源极分别连接在所述两条数据线上。
本领域的技术人员可以理解， 在步骤 S101 中， 例如， 在形成栅线和栅 极的同时还可以形成公共电极线， 然后在步骤 S104 中使公共电极与所述公 共电极线在阵列基板的周边通过过孔相连接。
进一步地， 在步骤 S104 中， 例如， 还可以使形成的公共电极延伸至其 所在像素单元的上方和 /或下方的栅线的上方， 与所述栅线形成存储电容。 形 成的具体结构可参见图 1或者图 1B。图 1只示出了阵列基板上的上下相邻的 两个像素单元，如图 1所示，下方的像素单元的公共电极 9延伸到了栅线 321 的上方， 上方的像素单元的公共电极 9延伸到了栅线 322的上方； 图 1B为 图 1中 B1-B1截面示意图， 也示出了上方的像素单元的公共电极 9延伸到了 栅线 322的上方。 由于公共电极延伸到了栅线的上方， 这种重叠结构可以屏 蔽栅线上的信号对像素电极的影响， 进而减小栅线上方黑矩阵的宽度， 提高 开口率。
实施例四
本实施例提供一种液晶面板， 如图 7所示， 包括阵列基板 11、 彩膜基板 14以及填充在二者之间的液晶 12。阵列基板 11和彩膜基板 14彼此对置以形 成液晶盒， 并且使用多个隔垫物（未示出） 以维持二者之间的间距。 所使用 的阵列基板为上述实施例所提供的阵列基板。 彩膜基板 14上包括黑矩阵 10 和彩色树脂 13。 黑矩阵 10限定了彩膜基板 14的像素区域， 这些像素区域与 阵列基板 11上的像素区域相对应。 而且， 在所述彩膜基板 14上， 对应所述 栅线的位置、 对应所述数据线的位置以及对应相邻两条数据线之间的两列像 素单元交界的位置， 均设置有黑矩阵， 包括黑矩阵 101、 黑矩阵 102和黑矩 阵 103 , 如图 6所示。 例如， 对应所述数据线的位置的黑矩阵 102的宽度为 17-23um,对应相邻两条数据线之间的两列像素单元交界的位置的黑矩阵 103 的宽度为 6-10um。
优选地， 对应所述数据线的位置的黑矩阵 102的宽度为 20um, 对应相 邻两条数据线之间的两列像素单元交界的位置的黑矩阵 103的宽度为 8um。 此时， 可以在保证显示效果（如避免漏光以及保证显示均匀性等） 的同时， 最大限度地提高开口率。
关于黑矩阵 101的宽度， 在此不做限定， 任何可以实现其作用的宽度均 可。 当使公共电极延伸到栅线上方时， 该重叠结构可以屏蔽栅线上的信号对 像素电极的影响， 因而可以减小栅线上方黑矩阵 101的宽度， 进一步提高开 口率。
实施例五
本实施例提供一种液晶面板的制造方法， 包括上述实施例所述的阵列基 板的制造方法。 所制造的液晶面板例如如图 6和图 7所示。
进一步地， 所述液晶面板的制造方法， 还包括制造彩膜基板的方法， 在 所述彩膜基板上， 对应所述栅线的位置、 对应所述数据线的位置以及对应相 邻两条数据线之间的两列像素单元交界的位置， 均设置有黑矩阵 10。 例如， 对应所述数据线的位置的黑矩阵 102的宽度为 17-23um, 对应相邻两条数据 线之间的两列像素单元交界的位置的黑矩阵 103的宽度为 6-10um。
优选地， 对应所述数据线的位置的黑矩阵 102的宽度为 20um, 对应相 邻两条数据线之间的两列像素单元交界的位置的黑矩阵 103的宽度为 8um。 此时， 可以在保证显示效果（如避免漏光以及保证显示均匀性等） 的同时， 最大限度地提高开口率。
关于黑矩阵 101的宽度， 在此不做限定， 任何可以实现其作用的宽度均 可。 当使公共电极延伸到栅线上方时， 该重叠结构可以屏蔽栅线上的信号对 像素电极的影响， 因而可以减小栅线上方黑矩阵 101的宽度， 进一步提高开 口率。
实施例六
本实施提供一种显示装置， 使用了上述实施例所述的液晶面板。 所述显 示装置， 可以为手机、 平板电脑、 监视器、 电视机、 笔记本电脑、 上网本等。 在所述显示装置中，还包括与所述液晶面板的入光面相对设置的背光源。 所述背光源可以为 CCFL背光源或者 LED背光源，优选为 LED背光源。 LED 背光可以具有更低的功耗和更好的图像色彩显示效果。
实施例七
本发明实施例提供一种显示器件的制造方法， 包括上述实施例所述的液 晶面板的制造方法。 所述显示装置， 可以为手机、 平板电脑、 监视器、 电视 机、 笔记本电脑、 上网本等。
在本实施例的显示装置的制造方法中， 还包括在所述液晶面板的入光面 相对设置背光源，所述背光源可以为 CCFL背光源或者 LED背光源，优选为 LED背光源。 LED背光可以具有更低的功耗和更好的图像色彩显示效果。
本发明实施例提供的像素单元结构， 相对于普通 TN模式的像素单元结 构， 具有更大的可视角度； 相对于普通 ADS 的像素单元结构， 则具有开口 率更高、工艺过程更加稳定及可选用使用双色调掩膜的 4Mask方式来实现等 优点； 进一步地， 其相对普通 ADS 实现的双栅结构， 还可以使公共电极延 伸到栅线上方， 屏蔽栅线上的信号对像素电极的影响， 进而减小栅线上方黑 矩阵的宽度， 提高开口率。
通过本发明实施例提供的阵列基板及其制造方法，所述 I-ADS阵列基板， 相对传统 TN模式的阵列基板， 具有更大的可视角度， 而且在 I-ADS基础上 进一步实现双栅结构和 Z反转（Z-inversion ) 的阵列基板， 则有利于降低功 耗； 进一步地， 其相对普通 ADS 实现的双栅结构， 可以使公共电极延伸到 栅线上方， 屏蔽栅线上的信号对像素电极的影响， 进而减小栅线上方黑矩阵 的宽度， 提高开口率， 进而提升了显示品质。
本发明实施例提供的液晶面板及其制造方法， 显示装置及其制造方法， 包括了上述的阵列基板及其制造方法， 相应地， 均可以在降低功耗的同时， 提高开口率， 进而提升显示品质。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种像素单元， 包括： 薄膜晶体管、 像素电极和公共电极， 所述薄膜 晶体管包括栅极、 设置于所述栅极之上的栅绝缘层、 设置于所述栅绝缘层之 上有源层、 设置于所述有源层之上的源极和漏极、 以及设置于所述源极和漏 极之上的钝化层，
其中， 所述公共电极直接设置在所述钝化层之上； 所述像素电极设置在 所述钝化层之下， 并与所述薄膜晶体管的漏极相连接。
2、根据权利要求 1所述的像素单元， 其中， 所述像素电极与所述栅极设 置在同一层， 所述钝化层和所述像素电极之间设置有栅绝缘层， 与所述公共 电极同层的连接电极通过两个过孔分别连接所述薄膜晶体管的漏极和所述像 素电极。
3、根据权利要求 1或 2所述的像素单元，其中，所述公共电极为狭缝状， 所述像素电极为板状。
4、 根据权利要求 1~3任一项所述的像素单元， 其中， 所述像素电极和 / 或所述公共电极为透明电极。
5、 根据权利要求 1~4任一项所述的像素单元， 其中， 所述钝化层为氧 化物、 氮化物、 氮氧化物或有机树脂。
6、 一种阵列基板， 包括：
基底基板， 和
所述基底基板上设置的多条栅线和多条数据线，
其中， 所述多条数据线垂直于所述多条栅线， 所述栅线和所述数据线彼 此交叉限定了多个像素区域，
其中，所述多个像素区域每个包括权利要求 1~5任一项所述的像素单元， 所述像素单元每个的薄膜晶体管的栅极与相应的栅线连接， 所述薄膜晶体管 的源极与相应的数据线连接。
7、根据权利要求 6所述的阵列基板， 其中，每行所述像素单元的上方和 下方均设置有一条栅线， 且每相邻两行所述像素单元之间设置有两条栅线； 每列所述像素单元的左侧或右侧设置有一条数据线， 且每相邻两条数据线之 间包括两列所述像素单元。
8、根据权利要求 7所述的阵列基板， 其中，每个所述像素单元的所述薄 膜晶体管的栅极与其所在的像素单元上方或下方的一条栅线连接， 所述薄膜 晶体管的源极与其所在的像素单元左侧或右侧的一条数据线连接， 实现 Z反 转的像素结构。
9、 根据权利要求 8所述的阵列基板， 其中， 所述 Z反转的像素结构包 括：
同列的奇数个像素单元中的薄膜晶体管的源极连接在该列两侧的数据线 中的一条数据线上， 偶数个像素单元中的薄膜晶体管的源极连接在该列两侧 的数据线中另一条数据线上， 且相邻两列中处于同一行的像素单元中的薄膜 晶体管的源极连接不同的两条数据线；
同行的所述像素单元两两一组通过其包括的薄膜晶体管的栅极交替地分 别连接在位于该行像素单元上方和下方的两条栅线上， 且每条所述栅线连接 的像素单元位于同一行；
两条相邻数据线之间的、 两个同行且相邻的像素单元的薄膜晶体管的栅 极分别连接在两条栅线上， 源极分别连接在所述两条数据线上。
10、 根据权利要求 6~9任一项所述的阵列基板， 其中， 每个所述像素单 元的所述公共电极延伸至其所在像素单元的上方和 /或下方的一条栅线的上 方， 与所述一条栅线形成存储电容。
11、 一种液晶面板， 包括彩膜基板和根据权利要求 6~10任一项所述的 阵列基板， 所述彩膜基板上包括黑矩阵，
其中， 在所述彩膜基板上， 对应所述多条栅线的位置、 对应所述多条数 据线的位置以及对应相邻两条数据线之间的两列像素单元交界的位置， 均设 置有黑矩阵。
12、 一种阵列基板的制造方法， 其中， 包括：
S101、 通过第一次构图工艺形成包括像素电极的图形， 通过第二次构图 工艺形成包括多条栅线和多个像素单元的薄膜晶体管栅极的图形；
或者 , 通过第一次构图工艺形成包括多条栅线和多个像素单元的薄膜晶 体管栅极的图形， 通过第二次构图工艺形成包括像素电极的图形；
S102、 通过第三次构图工艺形成包括栅绝缘层、 有源层、 多条数据线以 及所述薄膜晶体管的源极和漏极的图形； 5103、 通过第四次构图工艺形成包括钝化层的图形；
5104、 通过第五次构图工艺形成包括公共电极的图形。
13、根据权利要求 12所述的阵列基板的制造方法，其中，所述步骤 S101 中形成的多条栅线， 包括：在每行像素单元的上方和下方均形成有一条栅线， 且每相邻两行像素单元之间设置有两条栅线；
其中， 所述步骤 S102 中形成的多条数据线， 包括： 在每列所述像素单 元的左侧或右侧设置有一条数据线， 且每相邻两条数据线之间包括两列像素 单元。
14、 根据权利要求 13所述的阵列基板的制造方法， 其中， 在步骤 S101 中实现每个所述像素单元的薄膜晶体管的栅极与其所在的像素单元上方或下 方的一条栅线连接， 在步骤 S102 中实现每个所述像素单元的薄膜晶体管的 源极与其所在的像素单元左侧或右侧的一条数据线连接， 以实现 Z反转的像 素结构。
15、 根据权利要求 12-14任一所述的阵列基板的制造方法， 其中， 在步 骤 S104中， 形成的公共电极延伸至其所在像素单元的上方和 /或下方的一条 栅线的上方， 与所述一条栅线形成存储电容。
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