WO2017054394A1 - 阵列基板及其制作方法、显示装置 - Google Patents
阵列基板及其制作方法、显示装置 Download PDFInfo
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- WO2017054394A1 WO2017054394A1 PCT/CN2016/073874 CN2016073874W WO2017054394A1 WO 2017054394 A1 WO2017054394 A1 WO 2017054394A1 CN 2016073874 W CN2016073874 W CN 2016073874W WO 2017054394 A1 WO2017054394 A1 WO 2017054394A1
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Definitions
- the present disclosure generally relates to the field of display technology. More specifically, the present disclosure relates to an array substrate, a method of fabricating the same, and a display device.
- TFT-LCD thin film field effect transistor liquid crystal display
- TFT-LCDs can be classified into TN (Twisted Nematic) type, In Plane Switching (IPS) type, and Advanced Super Dimension Switch (ADS) according to the display mode.
- the ADS type TFT-LCD generally forms a multi-dimensional electric field by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer, so that between the slit electrodes in the liquid crystal cell All of the aligned liquid crystal molecules directly above the electrode are capable of rotating, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
- ADS technology can improve the picture quality of TFT-LCD products, making the display device have high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. .
- FIG. 1 illustrates a schematic cross-sectional view of a prior art ADS type array substrate.
- the array substrate sequentially includes pixel electrodes 3 arranged in the same layer, gate electrodes of common thin film transistors and common electrode line patterns (not shown), gate insulating layer 7, passivation layer 8, and film.
- the manufacturing method of the existing ADS type array substrate generally comprises: forming a pixel electrode arranged in the same layer, a gate of the thin film transistor and a common electrode line pattern on the transparent substrate; forming a gate insulating layer; forming an active layer pattern; Forming a source, a drain, and a data line pattern of the thin film transistor; forming a passivation layer; and forming a common electrode over the passivation layer.
- the interval between the common electrode line 4 and the pixel electrode 3 reduces the working efficiency of the liquid crystal of the corresponding portion, thereby reducing the transmittance of the pixel.
- an array substrate including a plurality of gate lines, a plurality of data lines crossing a plurality of gate lines, and a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines
- Each of the pixel units includes a thin film transistor, a gate insulating layer, a passivation layer disposed on one side of the gate insulating layer, a pixel electrode, and a common electrode, wherein a source and a drain of the thin film transistor are provided with a passivation layer and a gate Between the insulating layers, the common electrode is disposed on the other side of the gate insulating layer opposite to the passivation layer, and the pixel electrode is disposed on the passivation layer.
- the array substrate provided by the present disclosure, by exchanging the positions of the pixel electrode and the common electrode, the pixel electrode and the common electrode line are no longer arranged in the same layer, thus eliminating A space is provided between the pixel electrode and the common electrode line to ensure that there is no need for crosstalk between the two.
- the elimination of the interval improves the working efficiency of the liquid crystal, thereby improving the transmittance of the pixel.
- the above array substrate may further include a shield electrode disposed in the same layer as the pixel electrode and located above the data line.
- a shield electrode may be formed over the data line for shielding the electric field generated by the data line, thereby preventing the electric field from affecting the effective deflection of the liquid crystal molecules.
- the inventors have found that the width of the black matrix can be reduced to 6-8 ⁇ m in the presence of a shield electrode compared to a black matrix of at least 18-28 ⁇ m wide without a shield electrode, thereby greatly improving display The aperture ratio of the device.
- the common electrode may have a matrix structure, the common electrode includes a plurality of sub-common electrodes, and each of the pixel units corresponds to one sub-common electrode.
- the matrix structure of the common electrode is connected by a common electrode line in a direction perpendicular to the data line, and the common electrode is in direct contact electrical connection with the common electrode line.
- the matrix structure of the common electrode is connected by a connection electrode in a direction parallel to the data line, the connection The electrode and the common electrode are disposed in different layers, and the connection electrodes are respectively connected to the adjacent sub-common electrodes through the via holes.
- the via holes are formed in the gate insulating layer and the passivation layer.
- the shield electrodes are connected to each other by a shield electrode connection line in a direction perpendicular to the data lines, wherein the shield electrode and the shield electrode connection line are formed of the same material.
- the shield electrode and the common electrode may be connected to the same common electrode line.
- the shield electrode and the common electrode may be connected to different common electrode lines, and the signals on different common electrode lines may be the same or different.
- the signals on different common electrode lines are different, the signals in the shield electrode and the common electrode can be slightly different by adding a small signal input.
- the shield electrode and the common electrode may be electrically insulated from each other and connected to different common electrode lines, at which time the common electrode is not affected by the parasitic capacitance between the shield electrode and the data line.
- the array substrate may further include a pixel metal electrode corresponding to the pixel electrode in order to prevent the signal in the pixel electrode from being defective due to the large resistance of the ITO.
- An insulating layer may be present between the pixel electrode and the pixel metal electrode, and the two are connected to each other through via holes in the insulating layer.
- the pixel electrode is a slit electrode and the common electrode is a plate electrode.
- the electric field generated at the edge of the slit electrode and the electric field generated between the slit electrode layer and the plate electrode layer can form a multi-dimensional electric field, so that all between the slit electrodes in the liquid crystal cell and directly above the electrodes
- the aligned liquid crystal molecules are capable of generating rotation, thereby improving liquid crystal working efficiency and increasing light transmission efficiency.
- a display device comprising the array substrate as described above.
- the pixel electrode and the common electrode line are no longer arranged in the same layer, thus eliminating the need to provide a space between the pixel electrode and the common electrode line to ensure that there is no crosstalk between the two.
- the elimination of the interval improves the working efficiency of the liquid crystal, thereby improving the transmittance of the pixel.
- a method of fabricating an array substrate as described above comprising the steps of: forming a pattern including a gate electrode of a thin film transistor, a common electrode, and a common electrode line on a base substrate; forming a gate insulating layer; an active layer forming a thin film transistor; forming a pattern including a source, a drain, and a data line of the thin film transistor; forming a blunt a layer in which a source and a drain of the thin film transistor are disposed between the passivation layer and the gate insulating layer; and a pixel electrode is formed on the passivation layer.
- the above method may further include forming a shield electrode on the passivation layer, wherein the shield electrode is disposed in the same layer as the pixel electrode and located above the data line.
- the shield electrode can shield the electric field generated by the data line, thereby preventing the electric field from affecting the effective deflection of the liquid crystal molecules.
- the above method may further include forming a pixel metal electrode over the pixel electrode, an insulating layer between the pixel electrode and the pixel metal electrode, and connecting the pixel electrode and the pixel metal electrode through a via hole in the insulating layer . Since the pixel electrode is usually fabricated using ITO having a large resistivity, the addition of the pixel metal electrode can prevent the signal in the pixel electrode from being defective due to the large resistance of the ITO.
- Figure 1 schematically illustrates a cross-sectional view of a prior art array substrate
- Figure 2 schematically illustrates a top view of an array substrate in the prior art
- FIG. 3 schematically illustrates a cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure
- FIG. 4 schematically illustrates a top view of an array substrate in accordance with an embodiment of the present disclosure
- FIG. 5 schematically illustrates a cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure
- FIG. 6 schematically illustrates a matrix structure design of a common electrode in accordance with an embodiment of the present disclosure
- FIG. 7 schematically illustrates a structural design of a shield electrode in accordance with an embodiment of the present disclosure
- FIG. 8 illustrates simulation results of crosstalk analysis between a pixel electrode and a shield electrode
- FIG. 9 is a flow chart of a method for fabricating an array substrate in accordance with an embodiment of the present disclosure.
- An array substrate includes a plurality of gate lines, a plurality of data lines crossing the plurality of gate lines, and a plurality of pixel units defined by a plurality of gate lines and a plurality of data lines, each of the pixel units including Thin film transistor, gate insulating layer 7, arranged in a passivation layer 8 on one side of the gate insulating layer 7, a pixel electrode 3, and a common electrode 2, wherein a source and a drain 5 of the thin film transistor are disposed between the passivation layer 8 and the gate insulating layer 7, and the common electrode 2 is disposed On the other side of the gate insulating layer 7 opposite to the passivation layer 8, the pixel electrode 3 is disposed on the passivation layer 8.
- the pixel electrode 3 is disposed at The common electrode 2 is disposed above the passivation layer 8 under the gate insulating layer 7 (this is the same as disposing the pixel electrode 3 under the gate insulating layer 7 in FIG. 1 and arranging the common electrode 2 over the passivation layer 8)
- the arrangement is reversed), the pixel electrode 3 and the common electrode line 4 are no longer arranged in the same layer, thus eliminating the need to provide an interval between the pixel electrode 3 and the common electrode line 4 to ensure that there is no crosstalk between the two.
- FIG. 5 illustrates a cross-sectional view of an array substrate in accordance with another embodiment of the present disclosure. 5 is different from FIG. 3 in that the array substrate further includes a shield electrode 9 disposed in the same layer as the pixel electrode 3 and located above the data line 5.
- the shield electrode 9 located above the data line 5 is capable of shielding the electric field generated by the data line 5, thereby preventing the electric field from affecting the effective deflection of the liquid crystal molecules.
- the width of the black matrix is at least 18-28 ⁇ m, and in the presence of the shield electrode 9, the width of the black matrix can be reduced to 6-8 ⁇ m, thus greatly increasing the aperture ratio of the display device. .
- the common electrode may have a matrix structure, the common electrode includes a plurality of sub-common electrodes, and each of the pixel units corresponds to one sub-common electrode.
- 6 and 7 respectively illustrate structural designs of a common electrode and a shield electrode in accordance with one embodiment.
- the matrix of the common electrode 2 is connected by a common electrode line 4 in a direction perpendicular to the data line, the common electrode 2 is in direct contact electrical connection with the common electrode line 4, and the connection electrode is passed in a direction parallel to the data line.
- 10 is connected, the connection electrode 10 and the common electrode 2 are disposed in different layers, and the connection electrodes 10 are respectively connected to the adjacent sub-common electrodes through the via holes 6.
- the connection electrode 10 is connected to an adjacent sub-common electrode through a via hole 6 formed in the gate insulating layer and the passivation layer.
- the shield electrodes 9 are connected to each other by a shield electrode connection line in a direction perpendicular to the data lines, and the shield electrodes 9 and the shield electrode connection lines are formed of the same material (for example, indium tin oxide (ITO)).
- ITO indium tin oxide
- the shield electrode and the common electrode may be connected to the same common electrode line.
- the shield electrode and the common electrode may be connected to different common electrode lines, and the signals on different common electrode lines may be the same or different.
- the signals on different common electrode lines are different, the signals in the shield electrode and the common electrode can be slightly different by adding a small signal input.
- the shield electrode and the common electrode may be electrically insulated from each other and connected to different common electrode lines, at which time the common electrode is not affected by the parasitic capacitance between the shield electrode and the data line.
- the array substrate may further include a pixel metal electrode corresponding to the pixel electrode in order to prevent the signal in the pixel electrode from being defective due to the large resistance of the ITO.
- An insulating layer may exist between the pixel electrode and the pixel metal electrode, and the pixel electrode and the pixel metal electrode are connected to each other through a via hole in the insulating layer.
- the pixel electrode 3 is a slit electrode
- the common electrode 2 is a plate electrode.
- Fig. 8 is a longitudinal sectional view of a pixmap. It can be seen from FIG. 8 that when the portion on the left side of the block is lit, the phenomenon of color mixing and light leakage does not occur in the block portion, so that the arrangement of the pixel electrode and the shield electrode in the same layer does not cause crosstalk between signals. It also does not cause light leakage and color mixing.
- the present disclosure also provides a display device including the array substrate as described above.
- the pixel electrode and the common electrode line are no longer arranged in the same layer, thus eliminating the need to provide a space between the pixel electrode and the common electrode line to ensure that there is no crosstalk between the two.
- the elimination of the interval improves the working efficiency of the liquid crystal, thereby improving the transmittance of the pixel.
- the display device provided by the present disclosure may be any mode liquid crystal display device such as TN, ADS, IPS, LTPS or the like.
- the display device can be a liquid crystal panel, a liquid crystal television, a display, Any product or component that has a display function, such as a mobile phone or a navigator.
- FIG. 9 illustrates a flow chart of a method of fabricating an array substrate as described above, in accordance with an embodiment of the present disclosure. Specifically, the method includes the following steps:
- a pattern including a gate electrode of the thin film transistor, a common electrode, and a common electrode line is formed on the base substrate; at S102, a gate insulating layer is formed; and at S104, an active layer of the thin film transistor is formed; at S106 Forming a pattern including a source, a drain, and a data line of the thin film transistor; and at S108, forming a passivation layer, wherein a source and a drain of the thin film transistor are disposed between the passivation layer and the gate insulating layer; At S110, a pixel electrode is formed on the passivation layer.
- step S100 may include first forming a metal layer on the base substrate, and patterning the metal layer to form a pattern including the gate electrode, the common electrode, and the common electrode line.
- the base substrate is a transparent substrate such as a glass substrate, a quartz substrate, an organic resin substrate, or the like.
- the metal layer may be deposited on the substrate by sputtering or thermal evaporation, wherein the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, etc.
- An alloy of metals, and the metal layer may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo or the like. Patterning methods include photolithography, wet etching, dry etching, and the like.
- the common electrode can also be fabricated by depositing an indium tin oxide (ITO) material.
- ITO indium tin oxide
- the material of the gate insulating layer may be selected from an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the material of the gate insulating layer may be SiNx, SiOx or Si(ON)x.
- Step S104 may specifically include forming a semiconductor layer, and patterning the semiconductor layer to form an active layer pattern of the thin film transistor.
- the material of the active layer may be a silicon semiconductor or a metal oxide semiconductor.
- Step S106 may specifically include forming a metal layer on the substrate of the step S104, and patterning the metal layer to form a pattern including a source, a drain, and a data line of the thin film transistor.
- the material of the passivation layer may be selected from an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure.
- the material of the passivation layer may be SiNx, SiOx or Si(ON)x.
- the pixel electrode may be fabricated by depositing an indium tin oxide (ITO) material.
- ITO indium tin oxide
- the above method may further include forming a shield electrode on the passivation layer, wherein the shield electrode is located above the data line.
- the shield electrode can shield the electric field generated by the data line, thereby preventing the electric field from affecting the effective deflection of the liquid crystal molecules.
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Abstract
一种阵列基板,包括多条栅线、与多条栅线交叉的多条数据线,每两条栅线与对应的数据线定义一个像素单元,每一个像素单元包括薄膜晶体管、栅极绝缘层(7)、布置在栅极绝缘层一侧上的钝化层(8)、像素电极(3)和公共电极(2),其中薄膜晶体管的源极和漏极(5)布置在钝化层与栅极绝缘层之间,公共电极布置在与钝化层相对的栅极绝缘层的另一侧上,像素电极布置在钝化层上。还提供了一种制作阵列基板的方法和一种显示装置。
Description
本公开一般涉及显示技术领域。更具体地,本公开涉及一种阵列基板及其制作方法、显示装置。
随着薄膜场效应晶体管液晶显示(TFT-LCD)技术的发展和工业技术的进步,液晶显示器的生产成本持续降低并且制造工艺日益完善,因而已经取代阴极射线管显示器而成为平板显示领域中的主流技术。TFT-LCD显示器因其本身所具有的体积小、功耗低、无辐射等优点而成为理想的显示装置。
目前,TFT-LCD按照显示模式可以分为:扭曲向列(TN,Twisted Nematic)类型、平面转换(IPS,In Plane Switching)类型和高级超维场开关(ADS,Advanced Super Dimension Switch)类型。其中,ADS类型TFT-LCD通常通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场来形成多维电场,使得在液晶盒内的狭缝电极之间和电极正上方的所有取向液晶分子都能够产生旋转,从而提高了液晶工作效率并且增大了透光效率。ADS技术可以提高TFT-LCD产品的画面品质,使得显示装置具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。
图1图示了现有技术ADS型阵列基板的横截面示意图。如图1所示,从下至上,阵列基板依次包括同层布置的像素电极3、薄膜晶体管的栅极和公共电极线图形(未示出)、栅极绝缘层7、钝化层8、薄膜晶体管的源极、漏极和数据线图形5,以及公共电极2。相应地,现有ADS型阵列基板的制作方法一般包括:在透明基板上形成同层布置的像素电极、薄膜晶体管的栅极和公共电极线图形;形成栅极绝缘层;形成有源层图形;形成薄膜晶体管的源极、漏极和数据线图形;形成钝化层;以及在钝化层上方形成公共电极。
图1中所示的阵列基板中所存在的问题在于,如图2所示,与薄膜晶体管的栅极1同层布置的公共电极线4和像素电极3二者连接不同的信号线,因此在二者之间需要存在一定间隔d以保证公共电极线4
和像素电极3中的信号之间没有串扰。公共电极线4和像素电极3之间的间隔降低了对应部分的液晶的工作效率,进而降低了像素的透过率。
发明内容
本公开的一个目的是提供一种使用在ADS类型TFT-LED中的阵列基板及其制作方法,其能够至少部分地缓解或消除现有技术中所存在的问题。
根据本公开的第一方面,提供了一种阵列基板,包括多条栅线、与多条栅线交叉的多条数据线以及由多条栅线和多条数据线交叉定义的多个像素单元,每一个像素单元包括薄膜晶体管、栅极绝缘层、布置在栅极绝缘层一侧上的钝化层、像素电极和公共电极,其中薄膜晶体管的源极和漏极布置钝化层与栅极绝缘层之间,公共电极布置在与钝化层相对的栅极绝缘层的另一侧上,像素电极布置在钝化层上。
相比于上述现有技术中的阵列基板,在本公开所提供的阵列基板中,通过将像素电极和公共电极的位置互换,像素电极与公共电极线不再同层布置,因此消除了在像素电极与公共电极线之间设置间隔以保证二者之间没有串扰的需要。所述间隔的消除提升了液晶的工作效率,进而提升了像素的透过率。
根据一个实施例,上述阵列基板还可以包括与像素电极同层布置并且位于数据线上方的屏蔽电极。
在向数据线施加电压的情况下,由数据线产生的电场会导致数据线上方及两侧的液晶分子无法有效偏转,从而造成漏光的问题。为了解决这一问题,可以在数据线上方形成屏蔽电极,用于屏蔽数据线所产生的电场,从而防止该电场影响液晶分子的有效偏转。发明人已经发现,相比于在没有屏蔽电极的情况下的至少18-28μm宽的黑矩阵,在存在屏蔽电极的情况下,黑矩阵的宽度可以减小到6-8μm,从而极大地提高显示装置的开口率。
根据另一实施例,公共电极可以具有矩阵结构,所述公共电极包括多个子公共电极,并且每一个像素单元对应于一个子公共电极。可选地,公共电极的矩阵结构在垂直于数据线的方向上通过公共电极线连接,公共电极与公共电极线直接接触电连接。并且可选地,公共电极的矩阵结构在平行于数据线的方向上通过连接电极连接,所述连接
电极与公共电极设置于不同层,并且所述连接电极分别与相邻的子公共电极通过过孔连接。具体地,所述过孔制作在栅极绝缘层和钝化层中。
根据一个实施例,屏蔽电极在垂直于数据线的方向上通过屏蔽电极连接线相互连接,其中屏蔽电极与屏蔽电极连接线由相同材料形成。
根据又一实施例,屏蔽电极和公共电极可以连接相同的公共电极线。可替换地,屏蔽电极和公共电极可以连接不同的公共电极线,并且不同公共电极线上的信号可以相同或者不同。在不同公共电极线上的信号不同时,可以通过添加小信号输入来使屏蔽电极和公共电极中的信号略有不同。
根据实施例,屏蔽电极和公共电极可以相互电绝缘,并且连接不同的公共电极线,此时公共电极不受屏蔽电极和数据线之间的寄生电容的影响。
根据再一实施例,由于通常采用具有较大电阻率的ITO来制作像素电极,因此为防止像素电极中信号由于ITO的大电阻而产生不良,阵列基板还可以包括与像素电极对应的像素金属电极,在像素电极和像素金属电极之间可以存在绝缘层,并且二者通过绝缘层中的过孔相互连接。
根据另外的实施例,像素电极为狭缝电极,而公共电极为板状电极。由此,在狭缝电极边缘所产生的电场以及在狭缝电极层与板状电极层之间产生的电场能够形成多维电场,使得在液晶盒内的狭缝电极之间和电极正上方的所有取向液晶分子都能够产生旋转,从而提高液晶工作效率并且增大透光效率。
根据本公开的第二方面,提供了一种包括如以上所描述的阵列基板的显示装置。通过将像素电极和公共电极的位置互换,像素电极与公共电极线不再同层布置,因此消除了在像素电极与公共电极线之间设置间隔以保证二者之间没有串扰的需要。所述间隔的消除提升了液晶的工作效率,进而提升了像素的透过率。
根据本公开的第三方面,提供了一种制作如以上所描述的阵列基板的方法,包括以下步骤:在衬底基板上形成包括薄膜晶体管的栅极、公共电极和公共电极线的图形;形成栅极绝缘层;形成薄膜晶体管的有源层;形成包括薄膜晶体管的源极、漏极和数据线的图形;形成钝
化层,其中薄膜晶体管的源极和漏极布置钝化层与栅极绝缘层之间;以及在钝化层上形成像素电极。
根据本公开的实施例,上述方法还可以包括在钝化层上形成屏蔽电极,其中屏蔽电极与像素电极同层布置,并且位于数据线上方。屏蔽电极可以屏蔽数据线所产生的电场,从而防止该电场影响液晶分子的有效偏转。
根据本公开的另一实施例,上述方法还可以包括在像素电极上方形成像素金属电极,像素电极与像素金属电极之间存在绝缘层,并且像素电极与像素金属电极通过绝缘层中的过孔相连。由于通常采用具有较大电阻率的ITO来制作像素电极,因此添加像素金属电极可以防止像素电极中信号由于ITO的大电阻而产生不良。
本公开的这些以及其它方面从以下描述的实施例显而易见,并将参照以下描述的实施例来阐述本公开的这些以及其它方面。在附图中,
图1示意性地图示了现有技术阵列基板的横截面视图;
图2示意性地图示了现有技术中的阵列基板的顶视图;
图3示意性地图示了根据本公开的实施例的阵列基板的横截面视图;
图4示意性地图示了根据本公开的实施例的阵列基板的顶视图;
图5示意性地图示了根据本公开的另一实施例的阵列基板的横截面视图;
图6示意性地图示了根据本公开的实施例的公共电极的矩阵结构设计;
图7示意性地图示了根据本公开的实施例的屏蔽电极的结构设计;
图8图示了像素电极与屏蔽电极之间的串扰分析的模拟结果;以及
图9为根据本公开的实施例的用于制作阵列基板的方法的流程图。
图3和图4分别图示了根据本公开的实施例的阵列基板的横截面视图和顶视图。根据本公开的实施例的阵列基板包括多条栅线、与多条栅线交叉的多条数据线以及由多条栅线和多条数据线交叉定义的多个像素单元,每一个像素单元包括薄膜晶体管、栅极绝缘层7、布置在
栅极绝缘层7一侧上的钝化层8、像素电极3和公共电极2,其中薄膜晶体管的源极和漏极5布置钝化层8与栅极绝缘层7之间,公共电极2布置在与钝化层8相对的栅极绝缘层7的另一侧上,像素电极3布置在钝化层8上。
相比于图1中所示的现有技术中的阵列基板,在上述阵列基板中,通过将像素电极3和公共电极2的位置互换,即如图3所示,将像素电极3布置在钝化层8上方而将公共电极2布置在栅极绝缘层7下方(这与图1中的将像素电极3布置在栅极绝缘层7下方而将公共电极2布置在钝化层8上方的布置相反),像素电极3与公共电极线4不再同层布置,因此消除了在像素电极3与公共电极线4之间设置间隔以保证二者之间没有串扰的需要。如图4所示,在公共电极2与公共电极线4之间可以不存在间隔,甚至二者可以相互重叠。所述间隔的消除从而提升了液晶的工作效率,进而提升了像素的透过率。
图5图示了根据本公开的另一实施例的阵列基板的横截面视图。图5与图3的不同之处在于,阵列基板还包括与像素电极3同层布置并且位于数据线5上方的屏蔽电极9。
位于数据线5上方的屏蔽电极9能够屏蔽数据线5所产生的电场,从而防止该电场影响液晶分子的有效偏转。在没有屏蔽电极9的情况下,黑矩阵的宽度至少为18-28μm,而在存在屏蔽电极9的情况下,黑矩阵的宽度可以减小到6-8μm,因此极大地提高显示装置的开口率。
根据实施例,公共电极可以具有矩阵结构,公共电极包括多个子公共电极,并且每一个像素单元对应于一个子公共电极。图6和图7分别图示了根据一个实施例的公共电极和屏蔽电极的结构设计。如图6所示,公共电极2的矩阵在垂直于数据线的方向上通过公共电极线4连接,公共电极2与公共电极线4直接接触电连接,在平行于数据线的方向上通过连接电极10连接,该连接电极10与公共电极2设置于不同层,并且连接电极10分别与相邻的子公共电极通过过孔6连接。具体地,连接电极10通过制作在栅极绝缘层和钝化层中的过孔6与相邻的子公共电极连接。
类似地,如图7所示,屏蔽电极9在垂直于数据线的方向上通过屏蔽电极连接线相互连接,屏蔽电极9与屏蔽电极连接线由相同材料(例如氧化铟锡(ITO))形成。
在本公开所提出的阵列基板中,屏蔽电极和公共电极可以连接相同的公共电极线。可替换地,屏蔽电极和公共电极可以连接不同的公共电极线,并且不同公共电极线上的信号可以相同或者不同。在不同公共电极线上的信号不同时,可以通过添加小信号输入来使屏蔽电极和公共电极中的信号略有不同。
根据实施例,屏蔽电极和公共电极可以相互电绝缘,并且连接不同的公共电极线,此时公共电极不受屏蔽电极和数据线之间的寄生电容的影响。
根据一个实施例,由于通常采用具有较大电阻率的ITO来制作像素电极,因此为防止像素电极中信号由于ITO的大电阻而产生不良,阵列基板还可以包括与像素电极对应的像素金属电极,在像素电极和像素金属电极之间可以存在绝缘层,并且像素电极与像素金属电极通过绝缘层中的过孔相互连接。
如图3和图5所示,像素电极3为狭缝电极,并且公共电极2为板状电极。由此,在狭缝电极边缘所产生的电场以及在狭缝电极层与板状电极层之间产生的电场能够形成多维电场,使得在液晶盒内的狭缝电极之间和电极正上方的所有取向液晶分子都能够产生旋转,从而提高液晶工作效率并且增大透光效率。
在本公开所提出的阵列基板中,像素电极与屏蔽电极同层布置,并且二者连接到不同的信号线。为证明在像素电极与屏蔽电极的信号之间不存在串扰,因而不会引起漏光和混色,对图5所示的阵列基板进行了模拟。模拟结果如图8所示。图8为像素图的纵截面视图。从图8可以看到,当点亮方框左侧的部分时,在方框部分中没有出现混色和漏光的现象,因此将像素电极和屏蔽电极同层布置不会引起信号之间的串扰,也不会引起漏光和混色。
本公开还提供了一种包括如以上所描述的阵列基板的显示装置。通过将像素电极和公共电极的位置互换,像素电极与公共电极线不再同层布置,因此消除了在像素电极与公共电极线之间设置间隔以保证二者之间没有串扰的需要。所述间隔的消除提升了液晶的工作效率,进而提升了像素的透过率。
本公开所提供的显示装置可以为TN、ADS、IPS、LTPS等任何模式的液晶显示装置。该显示装置可以为液晶面板、液晶电视、显示器、
手机、导航仪等任何具有显示功能的产品或其组件。
图9图示了根据本公开的实施例的制作如以上所描述的阵列基板的方法的流程图。具体地,所述方法包括以下步骤:
在S100处,在衬底基板上形成包括薄膜晶体管的栅极、公共电极和公共电极线的图形;在S102处,形成栅极绝缘层;在S104处,形成薄膜晶体管的有源层;在S106处,形成包括薄膜晶体管的源极、漏极和数据线的图形;在S108处,形成钝化层,其中薄膜晶体管的源极和漏极布置钝化层与栅极绝缘层之间;以及在S110处,在钝化层上形成像素电极。
具体地,步骤S100可以包括首先在衬底基板上形成金属层,对所述金属层进行图案化,从而形成包括栅极、公共电极和公共电极线的图形。衬底基板为透明基板,例如玻璃基板、石英基板和有机树脂基板等。可以采用溅射或热蒸发的方法在衬底基板上沉积金属层,其中栅极金属层可以是Cu,Al,Ag,Mo,Cr,Nd,Ni,Mn,Ti,Ta,W等金属以及这些金属的合金,并且金属层可以为单层结构或者诸如Cu\Mo,Ti\Cu\Ti,Mo\Al\Mo等之类的多层结构。图案化的方法包括光刻、湿法刻蚀和干法刻蚀等。公共电极也可以通过沉积铟锡氧化物(ITO)材料来制作。
在步骤S102中,栅极绝缘层的材料可以选自氧化物、氮化物或者氮氧化物,并且可以为单层、双层或多层结构。具体地,栅极绝缘层的材料可以是SiNx,SiOx或Si(ON)x。
步骤S104可以具体包括形成半导体层,对所述半导体层进行图案化,以形成薄膜晶体管的有源层图形。有源层的材料可以为硅半导体或金属氧化物半导体。
步骤S106可以具体包括,在完成步骤S104的衬底基板上形成金属层,对所述金属层进行图案化,从而形成包括薄膜晶体管的源极、漏极和数据线的图形。
在步骤S108中,钝化层的材料可以选自氧化物、氮化物或者氮氧化物,并且可以为单层、双层或多层结构。例如,钝化层的材料可以是SiNx,SiOx或Si(ON)x。
在步骤S110中,像素电极可以通过沉积铟锡氧化物(ITO)材料来制作。
根据本公开的实施例,上述方法还可以包括在钝化层上形成屏蔽电极,其中屏蔽电极位于数据线上方。屏蔽电极可以屏蔽数据线所产生的电场,从而防止该电场影响液晶分子的有效偏转。
虽然已经在附图和前述描述中详细图示和描述了本公开,但是这样的图示和描述要被视为说明性或示例性而非限制性的;本公开不限于所公开的实施例。本领域技术人员在实践所要求保护的公开时,通过研究附图、公开内容和随附权利要求,能够理解和实现对所公开的实施例的其它变型。例如,以上描述的方法不要求以所描述的特定次序或顺序的次序来实现合期望的结果。可以提供其它步骤,或者可以从所描述的方法中除去步骤,并且其它组件可以添加到所描述的装置或者从所描述的装置移除。其它实施例可以在本公开的范围内。
Claims (12)
- 一种阵列基板,包括多条栅线、与多条栅线交叉的多条数据线、以及由多条栅线和多条数据线交叉定义的多个像素单元,每一个像素单元包括薄膜晶体管、栅极绝缘层、布置在栅极绝缘层一侧上的钝化层、像素电极和公共电极,其中薄膜晶体管的源极和漏极布置钝化层与栅极绝缘层之间,公共电极布置在与钝化层相对的栅极绝缘层的另一侧上,像素电极布置在钝化层上,其中所述阵列基板还包括与像素电极同层布置并且位于数据线上方的屏蔽电极。
- 权利要求1的阵列基板,其中公共电极具有矩阵结构,所述公共电极包括多个子公共电极,并且每一个像素单元对应于一个子公共电极。
- 权利要求2的阵列基板,其中公共电极的矩阵结构在垂直于数据线的方向上通过公共电极线连接,公共电极与公共电极线直接接触电连接。
- 权利要求3的阵列基板,其中公共电极的矩阵结构在平行于数据线的方向上通过连接电极连接,所述连接电极与所述公共电极设置于不同层,并且所述连接电极分别与相邻的子公共电极通过过孔连接。
- 权利要求1的阵列基板,其中屏蔽电极在垂直于数据线的方向上,通过屏蔽电极连接线相互连接,其中屏蔽电极与屏蔽电极连接线由相同材料形成。
- 权利要求1的阵列基板,其中屏蔽电极和公共电极连接相同的公共电极线。
- 权利要求1的阵列基板,其中屏蔽电极与公共电极相互电绝缘,并且连接不同的公共电极线。
- 权利要求1的阵列基板,其中阵列基板还包括与像素电极对应的像素金属电极,在像素电极和像素金属电极之间存在绝缘层,并且像素电极与像素金属电极通过绝缘层中的过孔相互连接。
- 权利要求1的阵列基板,其中像素电极为狭缝电极,并且公共电极为板状电极。
- 一种显示装置,包括如权利要求1-9中任一项所述的阵列基板。
- 一种用于制作阵列基板的方法,包括以下步骤:在衬底基板上形成包括薄膜晶体管的栅极、公共电极和公共电极线的图形;形成栅极绝缘层;形成薄膜晶体管的有源层;形成包括薄膜晶体管的源极、漏极和数据线的图形;形成钝化层,其中薄膜晶体管的源极和漏极布置钝化层与栅极绝缘层之间;在钝化层上形成像素电极;以及在钝化层上形成屏蔽电极,其中屏蔽电极与像素电极同层布置并且位于数据线上方。
- 权利要求11的方法,还包括在像素电极上方形成像素金属电极,像素电极与像素金属电极之间存在绝缘层,并且像素电极与像素金属电极通过绝缘层中的过孔相连。
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CN206074968U (zh) * | 2016-10-14 | 2017-04-05 | 京东方科技集团股份有限公司 | 阵列基板及显示装置 |
CN106405967A (zh) * | 2016-11-11 | 2017-02-15 | 京东方科技集团股份有限公司 | 一种阵列基板、液晶显示面板及显示装置 |
CN108255355B (zh) * | 2016-12-29 | 2021-01-15 | 南京瀚宇彩欣科技有限责任公司 | 内嵌式触控显示面板 |
CN108445682A (zh) * | 2018-02-06 | 2018-08-24 | 昆山龙腾光电有限公司 | 一种阵列基板、阵列基板的制作方法及液晶显示装置 |
CN108459445B (zh) * | 2018-03-30 | 2021-05-18 | 上海天马微电子有限公司 | 一种液晶显示面板、显示装置及液晶显示面板的制备方法 |
CN109244083B (zh) * | 2018-09-05 | 2020-12-08 | 京东方科技集团股份有限公司 | 显示背板及其制造方法、显示面板及可穿戴设备 |
CN109449166A (zh) * | 2018-11-01 | 2019-03-08 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法和显示面板 |
CN113348407A (zh) * | 2019-04-03 | 2021-09-03 | 深圳市柔宇科技股份有限公司 | 显示面板及显示装置 |
CN113820893B (zh) * | 2020-06-18 | 2022-12-20 | 京东方科技集团股份有限公司 | 显示面板和显示装置 |
CN112599536A (zh) * | 2020-12-10 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | 显示面板及其制作方法、拼接显示面板 |
CN114035381B (zh) * | 2021-01-18 | 2022-08-26 | 重庆康佳光电技术研究院有限公司 | 彩膜基板、显示面板、显示装置及修复方法 |
CN114879422A (zh) * | 2022-05-25 | 2022-08-09 | 广州华星光电半导体显示技术有限公司 | 阵列基板以及显示装置 |
CN115113447A (zh) * | 2022-06-29 | 2022-09-27 | 长沙惠科光电有限公司 | 阵列基板和显示面板 |
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