WO2015180302A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2015180302A1
WO2015180302A1 PCT/CN2014/086809 CN2014086809W WO2015180302A1 WO 2015180302 A1 WO2015180302 A1 WO 2015180302A1 CN 2014086809 W CN2014086809 W CN 2014086809W WO 2015180302 A1 WO2015180302 A1 WO 2015180302A1
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Prior art keywords
array substrate
thin film
film transistor
insulating layer
pixel electrode
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PCT/CN2014/086809
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English (en)
French (fr)
Inventor
曹占锋
丁录科
张文林
孔祥春
张锋
姚琪
章志兴
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/436,004 priority Critical patent/US9835921B2/en
Publication of WO2015180302A1 publication Critical patent/WO2015180302A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/136222—Colour filters incorporated in the active matrix substrate
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Definitions

  • At least one embodiment of the present invention is directed to an array substrate, a method of fabricating the same, and a display device.
  • Liquid crystal displays are widely used in various fields such as computers, mobile phones, televisions, and measurement displays due to their low operating voltage, low power consumption, flexible display, and low radiation.
  • the LCD may include a liquid crystal display panel including an array substrate provided with a thin film transistor, a color filter substrate paired with the array substrate, and a liquid crystal layer interposed between the two substrates.
  • an electric field is generated between the pixel electrode on the array substrate and the common electrode on the color filter substrate to drive the liquid crystal molecules in the liquid crystal layer, so that the deflection angles of the liquid crystal molecules in the liquid crystal layer are inconsistent. This allows the LCD to display.
  • At least one embodiment of the present invention provides an array substrate, a method for fabricating the same, and a display device for preventing oxidation of a metal such as copper during a patterning process of a transparent conductive film to ensure conductivity of the source and the drain.
  • At least one embodiment of the present invention provides an array substrate including a plurality of pixel unit regions arranged in an array, the pixel unit regions including a thin film transistor and a pixel electrode, an active layer of the thin film transistor, and the A first insulating layer is formed between the pixel electrodes, the first insulating layer is formed with a first via hole and a second via hole, and the first via hole and the second via hole respectively correspond to the active layer
  • the source of the thin film transistor is connected to the active layer through the first via, and a drain of the thin film transistor is overlapped over the pixel electrode and connected through the second via The active layer.
  • At least one embodiment of the present invention provides a display device including the above array substrate.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: forming a pattern of an active layer, a first insulating layer, and a pixel electrode of a thin film transistor, the first insulating layer including a first via And the second via, the first via and the second via respectively corresponding to the active Forming a source including a source and a drain of the thin film transistor, the source of the thin film transistor being connected to the active layer through the first via, the drain of the thin film transistor being overlapped
  • the active layer is connected over the pixel electrode and through the second via.
  • FIG. 1 is a plan view 1 of an array substrate according to an embodiment of the present invention.
  • Figure 2 is a cross-sectional view taken along line A-A' of Figure 1;
  • FIG. 3 is a schematic structural view 1 of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a second schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view 3 of an array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view 4 of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a first flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic plan view 2 of an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a second flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic plan view 3 of an array substrate according to an embodiment of the present invention.
  • FIG. 11 is a plan view 4 of an array substrate according to an embodiment of the present invention.
  • Figure 12 is a cross-sectional view taken along line A-A' of Figure 11;
  • FIG. 13 is a schematic structural diagram 5 of an array substrate according to an embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram 6 of an array substrate according to an embodiment of the present invention.
  • 15 is a schematic plan view 5 of an array substrate according to an embodiment of the present invention.
  • Figure 16 is a cross-sectional view taken along line A-A' of Figure 15;
  • 17 is a plan view 6 of an array substrate according to an embodiment of the present invention.
  • Figure 18 is a cross-sectional view taken along line A-A' of Figure 17;
  • FIG. 19 is a schematic structural diagram 7 of an array substrate according to an embodiment of the present invention.
  • 11 black matrix
  • 12 color film
  • 13 transparent conductive film
  • a structure such as a source and a drain can be formed by using a metal such as copper, and then a transparent conductive film is formed, and the transparent conductive film is patterned to form a pixel. Electrode; in the process of patterning the transparent conductive film, a structure such as a source and a drain made of a metal such as copper is exposed, so that the metal surface is easily oxidized; and the thickness of the oxide layer on the metal surface can be over time. The continuation of the increase continues. When the thickness of the oxide layer is large, the conductivity of the source and the drain may be affected, which may cause the array substrate to fail to operate normally, the yield of the product is affected, and the user experience is lowered.
  • At least one embodiment of the present invention provides an array substrate, as shown in FIGS. 1 and 2, including a plurality of pixel unit regions arranged in an array, the pixel unit regions including a thin film transistor 2 and a pixel electrode 3.
  • a first insulating layer 4 is formed between the active layer 21 of the thin film transistor 2 and the pixel electrode 3, and the first insulating layer 4 has a first via hole 5 and a second via hole 6 formed therein.
  • the first via 5 and the second via 6 respectively correspond to both ends of the active layer 21; the source 24 of the thin film transistor 2 is connected to the active layer 21 through the first via 5
  • the drain electrode 25 of the thin film transistor 2 is overlapped over the pixel electrode 3 and connected to the active layer 21 through the second via hole 6.
  • first via 5 and the second via 6 respectively expose the source region and the drain region of the active layer, and the source 24 of the thin film transistor 2 electrically contacts the active layer 21 through the first via 5;
  • the drain 25 of the thin film transistor 2 is electrically connected to the active layer 21 through the second via 6.
  • the drain of the thin film transistor is overlapped at the pixel Connecting the active layer over the electrode and through the second via, the pixel electrode can be formed first, and then the source and the drain are formed, which prevents the formation of the pixel electrode after forming the source and the drain
  • the structure such as the source and the drain of the metal such as copper
  • the structure such as the source and the drain are oxidized, which ensures the conductivity of the source and the drain, thereby ensuring the normality of the array substrate. Work, product yield and user experience.
  • the array substrate further includes a data line 7 extending in a vertical direction and a gate line 8 extending in a horizontal direction, and the two intersect each other to define a pixel. unit.
  • the data line 7 and the source 24 and the drain 25 of the thin film transistor 2 may be located in the same layer, that is, the data line 7, the source 24, and the drain 25 may be Formed in the same patterning process.
  • the data line 7, the source electrode 24, and the drain electrode 25 are all formed after the formation of the pixel electrode 3, and the structure of the data line 7, the source electrode 24, and the drain electrode 25 can be prevented from being oxidized in the process of forming the pixel electrode 3.
  • the gate lines 8 can be formed on the substrate substrate 1 of the array substrate ( The structure of the gate electrode 22 and the gate insulating layer 23 of the thin film transistor 2 integrally formed with the gate line 8 is not shown in FIG.
  • the array substrate shown in FIG. 1 and FIG. 2 may be an array substrate of a twisted nematic (TN) mode.
  • the structure of the array substrate shown in FIG. 2 can be improved.
  • the array substrate may further include the pixel electrode on the basis of the array substrate shown in FIG. a second insulating layer 9 over 3 and a common electrode 10, the second insulating layer 9 being located between the common electrode 10 and the pixel electrode 3, which ensures insulation of the common electrode 10 and the pixel electrode 3 to ensure the common electrode 10 and the pixel A certain voltage difference is generated between the electrodes 3 to form an electric field to drive the deflection of the liquid crystal molecules.
  • the array substrate is an array substrate of an Advanced Super Dimension Switch (ADS) mode.
  • ADS Advanced Super Dimension Switch
  • ADS Advanced Super Dimension Switch
  • ADS technology whose core technical characteristics are described as: the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer.
  • a multi-dimensional electric field is formed, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no extrusion Advantages such as push mura.
  • ADS technology has improved high-transmission I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology.
  • the common electrode 10 in FIG. 3 may be a slit electrode, and the pixel electrode 3 may be a plate electrode.
  • the common electrode 10 and the second insulating layer 9 may also be disposed under the pixel electrode 3.
  • the array substrate may further include a second insulating layer 9 and a common electrode 10 under the thin film transistor 2, that is, the substrate substrate 1 of the array substrate may be sequentially disposed from bottom to top.
  • the common electrode 10, the second insulating layer 9, the gate line 8 (not shown in FIG. 4) and the gate electrode 22, the gate insulating layer 23, the thin film transistor 2, and the data line 7 are disposed in the same layer.
  • the common electrode 10 in FIG. 4 may be a flat plate, and the pixel electrode 3 may be a slit electrode.
  • the reduction in the width of the black matrix may cause deviations in the cell-assembly between the array substrate and the color filter substrate, thereby causing undesirable phenomena such as light leakage, and thus the width of the black matrix on the color filter substrate cannot be Any decrease.
  • both the black matrix and the color film may be formed on the array substrate. Since the black matrix is located on the array substrate, when the width of the black matrix is appropriately reduced, the black matrix can also sufficiently block the structure of the light shielding structure such as the gate line, the data line, and the thin film transistor, and reduce the possibility of light leakage. Improve the resolution and transmittance while ensuring the display effect of the display device. This technology is also called COA (Color Filter on Array) technology.
  • a black matrix 11 and a color film 12 may be formed over the substrate 1 under the structure formed in FIG. 2 to form a COA array substrate.
  • the underlying substrate structure of the array substrate shown in FIG. A black matrix 11 and a color film 12 are formed on top of 1 to form an ADS array substrate of COA, which will not be described herein.
  • a black matrix and a color film may also be formed on the upper layer of the array substrate.
  • the black matrix is formed, for example, corresponding to a gate line, a data line, and a thin film transistor, and a color film unit is formed corresponding to each pixel unit, for example, including a red, green, and blue color film unit.
  • the structures of the first insulating layer 4, the gate insulating layer 23, and the second insulating layer 9 may be made of an insulating material such as silicon oxide, silicon nitride, hafnium oxide or resin.
  • At least one embodiment of the present invention also provides a display device comprising any of the above array substrates.
  • the display device may be a product or component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • a liquid crystal display device includes an array substrate and a counter substrate, which are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the array substrate is a COA substrate, a black matrix and a color film may no longer be disposed on the opposite substrate.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, as shown in FIG. 7, which comprises the steps described below.
  • Step S101 forming a pattern of an active layer of the thin film transistor, a first insulating layer, and a pixel electrode.
  • the first insulating layer includes a first via hole and a second via hole, and the first via hole and the second via hole respectively correspond to both ends of the active layer.
  • Step S102 forming a pattern including a source and a drain of the thin film transistor.
  • a source of the thin film transistor is connected to the active layer through the first via, a drain of the thin film transistor is overlying the pixel electrode and the active is connected through the second via Floor.
  • a method of first forming a pixel electrode and then forming a pattern of a source and a drain can effectively prevent copper from being formed in the process of forming the pixel electrode after forming the source and the drain.
  • the structure such as the source and the drain which are made of metal is exposed, and the structure such as the source and the drain are oxidized, which ensures the conductivity of the source and the drain, thereby ensuring the normal operation of the array substrate and the product.
  • step S101 as shown in FIG. 8, a structure such as a gate line 8 and a gate electrode 22 formed in the same layer, and a gate insulating layer 23 may be formed first on the array substrate. Since the gate insulating layer 23 is a transparent insulating layer structure, it is not shown in FIG.
  • step S101 may include the steps described below.
  • Step S1011 forming a pattern of the active layer.
  • a semiconductor thin film is deposited by a method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), and a pattern of the active layer 21 is formed by a patterning process.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • Step S1012 forming a first insulating layer and a transparent conductive film.
  • the first insulating layer 4 is first formed by coating or the like, and then transparent conductive is formed on the first insulating layer 4 by magnetron sputtering or thermal evaporation. Film 13. Since the first insulating layer 4 is a transparent insulating layer structure, it is not shown in FIG.
  • FIG. 12 is a cross-sectional view of the array substrate shown in FIG. 11, and it can be seen from FIG. 12 that the first insulating layer 4 is located under the transparent conductive film 13.
  • Step S1013 performing a patterning process on the first insulating layer and the transparent conductive film to form a first via hole and a second via hole of the first insulating layer, and forming the pixel electrode.
  • a photoresist layer 14 is formed on the transparent conductive film 13 by coating or the like, and exposed by a mask to form the photoresist layer 14 into a completely exposed region. 141.
  • the unexposed area 142 and the partially exposed area 143 are as shown in FIG.
  • the transparent conductive film 13 and the first insulating layer 4 corresponding to the fully exposed region 141 are etched away by an etching process to form the pixel electrode 3, the first transparent conductive portion 15, and the second transparent conductive portion 16.
  • the gap between the pixel electrode 3, the first transparent conductive portion 15 and the second transparent conductive portion 16 is formed by etching, and the width of each slit 17 is, for example, greater than 3 micrometers, which ensures the pixel electrode 3 and the first transparent conductive
  • the portion 15 and the second transparent conductive portion 16 are insulated from each other.
  • the first transparent conductive portion 15 and the second transparent conductive portion 16 respectively cover the source corresponding region and the drain corresponding region of the active layer 21, as shown in FIGS. 15 and 16.
  • the photoresist layer 14 is a transparent structure, it is not shown in FIG. 15, and the following is similar and will not be described again.
  • first insulating layer 4 is further disposed under the pixel electrode 3, the first transparent conductive portion 15, and the second transparent conductive portion 16, as shown in FIG.
  • the photoresist layer of the partially exposed region 143 is removed by an ashing process, and the first insulating layer 4 and the transparent conductive film 13 corresponding to the first via 5 are exposed, and the first insulating layer 4 corresponding to the second via 6 is exposed. And the transparent conductive film 13, the first insulating layer 4 and the transparent conductive film 13 corresponding to the first via 5 and the second via 6 are sequentially etched by a corresponding etching means, as shown in FIGS. 17 and 18.
  • the photoresist layer 14 of the unexposed region 141 is removed, and the pattern of the first insulating layer 4 and the structure of the pixel electrode 3 and the like are respectively formed in the same patterning process, as shown in FIG.
  • step S102 can be performed to form the source electrode 24 and the drain electrode 25 to complete the fabrication process of the thin film transistor 2. It should be noted that, if the pattern of the pixel electrode 3 and the first insulating layer 4 is formed by the above-described manufacturing method of steps S1011 to S1013, the first transparent conductive portion 15 and the second transparent conductive portion 16 are formed in step S1013. The slit 17 exposes the corresponding region of the active layer 21 as shown in FIG.
  • the source layer 21 causes corrosion, and since the etching solution of the metallic copper has almost no influence on the active layer 21, in one embodiment, the source 24 and the drain 25 are formed using metallic copper.
  • the source 24 is provided with the first transparent conductive portion 15 under the bottom, the source 24 and the first transparent conductive portion 15 are connected in parallel, which is equivalent to reducing the relationship between the active layer 21 and the data line 7.
  • the resistance value is more conducive to the transmission of electrical signals.
  • the drain 25 is provided with a second transparent conductive portion 16 under the drain to reduce the resistance between the active layer 21 and the pixel electrode 3.
  • the data line 7 may be formed in the same patterning process as the source 24 and the drain 25, that is, the pattern including the source 24 and the drain 25 of the thin film transistor 2 includes : A pattern of the source 24 and the drain 25 of the thin film transistor 2 and a data line 7 are formed.
  • the array substrate of the embodiment of the present invention may also be an ADS type array substrate. Therefore, in one embodiment, the method for fabricating the array substrate may further include: forming a second insulating layer and a common electrode, wherein the second insulating layer is located at the Between the pixel electrode and the common electrode.
  • the second insulating layer 9 and the common electrode 10 may be formed on the basis of the array substrate shown in FIG. 2, for example, forming the structure of the array substrate as shown in FIG. 3; or may be disposed on the gate line 8 and the gate electrode.
  • the common electrode 10 and the second insulating layer 9 are formed before the 22-layer structure and the gate insulating layer 23, for example, to form the structure of the array substrate of FIG.
  • the array substrate of the embodiment of the present invention may also be a COA type array substrate. Therefore, in one embodiment, the method for fabricating the array substrate may further include: forming a black matrix and a color film.
  • a black matrix 11 and a color film 12 are formed over the base substrate 1 to form a COA array substrate.
  • a black matrix 11 and a color film 12 may be formed on the substrate substrate 1 under the layer structure of the array substrate shown in FIG. 4 to form an ADS array substrate of COA. No longer.

Abstract

一种阵列基板及其制备方法、显示装置，该种阵列基板包括多个包括薄膜晶体管（2）和像素电极（3）的像素单元区域，所述薄膜晶体管的有源层（21）和所述像素电极（3）之间形成有具有第一过孔（5）和第二过孔（6）的第一绝缘层（4），所述薄膜晶体管（2）的源极（24）通过所述第一过孔（5）连接所述有源层（21），所述薄膜晶体管（2）的漏极（25）搭接在所述像素电极（3）之上并通过所述第二过孔（6）连接所述有源层（21）。该阵列基板能够防止铜等金属在对透明导电薄膜进行构图工艺的过程中发生氧化。

Description

阵列基板及其制备方法、显示装置 技术领域
本发明的至少一个实施例涉及一种阵列基板及其制备方法、显示装置。
背景技术
由于使用工作电压低、功耗小、显示方式灵活、辐射低等优点，液晶显示器(Liquid Crystal Display，LCD)广泛应用于各种领域，如计算机、手机、电视及测量显示等领域。LCD可以包括液晶显示面板，液晶显示面板包括设置有薄膜晶体管的阵列基板、与阵列基板对盒的彩膜基板以及夹设在两基板之间的液晶层。在该LCD的工作过程中，由阵列基板上的像素电极和彩膜基板上的公共电极之间产生电场来驱动液晶层中的液晶分子，使液晶层中各处的液晶分子的偏转角度不一致，这使得LCD可以进行显示。
发明内容
本发明的至少一个实施例提供一种阵列基板及其制备方法、显示装置，以防止铜等金属在对透明导电薄膜进行构图工艺的过程中发生氧化，保证源极和漏极的导电能力。
本发明的至少一个实施例提供了一种阵列基板，其包括多个呈阵列排布的像素单元区域，所述像素单元区域包括薄膜晶体管和像素电极，所述薄膜晶体管的有源层和所述像素电极之间形成有第一绝缘层，所述第一绝缘层形成有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
本发明的至少一个实施例提供了一种显示装置，其包括上述的阵列基板。
本发明的至少一个实施例提供了一种阵列基板的制备方法，该方法包括：形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形，所述第一绝缘层包括第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源 层的两端；形成包括薄膜晶体管的源极和漏极的图形，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例中的阵列基板的平面示意图一；
图2为图1的A-A＇截面示意图；
图3为本发明实施例中的阵列基板的结构示意图一；
图4为本发明实施例中的阵列基板的结构示意图二；
图5为本发明实施例中的阵列基板的结构示意图三；
图6为本发明实施例中的阵列基板的结构示意图四；
图7为本发明实施例中的阵列基板的制备方法的流程图一；
图8为本发明实施例中的阵列基板的平面示意图二；
图9为本发明实施例中的阵列基板的制备方法的流程图二；
图10为本发明实施例中的阵列基板的平面示意图三；
图11为本发明实施例中的阵列基板的平面示意图四；
图12为图11的A-A＇截面示意图；
图13为本发明实施例中的阵列基板的结构示意图五；
图14为本发明实施例中的阵列基板的结构示意图六；
图15为本发明实施例中的阵列基板的平面示意图五；
图16为图15的A-A＇截面示意图；
图17为本发明实施例中的阵列基板的平面示意图六；
图18为图17的A-A＇截面示意图；
图19为本发明实施例中的阵列基板的结构示意图七。
附图标记说明：
1—衬底基板；     2—薄膜晶体管；    21—有源层；
22—栅极；        23—栅极绝缘层；   24—源极；
25—漏极；        3—像素电极；      4—第一绝缘层；
5—第一过孔；       6—第二过孔；          7—数据线；
8—栅线；           9—第二绝缘层；        10—公共电极；
11—黑矩阵；        12—彩膜；             13—透明导电薄膜；
14—光刻胶层；      141—完全曝光区域；    142—未曝光区域；
143—部分曝光区域； 15—第一透明导电部分； 16—第二透明导电部分；
17—缝隙。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于所描述的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
发明人发现，在形成阵列基板的各层结构的过程中，首先可以利用铜等金属形成源极和漏极等结构，之后形成一透明导电薄膜，并对该透明导电薄膜进行构图工艺以形成像素电极；在对透明导电薄膜进行构图工艺的过程中，铜等金属制成的源极和漏极等结构暴露在外，使得金属表面容易发生氧化；并且，金属表面的氧化层的厚度可随着时间的推移继续增加，当氧化层的厚度较大时，可能影响源极和漏极的导电能力，进而导致阵列基板可能无法正常工作，产品的良率受到影响，并且用户的使用体验降低。
本发明的至少一个实施例提供一种阵列基板，如图1和图2所示，其包括多个呈阵列排布的像素单元区域，所述像素单元区域包括薄膜晶体管2和像素电极3。所述薄膜晶体管2的有源层21和所述像素电极3之间形成有第一绝缘层4，所述第一绝缘层4在其中形成有第一过孔5和第二过孔6，所述第一过孔5和所述第二过孔6分别对应所述有源层21的两端；所述薄膜晶体管2的源极24通过所述第一过孔5连接所述有源层21；所述薄膜晶体管2的漏极25搭接在所述像素电极3之上并通过所述第二过孔6连接所述有源层21。
这里，第一过孔5和第二过孔6分别暴露有源层的源极区和漏极区，所述薄膜晶体管2的源极24通过第一过孔5电接触有源层21；所述薄膜晶体管2的漏极25通过第二过孔6电接触连接有源层21。
显然，在本发明实施例中，由于所述薄膜晶体管的漏极搭接在所述像素 电极之上并通过所述第二过孔连接所述有源层，可以首先制成像素电极，之后再形成源极和漏极，这防止了在形成源极、漏极之后形成像素电极的过程中，铜等金属制成的源极和漏极等结构暴露在外造成的源极和漏极等结构被氧化等不良现象，保证了源极和漏极的导电能力，进而保证了阵列基板的正常工作、产品的良率和用户的使用体验。
显然，如图1和图2所示，所述阵列基板还包括数据线7和栅线8，数据线7在竖直方向延伸，栅线8在水平方向延伸，二者彼此交叉从而界定了像素单元。在一个实施例中，所述数据线7与所述薄膜晶体管2的源极24和漏极25可位于同一图层，即所述数据线7、所述源极24和所述漏极25可在同一次构图工艺中形成。此时，数据线7、源极24和漏极25均在形成像素电极3之后才形成，可防止数据线7、源极24和漏极25等结构在形成像素电极3的过程中被氧化。
需要说明的是，在形成有源层21、第一绝缘层4和像素电极3的图形之前，结合图1和图2可知，可以在阵列基板的衬底基板1之上形成有栅线8(图2中未示出)、与栅线8一体成型的薄膜晶体管2的栅极22和栅极绝缘层23等结构。
显然，图1和图2所示的阵列基板可以为扭曲向列型(Twisted Nematic，简称TN)模式的阵列基板。在此基础上，可以考虑对图2所示的阵列基板的结构进行改进，例如，如图3所示，该阵列基板在图2所示的阵列基板的基础上还可以包括位于所述像素电极3之上的第二绝缘层9和公共电极10，第二绝缘层9位于公共电极10和像素电极3之间，这保证了公共电极10和像素电极3的绝缘，以保证公共电极10和像素电极3之间产生一定的电压差，从而形成电场，以驱动液晶分子的偏转。此时该阵列基板为高级超维场转换(Advanced Super Dimension Switch，简称ADS)模式的阵列基板。
所谓高级超维场转换(Advanced Super Dimension Switch，简称ADS)技术,其核心技术特性描述为：通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高液晶工作效率并增大透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤 压水波纹(push Mura)等优点。针对不同应用，ADS技术的改进技术有高透过率I-ADS技术、高开口率H-ADS和高分辨率S-ADS技术等。
为保证公共电极10和像素电极3可以形成多维电场，在一个实施例中，图3中的公共电极10可以为狭缝状电极，像素电极3可以为板状电极。
在一个实施例中，公共电极10和第二绝缘层9也可设置于像素电极3之下。例如，如图4所示，所述阵列基板还可以包括位于所述薄膜晶体管2之下的第二绝缘层9和公共电极10，即该阵列基板的衬底基板1由下至上可以依次设置有公共电极10、第二绝缘层9、同层设置的栅线8(图4中未示出)和栅极22、栅极绝缘层23、薄膜晶体管2和数据线7等结构。
此时，为保证公共电极10和像素电极3可以形成多维电场，在一个实施例中，图4中的公共电极10可以为平板状，像素电极3可以为狭缝状电极。
由于近年来人们对于显示装置的透光率、分辨率、功耗等的要求越来越高，显示装置都在向着高透过率、高分辨率、低功耗等方向发展。显示装置的分辨率越高，每一个像素单元的尺寸越小，当像素单元的边长由几十微米变为十几微米时，显然，像素单元的尺寸得到了大幅度的减小，此时，若划分像素单元的黑矩阵的宽度仍然保持不变，相对于像素单元而言，黑矩阵将变得明显，将会影响显示装置的显示效果。因此，黑矩阵的宽度可相应的减小以保证显示装置的显示效果。之后，在黑矩阵圈出来的对应像素单元的显示区域上方形成彩膜(color filter)。
但是，黑矩阵的宽度减小可能导致阵列基板和彩膜基板之间的对盒(cell-assembly)出现偏差，进而导致漏光等不良现象的产生，因此位于彩膜基板上的黑矩阵的宽度不能任意减小。为了避免黑矩阵减小带来的漏光等不良现象，可以将黑矩阵和彩膜都形成在阵列基板上。由于黑矩阵位于阵列基板上，在适当减小黑矩阵的宽度时，也能保证黑矩阵能够充分遮挡栅线、数据线和薄膜晶体管等需遮光的结构的同时减少漏光现象发生的可能性，在提高分辨率、透过率的同时保证显示装置的显示效果。这种技术又叫做COA(Color Filter on Array)技术。
在本发明的一个实施例中，如图5所示，可以在图2所形成的结构之下、衬底基板1之上形成黑矩阵11和彩膜12，以形成COA阵列基板。在一个实施例中，如图6所示，还可在图4所示的阵列基板的层结构之下、衬底基板 1之上形成黑矩阵11和彩膜12，以形成COA的ADS阵列基板，在此不再赘述。在另一个实施例中，黑矩阵和彩膜也可以形成在阵列基板的上层。黑矩阵例如对应于栅线、数据线和薄膜晶体管形成，而彩膜单元对应于每个像素单元形成，例如包括红绿蓝色彩膜单元。
在不同实施例中，第一绝缘层4、栅极绝缘层23和第二绝缘层9等结构都可采用氧化硅、氮化硅、氧化铪或树脂等绝缘材料制成。
本发明的至少一个实施例还提供了一种显示装置，其包括上述任意一种阵列基板。例如，该显示装置可以为：液晶面板、电子纸、OLED面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
本发明实施例的液晶显示装置包括阵列基板与对置基板，二者彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。当阵列基板为COA基板时，对置基板上可不再设置黑矩阵和彩膜。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
本发明的至少一个实施例还提供了一种阵列基板的制备方法，如图7所示，该制备方法包括如下所述的步骤。
步骤S101、形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形。所述第一绝缘层包括第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端。
步骤S102、形成包括薄膜晶体管的源极和漏极的图形。所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
显然，在本发明实施例的技术方案中，采用首先形成像素电极，之后再形成源极和漏极的图形的方法，可有效防止在形成源极、漏极之后形成像素电极的过程中，铜等金属制成的源极和漏极等结构暴露在外造成的源极和漏极等结构被氧化等不良现象，保证了源极和漏极的导电能力，进而保证了阵列基板的正常工作、产品的良率，和用户的使用体验。
显然，在步骤S101之前，如图8所示，阵列基板上可以首先形成有同层形成的栅线8和栅极22等结构、以及栅极绝缘层23。由于栅极绝缘层23为透明绝缘层结构，因此图8中未示出。
在本发明的一个实施例中，如图9所示，步骤S101可以包括如下所述的步骤。
步骤S1011、形成有源层的图形。
如图10所示，在图8的基础上，通过例如等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)的方法沉积半导体薄膜，通过构图工艺，形成有源层21的图形。
步骤S1012、形成第一绝缘层和透明导电薄膜。
如图11所示，在图10的基础上，首先通过涂覆等方式形成第一绝缘层4，之后，采用磁控溅射或热蒸发等方式，在第一绝缘层4之上形成透明导电薄膜13。由于第一绝缘层4为透明绝缘层结构，因此图11中未示出。
图12为图11所示的阵列基板的截面图，从图12中可看到第一绝缘层4位于透明导电薄膜13之下。
步骤S1013、对所述第一绝缘层和所述透明导电薄膜进行构图工艺，形成所述第一绝缘层的第一过孔和第二过孔，并形成所述像素电极。
例如，如图13所示，首先在图12的基础上，在透明导电薄膜13之上通过涂覆等方式形成光刻胶层14，采用掩模板曝光，使光刻胶层14形成完全曝光区域141、未曝光区域142和部分曝光区域143，如图14所示。
通过刻蚀工艺，刻蚀掉完全曝光区域141对应的透明导电薄膜13和第一绝缘层4，形成像素电极3、第一透明导电部分15和第二透明导电部分16。像素电极3、第一透明导电部分15和第二透明导电部分16之间均通过刻蚀形成缝隙17，每一缝隙17的宽度例如均大于3微米，这可保证像素电极3、第一透明导电部分15和第二透明导电部分16相互绝缘。第一透明导电部分15、第二透明导电部分16分别覆盖有源层21的源极对应区域和漏极对应区域，如图15和16所示。
需要说明的是，由于光刻胶层14为透明结构，因此图15中并未示出，以下类似，不再赘述。
显然，所述像素电极3、第一透明导电部分15和第二透明导电部分16之下还设置有第一绝缘层4，如图16所示。
通过灰化工艺去除部分曝光区域143的光刻胶层，暴露出第一过孔5对应的第一绝缘层4和透明导电薄膜13，以及第二过孔6对应的第一绝缘层4 和透明导电薄膜13，通过相应的刻蚀手段依次刻蚀除去第一过孔5和第二过孔6对应的第一绝缘层4和透明导电薄膜13，如图17和18所示。
最后，去除未曝光区域141的光刻胶层14，即可实现在同一次构图工艺中分别形成第一绝缘层4的图形和像素电极3等结构的图形，如图19所示。
之后就可执行步骤S102，形成源极24和漏极25，完成薄膜晶体管2的制作过程。需要说明的是，若采用上述步骤S1011～步骤S1013的制作方法形成像素电极3和第一绝缘层4的图形，由于步骤S1013中形成的第一透明导电部分15和第二透明导电部分16之间的缝隙17将有源层21的对应区域暴露，如图19所示，因此，为了防止在源极24和漏极25的构图工艺中，源极24和漏极25对应的刻蚀液对有源层21造成腐蚀，而由于金属铜的刻蚀液对有源层21几乎无影响，因此在一个实施例中，利用金属铜来形成源极24和漏极25。
最后，形成如图1和2所示的阵列基板。
在本发明实施例中，由于源极24下铺设有第一透明导电部分15，使得源极24和第一透明导电部分15并联，这相当于减小有源层21和数据线7之间的电阻值，更有利于电信号的传输。类似的，漏极25下铺设有第二透明导电部分16，可减小有源层21和像素电极3之间的电阻值。
在本发明的一个实施例中，所述数据线7可与源极24和漏极25在同一次构图工艺中形成，即所述形成包括薄膜晶体管2的源极24和漏极25的图形包括：形成薄膜晶体管2的源极24和漏极25的图形、数据线7。
本发明实施例的阵列基板还可为ADS型阵列基板，因此，在一个实施例中，该阵列基板的制备方法还可包括：形成第二绝缘层和公共电极，所述第二绝缘层位于所述像素电极和所述公共电极之间。
例如，第二绝缘层9和公共电极10可以在图2所示的阵列基板的基础上形成，例如，形成如图3所示的阵列基板的结构；也可设置在形成栅线8和栅极22等结构、以及栅极绝缘层23之前形成公共电极10和第二绝缘层9，例如，形成如图4的阵列基板的结构。
本发明实施例的阵列基板也可为COA型阵列基板，因此，在一个实施例中，该阵列基板的制备方法还可包括：形成黑矩阵和彩膜。
例如，在本发明实施例中，如图5所示，可以在图2所形成的结构之下、 衬底基板1之上形成黑矩阵11和彩膜12，以形成COA阵列基板。类似的，如图6所示，还可在图4所示的阵列基板的层结构之下、衬底基板1之上形成黑矩阵11和彩膜12，以形成COA的ADS阵列基板，在此不再赘述。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2014年5月26日递交的中国专利申请第201410224631.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (10)

  1. 一种阵列基板，包括多个呈阵列排布的像素单元区域，其中，所述像素单元区域包括薄膜晶体管和像素电极，所述薄膜晶体管的有源层和所述像素电极之间形成有第一绝缘层，所述第一绝缘层形成有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
  2. 根据权利要求1所述的阵列基板，还包括：数据线，其中，所述数据线与所述薄膜晶体管的源极和漏极位于同一图层。
  3. 根据权利要求1或2所述的阵列基板，还包括：依次位于所述像素电极之上的第二绝缘层和公共电极。
  4. 根据权利要求1或2所述的阵列基板，还包括：依次位于所述薄膜晶体管之下的第二绝缘层和公共电极。
  5. 根据权利要求1-4任一所述的阵列基板，还包括：对应于像素单元区域设置的黑矩阵和彩膜。
  6. 一种显示装置，包括如权利要求1-5任一项所述的阵列基板。
  7. 一种阵列基板的制备方法，包括：
    形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形，其中，所述第一绝缘层包括第一过孔和第二过孔，所述第一过孔和所述第二过孔分别对应所述有源层的两端；
    形成包括薄膜晶体管的源极和漏极的图形，其中，所述薄膜晶体管的源极通过所述第一过孔连接所述有源层，所述薄膜晶体管的漏极搭接在所述像素电极之上并通过所述第二过孔连接所述有源层。
  8. 根据权利要求7所述的制备方法，其中，所述形成薄膜晶体管的有源层、第一绝缘层和像素电极的图形包括：
    形成有源层的图形；
    形成第一绝缘层和透明导电薄膜；
    对所述第一绝缘层和所述透明导电薄膜进行构图工艺，形成所述第一绝缘层的第一过孔和第二过孔，并形成所述像素电极。
  9. 根据权利要求7或8所述的制备方法，其中，所述形成包括薄膜晶体管的源极和漏极的图形包括：
    形成薄膜晶体管的源极和漏极的图形、数据线。
  10. 根据权利要求7-9任一所述的制备方法，还包括：
    形成第二绝缘层和公共电极，其中，所述第二绝缘层位于所述像素电极和所述公共电极之间。
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