WO2013104300A1 - 阵列基板及包括该阵列基板的显示装置 - Google Patents

阵列基板及包括该阵列基板的显示装置 Download PDF

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Publication number
WO2013104300A1
WO2013104300A1 PCT/CN2013/070240 CN2013070240W WO2013104300A1 WO 2013104300 A1 WO2013104300 A1 WO 2013104300A1 CN 2013070240 W CN2013070240 W CN 2013070240W WO 2013104300 A1 WO2013104300 A1 WO 2013104300A1
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Prior art keywords
layer
pixel electrode
array substrate
thin film
film transistor
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PCT/CN2013/070240
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English (en)
French (fr)
Inventor
宋泳锡
刘圣烈
崔承镇
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京东方科技集团股份有限公司
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Priority to US13/996,318 priority Critical patent/US8933472B2/en
Publication of WO2013104300A1 publication Critical patent/WO2013104300A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/48—Flattening arrangements

Definitions

  • Embodiments of the present invention relate to an array substrate and a display device including the array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • IPS In-Plane Switching
  • VA Very Alignment
  • AD-SDS Advanced-Super Dimensional Switching, also referred to as ADS
  • a multi-dimensional electric field is formed by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the liquid crystals are directly above the slit electrode in the liquid crystal cell and above the electrode.
  • the molecules are capable of rotating, thereby improving the efficiency of the liquid crystal and increasing the light transmission efficiency.
  • ADS technology can improve the quality of TFT-LCD images, with high transmittance, wide viewing angle, high aperture ratio, low chromatic aberration, low response time, and no Push Mura.
  • FIG. 1 it is a TFT array substrate structure in the conventional ADS mode, in which a schematic cross-sectional view of one pixel region is shown.
  • the bottommost layer is the glass substrate 1, and then the gate electrode 2, the insulating layer 3, and the active layer 4 are sequentially arranged upward from the glass substrate 1, and the drain 5 and the source 6 are formed over the active layer 4.
  • the relevant region with the drain 5 and the source 6 constitutes a thin film transistor (TFT) region in the pixel region, and the pixel electrode 7 (which can be regarded as a plate)
  • TFT thin film transistor
  • the pixel electrode 7 (which can be regarded as a plate)
  • the electrode is formed on the insulating layer 3 in contact with the drain 5, the source 6 is integrally formed with a data line (not shown), and the drain 5, the source 6 and the pixel electrode 7 are covered with a passivation layer 9,
  • a common electrode 8 (which can be regarded as a slit electrode) is formed on the passivation layer 9.
  • the relevant region of the pixel electrode 7 and the common electrode 8 constitutes a pixel electrode pattern region (also It is called the display area).
  • the fabrication process of the above array substrate is roughly as shown in FIG. 2.
  • the structure is applied to a small mobile product, although there is a certain increase in aperture ratio due to the absence of vias in the pixel, since it is also required to provide an additional color filter thereon, In the bonding process of the preparation process, the aperture ratio is too low due to the adhesion of the edges.
  • the embodiment of the present invention solves the problem that the liquid crystal molecules cannot be horizontally driven due to the break of the layers inside the pixel in the prior art, and the problem of light leakage due to disclination and deterioration of contrast is solved.
  • An aspect of the invention provides an array substrate including a gate line and a data line defining a pixel region, the pixel region including a thin film transistor region and a pixel electrode pattern region, wherein a gate electrode and a source region are formed in the thin film transistor region a drain, a gate insulating layer, an active layer, and a passivation layer, and a channel portion is formed between the source and the drain, the channel portion being recessed to the inside of the active layer;
  • the gate insulating layer, the pixel electrode, the passivation layer, and the common electrode are formed in the electrode pattern region, wherein the common electrode and the pixel electrode may form a plurality of pairs with respect to the array substrate after being energized, for example
  • the pixel electrode is formed on a portion of the surface of the active layer other than the channel portion and extends over the gate insulating layer in the pixel electrode pattern region; in the thin film transistor region, the A drain and a source are formed on the pixel electrode.
  • the source and the drain are formed on the active layer; at the portion where the pixel electrode pattern region is combined with the thin film transistor region, the pixel One end of the electrode is overlapped on one end of the source.
  • the material for the color resin layer is a material having a dielectric constant of 3 to 5 F/m and a thickness of 0.5 ⁇ m to 2 ⁇ m.
  • the material for the pixel electrode and the common electrode is transparent Conductive metal material.
  • a black matrix layer is formed on the passivation layer in the thin film transistor region.
  • the black matrix layer is an opaque resin layer
  • the material used for the array substrate is a material having a sheet resistance of more than 10 12 Q/sq, a thickness of 0.5 ⁇ m to 2 ⁇ m, and an optical density of 4 or more.
  • Another aspect of the present invention provides a display device comprising any of the array substrates as described above.
  • FIG. 1 is a schematic cross-sectional view of an array substrate in an ADS mode in the prior art
  • FIG. 2 is a flow chart showing the fabrication of the array substrate shown in FIG. 1;
  • Embodiment 3 is a schematic plan view of the array substrate of Embodiment 1 in a manufacturing process
  • Embodiment 4 is a schematic cross-sectional view showing the array substrate of Embodiment 1 in a manufacturing process
  • FIG. 6 is a schematic cross-sectional view showing the array substrate of Embodiment 2 in a manufacturing process
  • Fig. 8 is a schematic cross-sectional view showing a liquid crystal display device of Embodiment 3.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel regions arranged in a matrix, each of the pixel regions including a thin film transistor as a switching element and A pixel electrode and a common electrode for forming a driving electric field.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel regions, but other pixel regions may be formed identically.
  • the array substrate includes a gate line 21 and a data line 22 defining a plurality of pixel regions P on a base substrate (for example, a glass or plastic substrate), each of the pixel regions including a thin film transistor region and a pixel. Electrode graphic area.
  • a gate electrode 2, a gate insulating layer 3, an active layer 4, a source electrode 5, a drain electrode 6, and a passivation layer 9 are formed in the thin film transistor region, and a channel is formed between the source electrode 5 and the drain electrode 6.
  • the channel portion is recessed into the inside of the active layer 4; the gate electrode 2 is formed integrally with the gate line 21; and the drain electrode 6 is formed integrally with the data line 22.
  • the gate insulating layer 3, the pixel electrode 7, the passivation layer 9, and the common electrode 8 are formed in a pixel electrode pattern region defined by the formation regions of the common electrode 8 and the pixel electrode 7.
  • the common electrode 8 and the pixel electrode 7 may form a multi-dimensional electric field between each other after being energized.
  • a color resin layer 11 is formed between the layer 9 and the common electrode 8.
  • a black matrix layer 10 is formed on the passivation layer 9 in a thin film transistor region corresponding to the pixel electrode pattern region.
  • the source 5 and the drain 6 are formed on the active layer 4; at a portion where the pixel electrode pattern region is combined with the thin film transistor region, one end of the pixel electrode 7 Connected to one end of the source 5 .
  • the active layer 4 may include a silicon semiconductor layer such as amorphous silicon or an oxide semiconductor layer, and an ohmic contact layer may be formed on a side of the semiconductor material layer adjacent to the source and drain electrodes.
  • the material used for the pixel electrode 7 and the common electrode 8 may be a metal for wiring the gate and the data line, such as a metal having good conductivity such as Mo, AI, Ti, Cu, or an alloy thereof, or transparent and Conductive materials for selective etching, such as nano-amorphous indium tin oxide (a-ITO), indium oxide (Indium Zinc Oxide, IZO), etc., these materials are treated by TCO (Transparent Conducting Oxide)
  • TCO Transparent Conducting Oxide
  • the material used for the resin layer 11 may have a dielectric constant of 3 to 5 F/m and a thickness of
  • the resin layers provided in different pixel regions may be of different colors, such as red, green, and blue (RGB), respectively, or other color combinations, for example, may further include white (W).
  • RGB red, green, and blue
  • W white
  • These colored resin layers may be coated with a pigment-added resin material known in the art.
  • the black matrix layer 10 may be an opaque resin layer, and the material used is a surface resistance greater than
  • a material having a thickness of 0.5 ⁇ m to 2 ⁇ m and an optical density of 4 or more, for example, may also be an opaque metal oxide.
  • FIG. 3 and FIG. 4 the process can be summarized as follows: First, forming a gate line, a gate, a gate insulating layer, a pattern of an active layer, a source, and a drain, forming a thin film transistor region; then, forming a pattern including a color resin layer; finally, forming a pattern including a pixel electrode, a data line, a passivation layer, and a common electrode to form a pixel electrode pattern region.
  • steps S1-S6 shown in Fig. 3 and steps S101-S110 shown in Fig. 4 the example includes the following steps in detail:
  • Step S1 corresponding to steps S101 and S102, depositing a first conductive metal layer on the glass substrate 1, and etching the first metal layer by a first mask process using a monotone mask Grid line and gate 2;
  • Step S2 corresponding to steps S103 and S104, sequentially depositing a gate insulating layer 3 made of a material such as SiNx or SiON, a semiconductor active layer 4 made of a material such as a-Si, or the like on the formed structure; Depositing a second conductive metal layer thereon by using a second mask process using a halftone mask or a two-tone mask to obtain a channel portion corresponding to the source 5, the drain 6, and the thin film transistor a pattern of the photoresist pattern, and then etching the second metal layer to form the source 5 and the drain 6 by a continuous etching process and an ashing process, thereby forming a thin film transistor region;
  • Step S3 corresponding to S105, depositing a transparent and conductive third metallic layer on the above structure, forming the pixel electrode 7 by a third mask process and a continuous etching process, for example, using a monotone mask; Partially etching a portion of the semiconductor layer corresponding to the channel portion of the TFT; here, since etching a portion of the semiconductor layer corresponding to the channel portion of the TFT, the pixel electrode 7 is formed by etching in a third mask etching process After the steps are performed, therefore, the adverse effects of subsequent processes on the TFT channel can be prevented;
  • Step S4 corresponding to S106 and S107, depositing a SiNx passivation layer 9 to protect the TFT portion and the pixel portion in the above structure; around the upper portion of the TFT of the substrate and the panel, by using a fourth mask process of a monotone mask, Depositing a black matrix layer 10 of an opaque mask resin layer, and patterning the passivation layer 9;
  • Step S5 corresponding to S108 and S109, depositing a resin layer on the above structure, and forming, for example, RGB color by successively using a fifth mask process, a sixth mask process, and a seventh mask process using a single-tone mask.
  • a resin layer 11 depositing a SiNx layer on the substrate, and forming a hole for connecting the common electrode 8 and the lower portion of the storage capacitor bottom electrode formed of the gate metal through the eighth mask process;
  • Step S6 Corresponding to S110, a transparent and conductive fourth metal layer is deposited on the above structure, and the transparent common electrode 8 is formed by, for example, a ninth mask process using a single-tone mask and a continuous etching process.
  • the array substrate includes gate lines and data lines defining a plurality of pixel regions on a base substrate (eg, a glass or plastic substrate), each of the pixel regions including a thin film transistor region and a pixel electrode pattern region.
  • a base substrate eg, a glass or plastic substrate
  • the thin film transistor includes a gate electrode 2, a gate insulating layer 3, an active layer 4, a source electrode 5, a drain electrode 6, and a passivation layer 9, and a channel portion is formed between the source electrode 5 and the drain electrode 6
  • the channel portion is recessed into the inside of the active layer 4; the gate insulating layer 3, the pixel electrode 7, and the passivation layer are formed in the pixel electrode pattern region defined by the formation regions of the common electrode 8 and the pixel electrode 7. 9 and the common electrode 8.
  • the common electrode 8 and the pixel electrode 7 constitute a multi-dimensional electric field between each other after being energized.
  • a color resin layer 11 is formed between the common electrode 8 and the passivation layer 9.
  • a black matrix layer 10 is formed on the passivation layer 9 in a thin film transistor region corresponding to the pixel electrode pattern region.
  • the pixel electrode 7 is formed on a portion of the surface of the active layer 4 other than the channel portion, and extends over the gate insulating layer 3 in the pixel electrode pattern region; and in the thin film transistor region The drain 5 and the source 6 are formed on the pixel electrode 7.
  • the difference lies in: the difference in position between the pixel electrode 7 and the drain 5 and the source 6, when the pixel electrode 7 is located below the source 6.
  • the pixel electrode 7 and the source electrode 6 can be completed by a mask process, so that there is a large difference in process between the two. 4 is performed in the order of gate 2 - active layer 3 - drain 5, source 6 - pixel electrode 7 - ..., in FIG. 6 with gate 2 - active layer 3 - pixel electrode
  • the order of 7-drain 5, source 6-... is used to carry out the preparation process.
  • the materials of the respective layers in Example 2 may be selected from the materials of the respective layers in Example 1.
  • the array substrate provided by the embodiment of the present invention has the following advantages:
  • the array substrate of the ADS mode in which the color filter is integrated can be manufactured by only nine mask processes;
  • connection hole in the pixel structure, which further increases the aperture ratio, and further, it is advantageous not only for a large panel but also for the manufacture of a small panel.
  • Embodiment 3 of the present invention further provides a display device comprising the array substrate of any of the above embodiments.
  • the display device may be a product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the liquid crystal display device includes an array substrate 200 and a counter substrate 300 which are opposed to each other and sealed by a sealant 300 to form a liquid crystal cell in which a liquid crystal material 400 is filled.
  • the array substrate 200 may be the array substrate of Embodiment 1 or 2, and the pixel electrode of each pixel region is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the counter substrate 300 may be a white glass substrate or a plastic substrate.
  • the liquid crystal display device can also include a backlight 500 that provides backlighting for the array substrate.

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Abstract

一种阵列基板，其在薄膜晶体管区域内形成有栅极（2）、源极（5）、漏极（6）、栅绝缘层（3）、有源层(4）以及钝化层（9），在像素电极图形区域中形成栅绝缘层（3）、像素电极（7）、钝化层（9）以及公共电极(8），且在钝化层（9）与公共电极（8）之间形成有彩色树脂层（11）。由于在钝化层（9）上形成了有利地平坦化的彩色树脂层（11），从而可以适合水平驱动的方式来尽量降低漏光，提高面板的对比度、开口率并降低生产成本。

Description

阵列基板及包括该阵列基板的显示装置 技术领域
本发明的实施例涉及一种阵列基板及包括该阵列基板的显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )具有体积小、 功耗低、 无辐射等特点， 在平板显示器市场占据了 主导地位。 随着技术的进步， 消费者对移动性产品的显示效果提出了更高的 要求， 普通的 TN ( Twisted Nematic, 扭曲向列）型液晶显示器的显示效果已 经不能满足市场的需求。 性产品中，比如 IPS ( In-Plane Switching,共面转换）、 VA( Vertical Alignment, 垂直配向） 、 AD-SDS ( Advanced-Super Dimensional Switching, 高级超维场 开关， 也简称为 ADS )等广视角技术。 在 ADS模式下， 通过同一平面内狭 缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多 维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子都能够产生 旋转， 从而提高了液晶工作效率并增大了透光效率。 由此， ADS技术可以提 高 TFT-LCD画面品质， 具有高透过率、 宽视角、 高开口率、 低色差、 低响 应时间、 无挤压水波紋（ Push Mura )等优点。
如图 1所示， 为现有的 ADS模式下的 TFT阵列基板结构， 其中示出了 一个像素区域的截面示意图。 在该阵列基板之中， 最底层为玻璃基板 1 , 然 后从玻璃基板 1向上依次为栅极 2、 绝缘层 3、 有源层 4, 在有源层 4上方形 成有漏极 5和源极 6, 在光线传播的方向上（即图中的垂直方向上） ， 与该 漏极 5和源极 6的相关区域构成像素区域中的薄膜晶体管 （TFT ) 区域， 像 素电极 7 (可视为板状电极 )形成在绝缘层 3上与漏极 5相接触， 源极 6与 数据线（未示出）一体形成， 在漏极 5、 源极 6及像素电极 7上覆盖有钝化 层 9, 在钝化层 9上形成公共电极 8 (可视为狭缝电极）， 在光线传播的方向 上， 像素电极 7与公共电极 8的相关区域则构成了像素电极图形区域（也可 以称为显示区域） 。
上述阵列基板的结构的制作过程大致如图 2所示。 该结构在应用于小型 移动产品时， 尽管由于不存在像素内过孔， 使得其开口率会存在一定程度的 增加， 但由于还需要在其上提供另外的彩色滤光片 （ Color Filter ) , 所以在 制备工艺的粘合过程中会因边缘的粘合状况而导致开口率随之过低。
此外， 从图 1中可以看出， 由于 TFT结构与数据线（源极 6 ) 的上表面 之间存有断差（step ) , 而该断差显然不利于 ADS模式应用水平的驱动方式， 从而会使得液晶无法正常驱动， 进而引发漏光并导致对比度（Contrast Ratio, CR ) 降低。 发明内容
本发明的实施例针对现有技术中因像素内部各层的断差导致无法对液晶 分子进行水平驱动的情况， 解决了因为向错（disclination ) 而引起漏光并使 对比度劣化的问题。
本发明的一个方面提供一种阵列基板， 包括限定了像素区域的栅线和数 据线， 所述像素区域包括薄膜晶体管区域以及像素电极图形区域， 所述薄膜 晶体管区域中形成有栅极、 源极、 漏极、 栅绝缘层、 有源层以及钝化层， 且 在所述源极和漏极之间形成有沟道部， 所述沟道部凹陷至所述有源层内部； 所述像素电极图形区域中形成有所述栅绝缘层、 像素电极、 所述钝化层以及 公共电极， 其中， 所述公共电极和像素电极在通电之后可在彼此之间形成多 对于所述阵列基板， 例如， 所述像素电极形成于所述有源层表面除沟道 部以外的部位上， 并延伸覆盖所述像素电极图形区域中的所述栅极绝缘层； 在所述薄膜晶体管区域内， 所述漏极及源极形成于所述像素电极上。
对于所述阵列基板， 例如， 在所述薄膜晶体管区域内， 所述源极及漏极 形成于有源层上； 在所述像素电极图形区域与薄膜晶体管区域相结合的部位 处， 所述像素电极的一端搭接于所述源极的一端上。
对于所述阵列基板， 例如， 所述彩色树脂层釆用的材料为介电常数为 3~5F/m且厚度为 0.5μπι~2μπι的材料。
对于所述阵列基板， 例如， 所述像素电极和公共电极釆用的材料为透明 导电的金属材料。
对于所述阵列基板， 例如， 所述薄膜晶体管区域内， 所述钝化层上形成 有黑矩阵层。
对于所述阵列基板， 例如， 所述黑矩阵层为不透明树脂层， 其所釆用的 材料为面电阻大于 1012Q/sq、 厚度为 0.5μπι~2μπι且光密度为 4以上的材料。
此外， 本发明的另一个方面还提供了一种显示装置， 其包括如上所述任 一种阵列基板。 附图说明
为了更清楚地说明本实施例的技术方案， 下面将对实施例的附图作简单 地介绍， 显而易见地， 下面描述中的附图仅仅涉及本发明的一些实施例， 而 非对本发明的限制。
图 1为现有技术中 ADS模式下阵列基板的截面示意图；
图 2为图 1所示的阵列基板的制作流程图；
图 3为实施例 1的阵列基板在制造过程中的俯视示意图；
图 4为实施例 1的阵列基板在制造过程中的截面示意图；
图 5为实施例 1的阵列基板的截面示意图；
图 6为实施例 2的阵列基板在制造过程中的截面示意图；
图 7为实施例 2的阵列基板的截面示意图；
图 8为实施例 3的液晶显示装置的截面示意图。
附图标记：
1 : 玻璃基板、 2: 栅极、 3: 栅极绝缘层、 4: 有源层、 5: 漏极、 6: 源 极、 7: 像素电极、 8: 公共电极、 9: 钝化层、 10: 黑矩阵层、 11 : 彩色树脂 层； 21 : 栅线； 22: 数据线； 200: 阵列基板； 300: 对置基板； 300: 封框胶； 400: 液晶材料。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 "一个" 或者 "一" 等类似词 语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类 似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排除其他元 件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理的或者机 械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对 位置改变后， 则该相对位置关系也可能相应地改变。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素区域， 每个像素区域包括作为开关 元件的薄膜晶体管和例如用于形成驱动电场的像素电极和公共电极。 例如， 每个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应 的数据线电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下 面的描述主要针对单个或多个像素区域进行， 但是其他像素区域可以相同地 形成。
实施例 1
本实施例提供一种阵列基板， 其可以应用于 ADS模式。 如图 3及图 4 所示， 该阵列基板包括在基底基板（例如玻璃或塑料基板）上限定了多个像 素区域 P的栅线 21和数据线 22, 每个像素区域包括薄膜晶体管区域以及像 素电极图形区域。
所述薄膜晶体管区域中形成有栅极 2、 栅绝缘层 3、 有源层 4、 源极 5、 漏极 6以及钝化层 9, 且在源极 5和漏极 6之间形成有沟道部， 所述沟道部 凹陷至有源层 4内部； 栅极 2与栅线 21—体形成； 漏极 6与数据线 22—体 形成。
在由所述公共电极 8和像素电极 7的形成区域所界定的像素电极图形区 域内形成了所述栅绝缘层 3、 像素电极 7、 钝化层 9以及公共电极 8。 所述公 共电极 8和像素电极 7在通电之后可以在彼此之间形成多维电场。 在所述钝 化层 9与公共电极 8之间形成有彩色树脂层 11。在与所述像素电极图形区域 相对应的薄膜晶体管区域内， 在所述钝化层 9上形成有黑矩阵层 10。
在所述薄膜晶体管区域内， 所述源极 5及漏极 6形成于有源层 4上； 在 所述像素电极图形区域与薄膜晶体管区域相结合的部位处， 所述像素电极 7 的一端搭接于所述源极 5的一端上。
有源层 4可以包括非晶硅等硅半导体层或包括氧化物半导体层， 在半导 体材料层与源漏极相邻的一侧上还可以形成有欧姆接触层。
所述像素电极 7、 公共电极 8所釆用的材料可以为用于栅极与数据线布 线的金属， 比如 Mo、 AI、 Ti、 Cu等导电性好的金属或其合金， 或者是透明 且可进行选择性刻蚀的导电材料， 比如纳米无定形铟锡氧化物（a-ITO ) , 氧 化铟辞 （Indium Zinc Oxide, IZO ) 等， 这些材料经过 TCO ( Transparent Conducting Oxide, 透明导电氧化）处理成为透明性良好的金属性材料。 这样 的金属性材料（例如， a-ITO、 IZO )等与用于布线的金属 （Mo、 AI... )等 为可选择进行湿法刻蚀（Wet Etch ) 的材料。
所述树脂层 11 所釆用的材料可以为介电常数为 3~5F/m 且厚度为
0.5μπ！〜 2μπι的材料； 不同像素区域中所提供的树脂层可以是不同颜色的， 例 如分别为红色、 绿色和蓝色（RGB ) , 或其他颜色组合， 例如还可以进一步 包括白色（W ) 。 这些彩色树脂层可以釆用本领域已知的添加了颜料的树脂 材料。
所述黑矩阵层 10 可以为不透明树脂层， 其所釆用的材料为面电阻大于
10¾/sq, 厚度为 0.5μπι~2μπι且光密度为 4以上的材料， 例如还可以为不透 明的金属氧化物。
根据上述的结构， 下面具体描述该 ADS模式下的阵列基板结构的制作 工艺的一个示例， 对照图 3及图 4, 该工艺可以概括为： 首先， 形成包括栅 线、 栅极、 栅绝缘层、 有源层、 源极、 漏极的图形， 构成薄膜晶体管区域； 然后， 形成包括彩色树脂层的图形； 最后， 形成包括像素电极、 数据线、 钝 化层、公共电极的图形，构成像素电极图形区域。参见图 3中示出的步骤 S1-S6 以及图 4中示出的步骤 S101-S110, 该示例详细地包括如下步骤：
步骤 S1: 对应于步骤 S101及 S102, 在玻璃基板 1上沉积导电性好的第 一金属层， 通过利用单色调掩模板的第一掩膜工艺将该第一金属层刻蚀形成 栅线及栅极 2;
步骤 S2:对应于步骤 S103及 S104,在所形成的结构上依次沉积釆用 SiNx 或 SiON等材料的栅绝缘层 3、釆用 a-Si等材料的半导体有源层 4; 在所形成 的基板上沉积导电性好的第二金属层，通过利用半色调掩膜 ( Halftone Mask ) 板或双色调掩模板的第二掩膜工艺得到具有对应于源极 5、 漏极 6以及薄膜 晶体管沟道部的图案的光刻胶图形， 然后利用连续刻蚀工艺和灰化工艺将第 二金属层刻蚀形成源极 5、 漏极 6, 从而构成薄膜晶体管区域；
步骤 S3: 对应于 S105, 在上述结构上沉积透明且导电性好的第三金属 性层 , 通过例如利用单色调掩模的第三掩膜工艺与连续刻蚀工艺来形成像素 电极 7; 之后， 部分刻蚀对应于上述 TFT沟道部的部分半导体层； 此处， 由 于刻蚀对应于 TFT沟道部的部分半导体层的过程，是在以第三掩膜刻蚀工艺 刻蚀形成像素电极 7的步骤之后进行的， 因此， 可防止后续工艺对 TFT沟道 的不良影响；
步骤 S4: 对应于 S106及 S107 , 沉积 SiNx钝化层 9来保护上述结构中 的 TFT部分与像素部分； 在上述基板的 TFT上部与面板周围， 通过利用单 色调掩模板的第四掩膜工艺， 沉积不透明掩膜树脂层的黑矩阵层 10, 并制作 出钝化层 9的图案；
步骤 S5: 对应于 S108及 S109, 在上述结构上沉积树脂层， 并通过连续 的利用单色调掩模板的第五掩膜工艺、 第六掩膜工艺、 第七掩膜工艺， 来形 成例如 RGB彩色树脂层 11； 在上述基板上沉积 SiNx层， 并通过第八掩膜工 艺， 形成用于将公共电极 8与下部由栅金属形成的存贮电容底电极进行连接 的孔；
步骤 S6: 对应于 S110, 在上述结构上沉积透明且导电性好的第四金属 层， 通过例如利用单色调掩模板的第九掩膜工艺以及连续的刻蚀工艺来形成 透明的公共电极 8。
最后，形成如图 5所示的阵列基板，其中示出了一个像素区域的截面图。 实施例 2
本实施例提供另一种 ADS模式下的阵列基板， 如图 6及图 7所示。 所 述阵列基板包括在基底基板（例如玻璃或塑料基板）上限定了多个像素区域 的栅线和数据线，每个像素区域包括薄膜晶体管区域以及像素电极图形区域。 所述薄膜晶体管包括栅极 2、 栅绝缘层 3、 有源层 4、 源极 5、 漏极 6以及钝 化层 9,且在源极 5和漏极 6之间形成有沟道部，所述沟道部凹陷至有源层 4 内部； 在由所述公共电极 8和像素电极 7的形成区域所界定的像素电极图形 区域内形成了所述栅绝缘层 3、 像素电极 7、 钝化层 9以及公共电极 8。 所述 公共电极 8和像素电极 7在通电之后在彼此之间构成了多维电场。 在所述公 共电极 8与钝化层 9之间形成有彩色树脂层 11。在与所述像素电极图形区域 相对应的薄膜晶体管区域内， 在所述钝化层 9上形成有黑矩阵层 10。
所述像素电极 7形成于所述有源层 4表面除沟道部以外的部位上， 并延 伸覆盖所述像素电极图形区域中的所述栅极绝缘层 3; 且在所述薄膜晶体管 区域内， 所述漏极 5及源极 6形成于所述像素电极 7上。
图 4与图 6的制作流程中相同的部分在此不再赘述,其中差别之处在于： 像素电极 7与漏极 5、 源极 6之间的位置差别， 当像素电极 7位于源极 6下 方时， 像素电极 7与源极 6可通过一个掩膜工艺来完成， 从而两者之间存在 工艺上较大的差别。 图 4中以栅极 2-有源层 3-漏极 5、 源极 6-像素电极 7-... 的顺序来进行制备工艺， 图 6中以栅极 2-有源层 3-像素电极 7-漏极 5、 源极 6- ...的顺序来进行制备工艺。
实施例 2中各层的材料可以选用实施例 1中相应各层的材料。
与图 1、 图 2所示的现有技术相比较， 本发明的实施例所提供的阵列基 板具备如下优点：
( 1 ) 可以仅通过九个掩膜工艺即可制造完成集成了彩色滤光片的 ADS 模式的阵列基板；
( 2 )通过将利于平坦化的彩色树脂的图案制作于 TFT钝化层的上部， 来消除 TFT与数据线上面的断差，液晶排列时依靠部分液晶的扭曲来消除光 线的弯曲。 从而可以正常驱动釆取水平驱动方式的 ADS模式， 进而可以提 高对比度；
( 3 )可以避免现有的阵列基板与彩膜基板进行贴合而引起开口率降低的 问题， 可以保持高开口率， 并且因为该高开口率的结构 （数据线与公共线的 重叠） ， 从而可以提高透过率；
( 4 )像素结构中存在连接孔， 进一步提高了开口率， 此外， 其不仅有利 于大型面板， 同时也有利于小型面板的制造。 实施例 3
同时， 本发明的实施例 3还提供一种显示装置， 所述显示装置包括上述 实施例中任一种的阵列基板。所述显示装置可以为液晶面板、 电子纸、 OLED 面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具有显示功能 的产品或部件。
该显示装置的一个示例为液晶显示装置。 如图 8所示， 该液晶显示装置 包括阵列基板 200与对置基板 300, 二者彼此对置并通过封框胶 300密封周 边以形成液晶盒， 在液晶盒中填充有液晶材料 400。 阵列基板 200可以为实 施例 1或 2的阵列基板， 其每个像素区域的像素电极用于施加电场对液晶材 料的旋转的程度进行控制从而进行显示操作。 对置基板 300可以为白玻璃基 板或塑料基板。 该液晶显示装置还可以包括为阵列基板提供背光的背光源 500。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括限定了像素区域的栅线和数据线， 所述像素区域 包括薄膜晶体管区域以及像素电极图形区域， 所述薄膜晶体管区域中形成有 栅极、 源极、 漏极、 栅绝缘层、 有源层以及钝化层， 且在所述源极和漏极之 间形成有沟道部， 所述沟道部凹陷至所述有源层内部； 所述像素电极图形区 域中形成有所述栅绝缘层、 像素电极、 所述钝化层以及公共电极， 所述公共 电极和像素电极在通电之后可在彼此之间形成多维电场； 2、如权利要求 1所述的阵列基板， 其中， 所述像素电极形成于所述有源 层表面除沟道部以外的部位上， 并延伸覆盖所述像素电极图形区域中的所述 栅极绝缘层；
在所述薄膜晶体管区域内， 所述漏极及源极形成于所述像素电极上。
3、 如权利要求 1所述的阵列基板， 其中， 在所述薄膜晶体管区域内， 所 述源极及漏极形成于有源层上；
在所述像素电极图形区域与薄膜晶体管区域相结合的部位处， 所述像素 电极的一端搭接于所述源极的一端上。
4、如权利要求 1所述的阵列基板， 其中， 所述彩色树脂层釆用的材料为 介电常数为 3~5F/m且厚度为 0.5μπ！〜 2μπι的材料。
5、如权利要求 1所述的阵列基板， 其中， 所述像素电极和公共电极釆用 的材料为透明导电材料。
6、 如权利要求 1所述的阵列基板， 其中， 所述薄膜晶体管区域内， 所述 钝化层上形成有黑矩阵层。
7、如权利要求 6所述的阵列基板，其中，所述黑矩阵层为不透明树脂层， 其所釆用的材料为面电阻大于 1012Q/sq、厚度为 0.5μπι~2μπι且光密度为 4以 上的材料。
8、 一种显示装置， 包括如权利要求 1所述的阵列基板。
PCT/CN2013/070240 2012-01-12 2013-01-09 阵列基板及包括该阵列基板的显示装置 WO2013104300A1 (zh)

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