WO2021098475A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021098475A1
WO2021098475A1 PCT/CN2020/124931 CN2020124931W WO2021098475A1 WO 2021098475 A1 WO2021098475 A1 WO 2021098475A1 CN 2020124931 W CN2020124931 W CN 2020124931W WO 2021098475 A1 WO2021098475 A1 WO 2021098475A1
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Prior art keywords
layer
area
connection
connection layer
lead
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PCT/CN2020/124931
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English (en)
French (fr)
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张陶然
周炟
廖文骏
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/299,317 priority Critical patent/US20220059639A1/en
Publication of WO2021098475A1 publication Critical patent/WO2021098475A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • This article relates to but not limited to the field of display technology, and in particular refers to a display substrate, a preparation method thereof, and a display device.
  • part of the frame is usually bent to the back of the screen.
  • the frame area used to set the driver chip and bonding circuit is bent to the back of the screen to set the frame of the driver chip and bonding circuit.
  • a bending area ie, Pad Bending area
  • Pad Bending area can be set between the area and other border areas that are not to be bent.
  • the embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display device.
  • an embodiment of the present disclosure provides a display substrate including: a display area, a bending area, and a first transition area between the display area and the bending area.
  • the display area is provided with a signal line layer
  • the bending area is provided with a first lead layer
  • the first transition area is provided with a first connection layer
  • the first connection layer is provided with at least one inorganic insulating layer.
  • the signal line layer is electrically connected to the first connection layer through a first via hole opened in the first step, and the first lead layer is electrically connected to the first connection layer.
  • an embodiment of the present disclosure provides a display device including the display substrate as described above.
  • inventions of the present disclosure provide a method for preparing a display substrate.
  • the display substrate includes a display area, a bending area, and a first transition area between the display area and the bending area.
  • the preparation method includes: forming a first connection layer in a first transition area, forming a first step on the first connection layer, the first step being formed by at least one inorganic insulating layer; forming a signal line layer in the display area, The bending area forms the first lead layer.
  • the signal line layer is electrically connected to the first connection layer through a first via hole opened in the first step, and the first lead layer is electrically connected to the first connection layer.
  • FIG. 1 is a schematic diagram of the structure of a display substrate
  • Figure 2 is a partial cross-sectional view in the direction of R-R in Figure 1;
  • FIG. 3 is a schematic diagram of a structure of a display substrate according to at least one embodiment of the present disclosure
  • Figure 4 is a partial cross-sectional view in the direction of I-I in Figure 3;
  • FIG. 5 is a schematic diagram of a display substrate after forming a barrier layer in at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the display substrate after forming a third insulating layer pattern in at least one embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of the display substrate after the first step and the third step are formed in at least one embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a display substrate after forming a first via hole, a second via hole, and a fifth via hole in at least one embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a display substrate after patterns of a signal lead layer, a first lead layer, and a source/drain electrode layer are formed in at least one embodiment of the present disclosure
  • FIG. 10 is a schematic partial top view of a display area, a first transition area, and a bending area according to at least one embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of another structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of another structure of the display substrate according to at least one embodiment of the present disclosure.
  • Figure 13 is a partial cross-sectional view in the direction of Q-Q in Figure 12;
  • FIG. 14 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • the present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements disclosed in the present disclosure can also be combined with any conventional features or elements to form a unique invention solution defined by the claims.
  • Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution defined by the claims. Therefore, it should be understood that any feature shown or discussed in this disclosure can be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other restrictions except for the restrictions made according to the appended claims and their equivalents.
  • at least one modification and change may be made within the protection scope of the appended claims.
  • the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method or process should not be limited to performing their steps in the written order, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure.
  • the inorganic film is grooved in the bending area to reduce the thickness of the inorganic film layer in the bending area, thereby achieving a 180-degree bending.
  • trenching with inorganic film in the bending area will form steps in the inorganic film layer, resulting in large gaps in the signal traces at the steps, resulting in electrical conduction in the dry etching (Dry Etch) process of the signal traces.
  • Material residue (Remain) causes a short circuit, which in turn causes the display panel to produce dark or bright lines (X-Line) defects, which affects the product yield.
  • FIG. 1 is a schematic diagram of the structure of a display substrate.
  • Fig. 2 is a partial cross-sectional view in the direction of R-R in Fig. 1.
  • the display substrate includes: a display area A, a bending area B, and a peripheral area C.
  • the display area A is provided with a sub-pixel array and signal lines
  • the peripheral area C can be provided with a driving chip
  • the driving chip can provide a driving signal to the display area A.
  • the bending area B is located between the display area A and the peripheral area C.
  • the bending area B is provided with signal leads, which are configured to electrically connect the driving chip in the peripheral area C and the signal line in the display area A.
  • the peripheral area C can be folded through the bending area B, for example, to the back of the display area A.
  • the sub-pixel array in the display area includes: thin film transistors and storage capacitors.
  • the thin film transistor includes a barrier layer 11, an active layer 12, a first insulating layer 13, a first gate electrode 14, a second insulating layer 16, a third insulating layer 18, and a source and drain electrode layer which are sequentially arranged on the substrate 10.
  • the storage capacitor includes a second gate electrode 15, a capacitor insulating layer (ie, the second insulating layer 16 ), and a capacitor electrode 17 which are sequentially disposed on the substrate 10.
  • the third insulating layer in the bending area can be sequentially removed by two mask processes (for example, EBA (Edge Bending A) mask and EBB (Edge Bending B) mask) 18.
  • EBA Edge Bending A
  • EBB Edge Bending B
  • the signal leads 21 in the bending area are arranged in the same layer as the source and drain electrode layers in the display area, and are prepared by the same process.
  • the embodiments of the present disclosure provide a display substrate, a preparation method thereof, and a display device, which can improve the problem of residual conductive material at the step of the inorganic film layer in the bending area.
  • An embodiment of the present disclosure provides a display substrate, including: a display area, a bending area, and a first transition area between the display area and the bending area.
  • the display area is provided with a signal line layer
  • the bending area is provided with a first lead layer
  • the first transition area is provided with a first connection layer
  • the first connection layer is provided with a first step formed by at least one inorganic insulating layer.
  • the signal line layer is electrically connected to the first connection layer through the first via hole opened in the first step
  • the first lead layer is electrically connected to the first connection layer.
  • the inorganic insulating layer forming the first step may include an interlayer insulation (ILD, Inner Layer Dielectric) layer, or an interlayer insulation layer and a gate insulation (GI, Gate Insulator) layer.
  • ILD Interlayer insulation
  • GI Gate Insulator
  • an inorganic insulating layer is provided between the first lead layer and the first connection layer, and the first lead layer is electrically connected to the first connection layer through a second via hole penetrating the inorganic insulating layer.
  • the inorganic insulating layer provided between the first lead layer and the first connection layer may be a gate insulating layer.
  • this embodiment is not limited to this.
  • the material of the first connection layer may be a metal (for example, molybdenum Mo) or a material with semiconductor properties (for example, polysilicon).
  • the display substrate may further include: a second transition area and a peripheral area, and the second transition area is located between the bending area and the peripheral area.
  • the peripheral area is provided with a second lead layer
  • the second transition area is provided with a second connection layer
  • the second connection layer is provided with a second step formed by at least one inorganic insulating layer.
  • the second lead layer is electrically connected to the second connection layer through a third via hole opened in the second step
  • the first lead layer is electrically connected to the second connection layer.
  • the inorganic insulating layer forming the second step may include: an interlayer insulating layer, or, an interlayer insulating layer and a gate insulating layer. However, this embodiment is not limited to this.
  • an inorganic insulating layer is provided between the first lead layer and the second connection layer, and the first lead layer is electrically connected to the second connection layer through a fourth via hole penetrating the inorganic insulating layer.
  • the inorganic insulating layer provided between the first lead layer and the second connecting layer may be a gate insulating layer.
  • this embodiment is not limited to this.
  • the second connection layer and the first connection layer are arranged in the same layer and use the same material.
  • the embodiment of the present disclosure realizes the electrical connection between the signal line layer of the display area and the first lead layer of the bending area by providing the first connection layer, avoiding the arrangement of traces on the first step, thereby improving the etching process.
  • the residual problem of conductive material at the step can realize the normal signal transmission, improve the product yield, and ensure the display effect.
  • FIG. 3 is a schematic diagram of a structure of a display substrate according to at least one embodiment of the present disclosure.
  • Fig. 4 is a partial cross-sectional view in the direction of I-I in Fig. 3.
  • the main structure of the display substrate includes: a display area A, a first transition area D1, a bending area B, and a peripheral area C.
  • the first transition area D1 is located between the display area A and the bending area B
  • the peripheral area C is located on the side of the bending area B away from the first transition area D1.
  • the peripheral area C can be provided with a driving chip, and the driving chip can provide a driving signal to the display area A.
  • the bending area may also be located on opposite sides of the upper and lower sides of the display area, or located on four sides of the display area.
  • FIG. 4 illustrates the structure of the display area, the first transition area and the bending area on a plane perpendicular to the display substrate.
  • the main structure of the display area includes a plurality of light-emitting units and signal lines distributed in an array.
  • At least one of the plurality of light-emitting units includes a driving structure layer and a light-emitting structure layer disposed on a substrate, and the driving structure layer includes a plurality of thin film transistors (TFT).
  • the signal lines may include data lines and gate lines (not shown).
  • only one thin film transistor included in one light-emitting unit is taken as an example for illustration.
  • the driving structure layer mainly includes a barrier layer 11 arranged on the substrate 10, a thin film transistor and a storage capacitor arranged on the barrier layer 11.
  • the thin film transistor includes an active layer 12, a first insulating layer 13, a first gate electrode 14, a second insulating layer 16, a third insulating layer 18, and a source and drain electrode layer (for example, including source and drain electrode layers) which are sequentially arranged on the barrier layer 11.
  • the storage capacitor includes a second gate electrode 15, a capacitor insulating layer (ie, the second insulating layer 16 ), and a capacitor electrode 17 which are sequentially disposed on the substrate 10.
  • the main structure of the bending area includes: a barrier layer 11 provided on the base 10 and a first lead layer 22 provided on the barrier layer 11.
  • the main structure of the first transition region includes: a barrier layer 11 arranged on the substrate 10, a first insulating layer 13 arranged on the barrier layer 11, a first connection layer 23 arranged on the first insulating layer 13, and a first connecting layer 23 arranged on the first insulating layer 13.
  • the first step T1 is formed by the third insulating layer 18.
  • the signal line layer 24 in the display area is electrically connected to the first connection layer 23 through the first via hole opened in the first step T1.
  • the first lead layer 22 in the bending area is electrically connected to the first connection layer 23 through a second via hole penetrating the second insulating layer 16.
  • the first connection layer 23 can realize the electrical connection between the signal line layer 24 in the display area and the first lead layer 22 in the bending area, avoiding the formation of traces on the first step T1, and can improve the first step in the etching process.
  • the second insulating layer 16 remains on the first connection layer 23, which can reduce the short circuit caused by the conductive material above and the first connection layer 23.
  • the "patterning process" mentioned in this embodiment includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, photoresist stripping, etc., which are known and mature preparation processes.
  • the deposition may use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating may use a known coating process, and the etching may use a known method, which is not limited here.
  • 5 to 9 are schematic diagrams of the manufacturing process of the display substrate according to at least one embodiment of the present disclosure.
  • the preparation process of the display substrate includes the following steps.
  • a barrier layer is formed on the substrate.
  • Forming a barrier layer on the substrate includes depositing a barrier film on the substrate 10 to form a barrier layer 11, as shown in FIG. 5.
  • the substrate 10 may be a flexible substrate, using materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft film.
  • the barrier film may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., and may be a single layer or a multilayer structure of silicon nitride/silicon oxide.
  • the barrier layer 11 can be used to improve the water and oxygen resistance of the substrate 10.
  • Forming the active layer pattern on the substrate includes: depositing an active layer film on the substrate 10 forming the above structure, and patterning the active layer film through a patterning process to form the active layer 12 disposed on the barrier layer 11
  • the pattern is shown in Figure 6. Wherein, the pattern of the active layer 12 is only formed in the display area, and only the barrier layer 11 is formed in the bending area and the first transition area at this time.
  • the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p- At least one material such as Si), hexathiophene, polythiophene, etc., that is, this embodiment is also applicable to displays based on top gate (Top Gate) thin film transistors (TFT) manufactured based on oxide (Oxide) technology, silicon technology, and organic technology. Substrate.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • polysilicon p- At least one material such as Si
  • TFT thin film transistors
  • Forming the gate electrode layer and the first connection layer pattern includes: sequentially depositing a first insulating film and a first metal film on the substrate 10 forming the above structure, and patterning the first metal film through a patterning process to form the covering active layer 12 And the first insulating layer 13 of the barrier layer 11, the first connection layer 23 disposed on the first insulating layer 13, the first gate electrode 14, the second gate electrode 15 and the gate line (not shown) pattern, as shown in FIG. 6 Shown.
  • the first connection layer 23 is formed in the first transition area; the first gate electrode 14, the second gate electrode 15 and the gate line (not shown) are formed in the display area.
  • the first insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high dielectric constant (High-k) materials, such as aluminum oxide (AlOx), Hafnium oxide (HfOx), tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • High-k high dielectric constant
  • the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum neodymium (AlNd), molybdenum niobium
  • the alloy (MoNb), etc. can be a multilayer metal, such as Mo/Cu/Mo, etc., or can be a stack structure formed by a metal and a transparent conductive material, such as ITO/Ag/ITO, etc.
  • Forming the pattern of the capacitor electrode layer includes: sequentially depositing a second insulating film and a second metal film on the substrate 10 forming the above structure, and patterning the second metal film through a patterning process to form a covering first connection layer 23 and a first gate.
  • the patterns of the electrode 14, the second gate electrode 15, the second insulating layer 16 of the first insulating layer 13, and the capacitor electrode 17 disposed on the second insulating layer 16 are as shown in FIG. 6.
  • the position of the capacitor electrode 17 corresponds to the position of the second gate electrode 15, and the capacitor electrode 17 and the second gate electrode 15 constitute a capacitor.
  • the second insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high dielectric constant (High-k) materials, such as aluminum oxide (AlOx), Hafnium oxide (HfOx), tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • High-k high dielectric constant
  • the second metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum neodymium (AlNd), molybdenum niobium
  • the alloy (MoNb), etc. can be a multilayer metal, such as Mo/Cu/Mo, etc., or can be a stack structure formed by a metal and a transparent conductive material, such as ITO/Ag/ITO, etc.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate 10 forming the above structure, and patterning the third insulating film through a patterning process to form the third insulating layer 18 pattern, as shown in FIG. 6.
  • the third insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or can be made of high dielectric constant (High-k) materials, such as aluminum oxide (AlOx), Hafnium oxide (HfOx), tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
  • the first insulating layer 13 and the second insulating layer 16 are also referred to as gate insulating layers, and the third insulating layer 18 is also referred to as an interlayer insulating layer.
  • the first step and the third step are formed.
  • Forming the first step and the third step includes: using a first mask (for example, an EBA mask) to etch the third insulating layer 18 through a laser or other related processes on the substrate 10 forming the above structure, and the third insulating layer 18 is etched in the first transition area.
  • a first step T1 is formed on the first connection layer 23; a second mask (for example, EBB mask) is used to etch the first insulating layer 13 and the second insulating layer 16 through a laser and other related processes to form the bending area
  • the third step T3 is shown in FIG. 7.
  • the third insulating layer 18 can be etched by controlling the etching rate of the inorganic film, leaving the second insulating layer 16 to ensure the first step T1.
  • the surface of a connecting layer 23 covers a part of the second insulating layer 16 to prevent the first connecting layer 23 from contacting the potential residual conductive material above and causing a short circuit problem.
  • all the second insulating layer 16 above the first connection layer 23 remains.
  • a part of the second insulating layer 16 above the first connection layer 23 near the bending area may be etched away to expose a part of the first connection layer 23 so as to be subsequently electrically connected to the first lead layer in the bending area. connection.
  • the first via hole, the second via hole and the fifth via hole are formed.
  • Forming the first via hole, the second via hole and the fifth via hole includes: perforating the first insulating layer 13, the second insulating layer 16, and the third insulating layer 18 on the substrate 10 formed with the above structure.
  • a first via K1 and a fifth via K5 are opened on the third insulating layer 18, and a second via K2 is opened on the second insulating layer 16, as shown in FIG.
  • the first via K1, the second via K2, and the fifth via K5 may be carbon nanotube (CNT) holes.
  • CNT carbon nanotube
  • the first via hole K1 is located at the first step T1, and the third insulating layer 18 and the second insulating layer 16 in the first via hole K1 are etched away, exposing the first connection layer 23.
  • the second insulating layer 16 in the second via hole K2 is etched away, exposing the first connection layer 23.
  • the two fifth via holes K5 are located in the display area, and the third insulating layer 18, the second insulating layer 16 and the first insulating layer 13 in the two fifth via holes K5 are etched away, exposing two parts of the active layer 12 end.
  • Patterns of the source and drain electrode layers, the signal line layer and the first lead layer are formed.
  • Forming the source and drain electrode layer, the signal line layer and the first lead layer pattern includes: depositing a third metal film on the substrate 10 formed with the above structure, patterning the third metal film through a patterning process, and forming a source electrode 19 in the display area ,
  • the drain electrode 20, the signal line layer 24 (for example, including the data line), and the first wiring layer 22 are patterned, as shown in FIG. 9.
  • the source electrode 19 is connected to the active layer 12 through the fifth via hole K5
  • the drain electrode 20 is connected to the active layer 12 through the fifth via hole K5
  • the signal line layer 24 is connected to the first connection layer 23 through the first via hole K1.
  • the first lead layer 22 is electrically connected to the first connection layer 23 through the second via K2.
  • the first connection layer 23 can electrically connect the signal line layer 24 of the display area and the first lead layer 22 of the bending area, so as to realize the normal transmission of data signals.
  • the material of the first connection layer may be molybdenum (Mo), and the overlap between the first connection layer and the signal line layer and the first lead layer is an ohmic contact, and no obvious overlap abnormality occurs. , Can realize the normal signal transmission.
  • the subsequent preparation process includes forming a planarization (PLN) layer pattern, an anode pattern, a Pixel Define Layer (PDL) pattern, an organic light-emitting layer, a cathode pattern, and an encapsulation layer, etc., which will not be repeated here.
  • PLL planarization
  • PDL Pixel Define Layer
  • the first connection layer is provided in the first transition area between the display area and the bending area, and the signal line layer and the bending area of the display area
  • the first lead layer is electrically connected to realize normal signal transmission.
  • there is no need to form a trace pattern at the first step of the first transition area which can greatly reduce the residual conductive material at the step, thereby improving the problem of the residual conductive material at the step of the inorganic film layer in the bending area, and can effectively improve the signal The etching speed of the wire preparation process.
  • retaining the second insulating layer above the first connection layer can reduce the problem of poor X-Line caused by short-circuit between the upper conductive material residue and the first connection layer.
  • the preparation process of the embodiments of the present disclosure can be realized by using mature preparation equipment, the improvement of the existing process is small, and it can be well compatible with the existing preparation process. Therefore, the process is simple to implement, easy to implement, and has high production efficiency. It has the advantages of easy process realization, low production cost and high yield rate, and has good application prospects.
  • the structure shown in this embodiment and the preparation process thereof are merely illustrative. In some embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the organic light emitting diode (OLED) display substrate may not only have a top emission structure, but also a bottom emission structure.
  • the thin film transistor can be not only a top gate structure, but also a bottom gate structure, not only a double gate structure, but also a single gate structure.
  • the thin film transistor can be an amorphous silicon (a-Si) thin film transistor, a low temperature polysilicon (LTPS) thin film transistor or an oxide (Oxide) thin film transistor, and other electrodes, leads and structures can be provided in the driving structure layer and the light emitting structure layer. ⁇ Film layer.
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • Oxide oxide
  • other electrodes, leads and structures can be provided in the driving structure layer and the light emitting structure layer.
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • Oxide oxide
  • FIG. 11 is a schematic diagram of another structure of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 11 illustrates the structure of the display area, the first transition area and the bending area on a plane perpendicular to the display substrate.
  • the first connection layer 23 of the display substrate of this embodiment is disposed on the barrier layer 11, that is, is disposed on the same layer as the active layer 12 in the display area.
  • the material of the first connection layer 23 may be amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-IGZO) At least one material such as Si), polysilicon (p-Si), hexathiophene, and polythiophene.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-IGZO amorphous silicon
  • At least one material such as Si), polysilicon (p-Si), hexathiophene, and polythiophene.
  • the material of the first connection layer 23 is polysilicon (p-Si) as an example for description.
  • the preparation process of the display substrate of this embodiment is basically the same as the preparation process of the display substrate of the previous embodiment.
  • the difference is: in step (2), when the active layer pattern is formed on the base, the first connection is also formed.
  • Layer 23 For example, the first connection layer 23 can be completed by an Excimer Laser Annealing (ELA) process, and at the same time, it can be heavily doped by P+Doping (doping) to ensure that the prepared first connection layer 23 has good conductivity. performance.
  • ELA Excimer Laser Annealing
  • P+Doping P+Doping
  • step (6) the first step T1 is formed by etching part of the second insulating layer 16 and the third insulating layer 18 above the first connection layer, that is, the first insulating layer 13 is retained on the first connection layer 23, To ensure that the surface of the first connection layer 23 is covered with an insulating layer, so as to prevent the first connection layer 23 from contacting the potential residual conductive material to cause a short circuit.
  • This embodiment also achieves the technical effects of the foregoing embodiments, including improving the problem of residual conductive material at the step of the inorganic film layer in the bending area, and improving the display effect of the display substrate.
  • FIG. 12 is a schematic diagram of another structure of the display substrate according to at least one embodiment of the present disclosure.
  • Fig. 13 is a partial cross-sectional view in the direction of Q-Q in Fig. 12.
  • the main structure of the display substrate includes: a display area A, a first transition area D1, a bending area B, a second transition area D2, and a peripheral area C.
  • the first transition area D1 is located between the display area A and the bending area B
  • the second transition area D2 is located between the peripheral area C and the bending area B.
  • a second connection layer can be provided in the second transition area between the bending area and the peripheral area, and the first lead layer and the second lead layer can be Electrical connection to achieve normal signal transmission.
  • FIG. 13 illustrates the structure of the display area, the first transition area, the bending area, the second transition area, and the peripheral area on a plane perpendicular to the display substrate.
  • a second connection layer is provided in the second transition area, which is electrically connected to the second lead layer and the first lead layer, respectively.
  • the rest of the structure of the display substrate in this embodiment can refer to the embodiment shown in FIG. 3, so it will not be repeated here.
  • the main structure of the bending area includes: a barrier layer 11 provided on the base 10 and a first lead layer 22 provided on the barrier layer 11.
  • the main structure of the first transition region includes: a barrier layer 11 arranged on the substrate 10, a first insulating layer 13 arranged on the barrier layer 11, a first connection layer 23 arranged on the first insulating layer 13, and a first connecting layer 23 arranged on the first insulating layer 13.
  • a second insulating layer 16 on the connecting layer 23 and a first step T1 disposed on the second insulating layer 16, and the first step T1 is formed by the third insulating layer 18.
  • the main structure of the second transition region includes: a barrier layer 11 arranged on the substrate 10, a first insulating layer 13 arranged on the barrier layer 11, a second connecting layer 25 arranged on the first insulating layer 13, and a second connecting layer 25 arranged on the first insulating layer.
  • the second insulating layer 16 on the second connection layer 25 and the second step T2 provided on the second insulating layer 16 are formed by the third insulating layer 18.
  • the main structure of the peripheral area includes: a barrier layer 11, a first insulating layer 13, a second insulating layer 16, a third insulating layer 18, and a second lead layer 26 arranged on the substrate 10 in sequence.
  • the signal line layer 24 in the display area is electrically connected to the first connection layer 23 through the first via hole opened in the first step T1.
  • the second lead layer 26 in the peripheral area is electrically connected to the second connection layer 25 through a third via hole opened in the second step T2.
  • the first lead layer 22 in the bending area is electrically connected to the first connection layer 23 through a second via hole that penetrates the second insulating layer 16, and is electrically connected to the second connection layer 25 through a fourth via hole that penetrates the second insulating layer 16 .
  • the preparation process of the display substrate of this embodiment is basically the same as the preparation process of the display substrate of the embodiment shown in FIG. 3, except that: in step (3), a first connection layer, a second connection layer and a gate electrode are formed Layer pattern. In other words, in this embodiment, both the first connection layer 23 and the second connection layer 25 are arranged in the same layer as the gate electrode layer of the display area, and are made of the same material.
  • step (6) the first step T1 is formed by etching part of the third insulating layer 18 above the first connection layer 23, and the second step T1 is formed by etching part of the third insulating layer 18 above the second connection layer 25.
  • Step T2 and etch away the first insulating layer 13, the second insulating layer 16, and the third insulating layer 18 in the bending area.
  • a first via hole is opened at the first step T1 to expose the first connection layer 23, and a second via hole is opened on the second insulating layer 16 to expose the first connection layer 23; on the second step T2
  • a third via hole is opened at the position to expose the second connection layer 25, and a fourth via hole is opened in the second insulating layer 16 to expose the second connection layer 25.
  • step (8) the source and drain electrode layers, the signal line layer 24, the first lead layer 22, and the second lead layer 26 are prepared at the same time.
  • the signal line layer 24 is electrically connected to the first connection layer 23 through the first via hole
  • the first lead layer 22 is electrically connected to the first connection layer 23 through the second via hole
  • the first lead layer 22 is electrically connected to the first connection layer 23 through the fourth via hole.
  • the second connection layer 25 is electrically connected
  • the second lead layer 26 is electrically connected to the second connection layer 25 through a third via hole.
  • both the first connection layer and the second connection layer may be provided in the same layer as the active layer of the display area; or, the first connection layer may be provided in the same layer as the active layer of the display area, and the second connection layer It may be provided in the same layer as the gate electrode layer in the display area; alternatively, the first connection layer may be provided in the same layer as the gate electrode layer in the display area, and the second connection layer may be provided in the same layer as the active layer in the display area.
  • the first connection layer and the second connection layer may use the same material or different materials. However, the embodiment of the present disclosure does not limit this.
  • the signal line layer of the display area and the first lead layer of the bending area are electrically connected through the first connection layer, and the first lead layer of the bending area and the first lead layer of the peripheral area are connected through the second connection layer.
  • the two lead layers are electrically connected, which can avoid setting traces on the first step and the second step, thereby improving the problem of residual conductive material at the step during the etching process, so as to achieve normal signal transmission, improve product yield, and ensure display effect.
  • the embodiment of the present disclosure also provides a method for preparing a display substrate to prepare the display substrate of the foregoing embodiment.
  • the display substrate includes a display area, a bending area, and a first transition area between the display area and the bending area.
  • the method for preparing the display substrate provided by this embodiment includes: forming a first connection layer in a first transition area, and forming a first step on the first connection layer, wherein the first step is formed by at least one inorganic insulating layer; A signal line layer is formed, and a first lead layer is formed in the bending area.
  • the signal line layer is electrically connected to the first connection layer through the first via hole opened in the first step, and the first lead layer is electrically connected to the first connection layer.
  • the preparation method of this embodiment may further include: before forming the first lead layer in the bending region, forming an inorganic insulating layer on the first connection layer, the inorganic insulating layer having a second via hole to The first lead layer formed subsequently is electrically connected to the first connection layer through the second via hole.
  • the material of the first connection layer may be a metal or a material with semiconductor properties.
  • forming the first connection layer in the first transition area may include: forming the first connection layer in the first transition area while forming the driving structure layer in the display area, wherein the driving structure layer is included in The active layer, the first insulating layer, the gate electrode layer, the second insulating layer, the capacitor electrode layer, the third insulating layer and the source and drain electrode layers are arranged in sequence on the substrate; wherein the first connection layer and the active layer are arranged in the same layer Or, the first connection layer and the gate electrode layer are provided in the same layer.
  • the display substrate may further include: a peripheral area and a second transition area located between the bending area and the peripheral area.
  • the preparation method of this embodiment may further include: forming a second connection layer in the second transition area, and forming a second step on the second connection layer, wherein the second step is formed by at least one inorganic insulating layer; and forming a signal in the display area.
  • the wire layer is formed in the bending area while the first wiring layer is formed, and the second wiring layer is formed in the peripheral area.
  • the second lead layer is electrically connected to the second connection layer through a third via hole opened in the second step, and the first lead layer is electrically connected to the second connection layer.
  • the preparation method of this embodiment may further include: before forming the first lead layer in the bending region, forming an inorganic insulating layer on the second connection layer, the inorganic insulating layer having a fourth via to The first lead layer formed subsequently is electrically connected to the second connection layer through the fourth via hole.
  • the second connection layer and the first connection layer are arranged in the same layer and use the same material.
  • FIG. 14 is a schematic diagram of a display device according to at least one embodiment of the disclosure. As shown in FIG. 14, this embodiment provides a display device 91 including a display substrate 910.
  • the display substrate 910 is the display substrate provided in the foregoing embodiment.
  • the display device 91 may be any product or component with a display function, such as an OLED display panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the present disclosure is not limited to this.
  • the orientation or positional relationship indicated by “outside” is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, It is constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be interpreted broadly, for example, it may be a fixed connection, or may be a detachable connection, or Integrally connected; may be a mechanical connection, or may be an electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, or may be internal communication between two components.
  • installed may be a fixed connection, or may be a detachable connection, or Integrally connected

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Abstract

一种显示基板，包括：显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域。显示区域设置有信号线层，弯折区域设置有第一引线层，第一过渡区域设置有第一连接层，第一连接层上设置有由至少一个无机绝缘层形成的第一台阶。信号线层通过开设在第一台阶的第一过孔与第一连接层电连接，第一引线层与第一连接层电连接。

Description

显示基板及其制备方法、显示装置
本申请要求于2019年11月19日提交中国专利局、申请号为201911133333.0、发明名称为“一种显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
目前，用户和市场对智能手机等显示产品的占屏比要求越来越高，全屏无边框或窄边框的显示产品已经成为主流发展方向。为了缩减屏幕边框宽度，通常会将部分边框弯折到屏幕的背面，如将用于设置驱动芯片和绑定电路的边框区域弯折到屏幕的背面，用于设置驱动芯片和绑定电路的边框区域与不进行弯折的其他边框区域之间可以设置弯折区域(即，Pad Bending区域)。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供了一种显示基板，包括：显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域。所述显示区域设置有信号线层，所述弯折区域设置有第一引线层，所述第一过渡区域设置有第一连接层，且所述第一连接层上设置有由至少一个无机绝缘层形成的第一台阶。所述信号线层通过开设在所述第一台阶的第一过孔与所述第一连接层电连接，所述第一引线层与所述第一连接层电连接。
另一方面，本公开实施例提供了一种显示装置，包括如上所述的显示基 板。
另一方面，本公开实施例提供了一种显示基板的制备方法。所述显示基板包括显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域。所述制备方法包括：在第一过渡区域形成第一连接层，在第一连接层上形成第一台阶，所述第一台阶由至少一个无机绝缘层形成；在显示区域形成信号线层，在弯折区域形成第一引线层。其中，所述信号线层通过开设在所述第一台阶的第一过孔与所述第一连接层电连接，所述第一引线层与所述第一连接层电连接。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示基板的结构示意图；
图2为图1中R-R方向的局部剖视图；
图3为本公开至少一实施例的显示基板的一种结构示意图；
图4为图3中的I-I方向的局部剖视图；
图5为本公开至少一实施例形成阻挡层后的显示基板的示意图；
图6为本公开至少一实施例形成第三绝缘层图案后的显示基板的示意图；
图7为本公开至少一实施例形成第一台阶和第三台阶后的显示基板的示意图；
图8为本公开至少一实施例形成第一过孔、第二过孔和第五过孔后的显示基板的示意图；
图9为本公开至少一实施例形成信号引线层、第一引线层和源漏电极层图案后的显示基板的示意图；
图10为本公开至少一实施例的显示区域、第一过渡区域和弯折区域的局部俯视示意图；
图11为本公开至少一实施例的显示基板的另一结构示意图；
图12为本公开至少一实施例的显示基板的又一结构示意图；
图13为图12中Q-Q方向的局部剖视图；
图14为本公开至少一实施例的显示装置的示意图。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由权利要求限定的独特的发明方案。因此，应当理解，在本公开中示出或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行至少一种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法或过程 的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
在传统方式中，通过对弯折区域进行无机膜挖槽，以减少弯折区域的无机膜层的厚度，从而实现180度弯折。然而，对弯折区域进行无机膜挖槽，会在无机膜层形成台阶，造成台阶处的信号走线出现较大落差，导致在信号走线的干法刻蚀(Dry Etch)工艺中出现导电材料残留(Remain)而引起短路，进而造成显示面板产生暗线或亮线(X-Line)不良，影响产品良率。
图1为一种显示基板的结构示意图。图2为图1中R-R方向的局部剖视图。如图1所示，显示基板包括：显示区域A、弯折区域B和外围区域C。其中，显示区域A内设置有子像素阵列和信号线，外围区域C可以设置驱动芯片，驱动芯片可以给显示区域A提供驱动信号。弯折区域B位于显示区域A和外围区域C之间，弯折区域B内设置信号引线，配置为电连接外围区域C内的驱动芯片和显示区域A内的信号线。外围区域C可以通过弯折区域B进行折叠，比如，折叠至显示区域A的背面。
如图2所示，在显示区域内的子像素阵列包括：薄膜晶体管和存储电容。其中，薄膜晶体管包括依次设置在基底10上的阻隔层11、有源层12、第一绝缘层13、第一栅电极14、第二绝缘层16、第三绝缘层18和源漏电极层(包括源电极19和漏电极20)。存储电容包括依次设置在基底10上的第二栅电极15、电容绝缘层(即第二绝缘层16)和电容电极17。其中，在形成第三绝缘层18之后，可以通过两道掩模(mask)工艺(比如，EBA(Edge Bending A)mask和EBB(Edge Bending B)mask)依次去除弯折区域的第三绝缘层18、第二绝缘层16和第一绝缘层13，从而减少弯折区域的无机膜层厚度，以实现弯折。其中，弯折区域的信号引线21与显示区域的源漏电极层同层设置，且采用相同的工艺制备。
由图2可见，在弯折区域通过对无机膜层挖槽，会形成台阶，造成信号引线21的走线出现较大落差，如此一来，在制备信号引线的干法刻蚀工艺中容易出现导电材料残留(Remain)问题，进而导致出现短路的情况，造成X-Line不良，影响产品良率，而且大量的导电材料残留也存在极大的信赖性 风险。
本公开实施例提供一种显示基板及其制备方法、显示装置，可以改善弯折区域的无机膜层台阶处的导电材料残留问题。
本公开实施例提供一种显示基板，包括：显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域。显示区域设置有信号线层，弯折区域设置有第一引线层，第一过渡区域设置有第一连接层，且第一连接层上设置有由至少一个无机绝缘层形成的第一台阶。信号线层通过开设在第一台阶的第一过孔与第一连接层电连接，第一引线层与第一连接层电连接。其中，形成第一台阶的无机绝缘层可以包括：层间绝缘(ILD，Inner Layer Dielectric)层，或者，包括层间绝缘层和栅绝缘(GI，Gate Insulator)层。
在一些示例性实施方式中，第一引线层和第一连接层之间设置有一个无机绝缘层，第一引线层通过贯穿所述无机绝缘层的第二过孔与第一连接层电连接。其中，第一引线层和第一连接层之间设置的无机绝缘层可以为一个栅绝缘层。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一连接层的材料可以为金属(比如，钼Mo)或具有半导体性能的材料(比如，多晶硅)。
在一些示例性实施方式中，显示基板还可以包括：第二过渡区域和外围区域，第二过渡区域位于弯折区域和外围区域之间。外围区域设置有第二引线层，第二过渡区域设置有第二连接层，且第二连接层上设置有由至少一个无机绝缘层形成的第二台阶。第二引线层通过开设在第二台阶的第三过孔与第二连接层电连接，第一引线层与第二连接层电连接。其中，形成第二台阶的无机绝缘层可以包括：层间绝缘层，或者，包括层间绝缘层和栅绝缘层。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一引线层和第二连接层之间设置有一个无机绝缘层，第一引线层通过贯穿所述无机绝缘层的第四过孔与第二连接层电连接。其中，第一引线层和第二连接层之间设置的无机绝缘层可以为一个栅绝缘层。然而，本实施例对此并不限定。
在一些示例性实施方式中，第二连接层与第一连接层同层设置且采用相 同材料。
本公开实施例通过设置第一连接层，实现显示区域的信号线层和弯折区域的第一引线层之间的电连接，避免在第一台阶上设置走线，从而改善刻蚀工艺中在台阶处的导电材料残留问题，实现信号正常传输，提高产品良率，并保证显示效果。
下面通过一些示例详细说明本公开实施例的技术方案。
图3为本公开至少一实施例的显示基板的一种结构示意图。图4为图3中I-I方向的局部剖视图。如图3所示，在平行于显示基板的平面上，显示基板的主体结构包括：显示区域A、第一过渡区域D1、弯折区域B和外围区域C。其中，第一过渡区域D1位于显示区域A和弯折区域B之间，外围区域C位于弯折区域B远离第一过渡区域D1的一侧。其中，外围区域C可以设置驱动芯片，驱动芯片可以给显示区域A提供驱动信号。然而，本公开对此并不限定。在其他实现方式中，弯折区域还可以位于显示区域的上下相对两侧，或者，位于显示区域的四侧。
图4示意了在垂直于显示基板的平面上，显示区域、第一过渡区域和弯折区域的结构。如图4所示，在垂直于显示基板的平面上，显示区域的主体结构包括呈阵列分布的多个发光单元和信号线。多个发光单元中的至少一个发光单元包括设置在基底上的驱动结构层和发光结构层，驱动结构层包括多个薄膜晶体管(Thin Film Transistor，TFT)。信号线可以包括数据线和栅线(图未示)。图4中仅以一个发光单元包括的一个薄膜晶体管为例进行示意。其中，驱动结构层主要包括设置在基底10上的阻隔层11、设置在阻隔层11上的薄膜晶体管和存储电容。其中，薄膜晶体管包括依次设置在阻隔层11上的有源层12、第一绝缘层13、第一栅电极14、第二绝缘层16、第三绝缘层18和源漏电极层(例如包括源电极19和漏电极20)。存储电容包括依次设置在基底10上的第二栅电极15、电容绝缘层(即第二绝缘层16)和电容电极17。
如图4所示，在垂直于显示基板的平面上，弯折区域的主体结构包括：设置在基底10上的阻隔层11、设置在阻隔层11上的第一引线层22。第一过渡区域的主体结构包括：设置在基底10上的阻隔层11、设置在阻隔层11上 的第一绝缘层13、设置在第一绝缘层13上的第一连接层23、设置在第一连接层13上的第二绝缘层16以及设置在第二绝缘层16上的第一台阶T1。第一台阶T1由第三绝缘层18形成。
如图4所示，显示区域的信号线层24通过开设在第一台阶T1的第一过孔与第一连接层23电连接。弯折区域的第一引线层22通过贯穿第二绝缘层16的第二过孔与第一连接层23电连接。通过第一连接层23可以实现显示区域的信号线层24与弯折区域的第一引线层22之间的电连接，避免在第一台阶T1上形成走线，可以改善刻蚀工艺中在第一台阶T1处的导电材料残留问题。而且，第一连接层23上保留第二绝缘层16，可以减少上方的导电材料与第一连接层23引起的短路。
下面通过本实施例的显示基板的制备过程进一步说明本实施例的技术方案。其中，本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是已知成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。
图5至图9为本公开至少一实施例的显示基板的制备过程的示意图。在一些示例性实施方式中，显示基板的制备过程包括以下步骤。
(1)在基底上形成阻挡(barrier)层。在基底上形成阻挡层包括：在基底10上沉积一层阻挡薄膜，形成阻挡层11，如图5所示。
其中，基底10可以为柔性基底，采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料。阻挡薄膜可以采用氮化硅(SiNx)或氧化硅(SiOx)等，可以是单层，也可以是氮化硅/氧化硅的多层结构。本实施例中，阻挡层11可以用于提高基底10的抗水氧能力。
(2)在基底上形成有源层图案。在基底上形成有源层图案包括：在形成上述结构的基底10上，沉积一层有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成设置在阻挡层11上的有源层12图案，如图6所示。其中，有源层12图案仅形成在显示区域，此时的弯折区域和第一过渡区域仅形成有阻挡层11。
其中，有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等至少一种材料，即本实施例同时适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的基于顶栅(Top Gate)薄膜晶体管(TFT)的显示基板。
(3)形成栅电极层和第一连接层图案。形成栅电极层和第一连接层图案包括：在形成上述结构的基底10上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层12和阻挡层11的第一绝缘层13、设置在第一绝缘层13上的第一连接层23、第一栅电极14、第二栅电极15和栅线(未示出)图案，如图6所示。其中，第一连接层23形成在第一过渡区域；第一栅电极14、第二栅电极15和栅线(图未示)形成在显示区域。
其中，第一绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或可以采用高介电常数(High k)材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。
其中，第一金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钼(Mo)等，或上述金属的合金材料，如铝钕合金(AlNd)、钼铌合金(MoNb)等，可以是多层金属，如Mo/Cu/Mo等，或可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
(4)形成电容电极层图案。形成电容电极层图案包括：在形成上述结构的基底10上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一连接层23、第一栅电极14、第二栅电极15和第一绝缘层13的第二绝缘层16以及设置在第二绝缘层16上的电容电极17图案，如图6所示。其中，电容电极17的位置与第二栅电极15的位置相对应，电容电极17与第二栅电极15构成电容。
其中，第二绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或可以采用高介电常数(High k)材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。
其中，第二金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、 钼(Mo)等，或上述金属的合金材料，如铝钕合金(AlNd)、钼铌合金(MoNb)等，可以是多层金属，如Mo/Cu/Mo等，或可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
(5)形成第三绝缘层图案。形成第三绝缘层图案包括：在形成上述结构的基底10上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层18图案，如图6所示。
其中，第三绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，或可以采用高介电常数(High k)材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。
通常，第一绝缘层13和第二绝缘层16也称之为栅绝缘层，第三绝缘层18也称之为层间绝缘层。
(6)形成第一台阶和第三台阶。形成第一台阶和第三台阶包括：在形成上述结构的基底10上，采用第一掩模(比如，EBA mask)通过激光等相关工艺对第三绝缘层18进行刻蚀，在第一过渡区域的第一连接层23上形成第一台阶T1；采用第二掩模(比如，EBB mask)通过激光等相关工艺对第一绝缘层13和第二绝缘层16进行刻蚀，在弯折区域形成第三台阶T3，如图7所示。
在本实施例中，在无机膜层刻蚀形成第一台阶T1的过程中，可以通过控制无机膜层刻蚀速率对第三绝缘层18进行刻蚀，保留第二绝缘层16，以保证第一连接层23表面覆盖部分的第二绝缘层16，防止第一连接层23与上方潜在的残留导电材料接触造成短路问题。
在本实施例中，第一连接层23上方的第二绝缘层16全部保留。然而，本公开对此并不限定。在其他实现方式中，可以将第一连接层23上方靠近弯折区域的部分第二绝缘层16刻蚀掉，以露出部分第一连接层23，以便后续与弯折区域的第一引线层电连接。
(7)形成第一过孔、第二过孔和第五过孔。形成第一过孔、第二过孔和第五过孔包括：在形成上述结构的基底10上，对第一绝缘层13、第二绝缘层16和第三绝缘层18进行打孔。在第三绝缘层18上开设有第一过孔K1和 第五过孔K5，在第二绝缘层16上开设有第二过孔K2，如图8所示。其中，第一过孔K1、第二过孔K2和第五过孔K5可以为碳纳米管(CNT)孔。然而，本公开对此并不限定。
其中，第一过孔K1位于第一台阶T1处，第一过孔K1中的第三绝缘层18和第二绝缘层16被刻蚀掉，暴露出第一连接层23。第二过孔K2中的第二绝缘层16被刻蚀掉，暴露出第一连接层23。两个第五过孔K5位于显示区域，两个第五过孔K5中的第三绝缘层18、第二绝缘层16和第一绝缘层13被刻蚀掉，暴露出有源层12的两端。
(8)形成源漏电极层、信号线层和第一引线层图案。形成源漏电极层、信号线层和第一引线层图案包括：在形成上述结构的基底10上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在显示区域形成源电极19、漏电极20和信号线层24(例如，包括数据线)、第一引线层22图案，如图9所示。其中，源电极19通过第五过孔K5与有源层12连接，漏电极20通过第五过孔K5与有源层12连接，信号线层24通过第一过孔K1与第一连接层23电连接，第一引线层22通过第二过孔K2与第一连接层23电连接。
如图10所示，第一连接层23可以电连接显示区域的信号线层24和弯折区域的第一引线层22，从而实现数据信号的正常传输。在本实施例中，第一连接层的材料可以为钼(Mo)，在第一连接层和信号线层与第一引线层之间的搭接为欧姆接触，不会出现明显的搭接异常，可以实现信号正常传输。
通过上述过程，在基底10上完成了位于显示区域的驱动结构层、第一过渡区域和弯折区域的引线连接结构的制备。
后续制备过程包括形成平坦化(PLN)层图案、阳极图案、像素定义层(Pixel Define Layer，PDL)图案、有机发光层、阴极图案和封装层等结构，于此不再赘述。
通过上述制备流程可以看出，本实施例所提供的显示基板，通过在显示区域和弯折区域之间的第一过渡区域设置第一连接层，对显示区域的信号线层和弯折区域的第一引线层进行电连接，可以实现信号正常传输。而且，在第一过渡区域的第一台阶处无需形成走线图案，可以大幅降低台阶处的导电材料残留，从而改善弯折区域的无机膜层台阶处的导电材料残留问题，而且 可以有效提高信号走线制备过程的刻蚀速度。另外，在第一连接层上方保留第二绝缘层，可以减少上部导电材料残留与第一连接层短路造成X-Line不良的问题。
此外，由于本公开实施例的制备工艺利用成熟的制备设备即可实现，对现有工艺改进较小，能够很好地与现有制备工艺兼容，因此工艺实现简单，易于实施，生产效率高，具有易于工艺实现、生产成本低和良品率高等优点，具有良好的应用前景。
本实施例所示结构及其制备过程仅仅是一种示例性说明。在一些实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，有机发光二极管(OLED)显示基板不仅可以为顶发射结构，也可以是底发射结构。又如，薄膜晶体管不仅可以是顶栅结构，也可以是底栅结构，不仅可以是双栅结构，也可以是单栅结构。再如，薄膜晶体管可以是非晶硅(a-Si)薄膜晶体管、低温多晶硅(LTPS)薄膜晶体管或氧化物(Oxide)薄膜晶体管，驱动结构层和发光结构层中还可以设置其它电极、引线和结构膜层。然而，本公开实施例在此不做限定。
图11为本公开至少一实施例的显示基板的另一结构示意图。图11示意了在垂直于显示基板的平面上，显示区域、第一过渡区和弯折区域的结构。本实施例的显示基板的第一连接层23设置在阻隔层11上，即与显示区域的有源层12同层设置。本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在本实施例中，第一连接层23的材料可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等至少一种材料。
下面以第一连接层23的材料为多晶硅(p-Si)为例进行说明。本实施例的显示基板的制备过程与前述实施例的显示基板的制备过程基本上相同，所不同的是：在步骤(2)，在基底上形成有源层图案的同时，还形成第一连接层23。比如，第一连接层23可以通过准分子激光退火(ELA，Excimer Laser Annealing)工艺完成，同时通过P+Doping(掺杂)进行重掺杂，以确保制备的第一连接层23具有良好的导电性能。在步骤(3)中仅形成栅电极层图 案。在步骤(6)中，通过刻蚀第一连接层上方的部分第二绝缘层16和第三绝缘层18，形成第一台阶T1，即在第一连接层23上保留第一绝缘层13，以确保第一连接层23表面覆盖有绝缘层，从而防止第一连接层23与潜在的残留导电材料接触造成短路。
本实施例同样实现了前述实施例的技术效果，包括改善弯折区域的无机膜层台阶处的导电材料残留问题，提高显示基板的显示效果。
图12为本公开至少一实施例的显示基板的又一结构示意图。图13为图12中Q-Q方向的局部剖视图。如图12所示，在平行于显示基板的平面上，显示基板的主体结构包括：显示区域A、第一过渡区域D1、弯折区域B、第二过渡区域D2和外围区域C。其中，第一过渡区域D1位于显示区域A和弯折区域B之间，第二过渡区域D2位于外围区域C和弯折区域B之间。
在本实施例中，为了实现外围区域翻折到显示区域的背面，可以在弯折区域和外围区域之间的第二过渡区域设置第二连接层，对第一引线层和第二引线层进行电连接，以实现信号正常传输。
图13示意了在垂直于显示基板的平面上，显示区域、第一过渡区域、弯折区域、第二过渡区域和外围区域的结构。在垂直于显示基板的平面上，在第二过渡区域设置有第二连接层，分别电连接第二引线层和第一引线层。本实施例显示基板的其余结构可以参照前述图3所示的实施例，故于此不再赘述。
如图13所示，在垂直于显示基板的平面上，弯折区域的主体结构包括：设置在基底10上的阻隔层11、设置在阻隔层11上的第一引线层22。第一过渡区域的主体结构包括：设置在基底10上的阻隔层11、设置在阻隔层11上的第一绝缘层13、设置在第一绝缘层13上的第一连接层23、设置在第一连接层23上的第二绝缘层16以及设置在第二绝缘层16上的第一台阶T1，第一台阶T1由第三绝缘层18形成。第二过渡区域的主体结构包括：设置在基底10上的阻隔层11、设置在阻隔层11上的第一绝缘层13、设置在第一绝缘层13上的第二连接层25、设置在第二连接层25上的第二绝缘层16以及设置在第二绝缘层16上的第二台阶T2，第二台阶T2由第三绝缘层18形成。外围区域的主体结构包括：依次设置在基底10上的阻隔层11、第一绝缘层 13、第二绝缘层16、第三绝缘层18和第二引线层26。
如图13所示，显示区域的信号线层24通过开设在第一台阶T1的第一过孔与第一连接层23电连接。外围区域的第二引线层26通过开设在第二台阶T2的第三过孔与第二连接层25电连接。弯折区域的第一引线层22通过贯穿第二绝缘层16的第二过孔与第一连接层23电连接，通过贯穿第二绝缘层16的第四过孔与第二连接层25电连接。
本实施例的显示基板的制备过程与图3所示实施例的显示基板的制备过程基本相同，所不同的是：在步骤(3)中，形成第一连接层、第二连接层以及栅电极层图案。换言之，在本实施例中，第一连接层23和第二连接层25均与显示区域的栅电极层同层设置，且采用相同材料。在步骤(6)中，通过刻蚀第一连接层23上方的部分第三绝缘层18，形成第一台阶T1，通过刻蚀第二连接层25上方的部分第三绝缘层18，形成第二台阶T2，并且将弯折区域的第一绝缘层13、第二绝缘层16和第三绝缘层18刻蚀掉。在步骤(7)中，在第一台阶T1处开设第一过孔，露出第一连接层23，在第二绝缘层16开设第二过孔，露出第一连接层23；在第二台阶T2处开设第三过孔，露出第二连接层25，在第二绝缘层16开设第四过孔，露出第二连接层25。在步骤(8)中，同时制备源漏电极层、信号线层24、第一引线层22和第二引线层26。其中，信号线层24通过第一过孔与第一连接层23电连接，第一引线层22通过第二过孔与第一连接层23电连接，第一引线层22通过第四过孔与第二连接层25电连接，第二引线层26通过第三过孔与第二连接层25电连接。
在其他实现方式中，第一连接层和第二连接层可以均与显示区域的有源层同层设置；或者，第一连接层可以与显示区域的有源层同层设置，第二连接层可以与显示区域的栅电极层同层设置；或者，第一连接层可以与显示区域的栅电极层同层设置，第二连接层可以与显示区域的有源层同层设置。第一连接层和第二连接层可以采用相同的材料或不同的材料。然而，本公开实施例对此并不限定。
在本实施例中，通过第一连接层对显示区域的信号线层和弯折区域的第一引线层进行电连接，通过第二连接层对弯折区域的第一引线层和外围区域的第二引线层进行电连接，可以避免在第一台阶和第二台阶上设置走线，从 而改善刻蚀工艺中在台阶处的导电材料残留问题，以实现信号正常传输，提高产品良率，并保证显示效果。
本公开实施例还提供了一种显示基板的制备方法，以制备出前述实施例的显示基板。显示基板包括显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域。本实施例提供的显示基板的制备方法包括：在第一过渡区域形成第一连接层，在第一连接层上形成第一台阶，其中，第一台阶由至少一个无机绝缘层形成；在显示区域形成信号线层，在弯折区域形成第一引线层。其中，信号线层通过开设在第一台阶的第一过孔与第一连接层电连接，第一引线层与第一连接层电连接。
在一示例性实施方式中，本实施例的制备方法还可以包括：在弯折区域形成第一引线层之前，在第一连接层上形成无机绝缘层，无机绝缘层具有第二过孔，以使后续形成的第一引线层通过第二过孔与第一连接层电连接。
在一示例性实施方式中，第一连接层的材料可以为金属或具有半导体性能的材料。
在一示例性实施方式中，在第一过渡区域形成第一连接层，可以包括：在显示区域形成驱动结构层的同时，在第一过渡区域形成第一连接层，其中，驱动结构层包括在基底上依次设置的有源层、第一绝缘层、栅电极层、第二绝缘层、电容电极层、第三绝缘层和源漏电极层；其中，第一连接层与有源层同层设置，或者，第一连接层与栅电极层同层设置。
在一示例性实施方式中，显示基板还可以包括：外围区域和位于弯折区域和外围区域之间的第二过渡区域。本实施例的制备方法还可以包括：在第二过渡区域形成第二连接层，在第二连接层上形成第二台阶，其中，第二台阶由至少一个无机绝缘层形成；在显示区域形成信号线层且在弯折区域形成第一引线层的同时，在外围区域形成第二引线层。其中，第二引线层通过开设在第二台阶的第三过孔与第二连接层电连接，第一引线层与第二连接层电连接。
在一示例性实施方式中，本实施例的制备方法还可以包括：在弯折区域形成第一引线层之前，在第二连接层上形成无机绝缘层，无机绝缘层具有第四过孔，以使后续形成的第一引线层通过第四过孔与第二连接层电连接。
在一示例性实施方式中，第二连接层与第一连接层同层设置且采用相同材料。
有关显示基板的制备过程，已在之前的实施例中详细说明，这里不再赘述。
本公开实施例还提供了一种显示装置，包括前述实施例的显示基板。图14为本公开至少一实施例的显示装置的示意图。如图14所示，本实施例提供一种显示装置91，包括：显示基板910。显示基板910为前述实施例提供的显示基板。在一些示例中，显示装置91可以为：OLED显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本公开对此并不限定。
在本公开实施例的描述中，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开实施例的描述中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，或可以是可拆卸连接，或一体地连接；可以是机械连接，或可以是电连接；可以是直接相连，或可以通过中间媒介间接相连，或可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种显示基板，包括：显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域；
    所述显示区域设置有信号线层，所述弯折区域设置有第一引线层，所述第一过渡区域设置有第一连接层，所述第一连接层上设置有由至少一个无机绝缘层形成的第一台阶；
    所述信号线层通过开设在所述第一台阶的第一过孔与所述第一连接层电连接，所述第一引线层与所述第一连接层电连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一引线层和第一连接层之间设置有一个无机绝缘层，所述第一引线层通过贯穿所述无机绝缘层的第二过孔与所述第一连接层电连接。
  3. 根据权利要求1所述的显示基板，其中，所述第一连接层的材料为金属或具有半导体性能的材料。
  4. 根据权利要求1所述的显示基板，其中，所述显示区域内还设置有驱动结构层；所述驱动结构层包括：在基底上依次设置的有源层、第一绝缘层、栅电极层、第二绝缘层、电容电极层、第三绝缘层和源漏电极层；所述信号线层、所述第一引线层与所述源漏电极层同层设置；
    其中，所述第一连接层与所述栅电极层同层设置，或者，所述第一连接层与所述有源层同层设置。
  5. 根据权利要求1至4中任一项所述的显示基板，还包括：第二过渡区域和外围区域，所述第二过渡区域位于弯折区域和外围区域之间；
    其中，所述外围区域设置有第二引线层，所述第二过渡区域设置有第二连接层，且所述第二连接层上设置有由至少一个无机绝缘层形成的第二台阶；
    所述第二引线层通过开设在第二台阶的第三过孔与所述第二连接层电连接，所述第一引线层与所述第二连接层电连接。
  6. 根据权利要求5所述的显示基板，其中，所述第一引线层和第二连接层之间设置有一个无机绝缘层，所述第一引线层通过贯穿所述无机绝缘层的 第四过孔与所述第二连接层电连接。
  7. 根据权利要求5所述的显示基板，其中，所述第二连接层与所述第一连接层同层设置且采用相同材料。
  8. 一种显示装置，包括如权利要求1至7中任一项所述的显示基板。
  9. 一种显示基板的制备方法，所述显示基板包括显示区域、弯折区域以及位于显示区域和弯折区域之间的第一过渡区域；
    所述制备方法包括：
    在第一过渡区域形成第一连接层，在第一连接层上形成第一台阶，所述第一台阶由至少一个无机绝缘层形成；
    在显示区域形成信号线层，在弯折区域形成第一引线层，其中，所述信号线层通过开设在所述第一台阶的第一过孔与所述第一连接层电连接，所述第一引线层与所述第一连接层电连接。
  10. 根据权利要求9所述的制备方法，还包括：在所述弯折区域形成第一引线层之前，在第一连接层上形成无机绝缘层，所述无机绝缘层具有第二过孔，以使所述第一引线层通过所述第二过孔与第一连接层电连接。
  11. 根据权利要求9所述的制备方法，其中，所述第一连接层的材料为金属或具有半导体性能的材料。
  12. 根据权利要求9所述的制备方法，其中，所述在第一过渡区域形成第一连接层，包括：
    在显示区域形成驱动结构层的同时，在第一过渡区域形成第一连接层，其中，驱动结构层包括在基底上依次设置的有源层、第一绝缘层、栅电极层、第二绝缘层、电容电极层、第三绝缘层和源漏电极层；
    其中，所述第一连接层与所述有源层同层设置，或者，所述第一连接层与所述栅电极层同层设置。
  13. 根据权利要求9至12中任一项所述的制备方法，其中，所述显示基板还包括：外围区域、位于弯折区域和外围区域之间的第二过渡区域；
    所述制备方法还包括：
    在第二过渡区域形成第二连接层，在第二连接层上形成第二台阶，所述第二台阶由至少一个无机绝缘层形成；
    在显示区域形成信号线层且在弯折区域形成第一引线层的同时，在外围区域形成第二引线层，其中，所述第二引线层通过开设在所述第二台阶的第三过孔与所述第二连接层电连接，所述第一引线层与第二连接层电连接。
  14. 根据权利要求13所述的制备方法，还包括：在所述外围区域形成第一引线层之前，在第二连接层上形成无机绝缘层，所述无机绝缘层具有第四过孔，以使所述第一引线层通过所述第四过孔与第二连接层电连接。
  15. 根据权利要求13所述的制备方法，其中，所述第二连接层与所述第一连接层同层设置且采用相同材料。
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