WO2021114660A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

Info

Publication number
WO2021114660A1
WO2021114660A1 PCT/CN2020/102161 CN2020102161W WO2021114660A1 WO 2021114660 A1 WO2021114660 A1 WO 2021114660A1 CN 2020102161 W CN2020102161 W CN 2020102161W WO 2021114660 A1 WO2021114660 A1 WO 2021114660A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
layer
plate
pattern
Prior art date
Application number
PCT/CN2020/102161
Other languages
English (en)
French (fr)
Inventor
许晨
郝学光
乔勇
吴新银
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/265,815 priority Critical patent/US11963420B2/en
Priority to EP20864329.6A priority patent/EP4075511A4/en
Priority to JP2021538033A priority patent/JP2023504757A/ja
Publication of WO2021114660A1 publication Critical patent/WO2021114660A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • PM passive matrix
  • AM active matrix
  • TFT Thin Film Transistor
  • the gate electrode voltage of the driving transistor is maintained by the storage capacitor. Due to the leakage current of the transistor, the voltage stored in the storage capacitor will gradually decrease, causing the potential of the gate electrode of the transistor to change, thereby affecting the current flowing through the organic electroluminescent diode and affecting the light-emitting brightness of the sub-pixel. For this reason, the capacity of the storage capacitor is usually designed to be large enough to increase the duration of the voltage.
  • the present disclosure provides a display substrate including a substrate and a plurality of sub-pixels corresponding to different colors provided on the substrate, each of the sub-pixels including a pixel driving circuit and a device electrically connected to the pixel driving circuit.
  • Electromechanical light-emitting diodes including a substrate and a plurality of sub-pixels corresponding to different colors provided on the substrate, each of the sub-pixels including a pixel driving circuit and a device electrically connected to the pixel driving circuit.
  • the pixel driving circuit includes a first transistor, a second transistor, and a storage capacitor.
  • a gate electrode of the first transistor is coupled to a first scan line, and a first electrode of the first transistor is coupled to a data line.
  • the second electrode of the first transistor is coupled to the gate electrode of the second transistor; the first electrode of the second transistor is coupled to the first power supply voltage line, and the second electrode of the second transistor is coupled to the The first pole of the organic electroluminescence diode, the second pole of the organic electroluminescence diode is coupled to a second power supply voltage line;
  • the first pole of the storage capacitor is coupled to the gate electrode of the second transistor ,
  • the second electrode of the storage capacitor is coupled to the second electrode of the second transistor, and the storage capacitor is used to store the potential of the gate electrode of the second transistor;
  • the display substrate In a direction perpendicular to the base, the display substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, and a second metal layer that are stacked;
  • the metal oxide layer includes a first pattern, a second pattern, and a capacitor pattern, the first pattern serves as an active layer of the first transistor, and the second pattern serves as an active layer of the second transistor,
  • the capacitor pattern serves as the first pole of the storage capacitor;
  • the first metal layer includes a first electrode plate, and at least a first overlapping area exists between the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the capacitor pattern on the substrate to form a first storage capacitor;
  • the second metal layer includes a second electrode plate, and at least a second overlapping area exists between the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the capacitor pattern on the substrate to form a second storage capacitor;
  • the electric potential of the first electrode plate and the second electrode plate are the same.
  • a gate insulating layer is further included between the first insulating layer and the second insulating layer, and the thickness of the gate insulating layer is smaller than the thickness of the second insulating layer.
  • the thickness of the first insulating layer is less than the sum of the thicknesses of the gate insulating layer and the second insulating layer.
  • a gate metal layer is further included between the first metal layer and the second metal layer, and the thickness of the second metal layer is greater than the thickness of the gate metal layer.
  • the channel width to length ratio of the first transistor is smaller than the channel width to length ratio of the second transistor.
  • the voltage of the first power supply voltage line is greater than the voltage of the second power supply voltage line
  • the maximum voltage of the data line is less than the maximum voltage of the first scan line
  • the data The maximum voltage of the line is less than the voltage of the first power supply voltage line.
  • the orthographic projection of the first pattern on the substrate and the orthographic projection of the capacitor pattern on the substrate are spaced apart, and the orthographic projection of the first pattern on the substrate The projection and the orthographic projection of the first electrode plate on the substrate are arranged at intervals.
  • the first pattern and the capacitor pattern are an integral structure.
  • the pixel driving circuit further includes a third transistor, the gate electrode of the third transistor is coupled to the second scan line, the first electrode of the third transistor is connected to the compensation line, so The second electrode of the third transistor is coupled to the second electrode of the second transistor.
  • the metal oxide layer further includes a third pattern, and the third pattern serves as an active layer of the third transistor.
  • the second insulating layer covers the first scan line, the second scan line, the gate electrode of the first transistor, the gate electrode of the second transistor, and the A gate electrode of the third transistor; and a plurality of via holes are respectively opened on the second insulating layer.
  • the second metal layer further includes the data line, the first power supply voltage line, the source electrode of the first transistor, the drain electrode of the first transistor, and the The source electrode of the second transistor, the drain electrode of the second transistor, the source electrode of the third transistor, and the drain electrode of the third transistor.
  • the source electrode of the first transistor and the data line have an integrated structure
  • the source electrode of the second transistor and the first power supply voltage line have an integrated structure
  • the second transistor has an integrated structure with the data line.
  • the drain electrode of the transistor and the drain electrode of the third transistor are integrated with the second plate.
  • the capacitor plate and the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are arranged in the same layer and have the same material. And it is formed by the same patterning process.
  • the second plate is connected to the data line, the first power supply voltage line, the first source electrode, the drain electrode of the first transistor, and the second transistor
  • the source electrode of the second transistor, the drain electrode of the second transistor, the source electrode of the third transistor, and the drain electrode of the third transistor are arranged in the same layer, have the same material, and are formed by the same patterning process.
  • the metal oxide layer is a single layer, a double layer or a multilayer.
  • the metal oxide layer includes a first oxide layer and a second oxide layer that are stacked, wherein the second oxide layer is more conductive than the first oxide layer.
  • the layer is low, and the band gap of the second oxide layer is larger than that of the first oxide layer.
  • the first oxide layer is disposed close to the gate electrodes of the first transistor, the second transistor, and the third transistor.
  • the present disclosure also provides a display device including any of the above-mentioned display substrates.
  • FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit
  • FIG. 2a is a schematic diagram showing an exemplary partial structure of a substrate according to an embodiment of the disclosure
  • Figure 2b is a cross-sectional view along the A-A direction in Figure 2a;
  • FIG. 3a is a schematic diagram after the first metal layer pattern is formed in the present disclosure
  • Figure 3b is a cross-sectional view along the A-A direction in Figure 3a;
  • FIG. 4a is a schematic diagram after the active layer and the capacitor plate pattern are formed in the present disclosure
  • Figure 4b is a cross-sectional view along the A-A direction in Figure 4a;
  • FIG. 5a is a schematic diagram of the disclosure after forming a gate electrode pattern
  • Figure 5b is a cross-sectional view along the A-A direction in Figure 5a;
  • Fig. 6a is a schematic diagram of the present disclosure after forming a second insulating layer pattern
  • Figure 6b is a cross-sectional view taken along the line A-A in Figure 6a;
  • Fig. 7a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the present disclosure.
  • Figure 7b is a cross-sectional view taken along the line A-A in Figure 7a;
  • FIG. 8a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the disclosure.
  • Figure 8b is a cross-sectional view along the A-A direction in Figure 8a;
  • FIG. 9a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the disclosure.
  • Figure 9b is a cross-sectional view along the A-A direction in Figure 9a;
  • FIG. 10a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the disclosure.
  • Figure 10b is a cross-sectional view along the line A-A in Figure 10a;
  • FIG. 11 is an overall layout diagram of a display substrate according to an embodiment of the disclosure.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in the present disclosure, the “source electrode” and the “drain electrode” can be interchanged with each other.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the "conductive layer” may be referred to as the “conductive film” in some cases.
  • the “insulating film” may be referred to as an “insulating layer” in some cases.
  • the “semiconductor” in the present disclosure may sometimes be referred to as an “insulator”.
  • the “insulator” in the present disclosure may sometimes be referred to as “semiconductor”.
  • the “insulator” in the present disclosure may sometimes be referred to as “semi-insulator”.
  • the “semiconductor” in the present disclosure may sometimes be referred to as “conductor”.
  • the “conductor” in the present disclosure may sometimes be referred to as a “semiconductor”.
  • the impurities of the semiconductor refer to elements other than the main components of the semiconductor.
  • elements with a concentration lower than 0.1 atomic% are impurities.
  • a density of states (DOS) may be formed in the semiconductor, the carrier mobility may be reduced, or the crystallinity may be reduced.
  • the semiconductor contains an oxide semiconductor as examples of impurities that change the characteristics of the semiconductor, there are group 1 elements, group 2 elements, group 14 elements, group 15 elements, transition metals other than the main component, etc., as typical examples .
  • oxygen vacancies sometimes occur due to the mixing of impurities such as hydrogen.
  • the semiconductor contains silicon, as examples of impurities that change the characteristics of the semiconductor, there are oxygen, a group 1 element, a group 2 element, a group 13 element, and a group 15 element other than hydrogen.
  • the part where the gate electrode and the source electrode overlap is usually used as the two plates of the storage capacitor, and the gate insulating layer acts as the dielectric.
  • the overlap area of the plate is usually increased , Choose a higher dielectric constant material as the gate insulating layer or reduce the thickness of the gate insulating layer.
  • the solution to increase the overlapping area of the plates not only runs counter to the high resolution requirement, but also reduces the design margin, which causes increased process difficulty, yield loss, and reduced display quality.
  • the solution of choosing a higher dielectric constant material as the gate insulating layer can increase the capacity of the storage capacitor, but in other areas of the display substrate, the high dielectric constant material has a greater impact on the performance of the transistor and will also reduce the display quality.
  • the solution to reduce the thickness of the gate insulating layer not only increases the process flow, but is also incompatible with the self-aligned doping process, which will also reduce the display quality.
  • an embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a base.
  • the display substrate of the present disclosure includes a plurality of sub-pixels corresponding to different colors arranged on the base, and each sub-pixel includes a pixel driving circuit and an electrical connection to the pixel driving circuit.
  • Organic electroluminescent diode OLED Organic electroluminescent diode OLED.
  • FIG. 1 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CST .
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the gate electrode of the first transistor T1 is coupled to the first scan line Gn, the first electrode of the first transistor T1 is coupled to the data line Dn, and the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2,
  • the first transistor T1 is used to receive the data signal transmitted by the data line Dn under the control of the first scan line Gn, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power supply voltage line VDD, and the second electrode of the second transistor T2 is coupled to the OLED
  • the first pole and the second transistor T2 are used to generate a corresponding current on the second pole under the control of the data signal received by the gate electrode.
  • the gate electrode of the third transistor T3 is coupled to the second scan line Sn, the first electrode of the third transistor T3 is connected to the compensation line Se, and the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2.
  • the three transistors T3 are used to extract the threshold voltage Vth and the mobility of the second transistor T2 in response to the compensation timing to compensate the threshold voltage Vth.
  • the first pole of the OLED is coupled to the second pole of the second transistor T2, and the second pole of the OLED is coupled to the second power supply voltage line VSS.
  • the OLED is used to emit corresponding brightness in response to the current of the second pole of the second transistor T2.
  • the first storage capacitor C ST electrode of the second transistor T2 is coupled to the gate electrode
  • the second electrode of the storage capacitor C ST is coupled to the second electrode of the second transistor T2
  • is connected to the storage capacitor C ST is used to store a second transistor T2
  • the potential of the gate electrode is used to store a second transistor T2 The potential of the gate electrode.
  • the voltage of the first power supply voltage line VDD is greater than the voltage of the second power supply voltage line VSS, the maximum voltage of the data signal of the data line Dn is less than the maximum voltage of the first scan line Gn, and the maximum voltage of the data signal of the data line Dn is less than that of the first power supply.
  • the voltage of the voltage line VDD is greater than the voltage of the second power supply voltage line VSS.
  • the substrate includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer, and a second metal layer that are stacked;
  • the metal oxide layer includes The first pattern, the second pattern and the capacitance pattern, the first pattern is used as the active layer of the first transistor, the second pattern is used as the active layer of the second transistor, and the capacitance pattern is used as the The first electrode of the storage capacitor;
  • the first metal layer includes a first electrode plate as a second electrode of the storage capacitor, the orthographic projection of the first electrode plate on the substrate and the capacitor pattern on the substrate There is at least a first overlapping area in the orthographic projection to form a first storage capacitor;
  • the second metal layer includes a second electrode plate as another second electrode of the storage capacitor, and the second electrode plate is on the substrate There is at least a second overlap area between the orthographic projection on the substrate and the orthographic projection of the capacitor pattern on the substrate to form a second storage capacitor;
  • a first storage capacitor and a second storage capacitor are formed by a metal oxide layer, a first electrode plate of the first metal layer and a second electrode plate of the second metal layer, respectively, and the first electrode
  • the potential of the plate and the second plate are the same, thus forming the first storage capacitor and the second storage capacitor in parallel, which effectively increases the capacity of the storage capacitor, and effectively increases the capacity of the storage capacitor without affecting the display quality. And it is conducive to the realization of high-resolution display.
  • the display substrate can be implemented in a variety of ways, which will be described in detail in the following embodiments.
  • FIG. 2a is a schematic diagram showing an exemplary partial structure of a substrate according to an embodiment of the disclosure
  • FIG. 2b is a cross-sectional view taken along the line A-A in FIG. 2a.
  • the display substrate provided by this embodiment includes:
  • the first insulating layer 12 covers the first metal layer including the first electrode plate 11 and the connecting wire 40;
  • a metal oxide layer is provided on the first insulating layer 12, and the metal oxide layer includes a first pattern as the first active layer 13, a second pattern as the second active layer 23, and a third active layer 33.
  • the third pattern and the capacitive pattern as the capacitive plate 14, the orthographic projection of the capacitive plate 14 on the substrate 10 and the orthographic projection of the first plate 11 on the substrate 10 have a first overlap area, and the capacitive plate 14 serves as a storage
  • the first pole of the capacitor is used to form a first storage capacitor with the first pole plate 11;
  • the patterns of the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 are the same.
  • the first gate electrode 16 and the first scan line Gn have an integral structure.
  • the gate electrode 36 and the second scan line Sn have an integral structure;
  • the second insulating layer 17 covers the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and a plurality of via holes are respectively opened thereon, and a plurality of via holes Including: the first via hole V1 and the second via hole V2 exposing both ends of the first active layer 13, the third via hole V3 exposing the second gate electrode 26, and the fourth via hole V4 exposing the capacitor plate 14 , The fifth via hole V5 and the sixth via hole V6 at both ends of the second active layer 23 are exposed, the seventh via hole V7 of the first electrode plate 11 is exposed, and the eighth via hole at both ends of the third active layer 33 is exposed.
  • the hole V8 and the ninth via hole V9 expose the tenth via hole V10 of the connecting line 40;
  • the first active layer may be the active layer of the first transistor T1
  • the second active layer may be an active layer of the second transistor T2
  • the third active layer may be an active layer of the third transistor T3.
  • the second metal layer includes a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, and a second The drain electrode 29, the third source electrode 38, the third drain electrode 39, and the second plate 30.
  • the second electrode plate 30 serves as the other second electrode of the storage capacitor and is used to form a second storage capacitor with the capacitor electrode plate 14.
  • the first source electrode 18 and the data line Dn have an integrated structure
  • the second source electrode 28 and the first power supply voltage line VDD have an integrated structure
  • the second drain electrode 29 and the third drain electrode 39 and the second electrode plate 30 have an integrated structure.
  • the first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1
  • the first drain electrode 19 is connected to the other end of the first active layer 13 through the second via hole V2.
  • the pole 19 is connected to the second gate electrode 26 through the third via hole V3, and the first drain electrode 19 is also connected to the capacitor plate 14 through the fourth via hole V4.
  • the second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6.
  • the third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8, and is also connected to the connecting line 40 through the tenth via hole V10.
  • the third drain electrode 39 is connected to the third active layer through the ninth via hole V9.
  • the other end of the source layer 33 is connected.
  • the second electrode plate 30 is connected to the first electrode plate 11 through the seventh via hole V7, so that the first electrode plate 11 and the second electrode plate 30 have the same potential.
  • the first source electrode 18 may be the source electrode of the first transistor T1
  • the first drain electrode 19 may be the drain electrode or the second source electrode 28 of the first transistor T1. It may be the source electrode of the second transistor T2, the second drain electrode 29 may be the drain electrode of the second transistor T2, and the third source electrode 38 may be the source electrode and the third drain electrode of the third transistor T3. 39 may be the drain electrode of the third transistor T3.
  • the source electrode of the first transistor T1 may be the first electrode or the second electrode of the first transistor T1, and the drain electrode of the first transistor T1 may be the The second electrode or the first electrode of the first transistor T1; the source electrode of the second transistor T2 may be the first electrode or the second electrode of the second transistor T2, and the source electrode of the second transistor T2
  • the capacitive electrode plate 14 is arranged in the same layer as the first active layer 13, the second active layer 23 and the third active layer 33, the material is the same and is formed by the same patterning process; the second electrode plate 30 and the data line Dn , The first power supply voltage line VDD, the first source electrode 18, the first drain electrode 19, the second source electrode 28, the second drain electrode 29, the third source electrode 38, and the third drain electrode 39 are arranged in the same layer, with the same material and It is formed by the same patterning process.
  • the capacitor plate 14 is used as the first electrode of the storage capacitor
  • the first plate 11 is used as a second electrode of the storage capacitor and also as a shielding layer
  • the second plate 30 is used as the other second electrode of the storage capacitor.
  • the technical solution of this embodiment is further described below through the preparation process of the display substrate of this embodiment.
  • the "patterning process” referred to in this embodiment includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which is a mature preparation process.
  • the deposition may use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating may use a known coating process, and the etching may use a known method, which is not limited herein.
  • thin film refers to a thin film made by depositing a certain material on a substrate or other processes.
  • the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” needs a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • Forming the first metal layer pattern includes: depositing a first metal film on a substrate, patterning the first metal film through a patterning process, and forming a first metal layer including a pattern of the first electrode plate 11 and the connecting line 40 on the substrate 10, As shown in Fig. 3a and Fig. 3b, Fig. 3b is a cross-sectional view along the AA direction in Fig. 3a.
  • the first electrode plate 11 serves not only as a shielding layer, but also as a second electrode of the storage capacitor to form the first storage capacitor.
  • Forming the pattern of the metal oxide layer includes: sequentially depositing a first insulating film and a metal oxide film on the substrate on which the aforementioned pattern is formed, and patterning the metal oxide film through a patterning process to form a covering first electrode plate 11 and connecting lines 40 of the first insulating layer 12, and the metal oxide layer pattern formed on the first insulating layer 12, the metal oxide layer includes the second active layer 23, the first active layer 13, the third active layer 33 and
  • the pattern of the capacitor plate 14 is shown in FIG. 4a and FIG. 4b, and FIG. 4b is a cross-sectional view along the AA direction in FIG. 4a.
  • the first active layer 13 corresponds to the first pattern, as the active layer of the first transistor, and the second active layer 23 corresponds to the second pattern, as the active layer of the second transistor, and the third active layer 33
  • the capacitor plate 14 corresponds to the capacitor pattern, and the capacitor pattern is conductively processed as the first electrode of the storage capacitor.
  • the orthographic projection of the capacitor plate 14 (capacitance pattern) on the substrate 10 and the orthographic projection of the first electrode plate 11 on the substrate 10 have a first overlapping area, and the first electrode plate 11 serves as the second electrode of the storage capacitor and
  • the capacitor plate 14 forms a first storage capacitor.
  • the orthographic projection of the first active layer 13 (first pattern) as the active layer of the first transistor on the substrate 10 and the orthographic projection of the capacitor plate 14 (capacitance pattern) on the substrate 10 are spaced apart , That is, there is no overlapping area between the two.
  • the orthographic projection of the first active layer 13 (first pattern) on the substrate 10 and the orthographic projection of the first electrode plate 11 on the substrate 10 are spaced apart, that is, there is no overlapping area between the two.
  • the widths of the first active layer 13 and the second active layer 23 the channel aspect ratio of the first transistor is smaller than that of the second transistor.
  • Forming the gate electrode pattern includes: sequentially depositing a gate insulating film and a gate metal film on the substrate with the aforementioned pattern, patterning the gate insulating film and the gate metal film through a patterning process, forming a pattern of the gate insulating layer 15 and setting it on the gate insulating film.
  • the pattern of the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26 and the third gate electrode 36 on the layer 15, the pattern of the gate insulating layer 15 and the first scan line Gn, the second scan The line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 have the same pattern.
  • the second gate electrode 26 is located at a position corresponding to the first electrode plate 11.
  • the first gate electrode 16 is connected to the first scan line Gn.
  • the third gate electrode 36 is an integrated structure connected to the second scan line Sn, as shown in FIG. 5a and FIG. 5b, and FIG. 5b is a cross-sectional view along the AA direction in FIG. 5a.
  • Forming the second insulating layer pattern includes: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating film through a patterning process to form a pattern of the second insulating layer 17 covering the aforementioned structure.
  • a plurality of via holes are opened on 17 and the plurality of via holes are respectively: the first via hole V1 and the second via hole V2 exposing both ends of the first active layer 13 and the third via hole exposing the second gate electrode 26 V3, the fourth via hole V4 of the capacitor plate 14 is exposed, the fifth via hole V5 and the sixth via hole V6 at both ends of the second active layer 23 are exposed, and the seventh via hole V7 of the first plate 11 is exposed , The eighth via V8 and the ninth via V9 at both ends of the third active layer 33 are exposed, and the tenth via V10 of the connecting line 40 is exposed, as shown in FIG. 6a and FIG. 6b, and FIG. 6b is in FIG. 6a Sectional view in AA direction.
  • the thickness of the gate insulating layer 15 is smaller than the thickness of the second insulating layer 17, and the thickness of the first insulating layer 12 is smaller than the sum of the thicknesses of the gate insulating layer 15 and the second insulating layer 17, under the premise of ensuring the insulating effect. , Improve the capacity of the storage capacitor.
  • Forming the second metal layer pattern includes: depositing a second metal film on the substrate with the aforementioned pattern, patterning the second metal film through a patterning process, and forming a second metal layer pattern on the second insulating layer 17.
  • the metal layer includes: a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, a second drain electrode 29, a third source electrode 38, and a third drain electrode 39 And the second plate 30 pattern.
  • the first source electrode 18 is an integrated structure connected to the data line Dn
  • the second source electrode 28 is an integrated structure connected to the first power supply voltage line VDD
  • the second drain electrode 29 and the third drain electrode 39 are connected to the second The integral structure of the connection of the plates 30.
  • the first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1
  • the first drain electrode 19 is connected to the other end of the first active layer 13 through the second via hole V2.
  • the first leakage current The pole 19 is connected to the second gate electrode 26 through the third via hole V3, and the first drain electrode 19 is also connected to the capacitor plate 14 through the fourth via hole V4.
  • the second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6.
  • the third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8, and is also connected to the connecting line 40 through the tenth via hole V10.
  • the third drain electrode 39 is connected to the third active layer through the ninth via hole V9.
  • the other end of the source layer 33 is connected.
  • the second electrode plate 30 is connected to the first electrode plate 11 through the seventh via hole V7.
  • the orthographic projection of the second electrode plate 30 on the substrate 10 and the orthographic projection of the capacitor electrode plate 14 on the substrate 10 have a second overlapping area, As another second pole of the storage capacitor, it is used to form a second storage capacitor with the capacitor plate 14, as shown in FIG. 2a and FIG. 2b.
  • the thickness of the second metal layer is greater than the thickness of the gate metal layer.
  • the first metal layer, the gate metal layer, and the second metal layer can be made of metal materials, such as chromium (Cr), gold (Au), zinc (Zn), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), etc., Or an alloy containing the foregoing metal elements as a component or an alloy containing a combination of the foregoing metal elements, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., may be a multilayer metal, such as Mo/Cu/Mo.
  • metal materials such as chromium (Cr), gold (Au), zinc (Zn), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), tantalum (Ta), titanium (Ti),
  • a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used.
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti
  • a Cu-Mn alloy film is used.
  • the thickness of the first metal layer is 800 to 1200 angstroms
  • the thickness of the gate metal layer is 3000 to 5000 angstroms
  • the thickness of the second metal layer is 3000 to 9000 angstroms.
  • the first insulating layer, the gate insulating layer, and the second insulating layer may be silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), or may be aluminum oxide (AlOx), hafnium oxide (HfOx). ), tantalum oxide (TaOx), yttrium oxide, zirconium oxide, gallium oxide, magnesium oxide, lanthanum oxide, cerium oxide or neodymium oxide, etc.
  • the thickness of the first insulating layer is 3000 to 5000 angstroms
  • the thickness of the gate insulating layer is 1000 to 2000 angstroms
  • the thickness of the second insulating layer is 4500 to 7000 angstroms.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten and indium and zinc, an oxide containing titanium and indium, and an oxide containing titanium and indium.
  • the metal oxide layer may be an oxide semiconductor containing indium (In), which can increase carrier mobility (electron mobility).
  • the oxide semiconductor may contain the element M.
  • the element M may be aluminum, gallium, yttrium, tin, or the like.
  • other elements that can be used as the element M there are boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten.
  • the element M a plurality of the above-mentioned elements may be combined in some cases.
  • the element M is an element having a high bond energy with oxygen, for example.
  • the element M is an element whose bond energy with oxygen is higher than that of indium.
  • the element M is, for example, an element having a function of increasing the energy gap of an oxide semiconductor.
  • the metal oxide layer may contain zinc (Zn), and it is easy to crystallize when the oxide semiconductor contains zinc.
  • the oxide semiconductor is not limited to an oxide semiconductor containing indium, and may be an oxide semiconductor containing zinc, gallium, or tin that does not contain indium, such as zinc tin oxide or gallium tin oxide.
  • the metal oxide layer is In-M-Zn oxide, when the sum of In and M is 100 atomic%, it may be: In is less than 50 atomic%, and M is more than 50 atomic%.
  • the metal oxide layer uses an oxide with a large energy gap, for example, 2.5 eV or more and 4.2 eV or less, or may be 2.8 eV or more and 3.8 eV or less, or may be 3 eV or more and 3.5 eV or less.
  • the metal oxide layer is an oxide containing indium (In), M, and zinc (Zn), where M is aluminum (Al), gallium (Ga), or tin (Sn).
  • the composition of the active layer of the first, second and third transistors may be the same or substantially the same to reduce the manufacturing cost.
  • This embodiment is not limited to this, and the compositions of the active layers of the three transistors may also be different from each other.
  • the active layers of the three transistors all have regions where the atomic percentage of In is greater than the atomic percentage of M, the field effect mobility of the first transistor and the second transistor can be improved.
  • one or both of the field-effect mobility of the first transistor and the second transistor may exceed 10 cm2/Vs, for example, may exceed 30 cm2/Vs.
  • the display device when the above-mentioned transistor with high field-effect mobility is used in a gate driver for generating a gate signal of a display device, the display device may have a narrow bezel.
  • the above-mentioned transistor with high field-effect mobility is used in a source driver that supplies a signal from a signal line included in a display device, the number of wirings connected to the display device can be reduced.
  • the above-mentioned transistor with high field effect mobility is used for the transistor of the pixel circuit included in the display device, the display quality of the display device can be improved.
  • the metal oxide layer of this embodiment may be a single layer, or a double layer or multiple layers.
  • the metal oxide layer When the metal oxide layer is a double layer, it includes a first oxide layer and a second oxide layer that are stacked.
  • the conductivity of the second oxide layer may be lower than that of the first oxide layer and the band gap may be larger than that of the first oxide layer.
  • the first oxide layer may be a main channel layer through which electrons move, and thus may be disposed close to the first, second, and third gate electrodes.
  • IGZO indium gallium zinc oxide
  • the channel directions and shapes of different sub-pixels can be realized.
  • the channel aspect ratio of the first transistor is smaller than the channel aspect ratio of the second transistor.
  • the metal oxide layer can have different composition content to meet different electrical characteristics.
  • the aforementioned conductive treatment is to perform plasma treatment using the first, second, and third gate electrodes as masks after the patterns of the first, second, and third gate electrodes are formed to oxidize the metal in the corresponding area.
  • the material layer is processed into a conductive layer.
  • the metal oxide layer can be divided into three regions.
  • the first region includes the region overlapping the first, second, and third gate electrodes. This region serves as the channel region of the transistor.
  • the second area includes the area adjacent to the first area, that is, the area adjacent to the first, second, and third gate electrodes but not covered by the first, second, and third gate electrodes. This area serves as the source and drain area of the transistor.
  • the three areas include the area overlapping the first electrode plate and the second electrode plate, and this area is used as the electrode plate area of the storage capacitor.
  • the composition of indium gallium zinc oxide (IGZO) in the three regions is different.
  • the oxygen content of the first region is in the range of 30 to 50 atomic%
  • the oxygen content of the second region is in the range of 50 to 60 atomic%
  • the oxygen content of the second region is in the range of 60 to 70 atomic%.
  • the oxygen content of IGZO in the first region is less than the oxygen content of IGZO in the second region
  • the oxygen content of IGZO in the second region is less than the oxygen content of IGZO in the third region.
  • the zinc content of IGZO in the first region is greater than the zinc content of IGZO in the second region
  • the zinc content of IGZO in the second region is greater than the zinc content of IGZO in the third region.
  • the zinc content of IGZO in the first region The atomic ratio of oxygen to zinc (O/Zn) is smaller than O/Zn in the second region, and O/Zn in the second region is smaller than O/Zn in the third region.
  • the oxide in the first region is mainly of semiconductor characteristics. Increasing the content of In element can significantly increase the carrier concentration. In order to increase the carrier concentration in the first region and improve the driving ability of the transistor, the content of In atoms in the first region is greater than that in the second region. The atomic content, and the In atomic content in the second region is greater than the In atomic content in the third region.
  • the following table shows an example of the composition of indium gallium zinc oxide (IGZO) in the three regions.
  • Weight% represents the proportion of the element in the oxide
  • Atomic% represents the atomic percentage of the element in the oxide.
  • the first area is the channel area of at least one of the three transistors
  • the second area is the source and drain area of at least one of the three transistors
  • the third area is the plate area of the storage capacitor.
  • IGZO includes elements such as oxygen (O), zinc (Zn), gallium (Ga), and indium (In).
  • the first region is shielded by the gate electrode without plasma treatment.
  • the relative weight content of Zn:Ga:In is 11.82:25.68:28.38:34.12
  • the atomic relative content is 40.24:21.40:22.18:16.18.
  • the relative weight content of multiple elements O:Zn:Ga:In is 23.35:18.72:25.66:32.24, and the relative atomic content is 60.94:11.95:15.37:11.72.
  • the weight and atomic content of oxygen in the IGZO in the third region are greatly increased, and the weight and atomic content of zinc (Zn) are reduced, which improves the conductivity of IGZO.
  • the second region is not blocked by the gate electrode, because this region is adjacent to the gate electrode and affected by the gate electrode, the weight and atomic content of oxygen in the IGZO in the second region is lower than that of the third region, and the weight and atomic content of zinc (Zn) It is higher than the third region, so the conductivity of IGZO in the second region is lower than that of IGZO in the third region.
  • the metal oxide layer in the third region serves as the first pole of the storage capacitor, it needs good electrical conductivity, that is, it needs a better degree of conductorization.
  • the gate electrode is used as a mask for plasma treatment, in theory, the further away from the gate electrode, the better the degree of conductorization and the better the conductivity.
  • the minimum distance between the metal oxide layer (capacitor plate 14) and the first gate electrode 16 in the third region may be greater than L1, and the minimum distance between the capacitor plate 14 and the second gate electrode 26 may be greater than L2, the minimum distance between the capacitor plate 14 and the third gate electrode 36 is greater than L3, L1 is the width of the first gate electrode 16, L2 is the width of the second gate electrode 26, and L3 is the width of the third gate electrode 36.
  • L1 is the width of the first gate electrode 16
  • L2 is the width of the second gate electrode 26
  • L3 is the width of the third gate electrode 36.
  • the above-mentioned distance is the distance between the two in the direction perpendicular to the substrate.
  • the minimum distance between the metal oxide layer (capacitor plate 14) and the first gate electrode 16 in the third region is greater than L1
  • the capacitor plate The minimum distance between 14 and the second gate electrode 26 is greater than L2
  • the minimum distance between the capacitor plate 14 and the third gate electrode 36 is greater than L3, these three designs can meet any two or one of the conditions .
  • L1 is the width of the first gate electrode 16
  • L2 is the width of the second gate electrode 26
  • L3 is the width of the third gate electrode 36.
  • the capacitor plate 14 made of metal oxide is used as the first electrode of the storage capacitor, and the first plate 11 in the first metal layer is used as the first electrode of the storage capacitor.
  • One second pole of the storage capacitor, and the second electrode plate 30 in the second metal layer serves as the other second pole of the storage capacitor. Since the second electrode plate 30 is connected to the first electrode plate 11 through the seventh via V7, The first plate 11 and the second plate 30 have the same potential, and the capacitor plate 14 as the first electrode of the storage capacitor passes through the third via V3, the first drain electrode 19, and the fourth via V4.
  • the gate electrode 26 is connected and has a different voltage from the first electrode plate 11 and the second electrode plate 30.
  • the storage capacitor of the embodiment of the present disclosure is formed by three capacitors in parallel, which maximizes the capacity of the storage capacitor.
  • the capacitor plate 14 used as the first electrode of the storage capacitor and the active layer in this embodiment are arranged in the same layer and located between the first metal layer and the second metal layer, the capacitor plate 14 and the first electrode plate 11 are located in the same layer.
  • the distance between the two is relatively short, only the first insulating layer 12 is separated, and the distance between the capacitor plate 14 and the second plate 30 is also relatively short, and only the second insulating layer 17 is separated.
  • the capacity of each storage capacitor of the present disclosure is greater than that of the storage capacitor of the original structure, even if it is applied to a smaller
  • the pixel size can also ensure the required storage capacitor capacity, which is conducive to achieving high-resolution display. Since neither the first insulating layer 12 and the second insulating layer 17 need to use high-dielectric constant materials nor reduce the thickness, the structural design of the embodiment of the present disclosure does not increase the process flow, and is compatible with the self-aligned doping process , Will not affect the performance of the thin film transistor, and ensure the display quality.
  • the patterning times of the display substrate prepared in this embodiment are the same as the patterning times of the original preparation method.
  • Existing process equipment can be used to implement this embodiment, which has good process compatibility, strong practicability, and good applications. prospect.
  • this embodiment realizes the effective increase of the storage capacitor under the premise of ensuring the display quality, and is beneficial to the realization of high-resolution display.
  • FIG. 7a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the disclosure
  • FIG. 7b is a cross-sectional view taken along the line A-A in FIG. 7a.
  • This embodiment includes a capacitor plate as the first electrode of the storage capacitor, a first plate as a shielding layer and a second electrode of the storage capacitor, and a second plate as the other second electrode of the storage capacitor.
  • a first storage capacitor is formed between a plate and a capacitor plate, and a second storage capacitor is formed between the second plate and the capacitor plate.
  • the first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor.
  • the capacitor plate 14 and the first active layer 13 can be an integral structure, that is, the capacitor plate 14 and the first active layer 13 are continuous
  • the metal oxide is formed, and the fourth via is eliminated.
  • the display substrate of this embodiment includes:
  • the structure of the substrate 10, the first electrode plate 11, the connecting wire 40 and the first insulating layer 12 can be referred to the description in the foregoing embodiment;
  • the metal oxide layer includes a first active layer 13, a second active layer 23, a third active layer 33 and a capacitor plate 14.
  • the first active layer 13 and the capacitor plate 14 are an integral structure, the orthographic projection of the capacitor plate 14 on the substrate 10 and the orthographic projection of the first electrode plate 11 on the substrate 10 have a first overlap area, and the capacitor plate 14 serves as the first overlapped area of the storage capacitor.
  • One pole is used to form a first storage capacitor with the first pole plate 11;
  • the gate insulating layer 15 and the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 are arranged on the gate insulating layer 15.
  • the structure can be referred to in the previous embodiment description;
  • the second insulating layer 17 covers the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and a plurality of via holes are respectively opened thereon.
  • the fourth via hole in the foregoing embodiment is eliminated; or it can be understood that the second via hole and the fourth via hole in the foregoing embodiment are via holes of the integrated structure of this embodiment;
  • the second metal layer includes a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, and a second The drain electrode 29, the third source electrode 38, the third drain electrode 39, and the second plate 30.
  • the second electrode plate 30 serves as the other second electrode of the storage capacitor and is used to form a second storage capacitor with the capacitor electrode plate 14.
  • the first source electrode 18 and the data line Dn have an integrated structure
  • the second source electrode 28 and the first power supply voltage line VDD have an integrated structure
  • the second drain electrode 29 and the third drain electrode 39 and the second electrode plate 30 have an integrated structure.
  • the first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1
  • the first drain electrode 19 is connected to the other end of the first active layer 13 (also the capacitor plate 14) through the integrated via hole.
  • the first drain electrode 19 is connected to the second gate electrode 26 through the third via V3.
  • the second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6.
  • the third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8, and is also connected to the connecting line 40 through the tenth via hole V10.
  • the third drain electrode 39 is connected to the third active layer through the ninth via hole V9.
  • the other end of the source layer 33 is connected.
  • the second electrode plate 30 is connected to the first electrode plate 11 through the seventh via hole V7.
  • This embodiment can also increase the capacity of the storage capacitor, facilitate high-resolution display, and ensure display quality.
  • the capacitor plate and the second active layer are arranged in an integrated structure, which are at the same potential, so the fourth via is eliminated, which simplifies the via etching process, and facilitates the realization of high-resolution design.
  • the area of the capacitor plate is increased, and the capacity of the overall storage capacitor is further improved.
  • the second active layer and the capacitor plate pattern in the process of forming the active layer and the capacitor plate pattern, the second active layer and the capacitor plate are integrated; the second active layer and the capacitor plate are formed as an integrated structure; In the process of patterning the insulating layer, it is not necessary to form the fourth via hole. In the process of forming the second metal layer pattern, the second drain electrode is only connected to the second active layer through the second via hole and to the first gate through the third via hole. The electrode connection will not be repeated here.
  • FIG. 8a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the disclosure
  • FIG. 8b is a cross-sectional view taken along the line A-A in FIG. 8a.
  • This embodiment includes a capacitor plate as the first electrode of the storage capacitor, a first plate as a shielding layer and a second electrode of the storage capacitor, and a second plate as the other second electrode of the storage capacitor.
  • a first storage capacitor is formed between a plate and a capacitor plate, and a second storage capacitor is formed between the second plate and the capacitor plate.
  • the first storage capacitor and the second storage capacitor are connected in parallel to form a storage capacitor. As shown in FIGS.
  • the display substrate of this embodiment includes:
  • the structure of the substrate 10, the first electrode plate 11, the connecting wire 40 and the first insulating layer 12 can be referred to the description in the foregoing embodiment;
  • the metal oxide layer includes a first active layer 13, a second active layer 23, a third active layer 33 and a capacitor plate 14.
  • the first active layer 13 and the capacitor plate 14 are an integral structure, the orthographic projection of the capacitor plate 14 on the substrate 10 and the orthographic projection of the first electrode plate 11 on the substrate 10 have a first overlap area, and the capacitor plate 14 serves as the first overlapped area of the storage capacitor.
  • One pole is used to form a first storage capacitor with the first pole plate 11;
  • the gate insulating layer 15 and the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26 and the third gate electrode 36 are arranged on the gate insulating layer 15.
  • the gate insulating layer 15 is connected to the first The scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 have the same pattern.
  • the first gate electrode 16 is an integrated structure connected to the first scan line Gn.
  • the electrode 36 is an integral structure connected to the second scan line Sn, and the second gate electrode 26 is in the shape of a broken line;
  • the second insulating layer 17 covers the first scan line Gn, the second scan line Sn, the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36, and a plurality of via holes are respectively opened thereon, and a plurality of via holes Including: the first via hole V1 exposing one end of the first active layer 13 and the second via hole V2 exposing the other end of the first active layer 13 and the second gate electrode 26 at the same time, exposing the second active layer 23
  • the fifth via hole V5 and the sixth via hole V6 at both ends expose the seventh via hole V7 of the first plate 11, and the eighth via hole V8 and the ninth via hole V9 at both ends of the third active layer 33 are exposed.
  • the tenth via hole V10 of the connecting line 40 is exposed; or it can be understood that the second via hole, the third via hole, and the fourth via hole of the foregoing embodiment are the via holes of the integrated structure of this embodiment;
  • the second metal layer includes a data line Dn, a first power supply voltage line VDD, a first source electrode 18, a first drain electrode 19, a second source electrode 28, and a second The drain electrode 29, the third source electrode 38, the third drain electrode 39, and the second plate 30.
  • the second electrode plate 30 serves as the other second electrode of the storage capacitor and is used to form a second storage capacitor with the capacitor electrode plate 14.
  • the first source electrode 18 and the data line Dn have an integrated structure
  • the second source electrode 28 and the first power supply voltage line VDD have an integrated structure
  • the second drain electrode 29 and the third drain electrode 39 and the second electrode plate 30 have an integrated structure.
  • the first source electrode 18 is connected to one end of the first active layer 13 through the first via hole V1
  • the first drain electrode 19 is connected to the other end of the first active layer 13 and the second gate electrode 26 through the integrated via hole. connection.
  • the second source electrode 28 is connected to one end of the second active layer 23 through the fifth via hole V5, and the second drain electrode 29 is connected to the other end of the second active layer 23 through the sixth via hole V6.
  • the third source electrode 38 is connected to one end of the third active layer 33 through the eighth via hole V8, and is also connected to the connection line 40 through the tenth via hole V10.
  • the third drain electrode 39 is connected to the third active layer through the ninth via hole V9.
  • the other end of the source layer 33 is connected.
  • the second electrode plate 30 is connected to the first electrode plate 11 through the seventh via hole V7.
  • This embodiment can also increase the capacity of the storage capacitor, facilitate high-resolution display, and ensure display quality.
  • the capacitor plate and the second active layer are arranged in an integrated structure to have the same potential, and the third via hole and the fourth via hole are eliminated, and only the second via hole and the second drain electrode are retained.
  • the second via hole is connected to the second active layer and the first gate electrode at the same time, which not only simplifies the process and facilitates the realization of high-resolution design, but also integrates the originally separated capacitor plate and the second active layer into one
  • the structure increases the area of the capacitor plate and the area of the second metal layer, which further improves the capacity of the overall storage capacitor.
  • the second active layer and the capacitor plate pattern in the process of forming the active layer and the capacitor plate pattern, the second active layer and the capacitor plate are integrated; In the process of patterning the second insulating layer, a via hole that simultaneously exposes the integrated structure of the second active layer and the first gate electrode is formed; in the process of forming the pattern of the source and drain electrodes and the second metal layer, the second drain electrode passes through the integrated structure. The hole is connected to the second active layer and the first gate electrode at the same time, which will not be repeated here.
  • Fig. 9a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the present disclosure
  • Fig. 9b is a cross-sectional view taken along the line A-A in Fig. 9a.
  • two second gate electrodes 26 are formed at the position of the first drain electrode 19.
  • the second gate electrode 26 is in the shape of a broken line
  • two second gate electrodes 26 are formed at the second transistor position, and the integral structure via holes opened on the second insulating layer 17 simultaneously expose the two second gates.
  • the electrode 26 and the first active layer 13 and the first drain electrode 19 are simultaneously connected to the first active layer 13 and the two second gate electrodes 26 through the integrated via hole.
  • the integrated via hole exposes the first active layer 13 in the region between the two second gate electrodes 26, and at the same time exposes the second gate electrode 26 of the two second gate electrodes 26 adjacent to each other.
  • This embodiment can also increase the capacity of the storage capacitor, facilitate high-resolution display, and ensure display quality.
  • this embodiment by providing two first gate electrodes, the size of the second via hole is reduced, and the connection reliability is increased, which is further conducive to the realization of high-resolution design.
  • the preparation process of the display substrate of this embodiment can be referred to the description in the foregoing embodiment.
  • two first gate electrodes are formed at the position of the second drain electrode, which will not be repeated here.
  • Fig. 10a is a schematic diagram showing another exemplary partial structure of a substrate according to an embodiment of the disclosure
  • Fig. 10b is a cross-sectional view taken along the line A-A in Fig. 10a.
  • the positions of the two second gate electrodes 26 are different in this embodiment, and the two second gate electrodes 26 are respectively arranged on both sides of the step formed by the first electrode plate 11.
  • the second gate electrode 26 is in the shape of a zigzag line, and two second gate electrodes 26 are formed at the second transistor position, one second gate electrode 26 is located on the step formed by the first plate 11, and the other The two gate electrodes 26 are located under the steps, and the integral structure via holes opened on the second insulating layer 17 simultaneously expose the two second gate electrodes 26 and the first active layer 13 between the two second gate electrodes 26.
  • a drain electrode 19 is simultaneously connected to the first active layer 13 and the two second gate electrodes 26 through the integrated via hole.
  • This embodiment can also increase the capacity of the storage capacitor, facilitate high-resolution display, and ensure display quality.
  • this embodiment by arranging the two first gate electrodes on both sides of the step formed by the first metal layer, the failure caused by the fracture of the second active layer at the step can be effectively prevented, and the reliability of the connection is improved. Sex. For example, since the first gate electrode connected to the second drain electrode is provided on and under the step, even if the second active layer is broken at the step, it can be ensured that the second active layer and the capacitor plate have the same Potential.
  • FIG. 11 is an overall layout diagram of a display substrate according to an embodiment of the disclosure.
  • the first power supply voltage line VDD, the two data lines Dn, and the compensation line Se of the display substrate are parallel to each other and arranged in sequence.
  • a pixel column is formed between the first power supply voltage line VDD and the adjacent data line Dn.
  • Another pixel column is formed between the compensation line Se and the adjacent data line Dn.
  • four pixel columns are formed by arranging one compensation line Se and four data lines Dn between adjacent first power supply voltage lines VDD, and two of the four data lines Dn are located on one side of the compensation line Se.
  • the other two data lines Dn are located on the other side of the compensation line Se.
  • four pixel columns are formed by setting one first power supply voltage line VDD and four data lines Dn between adjacent compensation lines Se. Two of the four data lines Dn are located on the first power supply voltage line. On one side of VDD, the other two data lines Dn are located on the other side of the first power supply voltage line VDD.
  • both the first power supply voltage line VDD and the compensation line Se adopt a one-to-four structure.
  • the display substrate further includes a plurality of connecting lines 40.
  • the connecting lines 40 and the shielding layer of the display substrate are arranged in the same layer and pass the same patterning. The process is formed, and the connection line 40 is perpendicular to the first power supply voltage line VDD (compensation line Se).
  • a plurality of connection lines 40 connected to the first power supply voltage line VDD through via holes are respectively electrically connected to the pixels in the pixel column between the compensation line Se and the data line Dn on both sides of the first power supply voltage line VDD.
  • VDD is directly electrically connected to the pixels of the pixel columns on both sides of the first power supply voltage line VDD, so that one first power supply voltage line VDD can provide signals to the pixels of the four pixel columns.
  • the multiple connection lines 40 connected to the compensation line Se through vias are respectively electrically connected to the pixels in the pixel column between the first power supply voltage line VDD and the data line Dn on both sides of the compensation line Se, since the compensation line Se is directly electrically connected The pixels of the pixel columns on both sides of the compensation line Se, such a compensation line Se can provide signals to the pixels of the four pixel columns.
  • the display substrate designs the first power supply voltage line and the compensation line as a one-to-four structure, which effectively increases the size of each pixel at the same resolution, and makes full use of layout space and overall layout. Reasonable and other advantages.
  • the embodiment of the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the terms “installed”, “connected”, and “connected” should be interpreted in a broad sense unless otherwise clearly defined and limited.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate piece, and it can be internal to two components. Connected.
  • the meaning of the above-mentioned terms in the present disclosure can be understood according to the situation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示基板和显示装置，该显示基板包括在基底上叠设的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层和第二金属层；金属氧化物层包括第一图形、第二图形和电容图形，第一金属层包括第一极板，第一极板与所述电容图形至少存在第一交叠区域，以形成第一存储电容，第二金属层包括第二极板，所述第二极板与电容图形至少存在第二交叠区域，以形成第二存储电容，第一极板和第二极板的电位相同。

Description

显示基板和显示装置
本申请要求于2019年12月13日提交中国专利局、申请号为201922237251.2、发明名称为“显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，OLED)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术。依据驱动方式的不同，OLED可分为无源矩阵驱动(Passive Matrix，PM)型和有源矩阵驱动(Active Matrix，AM)型两种，其中AMOLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
对于AMOLED，从一帧的数据写入到下一帧的数据写入，驱动晶体管的栅电极电压由存储电容来维持。由于晶体管存在漏电流，存储电容所存储的电压会逐渐减小，造成晶体管的栅电极电位改变，进而影响到流过有机电致发光二极管的电流，影响子像素的发光亮度。为此，通常将存储电容的容量设计得足够大来增加电压的持续时间。
但随着高分辨率(PPI)显示技术的发展，像素尺寸越来越小，布图空间缩小导致设置存储电容的空间更为紧张，严重限制了存储电容容量的增加。虽然相关技术提出了一些解决方案，但这些解决方案存在降低显示品质的缺陷。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括基底以及在所述基底上设置的多个对应不同颜色的子像素，所述每个子像素包括像素驱动电路和电连接所述像素驱动电路的有机电致发光二极管；
所述像素驱动电路包括第一晶体管，第二晶体管和存储电容，所述第一晶体管的栅电极耦接于第一扫描线，所述第一晶体管的第一极耦接于数据线，所述第一晶体管的第二极耦接于所述第二晶体管的栅电极；所述第二晶体管的第一极耦接于第一电源电压线，所述第二晶体管的第二极耦接于所述有机电致发光二极管的第一极，所述有机电致发光二极管的第二极耦接于第二电源电压线；所述存储电容的第一极与所述第二晶体管的栅电极耦接，所述存储电容的第二极与所述第二晶体管的第二极耦接，所述存储电容用于存储所述第二晶体管的栅电极的电位；
在垂直于所述基底的方向上，所述显示基板包括叠设的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层和第二金属层；
所述金属氧化物层包括第一图形、第二图形和电容图形，所述第一图形作为所述第一晶体管的有源层，所述第二图形作为所述第二晶体管的有源层，所述电容图形作为所述存储电容的第一极；
所述第一金属层包括第一极板，所述第一极板在基底上的正投影与所述电容图形在基底上的正投影至少存在第一交叠区域，以形成第一存储电容；
所述第二金属层包括第二极板，所述第二极板在基底上的正投影与所述电容图形在基底上的正投影至少存在第二交叠区域，以形成第二存储电容；
所述第一极板和第二极板的电位相同。
在一示例性的实施方式中，所述第二图形在基底上的正投影与所述第一极板在所述基底上的正投影存在交叠区域。
在一示例性的实施方式中，所述第一绝缘层与第二绝缘层之间还包括栅 绝缘层，所述栅绝缘层的厚度小于所述第二绝缘层的厚度。
在一示例性的实施方式中，所述第一绝缘层的厚度小于所述栅绝缘层和所述第二绝缘层的厚度之和。
在一示例性的实施方式中，所述第一金属层与第二金属层之间还包括栅金属层，所述第二金属层的厚度大于所述栅金属层的厚度。
在一示例性的实施方式中，所述第一晶体管的沟道宽长比小于所述第二晶体管的沟道宽长比。
在一示例性的实施方式中，所述第一电源电压线的电压大于所述第二电源电压线的电压，所述数据线的最大电压小于所述第一扫描线的最大电压，所述数据线的最大电压小于所述第一电源电压线的电压。
在一示例性的实施方式中，所述第一图形在所述基底上的正投影与所述电容图形在所述基底上的正投影间隔设置，所述第一图形在所述基底上的正投影与所述第一极板在所述基底上的正投影间隔设置。
在一示例性的实施方式中，所述第一图形和所述电容图形为一体结构。
在一示例性的实施方式中，所述像素驱动电路还包括第三晶体管，所述第三晶体管的栅电极耦接于第二扫描线，所述第三晶体管的第一极连接补偿线，所述第三晶体管的第二极耦接于所述第二晶体管的所述第二极。
在一示例性的实施方式中，所述金属氧化物层还包括第三图形，所述第三图形作为所述第三晶体管的有源层。
在一示例性的实施方式中，所述第二绝缘层覆盖所述第一扫描线、所述第二扫描线、所述第一晶体管的栅电极、所述第二晶体管的栅电极和所述第三晶体管的栅电极；且，所述第二绝缘层上分别开设有多个过孔。
在一示例性的实施方式中，所述第二金属层还包括所述数据线、所述第一电源电压线、所述第一晶体管的源电极、所述第一晶体管的漏电极、所述第二晶体管的源电极、所述第二晶体管的漏电极、所述第三晶体管的源电极、及所述第三晶体管的漏电极。
在一示例性的实施方式中，所述第一晶体管的源电极与所述数据线为一体结构，所述第二晶体管的源电极与所述第一电源电压线为一体结构，所述 第二晶体管的漏电极和所述第三晶体管的漏电极与所述第二极板为一体结构。
在一示例性的实施方式中，所述电容极板与所述第一晶体管的有源层、所述第二晶体管的有源层和所述第三晶体管的有源层同层设置、材料相同且采用同一次构图工艺形成。
在一示例性的实施方式中，所述第二极板与所述数据线、所述第一电源电压线、所述第一源电极、所述第一晶体管的漏电极、所述第二晶体管的源电极、所述第二晶体管的漏电极、所述第三晶体管的源电极、所述第三晶体管的漏电极同层设置、材料相同且采用同一次构图工艺形成。
在一示例性的实施方式中，所述金属氧化物层为单层、双层或多层。
在一示例性的实施方式中，所述金属氧化物层包括叠设的第一氧化物层和第二氧化物层，其中，所述第二氧化物层的导电性比所述第一氧化物层低，并且所述第二氧化物层的禁带宽度比所述第一氧化物层大。
在一示例性的实施方式中，所述第一氧化物层设置成靠近所述第一晶体管、第二晶体管和第三晶体管的栅电极。
另一方面，本公开还提供了一种显示装置，包括上述任意的显示基板。
本公开的其它特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本公开而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为OLED像素驱动电路的等效电路示意图；
图2a为本公开实施例显示基板一种示例性局部结构的示意图；
图2b为图2a中A-A向的剖面图；
图3a为本公开形成第一金属层图案后的示意图；
图3b为图3a中A-A向的剖面图；
图4a为本公开形成有源层和电容极板图案后的示意图；
图4b为图4a中A-A向的剖面图；
图5a为本公开形成栅电极图案后的示意图；
图5b为图5a中A-A向的剖面图；
图6a为本公开形成第二绝缘层图案后的示意图；
图6b为图6a中A-A向的剖面图；
图7a为本公开实施例显示基板另一种示例性局部结构的示意图；
图7b为图7a中A-A向的剖面图；
图8a为本公开实施例显示基板又一种示例性局部结构的示意图；
图8b为图8a中A-A向的剖面图；
图9a为本公开实施例显示基板又一种示例性局部结构的示意图；
图9b为图9a中A-A向的剖面图；
图10a为本公开实施例显示基板又一种示例性局部结构的示意图；
图10b为图10a中A-A向的剖面图；
图11为本公开实施例显示基板的整体布局图。
详述
下面，参照附图对实施方式进行说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和详细内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。应当理解，下面所描述的实施例仅用于说明和解释本公开，并 不用于限定本公开。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状 态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换称为“导电膜”。与此同样，有时可以将“绝缘膜”换称为“绝缘层”。
在本公开中，例如当导电性充分低时，有时“半导体”具有“绝缘体”的特性。此外，由于“半导体”和“绝缘体”的边界不太清晰，因此有时不能精确地区别“半导体”和“绝缘体”。由此，有时可以将本公开中的“半导体”换称为“绝缘体”。同样地，有时可以将本公开中的“绝缘体”换称为“半导体”。另外，有时可以将本公开中的“绝缘体”换称为“半绝缘体”。
在本公开中，例如当导电性充分高时，有时“半导体”具有“导电体”的特性。此外，由于“半导体”和“导电体”的边界不太其清晰，因此有时不能精确地区别“半导体”和“导电体”。由此，有时可以将本公开中的“半导体”换称为“导电体”。同样地，有时可以将本公开中的“导电体”换称为“半导体”。
在本公开中，半导体的杂质是指半导体的主要成分之外的元素。例如，浓度低于0.1atomic％的元素是杂质。如果半导体包含杂质，有可能在半导体中形成态密度(Density Of States，DOS)，载流子迁移率有可能降低，或者结晶性有可能降低。在半导体包含氧化物半导体时，作为改变半导体特性的杂质的例子，有第1族元素、第2族元素、第14族元素、第15族元素、主要成分之外的过渡金属等，作为典型例子，有氢(包含于水中)、锂、钠、硅、硼、磷、碳、氮。在氧化物半导体中，有时由于氢等杂质的混入产生氧缺陷。此外，当半导体包含硅时，作为改变半导体特性的杂质的例子，有氧、除氢之外的第1族元素、第2族元素、第13族元素、第15族元素。
目前，显示基板结构中，通常是将栅电极与源电极位置相交叠的部分充当存储电容的两个极板，栅绝缘层充当电介质，提高存储电容C ST容量通常采用提升极板的交叠面积、选择更高介电常数材料作为栅绝缘层或者降低栅绝缘层厚度等手段。但是，提升极板交叠面积的解决方案不仅与高分辨率需求相悖，而且使得设计余量(margin)减少，造成工艺难度增加，良率损失， 降低了显示品质。另外，选择更高介电常数材料作为栅绝缘层的解决方案虽然可以提升存储电容的容量，但是显示基板的其它区域，高介电常数材料对晶体管性能有较大影响，也会降低显示品质。此外，降低栅绝缘层厚度的解决方案不仅增加了工艺流程，而且与自对准掺杂工艺不兼容，同样会降低显示品质。
为了在保证显示品质的前提下有效增大存储电容容量，本公开实施例提供了一种显示基板。显示基板包括基底，在平行于基底的方向上，本公开显示基板包括在基底上设置的多个对应不同颜色的子像素，所述每个子像素包括像素驱动电路和电连接所述像素驱动电路的有机电致发光二极管OLED。
图1为本公开实施例像素驱动电路的等效电路图。如图1所示，像素驱动电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容C ST。其中，第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管。第一晶体管T1的栅电极耦接于第一扫描线Gn，第一晶体管T1的第一极耦接于数据线Dn，第一晶体管T1的第二极耦接于第二晶体管T2的栅电极，第一晶体管T1用于在第一扫描线Gn控制下，接收数据线Dn传输的数据信号，使第二晶体管T2的栅电极接收所述数据信号。第二晶体管T2的栅电极耦接于第一晶体管T1的第二极，第二晶体管T2的第一极耦接于第一电源电压线VDD，第二晶体管T2的第二极耦接于OLED的第一极，第二晶体管T2用于在其栅电极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极耦接于第二扫描线Sn，第三晶体管T3的第一极连接补偿线Se，第三晶体管T3的第二极耦接于第二晶体管T2的第二极，第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。OLED的第一极耦接于第二晶体管T2的第二极，OLED的第二极耦接于第二电源电压线VSS，OLED用于响应第二晶体管T2的第二极的电流而发出相应亮度的光。存储电容C ST的第一极与第二晶体管T2的栅电极耦接，存储电容C ST的第二极与第二晶体管T2的第二极耦接，存储电容C ST用于存储第二晶体管T2的栅电极的电位。
其中，第一电源电压线VDD的电压大于第二电源电压线VSS的电压，数据线Dn数据信号的最大电压小于第一扫描线Gn的最大电压，数据线Dn数据信号的最大电压小于第一电源电压线VDD的电压。
在垂直于基底的方向上，本公开实施例显示基板包括叠设的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层和第二金属层；所述金属氧化物层包括第一图形、第二图形和电容图形，所述第一图形作为所述第一晶体管的有源层，所述第二图形作为所述第二晶体管的有源层，所述电容图形作为所述存储电容的第一极；所述第一金属层包括第一极板，作为所述存储电容的一个第二极，所述第一极板在基底上的正投影与所述电容图形在基底上的正投影至少存在第一交叠区域，以形成第一存储电容；所述第二金属层包括第二极板，作为所述存储电容的另一个第二极，所述第二极板在基底上的正投影与所述电容图形在基底上的正投影至少存在第二交叠区域，以形成第二存储电容；所述第一极板和第二极板的电位相同，以形成并联的第一存储电容和第二存储电容。
本公开实施例提供的显示基板，通过金属氧化物层与第一金属层的第一极板和第二金属层的第二极板分别形成第一存储电容和第二存储电容，且第一极板和第二极板的电位相同，因而形成并联的第一存储电容和第二存储电容，有效增大了存储电容的容量，在不影响显示品质的前提下，有效增大存储电容的容量，且有利于实现高分辨率显示。
本公开实施例显示基板可以采用多种方式实现，下面通过实施例详细说明。
图2a为本公开实施例显示基板一种示例性局部结构的示意图，图2b为图2a中A-A向的剖面图。如图2a和图2b所示，本实施例所提供的显示基板包括：
基底10；
设置在基底10上的第一金属层，第一金属层包括第一极板11和连接线40，第一极板11作为存储电容的一个第二极，用于形成第一存储电容；
第一绝缘层12，覆盖包括第一极板11和连接线40的第一金属层；
设置在第一绝缘层12上金属氧化物层，金属氧化物层包括作为第一有源层13的第一图形、作为第二有源层23的第二图形、作为第三有源层33的第三图形和作为电容极板14的电容图形，电容极板14在基底10上的正投影与第一极板11在基底10上的正投影存在第一交叠区域，电容极板14作为存储电容的第一极，用于与第一极板11形成第一存储电容；
栅绝缘层15以及设置在栅绝缘层15上的第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36，其中，栅绝缘层15与第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36的图案相同，第一栅电极16与第一扫描线Gn为一体结构，第三栅电极36与第二扫描线Sn为一体结构；
第二绝缘层17，覆盖第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36，其上分别开设多个过孔，多个过孔包括：暴露出第一有源层13两端的第一过孔V1和第二过孔V2，暴露出第二栅电极26的第三过孔V3，暴露出电容极板14的第四过孔V4，暴露出第二有源层23两端的第五过孔V5和第六过孔V6，暴露出第一极板11的第七过孔V7，暴露出第三有源层33两端的第八过孔V8和第九过孔V9，暴露出连接线40的第十过孔V10；在一示例性的实施方式中，所述第一有源层可以是所述第一晶体管T1的有源层，所述第二有源层可以是所述第二晶体管T2的有源层，所述第三有源层可以是所述第三晶体管T3的有源层。
设置在第二绝缘层17上的第二金属层，第二金属层包括数据线Dn、第一电源电压线VDD、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39和第二极板30，第二极板30在基底10上的正投影与电容极板14在基底10上的正投影存在第二交叠区域，第二极板30作为存储电容的另一个第二极，用于与电容极板14形成第二存储电容。第一源电极18与数据线Dn为一体结构，第二源电极28与第一电源电压线VDD为一体结构，第二漏电极29和第三漏电极39与第二极板30为一体结构。第一源电极18通过第一过孔V1与第一有源层13的一端连接，第一漏电极19通过第二过孔V2与第一有源层13的另一端连接，同时，第一漏电极19通过第三过孔V3与第二栅电极26连接，第一漏电极19还通过 第四过孔V4与电容极板14连接。第二源电极28通过第五过孔V5与第二有源层23的一端连接，第二漏电极29通过第六过孔V6与第二有源层23的另一端连接。第三源电极38通过第八过孔V8与第三有源层33的一端连接，同时通过第十过孔V10与连接线40连接，第三漏电极39通过第九过孔V9与第三有源层33的另一端连接。第二极板30通过第七过孔V7与第一极板11连接，使第一极板11和第二极板30具有相同的电位。
在一示例性的实施方式中，所述第一源电极18可以是所述第一晶体管T1的源电极、第一漏电极19可以是所述第一晶体管T1的漏电极、第二源电极28可以是所述第二晶体管T2的源电极、第二漏电极29可以是所述第二晶体管T2的漏电极、第三源电极38可以是所述第三晶体管T3的源电极、第三漏电极39可以是所述第三晶体管T3的漏电极。
在一示例性的实施方式中，所述第一晶体管T1的源电极可以是所述第一晶体管T1的所述第一极或第二极，所述第一晶体管T1的漏电极可以是所述第一晶体管T1的所述第二极或第一极；所述第二晶体管T2的源电极可以是所述第二晶体管T2的所述第一极或第二极，所述第二晶体管T2的漏电极可以是所述第二晶体管T2的所述第二极或第一极；所述第三晶体管T3的源电极可以是所述第三晶体管T3的所述第一极或第二极，所述第三晶体管T3的漏电极可以是所述第三晶体管T3的所述第二极或第一极。
其中，电容极板14与第一有源层13、第二有源层23和第三有源层33同层设置、材料相同且采用同一次构图工艺形成；第二极板30与数据线Dn、第一电源电压线VDD、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39同层设置、材料相同且采用同一次构图工艺形成。
本实施例中，电容极板14作为存储电容的第一极，第一极板11作为存储电容的一个第二极，同时作为遮挡层，第二极板30作为存储电容的另一个第二极，形成二个并联的存储电容，二个并联的存储电容分别为：第一极板11与电容极板14之间的第一存储电容，第二极板30与电容极板14之间的第二存储电容。
下面通过本实施例显示基板的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
(1)形成第一金属层图案。形成第一金属层图案包括：在基底上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在基底10上形成包括第一极板11和连接线40图案的第一金属层，如图3a和图3b所示，图3b为图3a中A-A向的剖面图。本实施例中，第一极板11既作为遮挡层，又作为存储电容的一个第二极，用于形成第一存储电容。
(2)形成金属氧化物层图案。形成金属氧化物层图案包括：在形成有前述图案的基底上，依次沉积第一绝缘薄膜和金属氧化物薄膜，通过构图工艺对金属氧化物薄膜进行构图，形成覆盖第一极板11和连接线40的第一绝缘层12，以及形成在第一绝缘层12上的金属氧化物层图案，金属氧化物层包括第二有源层23、第一有源层13、第三有源层33和电容极板14图案，如图4a和图4b所示，图4b为图4a中A-A向的剖面图。其中，第一有源层13对应于第一图形，作为第一晶体管的有源层，第二有源层23对应于第二图形，作为第二晶体管的有源层，第三有源层33对应于第三图形，作为第三晶体管的有源层，电容极板14对应于电容图形，且对电容图形进行了导体化处理，作为存储电容的第一极。其中，电容极板14(电容图形)在基底10上的正投影与第一极板11在基底10上的正投影存在第一交叠区域，第一极板11作为存储电容的第二极与电容极板14形成第一存储电容。作为第二晶体管的有源层的第二有源层23(第二图形)在基底10上的正投影与第一极板11在基底10上的正投影存在交叠区域，使得作为遮挡层的第一极板11可以遮挡第二晶体管的沟道区域，避免光线对沟道产生影响，以避免沟道因生成光 生漏电而影响显示效果。本实施例中，作为第一晶体管的有源层的第一有源层13(第一图形)在基底10上的正投影与电容极板14(电容图形)在基底10上的正投影间隔设置，即两者没有交叠区域。第一有源层13(第一图形)在基底10上的正投影与第一极板11在基底10上的正投影间隔设置，即两者没有交叠区域。本实施例中，通过设计第一有源层13和第二有源层23宽度，使第一晶体管的沟道宽长比小于第二晶体管的沟道宽长比。
(3)形成栅电极图案。形成栅电极图案包括：在形成有前述图案的基底上，依次沉积栅绝缘薄膜和栅金属薄膜，通过构图工艺对栅绝缘薄膜和栅金属薄膜进行构图，形成栅绝缘层15图案以及设置在栅绝缘层15上的第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36图案，栅绝缘层15图案与第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36图案相同，第二栅电极26位于第一极板11相对应位置，第一栅电极16是与第一扫描线Gn连接的一体结构，第三栅电极36是与第二扫描线Sn连接的一体结构，如图5a和图5b所示，图5b为图5a中A-A向的剖面图。
(4)形成第二绝缘层图案。形成第二绝缘层图案包括：在形成有前述图案的基底上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成覆盖前述结构的第二绝缘层17图案，第二绝缘层17上开设有多个过孔，多个过孔分别为：暴露出第一有源层13两端的第一过孔V1和第二过孔V2，暴露出第二栅电极26的第三过孔V3，暴露出电容极板14的第四过孔V4，暴露出第二有源层23两端的第五过孔V5和第六过孔V6，暴露出第一极板11的第七过孔V7，暴露出第三有源层33两端的第八过孔V8和第九过孔V9，暴露出连接线40的第十过孔V10，如图6a和图6b所示，图6b为图6a中A-A向的剖面图。本实施例中，栅绝缘层15的厚度小于第二绝缘层17的厚度，第一绝缘层12的厚度小于栅绝缘层15和第二绝缘层17的厚度之和，在保证绝缘效果的前提下，提高存储电容的容量。
(5)形成第二金属层图案。形成第二金属层图案包括：在形成有前述图案的基底上，沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，在第二绝缘层17上形成第二金属层图案，第二金属层包括：数据线Dn、第 一电源电压线VDD、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39和第二极板30图案。其中，第一源电极18是与数据线Dn连接的一体结构，第二源电极28是与第一电源电压线VDD连接的一体结构，第二漏电极29和第三漏电极39是与第二极板30连接的一体结构。第一源电极18通过第一过孔V1与第一有源层13的一端连接，第一漏电极19通过第二过孔V2与第一有源层13的另一端连接，同时，第一漏电极19通过第三过孔V3与第二栅电极26连接，第一漏电极19还通过第四过孔V4与电容极板14连接。第二源电极28通过第五过孔V5与第二有源层23的一端连接，第二漏电极29通过第六过孔V6与第二有源层23的另一端连接。第三源电极38通过第八过孔V8与第三有源层33的一端连接，同时通过第十过孔V10与连接线40连接，第三漏电极39通过第九过孔V9与第三有源层33的另一端连接。第二极板30通过第七过孔V7与第一极板11连接，第二极板30在基底10上的正投影与电容极板14在基底10上的正投影存在第二交叠区域，作为存储电容的另一个第二极，用于与电容极板14形成第二存储电容，如图2a和图2b所示。本实施例中，第二金属层的厚度大于栅金属层的厚度。
本实施例中，第一金属层、栅金属层和第二金属层可以采用金属材料，如铬(Cr)、金(Au)、锌(Zn)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、钽(Ta)、钛(Ti)、钨(W)、锰(Mn)、镍(Ni)、铁(Fe)、钴(Co)等中的任意一种，或包含上述金属元素作为成分的合金或者包含上述金属元素的组合的合金等，如铝钕合金(AlNd)或钼铌合金(MoNb)等，可以是多层金属，如Mo/Cu/Mo等。在一示例性的实施方式中，可以采用Cu-X合金膜(其中X为Mn、Ni、Cr、Fe、Co、Mo、Ta或Ti)。通过使用Cu-X合金膜，由于可以通过湿蚀刻工序对薄膜进行加工，可以降低制造成本。在一示例性的实施方式中，采用Cu-Mn合金膜。其中，第一金属层的厚度为800至1200埃，栅金属层的厚度为3000至5000埃，第二金属层的厚度为3000至9000埃。
第一绝缘层、栅绝缘层和第二绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)等，或者可以采用氧化铝(AlOx)、氧 化铪(HfOx)、氧化钽(TaOx)、氧化钇、氧化锆、氧化镓、氧化镁、氧化镧、氧化铈或氧化钕等。其中，第一绝缘层的厚度为3000至5000埃，栅绝缘层的厚度为1000至2000埃，第二绝缘层的厚度为4500至7000埃。
本实施例中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、或者包含铟和镓和锌的氧化物等。
金属氧化物层可以是包含铟(In)的氧化物半导体，可以提高载流子迁移率(电子迁移率)。此外，氧化物半导体可以包含元素M。元素M可以是铝、镓、钇或锡等。作为可用作元素M的其他元素，有硼、硅、钛、铁、镍、锗、钇、锆、钼、镧、铈、钕、铪、钽或钨等。注意，作为元素M有时也可以组合多个上述元素。元素M例如是与氧的键能高的元素。元素M是与氧的键能高于铟的元素。或者，元素M例如是具有增大氧化物半导体的能隙的功能的元素。此外，金属氧化物层可以包含锌(Zn)，当氧化物半导体包含锌时容易晶化。在一示例性实施例中，氧化物半导体不局限于包含铟的氧化物半导体，可以是锌锡氧化物或镓锡氧化物等不包含铟且包含锌、镓或锡的氧化物半导体等。
在金属氧化物层是In-M-Zn氧化物的情况下，在In和M的总和为100atomic％时，可以是：In为低于50atomic％，M为高于50atomic％。金属氧化物层使用能隙大的氧化物，例如是2.5eV以上且4.2eV以下，或者可以为2.8eV以上且3.8eV以下，或者可以为3eV以上且3.5eV以下。在一示例性的实施方式中，金属氧化物层是包含铟(In)、M及锌(Zn)的氧化物，其中M为铝(Al)、镓(Ga)或锡(Sn)。
本实施例中，第一、第二和第三晶体管的有源层的组成可以相同或者大致相同，以降低制造成本。本实施例不局限于此，三个晶体管的有源层的组成也可以彼此不同。当三个晶体管的有源层都具有In的原子百分比大于M的原子百分比的区域时，可以提高第一晶体管和第二晶体管的场效应迁移率。例如，第一晶体管和第二晶体管的场效应迁移率中的一个或两个可以超过10cm2/Vs，例如可以是超过30cm2/Vs。例如，当将上述场效应迁移率高的晶 体管用于显示装置的生成栅极信号的栅极驱动器时，该显示装置可以具有宽度窄的边框。当将上述场效应迁移率高的晶体管用于显示装置所包括的供应来自信号线的信号的源极驱动器时，可以减少与显示装置连接的布线数。当将上述场效应迁移率高的晶体管用于显示装置所包括的像素电路的晶体管时，可以提高显示装置的显示品质。
在一示例性实施例中，本实施例的金属氧化物层可以单层，也可以是双层或多层。当金属氧化物层是双层时，包括叠设的第一氧化物层和第二氧化物层。第二氧化物层的导电性可比第一氧化物层低并且禁带宽度可比第一氧化物层大。第一氧化物层可以是电子移动的主沟道层，因而可设置成靠近第一、第二和第三栅电极。当金属氧化物层是单层时，可以采用氧化铟镓锌(IGZO)材料。
本实施例中，由于金属氧化物层一部分作为晶体管的有源层，另一部分作为存储电容的第一极，因此在进行导体化处理时，一方面可以实现不同子像素的沟道方向和形状有所区别，以适应不同的宽长比设计，例如，通过设计第一有源层和第二有源层的宽度，使第一晶体管的沟道宽长比小于第二晶体管的沟道宽长比。另一方面可以在一个子像素内的不同区域，金属氧化物层具有不同的成分含量，以适应不同的电特性需求。
前述所说的导体化处理，是在形成第一、第二和第三栅电极等图案后，利用第一、第二和第三栅电极作为掩膜进行等离子体处理，将相应区域的金属氧化物层处理成导体化层。如图4a和图5a所示，可以将金属氧化物层划分为三个区域，第一区域包括与第一、第二和第三栅电极重叠的区域，该区域作为晶体管的沟道区域，第二区域包括邻近第一区域的区域，即与第一、第二和第三栅电极邻近但未被第一、第二和第三栅电极覆盖的区域，该区域作为晶体管的源漏区域，第三区域包括与第一极板和第二极板重叠的区域，该区域作为储存电容的极板区域。本实施例中，三个区域中氧化铟镓锌(IGZO)的成分不同。
本实施例中，所述第一区域氧含量范围在30至50atomaic％之内，所述第二区域氧含量范围在50至60atomaic％之内，所述第二区域氧含量范围在60至70atomaic％之内，在一示例性的实施方式中，，第一区域中IGZO的氧 含量小于第二区域中IGZO的氧含量，第二区域中IGZO的氧含量小于第三区域中IGZO的氧含量。第一区域中IGZO的锌含量大于第二区域中IGZO的锌含量，第二区域中IGZO的锌含量大于第三区域中IGZO的锌含量，在一示例性实施例中，所述第一区域中氧元素和锌元素原子比(O/Zn)小于第二区域O/Zn，所述第二区域中O/Zn小于第三区域O/Zn。此外第一区域氧化物主要为半导体特性，提升In元素含量能显著提升载流子浓度，为提升第一区域载流子浓度以提升晶体管的驱动能力，第一区域In原子含量大于第二区域In原子含量，进而第二区域In原子含量大于第三区域In原子含量。
下表给出了三个区域中氧化铟镓锌(IGZO)成分的一种示例，Weight％代表元素在氧化物中的所占比重，Atomic％代表该元素在氧化物中所占的原子百分比。
Figure PCTCN2020102161-appb-000001
其中，第一区域为三个晶体管中的至少一个晶体管的沟道区域，第二区域为三个晶体管中的至少一个晶体管的源漏区域，第三区域为存储电容的极板区域。如上表所示，IGZO中包括氧(O)、锌(Zn)、镓(Ga)和铟(In)等元素，第一区域由于栅电极的遮挡，未经等离子体处理，多个元素O:Zn:Ga:In的重量相对含量为11.82：25.68：28.38：34.12，原子相对含量为40.24：21.40：22.18：16.18。第三区域由于未受遮挡，进行了等离子体处理，多个元素O:Zn:Ga:In的重量相对含量为23.35：18.72：25.66：32.24，原子相对 含量为60.94：11.95：15.37：11.72。通过等离子体处理后，第三区域的IGZO中氧的重量和原子含量大大增加，锌(Zn)的重量和原子含量减小，提高了IGZO的导电性。虽然第二区域未被栅电极遮挡，但由于该区域邻近栅电极，受栅电极影响，第二区域的IGZO中氧的重量和原子含量低于第三区域，锌(Zn)的重量和原子含量高于第三区域，因而第二区域的IGZO的导电性低于第三区域的IGZO。
由于第三区域的金属氧化物层作为存储电容的第一极，因而需要良好的导电特性，即需要较优的导体化程度。在采用栅电极作为掩膜进行等离子体处理时，理论上离栅电极越远的区域，其导体化程度越好，导电特性越优。因此本实施例可以设置第三区域的金属氧化物层(电容极板14)与第一栅电极16之间的最小距离大于L1，电容极板14与第二栅电极26之间的最小距离大于L2，电容极板14与第三栅电极36之间的最小距离大于L3，L1为第一栅电极16的宽度，L2为第二栅电极26的宽度，L3为第三栅电极36的宽度。这样，第三区域的金属氧化物层的等离子体处理不会受到第一栅电极16、第二栅电极26和第三栅电极36的影响，最大限度地提高第三区域的金属氧化物层的导体化程度。需要说明的是，上述距离为在垂直于基板方向上二者的距离。此外，作为一种变形实施例，由于高分辨背板设计的需要，上述第三区域的金属氧化物层(电容极板14)与第一栅电极16之间的最小距离大于L1，电容极板14与第二栅电极26之间的最小距离大于L2，以及电容极板14与第三栅电极36之间的最小距离大于L3，这三种设计可以满足其中的任意两种情况或者一种情况。在另一示例性实施例中，可以设计成先考虑电容极板14与第一电极和第二电极三者交叠的图形满足上述关系。其中，L1为第一栅电极16的宽度，L2为第二栅电极26的宽度，L3为第三栅电极36的宽度。这样，第三区域的金属氧化物层的等离子体处理受到第一栅电极16、第二栅电极26和第三栅电极36的影响较小，最大限度地提高第三区域的金属氧化物层的导体化程度。
通过本实施例显示基板的结构和制备过程可以看出，本实施例中，采用金属氧化物材料的电容极板14作为存储电容的第一极，第一金属层中的第一极板11作为存储电容的一个第二极，第二金属层中的第二极板30作为存储 电容的另一个第二极，由于第二极板30通过第七过孔V7与第一极板11连接，因此第一极板11和第二极板30具有相同的电位，而作为存储电容的第一极的电容极板14通过第三过孔V3、第一漏电极19和第四过孔V4与第二栅电极26连接，具有不同于第一极板11和第二极板30的电压，因此第一极板11、电容极板14和第二极板30之间形成二个并联的存储电容，二个并联的电容分别为：第一极板11与电容极板14之间的第一存储电容，第二极板30与电容极板14之间的第二存储电容。由于第二极板30之上还会形成透明电极层(未示出)，该透明电极层与电容极板14之间还会形成第三电容，因此本实施例实际上是形成了三个并联的存储电容。由此可见，相对于原来的结构，本公开实施例的存储电容由三个电容并联而成，最大限度地增大的存储电容的容量。由于本实施例作为存储电容的第一极的电容极板14与有源层同层设置，位于第一金属层和第二金属层之间，因此电容极板14与第一极板11之间的距离较近，仅间隔第一绝缘层12，电容极板14与第二极板30之间的距离也较近，仅间隔第二绝缘层17。由于间隔的绝缘层厚度较薄，且作为遮挡层的第一极板11的面积较大，因此本公开每个存储电容的容量均大于原有结构的存储电容的容量，即使应用于较小的像素尺寸，也能够保证所需的存储电容容量，有利于实现高分辨率显示。由于第一绝缘层12和第二绝缘层17均不需要采用高介电常数材料，也不需要降低厚度，因此本公开实施例的结构设计没有增加工艺流程，能够与自对准掺杂工艺兼容，不会影响薄膜晶体管的性能，保证了显示品质。
在一示例性实施例中，本实施例制备显示基板的构图次数与原来制备方式的构图次数相同，实施本实施例可以利用现有工艺设备，工艺兼容性好，实用性强，具有良好的应用前景。
综上所述，本实施例实现了在保证显示品质的前提下有效增大存储电容，且有利于实现高分辨率显示。
图7a为本公开实施例显示基板另一种示例性局部结构的示意图，图7b为图7a中A-A向的剖面图。本实施例包括作为存储电容的第一极的电容极板，作为遮挡层和存储电容的一个第二极的第一极板、以及作为存储电容的另一个第二极的第二极板，第一极板与电容极板之间形成第一存储电容，第 二极板与电容极板之间形成第二存储电容，第一存储电容和第二存储电容并联构成存储电容。如图7a和图7b所示，在本实施例中，电容极板14可以与第一有源层13(第一图形)为一体结构，即电容极板14和第一有源层13由连续的金属氧化物形成，取消第四过孔。例如，本实施例的显示基板包括：
基底10、第一极板11、连接线40和第一绝缘层12，结构可参见前述实施例中描述；
设置在第一绝缘层12上的金属氧化物层，金属氧化物层包括第一有源层13、第二有源层23、第三有源层33和电容极板14，第一有源层13与电容极板14为一体结构，电容极板14在基底10上的正投影与第一极板11在基底10上的正投影存在第一交叠区域，电容极板14作为存储电容的第一极，用于与第一极板11形成第一存储电容；
栅绝缘层15以及设置在栅绝缘层15上的第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36，结构可参见前述实施例中描述；
第二绝缘层17，覆盖第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36，其上分别开设多个过孔，在本实施例中取消了前述实施例中的第四过孔；或者可以理解为，前述实施例的第二过孔和第四过孔为本实施例一体结构的过孔；
设置在第二绝缘层17上的第二金属层，第二金属层包括数据线Dn、第一电源电压线VDD、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39和第二极板30，第二极板30在基底10上的正投影与电容极板14在基底10上的正投影存在第二交叠区域，第二极板30作为存储电容的另一个第二极，用于与电容极板14形成第二存储电容。第一源电极18与数据线Dn为一体结构，第二源电极28与第一电源电压线VDD为一体结构，第二漏电极29和第三漏电极39与第二极板30为一体结构。第一源电极18通过第一过孔V1与第一有源层13的一端连接，第一漏电极19通过一体结构的过孔与第一有源层13的另一端(也是电容极板14)连接，同时第一漏电极19通过第三过孔V3与第二栅电极26连接。 第二源电极28通过第五过孔V5与第二有源层23的一端连接，第二漏电极29通过第六过孔V6与第二有源层23的另一端连接。第三源电极38通过第八过孔V8与第三有源层33的一端连接，同时通过第十过孔V10与连接线40连接，第三漏电极39通过第九过孔V9与第三有源层33的另一端连接。第二极板30通过第七过孔V7与第一极板11连接。
本实施例同样可以增大存储电容的容量、有利于实现高分辨率显示、保证显示品质等。另外，本实施例通过将电容极板与第二有源层设置成一体结构，为相同的电位，因而取消了第四过孔，简化了过孔刻蚀工艺，有利于实现高分辨率设计，而且通过将原本分隔设置的电容极板和第二有源层形成一体结构，增大了电容极板的面积，进一步提升了整体存储电容的容量。
本实施例显示基板的制备过程可参见前述实施例中描述，在本实施例中，形成有源层和电容极板图案过程中，第二有源层和电容极板为一体结构；形成第二绝缘层图案过程中，不需要形成第四过孔，形成第二金属层图案过程中，第二漏电极仅通过第二过孔与第二有源层连接以及通过第三过孔与第一栅电极连接，这里不再赘述。
图8a为本公开实施例显示基板又一种示例性局部结构的示意图，图8b为图8a中A-A向的剖面图。本实施例包括作为存储电容的第一极的电容极板，作为遮挡层和存储电容的一个第二极的第一极板、以及作为存储电容的另一个第二极的第二极板，第一极板与电容极板之间形成第一存储电容，第二极板与电容极板之间形成第二存储电容，第一存储电容和第二存储电容并联构成存储电容。如图8a和图8b所示，在本实施例中，不仅可以将电容极板14与第一有源层13设置为一体结构，而且可以取消第三过孔和第四过孔，或者理解为第二过孔、第三过孔和第四过孔为一体结构。例如，本实施例的显示基板包括：
基底10、第一极板11、连接线40和第一绝缘层12，结构可参见前述实施例中描述；
设置在第一绝缘层12上的金属氧化物层，金属氧化物层包括第一有源层13、第二有源层23、第三有源层33和电容极板14，第一有源层13与电容极 板14为一体结构，电容极板14在基底10上的正投影与第一极板11在基底10上的正投影存在第一交叠区域，电容极板14作为存储电容的第一极，用于与第一极板11形成第一存储电容；
栅绝缘层15以及设置在栅绝缘层15上的第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36，栅绝缘层15与第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26、第三栅电极36图案相同，第一栅电极16是与第一扫描线Gn连接的一体结构，第三栅电极36是与第二扫描线Sn连接的一体结构，第二栅电极26为折线状；
第二绝缘层17，覆盖第一扫描线Gn、第二扫描线Sn、第一栅电极16、第二栅电极26和第三栅电极36，其上分别开设多个过孔，多个过孔包括：暴露出第一有源层13一端的第一过孔V1，同时暴露出第一有源层13另一端和第二栅电极26的第二过孔V2，暴露出第二有源层23两端的第五过孔V5和第六过孔V6，暴露出第一极板11的第七过孔V7，暴露出第三有源层33两端的第八过孔V8和第九过孔V9，暴露出连接线40的第十过孔V10；或者可以理解为，前述实施例的第二过孔、第三过孔和第四过孔为本实施例一体结构的过孔；
设置在第二绝缘层17上的第二金属层，第二金属层包括数据线Dn、第一电源电压线VDD、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39和第二极板30，第二极板30在基底10上的正投影与电容极板14在基底10上的正投影存在第二交叠区域，第二极板30作为存储电容的另一个第二极，用于与电容极板14形成第二存储电容。第一源电极18与数据线Dn为一体结构，第二源电极28与第一电源电压线VDD为一体结构，第二漏电极29和第三漏电极39与第二极板30为一体结构。第一源电极18通过第一过孔V1与第一有源层13的一端连接，第一漏电极19通过一体结构的过孔同时与第一有源层13的另一端和第二栅电极26连接。第二源电极28通过第五过孔V5与第二有源层23的一端连接，第二漏电极29通过第六过孔V6与第二有源层23的另一端连接。第三源电极38通过第八过孔V8与第三有源层33的一端连接，同时通过第十过孔V10与连接线40连接，第三漏电极39通过第九过孔V9与第三有源层33的另一 端连接。第二极板30通过第七过孔V7与第一极板11连接。
本实施例同样可以增大存储电容的容量、有利于实现高分辨率显示、保证显示品质等。另外，本实施例通过将电容极板与第二有源层设置成一体结构，为相同的电位，且取消了第三过孔和第四过孔，只保留第二过孔，第二漏电极通过第二过孔同时与第二有源层和第一栅电极连接，不仅简化了工艺，有利于实现高分辨率设计，而且通过将原本分隔设置的电容极板和第二有源层形成一体结构，增大了电容极板的面积，并增大了第二金属层的面积，进一步提升了整体存储电容的容量。
本实施例显示基板的制备过程可参见前述实施例中的描述，在本实施例中，形成有源层和电容极板图案过程中，第二有源层和电容极板为一体结构；形成第二绝缘层图案过程中，形成同时暴露出第二有源层和第一栅电极的一体结构的过孔；形成源漏电极和第二金属层图案过程中，第二漏电极通过一体结构的过孔同时与第二有源层和第一栅电极连接，这里不再赘述。
图9a为本公开实施例显示基板又一中示例性局部结构的示意图，图9b为图9a中A-A向的剖面图。如图9a和图9b所示，本实施例在第一漏电极19位置，形成有两个第二栅电极26。例如，本实施例第二栅电极26为折线状，且在第二晶体管位置形成两个第二栅电极26，第二绝缘层17上开设的一体结构的过孔同时暴露出两个第二栅电极26和第一有源层13，第一漏电极19通过一体结构的过孔同时与第一有源层13和两个第二栅电极26连接。其中，一体结构的过孔暴露出两个第二栅电极26之间区域的第一有源层13，并同时暴露出两个第二栅电极26相互邻近部分的第二栅电极26。
本实施例同样可以增大存储电容的容量、有利于实现高分辨率显示、保证了显示品质等。另外，本实施例通过设置两个第一栅电极，减小了第二过孔的尺寸，并增加了连接可靠性，进一步有利于实现高分辨率设计。
本实施例显示基板的制备过程可参见前述实施例中描述，在本实施例中，形成扫描线等图案过程中，在第二漏电极位置形成有两个第一栅电极，这里不再赘述。
图10a为本公开实施例显示基板又一中示例性局部结构的示意图，图10b 为图10a中A-A向的剖面图。如图10a和图10b所示，本实施例两个第二栅电极26的设置位置有所不同，两个第二栅电极26分别设置在第一极板11所形成的台阶处的两侧。例如，本实施例第二栅电极26为折线状，且在第二晶体管位置形成两个第二栅电极26，一个第二栅电极26位于第一极板11所形成的台阶上，另一个第二栅电极26位于台阶下，第二绝缘层17上开设的一体结构的过孔同时暴露出两个第二栅电极26以及两个第二栅电极26之间的第一有源层13，第一漏电极19通过一体结构的过孔同时与第一有源层13和两个第二栅电极26连接。
本实施例同样可以增大存储电容的容量、有利于实现高分辨率显示、保证了显示品质等。另外，本实施例通过将两个第一栅电极分别设置在第一金属层所形成的台阶处的两侧，可以有效防止第二有源层在台阶处断裂导致的失效，提升了连接的可靠性。例如，由于在台阶上及台阶下均设置有与第二漏电极连接的第一栅电极，即使第二有源层在台阶处断裂，也能够保证第二有源层与电容极板具有相同的电位。
本实施例显示基板的制备过程可参见前述实施例中描述，在本实施例中，形成扫描线等图案过程中，在第二漏电极位置形成两个第一栅电极的位置不同，这里不再赘述。
图11为本公开实施例显示基板的整体布局图。如图11所示，显示基板的第一电源电压线VDD、两条数据线Dn和补偿线Se相互平行且依次设置，第一电源电压线VDD与邻近的数据线Dn之间形成一个像素列，补偿线Se与邻近的数据线Dn之间形成另一个像素列。这样，相邻的第一电源电压线VDD之间通过设置1条补偿线Se和4条数据线Dn形成四个像素列，4条数据线Dn中两条数据线Dn位于补偿线Se的一侧，另两条数据线Dn位于补偿线Se的另一侧。同样，相邻的补偿线Se之间通过设置1条第一电源电压线VDD和4条数据线Dn也形成四个像素列，4条数据线Dn中两条数据线Dn位于第一电源电压线VDD的一侧，另两条数据线Dn位于第一电源电压线VDD的另一侧。
本公开实施例中，第一电源电压线VDD和补偿线Se均采用一拖四结构。在一示例性实施例中，显示基板还包括多条连接线40，连接线40与显示基 板的遮挡层(同时作为存储电容的第二极的第一极板)同层设置且通过同一次构图工艺形成，连接线40与第一电源电压线VDD(补偿线Se)垂直。通过过孔与第一电源电压线VDD连接的多个连接线40，分别电连接第一电源电压线VDD两侧的补偿线Se与数据线Dn之间像素列的像素，由于第一电源电压线VDD直接电连接第一电源电压线VDD两侧像素列的像素，这样一条第一电源电压线VDD能够向四列像素列的像素提供信号。同样，通过过孔与补偿线Se连接的多个连接线40，分别电连接补偿线Se两侧的第一电源电压线VDD与数据线Dn之间像素列的像素，由于补偿线Se直接电连接补偿线Se两侧像素列的像素，这样一条补偿线Se能够向四列像素列的像素提供信号。
本公开实施例显示基板通过将第一电源电压线和补偿线均设计为一拖四结构，在相同的分辨率下，有效增加了每个像素的尺寸，且具有充分利用布图空间、整体布局合理等优点。
本公开实施例还提供了一种显示装置，包括前述的显示基板。显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例的描述中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间件间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括基底以及在所述基底上设置的多个对应不同颜色的子像素，所述每个子像素包括像素驱动电路和电连接所述像素驱动电路的有机电致发光二极管；
    所述像素驱动电路包括第一晶体管，第二晶体管和存储电容，所述第一晶体管的栅电极耦接于第一扫描线，所述第一晶体管的第一极耦接于数据线，所述第一晶体管的第二极耦接于所述第二晶体管的栅电极；所述第二晶体管的第一极耦接于第一电源电压线，所述第二晶体管的第二极耦接于所述有机电致发光二极管的第一极，所述有机电致发光二极管的第二极耦接于第二电源电压线；所述存储电容的第一极与所述第二晶体管的栅电极耦接，所述存储电容的第二极与所述第二晶体管的第二极耦接，所述存储电容用于存储所述第二晶体管的栅电极的电位；
    在垂直于所述基底的方向上，所述显示基板包括叠设的第一金属层、第一绝缘层、金属氧化物层、第二绝缘层和第二金属层；
    所述金属氧化物层包括第一图形、第二图形和电容图形，所述第一图形作为所述第一晶体管的有源层，所述第二图形作为所述第二晶体管的有源层，所述电容图形作为所述存储电容的第一极；
    所述第一金属层包括第一极板，所述第一极板在基底上的正投影与所述电容图形在基底上的正投影至少存在第一交叠区域，以形成第一存储电容；
    所述第二金属层包括第二极板，所述第二极板在基底上的正投影与所述电容图形在基底上的正投影至少存在第二交叠区域，以形成第二存储电容；
    所述第一极板和第二极板的电位相同。
  2. 根据权利要求1所述的显示基板，其中，所述第二图形在基底上的正投影与所述第一极板在所述基底上的正投影存在交叠区域。
  3. 根据权利要求1所述的显示基板，所述第一绝缘层与第二绝缘层之间还包括栅绝缘层，所述栅绝缘层的厚度小于所述第二绝缘层的厚度。
  4. 根据权利要求3所述的显示基板，其中，所述第一绝缘层的厚度小于 所述栅绝缘层和所述第二绝缘层的厚度之和。
  5. 根据权利要求1所述的显示基板，所述第一金属层与第二金属层之间还包括栅金属层，所述第二金属层的厚度大于所述栅金属层的厚度。
  6. 根据权利要求1所述的显示基板，其中，所述第一晶体管的沟道宽长比小于所述第二晶体管的沟道宽长比。
  7. 根据权利要求1所述的显示基板，其中，所述第一电源电压线的电压大于所述第二电源电压线的电压，所述数据线的最大电压小于所述第一扫描线的最大电压，所述数据线的最大电压小于所述第一电源电压线的电压。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述第一图形在所述基底上的正投影与所述电容图形在所述基底上的正投影间隔设置，所述第一图形在所述基底上的正投影与所述第一极板在所述基底上的正投影间隔设置。
  9. 根据权利要求1至7中任一项所述的显示基板，其中，所述第一图形和所述电容图形为一体结构。
  10. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括第三晶体管，所述第三晶体管的栅电极耦接于第二扫描线，所述第三晶体管的第一极连接补偿线，所述第三晶体管的第二极耦接于所述第二晶体管的所述第二极。
  11. 根据权利要求10所述的显示基板，其中，所述金属氧化物层还包括第三图形，所述第三图形作为所述第三晶体管的有源层。
  12. 根据权利要求11所述的显示基板，其中，所述第二绝缘层覆盖所述第一扫描线、所述第二扫描线、所述第一晶体管的栅电极、所述第二晶体管的栅电极和所述第三晶体管的栅电极；且，所述第二绝缘层上分别开设有多个过孔。
  13. 根据权利要求12所述的显示基板，其中，所述第二金属层还包括所述数据线、所述第一电源电压线、所述第一晶体管的源电极、所述第一晶体管的漏电极、所述第二晶体管的源电极、所述第二晶体管的漏电极、所述第 三晶体管的源电极、及所述第三晶体管的漏电极。
  14. 根据权利要求13所述的显示基板，其中，所述第一晶体管的源电极与所述数据线为一体结构，所述第二晶体管的源电极与所述第一电源电压线为一体结构，所述第二晶体管的漏电极和所述第三晶体管的漏电极与所述第二极板为一体结构。
  15. 根据权利要求14所述的显示基板，其中，所述电容极板与所述第一晶体管的有源层、所述第二晶体管的有源层和所述第三晶体管的有源层同层设置、材料相同且采用同一次构图工艺形成。
  16. 根据权利要求15所述的显示基板，其中，所述第二极板与所述数据线、所述第一电源电压线、所述第一源电极、所述第一晶体管的漏电极、所述第二晶体管的源电极、所述第二晶体管的漏电极、所述第三晶体管的源电极、所述第三晶体管的漏电极同层设置、材料相同且采用同一次构图工艺形成。
  17. 根据权利要求1至16中任一项所述的显示基板，其中，所述金属氧化物层为单层、双层或多层。
  18. 根据权利要求17所述的显示基板，其中，所述金属氧化物层包括叠设的第一氧化物层和第二氧化物层，其中，所述第二氧化物层的导电性比所述第一氧化物层低，并且所述第二氧化物层的禁带宽度比所述第一氧化物层大。
  19. 根据权利要求18所述的显示基板，其中，所述第一氧化物层设置成靠近所述第一晶体管、第二晶体管和第三晶体管的栅电极。
  20. 一种显示装置，包括如权利要求1至19中任一项所述的显示基板。
PCT/CN2020/102161 2019-12-13 2020-07-15 显示基板和显示装置 WO2021114660A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/265,815 US11963420B2 (en) 2019-12-13 2020-07-15 Display substrate and display device
EP20864329.6A EP4075511A4 (en) 2019-12-13 2020-07-15 DISPLAY SUBSTRATE AND DISPLAY APPARATUS
JP2021538033A JP2023504757A (ja) 2019-12-13 2020-07-15 表示基板及び表示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201922237251.2U CN210607259U (zh) 2019-12-13 2019-12-13 显示基板和显示装置
CN201922237251.2 2019-12-13

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/265,815 A-371-Of-International US11963420B2 (en) 2019-12-13 2020-07-15 Display substrate and display device
US18/596,678 Continuation US20240215371A1 (en) 2019-12-13 2024-03-06 Display substrate and display device

Publications (1)

Publication Number Publication Date
WO2021114660A1 true WO2021114660A1 (zh) 2021-06-17

Family

ID=70696009

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/102161 WO2021114660A1 (zh) 2019-12-13 2020-07-15 显示基板和显示装置

Country Status (5)

Country Link
US (1) US11963420B2 (zh)
EP (1) EP4075511A4 (zh)
JP (1) JP2023504757A (zh)
CN (1) CN210607259U (zh)
WO (1) WO2021114660A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111564476B (zh) * 2020-05-15 2024-04-19 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN113972236A (zh) * 2020-07-23 2022-01-25 合肥鑫晟光电科技有限公司 显示基板及其制备方法、显示装置
CN112071882B (zh) * 2020-09-16 2023-07-28 合肥京东方卓印科技有限公司 显示基板及其制备方法、显示装置
CN112599010B (zh) * 2020-12-15 2022-08-09 昆山国显光电有限公司 显示面板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140097411A1 (en) * 2012-10-09 2014-04-10 Chaun-gi Choi Organic light-emitting display device and method of manufacturing the same
CN104078486A (zh) * 2013-03-26 2014-10-01 乐金显示有限公司 有机发光二极管显示装置及其制造方法
CN104576653A (zh) * 2013-10-16 2015-04-29 三星显示有限公司 薄膜晶体管阵列基板及其制造方法
CN104681585A (zh) * 2013-11-26 2015-06-03 乐金显示有限公司 有机发光二极管显示装置及其制造方法
US20160056225A1 (en) * 2014-08-19 2016-02-25 Samsung Display Co., Ltd. Organic light-emitting diode (oled) display and method of manufacturing the same
CN107452772A (zh) * 2016-05-31 2017-12-08 三星显示有限公司 有机发光显示设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2864841B2 (ja) * 1992-02-04 1999-03-08 三菱電機株式会社 高周波高出力トランジスタ
US10217416B2 (en) * 2016-07-05 2019-02-26 Innolux Corporation Display device
CN107039465A (zh) * 2017-04-28 2017-08-11 京东方科技集团股份有限公司 一种阵列基板及制备方法、显示面板和显示装置
KR102568285B1 (ko) * 2017-12-28 2023-08-17 엘지디스플레이 주식회사 유기발광표시패널 및 이를 이용한 유기발광표시장치
CN108428730B (zh) 2018-05-16 2021-01-26 京东方科技集团股份有限公司 Oled显示基板及其制作方法、显示装置
CN110098235B (zh) 2019-05-08 2021-09-24 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140097411A1 (en) * 2012-10-09 2014-04-10 Chaun-gi Choi Organic light-emitting display device and method of manufacturing the same
CN104078486A (zh) * 2013-03-26 2014-10-01 乐金显示有限公司 有机发光二极管显示装置及其制造方法
CN104576653A (zh) * 2013-10-16 2015-04-29 三星显示有限公司 薄膜晶体管阵列基板及其制造方法
CN104681585A (zh) * 2013-11-26 2015-06-03 乐金显示有限公司 有机发光二极管显示装置及其制造方法
US20160056225A1 (en) * 2014-08-19 2016-02-25 Samsung Display Co., Ltd. Organic light-emitting diode (oled) display and method of manufacturing the same
CN107452772A (zh) * 2016-05-31 2017-12-08 三星显示有限公司 有机发光显示设备

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4075511A4

Also Published As

Publication number Publication date
EP4075511A1 (en) 2022-10-19
US11963420B2 (en) 2024-04-16
EP4075511A4 (en) 2024-01-17
US20220115461A1 (en) 2022-04-14
JP2023504757A (ja) 2023-02-07
CN210607259U (zh) 2020-05-22

Similar Documents

Publication Publication Date Title
US10446711B2 (en) Thin film transistor array substrate and method for manufacturing the same
US20210257581A1 (en) Array substrate and method for manufacturing the same, display panel and display device
WO2021114660A1 (zh) 显示基板和显示装置
WO2021227744A1 (zh) 显示基板及其制备方法、显示装置
CN111179828B (zh) 显示基板及其制备方法、显示装置
WO2021023147A1 (zh) 显示基板及其制备方法、显示装置
CN109728000B (zh) 一种透明显示基板和显示面板
KR102543577B1 (ko) 트랜지스터 표시판, 그 제조 방법 및 이를 포함하는 표시 장치
US20220376001A1 (en) Oled display panel and preparation method therefor, and display apparatus
CN102738145B (zh) 显示装置和电子设备
KR20150079094A (ko) 유기전계발광표시장치 및 그 제조방법
CN110718571A (zh) 显示基板及其制备方法、显示装置
US20160336386A1 (en) Thin-film transistor substrate and method of manufacturing the thin-film transistor substrate
US10249761B2 (en) Thin-film transistor substrate
KR20080090122A (ko) 박막 트랜지스터, 이를 포함하는 유기 발광 표시 장치 및그 제조 방법
WO2022141444A1 (zh) 显示面板及显示装置
US20230157089A1 (en) Display Apparatus
CN111682031A (zh) 一种显示基板及其制备方法、显示装置
US20230029861A1 (en) Display substrate and manufacturing method therefor, and display device
US20220392987A1 (en) Display substrate and preparation method therefor, and display apparatus
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
US20220352275A1 (en) Oled display panel and method of manufacturing same
US11984070B2 (en) Display substrate and display device
US10879329B2 (en) Semiconductor device, semiconductor substrate, luminescent unit, and display unit
US20240215371A1 (en) Display substrate and display device

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2021538033

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20864329

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2020864329

Country of ref document: EP

Effective date: 20220713