WO2021023147A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2021023147A1
WO2021023147A1 PCT/CN2020/106544 CN2020106544W WO2021023147A1 WO 2021023147 A1 WO2021023147 A1 WO 2021023147A1 CN 2020106544 W CN2020106544 W CN 2020106544W WO 2021023147 A1 WO2021023147 A1 WO 2021023147A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
pixel
sub
insulating layer
layer
Prior art date
Application number
PCT/CN2020/106544
Other languages
English (en)
French (fr)
Inventor
宋振
王国英
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/288,571 priority Critical patent/US20210391402A1/en
Publication of WO2021023147A1 publication Critical patent/WO2021023147A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • PM passive matrix
  • AM active matrix
  • TFT Thin Film Transistor
  • a display substrate including a plurality of sub-pixels arranged in a matrix, each sub-pixel is provided with a pixel driving circuit including a plurality of thin film transistors and a storage capacitor, and among the plurality of sub-pixels
  • the storage capacitor of the sub-pixel and the storage capacitor of the adjacent sub-pixel adjacent to the sub-pixel are arranged in the common capacitor area of the sub-pixel and the adjacent sub-pixel, and the storage capacitor of the sub-pixel and the phase
  • the storage capacitors of adjacent sub-pixels are stacked.
  • the storage capacitor of the sub-pixel includes: a first electrode provided on the same layer as the light shielding layer in the pixel driving circuit, an insulating layer covering the first electrode, and The gate electrode of the thin film transistor is the second electrode arranged in the same layer.
  • the storage capacitors of the adjacent sub-pixels include: a third electrode provided in the same layer as the source and drain electrodes of the thin film transistor, an insulating layer covering the third electrode, The fourth electrode is provided on the same layer as the pixel electrode.
  • the pixel driving circuit includes: a substrate; a light shielding layer and a first electrode provided on the substrate, the first electrode being provided in the common capacitor region; The light-shielding layer and the first insulating layer of the first electrode; the active layer arranged on the first insulating layer; the second insulating layer covering the active layer; the gate arranged on the second insulating layer An electrode and a second electrode, the second electrode is arranged in the common capacitor area, and the first electrode and the second electrode form a storage capacitor of the sub-pixel.
  • the pixel driving circuit further includes: a third insulating layer covering the gate electrode and the second electrode; source and drain electrodes provided on the third insulating layer And a third electrode, the third electrode is arranged on the common capacitance area; a fourth insulating layer and a fifth insulating layer covering the source electrode, the drain electrode and the third electrode; arranged on the fifth insulating layer
  • the fourth electrode is arranged in the common capacitor area, and the third electrode and the fourth electrode form a storage capacitor of adjacent sub-pixels.
  • the plurality of thin film transistors includes a first thin film transistor, a second thin film transistor, and a third thin film transistor
  • the first thin film transistor includes a first active layer, a first gate Electrode, a first source electrode and a first drain electrode
  • the second thin film transistor includes a second active layer, a second gate electrode, a second source electrode and a second drain electrode
  • the third thin film transistor includes a third The source layer, the third gate electrode, the third source electrode and the third drain electrode.
  • the first electrode and the light-shielding layer have an integral structure, and the first electrode connects the first drain electrode and the light-shielding layer through a via hole.
  • the third drain electrode; the second electrode and the first gate electrode are an integral structure, and the second electrode is connected to the second drain electrode through a via hole.
  • the third electrode connects the first gate electrode and the second drain electrode through a via hole, and the fourth electrode is connected to the
  • the pixel electrode has an integral structure, and the fourth electrode is connected to the first drain electrode and the third drain electrode through a via hole.
  • the display substrate according to any one of the foregoing embodiments further includes a color filter layer, the color filter layer is disposed between the fourth insulating layer and the fifth insulating layer, and the fifth insulating layer is provided with exposing the fourth insulating layer.
  • the fourth electrode is arranged in the via hole.
  • the pixel driving circuit further includes a switch scan line, a compensation scan line, and a data line.
  • the shared capacitor area is arranged between the two data lines.
  • the shared capacitance area is arranged between the switch scan line and the compensation scan line.
  • a display device including the display substrate of any one of the foregoing embodiments.
  • a method for manufacturing a display substrate including: forming a plurality of sub-pixels arranged in a matrix, and forming a pixel driving circuit including a plurality of thin film transistors and a storage capacitor in each sub-pixel, wherein, The storage capacitor of the sub-pixel of the plurality of sub-pixels and the storage capacitor of the adjacent sub-pixel adjacent to the sub-pixel are formed in the common capacitor area of the sub-pixel and the adjacent sub-pixel. The storage capacitor of the adjacent sub-pixel and the storage capacitor of the adjacent sub-pixel are stacked.
  • the storage capacitor of the sub-pixel is formed in the common capacitor area, including: forming a first electrode arranged in the same layer as the light shielding layer in the pixel driving circuit , The first electrode is formed in the common capacitor region; an insulating layer covering the first electrode is formed; a second electrode arranged in the same layer as the gate electrode of the thin film transistor is formed, and the second electrode is formed in the common Capacitance area.
  • the storage capacitors of the adjacent sub-pixels are formed in the common capacitor area, including: forming a third layer disposed on the same layer as the source and drain electrodes of the thin film transistor. An electrode, the third electrode is formed in the common capacitor area; an insulating layer covering the third electrode is formed; a fourth electrode is formed in the same layer as the pixel electrode, and the fourth electrode is formed in the common capacitor area .
  • forming a pixel driving circuit includes: forming a light shielding layer and a first electrode on a substrate, the first electrode being formed in the common capacitor region; The light shielding layer and the first insulating layer of the first electrode; forming an active layer on the first insulating layer; forming a second insulating layer covering the active layer; forming a gate electrode on the second insulating layer And a second electrode, the second electrode is formed in the common capacitor area, and the first electrode and the second electrode form the storage capacitor of the sub-pixel.
  • forming a pixel driving circuit further includes: forming a third insulating layer covering the gate electrode and the second electrode; and forming a source on the third insulating layer.
  • An electrode, a drain electrode, and a third electrode, the third electrode is formed in the common capacitance region; a fourth insulating layer and a fifth insulating layer are formed to cover the source electrode, the drain electrode, and the third electrode;
  • a pixel electrode and a fourth electrode are formed on the five insulating layers, the fourth electrode is formed in the common capacitor area, and the third electrode and the fourth electrode form a storage capacitor of adjacent sub-pixels.
  • the forming the light-shielding layer and the first electrode on the substrate includes: forming the light-shielding layer of the sub-pixel and the light-shielding layer of the adjacent sub-pixel on the substrate, and the light-shielding layer of the sub-pixel and the first electrode have an integral structure;
  • the forming the gate electrode and the second electrode on the second insulating layer includes: forming the first gate electrode, the second gate electrode and the third gate electrode of the sub-pixel on the second insulating layer, and the adjacent sub-pixels.
  • the first gate electrode, the second gate electrode and the third gate electrode of the pixel, and the first gate electrode and the second electrode of the sub-pixel have an integral structure;
  • the forming the pixel electrode and the fourth electrode on the fifth insulating layer includes: forming the pixel electrode of the sub-pixel and the pixel electrode of the adjacent sub-pixel on the fifth insulating layer, and the pixel of the adjacent sub-pixel
  • the electrode and the fourth electrode have an integral structure, and the pixel electrodes of the adjacent sub-pixels are connected to the first drain electrode and the third drain electrode of the adjacent sub-pixels through via holes.
  • the forming a source electrode, a drain electrode, and a third electrode on the third insulating layer includes: forming a data line on the third insulating layer , Compensation line, first source electrode, first drain electrode, second source electrode, second drain electrode, third source electrode, third drain electrode, and third electrode.
  • the compensation line is connected to the connection line through a via;
  • the first source electrode is connected to the first active layer through a via, and the first The drain electrode is simultaneously connected to the first active layer and the light-shielding layer through the via hole, so that the first drain electrode of the sub-pixel is connected to the first electrode;
  • the second source electrode and the data line are in an integrated structure, and the second source electrode passes through
  • the via hole is connected to the second active layer, and the second drain electrode is simultaneously connected to the second active layer and the first gate electrode through the via hole, so that the second drain electrode of the sub-pixel is connected to the second electrode;
  • the third The source electrode is simultaneously connected to the connection line and the third active layer through the via hole, and the third drain electrode is simultaneously connected to the third active layer and the light shielding layer through the via hole, so that the third drain electrode of the sub-pixel is connected to the first electrode ;
  • the third electrode is connected to the first gate electrode of an adjacent sub
  • the forming the fourth insulating layer and the fifth insulating layer covering the source electrode, the drain electrode, and the third electrode includes: The fourth insulating layer of the electrode, the drain electrode, and the third electrode; forming a color filter layer on the fourth insulating layer; forming a fifth insulating layer covering the color filter layer, and forming an exposed layer on the fifth insulating layer A via hole of the fourth insulating layer, where the via hole is used to arrange the fourth electrode.
  • FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit
  • FIG. 2 is a schematic diagram of the structure of a sub-pixel in a bottom emission type OLED
  • FIG. 3 is a schematic diagram showing that two sub-pixels on a substrate share a capacitor area in an embodiment of the disclosure
  • FIG. 4 is a schematic diagram showing a stacked arrangement of two sub-pixel storage capacitors on a substrate according to an embodiment of the disclosure
  • FIG. 5 is a schematic structural diagram of an exemplary embodiment of a display substrate of the present disclosure.
  • Figure 6 is a cross-sectional view taken along the line A-A in Figure 5;
  • FIG. 7 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after the light shielding layer and the first electrode pattern are formed;
  • Fig. 8 is a sectional view taken along the line A-A in Fig. 7;
  • FIG. 9 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after an active layer pattern is formed;
  • Fig. 10 is a sectional view taken along the line A-A in Fig. 9;
  • FIG. 11 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after forming gate electrode and second electrode patterns
  • Figure 12 is a cross-sectional view along the A-A direction in Figure 11;
  • FIG. 13 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after a third insulating layer pattern is formed;
  • Figure 14 is a cross-sectional view taken along the line A-A in Figure 13;
  • FIG. 15 is a schematic diagram of the embodiment shown in FIG. 5 of the present disclosure after source and drain electrodes and third electrode patterns are formed;
  • Figure 16 is a cross-sectional view taken along the line A-A in Figure 15;
  • FIG. 17 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after forming a fifth insulating layer pattern
  • Figure 18 is a cross-sectional view taken along the line A-A in Figure 17;
  • FIG. 19 is a schematic diagram of the embodiment shown in FIG. 5 of the present disclosure after the pixel electrode and the fourth electrode pattern are formed;
  • Figure 20 is a cross-sectional view taken along the line A-A in Figure 19;
  • 21 is a schematic diagram of an equivalent circuit of the left sub-pixel of the embodiment shown in FIG. 5 of the disclosure.
  • FIG. 22 is a schematic diagram of an equivalent circuit of the sub-pixel on the right side of the embodiment shown in FIG. 5 of the present disclosure.
  • FIG. 23 is a schematic diagram of pixel arrangement of the embodiment shown in FIG. 5 of the present disclosure.
  • FIG. 24 is a schematic structural diagram of another exemplary embodiment of a display substrate of the present disclosure.
  • GN switch scan line
  • SN compensation scan line
  • LN Connecting line
  • DN Data line
  • SE Compensation line
  • the pixel aperture ratio is one of the parameters and also a factor for improving the resolution of the display device, for example, for bottom emission OLEDs.
  • the bottom emission type OLED has a light-emitting area and a driving circuit area in each sub-pixel.
  • the light-emitting structure is arranged in the light-emitting area.
  • Multiple TFTs and storage capacitors (C ST ) are arranged in parallel in the driving circuit area.
  • the storage capacitor usually occupies a larger area.
  • the size of sub-pixels is getting smaller and smaller, so that the proportion of the pixel area occupied by the driving circuit area is getting larger and larger, resulting in a significant reduction in pixel aperture ratio.
  • the pixel aperture ratio is usually about 40%, and when the above structure is applied to a high PPI, the pixel aperture ratio is 10%-20%. Practical use shows that low pixel aperture ratio may cause problems such as increased power consumption and attenuation of the life of luminescent materials.
  • FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit, which illustrates a 3T1C driving structure.
  • the pixel driving circuit is electrically connected to the switching scan line GN, the compensation scan line SN, the data line DN, the power supply line VDD, and the compensation line SE.
  • the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C ST .
  • the first transistor T1 may be a driving transistor
  • the second transistor T2 may be a switching transistor
  • the third transistor T3 may be a compensation transistor.
  • the gate electrode of the first transistor T1 is connected to the second electrode of the second transistor T2 and the first electrode of the storage capacitor C ST , the first electrode of the first transistor T1 is connected to the first power line VDD, and the first transistor T1 The second electrode of is connected to the second electrode of the storage capacitor C ST and the second electrode of the third transistor T3.
  • the gate electrode of the second transistor T2 is connected to the scan line GN
  • the first electrode of the second transistor T2 is connected to the data line DN
  • the gate electrode of the third transistor T3 is connected to the compensation scan line SN
  • the first electrode of the third transistor T3 The pole is connected to the compensation line SE.
  • the anode of the OLED is connected to the second electrode of the first transistor T1
  • the cathode of the OLED is connected to the low voltage line VSS, and is configured to emit light of corresponding brightness in response to the current of the second electrode of the first transistor T1.
  • the third transistor T3 can extract the threshold voltage Vth and mobility of the first transistor T1 in response to the timing of compensation to compensate the threshold voltage Vth, and the storage capacitor C ST is used to maintain the N1 node and the N2 node in a frame of light emission period. Voltage, so higher storage capacity is required.
  • FIG. 2 is a schematic diagram of the structure of a sub-pixel in a bottom emission type OLED.
  • each sub-pixel is provided with a light-emitting area and a driving circuit area.
  • the driving circuit area includes a TFT area and a capacitor area.
  • the light-emitting structure is arranged in the light-emitting area.
  • a plurality of TFTs driving the light-emitting structure are arranged in the TFT area.
  • the electrode plates are arranged in the capacitor area, and the electrode plates of a plurality of TFTs and storage capacitors are arranged side by side.
  • the storage capacitor is composed of a shielding layer and a conductive active layer as the two electrode plates of the storage capacitor.
  • the electrode plate needs a large area, that is, the capacitor area occupies a large area. Therefore, when the above structure is applied to high PPI, the pixel aperture ratio is very low.
  • embodiments of the present disclosure provide a display substrate.
  • the display substrate of the embodiment of the present disclosure includes a plurality of sub-pixels arranged in a matrix, and each sub-pixel is provided with a pixel driving circuit including a plurality of thin film transistors and a storage capacitor.
  • the storage capacitor of the sub-pixel pixel driving circuit and the adjacent sub-pixel pixel driving circuit The storage capacitor is arranged in the common capacitance area of the two sub-pixels, and the storage capacitor of the pixel driving circuit of the sub-pixel and the storage capacitor of the adjacent sub-pixel pixel driving circuit are stacked.
  • FIG. 3 is a schematic diagram showing that two sub-pixels share a capacitor area on a substrate according to an embodiment of the disclosure
  • FIG. 4 is a schematic diagram showing that two sub-pixel storage capacitors are stacked on a substrate according to an embodiment of the disclosure.
  • the two sub-pixels are the current sub-pixel and adjacent sub-pixels.
  • Each sub-pixel is provided with a light-emitting area and a TFT area.
  • the capacitor areas of the two sub-pixels together form a common capacitor area, which constitutes the electrode of each sub-pixel storage capacitor.
  • the boards are all arranged in the shared capacitance area.
  • the electrode plate constituting the storage capacitor of the sub-pixel pixel driving circuit includes a first electrode and a second electrode.
  • the first electrode and the light shielding layer are provided in the same layer, and the second electrode is provided in the same layer as the gate electrode of the thin film transistor.
  • the first electrode and the second electrode are arranged in the common capacitance area of the two sub-pixels.
  • the electrode plates constituting the storage capacitor of the adjacent sub-pixel pixel driving circuit include a third electrode and a fourth electrode.
  • the third electrode is arranged in the same layer as the source and drain electrodes of the thin film transistor, the fourth electrode is arranged in the same layer as the pixel electrode, and the third electrode is arranged in the same layer as the pixel electrode.
  • the fourth electrode are arranged in the common capacitance area of the two sub-pixels.
  • the embodiment of the present disclosure proposes a display substrate, which realizes sharing of capacitor regions and stacking of storage capacitors by using a laminated structure in the display substrate.
  • the present disclosure combines the capacitor regions of two adjacent sub-pixels as a shared capacitor region of the two sub-pixels.
  • the electrode plates constituting the storage capacitor of each sub-pixel are arranged in the shared capacitor region, so that the storage capacitors of the two sub-pixels form a stack.
  • the structure greatly reduces the area of each sub-pixel capacitance area, reduces the proportion of the pixel area occupied by the driving circuit area, effectively improves the pixel aperture ratio, is suitable for high PPI display, and reduces power consumption.
  • FIG. 5 is a schematic structural diagram of an exemplary embodiment of the display substrate of the present disclosure.
  • FIG. 6 is a cross-sectional view along the A-A direction in FIG. 5, illustrating the structure of two adjacent sub-pixels of the bottom emission display substrate.
  • the two adjacent sub-pixels may be a red sub-pixel and a green sub-pixel, or may be a blue sub-pixel and a green sub-pixel, or may be a red sub-pixel and a blue sub-pixel.
  • the left sub-pixel in FIG. 5 refers to the current sub-pixel
  • the right sub-pixel in FIG. 5 refers to the adjacent sub-pixel.
  • the display substrate provided by this embodiment may include:
  • the light-shielding layer 11 and the first electrode 12 are arranged on the substrate 10; wherein the first electrode 12 is arranged in the common capacitance area of the two sub-pixels, each sub-pixel is provided with a light-shielding layer 11, and the light-shielding layer 11 of the left sub-pixel It is connected to the first electrode 12 and has an integrated structure, and the light shielding layer 11 of the right sub-pixel is separately provided;
  • the first insulating layer 13 covers the light shielding layer 11 and the first electrode 12;
  • the first active layer 14, the second active layer 24, and the third active layer 34 are arranged on the first insulating layer 13; wherein the two sub-pixels are both provided with the first active layer 14, the second active layer 24 and the third active layer 34;
  • the second gate electrode 26 of the two sub-pixels is integrated with the switching scan line GN
  • the third gate electrode 36 is integrated with the compensation scan line SN
  • the first gate electrode 16 and the second electrode 17 of the left sub-pixel Connected and integrated structure, the first gate electrode 16 of the right sub-pixel is separately arranged;
  • the third insulating layer 20 covers the switching scan line GN, the compensation scan line SN, the connecting line LN, the first gate electrode 16, the second gate electrode 26, the third gate electrode 36 and the second electrode 17, and a plurality of Via holes
  • multiple via holes include: the first via hole V1 in the two sub-pixels exposing the first gate electrode 16 and the second active layer 24 at the same time, and the second via hole in the right sub-pixel exposing the first gate electrode 16 Via V2, the third via V3 and the fourth via V4 at both ends of the first active layer 14 are exposed in the two sub-pixels, and the fifth via V5 of the second active layer 24 is exposed in the two sub-pixels.
  • the connecting line LN and the sixth via hole V6 of the third active layer 34 are exposed in each sub-pixel, the seventh via hole V7 of the third active layer 34 is exposed in two sub-pixels, and the light shielding layer is exposed in two sub-pixels
  • the eighth via V8 and the ninth via V9 of 11, the tenth via V10 of the connection line LN is exposed in the right sub-pixel; wherein, the first via V1 and the sixth via V6 are both double connection holes,
  • the first via hole V1 simultaneously exposes the first gate electrode 16 and the second active layer 24, and the sixth via hole V6 simultaneously exposes the connecting line LN and the third active layer 34;
  • the data line DN, the compensation line SE, the first source electrode 18, the first drain electrode 19, the second source electrode 28, the second drain electrode 29, the third source electrode 38, the third drain electrode 39 and the third electrode 30 are arranged On the third insulating layer 20, the first source electrode 18 of the two sub-pixels is connected to the first active layer 14 through the fourth via hole V4, and the first drain electrode 19 is connected to the first active layer 14 through the third via hole V3.
  • the second source electrode 28 of the two sub-pixels is integrated with the data line DN, and is connected to the second active layer 24 through the fifth via V5, and the second leakage
  • the pole 29 is simultaneously connected to the second active layer 24 and the first gate electrode 16 through the first via hole V1; the third source electrode 38 of the two sub-pixels is simultaneously connected to the connecting line LN and the third active layer through the sixth via hole V6. 34.
  • the third drain electrode 39 is connected to the third active layer 34 through the seventh via hole V7, and is also connected to the light shielding layer 11 through the eighth via hole V8; the third electrode 30 is arranged in the common capacitance area of the two sub-pixels, It is connected to the first gate electrode 16 of the right sub-pixel through the second via hole V2; the compensation line SE is connected to the connection line LN through the tenth via hole V10;
  • the fourth insulating layer 31 and the fifth insulating layer 33 cover the aforementioned structure, on which are formed an eleventh via V10 and a twelfth via V11, and the eleventh via V11 is located at the third drain electrode in the two sub-pixels Position 39 exposes the surface of the third drain electrode 39, and the twelfth via V12 is located at the position of the third electrode 30, exposing the surface of the fourth insulating layer 31;
  • the pixel electrode 40 and the fourth electrode 35 are arranged on the fifth insulating layer 33.
  • the pixel electrodes 40 of the two sub-pixels are connected to the third drain electrode 39 through the eleventh via hole V11.
  • the fourth electrode 35 is arranged on the two sub-pixels.
  • the common capacitor area is located in the twelfth via hole V12 and is an integral structure with the pixel electrode 40 of the right sub-pixel.
  • the first electrode and the second electrode are arranged in the common capacitor area of the two sub-pixels to form the storage capacitor of the left sub-pixel
  • the third electrode and the fourth electrode are arranged in the common capacitor area of the two sub-pixels to form the right
  • the storage capacitor of the side sub-pixel and the storage capacitor of the left sub-pixel are located under the storage capacitor of the right sub-pixel, forming a stacked structure of the storage capacitor of the left sub-pixel and the storage capacitor of the right sub-pixel.
  • the technical solution of this embodiment is further described below through the preparation process of the display substrate of this embodiment.
  • the "patterning process” mentioned in this embodiment includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are some preparation processes.
  • the deposition may use sputtering, evaporation, chemical vapor deposition and other processes, and the coating may use a coating process, which is not limited here.
  • “thin film” refers to a layer of film made by depositing a certain material on a substrate or by other processes. If the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” needs a patterning process during the entire production process, it is called a "thin film” before the patterning process and a "layer” after the patterning process.
  • the "layer” after the patterning process contains at least one "pattern”.
  • Forming the light shielding layer and the first electrode pattern includes: depositing a first metal film on a substrate, patterning the first metal film through a patterning process, and forming a light shielding layer 11 and a first electrode 12 pattern on the substrate 10, as shown in FIGS. 7 and As shown in Fig. 8, Fig. 8 is a cross-sectional view taken along the line AA in Fig. 7.
  • each sub-pixel is provided with a light-shielding layer 11, and the first electrode 12 is provided in the common capacitance area of the two sub-pixels, that is, the first electrode 12 is provided between the two light-shielding layers 11, and the The light shielding layer 11 and the first electrode 12 are connected to form an integral structure.
  • the first electrode 12 in this embodiment is used to form the bottom electrode plate of the storage capacitor of the left sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the first electrode 12 occupies the capacitance of the left sub-pixel. Area and the capacitance area of the right sub-pixel.
  • the storage capacitor of the left sub-pixel is called the first storage capacitor.
  • the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum niobium alloy (AlNd), molybdenum niobium Alloy (MoNb), etc., can be a multilayer metal, such as Mo/Cu/Mo, etc., or a stack structure formed by metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc.
  • alloy materials of the foregoing metals such as aluminum niobium alloy (AlNd), molybdenum niobium Alloy (MoNb), etc.
  • AlNd aluminum niobium alloy
  • MoNb molybdenum niobium Alloy
  • Forming the pattern of the active layer includes: sequentially depositing a first insulating film and an active film on the substrate on which the aforementioned pattern is formed, and patterning the active film through a patterning process to form a covering light shielding layer 11 and a first electrode 12
  • the pattern of the first insulating layer 13, and the first active layer 14, the second active layer 24, and the third active layer 34 formed on the first insulating layer 13, as shown in FIGS. 9 and 10, 10 is a cross-sectional view in the AA direction in FIG. 9. Wherein, the first active layer 14, the second active layer 24, and the third active layer 34 are formed in the two sub-pixels.
  • the first active layer 14 serves as the active layer of the driving TFT (the first transistor T1)
  • the second active layer 24 serves as an active layer of the switching TFT (second transistor T2)
  • the third active layer 34 serves as an active layer of the compensation TFT (third transistor T3).
  • the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si)
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polysilicon
  • Various materials such as hexathiophene or polythiophene, that is, this embodiment is also applicable to display substrates based on top gate TFTs manufactured based on oxide (Oxide) technology, silicon technology
  • the first insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or can be made of high-dielectric constant High-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx) ), tantalum oxide (TaOx), etc., can be single layer, multiple layers or composite layers. Generally, the first insulating layer 13 is referred to as a buffer layer.
  • Forming the gate electrode and the second electrode pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate with the aforementioned pattern, first coating a layer of photoresist on the second metal film, passing through a mask, Exposure and development to form a photoresist pattern, use an etching process to etch the second metal film, and then use the second metal film as a mask to self-align and etch the second insulating film downward to form a pattern of the second insulating layer 15, and The pattern of the switch scan line GN, the compensation scan line SN, the connection line LN, the first gate electrode 16, the second gate electrode 26, the third gate electrode 36 and the second electrode 17 arranged on the second insulating layer 15, as shown in FIG.
  • Fig. 12 is a cross-sectional view taken along the line AA in Fig. 11. Subsequently, the exposed first active layer 14, the second active layer 24, and the third active layer 34 are subjected to a conductive treatment using the scan line and the gate electrode pattern as a mask.
  • the second electrode 17 is arranged in the common capacitance area of the two sub-pixels, and is arranged between the first gate electrodes 16 of the two sub-pixels, and its position corresponds to the position of the first electrode 12, that is, the second electrode 17
  • the orthographic projection on the substrate is within the orthographic projection range of the first electrode 12 on the substrate.
  • the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 are provided in the two sub-pixels.
  • the second gate electrode 26 of the two sub-pixels is an integrated structure connected with the switch scan line GN.
  • the tri-gate electrode 36 is an integral structure connected to the compensation scan line SN.
  • the first gate electrode 16 and the second electrode 17 in the left sub-pixel are connected to form an integral structure.
  • the second electrode 17 in this embodiment is used to form the upper electrode plate of the storage capacitor of the left sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the second electrode 17 occupies the capacitance of the left sub-pixel. Area and the capacitance area of the right sub-pixel.
  • the switching scan line GN is used to provide the second gate electrode 26 of the two sub-pixels with an on/off signal to control the switching TFT
  • the compensation scan line SN is used to provide the third gate electrode 36 of the two sub-pixels with a control to turn on/off the compensation TFT.
  • the signal connection line LN serves as the source electrode of the compensation TFT in the two sub-pixels, and will be connected to the compensation line SE formed later.
  • the common capacitance area of the two sub-pixels is arranged between the switching scan line GN and the compensation scan line SN.
  • the second metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum-niobium alloy (AlNd, molybdenum-niobium alloy) (MoNb), etc., can be a multilayer metal, such as Mo/Cu/Mo, etc., or a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • the second insulating film can be silicon oxide ( SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.
  • High k materials can also be used, such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., which can be a single layer, Multi-layer or composite layer.
  • AlOx aluminum oxide
  • HfOx hafnium oxide
  • TaOx tantalum oxide
  • the second insulating layer 15 is called a gate insulating (GI) layer.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate formed with the aforementioned pattern, and patterning the third insulating film through a patterning process to form a pattern of the third insulating layer 20 covering the aforementioned structure.
  • the third insulating layer A plurality of via holes are opened on 20, and the plurality of via holes are respectively: a first via hole V1 formed in the two sub-pixels that simultaneously exposes the first gate electrode 16 and the second active layer 24, and is formed in the right sub-pixel
  • the second via hole V2 exposing the first gate electrode 16, the third via hole V3 and the fourth via hole V4 formed in the two sub-pixels exposing both ends of the first active layer 14, the exposed portion formed in the two sub-pixels
  • the fifth via hole V5 of the second active layer 24 is formed, and the connecting line LN and the sixth via hole V6 of the third active layer 34 are exposed at the same time when the two sub-pixels are formed.
  • the via hole V10 is shown in FIG. 13 and FIG. 14, and FIG. 14 is a cross-sectional view along the AA direction in FIG. 13.
  • the first via hole V1 formed in the two sub-pixels is a via hole exposing the first gate electrode 16 and the second active layer 24 at the same time.
  • the via via hole is composed of two half holes, and one half hole is exposed. The first gate electrode 16 is exposed, and the second active layer 24 is exposed by the other half hole.
  • the sixth via hole V6 in the two sub-pixels is a via hole that simultaneously exposes the connecting line LN and the third active layer 34. One half hole exposes the connecting line LN, and the other half hole exposes the third active layer. 34. Setting the first via hole V1 and the sixth via hole V6 as transfer via holes can reduce the occupied area of the driving circuit area and increase the aperture ratio.
  • the third insulating layer 20 can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and can also be made of high-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx) , Tantalum Oxide (TaOx), etc., can be single layer, multilayer or composite layer.
  • the third insulating layer 20 is referred to as an interlayer insulation (ILD) layer.
  • ILD interlayer insulation
  • Forming the source and drain electrodes and the third electrode pattern includes: depositing a third metal film on the substrate with the aforementioned pattern, patterning the third metal film through a patterning process, and forming a power supply line (not shown) on the third insulating layer 20 Out), data line DN, compensation line SE, first source electrode 18, first drain electrode 19, second source electrode 28, second drain electrode 29, third source electrode 38, third drain electrode 39, and third electrode 30 pattern, as shown in FIG. 15 and FIG. 16, FIG. 16 is a cross-sectional view in the AA direction in FIG. among them,
  • the data line DN is arranged outside the two sub-pixels, so that the common capacitance area of the two sub-pixels is located between the two data lines DN.
  • Each data line DN provides a data signal for the switching TFT of the adjacent sub-pixel, and the compensation line SE is arranged on the data line.
  • the outer side of the line DN is connected to the connection line LN through the tenth via V10 to provide compensation signals for the compensation TFTs of the two sub-pixels between the two data lines DN.
  • the first source electrode 18 of the two sub-pixels is an integrated structure connected with a power supply line (not shown), and the first source electrode 18 of each sub-pixel passes through the fourth via hole V4 and is connected to the first active layer 14 of the sub-pixel.
  • One end is connected, the first drain electrode 19 of each sub-pixel is connected to the other end of the first active layer 14 of the sub-pixel through the third via hole V3 on the one hand, and is connected to the sub-pixel through the ninth via hole V9 on the other hand.
  • the light shielding layer 11 is connected.
  • the first drain electrode 19 of the left sub-pixel is connected to the first electrode 12, that is, the first drain electrode of the left sub-pixel 19 is connected to the bottom electrode plate forming the first storage capacitor, and the first drain electrode 19 and the first electrode 12 in the left sub-pixel have the same potential.
  • the second source electrode 28 of each sub-pixel is an integral structure connected to the data line DN of the sub-pixel, and the second source electrode 28 of each sub-pixel passes through the fifth via hole V5 and is connected to the second active layer 24 of the sub-pixel.
  • One end is connected, the second drain electrode 29 of each sub-pixel is connected to the other end of the second active layer 24 of the sub-pixel on the one hand through the first via hole V1, and to the first gate electrode 16 of the sub-pixel on the other hand. Connection, that is, the second drain electrode 29 is simultaneously connected to the second active layer 24 and the first gate electrode 16 through the first via V1.
  • the second drain electrode 29 of the left sub-pixel is connected to the second electrode 17, that is, the second The drain electrode 29 is connected to the upper plate forming the first storage capacitor, and the potentials of the first gate electrode 16, the second drain electrode 29 and the second electrode 17 of the left sub-pixel are the same.
  • the third source electrode 38 of each sub-pixel is connected to the connecting line LN on the one hand through the sixth via hole V6, and is connected to one end of the third active layer 34 of the sub-pixel on the other hand, and the third drain electrode of each sub-pixel 39 is connected to the other end of the third active layer 34 of the sub-pixel through a seventh via hole V7 on the one hand, and connected to the light shielding layer 11 of the sub-pixel through an eighth via hole V8 on the other hand. Since the third source electrode 38 is connected to the connecting line LN and the connecting line LN is connected to the compensation line SE, the compensation signal of the compensation line SE is applied to the third source electrode 38.
  • the third drain electrode 39 of the left sub-pixel is connected to the light-shielding layer 11, and the light-shielding layer 11 is an integrated structure connected to the first electrode 12, it is equivalent to the third drain electrode 39 and the first electrode 12 of the left sub-pixel. Connection, that is, the third drain electrode 39 of the left sub-pixel is connected to the lower electrode plate forming the first storage capacitor, the first drain electrode 19 of the left sub-pixel, the third drain electrode 39 of the left sub-pixel, and the first electrode The potential of 12 is the same.
  • the main part of the third electrode 30 is arranged in the common capacitance area of the two sub-pixels, and its position corresponds to the position of the second electrode 17, that is, the orthographic projection of the main part of the third electrode 30 on the substrate is located on the second electrode 17 on the substrate. Within the range of the orthographic projection.
  • the right protruding part of the third electrode 30 is connected to the first gate electrode 16 of the right sub-pixel through the second via hole V2. Since the first gate electrode 16 of the right sub-pixel is connected to the second drain electrode 29, it is equivalent to that the third electrode 30 is connected to the second drain electrode 29 of the right sub-pixel, and the first gate electrode 16 of the right sub-pixel is connected to The second drain electrode 29 and the third electrode 30 of the right sub-pixel have the same potential.
  • the third electrode 30 of this embodiment is used to form the bottom electrode plate of the storage capacitor of the right sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the third electrode 30 occupies the capacitance of the right sub-pixel. Area and the capacitance area of the left sub-pixel.
  • the storage capacitor of the right sub-pixel is called the second storage capacitor.
  • Forming the fourth insulating layer and the fifth insulating layer pattern includes: first depositing a fourth insulating film on the substrate formed with the aforementioned pattern to form the fourth insulating layer 31 covering the aforementioned structure, and then coating the fifth insulating film, using the first The fifth insulating film is used as a photoresist, and the fourth insulating layer 31 is etched through masking, exposure and development to form a pattern of the fifth insulating layer 33 covering the foregoing structure.
  • the fifth insulating layer 33 is formed with the eleventh insulating layer.
  • the hole V11 and the twelfth via hole V12 wherein the eleventh via hole V11 is located at the position of the third drain electrode 39 in the two sub-pixels, and the fifth insulating layer 33 and the fourth insulating layer 33 in the two eleventh via holes V11
  • the insulating layer 31 is removed, and the surface of the third drain electrode 39 is exposed.
  • the twelfth via hole V12 is located at the position of the third electrode 30, and the fifth insulating layer 33 in the twelfth via hole V12 is removed, exposing the surface of the fourth insulating layer 31, as shown in FIGS. 17 and 18, 18 is a cross-sectional view along the AA direction in FIG. 17.
  • the fourth insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or high-k materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), Tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
  • the material of the fifth insulating film includes, but is not limited to, polysiloxane-based materials, acrylic-based materials, or polyimide-based materials.
  • the fourth insulating layer 31 is referred to as a passivation (PVX) layer
  • the fifth insulating layer 33 is referred to as a flattening (PNL) layer.
  • the pixel electrode and the fourth electrode pattern are formed.
  • Forming the pixel electrode and the fourth electrode pattern includes: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film through a patterning process to form the pattern of the pixel electrode 40 and the fourth electrode 35.
  • the pixel electrode 40 is connected to the third drain electrode 39 of the left sub-pixel through the eleventh via hole V11, and the pixel electrode 40 of the right sub-pixel is connected to the third drain electrode 39 of the right sub-pixel through the eleventh via V11 ,
  • the fourth electrode 35 is formed in the twelfth via hole V12, and is an integrated structure connected with the pixel electrode 40 of the right sub-pixel, as shown in FIGS. 19 and 20, and FIG. 20 is a cross-section along the AA direction in FIG. Figure.
  • the transparent conductive film can be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the fourth electrode 35 is arranged in the common capacitance area of the two sub-pixels, and its position corresponds to the position of the third electrode 30, that is, the orthographic projection of the fourth electrode 35 on the substrate is located on the third electrode 30 on the substrate. Within the orthographic projection range.
  • the fourth electrode 35 in this embodiment is used to form the upper electrode plate of the storage capacitor of the right sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the fourth electrode 35 occupies the capacitance of the right sub-pixel. Area and the capacitance area of the left sub-pixel.
  • the third electrode 30 is connected to the first gate electrode 16 of the right sub-pixel, and the first gate electrode 16 of the right sub-pixel is connected to the second drain electrode 29, it is equivalent to the third electrode 30 and the right sub-pixel.
  • the second drain electrode 29 is connected, and the potential of the first gate electrode 16 of the right sub-pixel and the second drain electrode 29 of the right sub-pixel is the same as the potential of the third electrode 30.
  • the pixel electrode 40 of the right sub-pixel is connected to the third drain electrode 39 of the right sub-pixel, and the fourth electrode 35 is an integrated structure connected to the pixel electrode 40 of the right sub-pixel, it is equivalent to the fourth electrode 35 and The third drain electrode 39 of the right sub-pixel is connected.
  • the third drain electrode 39 of the right sub-pixel is also connected to the first drain electrode 19 of the right sub-pixel, the potentials of the first drain electrode 19, the third drain electrode 39 and the pixel electrode 40 of the right sub-pixel are The potential is the same as that of the fourth electrode 35.
  • the third electrode 30 and the fourth electrode 35 serve as two electrode plates forming the second storage capacitor C ST , the third electrode 30 is the lower electrode plate, and the fourth electrode 35 is the upper electrode plate.
  • the subsequent preparation process includes forming structures such as the light-emitting layer, the cathode, and the encapsulation layer, and the preparation method is the same as that of the related technology, and will not be repeated here.
  • FIG. 21 is a schematic diagram of the equivalent circuit of the left sub-pixel in the first embodiment of the disclosure
  • FIG. 22 is a schematic diagram of the equivalent circuit of the right sub-pixel in the first embodiment of the disclosure.
  • the first active layer 14, the first gate electrode 16, the first source electrode 18 and the first drain electrode 19 constitute the first transistor T1
  • the source electrode 28 and the second drain electrode 29 constitute a second transistor T2
  • the third active layer 14, the third gate electrode 16, the third source electrode 18, and the third drain electrode 19 constitute a third transistor T3
  • the first transistor T1 is
  • the driving transistor the second transistor T2 is a switching transistor
  • the third transistor T3 is a compensation transistor.
  • the first storage capacitor C ST is formed by the first electrode 12 and the second electrode 17.
  • the first electrode 12 is the lower electrode plate
  • the second electrode 17 is the upper electrode plate.
  • the first gate electrode 16 of the first transistor T1 is connected to the second drain electrode 29 of the second transistor T2 and the first storage capacitor C ST as the second electrode 17 of the upper electrode plate
  • the first source electrode 18 of the first transistor T1 Connected to the power supply line VDD
  • the first drain electrode 19 of the first transistor T1 is connected to the third drain electrode 39 of the third transistor T3 and the first storage capacitor C ST as the first electrode 12 of the lower electrode plate.
  • the second gate electrode 26 of the second transistor T2 is connected to the switch scan line GN, the second source electrode 28 of the second transistor T2 is connected to the data line DN, and the second drain electrode 29 of the second transistor T2 is connected to the first gate of the first transistor T1.
  • the electrode 16 and the first storage capacitor C ST serve as the second electrode 17 of the upper electrode plate.
  • the third gate electrode 36 of the third transistor T3 is connected to the compensation scan line SN, the third source electrode 38 of the third transistor T3 is connected to the compensation line SE, and the third drain electrode 39 of the third transistor T3 is connected to the first drain of the first transistor T1.
  • the electrode 19 and the first storage capacitor C ST serve as the first electrode 12 of the lower electrode plate.
  • the second storage capacitor C ST is formed by the third electrode 30 and the fourth electrode 35, the third electrode 30 is the lower electrode plate, and the fourth electrode 31 is the upper electrode plate.
  • the first gate electrode 16 of the first transistor T1 is connected to the second drain electrode 29 of the second transistor T2 and the second storage capacitor C ST as the third electrode 30 of the lower electrode plate, and the first source electrode 18 of the first transistor T1 Connected to the power supply line VDD, the first drain electrode 19 of the first transistor T1 is connected to the third drain electrode 39 of the third transistor T3 and the second storage capacitor C ST as the fourth electrode 35 of the upper electrode plate.
  • the second gate electrode 26 of the second transistor T2 is connected to the switch scan line GN, the second source electrode 28 of the second transistor T2 is connected to the data line DN, and the second drain electrode 29 of the second transistor T2 is connected to the first gate of the first transistor T1.
  • the electrode 16 and the first storage capacitor C ST serve as the third electrode 30 of the lower electrode plate.
  • the third gate electrode 36 of the third transistor T3 is connected to the compensation scan line SN, the third source electrode 38 of the third transistor T3 is connected to the compensation line SE, and the third drain electrode 39 of the third transistor T3 is connected to the first drain of the first transistor T1.
  • the pole 19 and the second storage capacitor C ST serve as the fourth electrode 35 of the upper electrode plate.
  • FIG. 23 is a schematic diagram of the pixel arrangement of the first embodiment of the disclosure.
  • the display substrate includes a plurality of pixel units arranged in a matrix, each pixel unit includes 4 sub-pixels, and the 4 sub-pixels are arranged in red (R), green (G), blue (B), and green (G).
  • R red
  • G green
  • B blue
  • G green
  • the capacitor regions of the R sub-pixel and the G sub-pixel are combined as the common capacitor region of the R sub-pixel and the G sub-pixel
  • the capacitor regions of the B sub-pixel and the G sub-pixel are combined as the common capacitor of the B sub-pixel and the G sub-pixel.
  • Area the capacitor regions of the R sub-pixel and the G sub-pixel are combined as the common capacitor region of the R sub-pixel and the G sub-pixel.
  • the 4 sub-pixels in this embodiment are arranged in RGBG, which can be understood as a pixel unit including 2 sub-pixel units, each sub-pixel unit includes 2 sub-pixels, the first sub-pixel unit includes R sub-pixels and G sub-pixels, and the second sub-pixel unit The unit includes B sub-pixels and G sub-pixels.
  • the first sub-pixel unit borrows the missing B sub-pixel from the adjacent second sub-pixel unit to form three primary color sub-pixels RGB.
  • the second sub-pixel unit borrows the missing R sub-pixel from the adjacent first sub-pixel unit to form three primary color sub-pixels RGB. It can be seen that the RGBG arrangement in this embodiment can improve the resolution, and the resolution can reach 1.5 times of the existing RGB arrangement.
  • this embodiment uses the laminated structure in the display substrate to realize the sharing of capacitor regions and the overlapping of storage capacitors, so as to reduce the area of each sub-pixel capacitor region, and finally increase the pixel size. Opening rate.
  • the capacitance areas of two adjacent sub-pixels are combined together as the shared capacitance area of the two sub-pixels, and the electrode plates constituting the storage capacitor of each sub-pixel are arranged in the shared capacitance area.
  • the two electrode plates are the first electrode provided in the same layer as the shielding layer and the second electrode provided in the same layer as the gate electrode.
  • the storage capacitor formed is located at the lower layer of the pixel drive circuit, and the two electrode plates of the other sub-pixel They are the third electrode provided on the same layer as the source and drain electrodes and the fourth electrode provided on the same layer as the pixel electrode.
  • the storage capacitors formed are located in the upper layer of the pixel drive circuit, so that the storage capacitors of the two sub-pixels form a stacked layer arranged up and down. structure.
  • each sub-pixel capacitor area of this embodiment is the same as the area of the sub-pixel capacitor area of the related structure, the area of each sub-pixel electrode plate of this embodiment is doubled, which greatly increases the capacity of the storage capacitor, even if it is applied Due to the smaller pixel size, the required storage capacitor capacity can also be guaranteed, which is conducive to achieving high-resolution display.
  • the capacity of the storage capacitor of each sub-pixel of this embodiment is the same as that of the sub-pixel of the related structure, it is only necessary to design the area of the shared capacitor region of the two sub-pixels to be slightly larger than the area of the sub-pixel capacitor region of the related structure.
  • each sub-pixel capacitor area is only about one-half of the area of the sub-pixel capacitor area of the relevant structure, which greatly reduces the area of each sub-pixel capacitor area and reduces the pixel area occupied by each sub-pixel drive circuit area.
  • the pixel aperture ratio can be increased by at least 10% under high PPI. Therefore, the display substrate structure of this embodiment saves the area occupied by the capacitor, improves the pixel aperture ratio, is suitable for high PPI display, reduces power consumption, and avoids problems such as the lifetime degradation of luminescent materials.
  • the display substrate of this embodiment adopts three layers of the first electrode provided in the same layer as the shielding layer, the buffer layer, and the second electrode provided in the same layer as the gate electrode to realize a storage capacitor structure of one sub-pixel
  • the The third electrode on the same layer as the drain electrode, the passivation layer and the fourth electrode on the same layer as the pixel electrode realize the storage capacitor structure of another sub-pixel
  • the second electrode and the gate electrode have the same potential
  • the third electrode It is also the same potential as the gate electrode, so the Vs potential of the two storage capacitors can be set to the first electrode at the bottom and the fourth electrode at the top, and the Vg signal is applied to the second and third electrodes in the middle to effectively reduce
  • the crosstalk between the signals is small, and the influence between the two storage capacitors is small, which ensures the stability and reliability of the work.
  • the sub-pixels and wiring arrangements of the display substrate in this embodiment are reasonably designed.
  • the storage capacitor In the horizontal direction, the storage capacitor is located between the two data lines DN, and in the vertical direction, the storage capacitor is located between the switch scan lines GN and GN.
  • the compensation scan lines SN and the storage capacitors are arranged between multiple thin film transistors, there are no crossovers on them, and multiple signal wiring positions are more concentrated, which can reduce haze, improve display effects, and effectively ensure the yield.
  • the display substrate prepared in this embodiment does not add new processes and introduce new materials, and has good process compatibility, high process feasibility, strong practicability, and good application prospects.
  • this embodiment effectively improves the pixel aperture ratio of the bottom-emission OLED without increasing the cost and sacrificing the yield, which is conducive to the realization of high-resolution display, and effectively solves the problem of pixels in existing solutions. Defects with low aperture ratio.
  • FIG. 24 is a schematic structural diagram of another exemplary embodiment of a display substrate of the present disclosure.
  • This embodiment shows that the main structure of the substrate is basically the same as that of the aforementioned first embodiment, except that this embodiment also has a color film layer between the fourth insulating layer and the fifth insulating layer.
  • the color filter layer 32 is located in the light-emitting area of each sub-pixel, is disposed on the fourth insulating layer 31 and covered by the fifth insulating layer 33.
  • the structure of the foregoing embodiment is suitable for the light emitting layer to emit light of the required color, and the structure of this embodiment is suitable for the light emitting layer of all sub-pixels to emit light of the same color.
  • the color film layer 32 is filtered to realize the desired color of each sub-pixel. Light.
  • This embodiment shows that the preparation process of the substrate is basically the same as the preparation process of the foregoing first embodiment, except that between step (5) and step (6), a color film layer pattern is formed.
  • the fourth insulating film and the color filter film are sequentially deposited on the substrate with the pattern in step (5), and the fourth insulating film covering the aforementioned structure is formed by masking, exposing and developing the color filter film.
  • the color film layer 32 of the left sub-pixel is a red color film
  • the color film layer 32 of the right sub-pixel is a green color film
  • the color film layer 32 of the left sub-pixel is a blue color film
  • the color film layer 32 of the right sub-pixel is a green color film.
  • This embodiment also achieves the technical effects of the foregoing embodiments, including effectively increasing the pixel aperture ratio of the bottom emission OLED, which is beneficial to realize high-resolution display.
  • the embodiments of the present disclosure can be applied to a structure in which the pixel unit includes 3 sub-pixels.
  • the capacitor regions of the R sub-pixel and the B sub-pixel can be combined as a common capacitor area of the two sub-pixels.
  • the two sub-pixels adopt the structural arrangement proposed in the embodiment of the present disclosure, and the G
  • the capacitor area of the sub-pixels is used as a separate capacitor area, and the sub-pixels can be arranged in a related art structure.
  • the wiring design can be optimized to match the display substrate structure of the present disclosure.
  • the embodiment of the present disclosure also provides a method for preparing a display substrate to prepare the display substrate of the foregoing embodiment.
  • the preparation method of the display substrate of the embodiment of the present disclosure includes: forming a plurality of sub-pixels arranged in a matrix, each sub-pixel is formed with a pixel driving circuit including a plurality of thin film transistors and a storage capacitor, the storage capacitor of the sub-pixel and the storage of adjacent sub-pixels The capacitor is formed in the common capacitor area of the two sub-pixels, and the storage capacitor of the sub-pixel and the storage capacitor of the adjacent sub-pixel are stacked.
  • the storage capacitor of the sub-pixel is formed in the common capacitor area of the two sub-pixels, including:
  • first electrode provided in the same layer as the light shielding layer in the pixel driving circuit, and the first electrode is formed in the common capacitance area of the two sub-pixels;
  • a second electrode arranged in the same layer as the gate electrode of the thin film transistor is formed, and the second electrode is formed in the common capacitance area of the two sub-pixels.
  • the storage capacitors of adjacent sub-pixels are formed in the common capacitor area of two sub-pixels, including:
  • a fourth electrode arranged in the same layer as the pixel electrode is formed, and the fourth electrode is formed in the common capacitance area of the two sub-pixels.
  • forming the pixel driving circuit includes:
  • a gate electrode and a second electrode are formed on the second insulating layer, the second electrode is formed in a common capacitor area of two sub-pixels, and the first electrode and the second electrode form a storage capacitor of the sub-pixel.
  • forming the pixel driving circuit further includes: forming a third insulating layer covering the gate electrode and the second electrode;
  • a pixel electrode and a fourth electrode are formed on the fifth insulating layer, the fourth electrode is formed in a common capacitance area of two sub-pixels, and the third electrode and the fourth electrode form a storage capacitor of adjacent sub-pixels.
  • forming the light-shielding layer and the first electrode on the substrate includes: forming the light-shielding layer of the sub-pixel and the light-shielding layer of the adjacent sub-pixel on the substrate, and the light-shielding layer and the first electrode of the sub-pixel are One-piece structure.
  • forming the gate electrode and the second electrode on the second insulating layer includes: forming the first gate electrode, the second gate electrode, and the third gate of the sub-pixel on the second insulating layer. Electrodes, and the first gate electrode, the second gate electrode and the third gate electrode of the adjacent sub-pixels, and the first gate electrode and the second electrode of the sub-pixel have an integral structure.
  • forming the pixel electrode and the fourth electrode on the fifth insulating layer includes: forming the pixel electrode of the current sub-pixel and the pixel electrode of the adjacent sub-pixel on the fifth insulating layer, the The pixel electrode of the adjacent sub-pixel and the fourth electrode are in an integral structure, and the pixel electrode of the adjacent sub-pixel is connected to the first drain electrode and the third drain electrode of the adjacent sub-pixel through a via hole.
  • forming a source electrode, a drain electrode, and a third electrode on the third insulating layer includes:
  • a data line, a compensation line, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a third source electrode, a third drain electrode, and a third electrode are formed on the third insulating layer.
  • the compensation line is connected to the connection line through a via
  • the first source electrode is connected to the first active layer through the via hole, and the first drain electrode is simultaneously connected to the first active layer and the light shielding layer through the via hole, so that the first drain electrode of the sub-pixel is connected to the first electrode ;
  • the second source electrode and the data line are in an integrated structure, the second source electrode is connected to the second active layer through the via hole, and the second drain electrode is simultaneously connected to the second active layer and the first gate through the via hole. Electrode connection, connecting the second drain electrode of the sub-pixel to the second electrode;
  • the third source electrode is simultaneously connected to the connection line and the third active layer through the via hole, and the third drain electrode is simultaneously connected to the third active layer and the light shielding layer through the via hole, so that the third drain electrode of the sub-pixel Connect the first electrode;
  • the third electrode is connected to the first gate electrode of the adjacent sub-pixel through a via hole.
  • forming the fourth insulating layer and the fifth insulating layer covering the source electrode, the drain electrode, and the third electrode includes:
  • a fifth insulating layer covering the color filter layer is formed.
  • forming a fifth insulating layer covering the color filter layer includes:
  • a via hole exposing the fourth insulating layer is formed in the fifth insulating layer, and the via hole is used for arranging the fourth electrode.
  • the preparation method of the display substrate of the embodiment of the present disclosure also realizes that the pixel aperture ratio of the bottom emission type OLED is effectively improved without increasing the cost and sacrificing the yield, which is beneficial to realize high-resolution display.
  • the embodiment of the present disclosure also provides a display device, including the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the terms “installed”, “connected”, and “connected” should be interpreted broadly. For example, it can be a fixed connection, it can be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate piece, and it can be internal to two components. Connected.
  • installed e.g., it can be a fixed connection, it can be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate piece, and it can be internal to two components. Connected.
  • the meaning of the above-mentioned terms in the present disclosure can be understood according to the situation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，包括矩阵排布的多个子像素，每个子像素设置有包括多个薄膜晶体管和存储电容的像素驱动电路，所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容设置在所述本子像素和所述相邻子像素的共用电容区，所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。

Description

显示基板及其制备方法、显示装置
本申请要求于2019年8月6日提交中国专利局、申请号为201910720928.X、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管显示装置(Organic Light Emitting Diode，OLED)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术。依据驱动方式的不同，OLED可分为无源矩阵驱动(Passive Matrix，PM)型和有源矩阵驱动(Active Matrix，AM)型两种，其中AMOLED是电流驱动器件，采用独立的薄膜晶体管(Thin Film Transistor，TFT)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
根据本公开的至少一个实施例，提供了一种显示基板，包括矩阵排布的多个子像素，每个子像素设置有包括多个薄膜晶体管和存储电容的像素驱动电路，所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容设置在所述本子像素和所述相邻子像素的共用电容区，所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。
根据前述任一实施例的显示基板，例如，所述本子像素的存储电容包括：与像素驱动电路中的遮光层同层设置的第一电极，覆盖所述第一电极的绝缘层，与所述薄膜晶体管的栅电极同层设置的第二电极。
根据前述任一实施例的显示基板，例如，所述相邻子像素的存储电容包括：与所述薄膜晶体管的源漏电极同层设置的第三电极，覆盖所述第三电极的绝缘层，与像素电极同层设置的第四电极。
根据前述任一实施例的显示基板，例如，所述像素驱动电路包括：基底；设置在所述基底上的遮光层和第一电极，所述第一电极设置在所述共用电容区；覆盖所述遮光层和第一电极的第一绝缘层；设置在所述第一绝缘层上的有源层；覆盖所述有源层的第二绝缘层；设置在所述第二绝缘层上的栅电极和第二电极，所述第二电极设置在所述共用电容区，所述第一电极和第二电极形成本子像素的存储电容。
根据前述任一实施例的显示基板，例如，所述像素驱动电路还包括：覆盖所述栅电极和第二电极的第三绝缘层；设置在所述第三绝缘层上的源电极、漏电极和第三电极，所述第三电极设置在所述共用电容区；覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层；设置在所述第五绝缘层上的像素电极和第四电极，所述第四电极设置在所述共用电容区，所述第三电极和第四电极形成相邻子像素的存储电容。
根据前述任一实施例的显示基板，例如，所述多个薄膜晶体管包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管，所述第一薄膜晶体管包括第一有源层、第一栅电极、第一源电极和第一漏电极，所述第二薄膜晶体管包括第二有源层、第二栅电极、第二源电极和第二漏电极，所述第三薄膜晶体管包括第三有源层、第三栅电极、第三源电极和第三漏电极。
根据前述任一实施例的显示基板，例如，在所述本子像素中，所述第一电极与所述遮光层为一体结构，所述第一电极通过过孔连接所述第一漏电极和所述第三漏电极；所述第二电极与所述第一栅电极为一体结构，所述第二电极通过过孔连接所述第二漏电极。
根据前述任一实施例的显示基板，例如，在所述相邻子像素中，所述第三电极通过过孔连接所述第一栅电极和所述第二漏电极，所述第四电极与所 述像素电极为一体结构，所述第四电极通过过孔连接所述第一漏电极和所述第三漏电极。
根据前述任一实施例的显示基板，例如，还包括彩膜层，所述彩膜层设置在第四绝缘层与第五绝缘层之间，所述第五绝缘层上开设有暴露出第四绝缘层的过孔，所述第四电极设置在所述过孔内。
根据前述任一实施例的显示基板，例如，所述像素驱动电路还包括开关扫描线、补偿扫描线和数据线，在水平方向上，所述共用电容区设置在两条数据线之间，在垂直方向上，所述共用电容区设置在开关扫描线和补偿扫描线之间。
根据本公开的至少一个实施例，提供了一种显示装置，包括前述任一实施例的显示基板。
根据本公开的至少一个实施例，提供了一种显示基板的制备方法，包括：形成矩阵排布的多个子像素，在每个子像素形成包括多个薄膜晶体管和存储电容的像素驱动电路，其中，所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容形成在所述本子像素和所述相邻子像素的共用电容区，所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。
根据本公开前述任一实施例的显示基板的制备方法，例如，所述本子像素的存储电容形成在所述共用电容区，包括：形成与像素驱动电路中的遮光层同层设置的第一电极，所述第一电极形成在所述共用电容区；形成覆盖所述第一电极的绝缘层；形成与薄膜晶体管的栅电极同层设置的第二电极，所述第二电极形成在所述共用电容区。
根据本公开前述任一实施例的显示基板的制备方法，例如，所述相邻子像素的存储电容形成在所述共用电容区，包括：形成与薄膜晶体管的源漏电极同层设置的第三电极，所述第三电极形成在所述共用电容区；形成覆盖所述第三电极的绝缘层；形成与像素电极同层设置的第四电极，所述第四电极形成在所述共用电容区。
根据本公开前述任一实施例的显示基板的制备方法，例如，形成像素驱 动电路包括：在基底上形成遮光层和第一电极，所述第一电极形成在所述共用电容区；形成覆盖所述遮光层和第一电极的第一绝缘层；在所述第一绝缘层上形成有源层；形成覆盖所述有源层的第二绝缘层；在所述第二绝缘层上形成栅电极和第二电极，所述第二电极形成在所述共用电容区，所述第一电极和第二电极形成所述本子像素的存储电容。
根据本公开前述任一实施例的显示基板的制备方法，例如，形成像素驱动电路还包括：形成覆盖所述栅电极和第二电极的第三绝缘层；在所述第三绝缘层上形成源电极、漏电极和第三电极，所述第三电极形成在所述共用电容区；形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层；在所述第五绝缘层上形成像素电极和第四电极，所述第四电极形成在所述共用电容区，所述第三电极和第四电极形成相邻子像素的存储电容。
根据本公开前述任一实施例的显示基板的制备方法，例如，
所述在基底上形成遮光层和第一电极包括：在基底上形成本子像素的遮光层和相邻子像素的遮光层，所述本子像素的遮光层与第一电极为一体结构；
所述在所述第二绝缘层上形成栅电极和第二电极包括：在所述第二绝缘层上形成本子像素的第一栅电极、第二栅电极和第三栅电极，以及相邻子像素的第一栅电极、第二栅电极和第三栅电极，所述本子像素的第一栅电极与第二电极为一体结构；
所述在所述第五绝缘层上形成像素电极和第四电极包括：在所述第五绝缘层上形成本子像素的像素电极和相邻子像素的像素电极，所述相邻子像素的像素电极与所述第四电极为一体结构，所述相邻子像素的像素电极通过过孔连接相邻子像素的第一漏电极和第三漏电极。
根据本公开前述任一实施例的显示基板的制备方法，例如，所述在所述第三绝缘层上形成源电极、漏电极和第三电极包括：在所述第三绝缘层上形成数据线、补偿线、第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和第三电极。
根据本公开前述任一实施例的显示基板的制备方法，例如，所述补偿线通过过孔与连接线连接；所述第一源电极通过过孔与第一有源层连接，所述 第一漏电极通过过孔同时与第一有源层和遮光层连接，使本子像素的第一漏电极连接第一电极；所述第二源电极与数据线为一体结构，所述第二源电极通过过孔与第二有源层连接，所述第二漏电极通过过孔同时与第二有源层和第一栅电极连接，使本子像素的第二漏电极连接第二电极；所述第三源电极通过过孔同时与连接线和第三有源层连接，所述第三漏电极通过过孔同时与第三有源层和遮光层连接，使本子像素的第三漏电极连接第一电极；所述第三电极通过过孔与相邻子像素的第一栅电极连接。
根据本公开前述任一实施例的显示基板的制备方法，例如，所述形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层，包括：形成覆盖所述源电极、漏电极和第三电极的第四绝缘层；在所述第四绝缘层上形成彩膜层；形成覆盖所述彩膜层的第五绝缘层，在所述第五绝缘层形成暴露出第四绝缘层的过孔，所述过孔用于设置所述第四电极。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为OLED像素驱动电路的等效电路示意图；
图2为一种底发射型OLED中子像素的结构示意图；
图3为本公开实施例显示基板两个子像素共用电容区的示意图；
图4为本公开实施例显示基板两个子像素存储电容叠层设置的示意图；
图5为本公开显示基板一种示例性实施例的结构示意图；
图6为图5中A-A向的剖面图；
图7为本公开图5所示实施例形成遮光层和第一电极图案后的示意图；
图8为图7中A-A向的剖面图；
图9为本公开图5所示实施例形成有源层图案后的示意图；
图10为图9中A-A向的剖面图；
图11为本公开图5所示实施例形成栅电极和第二电极图案后的示意图；
图12为图11中A-A向的剖面图；
图13为本公开图5所示实施例形成第三绝缘层图案后的示意图；
图14为图13中A-A向的剖面图；
图15为本公开图5所示实施例形成源漏电极和第三电极图案后的示意图；
图16为图15中A-A向的剖面图；
图17为本公开图5所示实施例形成第五绝缘层图案后的示意图；
图18为图17中A-A向的剖面图；
图19为本公开图5所示实施例形成像素电极和第四电极图案后的示意图；
图20为图19中A-A向的剖面图；
图21为本公开图5所示实施例左侧子像素的等效电路示意图；
图22为本公开图5所示实施例右侧子像素的等效电路示意图；
图23为本公开图5所示实施例子像素排布示意图；
图24为本公开显示基板另一种示例性实施例的结构示意图。
附图标记说明:
10—基底；             11—遮光层；           12—第一电极；
13—第一有源层；       14—第一有源层；       15—第二绝缘层；
16—第一栅电极；       17—第二电极；         18—第一源电极；
19—第一漏电极；       20—第三绝缘层；       24—第二有源层；
26—第二栅电极；       28—第二源电极；       29—第二漏电极；
30—第三电极；         31—第四绝缘层；       32—彩膜层；
33—第五绝缘层；       34—第三有源层；       35—第四电极；
36—第三栅电极；       38—第三源电极；       39—第三漏电极；
40—像素电极；         GN—开关扫描线；       SN—补偿扫描线；
LN—连接线；          DN—数据线；          SE—补偿线。
具体实施方式
下面结合附图和实施例对本公开的实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
OLED设计中，像素开口率是参数之一，也是提高显示装置分辨率的一个因素，例如对于底发射型OLED。底发射型OLED是在每个子像素设置发光区和驱动电路区，发光结构设置在发光区，多个TFT和存储电容(C ST)并列设置在驱动电路区，为了保证存储电容的容量，存储电容的电极板通常占用面积较大。随着高分辨率(PPI)显示技术的发展，子像素尺寸越来越小，使得驱动电路区占用像素面积的比例越来越大，导致像素开口率大幅度降低。例如，对于顶栅(Top Gate)底发射结构，上述结构应用于普通分辨率时，像素开口率通常在40％左右，而上述结构应用于高PPI时，像素开口率为10％～20％。实际使用表明，低的像素开口率可能会造成功耗上升和发光材料寿命衰减等问题。
图1为OLED像素驱动电路的等效电路示意图，示意了一种3T1C的驱动结构。如图1所示，该像素驱动电路与开关扫描线GN、补偿扫描线SN、数据线DN、电源线VDD以及补偿线SE电连接。像素驱动电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、存储电容C ST。其中，第一晶体管T1可以为驱动晶体管，第二晶体管T2可以为开关晶体管，第三晶体管T3可以为补偿晶体管。
在一个示例中，第一晶体管T1的栅电极连接第二晶体管T2的第二极和存储电容C ST的第一极，第一晶体管T1的第一极连接第一电源线VDD，第一晶体管T1的第二极连接存储电容C ST的第二极以及第三晶体管T3的第二极。
在一个示例中，第二晶体管T2的栅电极连接扫描线GN，第二晶体管T2的第一极连接数据线DN；第三晶体管T3的栅电极连接补偿扫描线SN，第三晶体管T3的第一极连接补偿线SE。OLED的阳极连接第一晶体管T1的第二 极，OLED的阴极连接低电压线VSS，被配置为响应第一晶体管T1的第二极的电流而发出相应亮度的光。其中，第三晶体管T3能够响应补偿的时序提取第一晶体管T1的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿，存储电容C ST用于保持在一帧发光周期内N1节点和N2节点电压，因此需要较高的存储容量。
图2为一种底发射型OLED中子像素的结构示意图。如图2所示，每个子像素设置有发光区和驱动电路区，驱动电路区包括TFT区和电容区，发光结构设置在发光区，驱动发光结构的多个TFT设置在TFT区，存储电容的电极板设置在电容区，多个TFT和存储电容的电极板并列设置。该结构中，存储电容是由遮挡层和导体化的有源层作为存储电容的两个电极板。为了保证存储电容的容量，电极板需要较大面积，即电容区占用较大面积，因而上述结构应用于高PPI时，像素开口率非常低。
为了有效提高底发射型OLED的像素开口率，本公开实施例提供一种显示基板。本公开实施例显示基板包括矩阵排布的多个子像素，每个子像素设置有包括多个薄膜晶体管和存储电容的像素驱动电路，本子像素像素驱动电路的存储电容和相邻子像素像素驱动电路的存储电容设置在两个子像素的共用电容区，本子像素像素驱动电路的存储电容和相邻子像素像素驱动电路的存储电容叠层设置。
图3为本公开实施例显示基板两个子像素共用电容区的示意图，图4为本公开实施例显示基板两个子像素存储电容叠层设置的示意图。如图3所示，两个子像素分别为本子像素和相邻子像素，每个子像素设置有发光区和TFT区，两个子像素的电容区一起组成共用电容区，构成每个子像素存储电容的电极板均设置在该共用电容区内。如图4所示，构成本子像素像素驱动电路的存储电容的电极板包括第一电极和第二电极，第一电极与遮光层同层设置，第二电极与薄膜晶体管的栅电极同层设置，第一电极和第二电极设置在两个子像素的共用电容区。构成相邻子像素像素驱动电路的存储电容的电极板包括第三电极和第四电极，第三电极与薄膜晶体管的源漏电极同层设置，第四电极与像素电极同层设置，第三电极和第四电极设置在两个子像素的共用电容区。
本公开实施例提出了一种显示基板，利用显示基板中的层叠结构实现了电容区共用和存储电容叠设。本公开将相邻两个子像素的电容区结合起来一起作为两个子像素的共用电容区，构成每个子像素存储电容的电极板均设置在该共用电容区，使两个子像素的存储电容形成叠层结构，大幅度减小了每个子像素电容区的面积，减小了驱动电路区占用像素面积的比例，有效提高了像素开口率，适用于高PPI显示，降低了功耗。
下面通过示例性实施例详细说明本公开实施例的技术方案。
图5为本公开显示基板一种示例性实施例的结构示意图，图6为图5中A-A向的剖面图，示意了底发射显示基板相邻两个子像素的结构。实际实施时，两个相邻子像素可以是红色子像素和绿色子像素，或者可以是蓝色子像素和绿色子像素，或者可以是红色子像素和蓝色子像素。本实施例中，图5中的左侧子像素是指本子像素，图5中的右侧子像素是指相邻子像素。如图5和图6所示，并结合图7至图20，本实施例所提供的显示基板可以包括：
基底10；
遮光层11和第一电极12，设置在基底10上；其中，第一电极12设置在两个子像素的共用电容区，每个子像素中均设置有遮光层11，左侧子像素的遮光层11与第一电极12连接且为一体结构，右侧子像素的遮光层11单独设置；
第一绝缘层13，覆盖遮光层11和第一电极12；
第一有源层14、第二有源层24和第三有源层34，设置在第一绝缘层13上；其中，两个子像素均设置有第一有源层14、第二有源层24和第三有源层34；
第二绝缘层15以及设置在第二绝缘层15上且与第二绝缘层15的图案相同的开关扫描线GN、补偿扫描线SN、连接线LN、第一栅电极16、第二栅电极26、第三栅电极36和第二电极17；其中，第二电极17设置在两个子像素的共用电容区，两个子像素均设置有第一栅电极16、第二栅电极26和第三栅电极36，两个子像素中的第二栅电极26与开关扫描线GN为一体结构，第 三栅电极36与补偿扫描线SN为一体结构，左侧子像素的第一栅电极16与第二电极17连接且为一体结构，右侧子像素的第一栅电极16单独设置；
第三绝缘层20，覆盖开关扫描线GN、补偿扫描线SN、连接线LN、第一栅电极16、第二栅电极26、第三栅电极36和第二电极17，其上分别开设多个过孔，多个过孔包括：两个子像素中同时暴露出第一栅电极16和第二有源层24的第一过孔V1，右侧子像素中暴露出第一栅电极16的第二过孔V2，两个子像素中暴露出第一有源层14两端的第三过孔V3和第四过孔V4，两个子像素中暴露出第二有源层24的第五过孔V5，两个子像素中同时暴露出连接线LN和第三有源层34的第六过孔V6，两个子像素中暴露出第三有源层34的第七过孔V7，两个子像素中暴露出遮光层11的第八过孔V8和第九过孔V9，右侧子像素中暴露出连接线LN的第十过孔V10；其中，第一过孔V1和第六过孔V6均为双连接孔，第一过孔V1同时暴露出第一栅电极16和第二有源层24，第六过孔V6同时暴露出连接线LN和第三有源层34；
数据线DN、补偿线SE、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39和第三电极30，设置在第三绝缘层20上，两个子像素的第一源电极18通过第四过孔V4与第一有源层14连接，第一漏电极19通过第三过孔V3与第一有源层14连接，同时通过第九过孔V9与遮光层11连接；两个子像素的第二源电极28与数据线DN为一体结构，通过第五过孔V5与第二有源层24连接，第二漏电极29通过第一过孔V1同时与第二有源层24和第一栅电极16连接；两个子像素的第三源电极38通过第六过孔V6同时与连接线LN和第三有源层34连接，第三漏电极39通过第七过孔V7与第三有源层34连接，同时通过第八过孔V8与遮光层11连接；第三电极30设置在两个子像素的共用电容区，通过第二过孔V2与右侧子像素的第一栅电极16连接；补偿线SE通过第十过孔V10与连接线LN连接；
第四绝缘层31和第五绝缘层33，覆盖前述结构，其上形成有第十一过孔V10和第十二过孔V11，第十一过孔V11位于两个子像素中的第三漏电极39位置，暴露出第三漏电极39的表面，第十二过孔V12位于第三电极30所在位置，暴露出第四绝缘层31的表面；
像素电极40和第四电极35，设置在第五绝缘层33上，两个子像素的像素电极40通过第十一过孔V11与第三漏电极39连接，第四电极35设置在两个子像素的共用电容区，位于第十二过孔V12内，与右侧子像素的像素电极40为一体结构。
本实施例中，第一电极和第二电极设置在两个子像素的共用电容区，形成左侧子像素的存储电容，第三电极和第四电极设置在两个子像素的共用电容区，形成右侧子像素的存储电容，左侧子像素的存储电容位于右侧子像素的存储电容的下方，形成左侧子像素的存储电容和右侧子像素的存储电容的叠层设置结构。
下面通过本实施例显示基板的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是一些制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等工艺，涂覆可采用涂覆工艺，在此不做限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
(1)形成遮光层和第一电极图案。形成遮光层和第一电极图案包括：在基底上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在基底10上形成遮光层11和第一电极12图案，如图7和图8所示，图8为图7中A-A向的剖面图。本实施例中，每个子像素中均设置有遮光层11，第一电极12设置在两个子像素的共用电容区，即第一电极12设置在两个遮光层11之间，左侧子像素的遮光层11与第一电极12连接成一体结构。虽然本实施例的第一电极12是用于形成左侧子像素的存储电容的下电极板，但其是设置在两个子像素的共用电容区，即第一电极12占据左侧子像素的电容区和右侧子像素的电容区。为简便起见，左侧子像素的存储电容称为第一存储电容。其中，第一金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钼(Mo)等，或上述金属的合金材料，如铝铌合金(AlNd)、钼铌合金(MoNb) 等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
(2)形成有源层图案。形成有源层图案包括：在形成有前述图案的基底上，依次沉积第一绝缘薄膜和有源(Active)薄膜，通过构图工艺对有源薄膜进行构图，形成覆盖遮光层11和第一电极12图案的第一绝缘层13，以及形成在第一绝缘层13上的第一有源层14、第二有源层24和第三有源层34图案，如图9和图10所示，图10为图9中A-A向的剖面图。其中，两个子像素中均形成有第一有源层14、第二有源层24和第三有源层34，第一有源层14作为驱动TFT(第一晶体管T1)的有源层，第二有源层24作为开关TFT(第二晶体管T2)的有源层，第三有源层34作为补偿TFT(第三晶体管T3)的有源层。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等多种材料，即本实施例同时适用于基于氧化物(Oxide)技术、硅技术以及有机物技术制造的基于顶栅(Top Gate)TFT的显示基板。第一绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)等，或者可以采用高介电常数High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第一绝缘层13称为缓冲(Buffer)层。
(3)形成栅电极和第二电极图案。形成栅电极和第二电极图案包括：在形成有前述图案的基底上，依次沉积第二绝缘薄膜和第二金属薄膜，先在第二金属薄膜上涂覆一层光刻胶，通过掩膜、曝光和显影形成光刻胶图案，利用刻蚀工艺刻蚀第二金属薄膜，后利用第二金属薄膜作为掩膜自对准向下刻蚀第二绝缘薄膜，形成第二绝缘层15图案，以及设置在第二绝缘层15上的开关扫描线GN、补偿扫描线SN、连接线LN、第一栅电极16、第二栅电极26、第三栅电极36和第二电极17图案，如图11和图12所示，图12为图11中A-A向的剖面图。随后，以扫描线和栅电极图案作为掩膜对暴露出的第一有源层14、第二有源层24和第三有源层34进行导体化处理。本实施例中，第二电极17设置在两个子像素的共用电容区，设置在两个子像素的第一栅电极16之间，其位置与第一电极12的位置相对应，即第二电极17在基底上的正投影位于第一电极12在基底上的正投影范围之内。两个子像素中均设置有 第一栅电极16、第二栅电极26和第三栅电极36，两个子像素的第二栅电极26是与开关扫描线GN连接的一体结构，两个子像素的第三栅电极36是与补偿扫描线SN连接的一体结构。左侧子像素中的第一栅电极16与第二电极17连接成一体结构。虽然本实施例的第二电极17是用于形成左侧子像素的存储电容的上电极板，但其是设置在两个子像素的共用电容区，即第二电极17占据左侧子像素的电容区和右侧子像素的电容区。开关扫描线GN用于向两个子像素的第二栅电极26提供控制开关TFT的开启/关闭信号，补偿扫描线SN用于向两个子像素的第三栅电极36提供控制补偿TFT的开启/关闭信号，连接线LN作为两个子像素中补偿TFT的源电极，将与后续形成的补偿线SE连接。两个子像素的共用电容区设置在开关扫描线GN和补偿扫描线SN之间。其中，第二金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钼(Mo)等，或上述金属的合金材料，如铝铌合金(AlNd、钼铌合金(MoNb)等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。第二绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，也可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第二绝缘层15称为栅绝缘(GI)层。
(4)形成第三绝缘层图案。形成第三绝缘层图案包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层20图案，第三绝缘层20上开设有多个过孔，多个过孔分别为：两个子像素中形成的同时暴露出第一栅电极16和第二有源层24的第一过孔V1，右侧子像素中形成的暴露出第一栅电极16的第二过孔V2，两个子像素中形成的暴露出第一有源层14两端的第三过孔V3和第四过孔V4，两个子像素中形成的暴露出第二有源层24的第五过孔V5，两个子像素中形成的同时暴露出连接线LN和第三有源层34的第六过孔V6，两个子像素中形成的暴露出第三有源层34的第七过孔V7，两个子像素中形成的暴露出遮光层11的第八过孔V8和第九过孔V9，右侧子像素中形成的暴露出连接线LN的第十过孔V10，如图13和图14所示，图14为图13中A-A向的剖面图。其中，两个子像素中形成的第一过孔V1为同时暴露出第一栅电极16和第二有源层24的转接过孔，转接过孔由两个半孔组成，一个半孔暴露出第 一栅电极16，另一个半孔暴露出第二有源层24。两个子像素中的第六过孔V6是同时暴露出连接线LN和第三有源层34的转接过孔，一个半孔暴露出连接线LN，另一个半孔暴露出第三有源层34。将第一过孔V1和第六过孔V6设置成转接过孔，可以缩小驱动电路区的占用面积，提升开口率。其中，第三绝缘层20可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，也可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。通常，第三绝缘层20称为层间绝缘(ILD)层。
(5)形成源漏电极和第三电极图案。形成源漏电极和第三电极图案包括：在形成有前述图案的基底上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第三绝缘层20上形成电源线(未示出)、数据线DN、补偿线SE、第一源电极18、第一漏电极19、第二源电极28、第二漏电极29、第三源电极38、第三漏电极39和第三电极30图案，如图15和图16所示，图16为图15中A-A向的剖面图。其中，
数据线DN设置在两个子像素的外侧，使得两个子像素的共用电容区位于两条数据线DN之间，每条数据线DN为邻近子像素的开关TFT提供数据信号，补偿线SE设置在数据线DN的外侧，通过第十过孔V10与连接线LN连接，为两个数据线DN之间的两个子像素的补偿TFT提供补偿信号。
两个子像素的第一源电极18是与电源线(未示出)连接的一体结构，每个子像素的第一源电极18通过第四过孔V4与该子像素的第一有源层14的一端连接，每个子像素的第一漏电极19一方面通过第三过孔V3与该子像素的第一有源层14的另一端连接，另一方面通过第九过孔V9与该子像素的遮光层11连接。由于左侧子像素的遮光层11是与第一电极12连接的一体结构，因此相当于左侧子像素的第一漏电极19与第一电极12连接，即左侧子像素的第一漏电极19与形成第一存储电容的下电极板连接，左侧子像素中第一漏电极19和第一电极12的电位相同。
每个子像素的第二源电极28是与该子像素的数据线DN连接的一体结构，每个子像素的第二源电极28通过第五过孔V5与该子像素的第二有源层24的一端连接，每个子像素的第二漏电极29通过第一过孔V1，一方面与该子像 素的第二有源层24的另一端连接，另一方面与该子像素的第一栅电极16连接，即第二漏电极29通过第一过孔V1同时与第二有源层24和第一栅电极16连接。由于左侧子像素的第一栅电极16是与第二电极17连接的一体结构，因此相当于左侧子像素的第二漏电极29与第二电极17连接，即左侧子像素的第二漏电极29与形成第一存储电容的上极板连接，左侧子像素的第一栅电极16、第二漏电极29和第二电极17的电位相同。
每个子像素的第三源电极38通过第六过孔V6，一方面与连接线LN连接，另一方面与该子像素的第三有源层34的一端连接，每个子像素的第三漏电极39一方面通过第七过孔V7与该子像素的第三有源层34的另一端连接，另一方面通过第八过孔V8与该子像素的遮光层11连接。由于第三源电极38与连接线LN连接，而连接线LN与补偿线SE连接，因此补偿线SE的补偿信号施加在第三源电极38上。由于左侧子像素的第三漏电极39与遮光层11连接，而遮光层11是与第一电极12连接的一体结构，因此相当于左侧子像素的第三漏电极39与第一电极12连接，即左侧子像素的第三漏电极39与形成第一存储电容的下电极板连接，左侧子像素的第一漏电极19、左侧子像素的第三漏电极39和第一电极12的电位相同。
第三电极30的主要部分设置在两个子像素的共用电容区，其位置与第二电极17的位置相对应，即第三电极30的主要部分在基底上的正投影位于第二电极17在基底上的正投影范围之内。第三电极30右侧凸出部分通过第二过孔V2与右侧子像素的第一栅电极16连接。由于右侧子像素的第一栅电极16与第二漏电极29连接，因此相当于第三电极30与右侧子像素的第二漏电极29连接，右侧子像素的第一栅电极16、右侧子像素的第二漏电极29和第三电极30的电位相同。虽然本实施例的第三电极30是用于形成右侧子像素的存储电容的下电极板，但其是设置在两个子像素的共用电容区，即第三电极30占据右侧子像素的电容区和左侧子像素的电容区。为简便起见，右侧子像素的存储电容称为第二存储电容。
(6)形成第四绝缘层和第五绝缘层图案。形成第四绝缘层和第五绝缘层图案包括：在形成有前述图案的基底上，先沉积第四绝缘薄膜，形成覆盖前述结构的第四绝缘层31，然后涂覆第五绝缘薄膜，利用第五绝缘薄膜作为光 刻胶，通过掩膜、曝光和显影，对第四绝缘层31进行刻蚀，形成覆盖前述结构的第五绝缘层33图案，第五绝缘层33上形成有第十一过孔V11和第十二过孔V12，其中，第十一过孔V11分别位于两个子像素中的第三漏电极39位置，两个第十一过孔V11内的第五绝缘层33和第四绝缘层31被去掉，暴露出第三漏电极39的表面。第十二过孔V12位于第三电极30所在位置，第十二过孔V12内的第五绝缘层33被去掉，暴露出第四绝缘层31的表面，如图17和图18所示，图18为图17中A-A向的剖面图。其中，第四绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)、氮氧化硅(SiON)等，也可以采用High k材料，如氧化铝(AlOx)、氧化铪(HfOx)、氧化钽(TaOx)等，可以是单层、多层或复合层。第五绝缘薄膜的材料包含但不限于聚硅氧烷系材料、亚克力系材料或聚酰亚胺系材料等。通常，第四绝缘层31称为钝化(PVX)层，第五绝缘层33称为平坦(PNL)层。
(7)形成像素电极和第四电极图案。形成像素电极和第四电极图案包括：在形成有前述图案的基底上，沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成像素电极40和第四电极35图案，左侧子像素的像素电极40通过第十一过孔V11与左侧子像素的第三漏电极39连接，右侧子像素的像素电极40通过第十一过孔V11与右侧子像素的第三漏电极39连接，第四电极35形成在第十二过孔V12内，且是与右侧子像素的像素电极40连接的一体结构，如图19和图20所示，图20为图19中A-A向的剖面图。其中，透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等。
本实施例中，第四电极35设置在两个子像素的共用电容区，其位置与第三电极30的位置相对应，即第四电极35在基底上的正投影位于第三电极30在基底上的正投影范围之内。虽然本实施例的第四电极35是用于形成右侧子像素的存储电容的上电极板，但其是设置在两个子像素的共用电容区，即第四电极35占据右侧子像素的电容区和左侧子像素的电容区。
由于第三电极30与右侧子像素的第一栅电极16连接，而右侧子像素的第一栅电极16与第二漏电极29连接，因此相当于第三电极30与右侧子像素的第二漏电极29连接，右侧子像素的第一栅电极16和右侧子像素的第二漏电极29的电位与第三电极30的电位相同。由于右侧子像素的像素电极40与 右侧子像素的第三漏电极39连接，而第四电极35是与右侧子像素的像素电极40连接的一体结构，因此相当于第四电极35与右侧子像素的第三漏电极39连接。同时，由于右侧子像素的第三漏电极39还与右侧子像素的第一漏电极19连接，因此右侧子像素的第一漏电极19、第三漏电极39和像素电极40的电位与第四电极35的电位相同。这样，第三电极30和第四电极35作为形成第二存储电容C ST的两个电极板，第三电极30为下电极板，第四电极35为上电极板。
后续制备过程包括形成发光层、阴极和封装层等结构，制备方式与相关技术相同，这里不再赘述。
图21为本公开第一实施例左侧子像素的等效电路示意图，图22为本公开第一实施例右侧子像素的等效电路示意图。本实施例中，第一有源层14、第一栅电极16、第一源电极18和第一漏电极19构成第一晶体管T1，第二有源层24、第二栅电极26、第二源电极28和第二漏电极29构成第二晶体管T2，第三有源层14、第三栅电极16、第三源电极18和第三漏电极19构成第三晶体管T3，第一晶体管T1为驱动晶体管，第二晶体管T2为开关晶体管，第三晶体管T3为补偿晶体管。
如图21所示，对于左侧子像素，第一存储电容C ST由第一电极12和第二电极17形成，第一电极12为下电极板，第二电极17为上电极板。其中，第一晶体管T1的第一栅电极16连接第二晶体管T2的第二漏电极29和第一存储电容C ST作为上电极板的第二电极17，第一晶体管T1的第一源电极18连接电源线VDD，第一晶体管T1的第一漏电极19连接第三晶体管T3的第三漏电极39和第一存储电容C ST作为下电极板的第一电极12。第二晶体管T2的第二栅电极26连接开关扫描线GN，第二晶体管T2的第二源电极28连接数据线DN，第二晶体管T2的第二漏电极29连接第一晶体管T1的第一栅电极16和第一存储电容C ST作为上电极板的第二电极17。第三晶体管T3的第三栅电极36连接补偿扫描线SN，第三晶体管T3的第三源电极38连接补偿线SE，第三晶体管T3的第三漏电极39连接第一晶体管T1的第一漏电极19和第一存储电容C ST作为下电极板的第一电极12。
如图22所示，对于右侧子像素，第二存储电容C ST由第三电极30和第四 电极35形成，第三电极30为下电极板，第四电极31为上电极板。其中，第一晶体管T1的第一栅电极16连接第二晶体管T2的第二漏电极29和第二存储电容C ST作为下电极板的第三电极30，第一晶体管T1的第一源电极18连接电源线VDD，第一晶体管T1的第一漏电极19连接第三晶体管T3的第三漏电极39和第二存储电容C ST作为上电极板的第四电极35。第二晶体管T2的第二栅电极26连接开关扫描线GN，第二晶体管T2的第二源电极28连接数据线DN，第二晶体管T2的第二漏电极29连接第一晶体管T1的第一栅电极16和第一存储电容C ST作为下电极板的第三电极30。第三晶体管T3的第三栅电极36连接补偿扫描线SN，第三晶体管T3的第三源电极38连接补偿线SE，第三晶体管T3的第三漏电极39连接第一晶体管T1的第一漏电极19和第二存储电容C ST作为上电极板的第四电极35。
图23为本公开第一实施例子像素排布示意图。本实施例中，显示基板包括矩阵排布的多个像素单元，每个像素单元包括4个子像素，4个子像素以红(R)绿(G)蓝(B)绿(G)排布。其中，R子像素和G子像素的电容区结合起来作为R子像素和G子像素的共用电容区，B子像素和G子像素的电容区结合起来作为B子像素和G子像素的共用电容区。本实施例4个子像素以RGBG排布，可以理解为一个像素单元包括2个子像素单元，每个子像素单元包括2个子像素，第一子像素单元包括R子像素和G子像素，第二子像素单元包括B子像素和G子像素。在呈现各种各样的颜色时，第一子像素单元从相邻的第二子像素单元中借用缺少的B子像素，形成三基色子像素RGB。同样，第二子像素单元从相邻的第一子像素单元借用缺少的R子像素，形成三基色子像素RGB。由此可见，本实施例采用RGBG排布可以提高分辨率，分辨率可以达到现有RGB排布的1.5倍。
通过本实施例显示基板的结构及其制备过程可以看出，本实施例利用显示基板中的层叠结构实现电容区共用和存储电容叠设，以减小每个子像素电容区的面积，最终提高像素开口率。在一个示例中，本实施例将相邻两个子像素的电容区结合起来一起作为两个子像素的共用电容区，构成每个子像素存储电容的电极板均设置在该的共用电容区，一个子像素的两个电极板分别是与遮挡层同层设置的第一电极和与栅电极同层设置的第二电极，形成的存储电容位于像素驱动电路的下层位置，另一个子像素的两个电极板分别是与 源漏电极同层设置的第三电极和与像素电极同层设置的第四电极，形成的存储电容位于像素驱动电路的上层位置，使两个子像素的存储电容形成上下设置的叠层结构。当本实施例每个子像素电容区面积与相关结构子像素电容区面积相同的情况下，本实施例每个子像素电极板的面积增加了约一倍，大幅度增加了存储电容的容量，即使应用于较小的像素尺寸，也能够保证所需的存储电容容量，有利于实现高分辨率显示。当本实施例每个子像素存储电容容量与相关结构子像素存储电容容量相同的情况下，只需将两个子像素共用电容区的面积设计成稍大于相关结构子像素电容区的面积，这样本实施例每个子像素电容区的面积仅为相关结构子像素电容区的面积的二分之一左右，大幅度减小了每个子像素电容区的面积，减小了每个子像素驱动电路区占用像素面积的比例，高PPI下像素开口率能够至少提高10％。因此，本实施例显示基板结构节省了电容占用版图的面积，提高了像素开口率，适用于高PPI显示，降低了功耗，避免了发光材料寿命衰减等问题。
在一个示例中，由于本实施例显示基板采用与遮挡层同层设置的第一电极、缓冲层和与栅电极同层设置的第二电极三层实现一个子像素的存储电容结构，采用与源漏电极同层设置的第三电极、钝化层和与像素电极同层设置的第四电极三层实现另一个子像素的存储电容结构，且第二电极与栅电极的电位相同，第三电极也与栅电极的电位相同，因此可以将两个存储电容的Vs电位设置为最底层的第一电极和最顶层的第四电极，对中间的第二电极和第三电极施加Vg信号，有效减小了信号间的串扰，两个存储电容之间的影响较小，保证了工作稳定性和可靠性。
在一个示例中，本实施例显示基板的子像素和走线排布设计合理，在水平方向上，存储电容位于两个数据线DN之间，在垂直方向上，存储电容位于开关扫描线GN和补偿扫描线SN之间，同时存储电容设置在多个薄膜晶体管之间，其上没有跨线，多个信号走线位置更加集中，可以降低雾度，提高显示效果，有效保证了良品率。
在一个示例中，本实施例制备显示基板没有增加新的工艺以及引入新的材料，工艺兼容性好，工艺可实现性高，实用性强，具有良好的应用前景。
综上所述，本实施例在不增加成本、牺牲良率的前提下，有效提高了底 发射型OLED的像素开口率，有利于实现高分辨率显示，有效解决了现有解决方案存在的像素开口率较低的缺陷。
图24为本公开显示基板另一种示例性实施例的结构示意图。本实施例显示基板的主体结构与前述第一实施例基本上相同，所不同的是，本实施例在第四绝缘层和第五绝缘层之间，还设置了彩膜层。如图24所示，彩膜层32位于每个子像素的发光区，设置在第四绝缘层31上，并被第五绝缘层33覆盖。前述实施例的结构适用于发光层出射所需颜色的光线，本实施例的结构适用于所有子像素的发光层出射相同颜色的光线，通过彩膜层32的过滤实现每个子像素出射所需颜色的光线。
本实施例显示基板的制备过程与前述第一实施例的制备过程基本上相同，所不同的是，在步骤(5)与步骤(6)之间，形成彩膜层图案。在本示例中，在完成步骤(5)图案的基底上，依次沉积第四绝缘薄膜和彩色滤光薄膜，通过对彩色滤光薄膜的掩膜、曝光和显影，形成覆盖前述结构的第四绝缘层31以及形成在第四绝缘层31上的彩膜层32图案。其中，左侧子像素的彩膜层32和右侧子像素的彩膜层32的结构相同，但彩膜层32的颜色不同。例如，左侧子像素的彩膜层32为红色彩膜，右侧子像素的彩膜层32为绿色彩膜。又如，左侧子像素的彩膜层32为蓝色彩膜，右侧子像素的彩膜层32为绿色彩膜。随后，执行步骤(6)涂覆第五绝缘薄膜等处理。
本实施例同样实现了前述实施例的技术效果，包括有效提高了底发射型OLED的像素开口率，有利于实现高分辨率显示。
前述实施例以像素单元包括4个子像素为例进行了说明，实际上，本公开实施例可以适用于像素单元包括3个子像素的结构。以像素单元包括RGB子像素为例，可以将R子像素和B子像素的电容区结合起来作为两个子像素的共用电容区，两个子像素采用本公开实施例提出的结构排布方式，而G子像素的电容区作为单独的电容区，子像素可以采用相关技术的结构排布方式。实际实施时，可以通过优化走线设计来配合本公开的显示基板结构。
基于前述实施例，本公开实施例还提供了一种显示基板的制备方法，以制备出前述实施例的显示基板。
本公开实施例显示基板的制备方法包括：形成矩阵排布的多个子像素，每个子像素形成有包括多个薄膜晶体管和存储电容的像素驱动电路，本子像素的存储电容和相邻子像素的存储电容形成在两个子像素的共用电容区，本子像素的存储电容和相邻子像素的存储电容叠层设置。
在一示例性实施例中，本子像素的存储电容形成在两个子像素的共用电容区，包括：
形成与像素驱动电路中的遮光层同层设置的第一电极，所述第一电极形成在两个子像素的共用电容区；
形成覆盖所述第一电极的绝缘层；
形成与薄膜晶体管的栅电极同层设置的第二电极，所述第二电极形成在两个子像素的共用电容区。
在一示例性实施例中，相邻子像素的存储电容形成在两个子像素的共用电容区，包括：
形成与薄膜晶体管的源漏电极同层设置的第三电极，所述第三电极形成在两个子像素的共用电容区；
形成覆盖所述第三电极的绝缘层；
形成与像素电极同层设置的第四电极，所述第四电极形成在两个子像素的共用电容区。
在一示例性实施例中，形成像素驱动电路包括：
在基底上形成遮光层和第一电极，所述第一电极形成在两个子像素的共用电容区；
形成覆盖所述遮光层和第一电极的第一绝缘层；
在所述第一绝缘层上形成有源层；
形成覆盖所述有源层的第二绝缘层；
在所述第二绝缘层上形成栅电极和第二电极，所述第二电极形成在两个子像素的共用电容区，所述第一电极和第二电极形成本子像素的存储电容。
在一示例性实施例中，形成像素驱动电路还包括：形成覆盖所述栅电极和第二电极的第三绝缘层；
在所述第三绝缘层上形成源电极、漏电极和第三电极，所述第三电极形成在两个子像素的共用电容区；
形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层；
在所述第五绝缘层上形成像素电极和第四电极，所述第四电极形成在两个子像素的共用电容区，所述第三电极和第四电极形成相邻子像素的存储电容。
在一示例性实施例中，在基底上形成遮光层和第一电极包括：在基底上形成本子像素的遮光层和相邻子像素的遮光层，所述本子像素的遮光层与第一电极为一体结构。
在一示例性实施例中，在所述第二绝缘层上形成栅电极和第二电极包括：在所述第二绝缘层上形成本子像素的第一栅电极、第二栅电极和第三栅电极，以及相邻子像素的第一栅电极、第二栅电极和第三栅电极，所述本子像素的第一栅电极与第二电极为一体结构。
在一示例性实施例中，在所述第五绝缘层上形成像素电极和第四电极包括：在所述第五绝缘层上形成本子像素的像素电极和相邻子像素的像素电极，所述相邻子像素的像素电极与所述第四电极为一体结构，所述相邻子像素的像素电极通过过孔连接相邻子像素的第一漏电极和第三漏电极。
在一示例性实施例中，在所述第三绝缘层上形成源电极、漏电极和第三电极包括：
在所述第三绝缘层上形成数据线、补偿线、第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和第三电极。
在一示例性实施例中，
所述补偿线通过过孔与连接线连接；
所述第一源电极通过过孔与第一有源层连接，所述第一漏电极通过过孔同时与第一有源层和遮光层连接，使本子像素的第一漏电极连接第一电极；
所述第二源电极与数据线为一体结构，所述第二源电极通过过孔与第二有源层连接，所述第二漏电极通过过孔同时与第二有源层和第一栅电极连接，使本子像素的第二漏电极连接第二电极；
所述第三源电极通过过孔同时与连接线和第三有源层连接，所述第三漏电极通过过孔同时与第三有源层和遮光层连接，使本子像素的第三漏电极连接第一电极；
所述第三电极通过过孔与相邻子像素的第一栅电极连接。
在一示例性实施例中，形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层，包括：
形成覆盖所述源电极、漏电极和第三电极的第四绝缘层；
在所述第四绝缘层上形成彩膜层；
形成覆盖所述彩膜层的第五绝缘层。
在一示例性实施例中，形成覆盖所述彩膜层的第五绝缘层，包括：
在所述第五绝缘层形成暴露出第四绝缘层的过孔，所述过孔用于设置所述第四电极。
有关显示基板的制备过程，已在之前的实施例中详细说明，这里不再赘述。
本公开实施例显示基板的制备方法同样实现了在不增加成本、牺牲良率的前提下，有效提高了底发射型OLED的像素开口率，有利于实现高分辨率显示。
本公开实施例还提供了一种显示装置，包括前述的显示基板。显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
在本公开实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间件间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括矩阵排布的多个子像素，每个子像素设置有包括多个薄膜晶体管和存储电容的像素驱动电路，所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容设置在所述本子像素和所述相邻子像素的共用电容区，所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。
  2. 根据权利要求1所述的显示基板，其中，所述本子像素的存储电容包括：
    与像素驱动电路中的遮光层同层设置的第一电极，覆盖所述第一电极的绝缘层，与所述薄膜晶体管的栅电极同层设置的第二电极。
  3. 根据权利要求1或2所述的显示基板，其中，所述相邻子像素的存储电容包括：
    与所述薄膜晶体管的源漏电极同层设置的第三电极，覆盖所述第三电极的绝缘层，与像素电极同层设置的第四电极。
  4. 根据权利要求1至3任一项所述的显示基板，其中，所述像素驱动电路包括：
    基底；
    设置在所述基底上的遮光层和第一电极，所述第一电极设置在所述共用电容区；
    覆盖所述遮光层和第一电极的第一绝缘层；
    设置在所述第一绝缘层上的有源层；
    覆盖所述有源层的第二绝缘层；
    设置在所述第二绝缘层上的栅电极和第二电极，所述第二电极设置在所述共用电容区，所述第一电极和第二电极形成本子像素的存储电容。
  5. 根据权利要求4所述的显示基板，其中，所述像素驱动电路还包括：
    覆盖所述栅电极和第二电极的第三绝缘层；
    设置在所述第三绝缘层上的源电极、漏电极和第三电极，所述第三电极设置在所述共用电容区；
    覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层；
    设置在所述第五绝缘层上的像素电极和第四电极，所述第四电极设置在所述共用电容区，所述第三电极和第四电极形成相邻子像素的存储电容。
  6. 根据权利要求5所述的显示基板，其中，所述多个薄膜晶体管包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管，
    所述第一薄膜晶体管包括第一有源层、第一栅电极、第一源电极和第一漏电极，
    所述第二薄膜晶体管包括第二有源层、第二栅电极、第二源电极和第二漏电极，
    所述第三薄膜晶体管包括第三有源层、第三栅电极、第三源电极和第三漏电极。
  7. 根据权利要求6所述的显示基板，其中，在所述本子像素中，所述第一电极与所述遮光层为一体结构，所述第一电极通过过孔连接所述第一漏电极和所述第三漏电极；所述第二电极与所述第一栅电极为一体结构，所述第二电极通过过孔连接所述第二漏电极。
  8. 根据权利要求6或7所述的显示基板，其中，在所述相邻子像素中，所述第三电极通过过孔连接所述第一栅电极和所述第二漏电极，所述第四电极与所述像素电极为一体结构，所述第四电极通过过孔连接所述第一漏电极和所述第三漏电极。
  9. 根据权利要求5所述的显示基板，还包括彩膜层，所述彩膜层设置在第四绝缘层与第五绝缘层之间，所述第五绝缘层上开设有暴露出第四绝缘层的过孔，所述第四电极设置在所述过孔内。
  10. 根据权利要求5至9任一项所述的显示基板，其中，所述像素驱动电路还包括开关扫描线、补偿扫描线和数据线，在水平方向上，所述共用电容区设置在两条数据线之间，在垂直方向上，所述共用电容区设置在开关扫描线和补偿扫描线之间。
  11. 一种显示装置，包括如权利要求1至10任一项所述的显示基板。
  12. 一种显示基板的制备方法，包括：
    形成矩阵排布的多个子像素，在每个子像素形成包括多个薄膜晶体管和存储电容的像素驱动电路，其中，所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容形成在所述本子像素和所述相邻子像素的共用电容区，所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。
  13. 根据权利要求12所述的显示基板的制备方法，其中，所述本子像素的存储电容形成在所述共用电容区，包括：
    形成与像素驱动电路中的遮光层同层设置的第一电极，所述第一电极形成在所述共用电容区；
    形成覆盖所述第一电极的绝缘层；
    形成与薄膜晶体管的栅电极同层设置的第二电极，所述第二电极形成在所述共用电容区。
  14. 根据权利要求12或13所述的显示基板的制备方法，其中，所述相邻子像素的存储电容形成在所述共用电容区，包括：
    形成与薄膜晶体管的源漏电极同层设置的第三电极，所述第三电极形成在所述共用电容区；
    形成覆盖所述第三电极的绝缘层；
    形成与像素电极同层设置的第四电极，所述第四电极形成在所述共用电容区。
  15. 根据权利要求12至14任一项所述的显示基板的制备方法，其中，形成像素驱动电路包括：
    在基底上形成遮光层和第一电极，所述第一电极形成在所述共用电容区；
    形成覆盖所述遮光层和第一电极的第一绝缘层；
    在所述第一绝缘层上形成有源层；
    形成覆盖所述有源层的第二绝缘层；
    在所述第二绝缘层上形成栅电极和第二电极，所述第二电极形成在所述共用电容区，所述第一电极和第二电极形成所述本子像素的存储电容。
  16. 根据权利要求15所述的显示基板的制备方法，其中，形成像素驱动电路还包括：
    形成覆盖所述栅电极和第二电极的第三绝缘层；
    在所述第三绝缘层上形成源电极、漏电极和第三电极，所述第三电极形成在所述共用电容区；
    形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层；
    在所述第五绝缘层上形成像素电极和第四电极，所述第四电极形成在所述共用电容区，所述第三电极和第四电极形成相邻子像素的存储电容。
  17. 根据权利要求16所述的显示基板的制备方法，其中，
    所述在基底上形成遮光层和第一电极包括：在基底上形成本子像素的遮光层和相邻子像素的遮光层，所述本子像素的遮光层与第一电极为一体结构；
    所述在所述第二绝缘层上形成栅电极和第二电极包括：在所述第二绝缘层上形成本子像素的第一栅电极、第二栅电极和第三栅电极，以及相邻子像素的第一栅电极、第二栅电极和第三栅电极，所述本子像素的第一栅电极与第二电极为一体结构；
    所述在所述第五绝缘层上形成像素电极和第四电极包括：在所述第五绝缘层上形成本子像素的像素电极和相邻子像素的像素电极，所述相邻子像素的像素电极与所述第四电极为一体结构，所述相邻子像素的像素电极通过过孔连接相邻子像素的第一漏电极和第三漏电极。
  18. 根据权利要求16所述的显示基板的制备方法，其中，所述在所述第三绝缘层上形成源电极、漏电极和第三电极包括：
    在所述第三绝缘层上形成数据线、补偿线、第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和第三电极。
  19. 根据权利要求18所述的显示基板的制备方法，其中，
    所述补偿线通过过孔与连接线连接；
    所述第一源电极通过过孔与第一有源层连接，所述第一漏电极通过过孔同时与第一有源层和遮光层连接，使本子像素的第一漏电极连接第一电极；
    所述第二源电极与数据线为一体结构，所述第二源电极通过过孔与第二有源层连接，所述第二漏电极通过过孔同时与第二有源层和第一栅电极连接，使本子像素的第二漏电极连接第二电极；
    所述第三源电极通过过孔同时与连接线和第三有源层连接，所述第三漏电极通过过孔同时与第三有源层和遮光层连接，使本子像素的第三漏电极连接第一电极；
    所述第三电极通过过孔与相邻子像素的第一栅电极连接。
  20. 根据权利要求16所述的显示基板的制备方法，其中，所述形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层，包括：
    形成覆盖所述源电极、漏电极和第三电极的第四绝缘层；
    在所述第四绝缘层上形成彩膜层；
    形成覆盖所述彩膜层的第五绝缘层，在所述第五绝缘层形成暴露出第四绝缘层的过孔，所述过孔用于设置所述第四电极。
PCT/CN2020/106544 2019-08-06 2020-08-03 显示基板及其制备方法、显示装置 WO2021023147A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/288,571 US20210391402A1 (en) 2019-08-06 2020-08-03 Display Substrate, Preparation Method Therefor and Display Apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910720928.XA CN110416278B (zh) 2019-08-06 2019-08-06 显示基板及其制备方法、显示装置
CN201910720928.X 2019-08-06

Publications (1)

Publication Number Publication Date
WO2021023147A1 true WO2021023147A1 (zh) 2021-02-11

Family

ID=68366159

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/106544 WO2021023147A1 (zh) 2019-08-06 2020-08-03 显示基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US20210391402A1 (zh)
CN (1) CN110416278B (zh)
WO (1) WO2021023147A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416278B (zh) * 2019-08-06 2022-09-27 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
US11444132B2 (en) * 2019-11-29 2022-09-13 Hefei Boe Joint Technology Co., Ltd. Display substrate having gate extension portion protruding from gate electrode of first transistor, display device and manufacturing method the same thereof
CN115776830A (zh) * 2019-11-29 2023-03-10 京东方科技集团股份有限公司 显示基板及显示装置
WO2021102989A1 (zh) 2019-11-29 2021-06-03 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN111179828B (zh) * 2020-01-15 2022-10-25 合肥京东方光电科技有限公司 显示基板及其制备方法、显示装置
US11545089B2 (en) 2020-05-15 2023-01-03 Hefei Boe Joint Technology Co., Ltd. Pixel driving circuit, display panel and electronic device
CN113871417A (zh) * 2020-06-30 2021-12-31 京东方科技集团股份有限公司 显示基板和显示装置
CN111816686B (zh) * 2020-07-24 2023-05-23 合肥京东方卓印科技有限公司 一种显示基板及其制作方法、显示面板
CN114609813B (zh) * 2022-03-22 2023-07-25 深圳市华星光电半导体显示技术有限公司 阵列基板及液晶显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1680861A (zh) * 2004-12-03 2005-10-12 友达光电股份有限公司 薄膜晶体管液晶显示器、叠层储存电容器及其形成方法
CN101738804A (zh) * 2009-12-30 2010-06-16 友达光电股份有限公司 像素结构
CN105159002A (zh) * 2015-09-18 2015-12-16 友达光电股份有限公司 像素结构
CN110416278A (zh) * 2019-08-06 2019-11-05 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8158980B2 (en) * 2001-04-19 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor
KR100892945B1 (ko) * 2002-02-22 2009-04-09 삼성전자주식회사 액티브 매트릭스형 유기전계발광 표시장치 및 그 제조방법
JP4073239B2 (ja) * 2002-04-24 2008-04-09 三洋電機株式会社 表示装置
TWI392946B (zh) * 2009-12-18 2013-04-11 Au Optronics Corp 畫素結構
CN101924122B (zh) * 2010-05-20 2012-07-18 昆山工研院新型平板显示技术中心有限公司 一种有源矩阵有机发光显示器及其制造方法
KR102408898B1 (ko) * 2015-06-19 2022-06-16 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
KR20180070334A (ko) * 2016-12-16 2018-06-26 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 포함하는 표시 장치
CN107785399B (zh) * 2017-10-26 2020-02-21 武汉天马微电子有限公司 一种显示面板及显示装置
CN108550582B (zh) * 2018-05-09 2022-11-08 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
US11195863B2 (en) * 2018-09-21 2021-12-07 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel having a storage capacitor, manufacturing method the same thereof and display module having the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1680861A (zh) * 2004-12-03 2005-10-12 友达光电股份有限公司 薄膜晶体管液晶显示器、叠层储存电容器及其形成方法
CN101738804A (zh) * 2009-12-30 2010-06-16 友达光电股份有限公司 像素结构
CN105159002A (zh) * 2015-09-18 2015-12-16 友达光电股份有限公司 像素结构
CN110416278A (zh) * 2019-08-06 2019-11-05 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN110416278B (zh) 2022-09-27
CN110416278A (zh) 2019-11-05
US20210391402A1 (en) 2021-12-16

Similar Documents

Publication Publication Date Title
WO2021023147A1 (zh) 显示基板及其制备方法、显示装置
WO2022057491A1 (zh) 显示基板及其制备方法、显示装置
US9379170B2 (en) Organic light emitting diode display device and method of fabricating the same
US11489029B2 (en) Transparent display substrate including capacitor overlapping driving and switching TFTs, and manufacturing method therefor
US10566402B2 (en) Organic light-emitting diode display and method of manufacturing the same
WO2022042059A1 (zh) Oled显示面板及其制备方法、显示装置
WO2022042046A1 (zh) 显示基板及其制备方法、显示装置
KR20150079094A (ko) 유기전계발광표시장치 및 그 제조방법
US10403696B2 (en) Organic light emitting display device and method of fabricating the same
CN111179828A (zh) 显示基板及其制备方法、显示装置
US20220123073A1 (en) Display Substrate and Preparation Method thereof, and Display Apparatus
WO2021114660A1 (zh) 显示基板和显示装置
CN111682031A (zh) 一种显示基板及其制备方法、显示装置
KR101820166B1 (ko) 화이트 유기발광다이오드 표시소자 및 그 제조방법
JP2016527696A (ja) 有機発光ダイオードの陽極接続構造及びその製造方法
WO2022017050A1 (zh) 显示基板及其制备方法、显示装置
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
WO2022222070A1 (zh) 显示基板及其制备方法、显示装置
WO2022178827A1 (zh) 显示基板及其制备方法、显示装置
KR20160060835A (ko) 유기발광다이오드 표시장치 및 그 제조방법
KR20160054139A (ko) 유기전계발광표시장치 및 그 제조방법
US20240057388A1 (en) Display Substrate and Preparation Method thereof, and Display Apparatus
WO2022222084A1 (zh) 显示基板及其制备方法、显示装置
US20230180521A1 (en) Display Substrate, Preparation Method thereof, and Display Apparatus
WO2023184235A1 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20849897

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20849897

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20849897

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 02/02/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20849897

Country of ref document: EP

Kind code of ref document: A1