WO2021023147A1 - 显示基板及其制备方法、显示装置 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
- H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/30—Devices specially adapted for multicolour light emission
- H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
Definitions
- the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display device.
- OLED Organic Light Emitting Diode
- PM passive matrix
- AM active matrix
- TFT Thin Film Transistor
- a display substrate including a plurality of sub-pixels arranged in a matrix, each sub-pixel is provided with a pixel driving circuit including a plurality of thin film transistors and a storage capacitor, and among the plurality of sub-pixels
- the storage capacitor of the sub-pixel and the storage capacitor of the adjacent sub-pixel adjacent to the sub-pixel are arranged in the common capacitor area of the sub-pixel and the adjacent sub-pixel, and the storage capacitor of the sub-pixel and the phase
- the storage capacitors of adjacent sub-pixels are stacked.
- the storage capacitor of the sub-pixel includes: a first electrode provided on the same layer as the light shielding layer in the pixel driving circuit, an insulating layer covering the first electrode, and The gate electrode of the thin film transistor is the second electrode arranged in the same layer.
- the storage capacitors of the adjacent sub-pixels include: a third electrode provided in the same layer as the source and drain electrodes of the thin film transistor, an insulating layer covering the third electrode, The fourth electrode is provided on the same layer as the pixel electrode.
- the pixel driving circuit includes: a substrate; a light shielding layer and a first electrode provided on the substrate, the first electrode being provided in the common capacitor region; The light-shielding layer and the first insulating layer of the first electrode; the active layer arranged on the first insulating layer; the second insulating layer covering the active layer; the gate arranged on the second insulating layer An electrode and a second electrode, the second electrode is arranged in the common capacitor area, and the first electrode and the second electrode form a storage capacitor of the sub-pixel.
- the pixel driving circuit further includes: a third insulating layer covering the gate electrode and the second electrode; source and drain electrodes provided on the third insulating layer And a third electrode, the third electrode is arranged on the common capacitance area; a fourth insulating layer and a fifth insulating layer covering the source electrode, the drain electrode and the third electrode; arranged on the fifth insulating layer
- the fourth electrode is arranged in the common capacitor area, and the third electrode and the fourth electrode form a storage capacitor of adjacent sub-pixels.
- the plurality of thin film transistors includes a first thin film transistor, a second thin film transistor, and a third thin film transistor
- the first thin film transistor includes a first active layer, a first gate Electrode, a first source electrode and a first drain electrode
- the second thin film transistor includes a second active layer, a second gate electrode, a second source electrode and a second drain electrode
- the third thin film transistor includes a third The source layer, the third gate electrode, the third source electrode and the third drain electrode.
- the first electrode and the light-shielding layer have an integral structure, and the first electrode connects the first drain electrode and the light-shielding layer through a via hole.
- the third drain electrode; the second electrode and the first gate electrode are an integral structure, and the second electrode is connected to the second drain electrode through a via hole.
- the third electrode connects the first gate electrode and the second drain electrode through a via hole, and the fourth electrode is connected to the
- the pixel electrode has an integral structure, and the fourth electrode is connected to the first drain electrode and the third drain electrode through a via hole.
- the display substrate according to any one of the foregoing embodiments further includes a color filter layer, the color filter layer is disposed between the fourth insulating layer and the fifth insulating layer, and the fifth insulating layer is provided with exposing the fourth insulating layer.
- the fourth electrode is arranged in the via hole.
- the pixel driving circuit further includes a switch scan line, a compensation scan line, and a data line.
- the shared capacitor area is arranged between the two data lines.
- the shared capacitance area is arranged between the switch scan line and the compensation scan line.
- a display device including the display substrate of any one of the foregoing embodiments.
- a method for manufacturing a display substrate including: forming a plurality of sub-pixels arranged in a matrix, and forming a pixel driving circuit including a plurality of thin film transistors and a storage capacitor in each sub-pixel, wherein, The storage capacitor of the sub-pixel of the plurality of sub-pixels and the storage capacitor of the adjacent sub-pixel adjacent to the sub-pixel are formed in the common capacitor area of the sub-pixel and the adjacent sub-pixel. The storage capacitor of the adjacent sub-pixel and the storage capacitor of the adjacent sub-pixel are stacked.
- the storage capacitor of the sub-pixel is formed in the common capacitor area, including: forming a first electrode arranged in the same layer as the light shielding layer in the pixel driving circuit , The first electrode is formed in the common capacitor region; an insulating layer covering the first electrode is formed; a second electrode arranged in the same layer as the gate electrode of the thin film transistor is formed, and the second electrode is formed in the common Capacitance area.
- the storage capacitors of the adjacent sub-pixels are formed in the common capacitor area, including: forming a third layer disposed on the same layer as the source and drain electrodes of the thin film transistor. An electrode, the third electrode is formed in the common capacitor area; an insulating layer covering the third electrode is formed; a fourth electrode is formed in the same layer as the pixel electrode, and the fourth electrode is formed in the common capacitor area .
- forming a pixel driving circuit includes: forming a light shielding layer and a first electrode on a substrate, the first electrode being formed in the common capacitor region; The light shielding layer and the first insulating layer of the first electrode; forming an active layer on the first insulating layer; forming a second insulating layer covering the active layer; forming a gate electrode on the second insulating layer And a second electrode, the second electrode is formed in the common capacitor area, and the first electrode and the second electrode form the storage capacitor of the sub-pixel.
- forming a pixel driving circuit further includes: forming a third insulating layer covering the gate electrode and the second electrode; and forming a source on the third insulating layer.
- An electrode, a drain electrode, and a third electrode, the third electrode is formed in the common capacitance region; a fourth insulating layer and a fifth insulating layer are formed to cover the source electrode, the drain electrode, and the third electrode;
- a pixel electrode and a fourth electrode are formed on the five insulating layers, the fourth electrode is formed in the common capacitor area, and the third electrode and the fourth electrode form a storage capacitor of adjacent sub-pixels.
- the forming the light-shielding layer and the first electrode on the substrate includes: forming the light-shielding layer of the sub-pixel and the light-shielding layer of the adjacent sub-pixel on the substrate, and the light-shielding layer of the sub-pixel and the first electrode have an integral structure;
- the forming the gate electrode and the second electrode on the second insulating layer includes: forming the first gate electrode, the second gate electrode and the third gate electrode of the sub-pixel on the second insulating layer, and the adjacent sub-pixels.
- the first gate electrode, the second gate electrode and the third gate electrode of the pixel, and the first gate electrode and the second electrode of the sub-pixel have an integral structure;
- the forming the pixel electrode and the fourth electrode on the fifth insulating layer includes: forming the pixel electrode of the sub-pixel and the pixel electrode of the adjacent sub-pixel on the fifth insulating layer, and the pixel of the adjacent sub-pixel
- the electrode and the fourth electrode have an integral structure, and the pixel electrodes of the adjacent sub-pixels are connected to the first drain electrode and the third drain electrode of the adjacent sub-pixels through via holes.
- the forming a source electrode, a drain electrode, and a third electrode on the third insulating layer includes: forming a data line on the third insulating layer , Compensation line, first source electrode, first drain electrode, second source electrode, second drain electrode, third source electrode, third drain electrode, and third electrode.
- the compensation line is connected to the connection line through a via;
- the first source electrode is connected to the first active layer through a via, and the first The drain electrode is simultaneously connected to the first active layer and the light-shielding layer through the via hole, so that the first drain electrode of the sub-pixel is connected to the first electrode;
- the second source electrode and the data line are in an integrated structure, and the second source electrode passes through
- the via hole is connected to the second active layer, and the second drain electrode is simultaneously connected to the second active layer and the first gate electrode through the via hole, so that the second drain electrode of the sub-pixel is connected to the second electrode;
- the third The source electrode is simultaneously connected to the connection line and the third active layer through the via hole, and the third drain electrode is simultaneously connected to the third active layer and the light shielding layer through the via hole, so that the third drain electrode of the sub-pixel is connected to the first electrode ;
- the third electrode is connected to the first gate electrode of an adjacent sub
- the forming the fourth insulating layer and the fifth insulating layer covering the source electrode, the drain electrode, and the third electrode includes: The fourth insulating layer of the electrode, the drain electrode, and the third electrode; forming a color filter layer on the fourth insulating layer; forming a fifth insulating layer covering the color filter layer, and forming an exposed layer on the fifth insulating layer A via hole of the fourth insulating layer, where the via hole is used to arrange the fourth electrode.
- FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit
- FIG. 2 is a schematic diagram of the structure of a sub-pixel in a bottom emission type OLED
- FIG. 3 is a schematic diagram showing that two sub-pixels on a substrate share a capacitor area in an embodiment of the disclosure
- FIG. 4 is a schematic diagram showing a stacked arrangement of two sub-pixel storage capacitors on a substrate according to an embodiment of the disclosure
- FIG. 5 is a schematic structural diagram of an exemplary embodiment of a display substrate of the present disclosure.
- Figure 6 is a cross-sectional view taken along the line A-A in Figure 5;
- FIG. 7 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after the light shielding layer and the first electrode pattern are formed;
- Fig. 8 is a sectional view taken along the line A-A in Fig. 7;
- FIG. 9 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after an active layer pattern is formed;
- Fig. 10 is a sectional view taken along the line A-A in Fig. 9;
- FIG. 11 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after forming gate electrode and second electrode patterns
- Figure 12 is a cross-sectional view along the A-A direction in Figure 11;
- FIG. 13 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after a third insulating layer pattern is formed;
- Figure 14 is a cross-sectional view taken along the line A-A in Figure 13;
- FIG. 15 is a schematic diagram of the embodiment shown in FIG. 5 of the present disclosure after source and drain electrodes and third electrode patterns are formed;
- Figure 16 is a cross-sectional view taken along the line A-A in Figure 15;
- FIG. 17 is a schematic diagram of the embodiment shown in FIG. 5 of the disclosure after forming a fifth insulating layer pattern
- Figure 18 is a cross-sectional view taken along the line A-A in Figure 17;
- FIG. 19 is a schematic diagram of the embodiment shown in FIG. 5 of the present disclosure after the pixel electrode and the fourth electrode pattern are formed;
- Figure 20 is a cross-sectional view taken along the line A-A in Figure 19;
- 21 is a schematic diagram of an equivalent circuit of the left sub-pixel of the embodiment shown in FIG. 5 of the disclosure.
- FIG. 22 is a schematic diagram of an equivalent circuit of the sub-pixel on the right side of the embodiment shown in FIG. 5 of the present disclosure.
- FIG. 23 is a schematic diagram of pixel arrangement of the embodiment shown in FIG. 5 of the present disclosure.
- FIG. 24 is a schematic structural diagram of another exemplary embodiment of a display substrate of the present disclosure.
- GN switch scan line
- SN compensation scan line
- LN Connecting line
- DN Data line
- SE Compensation line
- the pixel aperture ratio is one of the parameters and also a factor for improving the resolution of the display device, for example, for bottom emission OLEDs.
- the bottom emission type OLED has a light-emitting area and a driving circuit area in each sub-pixel.
- the light-emitting structure is arranged in the light-emitting area.
- Multiple TFTs and storage capacitors (C ST ) are arranged in parallel in the driving circuit area.
- the storage capacitor usually occupies a larger area.
- the size of sub-pixels is getting smaller and smaller, so that the proportion of the pixel area occupied by the driving circuit area is getting larger and larger, resulting in a significant reduction in pixel aperture ratio.
- the pixel aperture ratio is usually about 40%, and when the above structure is applied to a high PPI, the pixel aperture ratio is 10%-20%. Practical use shows that low pixel aperture ratio may cause problems such as increased power consumption and attenuation of the life of luminescent materials.
- FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit, which illustrates a 3T1C driving structure.
- the pixel driving circuit is electrically connected to the switching scan line GN, the compensation scan line SN, the data line DN, the power supply line VDD, and the compensation line SE.
- the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C ST .
- the first transistor T1 may be a driving transistor
- the second transistor T2 may be a switching transistor
- the third transistor T3 may be a compensation transistor.
- the gate electrode of the first transistor T1 is connected to the second electrode of the second transistor T2 and the first electrode of the storage capacitor C ST , the first electrode of the first transistor T1 is connected to the first power line VDD, and the first transistor T1 The second electrode of is connected to the second electrode of the storage capacitor C ST and the second electrode of the third transistor T3.
- the gate electrode of the second transistor T2 is connected to the scan line GN
- the first electrode of the second transistor T2 is connected to the data line DN
- the gate electrode of the third transistor T3 is connected to the compensation scan line SN
- the first electrode of the third transistor T3 The pole is connected to the compensation line SE.
- the anode of the OLED is connected to the second electrode of the first transistor T1
- the cathode of the OLED is connected to the low voltage line VSS, and is configured to emit light of corresponding brightness in response to the current of the second electrode of the first transistor T1.
- the third transistor T3 can extract the threshold voltage Vth and mobility of the first transistor T1 in response to the timing of compensation to compensate the threshold voltage Vth, and the storage capacitor C ST is used to maintain the N1 node and the N2 node in a frame of light emission period. Voltage, so higher storage capacity is required.
- FIG. 2 is a schematic diagram of the structure of a sub-pixel in a bottom emission type OLED.
- each sub-pixel is provided with a light-emitting area and a driving circuit area.
- the driving circuit area includes a TFT area and a capacitor area.
- the light-emitting structure is arranged in the light-emitting area.
- a plurality of TFTs driving the light-emitting structure are arranged in the TFT area.
- the electrode plates are arranged in the capacitor area, and the electrode plates of a plurality of TFTs and storage capacitors are arranged side by side.
- the storage capacitor is composed of a shielding layer and a conductive active layer as the two electrode plates of the storage capacitor.
- the electrode plate needs a large area, that is, the capacitor area occupies a large area. Therefore, when the above structure is applied to high PPI, the pixel aperture ratio is very low.
- embodiments of the present disclosure provide a display substrate.
- the display substrate of the embodiment of the present disclosure includes a plurality of sub-pixels arranged in a matrix, and each sub-pixel is provided with a pixel driving circuit including a plurality of thin film transistors and a storage capacitor.
- the storage capacitor of the sub-pixel pixel driving circuit and the adjacent sub-pixel pixel driving circuit The storage capacitor is arranged in the common capacitance area of the two sub-pixels, and the storage capacitor of the pixel driving circuit of the sub-pixel and the storage capacitor of the adjacent sub-pixel pixel driving circuit are stacked.
- FIG. 3 is a schematic diagram showing that two sub-pixels share a capacitor area on a substrate according to an embodiment of the disclosure
- FIG. 4 is a schematic diagram showing that two sub-pixel storage capacitors are stacked on a substrate according to an embodiment of the disclosure.
- the two sub-pixels are the current sub-pixel and adjacent sub-pixels.
- Each sub-pixel is provided with a light-emitting area and a TFT area.
- the capacitor areas of the two sub-pixels together form a common capacitor area, which constitutes the electrode of each sub-pixel storage capacitor.
- the boards are all arranged in the shared capacitance area.
- the electrode plate constituting the storage capacitor of the sub-pixel pixel driving circuit includes a first electrode and a second electrode.
- the first electrode and the light shielding layer are provided in the same layer, and the second electrode is provided in the same layer as the gate electrode of the thin film transistor.
- the first electrode and the second electrode are arranged in the common capacitance area of the two sub-pixels.
- the electrode plates constituting the storage capacitor of the adjacent sub-pixel pixel driving circuit include a third electrode and a fourth electrode.
- the third electrode is arranged in the same layer as the source and drain electrodes of the thin film transistor, the fourth electrode is arranged in the same layer as the pixel electrode, and the third electrode is arranged in the same layer as the pixel electrode.
- the fourth electrode are arranged in the common capacitance area of the two sub-pixels.
- the embodiment of the present disclosure proposes a display substrate, which realizes sharing of capacitor regions and stacking of storage capacitors by using a laminated structure in the display substrate.
- the present disclosure combines the capacitor regions of two adjacent sub-pixels as a shared capacitor region of the two sub-pixels.
- the electrode plates constituting the storage capacitor of each sub-pixel are arranged in the shared capacitor region, so that the storage capacitors of the two sub-pixels form a stack.
- the structure greatly reduces the area of each sub-pixel capacitance area, reduces the proportion of the pixel area occupied by the driving circuit area, effectively improves the pixel aperture ratio, is suitable for high PPI display, and reduces power consumption.
- FIG. 5 is a schematic structural diagram of an exemplary embodiment of the display substrate of the present disclosure.
- FIG. 6 is a cross-sectional view along the A-A direction in FIG. 5, illustrating the structure of two adjacent sub-pixels of the bottom emission display substrate.
- the two adjacent sub-pixels may be a red sub-pixel and a green sub-pixel, or may be a blue sub-pixel and a green sub-pixel, or may be a red sub-pixel and a blue sub-pixel.
- the left sub-pixel in FIG. 5 refers to the current sub-pixel
- the right sub-pixel in FIG. 5 refers to the adjacent sub-pixel.
- the display substrate provided by this embodiment may include:
- the light-shielding layer 11 and the first electrode 12 are arranged on the substrate 10; wherein the first electrode 12 is arranged in the common capacitance area of the two sub-pixels, each sub-pixel is provided with a light-shielding layer 11, and the light-shielding layer 11 of the left sub-pixel It is connected to the first electrode 12 and has an integrated structure, and the light shielding layer 11 of the right sub-pixel is separately provided;
- the first insulating layer 13 covers the light shielding layer 11 and the first electrode 12;
- the first active layer 14, the second active layer 24, and the third active layer 34 are arranged on the first insulating layer 13; wherein the two sub-pixels are both provided with the first active layer 14, the second active layer 24 and the third active layer 34;
- the second gate electrode 26 of the two sub-pixels is integrated with the switching scan line GN
- the third gate electrode 36 is integrated with the compensation scan line SN
- the first gate electrode 16 and the second electrode 17 of the left sub-pixel Connected and integrated structure, the first gate electrode 16 of the right sub-pixel is separately arranged;
- the third insulating layer 20 covers the switching scan line GN, the compensation scan line SN, the connecting line LN, the first gate electrode 16, the second gate electrode 26, the third gate electrode 36 and the second electrode 17, and a plurality of Via holes
- multiple via holes include: the first via hole V1 in the two sub-pixels exposing the first gate electrode 16 and the second active layer 24 at the same time, and the second via hole in the right sub-pixel exposing the first gate electrode 16 Via V2, the third via V3 and the fourth via V4 at both ends of the first active layer 14 are exposed in the two sub-pixels, and the fifth via V5 of the second active layer 24 is exposed in the two sub-pixels.
- the connecting line LN and the sixth via hole V6 of the third active layer 34 are exposed in each sub-pixel, the seventh via hole V7 of the third active layer 34 is exposed in two sub-pixels, and the light shielding layer is exposed in two sub-pixels
- the eighth via V8 and the ninth via V9 of 11, the tenth via V10 of the connection line LN is exposed in the right sub-pixel; wherein, the first via V1 and the sixth via V6 are both double connection holes,
- the first via hole V1 simultaneously exposes the first gate electrode 16 and the second active layer 24, and the sixth via hole V6 simultaneously exposes the connecting line LN and the third active layer 34;
- the data line DN, the compensation line SE, the first source electrode 18, the first drain electrode 19, the second source electrode 28, the second drain electrode 29, the third source electrode 38, the third drain electrode 39 and the third electrode 30 are arranged On the third insulating layer 20, the first source electrode 18 of the two sub-pixels is connected to the first active layer 14 through the fourth via hole V4, and the first drain electrode 19 is connected to the first active layer 14 through the third via hole V3.
- the second source electrode 28 of the two sub-pixels is integrated with the data line DN, and is connected to the second active layer 24 through the fifth via V5, and the second leakage
- the pole 29 is simultaneously connected to the second active layer 24 and the first gate electrode 16 through the first via hole V1; the third source electrode 38 of the two sub-pixels is simultaneously connected to the connecting line LN and the third active layer through the sixth via hole V6. 34.
- the third drain electrode 39 is connected to the third active layer 34 through the seventh via hole V7, and is also connected to the light shielding layer 11 through the eighth via hole V8; the third electrode 30 is arranged in the common capacitance area of the two sub-pixels, It is connected to the first gate electrode 16 of the right sub-pixel through the second via hole V2; the compensation line SE is connected to the connection line LN through the tenth via hole V10;
- the fourth insulating layer 31 and the fifth insulating layer 33 cover the aforementioned structure, on which are formed an eleventh via V10 and a twelfth via V11, and the eleventh via V11 is located at the third drain electrode in the two sub-pixels Position 39 exposes the surface of the third drain electrode 39, and the twelfth via V12 is located at the position of the third electrode 30, exposing the surface of the fourth insulating layer 31;
- the pixel electrode 40 and the fourth electrode 35 are arranged on the fifth insulating layer 33.
- the pixel electrodes 40 of the two sub-pixels are connected to the third drain electrode 39 through the eleventh via hole V11.
- the fourth electrode 35 is arranged on the two sub-pixels.
- the common capacitor area is located in the twelfth via hole V12 and is an integral structure with the pixel electrode 40 of the right sub-pixel.
- the first electrode and the second electrode are arranged in the common capacitor area of the two sub-pixels to form the storage capacitor of the left sub-pixel
- the third electrode and the fourth electrode are arranged in the common capacitor area of the two sub-pixels to form the right
- the storage capacitor of the side sub-pixel and the storage capacitor of the left sub-pixel are located under the storage capacitor of the right sub-pixel, forming a stacked structure of the storage capacitor of the left sub-pixel and the storage capacitor of the right sub-pixel.
- the technical solution of this embodiment is further described below through the preparation process of the display substrate of this embodiment.
- the "patterning process” mentioned in this embodiment includes treatments such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are some preparation processes.
- the deposition may use sputtering, evaporation, chemical vapor deposition and other processes, and the coating may use a coating process, which is not limited here.
- “thin film” refers to a layer of film made by depositing a certain material on a substrate or by other processes. If the "film” does not require a patterning process during the entire production process, the “film” can also be referred to as a "layer”. If the "thin film” needs a patterning process during the entire production process, it is called a "thin film” before the patterning process and a "layer” after the patterning process.
- the "layer” after the patterning process contains at least one "pattern”.
- Forming the light shielding layer and the first electrode pattern includes: depositing a first metal film on a substrate, patterning the first metal film through a patterning process, and forming a light shielding layer 11 and a first electrode 12 pattern on the substrate 10, as shown in FIGS. 7 and As shown in Fig. 8, Fig. 8 is a cross-sectional view taken along the line AA in Fig. 7.
- each sub-pixel is provided with a light-shielding layer 11, and the first electrode 12 is provided in the common capacitance area of the two sub-pixels, that is, the first electrode 12 is provided between the two light-shielding layers 11, and the The light shielding layer 11 and the first electrode 12 are connected to form an integral structure.
- the first electrode 12 in this embodiment is used to form the bottom electrode plate of the storage capacitor of the left sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the first electrode 12 occupies the capacitance of the left sub-pixel. Area and the capacitance area of the right sub-pixel.
- the storage capacitor of the left sub-pixel is called the first storage capacitor.
- the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum niobium alloy (AlNd), molybdenum niobium Alloy (MoNb), etc., can be a multilayer metal, such as Mo/Cu/Mo, etc., or a stack structure formed by metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
- metal materials such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc.
- alloy materials of the foregoing metals such as aluminum niobium alloy (AlNd), molybdenum niobium Alloy (MoNb), etc.
- AlNd aluminum niobium alloy
- MoNb molybdenum niobium Alloy
- Forming the pattern of the active layer includes: sequentially depositing a first insulating film and an active film on the substrate on which the aforementioned pattern is formed, and patterning the active film through a patterning process to form a covering light shielding layer 11 and a first electrode 12
- the pattern of the first insulating layer 13, and the first active layer 14, the second active layer 24, and the third active layer 34 formed on the first insulating layer 13, as shown in FIGS. 9 and 10, 10 is a cross-sectional view in the AA direction in FIG. 9. Wherein, the first active layer 14, the second active layer 24, and the third active layer 34 are formed in the two sub-pixels.
- the first active layer 14 serves as the active layer of the driving TFT (the first transistor T1)
- the second active layer 24 serves as an active layer of the switching TFT (second transistor T2)
- the third active layer 34 serves as an active layer of the compensation TFT (third transistor T3).
- the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si)
- a-IGZO amorphous indium gallium zinc oxide
- ZnON zinc oxynitride
- IZTO indium zinc tin oxide
- a-Si amorphous silicon
- p-Si polysilicon
- Various materials such as hexathiophene or polythiophene, that is, this embodiment is also applicable to display substrates based on top gate TFTs manufactured based on oxide (Oxide) technology, silicon technology
- the first insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), or can be made of high-dielectric constant High-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx) ), tantalum oxide (TaOx), etc., can be single layer, multiple layers or composite layers. Generally, the first insulating layer 13 is referred to as a buffer layer.
- Forming the gate electrode and the second electrode pattern includes: sequentially depositing a second insulating film and a second metal film on the substrate with the aforementioned pattern, first coating a layer of photoresist on the second metal film, passing through a mask, Exposure and development to form a photoresist pattern, use an etching process to etch the second metal film, and then use the second metal film as a mask to self-align and etch the second insulating film downward to form a pattern of the second insulating layer 15, and The pattern of the switch scan line GN, the compensation scan line SN, the connection line LN, the first gate electrode 16, the second gate electrode 26, the third gate electrode 36 and the second electrode 17 arranged on the second insulating layer 15, as shown in FIG.
- Fig. 12 is a cross-sectional view taken along the line AA in Fig. 11. Subsequently, the exposed first active layer 14, the second active layer 24, and the third active layer 34 are subjected to a conductive treatment using the scan line and the gate electrode pattern as a mask.
- the second electrode 17 is arranged in the common capacitance area of the two sub-pixels, and is arranged between the first gate electrodes 16 of the two sub-pixels, and its position corresponds to the position of the first electrode 12, that is, the second electrode 17
- the orthographic projection on the substrate is within the orthographic projection range of the first electrode 12 on the substrate.
- the first gate electrode 16, the second gate electrode 26, and the third gate electrode 36 are provided in the two sub-pixels.
- the second gate electrode 26 of the two sub-pixels is an integrated structure connected with the switch scan line GN.
- the tri-gate electrode 36 is an integral structure connected to the compensation scan line SN.
- the first gate electrode 16 and the second electrode 17 in the left sub-pixel are connected to form an integral structure.
- the second electrode 17 in this embodiment is used to form the upper electrode plate of the storage capacitor of the left sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the second electrode 17 occupies the capacitance of the left sub-pixel. Area and the capacitance area of the right sub-pixel.
- the switching scan line GN is used to provide the second gate electrode 26 of the two sub-pixels with an on/off signal to control the switching TFT
- the compensation scan line SN is used to provide the third gate electrode 36 of the two sub-pixels with a control to turn on/off the compensation TFT.
- the signal connection line LN serves as the source electrode of the compensation TFT in the two sub-pixels, and will be connected to the compensation line SE formed later.
- the common capacitance area of the two sub-pixels is arranged between the switching scan line GN and the compensation scan line SN.
- the second metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the foregoing metals, such as aluminum-niobium alloy (AlNd, molybdenum-niobium alloy) (MoNb), etc., can be a multilayer metal, such as Mo/Cu/Mo, etc., or a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.
- the second insulating film can be silicon oxide ( SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.
- High k materials can also be used, such as aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., which can be a single layer, Multi-layer or composite layer.
- AlOx aluminum oxide
- HfOx hafnium oxide
- TaOx tantalum oxide
- the second insulating layer 15 is called a gate insulating (GI) layer.
- Forming the third insulating layer pattern includes: depositing a third insulating film on the substrate formed with the aforementioned pattern, and patterning the third insulating film through a patterning process to form a pattern of the third insulating layer 20 covering the aforementioned structure.
- the third insulating layer A plurality of via holes are opened on 20, and the plurality of via holes are respectively: a first via hole V1 formed in the two sub-pixels that simultaneously exposes the first gate electrode 16 and the second active layer 24, and is formed in the right sub-pixel
- the second via hole V2 exposing the first gate electrode 16, the third via hole V3 and the fourth via hole V4 formed in the two sub-pixels exposing both ends of the first active layer 14, the exposed portion formed in the two sub-pixels
- the fifth via hole V5 of the second active layer 24 is formed, and the connecting line LN and the sixth via hole V6 of the third active layer 34 are exposed at the same time when the two sub-pixels are formed.
- the via hole V10 is shown in FIG. 13 and FIG. 14, and FIG. 14 is a cross-sectional view along the AA direction in FIG. 13.
- the first via hole V1 formed in the two sub-pixels is a via hole exposing the first gate electrode 16 and the second active layer 24 at the same time.
- the via via hole is composed of two half holes, and one half hole is exposed. The first gate electrode 16 is exposed, and the second active layer 24 is exposed by the other half hole.
- the sixth via hole V6 in the two sub-pixels is a via hole that simultaneously exposes the connecting line LN and the third active layer 34. One half hole exposes the connecting line LN, and the other half hole exposes the third active layer. 34. Setting the first via hole V1 and the sixth via hole V6 as transfer via holes can reduce the occupied area of the driving circuit area and increase the aperture ratio.
- the third insulating layer 20 can be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., and can also be made of high-k materials, such as aluminum oxide (AlOx), hafnium oxide (HfOx) , Tantalum Oxide (TaOx), etc., can be single layer, multilayer or composite layer.
- the third insulating layer 20 is referred to as an interlayer insulation (ILD) layer.
- ILD interlayer insulation
- Forming the source and drain electrodes and the third electrode pattern includes: depositing a third metal film on the substrate with the aforementioned pattern, patterning the third metal film through a patterning process, and forming a power supply line (not shown) on the third insulating layer 20 Out), data line DN, compensation line SE, first source electrode 18, first drain electrode 19, second source electrode 28, second drain electrode 29, third source electrode 38, third drain electrode 39, and third electrode 30 pattern, as shown in FIG. 15 and FIG. 16, FIG. 16 is a cross-sectional view in the AA direction in FIG. among them,
- the data line DN is arranged outside the two sub-pixels, so that the common capacitance area of the two sub-pixels is located between the two data lines DN.
- Each data line DN provides a data signal for the switching TFT of the adjacent sub-pixel, and the compensation line SE is arranged on the data line.
- the outer side of the line DN is connected to the connection line LN through the tenth via V10 to provide compensation signals for the compensation TFTs of the two sub-pixels between the two data lines DN.
- the first source electrode 18 of the two sub-pixels is an integrated structure connected with a power supply line (not shown), and the first source electrode 18 of each sub-pixel passes through the fourth via hole V4 and is connected to the first active layer 14 of the sub-pixel.
- One end is connected, the first drain electrode 19 of each sub-pixel is connected to the other end of the first active layer 14 of the sub-pixel through the third via hole V3 on the one hand, and is connected to the sub-pixel through the ninth via hole V9 on the other hand.
- the light shielding layer 11 is connected.
- the first drain electrode 19 of the left sub-pixel is connected to the first electrode 12, that is, the first drain electrode of the left sub-pixel 19 is connected to the bottom electrode plate forming the first storage capacitor, and the first drain electrode 19 and the first electrode 12 in the left sub-pixel have the same potential.
- the second source electrode 28 of each sub-pixel is an integral structure connected to the data line DN of the sub-pixel, and the second source electrode 28 of each sub-pixel passes through the fifth via hole V5 and is connected to the second active layer 24 of the sub-pixel.
- One end is connected, the second drain electrode 29 of each sub-pixel is connected to the other end of the second active layer 24 of the sub-pixel on the one hand through the first via hole V1, and to the first gate electrode 16 of the sub-pixel on the other hand. Connection, that is, the second drain electrode 29 is simultaneously connected to the second active layer 24 and the first gate electrode 16 through the first via V1.
- the second drain electrode 29 of the left sub-pixel is connected to the second electrode 17, that is, the second The drain electrode 29 is connected to the upper plate forming the first storage capacitor, and the potentials of the first gate electrode 16, the second drain electrode 29 and the second electrode 17 of the left sub-pixel are the same.
- the third source electrode 38 of each sub-pixel is connected to the connecting line LN on the one hand through the sixth via hole V6, and is connected to one end of the third active layer 34 of the sub-pixel on the other hand, and the third drain electrode of each sub-pixel 39 is connected to the other end of the third active layer 34 of the sub-pixel through a seventh via hole V7 on the one hand, and connected to the light shielding layer 11 of the sub-pixel through an eighth via hole V8 on the other hand. Since the third source electrode 38 is connected to the connecting line LN and the connecting line LN is connected to the compensation line SE, the compensation signal of the compensation line SE is applied to the third source electrode 38.
- the third drain electrode 39 of the left sub-pixel is connected to the light-shielding layer 11, and the light-shielding layer 11 is an integrated structure connected to the first electrode 12, it is equivalent to the third drain electrode 39 and the first electrode 12 of the left sub-pixel. Connection, that is, the third drain electrode 39 of the left sub-pixel is connected to the lower electrode plate forming the first storage capacitor, the first drain electrode 19 of the left sub-pixel, the third drain electrode 39 of the left sub-pixel, and the first electrode The potential of 12 is the same.
- the main part of the third electrode 30 is arranged in the common capacitance area of the two sub-pixels, and its position corresponds to the position of the second electrode 17, that is, the orthographic projection of the main part of the third electrode 30 on the substrate is located on the second electrode 17 on the substrate. Within the range of the orthographic projection.
- the right protruding part of the third electrode 30 is connected to the first gate electrode 16 of the right sub-pixel through the second via hole V2. Since the first gate electrode 16 of the right sub-pixel is connected to the second drain electrode 29, it is equivalent to that the third electrode 30 is connected to the second drain electrode 29 of the right sub-pixel, and the first gate electrode 16 of the right sub-pixel is connected to The second drain electrode 29 and the third electrode 30 of the right sub-pixel have the same potential.
- the third electrode 30 of this embodiment is used to form the bottom electrode plate of the storage capacitor of the right sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the third electrode 30 occupies the capacitance of the right sub-pixel. Area and the capacitance area of the left sub-pixel.
- the storage capacitor of the right sub-pixel is called the second storage capacitor.
- Forming the fourth insulating layer and the fifth insulating layer pattern includes: first depositing a fourth insulating film on the substrate formed with the aforementioned pattern to form the fourth insulating layer 31 covering the aforementioned structure, and then coating the fifth insulating film, using the first The fifth insulating film is used as a photoresist, and the fourth insulating layer 31 is etched through masking, exposure and development to form a pattern of the fifth insulating layer 33 covering the foregoing structure.
- the fifth insulating layer 33 is formed with the eleventh insulating layer.
- the hole V11 and the twelfth via hole V12 wherein the eleventh via hole V11 is located at the position of the third drain electrode 39 in the two sub-pixels, and the fifth insulating layer 33 and the fourth insulating layer 33 in the two eleventh via holes V11
- the insulating layer 31 is removed, and the surface of the third drain electrode 39 is exposed.
- the twelfth via hole V12 is located at the position of the third electrode 30, and the fifth insulating layer 33 in the twelfth via hole V12 is removed, exposing the surface of the fourth insulating layer 31, as shown in FIGS. 17 and 18, 18 is a cross-sectional view along the AA direction in FIG. 17.
- the fourth insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or high-k materials such as aluminum oxide (AlOx), hafnium oxide (HfOx), Tantalum oxide (TaOx), etc., can be a single layer, multiple layers or composite layers.
- the material of the fifth insulating film includes, but is not limited to, polysiloxane-based materials, acrylic-based materials, or polyimide-based materials.
- the fourth insulating layer 31 is referred to as a passivation (PVX) layer
- the fifth insulating layer 33 is referred to as a flattening (PNL) layer.
- the pixel electrode and the fourth electrode pattern are formed.
- Forming the pixel electrode and the fourth electrode pattern includes: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film through a patterning process to form the pattern of the pixel electrode 40 and the fourth electrode 35.
- the pixel electrode 40 is connected to the third drain electrode 39 of the left sub-pixel through the eleventh via hole V11, and the pixel electrode 40 of the right sub-pixel is connected to the third drain electrode 39 of the right sub-pixel through the eleventh via V11 ,
- the fourth electrode 35 is formed in the twelfth via hole V12, and is an integrated structure connected with the pixel electrode 40 of the right sub-pixel, as shown in FIGS. 19 and 20, and FIG. 20 is a cross-section along the AA direction in FIG. Figure.
- the transparent conductive film can be indium tin oxide (ITO) or indium zinc oxide (IZO).
- the fourth electrode 35 is arranged in the common capacitance area of the two sub-pixels, and its position corresponds to the position of the third electrode 30, that is, the orthographic projection of the fourth electrode 35 on the substrate is located on the third electrode 30 on the substrate. Within the orthographic projection range.
- the fourth electrode 35 in this embodiment is used to form the upper electrode plate of the storage capacitor of the right sub-pixel, it is arranged in the common capacitance area of the two sub-pixels, that is, the fourth electrode 35 occupies the capacitance of the right sub-pixel. Area and the capacitance area of the left sub-pixel.
- the third electrode 30 is connected to the first gate electrode 16 of the right sub-pixel, and the first gate electrode 16 of the right sub-pixel is connected to the second drain electrode 29, it is equivalent to the third electrode 30 and the right sub-pixel.
- the second drain electrode 29 is connected, and the potential of the first gate electrode 16 of the right sub-pixel and the second drain electrode 29 of the right sub-pixel is the same as the potential of the third electrode 30.
- the pixel electrode 40 of the right sub-pixel is connected to the third drain electrode 39 of the right sub-pixel, and the fourth electrode 35 is an integrated structure connected to the pixel electrode 40 of the right sub-pixel, it is equivalent to the fourth electrode 35 and The third drain electrode 39 of the right sub-pixel is connected.
- the third drain electrode 39 of the right sub-pixel is also connected to the first drain electrode 19 of the right sub-pixel, the potentials of the first drain electrode 19, the third drain electrode 39 and the pixel electrode 40 of the right sub-pixel are The potential is the same as that of the fourth electrode 35.
- the third electrode 30 and the fourth electrode 35 serve as two electrode plates forming the second storage capacitor C ST , the third electrode 30 is the lower electrode plate, and the fourth electrode 35 is the upper electrode plate.
- the subsequent preparation process includes forming structures such as the light-emitting layer, the cathode, and the encapsulation layer, and the preparation method is the same as that of the related technology, and will not be repeated here.
- FIG. 21 is a schematic diagram of the equivalent circuit of the left sub-pixel in the first embodiment of the disclosure
- FIG. 22 is a schematic diagram of the equivalent circuit of the right sub-pixel in the first embodiment of the disclosure.
- the first active layer 14, the first gate electrode 16, the first source electrode 18 and the first drain electrode 19 constitute the first transistor T1
- the source electrode 28 and the second drain electrode 29 constitute a second transistor T2
- the third active layer 14, the third gate electrode 16, the third source electrode 18, and the third drain electrode 19 constitute a third transistor T3
- the first transistor T1 is
- the driving transistor the second transistor T2 is a switching transistor
- the third transistor T3 is a compensation transistor.
- the first storage capacitor C ST is formed by the first electrode 12 and the second electrode 17.
- the first electrode 12 is the lower electrode plate
- the second electrode 17 is the upper electrode plate.
- the first gate electrode 16 of the first transistor T1 is connected to the second drain electrode 29 of the second transistor T2 and the first storage capacitor C ST as the second electrode 17 of the upper electrode plate
- the first source electrode 18 of the first transistor T1 Connected to the power supply line VDD
- the first drain electrode 19 of the first transistor T1 is connected to the third drain electrode 39 of the third transistor T3 and the first storage capacitor C ST as the first electrode 12 of the lower electrode plate.
- the second gate electrode 26 of the second transistor T2 is connected to the switch scan line GN, the second source electrode 28 of the second transistor T2 is connected to the data line DN, and the second drain electrode 29 of the second transistor T2 is connected to the first gate of the first transistor T1.
- the electrode 16 and the first storage capacitor C ST serve as the second electrode 17 of the upper electrode plate.
- the third gate electrode 36 of the third transistor T3 is connected to the compensation scan line SN, the third source electrode 38 of the third transistor T3 is connected to the compensation line SE, and the third drain electrode 39 of the third transistor T3 is connected to the first drain of the first transistor T1.
- the electrode 19 and the first storage capacitor C ST serve as the first electrode 12 of the lower electrode plate.
- the second storage capacitor C ST is formed by the third electrode 30 and the fourth electrode 35, the third electrode 30 is the lower electrode plate, and the fourth electrode 31 is the upper electrode plate.
- the first gate electrode 16 of the first transistor T1 is connected to the second drain electrode 29 of the second transistor T2 and the second storage capacitor C ST as the third electrode 30 of the lower electrode plate, and the first source electrode 18 of the first transistor T1 Connected to the power supply line VDD, the first drain electrode 19 of the first transistor T1 is connected to the third drain electrode 39 of the third transistor T3 and the second storage capacitor C ST as the fourth electrode 35 of the upper electrode plate.
- the second gate electrode 26 of the second transistor T2 is connected to the switch scan line GN, the second source electrode 28 of the second transistor T2 is connected to the data line DN, and the second drain electrode 29 of the second transistor T2 is connected to the first gate of the first transistor T1.
- the electrode 16 and the first storage capacitor C ST serve as the third electrode 30 of the lower electrode plate.
- the third gate electrode 36 of the third transistor T3 is connected to the compensation scan line SN, the third source electrode 38 of the third transistor T3 is connected to the compensation line SE, and the third drain electrode 39 of the third transistor T3 is connected to the first drain of the first transistor T1.
- the pole 19 and the second storage capacitor C ST serve as the fourth electrode 35 of the upper electrode plate.
- FIG. 23 is a schematic diagram of the pixel arrangement of the first embodiment of the disclosure.
- the display substrate includes a plurality of pixel units arranged in a matrix, each pixel unit includes 4 sub-pixels, and the 4 sub-pixels are arranged in red (R), green (G), blue (B), and green (G).
- R red
- G green
- B blue
- G green
- the capacitor regions of the R sub-pixel and the G sub-pixel are combined as the common capacitor region of the R sub-pixel and the G sub-pixel
- the capacitor regions of the B sub-pixel and the G sub-pixel are combined as the common capacitor of the B sub-pixel and the G sub-pixel.
- Area the capacitor regions of the R sub-pixel and the G sub-pixel are combined as the common capacitor region of the R sub-pixel and the G sub-pixel.
- the 4 sub-pixels in this embodiment are arranged in RGBG, which can be understood as a pixel unit including 2 sub-pixel units, each sub-pixel unit includes 2 sub-pixels, the first sub-pixel unit includes R sub-pixels and G sub-pixels, and the second sub-pixel unit The unit includes B sub-pixels and G sub-pixels.
- the first sub-pixel unit borrows the missing B sub-pixel from the adjacent second sub-pixel unit to form three primary color sub-pixels RGB.
- the second sub-pixel unit borrows the missing R sub-pixel from the adjacent first sub-pixel unit to form three primary color sub-pixels RGB. It can be seen that the RGBG arrangement in this embodiment can improve the resolution, and the resolution can reach 1.5 times of the existing RGB arrangement.
- this embodiment uses the laminated structure in the display substrate to realize the sharing of capacitor regions and the overlapping of storage capacitors, so as to reduce the area of each sub-pixel capacitor region, and finally increase the pixel size. Opening rate.
- the capacitance areas of two adjacent sub-pixels are combined together as the shared capacitance area of the two sub-pixels, and the electrode plates constituting the storage capacitor of each sub-pixel are arranged in the shared capacitance area.
- the two electrode plates are the first electrode provided in the same layer as the shielding layer and the second electrode provided in the same layer as the gate electrode.
- the storage capacitor formed is located at the lower layer of the pixel drive circuit, and the two electrode plates of the other sub-pixel They are the third electrode provided on the same layer as the source and drain electrodes and the fourth electrode provided on the same layer as the pixel electrode.
- the storage capacitors formed are located in the upper layer of the pixel drive circuit, so that the storage capacitors of the two sub-pixels form a stacked layer arranged up and down. structure.
- each sub-pixel capacitor area of this embodiment is the same as the area of the sub-pixel capacitor area of the related structure, the area of each sub-pixel electrode plate of this embodiment is doubled, which greatly increases the capacity of the storage capacitor, even if it is applied Due to the smaller pixel size, the required storage capacitor capacity can also be guaranteed, which is conducive to achieving high-resolution display.
- the capacity of the storage capacitor of each sub-pixel of this embodiment is the same as that of the sub-pixel of the related structure, it is only necessary to design the area of the shared capacitor region of the two sub-pixels to be slightly larger than the area of the sub-pixel capacitor region of the related structure.
- each sub-pixel capacitor area is only about one-half of the area of the sub-pixel capacitor area of the relevant structure, which greatly reduces the area of each sub-pixel capacitor area and reduces the pixel area occupied by each sub-pixel drive circuit area.
- the pixel aperture ratio can be increased by at least 10% under high PPI. Therefore, the display substrate structure of this embodiment saves the area occupied by the capacitor, improves the pixel aperture ratio, is suitable for high PPI display, reduces power consumption, and avoids problems such as the lifetime degradation of luminescent materials.
- the display substrate of this embodiment adopts three layers of the first electrode provided in the same layer as the shielding layer, the buffer layer, and the second electrode provided in the same layer as the gate electrode to realize a storage capacitor structure of one sub-pixel
- the The third electrode on the same layer as the drain electrode, the passivation layer and the fourth electrode on the same layer as the pixel electrode realize the storage capacitor structure of another sub-pixel
- the second electrode and the gate electrode have the same potential
- the third electrode It is also the same potential as the gate electrode, so the Vs potential of the two storage capacitors can be set to the first electrode at the bottom and the fourth electrode at the top, and the Vg signal is applied to the second and third electrodes in the middle to effectively reduce
- the crosstalk between the signals is small, and the influence between the two storage capacitors is small, which ensures the stability and reliability of the work.
- the sub-pixels and wiring arrangements of the display substrate in this embodiment are reasonably designed.
- the storage capacitor In the horizontal direction, the storage capacitor is located between the two data lines DN, and in the vertical direction, the storage capacitor is located between the switch scan lines GN and GN.
- the compensation scan lines SN and the storage capacitors are arranged between multiple thin film transistors, there are no crossovers on them, and multiple signal wiring positions are more concentrated, which can reduce haze, improve display effects, and effectively ensure the yield.
- the display substrate prepared in this embodiment does not add new processes and introduce new materials, and has good process compatibility, high process feasibility, strong practicability, and good application prospects.
- this embodiment effectively improves the pixel aperture ratio of the bottom-emission OLED without increasing the cost and sacrificing the yield, which is conducive to the realization of high-resolution display, and effectively solves the problem of pixels in existing solutions. Defects with low aperture ratio.
- FIG. 24 is a schematic structural diagram of another exemplary embodiment of a display substrate of the present disclosure.
- This embodiment shows that the main structure of the substrate is basically the same as that of the aforementioned first embodiment, except that this embodiment also has a color film layer between the fourth insulating layer and the fifth insulating layer.
- the color filter layer 32 is located in the light-emitting area of each sub-pixel, is disposed on the fourth insulating layer 31 and covered by the fifth insulating layer 33.
- the structure of the foregoing embodiment is suitable for the light emitting layer to emit light of the required color, and the structure of this embodiment is suitable for the light emitting layer of all sub-pixels to emit light of the same color.
- the color film layer 32 is filtered to realize the desired color of each sub-pixel. Light.
- This embodiment shows that the preparation process of the substrate is basically the same as the preparation process of the foregoing first embodiment, except that between step (5) and step (6), a color film layer pattern is formed.
- the fourth insulating film and the color filter film are sequentially deposited on the substrate with the pattern in step (5), and the fourth insulating film covering the aforementioned structure is formed by masking, exposing and developing the color filter film.
- the color film layer 32 of the left sub-pixel is a red color film
- the color film layer 32 of the right sub-pixel is a green color film
- the color film layer 32 of the left sub-pixel is a blue color film
- the color film layer 32 of the right sub-pixel is a green color film.
- This embodiment also achieves the technical effects of the foregoing embodiments, including effectively increasing the pixel aperture ratio of the bottom emission OLED, which is beneficial to realize high-resolution display.
- the embodiments of the present disclosure can be applied to a structure in which the pixel unit includes 3 sub-pixels.
- the capacitor regions of the R sub-pixel and the B sub-pixel can be combined as a common capacitor area of the two sub-pixels.
- the two sub-pixels adopt the structural arrangement proposed in the embodiment of the present disclosure, and the G
- the capacitor area of the sub-pixels is used as a separate capacitor area, and the sub-pixels can be arranged in a related art structure.
- the wiring design can be optimized to match the display substrate structure of the present disclosure.
- the embodiment of the present disclosure also provides a method for preparing a display substrate to prepare the display substrate of the foregoing embodiment.
- the preparation method of the display substrate of the embodiment of the present disclosure includes: forming a plurality of sub-pixels arranged in a matrix, each sub-pixel is formed with a pixel driving circuit including a plurality of thin film transistors and a storage capacitor, the storage capacitor of the sub-pixel and the storage of adjacent sub-pixels The capacitor is formed in the common capacitor area of the two sub-pixels, and the storage capacitor of the sub-pixel and the storage capacitor of the adjacent sub-pixel are stacked.
- the storage capacitor of the sub-pixel is formed in the common capacitor area of the two sub-pixels, including:
- first electrode provided in the same layer as the light shielding layer in the pixel driving circuit, and the first electrode is formed in the common capacitance area of the two sub-pixels;
- a second electrode arranged in the same layer as the gate electrode of the thin film transistor is formed, and the second electrode is formed in the common capacitance area of the two sub-pixels.
- the storage capacitors of adjacent sub-pixels are formed in the common capacitor area of two sub-pixels, including:
- a fourth electrode arranged in the same layer as the pixel electrode is formed, and the fourth electrode is formed in the common capacitance area of the two sub-pixels.
- forming the pixel driving circuit includes:
- a gate electrode and a second electrode are formed on the second insulating layer, the second electrode is formed in a common capacitor area of two sub-pixels, and the first electrode and the second electrode form a storage capacitor of the sub-pixel.
- forming the pixel driving circuit further includes: forming a third insulating layer covering the gate electrode and the second electrode;
- a pixel electrode and a fourth electrode are formed on the fifth insulating layer, the fourth electrode is formed in a common capacitance area of two sub-pixels, and the third electrode and the fourth electrode form a storage capacitor of adjacent sub-pixels.
- forming the light-shielding layer and the first electrode on the substrate includes: forming the light-shielding layer of the sub-pixel and the light-shielding layer of the adjacent sub-pixel on the substrate, and the light-shielding layer and the first electrode of the sub-pixel are One-piece structure.
- forming the gate electrode and the second electrode on the second insulating layer includes: forming the first gate electrode, the second gate electrode, and the third gate of the sub-pixel on the second insulating layer. Electrodes, and the first gate electrode, the second gate electrode and the third gate electrode of the adjacent sub-pixels, and the first gate electrode and the second electrode of the sub-pixel have an integral structure.
- forming the pixel electrode and the fourth electrode on the fifth insulating layer includes: forming the pixel electrode of the current sub-pixel and the pixel electrode of the adjacent sub-pixel on the fifth insulating layer, the The pixel electrode of the adjacent sub-pixel and the fourth electrode are in an integral structure, and the pixel electrode of the adjacent sub-pixel is connected to the first drain electrode and the third drain electrode of the adjacent sub-pixel through a via hole.
- forming a source electrode, a drain electrode, and a third electrode on the third insulating layer includes:
- a data line, a compensation line, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a third source electrode, a third drain electrode, and a third electrode are formed on the third insulating layer.
- the compensation line is connected to the connection line through a via
- the first source electrode is connected to the first active layer through the via hole, and the first drain electrode is simultaneously connected to the first active layer and the light shielding layer through the via hole, so that the first drain electrode of the sub-pixel is connected to the first electrode ;
- the second source electrode and the data line are in an integrated structure, the second source electrode is connected to the second active layer through the via hole, and the second drain electrode is simultaneously connected to the second active layer and the first gate through the via hole. Electrode connection, connecting the second drain electrode of the sub-pixel to the second electrode;
- the third source electrode is simultaneously connected to the connection line and the third active layer through the via hole, and the third drain electrode is simultaneously connected to the third active layer and the light shielding layer through the via hole, so that the third drain electrode of the sub-pixel Connect the first electrode;
- the third electrode is connected to the first gate electrode of the adjacent sub-pixel through a via hole.
- forming the fourth insulating layer and the fifth insulating layer covering the source electrode, the drain electrode, and the third electrode includes:
- a fifth insulating layer covering the color filter layer is formed.
- forming a fifth insulating layer covering the color filter layer includes:
- a via hole exposing the fourth insulating layer is formed in the fifth insulating layer, and the via hole is used for arranging the fourth electrode.
- the preparation method of the display substrate of the embodiment of the present disclosure also realizes that the pixel aperture ratio of the bottom emission type OLED is effectively improved without increasing the cost and sacrificing the yield, which is beneficial to realize high-resolution display.
- the embodiment of the present disclosure also provides a display device, including the aforementioned display substrate.
- the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
- the terms “installed”, “connected”, and “connected” should be interpreted broadly. For example, it can be a fixed connection, it can be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate piece, and it can be internal to two components. Connected.
- installed e.g., it can be a fixed connection, it can be a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate piece, and it can be internal to two components. Connected.
- the meaning of the above-mentioned terms in the present disclosure can be understood according to the situation.
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Abstract
Description
Claims (20)
- 一种显示基板,包括矩阵排布的多个子像素,每个子像素设置有包括多个薄膜晶体管和存储电容的像素驱动电路,所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容设置在所述本子像素和所述相邻子像素的共用电容区,所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。
- 根据权利要求1所述的显示基板,其中,所述本子像素的存储电容包括:与像素驱动电路中的遮光层同层设置的第一电极,覆盖所述第一电极的绝缘层,与所述薄膜晶体管的栅电极同层设置的第二电极。
- 根据权利要求1或2所述的显示基板,其中,所述相邻子像素的存储电容包括:与所述薄膜晶体管的源漏电极同层设置的第三电极,覆盖所述第三电极的绝缘层,与像素电极同层设置的第四电极。
- 根据权利要求1至3任一项所述的显示基板,其中,所述像素驱动电路包括:基底;设置在所述基底上的遮光层和第一电极,所述第一电极设置在所述共用电容区;覆盖所述遮光层和第一电极的第一绝缘层;设置在所述第一绝缘层上的有源层;覆盖所述有源层的第二绝缘层;设置在所述第二绝缘层上的栅电极和第二电极,所述第二电极设置在所述共用电容区,所述第一电极和第二电极形成本子像素的存储电容。
- 根据权利要求4所述的显示基板,其中,所述像素驱动电路还包括:覆盖所述栅电极和第二电极的第三绝缘层;设置在所述第三绝缘层上的源电极、漏电极和第三电极,所述第三电极设置在所述共用电容区;覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层;设置在所述第五绝缘层上的像素电极和第四电极,所述第四电极设置在所述共用电容区,所述第三电极和第四电极形成相邻子像素的存储电容。
- 根据权利要求5所述的显示基板,其中,所述多个薄膜晶体管包括第一薄膜晶体管、第二薄膜晶体管和第三薄膜晶体管,所述第一薄膜晶体管包括第一有源层、第一栅电极、第一源电极和第一漏电极,所述第二薄膜晶体管包括第二有源层、第二栅电极、第二源电极和第二漏电极,所述第三薄膜晶体管包括第三有源层、第三栅电极、第三源电极和第三漏电极。
- 根据权利要求6所述的显示基板,其中,在所述本子像素中,所述第一电极与所述遮光层为一体结构,所述第一电极通过过孔连接所述第一漏电极和所述第三漏电极;所述第二电极与所述第一栅电极为一体结构,所述第二电极通过过孔连接所述第二漏电极。
- 根据权利要求6或7所述的显示基板,其中,在所述相邻子像素中,所述第三电极通过过孔连接所述第一栅电极和所述第二漏电极,所述第四电极与所述像素电极为一体结构,所述第四电极通过过孔连接所述第一漏电极和所述第三漏电极。
- 根据权利要求5所述的显示基板,还包括彩膜层,所述彩膜层设置在第四绝缘层与第五绝缘层之间,所述第五绝缘层上开设有暴露出第四绝缘层的过孔,所述第四电极设置在所述过孔内。
- 根据权利要求5至9任一项所述的显示基板,其中,所述像素驱动电路还包括开关扫描线、补偿扫描线和数据线,在水平方向上,所述共用电容区设置在两条数据线之间,在垂直方向上,所述共用电容区设置在开关扫描线和补偿扫描线之间。
- 一种显示装置,包括如权利要求1至10任一项所述的显示基板。
- 一种显示基板的制备方法,包括:形成矩阵排布的多个子像素,在每个子像素形成包括多个薄膜晶体管和存储电容的像素驱动电路,其中,所述多个子像素中的本子像素的存储电容和与所述本子像素相邻的相邻子像素的存储电容形成在所述本子像素和所述相邻子像素的共用电容区,所述本子像素的存储电容和所述相邻子像素的存储电容叠层设置。
- 根据权利要求12所述的显示基板的制备方法,其中,所述本子像素的存储电容形成在所述共用电容区,包括:形成与像素驱动电路中的遮光层同层设置的第一电极,所述第一电极形成在所述共用电容区;形成覆盖所述第一电极的绝缘层;形成与薄膜晶体管的栅电极同层设置的第二电极,所述第二电极形成在所述共用电容区。
- 根据权利要求12或13所述的显示基板的制备方法,其中,所述相邻子像素的存储电容形成在所述共用电容区,包括:形成与薄膜晶体管的源漏电极同层设置的第三电极,所述第三电极形成在所述共用电容区;形成覆盖所述第三电极的绝缘层;形成与像素电极同层设置的第四电极,所述第四电极形成在所述共用电容区。
- 根据权利要求12至14任一项所述的显示基板的制备方法,其中,形成像素驱动电路包括:在基底上形成遮光层和第一电极,所述第一电极形成在所述共用电容区;形成覆盖所述遮光层和第一电极的第一绝缘层;在所述第一绝缘层上形成有源层;形成覆盖所述有源层的第二绝缘层;在所述第二绝缘层上形成栅电极和第二电极,所述第二电极形成在所述共用电容区,所述第一电极和第二电极形成所述本子像素的存储电容。
- 根据权利要求15所述的显示基板的制备方法,其中,形成像素驱动电路还包括:形成覆盖所述栅电极和第二电极的第三绝缘层;在所述第三绝缘层上形成源电极、漏电极和第三电极,所述第三电极形成在所述共用电容区;形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层;在所述第五绝缘层上形成像素电极和第四电极,所述第四电极形成在所述共用电容区,所述第三电极和第四电极形成相邻子像素的存储电容。
- 根据权利要求16所述的显示基板的制备方法,其中,所述在基底上形成遮光层和第一电极包括:在基底上形成本子像素的遮光层和相邻子像素的遮光层,所述本子像素的遮光层与第一电极为一体结构;所述在所述第二绝缘层上形成栅电极和第二电极包括:在所述第二绝缘层上形成本子像素的第一栅电极、第二栅电极和第三栅电极,以及相邻子像素的第一栅电极、第二栅电极和第三栅电极,所述本子像素的第一栅电极与第二电极为一体结构;所述在所述第五绝缘层上形成像素电极和第四电极包括:在所述第五绝缘层上形成本子像素的像素电极和相邻子像素的像素电极,所述相邻子像素的像素电极与所述第四电极为一体结构,所述相邻子像素的像素电极通过过孔连接相邻子像素的第一漏电极和第三漏电极。
- 根据权利要求16所述的显示基板的制备方法,其中,所述在所述第三绝缘层上形成源电极、漏电极和第三电极包括:在所述第三绝缘层上形成数据线、补偿线、第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和第三电极。
- 根据权利要求18所述的显示基板的制备方法,其中,所述补偿线通过过孔与连接线连接;所述第一源电极通过过孔与第一有源层连接,所述第一漏电极通过过孔同时与第一有源层和遮光层连接,使本子像素的第一漏电极连接第一电极;所述第二源电极与数据线为一体结构,所述第二源电极通过过孔与第二有源层连接,所述第二漏电极通过过孔同时与第二有源层和第一栅电极连接,使本子像素的第二漏电极连接第二电极;所述第三源电极通过过孔同时与连接线和第三有源层连接,所述第三漏电极通过过孔同时与第三有源层和遮光层连接,使本子像素的第三漏电极连接第一电极;所述第三电极通过过孔与相邻子像素的第一栅电极连接。
- 根据权利要求16所述的显示基板的制备方法,其中,所述形成覆盖所述源电极、漏电极和第三电极的第四绝缘层和第五绝缘层,包括:形成覆盖所述源电极、漏电极和第三电极的第四绝缘层;在所述第四绝缘层上形成彩膜层;形成覆盖所述彩膜层的第五绝缘层,在所述第五绝缘层形成暴露出第四绝缘层的过孔,所述过孔用于设置所述第四电极。
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