WO2022057491A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022057491A1
WO2022057491A1 PCT/CN2021/110760 CN2021110760W WO2022057491A1 WO 2022057491 A1 WO2022057491 A1 WO 2022057491A1 CN 2021110760 W CN2021110760 W CN 2021110760W WO 2022057491 A1 WO2022057491 A1 WO 2022057491A1
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Prior art keywords
metal layer
line
transistor
substrate
electrode
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PCT/CN2021/110760
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English (en)
French (fr)
Inventor
李永谦
袁粲
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/787,943 priority Critical patent/US20230021680A1/en
Publication of WO2022057491A1 publication Critical patent/WO2022057491A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • This article relates to, but is not limited to, the field of display technology, especially a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • PM Passive Matrix
  • AM Active Matrix
  • AMOLED is a current driving device, using independent thin film transistors (TFT, Thin Film Transistor) controls each sub-pixel, and each sub-pixel can be continuously and independently driven to emit light.
  • Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate. At least one sub-pixel of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit.
  • the pixel driving circuit includes a plurality of transistors and at least one storage capacitor.
  • the display substrate In a direction perpendicular to the base, the display substrate includes: a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer sequentially arranged on the base.
  • the semiconductor layer includes active layers of a plurality of transistors.
  • the first metal layer at least includes: a scan line extending along a first direction, gate electrodes of the plurality of transistors, and a first capacitor plate of the storage capacitor.
  • the second metal layer at least includes: a scan connection line extending along a first direction; a first via hole is provided in the insulating layer between the second metal layer and the first metal layer, and the scan connection line contacts through the the scan line exposed by the first via hole.
  • the third metal layer includes at least: a second capacitor plate of the storage capacitor.
  • the fourth metal layer at least includes: a data line extending in a second direction perpendicular to the first direction, and source and drain electrodes of the plurality of transistors.
  • the scan line includes a first portion and a second portion sequentially connected along a first direction.
  • the projection of the first portion on the substrate overlaps with the projection of the fourth metal layer on the substrate, and the projection of the second portion on the substrate overlaps the projection of the fourth metal layer on the substrate.
  • the projections do not overlap.
  • the average length of the second portion in the second direction is greater than the average length of the first portion in the second direction.
  • the first portion has a first edge and a second edge extending in a first direction
  • the second portion has a first edge and a third edge extending in a first direction
  • the first edge The second edge and the third edge are located on the same side of the first edge along the second direction
  • the third edge is located on the side of the second edge away from the first edge.
  • the first edge is an upper edge of the first and second portions
  • the second edge is a lower edge of the first portion
  • the third edge is the second edge the lower edge of the section.
  • the projection of the scan line on the substrate includes the projection of the scan line on the substrate.
  • the material of the first metal layer is molybdenum
  • the second metal layer includes a three-layer stack structure formed by titanium, aluminum and titanium.
  • the fourth metal layer further includes: a first power supply line extending along the second direction; and six columns of sub-pixels are arranged between two adjacent first power supply lines.
  • the first metal layer further includes: a power supply connection line extending along a first direction, the power supply connection line being connected to the first power supply line and the six columns of sub-pixels.
  • the display substrate further includes: a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer.
  • the first insulating layer is arranged between the semiconductor layer and the first metal layer
  • the second insulating layer is arranged between the first metal layer and the second metal layer
  • the third insulating layer is arranged on the Between the second metal layer and the third metal layer
  • the fourth insulating layer is disposed between the third metal layer and the fourth metal layer.
  • the display substrate further includes: a fifth metal layer disposed on a side of the fourth metal layer away from the substrate.
  • the fifth metal layer at least includes: a connection electrode that electrically connects the pixel driving circuit and the light-emitting element.
  • the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor.
  • the gate electrode of the first transistor is connected to the second electrode of the third transistor, the first capacitor plate of the storage capacitor and the second electrode of the fourth transistor, and the first electrode of the first transistor is connected to the second transistor
  • the second electrode of the first transistor is connected to the second capacitor plate of the storage capacitor, the first electrode of the fifth transistor and the first electrode of the light-emitting element.
  • the gate electrode of the second transistor is connected to the light-emitting control line, and the first electrode of the second transistor is connected to the first power supply line.
  • the gate electrode of the third transistor is connected to the first control signal line, and the first electrode of the third transistor is connected to the reference voltage line.
  • the gate electrode of the fourth transistor is connected to the scan line, and the first electrode of the fourth transistor is connected to the data line.
  • the gate electrode of the fifth transistor is connected to the second control signal line, and the second electrode of the fifth transistor is connected to the initial voltage line.
  • the third, fourth, and fifth transistors are dual-gate transistors; each dual-gate transistor includes two interconnected gate electrodes.
  • the first capacitor plate of the storage capacitor and the gate electrode of the first transistor are integrally formed.
  • the first metal layer further includes: a first control signal line, a second control signal line and a light emission control line; the third metal layer further includes: a reference voltage line and an initial voltage line.
  • the first control signal line, the second control signal line, the lighting control line, the reference voltage line and the initial voltage line all extend along the first direction.
  • the first control signal line and the second control signal line are located on both sides of the scan line, and the light emission control line is located on the second control line
  • the signal line is away from the side of the scan line.
  • the projection of the reference voltage line on the substrate is located on the side where the projection of the first control signal line on the substrate is far from the projection of the scan line on the substrate, and the projection of the initial voltage line on the substrate is located on the side of the substrate. Between the projection of the second control signal line and the light emission control line on the substrate.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a method for fabricating a display substrate.
  • the display substrate includes a base and a plurality of sub-pixels arranged on the base, at least one sub-pixel in the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit; the pixel driving circuit A plurality of transistors and at least one storage capacitor are included.
  • the preparation method includes: sequentially forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer on the substrate.
  • the semiconductor layer includes active layers of a plurality of transistors.
  • the first metal layer at least includes: a scan line extending along a first direction, gate electrodes of the plurality of transistors, and a first capacitor plate of the storage capacitor.
  • the second metal layer at least includes: a scan connection line extending along a first direction; a first via hole is provided in the insulating layer between the second metal layer and the first metal layer, and the scan connection line contacts through the the scan line exposed by the first via hole.
  • the third metal layer includes at least: a second capacitor plate of the storage capacitor.
  • the fourth metal layer at least includes: a data line extending in a second direction perpendicular to the first direction, and source and drain electrodes of the plurality of transistors.
  • the scan line includes a first part and a second part connected in sequence along a first direction, the projection of the first part on the substrate overlaps with the projection of the fourth metal layer on the substrate, so The projection of the second portion on the substrate does not overlap with the projection of the fourth metal layer on the substrate, and the average length of the second portion along the second direction is greater than that of the first portion along the second direction. the average length in the second direction.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 2 is an equivalent circuit diagram of a pixel driving circuit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a top view of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure
  • Fig. 4 is the cross-sectional schematic diagram of the P-P direction in Fig. 3;
  • Fig. 5 is the cross-sectional schematic diagram of Q-Q direction in Fig. 3;
  • FIG. 6 is a schematic diagram of a sub-pixel after a semiconductor layer pattern is formed in at least one embodiment of the present disclosure
  • Fig. 7 is the cross-sectional schematic diagram of Q-Q direction in Fig. 6;
  • FIG. 8 is a schematic diagram of a sub-pixel after forming a first metal layer pattern according to at least one embodiment of the present disclosure
  • FIG. 9 is a schematic cross-sectional view in the P-P direction in FIG. 8;
  • Figure 10 is a schematic cross-sectional view in the direction of Q-Q in Figure 8.
  • FIG. 11 is a schematic diagram of a sub-pixel after forming a second insulating layer pattern in at least one embodiment of the disclosure
  • FIG. 12 is a schematic cross-sectional view along the P-P direction in FIG. 11;
  • FIG. 13 is a schematic diagram of a sub-pixel after forming a second metal layer pattern according to at least one embodiment of the disclosure
  • FIG. 14 is a schematic cross-sectional view along the P-P direction in FIG. 13;
  • 15 is a schematic diagram of a sub-pixel after forming a third metal layer pattern in at least one embodiment of the disclosure
  • FIG. 16 is a schematic cross-sectional view in the direction of Q-Q in FIG. 15;
  • 17 is a schematic diagram of a sub-pixel after forming a fourth insulating layer pattern in at least one embodiment of the disclosure.
  • FIG. 18 is a schematic cross-sectional view in the direction Q-Q in FIG. 17;
  • 19 is a schematic diagram of a sub-pixel after forming a fourth metal layer pattern according to at least one embodiment of the disclosure.
  • 20 is a schematic diagram of a sub-pixel after forming a fifth metal layer pattern according to at least one embodiment of the disclosure
  • Figure 21 is a schematic cross-sectional view in the direction R-R in Figure 20;
  • FIG. 22 is a top view of a plurality of sub-pixels of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 23 is a schematic diagram of a plurality of sub-pixels after forming a semiconductor layer pattern in at least one embodiment of the disclosure.
  • FIG. 24 is a schematic diagram of a plurality of sub-pixels after forming a first metal layer pattern according to at least one embodiment of the disclosure
  • 25 is a schematic diagram of a plurality of sub-pixels after forming a second metal layer pattern in at least one embodiment of the disclosure
  • 26 is a schematic diagram of a plurality of sub-pixels after forming a third metal layer pattern according to at least one embodiment of the disclosure
  • FIG. 27 is a schematic diagram of a plurality of sub-pixels after forming a fourth metal layer pattern according to at least one embodiment of the disclosure.
  • FIG. 28 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
  • a “plurality” in this disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in the present disclosure, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having some electrical function” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus can include a state in which the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and therefore can include a state in which an angle of 85° or more and 95° or less is included.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base and a plurality of sub-pixels disposed on the base. At least one sub-pixel among the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit.
  • the pixel driving circuit includes a plurality of transistors and at least one storage capacitor.
  • the display substrate includes: a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer sequentially arranged on the substrate.
  • the semiconductor layer includes active layers of a plurality of transistors.
  • the first metal layer at least includes: a scan line extending along the first direction, gate electrodes of a plurality of transistors, and a first capacitor electrode plate of a storage capacitor.
  • the second metal layer at least includes: scan connection lines extending along the first direction.
  • the third metal layer at least includes: a second capacitor electrode plate of the storage capacitor.
  • the fourth metal layer at least includes: a data line extending along a second direction perpendicular to the first direction, and source and drain electrodes of a plurality of transistors.
  • the insulating layer between the second metal layer and the first metal layer is provided with a first via hole, and the scan connection line contacts the scan line exposed through the first via hole.
  • the scan line includes a first part and a second part connected in sequence along the first direction, the projection of the first part on the substrate overlaps with the projection of the fourth metal layer on the substrate, and the projection of the second part on the substrate overlaps with the projection of the fourth metal layer on the substrate.
  • the projections of the metal layers on the substrate do not overlap, and the average length of the second portion along the second direction is greater than the average length of the first portion along the second direction.
  • width refers to a feature dimension extending in a first direction
  • length refers to a feature dimension extending in a second direction
  • space optimization is achieved by designing a narrow overlapping area of the projection of the scan lines and the fourth metal layer on the substrate, and furthermore, by arranging scan connection lines connected to the scan lines on the second metal layer , on the basis of ensuring that the parasitic capacitance of the scan line is not increased, the resistance of the scan line can be greatly reduced, thereby reducing the loading of the scan line, so as to meet the driving requirements and ensure the normal driving function.
  • the first portion has a first edge and a second edge extending in a first direction
  • the second portion has a first edge and a third edge extending in the first direction
  • the second edge and the third edge The third edge is located on the same side of the first edge along the second direction
  • the third edge is located on the side of the second edge away from the first edge.
  • the scan line extends in a first direction and has a straight first edge and a second edge provided with a first protrusion; the first protrusion is provided on the second edge and is directed away from the second edge extending in the direction of the first protrusion having a third edge relative to the second edge.
  • the first protrusion and the region between the second edge corresponding to the position of the first protrusion and the first edge form the second part, and the region other than the second part is the first part.
  • the first protrusion may have a straight third edge, and the third edge may be parallel to the second edge.
  • this embodiment does not limit this.
  • the third edge may have a wavy structure.
  • the first edge is the upper edge of the first and second portions of the scan line
  • the second edge is the lower edge of the first portion of the scan line
  • the third edge is the lower edge of the second portion of the scan line edge.
  • the first edge may be the lower edge of the first and second portions of the scan line
  • the second edge may be the upper edge of the first portion of the scan line
  • the third edge may be the upper edge of the second portion of the scan line.
  • the projection of the scan lines on the substrate includes the projection of the scan lines on the substrate.
  • the scan connection line may have a straight fourth edge and a straight fifth edge, the fourth edge and the fifth edge extend along the first direction, and the fourth edge and the fifth edge are disposed opposite to each other, and the fourth edge
  • the distance between the scan line and the fifth edge (that is, the length of the scan line along the second direction) may be greater than or equal to the maximum distance between the first edge and the third edge of the scan line (that is, the second portion of the scan line along the second the maximum length of the direction).
  • this embodiment does not limit this.
  • the projections of the scan links on the substrate may coincide with the projections of the scan lines on the substrate, ie, the scan links and the scan lines may have the same shape.
  • the projection of the scan line on the substrate may partially overlap the projection of the scan line on the substrate.
  • the scan line may have fourth and fifth edges that are straight and extend along the first direction. The fourth edge and the fifth edge are opposite to each other, and the distance between the fourth edge and the fifth edge is less than or equal to the distance between the first edge and the second edge of the scan line.
  • the material of the first metal layer is molybdenum (Mo)
  • the second metal layer includes a three-layer stack structure formed by titanium (Ti), aluminum (Al), and titanium. That is, the second metal layer may include a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.
  • this embodiment does not limit the materials of the first metal layer and the second metal layer.
  • the second metal layer may be a single-layer metal structure.
  • the metal material with lower resistivity is used to prepare and form the second metal layer, which can reduce the resistance of the scan connection line.
  • the fourth metal layer further includes: a first power line extending in the second direction. Six columns of sub-pixels are arranged between two adjacent first power lines.
  • the first power lines are designed as a one-for-six structure. Under the same resolution (PPI, Pixels Per Inch), the size of each sub-pixel can be effectively increased, and the layout space can be fully utilized. , the overall layout is reasonable and so on.
  • the first metal layer further includes: a power supply connection line extending along the first direction, and the power supply connection line is connected with the first power supply line and the six columns of sub-pixels. Wherein, the extending direction of the power connection line is perpendicular to the extending direction of the first power line.
  • the display substrate may further include: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.
  • the first insulating layer is arranged between the semiconductor layer and the first metal layer
  • the second insulating layer is arranged between the first metal layer and the second metal layer
  • the third insulating layer is arranged between the second metal layer and the third metal layer
  • the fourth insulating layer is disposed between the third metal layer and the fourth metal layer.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be inorganic insulating layers.
  • the display substrate further includes: a fifth metal layer disposed on a side of the fourth metal layer away from the substrate; the fifth metal layer at least includes: a connection electrode electrically connecting the pixel driving circuit and the light-emitting element.
  • the first metal layer may be referred to as a first gate metal layer
  • the second metal layer may be referred to as a second gate metal layer
  • the third metal layer may be referred to as a third gate metal layer
  • the fourth metal layer may be referred to as Being the first source-drain metal layer
  • the fifth metal layer may be referred to as the second source-drain metal layer.
  • the pixel driving circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a storage capacitor.
  • the gate electrode of the first transistor is connected to the second electrode of the third transistor, the first capacitor plate of the storage capacitor and the second electrode of the fourth transistor, the first electrode of the first transistor is connected to the second electrode of the second transistor, The second electrode of the first transistor is connected to the second capacitor plate of the storage capacitor, the first electrode of the fifth transistor and the first electrode of the light emitting element.
  • the gate electrode of the second transistor is connected to the light-emitting control line, the first electrode of the second transistor is connected to the first power supply line; the gate electrode of the third transistor is connected to the first control signal line, and the first electrode of the third transistor is connected to the reference voltage
  • the gate electrode of the fourth transistor is connected to the scan line, the first pole of the fourth transistor is connected to the data line; the gate electrode of the fifth transistor is connected to the second control signal line, and the second pole of the fifth transistor is connected to the initial voltage line connection.
  • the first transistor is a driving transistor.
  • the pixel driving circuit may adopt a 5T1C design. However, this embodiment does not limit this.
  • the third transistor, the fourth transistor, and the fifth transistor are dual gate transistors; each dual gate transistor includes two interconnected gate electrodes.
  • the leakage current of the third transistor, the fourth transistor and the fifth transistor can be reduced by adopting the double gate design, thereby ensuring the functional correctness of the pixel driving circuit.
  • the first capacitor plate of the storage capacitor is integrally formed with the gate electrode of the first transistor.
  • the projection of the first capacitor plate of the storage capacitor on the substrate overlaps with the projection of the active layer of the first transistor on the substrate.
  • the first metal layer further includes: a first control signal line, a second control signal line, and a light emission control line; and the third metal layer further includes: a reference voltage line and an initial voltage line.
  • the first control signal line, the second control signal line, the lighting control line, the reference voltage line and the initial voltage line all extend along the first direction.
  • the first control signal line and the second control signal line are located on both sides of the scan line, and the light emission control line is located on a side of the second control signal line away from the scan line.
  • the projection of the reference voltage line on the substrate is located on the side where the projection of the first control signal line on the substrate is far from the projection of the scanning line on the substrate, and the projection of the initial voltage line on the substrate is located on the second control signal line and the light-emitting control line. between projections on the substrate.
  • this embodiment does not limit this.
  • FIG. 1 is a schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate of the present exemplary embodiment may include: a display area AA and a peripheral area located around the display area AA.
  • the display area AA may be provided with a plurality of sub-pixels PA regularly arranged, a plurality of first signal lines (for example, including a scan line G1, a control signal line and a light-emitting line) extending along a first direction (X direction in FIG. 1 ).
  • a control line EM a plurality of second signal lines (eg, including a data line DL and a first power supply line) extending along a second direction (the Y direction in FIG. 1 ).
  • the first direction and the second direction may be located in the same plane, and the first direction may be perpendicular to the second direction.
  • the first direction may be the row direction, which is parallel to the extension direction of the scan lines; the second direction may be the column direction, which is parallel to the extension direction of the data lines.
  • at least one first signal line may extend in the X direction, and a plurality of first signal lines may be sequentially arranged in the Y direction; at least one second signal line may extend in the Y direction, and the plurality of first signal lines may extend in the Y direction.
  • the two signal lines can be arranged in sequence along the X direction.
  • At least one sub-pixel PA among the plurality of sub-pixels may include a light-emitting element and a pixel driving circuit for driving the light-emitting element to emit light.
  • the pixel driving circuit may include: a plurality of transistors and at least one storage capacitor, for example, a design of 3T1C, 5T1C or 7T1C may be adopted. However, this embodiment does not limit this.
  • m rows of scan lines G1 ⁇ 1> to G1 ⁇ m> are arranged along the Y direction, and n columns of data lines DL ⁇ 1> to DL ⁇ are arranged along the X direction n>, the scanning line and the data line are insulated from each other.
  • m and n are both integers greater than 0.
  • the sub-pixels PA may be distributed at intersections of m rows of scan lines and n columns of data lines, and a plurality of sub-pixels PA are arranged according to a matrix-like rule.
  • three sub-pixels emitting light of different colors eg, red, green, and blue
  • four sub-pixels emitting light of different colors eg, red, green, blue, and white
  • this embodiment does not limit this.
  • the columns are sometimes referred to as the first column, the second column, . . . , and the n-th column in order from the left.
  • the peripheral area may be provided with a timing controller, a data driving circuit, a scan driving circuit and a light emitting driving circuit.
  • the scan driving circuit and the light-emitting driving circuit may be arranged on opposite sides of the display area AA (for example, the left and right sides of the display area AA), and the timing controller and the data driving circuit may be arranged on one side of the display area (for example, the display area upper or lower side of area AA).
  • the data driving circuit may provide data signals to a plurality of columns of sub-pixels through a plurality of data lines DL.
  • the scan driving circuit may provide scan signals to multiple rows of sub-pixels through multiple scan lines G1.
  • the scan drive circuit can also generate at least one control signal (illustration omitted in FIG. 1 ) synchronized with the scan signal row by row, and provide it to multiple rows of sub-pixels in the display area.
  • the light-emitting driving circuit may provide light-emitting control signals to the plurality of rows of sub-pixels through the plurality of light-emitting control lines EM.
  • the timing controller may provide driving signals to the data driving circuit, the scan driving circuit and the light emitting driving circuit. The actions of the scan driving circuit, the data driving circuit and the light emission control circuit can be controlled by the timing controller.
  • the timing controller may provide the data driving circuit with grayscale data specifying that the subpixels should display grayscale.
  • the data driving circuit may provide a data signal of a potential corresponding to the grayscale data of the sub-pixels to the sub-pixels of the row selected by the scanning driving circuit via the data lines.
  • FIG. 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to at least one embodiment of the present disclosure.
  • FIG. 2 illustrates the structure of a 5T1C pixel driving circuit.
  • the pixel driving circuit of one sub-pixel is connected with the scan line G1, the first control signal line G2, the second control signal line G3, the light emission control line EM, the first power supply line VDD, the reference voltage line Vref, the initial voltage
  • the line Vini and the data line DL are electrically connected.
  • the pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a storage capacitor Cst.
  • the gate electrode of the first transistor T1 is connected to the second electrode of the third transistor T3, the first capacitor plate of the storage capacitor Cst, and the second electrode of the fourth transistor T4, and the second electrode of the first transistor T1
  • the first electrode is connected to the second electrode of the second transistor T2
  • the second electrode of the first transistor T1 is connected to the second capacitor plate of the storage capacitor Cst, the first electrode of the fifth transistor T5 and the first electrode of the light-emitting element EL .
  • the gate electrode of the second transistor T2 is connected to the light emission control line EM
  • the first electrode of the second transistor T2 is connected to the first power supply line VDD.
  • the gate electrode of the third transistor T3 is connected to the first control signal line G2, and the first electrode of the third transistor T3 is connected to the reference voltage line Vref.
  • the gate electrode of the fourth transistor T4 is connected to the scan line G1, and the first electrode of the fourth transistor T4 is connected to the data line DL.
  • the gate electrode of the fifth transistor T5 is connected to the second control signal line G3, and the second electrode of the fifth transistor T5 is connected to the initial voltage line Vini.
  • the second electrode of the light-emitting element EL is connected to the second power supply line VSS.
  • the light emitting element EL is configured to emit light of corresponding luminance in response to the current of the second electrode of the first transistor T1.
  • the fifth transistor T5 can extract the threshold voltage Vth and the mobility of the first transistor T1 in response to the timing of compensation, so as to compensate the threshold voltage Vth.
  • the storage capacitor Cst is configured to maintain the node voltage of the gate electrode and the second electrode of the first transistor T1 during one frame of light emission period.
  • the first transistor T1 is a driving transistor, and other transistors except the first transistor T1 are switching transistors.
  • the first to fifth transistors T1 to T5 provided in this exemplary embodiment may all be P-type transistors or N-type transistors. This embodiment does not limit this.
  • the first to fifth transistors T1 to T5 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon thin film transistors.
  • the transistors in the pixel driving circuit provided in this embodiment are all transistors of the same type, which can avoid the influence of the difference between different types of transistors on the pixel driving circuit.
  • FIG. 3 is a top view of a sub-pixel in a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view along the P-P direction in FIG. 3 .
  • FIG. 5 is a schematic cross-sectional view along the Q-Q direction in FIG. 3 .
  • the display area of the display substrate provided by this exemplary embodiment includes: a substrate 10 , a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer sequentially arranged on the substrate 10 and the fourth metal layer.
  • a first insulating layer 81 is arranged between the semiconductor layer and the first metal layer, a second insulating layer 82 is arranged between the first metal layer and the second metal layer, and a third metal layer is arranged between the second metal layer and the third metal layer. Three insulating layers 83, and a fourth insulating layer 84 is disposed between the third metal layer and the fourth metal layer.
  • a fifth metal layer is further provided on a side of the fourth metal layer away from the substrate.
  • a fifth insulating layer is disposed between the fourth metal layer and the fifth metal layer.
  • a sixth insulating layer and a light emitting element are sequentially disposed on the side of the fifth metal layer away from the substrate.
  • the light emitting element may include a first electrode, an organic light emitting layer, and a second electrode stacked on the sixth insulating layer.
  • the first electrode may be a transparent anode and the second electrode may be a reflective cathode, or the first electrode may be a reflective anode and the second electrode may be a transparent cathode.
  • the first electrode of the light-emitting element may be connected to the fifth metal layer through a via hole on the sixth insulating layer.
  • the semiconductor layer may have a curved or bent shape.
  • the semiconductor layers may include: a first active layer 11 , a second active layer 21 , a third active layer 31 , a fourth active layer 41 and a fifth active layer 51 .
  • the first metal layer may include: scan line G1, first control signal line G2, second control signal line G3, light emission control line EM, power supply connection line 71, first capacitor plate 61, second gate electrode 22, third The gate electrode 321 , the fourth gate electrode 322 , the fifth gate electrode 421 , the sixth gate electrode 422 , the seventh gate electrode 521 , and the eighth gate electrode 522 .
  • the scan line G1 , the first control signal line G2 , the second control signal line G3 , the light emission control line EM and the power supply connection line 71 all extend in the X direction.
  • the second metal layer may include: scan connection lines 72 extending along the X direction.
  • the third metal layer may include: a reference voltage line Vref, an initial voltage line Vini, and a second capacitor plate 62 . Both the reference voltage line Vref and the initial voltage line Vini extend in the X direction.
  • the fourth metal layer may include: a first power supply line VDD, a data line DL, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode electrode 34 , fourth source electrode 43 , fourth drain electrode 44 , fifth source electrode 53 and fifth drain electrode 54 .
  • the first power supply line VDD and the data line DL extend in the Y direction.
  • the first capacitor plate 61 may serve as the gate electrode of the first transistor T1.
  • the first active layer 11, the first capacitor plate 61, the first source electrode 13 and the first drain electrode 14 form the first transistor T1; the second active layer 21, the second gate electrode 22, the second source electrode 23 and
  • the second drain electrode 24 forms the second transistor T2.
  • the third active layer 31 , the third gate electrode 321 , the fourth gate electrode 322 , the third source electrode 33 and the third drain electrode 34 form a third transistor T3 .
  • the fourth active layer 41, the fifth gate electrode 421, the sixth gate electrode 422, the fourth source electrode 43 and the fourth drain electrode 44 form a fourth transistor T4.
  • the fifth active layer 51 , the seventh gate electrode 521 , the eighth gate electrode 522 , the fifth source electrode 53 and the fifth drain electrode 54 form a fifth transistor T5 .
  • the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are double gate transistors. In this exemplary embodiment, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 adopt a double gate design, which can reduce the drain electrodes of the transistors and ensure the correctness of the function of the pixel driving circuit.
  • the scan connection line 72 may be connected to the scan line G1 through a plurality of vias (eg, three vias).
  • the projection of the scan line 72 on the substrate 10 includes the projection of the scan line G1 on the substrate 10 .
  • Connecting the scan connection line 72 to the scan line G1 through at least one via hole can greatly reduce the resistance on the basis of ensuring that the parasitic capacitance on the scan line G1 is not increased, thereby reducing the load of the scan line G1, thereby ensuring the pixel The functional correctness of the drive circuit.
  • the shape and size of the scan connection line 72 are not limited in this embodiment.
  • the projection of the scan line G1 on the substrate 10 coincides with the first power line VDD of the fourth metal layer, the data line DL and the third drain electrode 34 of the third transistor T3
  • the projections on the substrate 10 overlap.
  • the scanning line G1 includes a first part and a second part which are connected in sequence along the X direction, the projection of the first part on the substrate 10 overlaps with the projection of the fourth metal layer on the substrate 10, and the projection of the second part on the substrate 10 is the same as the projection of the fourth metal layer on the substrate 10.
  • the projections of the fourth metal layer on the substrate 10 do not overlap.
  • the average length of the second portion in the Y direction is greater than the average length of the first portion in the Y direction.
  • the structure of the display substrate will be described below through an example of a manufacturing process of the display substrate.
  • the "patterning process" referred to in the present disclosure includes deposition of film layers, photoresist coating, mask exposure, development, etching and photoresist stripping treatments.
  • Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can use any one or more of spray coating and spin coating
  • etching can use any one or more of dry etching and wet etching. one or more.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the “film” may also be referred to as a "layer”. If the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the projection of A includes the projection of B means that the boundary of the projection of B falls within the boundary of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.
  • the manufacturing process of the display substrate may include the following operations, as shown in FIGS. 6 to 21 .
  • a sub-pixel is taken as an example for description, and an equivalent circuit diagram of a pixel driving circuit of the sub-pixel is shown in FIG. 2 .
  • the transistors in the pixel driving circuit may be N-type transistors.
  • a semiconductor layer pattern is formed.
  • a semiconductor thin film is deposited on the substrate 10, and the semiconductor thin film is patterned through a patterning process to form a semiconductor layer pattern.
  • the semiconductor layer may have a curved or bent shape.
  • the semiconductor layer pattern includes a first active layer 11 , a second active layer 21 , a third active layer 31 , a fourth active layer 41 and a fifth active layer 51 .
  • the first active layer 11 serves as the active layer of the first transistor T1
  • the second active layer 21 serves as the active layer of the second transistor T2
  • the third active layer 31 serves as the active layer of the third transistor T3
  • the fourth The active layer 41 serves as the active layer of the fourth transistor T4
  • the fifth active layer 51 serves as the active layer of the fifth transistor T5.
  • the active layer may include a channel region, a source region, and a drain region.
  • the channel region may not be doped with impurities and have semiconductor characteristics.
  • the source and drain regions may be on both sides of the channel region, and are doped with impurities and thus have conductivity. Impurities may vary depending on the type of transistor (eg, N-type or P-type).
  • the substrate 10 may be a rigid substrate or a flexible substrate.
  • the rigid substrate may include one or more of glass, metal foil.
  • Flexible substrates may include polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide One or more of amine, polyvinyl chloride, polyethylene, textile fibers. However, this embodiment does not limit this.
  • a material for fabricating the semiconductor layer may be polysilicon or metal oxide, which is not limited in this embodiment of the present disclosure.
  • a first insulating film and a first metal film are sequentially deposited on the substrate 10 on which the aforementioned patterns are formed, and the first metal film is patterned through a patterning process to form a first insulating layer 81 covering the semiconductor layer pattern. , and a first metal layer pattern formed on the first insulating layer 81 . As shown in FIG. 8 to FIG.
  • the first metal layer pattern includes: a scan line G1 , a first control signal line G2 , a second control signal line G3 , a light emission control line EM, a first capacitor plate 61 , and a power connection line 71 , the second gate electrode 22 , the third gate electrode 321 , the fourth gate electrode 322 , the fifth gate electrode 421 , the sixth gate electrode 422 , the seventh gate electrode 521 and the eighth gate electrode 522 .
  • the projection of the first capacitor plate 61 on the substrate 10 overlaps with the projection of the first active layer 11 on the substrate 10 .
  • the first capacitor plate 61 not only serves as a plate of the storage capacitor Cst, but also serves as a gate electrode of the first transistor T1. In other words, one plate of the storage capacitor Cst and the gate electrode of the first transistor T1 have an integrated structure.
  • the scan line G1 , the first control signal line G2 , the second control signal line G3 , the light emission control line EM and the power connection line 71 all extend along the X direction.
  • the first control signal line G2, the scan line G1, the second control signal line G3, the light emission control line EM and the power connection line 71 are sequentially arranged along the Y direction.
  • the first control signal line G2 and the third control signal line G3 are located on both sides of the scan line G1, the light emission control line EM is located on the side of the third control signal line G3 away from the scan line G1, and the power connection line 71 is located on the light emission control line.
  • the EM is on the side away from the scan line G1.
  • the scan line G1 includes a straight first edge 701 and a second edge 702 provided with a first protrusion 703 .
  • the first edge 701 is the upper edge of the scan line G1
  • the second edge 702 is the lower edge of the scan line G1. Both the first edge 701 and the second edge 702 extend in the X direction.
  • the first protrusion 703 is disposed on the second edge 702 and extends away from the second edge 702 .
  • the shape of the first protrusion 703 may be a rectangle. However, this embodiment does not limit this.
  • the first protrusion 703 includes a straight third edge 705 , and the third edge 705 is located on the side of the second edge 702 away from the first edge 701 .
  • the third edge 705 may extend in the X direction.
  • the first distance L1 between the second edge 702 and the first edge 701 is smaller than the second distance L2 between the third edge 705 and the first edge 701 .
  • the scan line G1 includes a first portion S1 and a second portion S2 connected in sequence along the X direction, and the first portion S1 and the second portion S2 are continuous regions.
  • the first protrusion 703 is formed at the second portion S2.
  • the second portion S2 is an area between the first edge 701 and the third edge 705, and the first portion S1 is an area other than the second portion S2.
  • the average length of the first portion S1 in the Y direction is smaller than the average length of the second portion S2 in the Y direction.
  • the fifth gate electrode 421 and the sixth gate electrode 422 are disposed on the third edge 705 .
  • the fifth gate electrode 421 and the sixth gate electrode 422 may be disposed at the third edge 705 along the X direction and extend in a direction away from the third edge 705 .
  • the shape and size of the fifth gate electrode 421 and the sixth gate electrode 422 may be the same, for example, both may be rectangular or square; or, the shapes and sizes of the two may be different, for example, the fifth gate electrode 421 may be The gate electrode 422 may be square.
  • the projections of the fifth gate electrode 421 and the sixth gate electrode 422 on the substrate 10 overlap with the fourth active layer 41 .
  • the fifth gate electrode 421 , the sixth gate electrode 422 and the scan line G1 may have an integral structure.
  • the first control signal line G2, the third gate electrode 321 and the fourth gate electrode 322 may have an integral structure. As shown in FIG. 8 , the first control signal line G2 includes a straight upper edge and a straight lower edge. The third gate electrode 321 and the fourth gate electrode 322 are disposed on the lower edge of the first control signal line G2 and extend in a direction away from the lower edge. The third gate electrode 321 and the fourth gate electrode 322 are disposed at the lower edge of the first control signal line G2 along the X direction. The shape and size of the third gate electrode 321 and the fourth gate electrode 322 may be the same, eg, both are rectangular or square, or the shape and size may be different. The projections of the third gate electrode 321 and the fourth gate electrode 322 on the substrate 10 overlap with the projection of the third active layer 31 on the substrate 10 .
  • the second control signal line G3 , the seventh gate electrode 521 and the eighth gate electrode 522 have an integral structure. As shown in FIG. 8 , the second control signal line G3 includes a straight upper edge and a straight lower edge. The second control signal line G3 overlaps with the projection of the fifth active layer 51 on the substrate 10 . The overlapping region of the second control signal line G3 and the fifth active layer 51 may serve as the seventh gate electrode 521 .
  • the eighth gate electrode 522 is disposed on the lower edge of the second control signal line G3 and extends in a direction away from the lower edge. The eighth gate electrode 522 may be rectangular or square. The projection of the eighth gate electrode 522 on the substrate 10 overlaps with the projection of the fifth active layer 51 on the substrate 10 .
  • the second control signal line may include an upper edge provided with bumps and a straight lower edge, and an overlapping region of the second control signal line and the fifth active layer may serve as a seventh gate electrode and an eighth gate electrode.
  • the electrodes may be disposed on the lower edge of the second control signal line and extend in a direction away from the lower edge.
  • the light emission control line EM and the second gate electrode 22 may be of an integrated structure. As shown in FIG. 8 , the light emission control line EM includes a straight upper edge and a straight lower edge. Both the upper edge and the lower edge of the light emission control line EM extend along the Y direction X.
  • the second gate electrode 22 is disposed on the lower edge of the light emission control line EM, and extends in a direction away from the lower edge.
  • the second gate electrode 22 may be rectangular or square. The projection of the second gate electrode 22 on the substrate 10 overlaps with the projection of the second active layer 21 on the substrate 10 .
  • the power connection line 71 may include an upper edge provided with the first bump 711 and the second bump 712 and a straight lower edge.
  • the first bump 711 and the second bump 712 are disposed on the upper edge of the power connection line 71 and extend in a direction away from the upper edge.
  • the first bumps 711 and the second bumps 712 are sequentially arranged on the upper edge of the power connection line 71 along the X direction.
  • the shape and size of the first bump 711 and the second bump 712 may be the same or different, for example, the first bump 711 and the second bump 712 are both rectangular, and the size of the first bump 711 is smaller than that of the second bump 712 size.
  • the power connection line 71 may include a straight upper edge and a straight lower edge.
  • a second insulating film is deposited on the substrate 10 on which the foregoing pattern is formed, and the second insulating film is patterned through a patterning process to form a second insulating layer pattern covering the foregoing structure.
  • the second insulating layer 82 is provided with a plurality of via hole patterns, and the plurality of via hole patterns at least include: three first via holes V1 located at the position of the scan line G1 .
  • the three first via holes V1 are arranged at intervals along the X direction, and the second insulating layer 82 in each of the first via holes V1 is etched away to expose the surface of the scan line G1.
  • the first via hole V1 may be rectangular or circular. This embodiment does not limit this.
  • a second metal thin film is deposited on the substrate 10 on which the aforementioned patterns are formed, the second metal thin film is patterned through a patterning process, and a second metal layer pattern is formed on the second insulating layer 82 .
  • the second metal layer pattern includes: scan connection lines 72 .
  • the scan connection line 72 includes a straight fourth edge 721 and a straight fifth edge 722 .
  • the fourth edge 721 is the upper edge of the scan connection line 72
  • the fifth edge 722 is the lower edge of the scan connection line 72 .
  • the projection of the scan connection line 72 on the substrate 10 may include the projection of the scan line G1 on the substrate 10 .
  • the projection of the fourth edge 721 on the substrate 10 may coincide with the projection of the first edge of the scan line G1 on the substrate 10, and the projection of the fifth edge 722 on the substrate 10 may coincide with the projection of the first protrusion of the scan line G1.
  • the projections of the third edge on the substrate 10 overlap.
  • the projections of the scan connection lines 72 on the substrate 10 and the projections of the fifth gate electrodes 421 and the sixth gate electrodes 422 on the substrate 10 may not overlap.
  • the scan connection line 72 is electrically connected to the scan line G1 through a plurality of first via holes (eg, three first via holes V1 ).
  • the resistance of the scan line G1 can be greatly reduced without increasing the parasitic capacitance, thereby reducing the load of the scan line , so that it satisfies the functionality of the driver.
  • a third metal layer pattern is formed.
  • a third insulating film and a third metal film are sequentially deposited on the substrate 10 formed with the aforementioned patterns, and the third metal film is patterned through a patterning process to form a third metal film covering the second metal layer.
  • the third metal layer pattern includes: a reference voltage line Vref, an initial voltage line Vini and a second capacitor plate 62 . Both the reference voltage line Vref and the initial voltage line Vini extend in the X direction.
  • the projection of the reference voltage line Vref on the substrate 10 is located on the side of the projection of the first control signal line G2 on the substrate 10 away from the projection of the scan connection line 72 on the substrate 10 .
  • the projection of the initial voltage line Vini on the substrate 10 is located between the projection of the second control signal line G3 and the emission control line EM on the substrate 10 .
  • the projection of the second capacitor plate 62 on the substrate 10 overlaps with the projection of the first capacitor plate 61 on the substrate 10 .
  • the reference voltage line Vref includes an upper edge provided with the third bump and a lower edge provided with the fourth bump.
  • the third bump is disposed on the upper edge of the reference voltage line Vref and extends away from the upper edge; the fourth bump is disposed on the lower edge of the reference voltage line Vref and extends away from the lower edge.
  • the positions of the third bump and the fourth bump correspond to each other.
  • the reference voltage line may include a straight upper edge and a straight lower edge.
  • the initial voltage line Vini includes an upper edge provided with fifth bumps and a straight lower edge.
  • the fifth bump is disposed on the upper edge of the initial voltage line Vini and extends in a direction away from the upper edge.
  • the initial voltage line may include a straight upper edge and a straight lower edge.
  • a fourth insulating layer pattern is formed.
  • a fourth insulating film is deposited on the substrate 10 formed with the foregoing pattern, and the fourth insulating film is patterned through a patterning process to form a fourth insulating layer 84 pattern covering the foregoing structure.
  • the fourth insulating layer 84 is provided with a plurality of via patterns, and the plurality of via patterns include: a second via V2 and a third via located on both sides of the first capacitor plate 61 .
  • the eleventh via hole V11 and the twelfth via hole V12 are located at the position of the first capacitor plate 61 and adjacent to the thirteenth via hole V13 of the fourth active layer 41, and are located on the thirteenth via hole V13 on both sides of the second control signal line G3
  • the fourth insulating layer 84 , the third insulating layer 83 , the second insulating layer 82 and the first insulating layer 81 in the second via hole V2 and the third via hole V3 are etched away, exposing the first active layer 11 surfaces at both ends.
  • the fourth insulating layer 84 in the fourth via hole V4 and the fifth via hole V5 is etched away, exposing the surfaces of both ends of the second capacitor electrode plate 62 .
  • the fourth insulating layer 84 , the third insulating layer 83 , the second insulating layer 82 and the first insulating layer 81 in the sixth via V6 and the seventh via V7 are etched away, exposing the second active layer 21 . surfaces at both ends.
  • the fourth insulating layer 84 , the third insulating layer 83 , the second insulating layer 82 and the first insulating layer 81 in the eighth via V8 and the ninth via V9 are etched away, exposing the third active layer 31 . surfaces at both ends.
  • the fourth insulating layer 84 in the tenth via hole V10 is etched away, exposing the surface of the reference voltage line Vref.
  • the fourth insulating layer 84 , the third insulating layer 83 , the second insulating layer 82 and the first insulating layer 81 in the eleventh via V11 and the twelfth via V12 are etched away, exposing the fourth active layer 41 on both ends of the surface.
  • the fourth insulating layer 84 , the third insulating layer 83 and the second insulating layer 82 in the thirteenth via V13 are etched away, exposing the surface of the first capacitor plate 61 .
  • the fourth insulating layer 84 , the third insulating layer 83 , the second insulating layer 82 and the first insulating layer 81 in the fourteenth via hole V14 and the fifteenth via hole V15 are etched away, exposing the fifth active layer 51 on both ends of the surface.
  • the fourth insulating layer 84 in the sixteenth via hole V16 is etched away, exposing the surface of the initial voltage line Vini.
  • the fourth insulating layer 84 , the third insulating layer 83 and the second insulating layer 82 in the seventeenth via hole V17 and the eighteenth via hole V18 are etched away, exposing the surface of the power connection line 71 .
  • the vias may be rectangular or circular. However, this embodiment does not limit this.
  • a fourth metal layer pattern is formed.
  • a fourth metal thin film is deposited on the substrate 10 on which the aforementioned patterns are formed, the fourth metal thin film is patterned through a patterning process, and a fourth metal layer pattern is formed on the fourth insulating layer 84 .
  • the fourth metal layer pattern includes: a data line DL, a first power supply line VDD, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, and a third source
  • the data line DL and the first power supply line VDD extend in the Y direction.
  • the first power line VDD is located on the side of the data line DL away from the first capacitor plate 61 .
  • the first source electrode 13 is connected to the first end of the first active layer 11 through the second via hole V2; the first drain electrode 14 is connected to the second end of the first active layer 11 through the third via hole V3, and the first The drain electrode 14 is also connected to the second capacitor plate 62 through the fourth via hole V4.
  • the second source electrode 23 is connected to the first end of the second active layer 21 through the sixth via hole V6, the second source electrode 23 is also connected to the power supply connection line 71 through the seventeenth via hole V17;
  • the seventh via hole V7 is connected to the second end of the second active layer 21 , the second drain electrode 24 is also connected to the first source electrode 13 , and the second drain electrode 24 and the first drain electrode 13 may have an integrated structure.
  • the third source electrode 33 is connected to the first end of the third active layer 31 through the eighth via hole V8, and the third source electrode 33 is also connected to the reference voltage line Vref through the tenth via hole V10.
  • the third drain electrode 34 is connected to the second end of the third active layer 31 through the ninth via hole V9.
  • the fourth source electrode 43 is connected to the first end of the fourth active layer 41 through the eleventh via V11, the fourth source electrode 43 is also connected to the data line DL, and the fourth source electrode 43 and the data line DL can be integrated into one structure .
  • the fourth drain electrode 44 is connected to the second end of the fourth active layer 41 through the twelfth via hole V12, and the fourth drain electrode 44 is also connected to the first capacitor plate 61 through the thirteenth via hole V13.
  • the third drain electrode 34 and the fourth drain electrode 44 are connected, and the third drain electrode 34 and the fourth drain electrode 44 may have an integrated structure.
  • the fifth source electrode 53 is connected to the first end of the fifth active layer 51 through the fourteenth via hole V14, and the fifth source electrode 53 is also electrically connected to the initial voltage line Vini through the sixteenth via hole V16.
  • the fifth drain electrode 54 is connected to the second end of the fifth active layer 51 through the fifteenth via hole V15, and the fifth drain electrode 54 is also connected to the second capacitor plate 62 through the fifth via hole V5.
  • the scan line G1 overlaps the projection of the data line DL, the first power line VDD and the third drain electrode 34 on the substrate 10 .
  • the region overlapping with the projection of the fourth metal layer on the substrate 10 is the first part of the scan line G1
  • the region not overlapping with the projection of the fourth metal layer on the substrate 10 is the second part of the scan line G1 .
  • the average length of the second portion in the Y direction is greater than the average length of the first portion in the Y direction.
  • a fifth metal layer pattern is formed.
  • a fifth insulating film is coated, and a fifth insulating layer pattern is formed by masking, exposing and developing the fifth insulating film, and then, at the fifth A fifth metal film is deposited on the insulating layer, and the fifth metal film is patterned through a patterning process to form a fifth metal layer pattern.
  • the fifth insulating layer 85 is provided with a plurality of via hole patterns, and the plurality of via hole patterns at least include: a nineteenth via hole V19 located at the position of the fifth drain electrode 54 .
  • the fifth insulating layer 85 in the nineteenth via hole V19 is etched away, exposing the surface of the fifth drain electrode 54 .
  • the fifth metal layer pattern includes at least the connection electrode 73 .
  • the connection electrode 73 is connected to the fifth drain electrode 54 through the nineteenth via hole V19.
  • a sixth insulating film is coated on the substrate 10 formed with the aforementioned pattern, and a sixth insulating layer pattern is formed by masking, exposing and developing the sixth insulating film, and the sixth insulating layer
  • the via pattern opened on the top includes at least: the twentieth via hole V20 located at the position of the connection electrode 73 .
  • the sixth insulating layer in the twentieth via hole V20 is etched away, exposing the surface of the connection electrode 73 .
  • an anode thin film is deposited, and the anode thin film is patterned through a patterning process to form an anode pattern on the sixth insulating layer.
  • the anode can be connected to the connection electrode 73 through the twentieth via hole V20 to realize the connection between the anode and the pixel driving circuit.
  • a pixel definition film is coated on the substrate 10 formed with the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed by masking, exposing and developing processes, and the pixel definition layer is formed in each sub-pixel in the display area.
  • the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode.
  • an organic light-emitting layer is formed in the pixel opening formed above, and the organic light-emitting layer is connected to the anode.
  • a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern, and the cathodes are respectively connected to the organic light-emitting layer and the second power supply line VSS.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material/organic material/inorganic material.
  • the second power supply line VSS may be disposed on the same layer as the connection electrode 73 , and the cathode may be connected to the second power supply line VSS in various ways, such as laser drilling and the like.
  • the first metal layer, the second metal layer, the third metal layer, the fourth metal layer and the fifth metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum ( Any one or more of Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure , such as Mo/Cu/Mo and so on.
  • metal materials such as silver (Ag), copper (Cu), aluminum ( Any one or more of Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the first insulating layer 81, the second insulating layer 82, the third insulating layer 83 and the fourth insulating layer 84 may be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) or more, it may be a single layer, multiple layers or composite layers.
  • the first insulating layer 81 is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer 82 and the third insulating layer 83 are called a gate insulating (GI) layer
  • the fourth insulating layer 84 It is called an interlayer insulating (ILD) layer.
  • the fifth insulating layer 85 and the sixth insulating layer may be organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the fifth insulating layer 85 and the sixth insulating layer are called flat layers.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy. However, this embodiment does not limit this.
  • the anode can be made of a reflective material such as metal, and the cathode can be made of a transparent conductive material.
  • the pixel driver circuit can be a 3T1C or 7T1C design.
  • other electrodes or leads may also be arranged in the film layer structure, which is not limited in the present disclosure.
  • the display substrate provided by the embodiments of the present disclosure can adopt double-layer wirings (that is, the scan lines of the first metal layer and the scan connection lines of the second metal layer)
  • the scan signal used to control the writing of the data signal is transmitted, and the scan line can be narrowed, so that the average length of the overlapping area of the scan line and the fourth metal layer along the second direction is smaller than that of the scan line and the fourth metal layer.
  • the average length of the overlapping regions along the second direction In this way, on the basis of not increasing the parasitic capacitance of the scan line, the resistance of the scan line can be greatly reduced, thereby reducing the load and ensuring the driving function requirements.
  • the driving requirements of high resolution (PPI) medium to large size products can be met.
  • the preparation process of the present disclosure can be realized by using the current mature preparation equipment, and can be well compatible with the existing preparation process.
  • the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.
  • FIG. 22 is a top view of a plurality of sub-pixels of a display substrate according to at least one embodiment of the disclosure. As shown in FIG. 22 , six sub-pixels of the display substrate are taken as an example for illustration. Six columns of sub-pixels are arranged between two adjacent first power lines VDD, and each column of sub-pixels is represented by one sub-pixel. For example, the i-th red sub-pixel Ri, the i-th green sub-pixel Gi, the i-th blue sub-pixel Bi, and the i+1-th red sub-pixel are sequentially arranged between two adjacent first power supply lines VDD. Ri+1, the i+1 th green subpixel Gi+1, and the i+1 th blue subpixel Bi+1.
  • the structure of the pixel driving circuit of each sub-pixel may be the same.
  • the first power supply line VDD is designed as a one-to-six structure. Under the same resolution, the size of each sub-pixel can be effectively increased, and the layout space can be fully utilized, and the overall layout is reasonable. .
  • the display substrate includes a substrate, a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer sequentially disposed on the substrate.
  • a first insulating layer is arranged between the semiconductor layer and the first metal layer
  • a second insulating layer is arranged between the first metal layer and the second metal layer
  • a third insulating layer is arranged between the second metal layer and the third metal layer layer
  • a fourth insulating layer is disposed between the third metal layer and the fourth metal layer.
  • a fifth insulating layer is disposed between the fourth metal layer and the fifth metal layer.
  • the semiconductor layer has a curved or folded shape.
  • the semiconductor layers may include a plurality of first active layers 11 , a plurality of second active layers 21 , a plurality of third active layers 31 , a plurality of fourth active layers 41 and a plurality of fifth active layers 51 .
  • the structure of the semiconductor layer of the pixel driving circuit of each sub-pixel may be the same.
  • the first metal layer may include: a scan line G1, a first control signal line G2, a second control signal line G3, a light emission control line EM, a power connection line 71, a first A capacitor plate 61 and gate electrodes of a plurality of transistors.
  • the scan line G1 , the first control signal line G2 , the second control signal line G3 , the light emission control line EM and the power supply connection line 71 all extend along the first direction.
  • the first control signal line G2 and the second control signal line G3 are located on both sides of the scan line G1, the light emission control line EM is located on the side of the second control signal line G3 away from the scan line G1, and the power connection line 71 is located away from the light emission control line EM.
  • the first capacitor plate 61 has an integrated structure with the gate electrode of the first transistor
  • the scanning line G1 has an integrated structure with the gate electrode of the fourth transistor
  • the first control signal line G2 has an integrated structure with the gate electrode of the third transistor
  • the second The control signal line G3 has an integrated structure with the gate electrode of the fifth transistor
  • the light emission control line EM has an integrated structure with the gate electrode of the second transistor.
  • the second metal layer may include: scan connection lines 72 extending along the first direction.
  • the projection of the scan connection line 72 on the substrate includes the projection of the scan line G1 on the substrate, and may not overlap with the gate electrode of the fourth transistor.
  • the scan connection line 72 may be connected to the scan line G1 through a plurality of first via holes (eg, three first via holes).
  • the third metal layer may include a reference voltage line Vref, an initial voltage line Vini, and a second capacitor plate 62 .
  • the reference voltage line Vref and the initial voltage line Vini extend in the first direction.
  • the reference voltage line Vref may be located on the side of the first control signal line G2 away from the scan line G1, and the initial voltage line Vini may be located between the second control signal line G3 and the light emission control line EM.
  • the position of the second capacitor plate 62 corresponds to the position of the first capacitor plate 61 .
  • the fourth metal layer may include: a first power supply line VDD, a data line corresponding to each column of sub-pixels (for example, a data line DL_Ri corresponding to the i-th red sub-pixel Ri, The data line DL_Gi corresponding to the ith green subpixel Gi, the data line DL_Bi corresponding to the ith blue subpixel Bi, the data line DL_Ri+1 corresponding to the ith+1th red subpixel Ri+1, and the i+1th data line The data line DL_Gi+1 corresponding to the green sub-pixel Gi+1, the data line DL_Bi+1 corresponding to the i+1 th blue sub-pixel Bi+1), and the source and drain electrodes of the plurality of transistors.
  • a data line corresponding to each column of sub-pixels for example, a data line DL_Ri corresponding to the i-th red sub-pixel Ri, The data line DL_Gi corresponding to the ith green subpixel Gi, the data line DL_B
  • the data line corresponding to each column of sub-pixels may be located on the left side of the sub-pixels.
  • the first power line VDD and the data line extend along a second direction, and the second direction is perpendicular to the first direction.
  • the structures of the source and drain electrodes of the plurality of transistors in the pixel driving circuit of each sub-pixel may be the same.
  • the fifth metal layer may at least include: a connection electrode 73 .
  • the connection electrode 73 can connect the pixel driving circuit of the sub-pixel and the first electrode of the light-emitting element.
  • this embodiment does not limit this.
  • At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate.
  • the display substrate includes a base and a plurality of sub-pixels disposed on the base. At least one sub-pixel in the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit; the pixel driving circuit includes a plurality of transistors and at least one storage capacitor.
  • the preparation method of this embodiment includes: sequentially forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer on a substrate. Wherein, the semiconductor layer includes active layers of a plurality of transistors.
  • the first metal layer at least includes: a scan line extending along the first direction, gate electrodes of a plurality of transistors, and a first capacitor electrode plate of a storage capacitor.
  • the second metal layer at least includes: scan connection lines extending along the first direction.
  • the insulating layer between the second metal layer and the first metal layer is provided with a first via hole, and the scan connection line contacts the scan line exposed through the first via hole.
  • the third metal layer at least includes: a second capacitor electrode plate of the storage capacitor.
  • the fourth metal layer at least includes: a data line extending along a second direction perpendicular to the first direction, and source and drain electrodes of a plurality of transistors.
  • the scan line includes a first portion and a second portion sequentially connected along the first direction.
  • the projection of the first part on the substrate overlaps with the projection of the fourth metal layer on the substrate, the projection of the second part on the substrate does not overlap the projection of the fourth metal layer on the substrate, and the second part is along the second direction
  • the average length of is greater than the average length of the first portion along the second direction.
  • sequentially forming a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer on the substrate includes: forming a semiconductor layer on the substrate, the semiconductor layer including: a first A first active layer of a transistor, a second active layer of a second transistor, a third active layer of a third transistor, a fourth active layer of a fourth transistor, and a fifth active layer of a fifth transistor; forming A first insulating layer covering the semiconductor layer; a first metal layer is formed on the first insulating layer, and the first metal layer includes: scan lines, first control signal lines, second control signal lines, light-emitting control lines, power supply connection lines, A first capacitor electrode of a storage capacitor and gate electrodes of a plurality of transistors; a second insulating layer covering the first metal layer is formed, and a first via hole exposing the scan line is formed on the second insulating layer; on the second insulating layer forming a second metal layer, the second metal layer includes
  • a plurality of via holes are formed on the fourth insulating layer, and the plurality of via holes include: a second via hole and a third via hole exposing both ends of the first active layer, and a fourth via exposing both ends of the second capacitor plate.
  • the via hole and the fifth via hole exposing the sixth via hole and the seventh via hole at both ends of the second active layer, exposing the eighth via hole and the ninth via hole at both ends of the third active layer, exposing the The tenth via hole of the reference voltage line exposes the eleventh via hole and the twelfth via hole at both ends of the fourth active layer, the thirteenth via hole of the first capacitor plate is exposed, and the fifth via hole is exposed.
  • the fourth metal layer includes: a data line, a first power line, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a third source electrode, a third drain electrode, a fourth source electrode, a third Four drain electrodes, fifth source electrodes, and fifth drain electrodes.
  • the first source electrode is connected to the first end of the first active layer through the second via hole
  • the first drain electrode is connected to the second end of the first active layer through the third via hole
  • the first drain electrode is connected to the second end of the first active layer through the fourth through hole.
  • the hole is connected to the second capacitor plate
  • the second source electrode is connected to the first end of the second active layer through the sixth via hole
  • the second source electrode is connected to the power supply connection line through the seventeenth via hole
  • the second drain electrode The seventh via hole is connected to the second end of the second active layer
  • the second drain electrode is connected to the first source electrode
  • the third source electrode is connected to the first end of the third active layer through the eighth via hole
  • the third source electrode is connected to the first end of the third active layer through the eighth via hole.
  • the three source electrodes are connected to the reference voltage line through the tenth via hole, the third drain electrode is connected to the second end of the third active layer through the ninth via hole, and the fourth source electrode is connected to the fourth active layer through the eleventh via hole
  • the first end of the layer is connected, the fourth source electrode is connected to the data line, the fourth drain electrode is connected to the second end of the fourth active layer through the twelfth via hole, and the fourth drain electrode is connected to the fourth active layer through the thirteenth via hole.
  • a capacitor plate is connected, the third drain electrode is connected to the fourth drain electrode, the fifth source electrode is connected to the first end of the fifth active layer through the fourteenth via hole, and the fifth source electrode is connected to the first end of the fifth active layer through the sixteenth via hole.
  • the initial voltage line is electrically connected, the fifth drain electrode is connected to the second end of the fifth active layer through the fifteenth via hole, and the fifth drain electrode is also connected to the second capacitor plate through the fifth via hole.
  • the preparation method of this embodiment further includes: forming a fifth insulating layer covering the fourth metal layer; forming a fifth metal layer on the fifth insulating layer, where the fifth metal layer includes: A connection electrode connected to the fifth drain electrode of the transistor; a sixth insulating layer covering the fifth metal layer is formed; a light-emitting element is formed on the sixth insulating layer, the anode of the light-emitting element is connected to the connection electrode, and the cathode of the light-emitting element is connected to the second power supply line connection.
  • FIG. 28 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • this embodiment provides a display device 91 including: a display substrate 910 .
  • the display substrate 910 is the display substrate provided in the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate.
  • the display device 91 can be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. However, this embodiment does not limit this.

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Abstract

一种显示基板，包括：基底以及设置在基底上的多个子像素。多个子像素中的至少一个子像素包括像素驱动电路和电连接像素驱动电路的发光元件。像素驱动电路包括多个晶体管和至少一个存储电容。在垂直于基底的方向上，显示基板包括：依次设置在基底上的半导体层、第一金属层、第二金属层、第三金属层和第四金属层。半导体层包括：多个晶体管的有源层。第一金属层至少包括：沿第一方向延伸的扫描线、多个晶体管的栅电极、存储电容的第一电容极板。第二金属层至少包括：沿第一方向延伸的扫描连接线。第三金属层至少包括：存储电容的第二电容极板。第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、多个晶体管的源漏电极。

Description

显示基板及其制备方法、显示装置
本申请要求于2020年9月16日提交中国专利局、申请号为202010972329.X、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)具有超薄、大视角、主动发光、高亮度、发光颜色连续可调、成本低、响应速度快、低功耗、工作温度范围宽及可柔性显示等优点，已逐渐成为极具发展前景的下一代显示技术，并且受到越来越多的关注。依据驱动方式的不同，OLED可以分为无源矩阵驱动(PM，Passive Matrix)型和有源矩阵驱动(AM，Active Matrix)型两种，AMOLED是电流驱动器件，采用独立的薄膜晶体管(TFT，Thin Film Transistor)控制每个子像素，每个子像素皆可以连续且独立的驱动发光。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：基底以及设置在所述基底上的多个子像素。所述多个子像素中的至少一个子像素包括像素驱动电路和电连接所述像素驱动电路的发光元件。所述像素驱动电路包括多个晶体管和至少一个存储电容。在垂直于所述基底的方向上，所述显示基板包括： 依次设置在所述基底上的半导体层、第一金属层、第二金属层、第三金属层和第四金属层。所述半导体层包括：多个晶体管的有源层。所述第一金属层至少包括：沿第一方向延伸的扫描线、所述多个晶体管的栅电极、所述存储电容的第一电容极板。所述第二金属层至少包括：沿第一方向延伸的扫描连接线；所述第二金属层和第一金属层之间的绝缘层设置有第一过孔，所述扫描连接线接触通过所述第一过孔暴露的所述扫描线。所述第三金属层至少包括：所述存储电容的第二电容极板。所述第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、所述多个晶体管的源漏电极。所述扫描线包括沿着第一方向依次连接的第一部分和第二部分。所述第一部分在基底上的投影与所述第四金属层在所述基底上的投影存在交叠，所述第二部分在基底上的投影与所述第四金属层在所述基底上的投影没有交叠。所述第二部分沿第二方向的平均长度大于所述第一部分沿第二方向的平均长度。
在一些示例性实施方式中，所述第一部分具有沿第一方向延伸的第一边缘和第二边缘，所述第二部分具有沿第一方向延伸的第一边缘和第三边缘，所述第二边缘和第三边缘沿着所述第二方向位于所述第一边缘的同一侧，且所述第三边缘位于所述第二边缘远离所述第一边缘的一侧。
在一些示例性实施方式中，所述第一边缘为所述第一部分和第二部分的上边缘，所述第二边缘为所述第一部分的下边缘，所述第三边缘为所述第二部分的下边缘。
在一些示例性实施方式中，所述扫描连接线在所述基底上的投影包含所述扫描线在所述基底上的投影。
在一些示例性实施方式中，所述第一金属层的材料为钼，所述第二金属层包括钛、铝和钛形成的三层堆叠结构。
在一些示例性实施方式中，所述第四金属层还包括：沿第二方向延伸的第一电源线；相邻两条第一电源线之间排布有六列子像素。
在一些示例性实施方式中，所述第一金属层还包括：沿第一方向延伸的电源连接线，所述电源连接线与所述第一电源线和所述六列子像素连接。
在一些示例性实施方式中，所述显示基板还包括：第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。所述第一绝缘层设置在所述半导体层和第 一金属层之间，所述第二绝缘层设置在所述第一金属层和第二金属层之间，所述第三绝缘层设置在所述第二金属层和所述第三金属层之间，所述第四绝缘层设置在所述第三金属层和所述第四金属层之间。
在一些示例性实施方式中，所述显示基板还包括：第五金属层，设置在所述第四金属层远离所述基底的一侧。所述第五金属层至少包括：电连接所述像素驱动电路和发光元件的连接电极。
在一些示例性实施方式中，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和存储电容。所述第一晶体管的栅电极与第三晶体管的第二极、所述存储电容的第一电容极板以及第四晶体管的第二极连接，所述第一晶体管的第一极与第二晶体管的第二极连接，所述第一晶体管的第二极与所述存储电容的第二电容极板、第五晶体管的第一极和发光元件的第一电极连接。所述第二晶体管的栅电极与发光控制线连接，所述第二晶体管的第一极与第一电源线连接。所述第三晶体管的栅电极与第一控制信号线连接，所述第三晶体管的第一极与参考电压线连接。所述第四晶体管的栅电极与扫描线连接，所述第四晶体管的第一极与数据线连接。所述第五晶体管的栅电极与第二控制信号线连接，所述第五晶体管的第二极与初始电压线连接。
在一些示例性实施方式中，所述第三晶体管、第四晶体管和第五晶体管为双栅晶体管；每个双栅晶体管包括两个相互连接的栅电极。
在一些示例性实施方式中，所述存储电容的第一电容极板与所述第一晶体管的栅电极为一体结构。
在一些示例性实施方式中，所述第一金属层还包括：第一控制信号线、第二控制信号线和发光控制线；所述第三金属层还包括：参考电压线和初始电压线。所述第一控制信号线、第二控制信号线、发光控制线、参考电压线和初始电压线均沿所述第一方向延伸。
在一些示例性实施方式中，沿着所述第二方向上，所述第一控制信号线和第二控制信号线位于所述扫描线的两侧，所述发光控制线位于所述第二控制信号线远离所述扫描线的一侧。所述参考电压线在基底上的投影位于所述第一控制信号线在基底上的投影远离所述扫描线在基底上的投影的一侧，所 述初始电压线在基底上的投影位于所述第二控制信号线和发光控制线在基底上的投影之间。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板的制备方法。所述显示基板包括基底和设置在所述基底上的多个子像素，所述多个子像素中的至少一个子像素包括像素驱动电路和电连接所述像素驱动电路的发光元件；所述像素驱动电路包括多个晶体管和至少一个存储电容。所述制备方法包括：在所述基底上依次形成半导体层、第一金属层、第二金属层、第三金属层和第四金属层。所述半导体层包括多个晶体管的有源层。所述第一金属层至少包括：沿第一方向延伸的扫描线、所述多个晶体管的栅电极、所述存储电容的第一电容极板。所述第二金属层至少包括：沿第一方向延伸的扫描连接线；所述第二金属层和第一金属层之间的绝缘层设置有第一过孔，所述扫描连接线接触通过所述第一过孔暴露的所述扫描线。所述第三金属层至少包括：所述存储电容的第二电容极板。所述第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、所述多个晶体管的源漏电极。所述扫描线包括沿着第一方向依次连接的第一部分和第二部分，所述第一部分在所述基底上的投影与所述第四金属层在所述基底上的投影存在交叠，所述第二部分在所述基底上的投影与所述第四金属层在所述基底上的投影没有交叠，所述第二部分沿所述第二方向的平均长度大于所述第一部分沿所述第二方向的平均长度。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例提供的显示基板的结构示意图；
图2为本公开至少一实施例提供的像素驱动电路的等效电路图；
图3为本公开至少一实施例提供的显示基板中一个子像素的俯视图；
图4为图3中P-P方向的剖面示意图；
图5为图3中Q-Q方向的剖面示意图；
图6为本公开至少一实施例中形成半导体层图案后的一个子像素的示意图；
图7为图6中Q-Q方向的剖面示意图；
图8为本公开至少一实施例中形成第一金属层图案后的一个子像素的示意图；
图9为图8中P-P方向的剖面示意图；
图10为图8中Q-Q方向的剖面示意图；
图11为本公开至少一实施例中形成第二绝缘层图案后的一个子像素的示意图；
图12为图11中P-P方向的剖面示意图；
图13为本公开至少一实施例中形成第二金属层图案后的一个子像素的示意图；
图14为图13中P-P方向的剖面示意图；
图15为本公开至少一实施例中形成第三金属层图案后的一个子像素的示意图；
图16为图15中Q-Q方向的剖面示意图；
图17为本公开至少一实施例中形成第四绝缘层图案后的一个子像素的示意图；
图18为图17中Q-Q方向的剖面示意图；
图19为本公开至少一实施例中形成第四金属层图案后的一个子像素的示意图；
图20为本公开至少一实施例中形成第五金属层图案后的一个子像素的示意图；
图21为图20中R-R方向的剖面示意图；
图22为本公开至少一实施例的显示基板的多个子像素的俯视图；
图23为本公开至少一实施例中形成半导体层图案后的多个子像素的示意图；
图24为本公开至少一实施例中形成第一金属层图案后的多个子像素的示意图；
图25为本公开至少一实施例中形成第二金属层图案后的多个子像素的示意图；
图26为本公开至少一实施例中形成第三金属层图案后的多个子像素的示意图；
图27为本公开至少一实施例中形成第四金属层图案后的多个子像素的示意图；
图28为本公开至少一实施例提供的显示装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖 直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
本公开至少一实施例提供一种显示基板，包括：基底以及设置在基底上的多个子像素。多个子像素中的至少一个子像素包括：像素驱动电路和电连接像素驱动电路的发光元件。像素驱动电路包括多个晶体管和至少一个存储电容。在垂直于基底的方向上，显示基板包括：依次设置在基底上的半导体层、第一金属层、第二金属层、第三金属层和第四金属层。半导体层包括：多个晶体管的有源层。第一金属层至少包括：沿第一方向延伸的扫描线、多个晶体管的栅电极、存储电容的第一电容极板。第二金属层至少包括：沿第一方向延伸的扫描连接线。第三金属层至少包括：存储电容的第二电容极板。第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、多个晶体管的源漏电极。第二金属层和第一金属层之间的绝缘层设置有第一过孔，扫描连接线接触通过第一过孔暴露的扫描线。扫描线包括沿着第一方向依次连接的第一部分和第二部分，第一部分在基底上的投影与第四金属层在基底上的投影存在交叠，第二部分在基底上的投影与第四金属层在基底上的投影没有交叠，第二部分沿第二方向的平均长度大于第一部分沿第二方向的平均长度。
在本公开中，“宽度”表示沿第一方向延伸的特征尺寸，“长度”表示沿第二方向延伸的特征尺寸。
本实施例提供的显示基板，通过将扫描线与第四金属层在基底的投影的交叠区域设计较窄，实现空间优化，而且，通过在第二金属层设置与扫描线连接的扫描连接线，可以在保证不增加扫描线的寄生电容的基础上，大幅度减小扫描线的电阻，进而减小扫描线的负载(Loading)，以满足驱动需求，保证驱动的功能性正常。
在一些示例性实施方式中，第一部分具有沿第一方向延伸的第一边缘和第二边缘，第二部分具有沿第一方向延伸的第一边缘和第三边缘，第二边缘和第三边缘沿着第二方向位于第一边缘的同一侧，且第三边缘位于第二边缘 远离第一边缘的一侧。在一些示例中，扫描线沿第一方向延伸，且具有平直的第一边缘和设置有第一凸起的第二边缘；第一凸起设置在第二边缘上，且向着远离第二边缘的方向延伸，第一凸起具有相对于第二边缘的第三边缘。第一凸起以及第一凸起所在位置对应的第二边缘和第一边缘之间的区域形成第二部分，除第二部分之外的区域为第一部分。第一凸起可以具有平直的第三边缘，且第三边缘可以平行于第二边缘。然而，本实施例对此并不限定。例如，第三边缘可以具有波浪结构。
在一些示例性实施方式中，第一边缘为扫描线的第一部分和第二部分的上边缘，第二边缘为扫描线的第一部分的下边缘，第三边缘为扫描线的第二部分的下边缘。然而，本实施例对此并不限定。例如，第一边缘可以为扫描线的第一部分和第二部分的下边缘，第二边缘可以为扫描线的第一部分的上边缘，第三边缘可以为扫描线的第二部分的上边缘。
在一些示例性实施方式中，扫描连接线在基底上的投影包含扫描线在基底上的投影。在一些示例中，扫描连接线可以具有平直的第四边缘和平直的第五边缘，第四边缘和第五边缘沿第一方向延伸，且第四边缘和第五边缘相对设置，第四边缘和第五边缘之间的距离(即扫描连接线沿第二方向的长度)可以大于或等于扫描线的第一边缘和第三边缘之间的最大距离(即扫描线的第二部分沿第二方向的最大长度)。然而，本实施例对此并不限定。例如，扫描连接线在基底上的投影可以与扫描线在基底上的投影重合，即，扫描连接线和扫描线的形状可以相同。又如，扫描连接线在基底上的投影可以与扫描线在基底上的投影部分交叠，比如，扫描连接线可以具有平直且沿着第一方向延伸的第四边缘和第五边缘，第四边缘和第五边缘相对设置，且第四边缘和第五边缘之间的距离小于或等于扫描线的第一边缘和第二边缘之间的距离。
在一些示例性实施方式中，第一金属层的材料为钼(Mo)，第二金属层包括钛(Ti)、铝(Al)、钛形成的三层堆叠结构。即，第二金属层可以包括依次堆叠的钛层、铝层和钛层。然而，本实施例对于第一金属层和第二金属层的材料并不限定。在一些示例中，第二金属层可以为单层金属结构。在本示例性实施方式中，采用电阻率较低的金属材料制备形成第二金属层，可 以降低扫描连接线的电阻。
在一些示例性实施方式中，第四金属层还包括：沿第二方向延伸的第一电源线。相邻两条第一电源线之间排布有六列子像素。在本示例性实施方式中，第一电源线设计为一拖六的结构，在相同的分辨率(PPI，Pixels Per Inch)下，可以有效增加每个子像素的尺寸，且具有充分利用布图空间、整体布局合理等优点。
在一些示例性实施方式中，第一金属层还包括：沿第一方向延伸的电源连接线，电源连接线与第一电源线和六列子像素连接。其中，电源连接线的延伸方向与第一电源线的延伸方向垂直。
在一些示例性实施方式中，显示基板还可以包括：第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。第一绝缘层设置在半导体层和第一金属层之间，第二绝缘层设置在第一金属层和第二金属层之间，第三绝缘层设置在第二金属层和所述第三金属层之间，第四绝缘层设置在第三金属层和第四金属层之间。在一些示例中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以为无机绝缘层。
在一些示例性实施方式中，显示基板还包括：第五金属层，设置在第四金属层远离基底的一侧；第五金属层至少包括：电连接像素驱动电路和发光元件的连接电极。在一些示例中，第一金属层可以称为第一栅金属层，第二金属层可以称为第二栅金属层，第三金属层可以称为第三栅金属层，第四金属层可以称为第一源漏金属层，第五金属层可以称为第二源漏金属层。
在一些示例性实施方式中，像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和存储电容。第一晶体管的栅电极与第三晶体管的第二极、存储电容的第一电容极板以及第四晶体管的第二极连接，第一晶体管的第一极与第二晶体管的第二极连接，第一晶体管的第二极与存储电容的第二电容极板、第五晶体管的第一极和发光元件的第一电极连接。第二晶体管的栅电极与发光控制线连接，第二晶体管的第一极与第一电源线连接；第三晶体管的栅电极与第一控制信号线连接，第三晶体管的第一极与参考电压线连接；第四晶体管的栅电极与扫描线连接，第四晶体管的第一极与数据线连接；第五晶体管的栅电极与第二控制信号线连接，第五 晶体管的第二极与初始电压线连接。其中，第一晶体管为驱动晶体管。在本示例性实施方式中，像素驱动电路可以采用5T1C设计。然而，本实施例对此并不限定。
在一些示例性实施方式中，第三晶体管、第四晶体管和第五晶体管为双栅晶体管；每个双栅晶体管包括两个相互连接的栅电极。本示例性实施方式中，通过采用双栅设计可以减小第三晶体管、第四晶体管和第五晶体管的漏电流，从而确保像素驱动电路的功能正确性。
在一些示例性实施方式中，存储电容的第一电容极板与第一晶体管的栅电极为一体结构。存储电容的第一电容极板在基底的投影与第一晶体管的有源层在基底的投影存在交叠。在本示例性实施方式中，通过将存储电容的第一电容极板与第一晶体管的栅电极设计为一体结构，具有充分利用布图空间、整体布局合理等优点。
在一些示例性实施方式中，第一金属层还包括：第一控制信号线、第二控制信号线和发光控制线；第三金属层还包括：参考电压线和初始电压线。第一控制信号线、第二控制信号线、发光控制线、参考电压线和初始电压线均沿第一方向延伸。
在一些示例性实施方式中，沿着第二方向上，第一控制信号线和第二控制信号线位于扫描线的两侧，发光控制线位于第二控制信号线远离扫描线的一侧。参考电压线在基底上的投影位于第一控制信号线在基底上的投影远离扫描线在基底上的投影的一侧，初始电压线在基底上的投影位于第二控制信号线和发光控制线在基底上的投影之间。然而，本实施例对此并不限定。
图1为本公开至少一实施例的显示基板的结构示意图。如图1所示，本示例性实施例的显示基板可以包括：显示区域AA以及位于显示区域AA周边的外围区域。显示区域AA可以设置有规则排布的多个子像素PA、沿着第一方向(如图1中的X方向)延伸的多条第一信号线(例如，包括扫描线G1、控制信号线和发光控制线EM)、沿着第二方向(如图1中的Y方向)延伸的多条第二信号线(例如，包括数据线DL和第一电源线)。其中，第一方向和第二方向可以位于同一平面内，且第一方向可以垂直于第二方向。例如，第一方向可以为行方向，平行于扫描线的延伸方向；第二方向可以为 列方向，平行于数据线的延伸方向。在本示例性实施方式中，至少一条第一信号线可以沿X方向延伸，且多条第一信号线可以沿Y方向顺序排列；至少一条第二信号线可以沿Y方向延伸，且多条第二信号线可以沿X方向顺序排列。多个子像素中的至少一个子像素PA可以包括：发光元件和用于驱动发光元件发光的像素驱动电路。像素驱动电路可以包括：多个晶体管和至少一个存储电容，例如，可以采用3T1C、5T1C或7T1C的设计。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图1所示，沿Y方向设置有m行扫描线G1<1>至G1<m>，沿X方向且设置有n列数据线DL<1>至DL<n>，扫描线与数据线相互绝缘。其中，m和n均为大于0的整数。子像素PA可以分布在m行扫描线和n列数据线的交叉位置，多个子像素PA按照矩阵状规则排布。在一些示例中，三个出射不同颜色光(例如，红绿蓝)的子像素或者四个出射不同颜色光(例如，红绿蓝白)的子像素可以组成一个像素单元。然而，本实施例对此并不限定。
为了便于区分扫描线以及子像素的行，在图1中有时从上起按顺序称为第1行、第2行、……、第m行。同样地，为了便于区分数据线以及子像素的列，在图1中有时从左起按顺序称为第1列、第2列、……、第n列。
在一些示例性实施方式中，如图1所示，外围区域可以设置有时序控制器、数据驱动电路、扫描驱动电路以及发光驱动电路。其中，扫描驱动电路和发光驱动电路可以设置在显示区域AA的相对两侧(例如，显示区域AA的左右两侧)，时序控制器和数据驱动电路可以设置在显示区域的一侧(例如，显示区域AA的上侧或下侧)。然而，本实施例对此并不限定。数据驱动电路可以通过多条数据线DL向多列子像素提供数据信号。扫描驱动电路可以通过多条扫描线G1向多行子像素提供扫描信号。扫描驱动电路除了扫描信号之外，还可以按行生成与扫描信号同步的至少一种控制信号(图1中省略示意)，并提供给显示区域的多行子像素。发光驱动电路可以通过多条发光控制线EM向多行子像素提供发光控制信号。时序控制器可以向数据驱动电路、扫描驱动电路以及发光驱动电路提供驱动信号。扫描驱动电路、数据驱动电路以及发光控制电路的动作可以由时序控制器控制。时序控制器可 以向数据驱动电路提供指定在子像素应显示灰度的灰度数据。数据驱动电路可以将与子像素的灰度数据对应的电位的数据信号，经由数据线提供给扫描驱动电路选择出的行的子像素。
图2为本公开至少一实施例的像素驱动电路的等效电路示意图。图2示意了一种5T1C的像素驱动电路的结构。如图2所示，一个子像素的像素驱动电路与扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM、第一电源线VDD、参考电压线Vref、初始电压线Vini和数据线DL电连接。像素驱动电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和存储电容Cst。
在一些示例性实施方式中，第一晶体管T1的栅电极与第三晶体管T3的第二极、存储电容Cst的第一电容极板以及第四晶体管T4的第二极连接，第一晶体管T1的第一极与第二晶体管T2的第二极连接，第一晶体管T1的第二极与存储电容Cst的第二电容极板、第五晶体管T5的第一极和发光元件EL的第一电极连接。第二晶体管T2的栅电极与发光控制线EM连接，第二晶体管T2的第一极与第一电源线VDD连接。第三晶体管T3的栅电极与第一控制信号线G2连接，第三晶体管T3的第一极与参考电压线Vref连接。第四晶体管T4的栅电极与扫描线G1连接，第四晶体管T4的第一极与数据线DL连接。第五晶体管T5的栅电极与第二控制信号线G3连接，第五晶体管T5的第二极与初始电压线Vini连接。发光元件EL的第二电极与第二电源线VSS连接。发光元件EL被配置为响应第一晶体管T1的第二极的电流而发出相应亮度的光。第五晶体管T5能够响应补偿的时序提取第一晶体管T1的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。存储电容Cst被配置为保持在一帧发光周期内第一晶体管T1的栅电极和第二极的节点电压。其中，第一晶体管T1为驱动晶体管，除第一晶体管T1之外的其他晶体管均为开关晶体管。本示例性实施方式提供的第一晶体管T1至第五晶体管T5可以均为P型晶体管或N型晶体管。本实施例对此并不限定。
在一些示例性实施方式中，第一晶体管T1至第五晶体管T5均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。本实施例提供的像素驱动电路中的晶体管均为同一种类型的晶体管，可以避免不同类 型的晶体管之间的差异性对像素驱动电路造成的影响。
图3为本公开至少一实施例的显示基板中的一个子像素的俯视图。图4为图3中P-P方向的剖面示意图。图5为图3中Q-Q方向的剖面示意图。如图3至图5所示，本示例性实施方式提供的显示基板的显示区域包括：基底10、依次设置在基底10上的半导体层、第一金属层、第二金属层、第三金属层和第四金属层。半导体层和第一金属层之间设置有第一绝缘层81，第一金属层和第二金属层之间设置有第二绝缘层82，第二金属层和第三金属层之间设置有第三绝缘层83，第三金属层和第四金属层之间设置有第四绝缘层84。在一些示例中，第四金属层远离基底的一侧还设置有第五金属层。第四金属层和第五金属层之间设置有第五绝缘层。第五金属层远离基底的一侧依次设置有第六绝缘层和发光元件。发光元件可以包括叠设在第六绝缘层上的第一电极、有机发光层和第二电极。第一电极可以为透明阳极，第二电极可以为反射阴极，或者，第一电极可以为反射阳极，第二电极可以为透明阴极。发光元件的第一电极可以通过第六绝缘层上的过孔与第五金属层连接。
在一些示例性实施方式中，如图3所示，半导体层可以具有弯曲或弯折形状。半导体层可以包括：第一有源层11、第二有源层21、第三有源层31、第四有源层41和第五有源层51。第一金属层可以包括：扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM、电源连接线71、第一电容极板61、第二栅电极22、第三栅电极321、第四栅电极322、第五栅电极421、第六栅电极422、第七栅电极521和第八栅电极522。扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM和电源连接线71均沿X方向延伸。第二金属层可以包括：沿X方向延伸的扫描连接线72。第三金属层可以包括：参考电压线Vref、初始电压线Vini以及第二电容极板62。参考电压线Vref和初始电压线Vini均沿X方向延伸。第四金属层可以包括：第一电源线VDD、数据线DL、第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34、第四源电极43、第四漏电极44、第五源电极53和第五漏电极54。第一电源线VDD和数据线DL沿Y方向延伸。第一电容极板61可以作为第一晶体管T1的栅电极。第一有源层11、第一电容极板61、第一源电极13和第一漏电极14形成第一 晶体管T1；第二有源层21、第二栅电极22、第二源电极23和第二漏电极24形成第二晶体管T2。第三有源层31、第三栅电极321、第四栅电极322、第三源电极33和第三漏电极34形成第三晶体管T3。第四有源层41、第五栅电极421、第六栅电极422、第四源电极43和第四漏电极44形成第四晶体管T4。第五有源层51、第七栅电极521、第八栅电极522、第五源电极53和第五漏电极54形成第五晶体管T5。第三晶体管T3、第四晶体管T4和第五晶体管T5为双栅晶体管。本示例性实施方式中，第三晶体管T3、第四晶体管T4和第五晶体管T5采用双栅设计，可以减小晶体管的漏电极，确保像素驱动电路的功能正确性。
在一些示例性实施方式中，如图3和图4所示，扫描连接线72可以通过多个过孔(例如，三个过孔)与扫描线G1连接。扫描连接线72在基底10上的投影包括扫描线G1在基底10上的投影。通过至少一个过孔将扫描连接线72和扫描线G1连接，可以在保证不增加扫描线G1上的寄生电容的基础上，大幅度减小电阻，进而减小扫描线G1的负载，从而保证像素驱动电路的功能正确性。本实施例对于扫描连接线72的形状和尺寸并不限定。
在一些示例性实施方式中，如图3所示，扫描线G1在基底10上的投影与第四金属层的第一电源线VDD、数据线DL和第三晶体管T3的第三漏电极34在基底10上的投影存在交叠。扫描线G1包括沿X方向依次连接的第一部分和第二部分，第一部分在基底10上的投影与第四金属层在基底10上的投影存在交叠，第二部分在基底10上的投影与第四金属层在基底10上的投影没有交叠。第二部分沿Y方向的平均长度大于第一部分沿Y方向的平均长度。本示例性实施方式中，通过对扫描线G1进行窄化设计，可以优化布图空间，并减少扫描线的寄生电容。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜” 还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的投影包含B的投影”，是指B的投影的边界落入A的投影的边界范围内，或者A的投影的边界与B的投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作，如图6至图21所示。本示例性实施方式中以一个子像素为例进行说明，且该子像素的像素驱动电路的等效电路图如图2所示。像素驱动电路中的晶体管可以为N型晶体管。
(1)形成半导体层图案。
在一些示例性实施方式中，在基底10上沉积半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成半导体层图案。如图6和图7所示，半导体层可以具有弯曲或弯折形状。半导体层图案包括第一有源层11、第二有源层21、第三有源层31、第四有源层41和第五有源层51。第一有源层11作为第一晶体管T1的有源层，第二有源层21作为第二晶体管T2的有源层，第三有源层31作为第三晶体管T3的有源层，第四有源层41作为第四晶体管T4的有源层，第五有源层51作为第五晶体管T5的有源层。在一些示例中，有源层可以包括沟道区、源极区和漏极区。沟道区可以不掺杂杂质，并具有半导体特性。源极区和漏极区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型(例如，N型或P型)而变化。
在一些示例性实施方式中，基底10可以为刚性衬底或柔性衬底。刚性衬底可以包括玻璃、金属箔片中的一种或多种。柔性衬底可以包括聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。然而，本实施例对此并不限定。
在一些示例性实施方式中，半导体层的制作材料可以为多晶硅或者金属氧化物，本公开实施例对此不作限定。
(2)形成第一金属层图案。
在一些示例性实施方式中，在形成前述图案的基底10上依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖半导体层图案的第一绝缘层81、以及形成在第一绝缘层81上的第一金属层图案。如图8至图10所示，第一金属层图案包括：扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM、第一电容极板61、电源连接线71、第二栅电极22、第三栅电极321、第四栅电极322、第五栅电极421、第六栅电极422、第七栅电极521和第八栅电极522。第一电容极板61在基底10上的投影与第一有源层11在基底10上的投影存在交叠。第一电容极板61既作为存储电容Cst的一个极板，又作为第一晶体管T1的栅电极。换言之，存储电容Cst的一个极板和第一晶体管T1的栅电极为一体结构。
在一些示例性实施方式中，如图8所示，扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM和电源连接线71均沿X方向延伸。第一控制信号线G2、扫描线G1、第二控制信号线G3、发光控制线EM和电源连接线71依次沿Y方向排布。其中，第一控制信号线G2和第三控制信号线G3位于扫描线G1的两侧，发光控制线EM位于第三控制信号线G3远离扫描线G1的一侧，电源连接线71位于发光控制线EM远离扫描线G1的一侧。
在一些示例性实施方式中，如图8所示，扫描线G1包括平直的第一边缘701和设置有第一凸起703的第二边缘702。第一边缘701为扫描线G1的上边缘，第二边缘702为扫描线G1的下边缘。第一边缘701和第二边缘702均沿X方向延伸。第一凸起703设置在第二边缘702上，且向着远离第二边缘702的方向延伸。第一凸起703的形状可以为矩形。然而，本实施例对此并不限定。第一凸起703包括平直的第三边缘705，第三边缘705位于第二边缘702远离第一边缘701的一侧。第三边缘705可以沿X方向延伸。第二边缘702与第一边缘701之间的第一距离L1小于第三边缘705与第一边缘701之间的第二距离L2。在本示例性实施方式中，扫描线G1包括沿X方向依次连接的第一部分S1和第二部分S2，第一部分S1和第二部分S2为连续区域。第一凸起703形成在第二部分S2。第二部分S2为第一边缘701 和第三边缘705之间的区域，第一部分S1除第二部分S2之外的区域。第一部分S1沿Y方向的平均长度小于第二部分S2沿Y方向的平均长度。
在一些示例性实施方式中，如图8所示，第五栅电极421和第六栅电极422设置在第三边缘705上。第五栅电极421和第六栅电极422可以沿X方向设置在第三边缘705，且向着远离第三边缘705的方向延伸。第五栅电极421和第六栅电极422的形状和尺寸可以相同，例如可以均为矩形或正方形；或者，两者的形状和尺寸可以不同，例如，第五栅电极421可以为矩形，第六栅电极422可以为正方形。第五栅电极421和第六栅电极422在基底10上的投影与第四有源层41存在交叠。在本示例中，第五栅电极421、第六栅电极422和扫描线G1可以为一体结构。
在一些示例性实施方式中，第一控制信号线G2、第三栅电极321和第四栅电极322可以为一体结构。如图8所示，第一控制信号线G2包括平直的上边缘和平直的下边缘。第三栅电极321和第四栅电极322设置在第一控制信号线G2的下边缘上，且向着远离该下边缘的方向延伸。第三栅电极321和第四栅电极322沿着X方向设置在第一控制信号线G2的下边缘。第三栅电极321和第四栅电极322的形状和尺寸可以相同，例如，两者均为矩形或正方形，或者形状和尺寸可以不同。第三栅电极321和第四栅电极322在基底10上的投影与第三有源层31在基底10上的投影存在交叠。
在一些示例性实施方式中，第二控制信号线G3、第七栅电极521和第八栅电极522为一体结构。如图8所示，第二控制信号线G3包括平直的上边缘和平直的下边缘。第二控制信号线G3与第五有源层51在基底10上的投影存在交叠。第二控制信号线G3与第五有源层51的交叠区域可以作为第七栅电极521。第八栅电极522设置在第二控制信号线G3的下边缘，且向着远离下边缘的方向延伸。第八栅电极522可以为矩形或正方形。第八栅电极522在基底10上的投影与第五有源层51在基底10上的投影存在交叠。然而，本实施例对此并不限定。在一些示例中，第二控制信号线可以包括设置有凸块的上边缘和平直的下边缘，第二控制信号线与第五有源层的交叠区域可以作为第七栅电极，第八栅电极可以设置在第二控制信号线的下边缘上，且向着远离下边缘的方向延伸。
在一些示例性实施方式中，发光控制线EM和第二栅电极22可以为一体结构。如图8所示，发光控制线EM包括平直的上边缘和平直的下边缘。发光控制线EM的上边缘和下边缘均沿着Y方向X延伸。第二栅电极22设置在发光控制线EM的下边缘上，且向着远离下边缘的方向延伸。第二栅电极22可以为矩形或正方形。第二栅电极22在基底10上的投影与第二有源层21在基底10上的投影存在交叠。
在一些示例性实施方式中，电源连接线71可以包括设置有第一凸块711和第二凸块712的上边缘和平直的下边缘。第一凸块711和第二凸块712设置在电源连接线71的上边缘上，且向着远离上边缘的方向延伸。第一凸块711和第二凸块712沿X方向依次排布在电源连接线71的上边缘上。第一凸块711和第二凸块712的形状和尺寸可以相同或不同，例如，第一凸块711和第二凸块712均为矩形，且第一凸块711的尺寸小于第二凸块712的尺寸。然而，本实施例对此并不限定。在一些示例中，电源连接线71可以包括平直的上边缘和平直的下边缘。
(3)形成第二绝缘层图案。
在一些示例性实施方式中，在形成前述图案的基底10上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成覆盖前述结构的第二绝缘层图案。如图11和图12所示，第二绝缘层82上开设有多个过孔图案，多个过孔图案至少包括：位于扫描线G1所在位置的三个第一过孔V1。三个第一过孔V1沿X方向间隔设置，且每个第一过孔V1内的第二绝缘层82被刻蚀掉，暴露出扫描线G1的表面。第一过孔V1可以呈矩形或圆形。本实施例对此并不限定。
(4)形成第二金属层图案。
在一些示例性实施方式中，在形成前述图案的基底10上，沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，在第二绝缘层82上形成第二金属层图案。如图13和图14所示，第二金属层图案包括：扫描连接线72。扫描连接线72包括平直的第四边缘721和平直的第五边缘722。第四边缘721为扫描连接线72的上边缘，第五边缘722为扫描连接线72的下边缘。扫描连接线72在基底10上的投影可以包括扫描线G1在基底10上的投影。例如， 第四边缘721在基底10上的投影可以与扫描线G1的第一边缘在基底10上的投影重合，第五边缘722在基底10上的投影可以与扫描线G1的第一凸起的第三边缘在基底10上的投影交叠。扫描连接线72在基底10上的投影与第五栅电极421和第六栅电极422在基底10上的投影可以没有交叠。扫描连接线72通过多个第一过孔(例如，三个第一过孔V1)与扫描线G1电连接。通过对扫描线G1进行窄化设计，并电连接扫描线G1和扫描连接线72，可以在保证不增加寄生电容的基础上，大幅度减小扫描线G1的电阻，进而减小扫描线的负载，使其满足驱动的功能性正常。
(5)形成第三金属层图案。
在一些示例性实施方式中，在形成有前述图案的基底10上，依次沉积第三绝缘薄膜和第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成覆盖第二金属层的第三绝缘层83、以及形成在第三绝缘层83上的第三金属层图案。如图15和图16所示，第三金属层图案包括：参考电压线Vref、初始电压线Vini以及第二电容极板62。参考电压线Vref和初始电压线Vini均沿X方向延伸。参考电压线Vref在基底10上的投影位于第一控制信号线G2在基底10上的投影远离扫描连接线72在基底10上的投影的一侧。初始电压线Vini在基底10上的投影位于第二控制信号线G3和发光控制线EM在基底10上的投影之间。第二电容极板62在基底10上的投影与第一电容极板61在基底10上的投影存在交叠。
在一些示例性实施方式中，如图15所示，参考电压线Vref包括设置有第三凸块的上边缘和设置有第四凸块的下边缘。第三凸块设置在参考电压线Vref的上边缘上，且向着远离上边缘的方向延伸；第四凸块设置在参考电压线Vref的下边缘，且向着远离下边缘的方向延伸。第三凸块和第四凸块的位置对应。然而，本实施例对此并不限定。在一些示例中，参考电压线可以包括平直的上边缘和平直的下边缘。
在一些示例性实施方式中，如图15所示，初始电压线Vini包括设置有第五凸块的上边缘和平直的下边缘。第五凸块设置在初始电压线Vini的上边缘上，且向着远离上边缘的方向延伸。然而，本实施例对此并不限定。在一些示例中，初始电压线可以包括平直的上边缘和平直的下边缘。
(6)形成第四绝缘层图案。
在一些示例性实施方式中，在形成有前述图案的基底10上，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖前述结构的第四绝缘层84图案。如图17和图18所示，第四绝缘层84上开设有多个过孔图案，多个过孔图案包括：位于第一电容极板61两侧的第二过孔V2和第三过孔V3，位于第二电容极板62两端的第四过孔V4和第五过孔V5，位于第二栅电极22两侧的第六过孔V6和第七过孔V7，位于第三栅电极321和第四栅电极322两侧的第八过孔V8和第九过孔V9，位于参考电压线Vref所在位置的第十过孔V10，位于第五栅电极421和第六栅电极422两侧的第十一过孔V11和第十二过孔V12，位于第一电容极板61所在位置且邻近第四有源层41的第十三过孔V13，位于第二控制信号线G3两侧的第十四过孔V14和第十五过孔V15，位于初始电压线Vini的第五凸块所在位置的第十六过孔V16，位于电源连接线71的第二凸块所在位置的第十七过孔V17和第一凸块所在位置的第十八过孔V18。第二过孔V2和第三过孔V3内的第四绝缘层84、第三绝缘层83、第二绝缘层82和第一绝缘层81被刻蚀掉，暴露出第一有源层11的两端的表面。第四过孔V4和第五过孔V5内的第四绝缘层84被刻蚀掉，暴露出第二电容极板62的两端的表面。第六过孔V6和第七过孔V7内的第四绝缘层84、第三绝缘层83、第二绝缘层82和第一绝缘层81被刻蚀掉，暴露出第二有源层21的两端的表面。第八过孔V8和第九过孔V9内的第四绝缘层84、第三绝缘层83、第二绝缘层82和第一绝缘层81被刻蚀掉，暴露出第三有源层31的两端的表面。第十过孔V10内的第四绝缘层84被刻蚀掉，暴露出参考电压线Vref的表面。第十一过孔V11和第十二过孔V12内的第四绝缘层84、第三绝缘层83、第二绝缘层82和第一绝缘层81被刻蚀掉，暴露出第四有源层41的两端的表面。第十三过孔V13内的第四绝缘层84、第三绝缘层83和第二绝缘层82被刻蚀掉，暴露出第一电容极板61的表面。第十四过孔V14和第十五过孔V15内的第四绝缘层84、第三绝缘层83、第二绝缘层82和第一绝缘层81被刻蚀掉，暴露出第五有源层51的两端的表面。第十六过孔V16内的第四绝缘层84被刻蚀掉，暴露出初始电压线Vini的表面。第十七过孔V17和第十八过孔V18内的第四绝缘层84、第三绝缘层83和第二绝缘层82被刻蚀掉，暴露出电源连接线71的表面。在 一些示例中，上述过孔可以呈矩形或圆形。然而，本实施例对此并不限定。
(7)形成第四金属层图案。
在一些示例性实施方式中，在形成前述图案的基底10上，沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，在第四绝缘层84上形成第四金属层图案。如图19所示，第四金属层图案包括：数据线DL、第一电源线VDD、第一源电极13、第一漏电极14、第二源电极23、第二漏电极24、第三源电极33、第三漏电极34、第四源电极43、第四漏电极44、第五源电极53和第五漏电极54。数据线DL和第一电源线VDD沿Y方向延伸。第一电源线VDD位于数据线DL远离第一电容极板61的一侧。第一源电极13通过第二过孔V2与第一有源层11的第一端连接；第一漏电极14通过第三过孔V3与第一有源层11的第二端连接，第一漏电极14还通过第四过孔V4与第二电容极板62连接。第二源电极23通过第六过孔V6与第二有源层21的第一端连接，第二源电极23还通过第十七过孔V17与电源连接线71连接；第二漏电极24通过第七过孔V7与第二有源层21的第二端连接，第二漏电极24还与第一源电极13连接，第二漏电极24与第一漏电极13可以为一体结构。第三源电极33通过第八过孔V8与第三有源层31的第一端连接，第三源电极33还通过第十过孔V10与参考电压线Vref连接。第三漏电极34通过第九过孔V9与第三有源层31的第二端连接。第四源电极43通过第十一过孔V11与第四有源层41的第一端连接，第四源电极43还与数据线DL连接，第四源电极43与数据线DL可以为一体结构。第四漏电极44通过第十二过孔V12与第四有源层41的第二端连接，第四漏电极44还通过第十三过孔V13与第一电容极板61连接。第三漏电极34和第四漏电极44连接，第三漏电极34和第四漏电极44可以为一体结构。第五源电极53通过第十四过孔V14与第五有源层51的第一端连接，第五源电极53还通过第十六过孔V16与初始电压线Vini电连接。第五漏电极54通过第十五过孔V15与第五有源层51的第二端连接，第五漏电极54还通过第五过孔V5与第二电容极板62连接。
在一些示例性实施方式中，如图3至图5及图19所示，扫描线G1与数据线DL、第一电源线VDD和第三漏电极34在基底10上的投影存在交叠。 与第四金属层在基底10的投影存在交叠的区域为扫描线G1的第一部分，与第四金属层在基底10的投影没有交叠的区域为扫描线G1的第二部分。第二部分沿Y方向的平均长度大于第一部分沿Y方向的平均长度。根据扫描线G1与第四金属层的投影的交叠区域对扫描线G1进行窄化设计，可以优化空间，并减小扫描线的寄生电容。
(8)形成第五金属层图案。
在一些示例性实施方式中，在形成前述图案的基底10上，涂覆第五绝缘薄膜，通过对第五绝缘薄膜的掩膜、曝光和显影，形成第五绝缘层图案，然后，在第五绝缘层上沉积第五金属薄膜，通过构图工艺对第五金属薄膜进行构图，形成第五金属层图案。如图20和图21所示，第五绝缘层85上开设有多个过孔图案，多个过孔图案至少包括：位于第五漏电极54所在位置的第十九过孔V19。第十九过孔V19内的第五绝缘层85被刻蚀掉，暴露出第五漏电极54的表面。第五金属层图案至少包括连接电极73。连接电极73通过第十九过孔V19与第五漏电极54连接。
(9)形成第六绝缘层、阳极、像素定义层、有机发光层、阴极和封装层图案。
在一些示例性实施方式中，在形成有前述图案的基底10上，涂覆第六绝缘薄膜，通过对第六绝缘薄膜的掩膜、曝光和显影，形成第六绝缘层图案，第六绝缘层上开设的过孔图案至少包括：位于连接电极73所在位置的第二十过孔V20。第二十过孔V20内的第六绝缘层被刻蚀掉，暴露出连接电极73的表面。随后，在形成有前述图案的基底10上，沉积阳极薄膜，通过构图工艺对阳极薄膜进行构图，在第六绝缘层上形成阳极图案。阳极可以通过第二十过孔V20与连接电极73连接，实现阳极与像素驱动电路的连接。然后，在形成前述图案的基底10上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)图案，像素定义层形成在在显示区域的每个子像素中，每个子像素中的像素定义层形成有暴露出阳极的像素开口。随后，在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过构图工艺对阴极薄膜进行构图，形成阴极图案，阴极分别与有机发光层和第二电源线VSS连接。随后，在阴极上形成 封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。在一些可能的实现方式中，第二电源线VSS可以与连接电极73同层设置，阴极可以通过多种方式与第二电源线VSS连接，如激光打孔等。
在一些示例性实施方式中，第一金属层、第二金属层、第三金属层、第四金属层和第五金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层81、第二绝缘层82、第三绝缘层83和第四绝缘层84可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层81称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层82和第三绝缘层83称之为栅绝缘(GI)层，第四绝缘层84称之为层间绝缘(ILD)层。第五绝缘层85和第六绝缘层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。第五绝缘层85和第六绝缘层称之为平坦层。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。然而，本实施例对此并不限定。例如，阳极可以采用金属等反射材料，阴极可以采用透明导电材料。
本公开所示结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，像素驱动电路可以是3T1C或7T1C设计。再如，膜层结构中还可以设置其它电极或引线，本公开在此不做限定。
通过以上描述的显示基板的结构和制备流程可以看出，本公开实施例所提供的显示基板，可以采用双层走线(即第一金属层的扫描线和第二金属层的扫描连接线)传输用于控制数据信号写入的扫描信号，而且可以对扫描线进行窄化设计，使得扫描线与第四金属层的交叠区域沿第二方向的平均长度小于扫描线与第四金属层没有交叠的区域沿第二方向的平均长度。如此一来，可以在不增加扫描线的寄生电容的基础上，大幅度减小扫描线的电阻，进而 减小负载，保证驱动功能需求。在一些示例中，可以满足高分辨率(PPI)的中大尺寸产品的驱动需求。
本公开的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图22为本公开至少一实施例的显示基板的多个子像素的俯视图。如图22所示，以显示基板的六个子像素为例进行示意。在相邻两个第一电源线VDD之间排布有六列子像素，每列子像素以一个子像素示意。例如，相邻两个第一电源线VDD之间依次排布有第i个红色子像素Ri、第i个绿色子像素Gi、第i个蓝色子像素Bi、第i+1个红色子像素Ri+1、第i+1个绿色子像素Gi+1和第i+1个蓝色子像素Bi+1。每个子像素的像素驱动电路的结构可以相同。本示例性实施方式中，将第一电源线VDD设计为一拖六的结构，在相同的分辨率下，可以有效增加每个子像素的尺寸，且具有充分利用布图空间、整体布局合理等优点。
在一些示例性实施方式中，显示基板包括：基底、依次设置在基底上的半导体层、第一金属层、第二金属层、第三金属层、第四金属层和第五金属层。半导体层和第一金属层之间设置有第一绝缘层，第一金属层和第二金属层之间设置有第二绝缘层，第二金属层和第三金属层之间设置有第三绝缘层，第三金属层和第四金属层之间设置有第四绝缘层。第四金属层和第五金属层之间设置有第五绝缘层。
在一些示例性实施方式中，如图23所示，半导体层具有弯曲或弯折形状。半导体层可以包括：多个第一有源层11、多个第二有源层21、多个第三有源层31、多个第四有源层41和多个第五有源层51。每个子像素的像素驱动电路的半导体层的结构可以相同。
在一些示例性实施方式中，如图24所示，第一金属层可以包括：扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM、电源连接线71、第一电容极板61以及多个晶体管的栅电极。扫描线G1、第一控制信号线G2、第二控制信号线G3、发光控制线EM和电源连接线71均沿第一方向延伸。第一控制信号线G2和第二控制信号线G3位于扫描线G1的两侧， 发光控制线EM位于第二控制信号线G3远离扫描线G1的一侧，电源连接线71位于发光控制线EM远离扫描线G1的一侧。第一电容极板61与第一晶体管的栅电极为一体结构，扫描线G1与第四晶体管的栅电极为一体结构，第一控制信号线G2与第三晶体管的栅电极为一体结构，第二控制信号线G3与第五晶体管的栅电极为一体结构，发光控制线EM与第二晶体管的栅电极为一体结构。
在一些示例性实施方式中，如图25所示，第二金属层可以包括：沿第一方向延伸的扫描连接线72。扫描连接线72在基底上的投影包含扫描线G1在基底上的投影，且与第四晶体管的栅电极可以没有交叠。扫描连接线72可以通过多个第一过孔(例如，三个第一过孔)与扫描线G1连接。
在一些示例性实施方式中，如图26所示，第三金属层可以包括：参考电压线Vref、初始电压线Vini以及第二电容极板62。参考电压线Vref和初始电压线Vini沿第一方向延伸。参考电压线Vref可以位于第一控制信号线G2远离扫描线G1的一侧，初始电压线Vini可以位于第二控制信号线G3和发光控制线EM之间。第二电容极板62的位置与第一电容极板61的位置对应。
在一些示例性实施方式中，如图27所示，第四金属层可以包括：第一电源线VDD、每列子像素对应的数据线(例如，第i个红色子像素Ri对应的数据线DL_Ri、第i个绿色子像素Gi对应的数据线DL_Gi、第i个蓝色子像素Bi对应的数据线DL_Bi、第i+1个红色子像素Ri+1对应的数据线DL_Ri+1、第i+1个绿色子像素Gi+1对应的数据线DL_Gi+1、第i+1个蓝色子像素Bi+1对应的数据线DL_Bi+1)、多个晶体管的源漏电极。每列子像素对应的数据线可以位于子像素的左侧。第一电源线VDD和数据线沿第二方向延伸，第二方向垂直于第一方向。每个子像素的像素驱动电路的多个晶体管的源漏电极的结构可以相同。
在一些示例性实施方式中，如图22所示，第五金属层至少可以包括：连接电极73。连接电极73可以连接子像素的像素驱动电路和发光元件的第一电极。然而，本实施例对此并不限定。
关于每个子像素的像素驱动电路的详细结构可以参照上述实施例的说明，故于此不再赘述。
本公开至少一实施例还提供一种显示基板的制备方法。显示基板包括基底和设置在基底上的多个子像素。多个子像素中的至少一个子像素包括像素驱动电路和电连接像素驱动电路的发光元件；像素驱动电路包括多个晶体管和至少一个存储电容。本实施例的制备方法包括：在基底上依次形成半导体层、第一金属层、第二金属层、第三金属层和第四金属层。其中，半导体层包括多个晶体管的有源层。第一金属层至少包括：沿第一方向延伸的扫描线、多个晶体管的栅电极、存储电容的第一电容极板。第二金属层至少包括：沿第一方向延伸的扫描连接线。第二金属层和第一金属层之间的绝缘层设置有第一过孔，扫描连接线接触通过第一过孔暴露的所述扫描线。第三金属层至少包括：存储电容的第二电容极板。第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、多个晶体管的源漏电极。扫描线包括沿着第一方向依次连接的第一部分和第二部分。第一部分在基底上的投影与第四金属层在基底上的投影存在交叠，第二部分在基底上的投影与第四金属层在基底上的投影没有交叠，第二部分沿第二方向的平均长度大于第一部分沿第二方向的平均长度。
在一些示例性实施方式中，在基底上依次形成半导体层、第一金属层、第二金属层、第三金属层和第四金属层，包括：在基底上形成半导体层，半导体层包括：第一晶体管的第一有源层、第二晶体管的第二有源层、第三晶体管的第三有源层、第四晶体管的第四有源层和第五晶体管的第五有源层；形成覆盖半导体层的第一绝缘层；在第一绝缘层上形成第一金属层，第一金属层包括：扫描线、第一控制信号线、第二控制信号线、发光控制线、电源连接线、存储电容的第一电容电极以及多个晶体管的栅电极；形成覆盖第一金属层的第二绝缘层，第二绝缘层上形成有暴露出扫描线的第一过孔；在第二绝缘层上形成第二金属层，第二金属层包括扫描连接线，扫描连接线通过第一过孔与扫描线连接；形成覆盖第二金属层的第三绝缘层；在第三绝缘层上形成第三金属层，第三金属层包括：存储电容的第二电容电极；形成覆盖第三金属层的第四绝缘层；在第四绝缘层上形成第四金属层。第四绝缘层上形成有多个过孔，多个过孔包括：暴露出第一有源层的两端的第二过孔和第三过孔，暴露出第二电容极板的两端的第四过孔和第五过孔，暴露出第二有源层的两端的第六过孔和第七过孔，暴露出第三有源层的两端的第八过孔和 第九过孔，暴露出参考电压线的第十过孔，暴露出第四有源层的两端的第十一过孔和第十二过孔，暴露出第一电容极板的第十三过孔，暴露出第五有源层的两端的第十四过孔和第十五过孔，暴露出初始电压线的第十六过孔，暴露出电源连接线的第十七过孔和第十八过孔。第四金属层包括：数据线、第一电源线、第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极、第四源电极、第四漏电极、第五源电极和第五漏电极。第一源电极通过第二过孔与第一有源层的第一端连接，第一漏电极通过第三过孔与第一有源层的第二端连接，第一漏电极通过第四过孔与第二电容极板连接，第二源电极通过第六过孔与第二有源层的第一端连接，第二源电极通过第十七过孔与电源连接线连接，第二漏电极通过第七过孔与第二有源层的第二端连接，第二漏电极与第一源电极连接，第三源电极通过第八过孔与第三有源层的第一端连接，第三源电极通过第十过孔与参考电压线连接，第三漏电极通过第九过孔与第三有源层的第二端连接，第四源电极通过第十一过孔与第四有源层的第一端连接，第四源电极与数据线连接，第四漏电极通过第十二过孔与第四有源层的第二端连接，第四漏电极通过第十三过孔与第一电容极板连接，第三漏电极和第四漏电极连接，第五源电极通过第十四过孔与第五有源层的第一端连接，第五源电极通过第十六过孔与初始电压线电连接，第五漏电极通过第十五过孔与第五有源层的第二端连接，第五漏电极还通过第五过孔与第二电容极板连接。
在一些示例性实施方式中，本实施例的制备方法还包括：形成覆盖第四金属层的第五绝缘层；在第五绝缘层上形成第五金属层，第五金属层包括：与第五晶体管的第五漏电极连接的连接电极；形成覆盖第五金属层的第六绝缘层；在第六绝缘层上形成发光元件，发光元件的阳极与连接电极连接，发光元件的阴极与第二电源线连接。
关于本实施例的制备方法可以参照前述实施例的说明，故于此不再赘述。
图28为本公开至少一实施例的显示装置的示意图。如图28所示，本实施例提供一种显示装置91，包括：显示基板910。显示基板910为前述实施例提供的显示基板。其中，显示基板910可以为OLED显示基板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电 脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (16)

  1. 一种显示基板，包括：
    基底以及设置在所述基底上的多个子像素，所述多个子像素中的至少一个子像素包括像素驱动电路和电连接所述像素驱动电路的发光元件；所述像素驱动电路包括多个晶体管和至少一个存储电容；
    在垂直于所述基底的方向上，所述显示基板包括：依次设置在所述基底上的半导体层、第一金属层、第二金属层、第三金属层和第四金属层；
    所述半导体层包括：多个晶体管的有源层；
    所述第一金属层至少包括：沿第一方向延伸的扫描线、所述多个晶体管的栅电极、所述存储电容的第一电容极板；
    所述第二金属层至少包括：沿第一方向延伸的扫描连接线；所述第二金属层和第一金属层之间的绝缘层设置有第一过孔，所述扫描连接线接触通过所述第一过孔暴露的所述扫描线；
    所述第三金属层至少包括：所述存储电容的第二电容极板；
    所述第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、所述多个晶体管的源漏电极；
    所述扫描线包括沿着第一方向依次连接的第一部分和第二部分，所述第一部分在所述基底上的投影与所述第四金属层在所述基底上的投影存在交叠，所述第二部分在所述基底上的投影与所述第四金属层在所述基底上的投影没有交叠，所述第二部分沿所述第二方向的平均长度大于所述第一部分沿所述第二方向的平均长度。
  2. 根据权利要求1所述的显示基板，其中，所述第一部分具有沿第一方向延伸的第一边缘和第二边缘，所述第二部分具有沿第一方向延伸的第一边缘和第三边缘，所述第二边缘和第三边缘沿着所述第二方向位于所述第一边缘的同一侧，且所述第三边缘位于所述第二边缘远离所述第一边缘的一侧。
  3. 根据权利要求2所述的显示基板，其中，所述第一边缘为所述第一部分和第二部分的上边缘，所述第二边缘为所述第一部分的下边缘，所述第三边缘为所述第二部分的下边缘。
  4. 根据权利要求1所述的显示基板，其中，所述扫描连接线在所述基底上的投影包含所述扫描线在所述基底上的投影。
  5. 根据权利要求1所述的显示基板，其中，所述第一金属层的材料为钼，所述第二金属层包括钛、铝和钛形成的三层堆叠结构。
  6. 根据权利要求1所述的显示基板，其中，所述第四金属层还包括：沿第二方向延伸的第一电源线；相邻两条第一电源线之间排布有六列子像素。
  7. 根据权利要求6所述的显示基板，其中，所述第一金属层还包括：沿第一方向延伸的电源连接线，所述电源连接线与所述第一电源线和所述六列子像素连接。
  8. 根据权利要求1所述的显示基板，还包括：第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；
    所述第一绝缘层设置在所述半导体层和第一金属层之间，所述第二绝缘层设置在所述第一金属层和第二金属层之间，所述第三绝缘层设置在所述第二金属层和所述第三金属层之间，所述第四绝缘层设置在所述第三金属层和所述第四金属层之间。
  9. 根据权利要求1所述的显示基板，还包括：第五金属层，设置在所述第四金属层远离所述基底的一侧；
    所述第五金属层至少包括：电连接所述像素驱动电路和发光元件的连接电极。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述像素驱动电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和存储电容；
    所述第一晶体管的栅电极与第三晶体管的第二极、所述存储电容的第一电容极板以及第四晶体管的第二极连接，所述第一晶体管的第一极与第二晶体管的第二极连接，所述第一晶体管的第二极与所述存储电容的第二电容极板、第五晶体管的第一极和发光元件的第一电极连接；
    所述第二晶体管的栅电极与发光控制线连接，所述第二晶体管的第一极与第一电源线连接；
    所述第三晶体管的栅电极与第一控制信号线连接，所述第三晶体管的第一极与参考电压线连接；
    所述第四晶体管的栅电极与扫描线连接，所述第四晶体管的第一极与数据线连接；
    所述第五晶体管的栅电极与第二控制信号线连接，所述第五晶体管的第二极与初始电压线连接。
  11. 根据权利要求10所述的显示基板，其中，所述第三晶体管、第四晶体管和第五晶体管为双栅晶体管；每个双栅晶体管包括两个相互连接的栅电极。
  12. 根据权利要求10所述的显示基板，其中，所述存储电容的第一电容极板与所述第一晶体管的栅电极为一体结构。
  13. 根据权利要求10所述的显示基板，其中，所述第一金属层还包括：第一控制信号线、第二控制信号线和发光控制线；
    所述第三金属层还包括：参考电压线和初始电压线；
    所述第一控制信号线、第二控制信号线、发光控制线、参考电压线和初始电压线均沿所述第一方向延伸。
  14. 根据权利要求13所述的显示基板，其中，沿着所述第二方向上，所述第一控制信号线和第二控制信号线位于所述扫描线的两侧，所述发光控制线位于所述第二控制信号线远离所述扫描线的一侧；
    所述参考电压线在基底上的投影位于所述第一控制信号线在基底上的投影远离所述扫描线在基底上的投影的一侧，所述初始电压线在基底上的投影位于所述第二控制信号线和发光控制线在基底上的投影之间。
  15. 一种显示装置，包括如权利要求1至14中任一项所述的显示基板。
  16. 一种显示基板的制备方法，所述显示基板包括基底和设置在所述基底上的多个子像素，所述多个子像素中的至少一个子像素包括像素驱动电路和电连接所述像素驱动电路的发光元件；所述像素驱动电路包括多个晶体管和至少一个存储电容；
    所述制备方法包括：
    在所述基底上依次形成半导体层、第一金属层、第二金属层、第三金属层和第四金属层；所述半导体层包括多个晶体管的有源层；所述第一金属层至少包括：沿第一方向延伸的扫描线、所述多个晶体管的栅电极、所述存储电容的第一电容极板；所述第二金属层至少包括：沿第一方向延伸的扫描连接线；所述第二金属层和第一金属层之间的绝缘层设置有第一过孔，所述扫描连接线接触通过所述第一过孔暴露的所述扫描线；所述第三金属层至少包括：所述存储电容的第二电容极板；所述第四金属层至少包括：沿垂直于第一方向的第二方向延伸的数据线、所述多个晶体管的源漏电极；
    所述扫描线包括沿着第一方向依次连接的第一部分和第二部分，所述第一部分在所述基底上的投影与所述第四金属层在所述基底上的投影存在交叠，所述第二部分在所述基底上的投影与所述第四金属层在所述基底上的投影没有交叠，所述第二部分沿所述第二方向的平均长度大于所述第一部分沿所述第二方向的平均长度。
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