WO2023028944A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023028944A1
WO2023028944A1 PCT/CN2021/116217 CN2021116217W WO2023028944A1 WO 2023028944 A1 WO2023028944 A1 WO 2023028944A1 CN 2021116217 W CN2021116217 W CN 2021116217W WO 2023028944 A1 WO2023028944 A1 WO 2023028944A1
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Prior art keywords
initialization signal
signal line
sub
transistor
pixels
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PCT/CN2021/116217
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English (en)
French (fr)
Inventor
刘彪
尚庭华
杨慧娟
马宏伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21955484.7A priority Critical patent/EP4307860A4/en
Priority to PCT/CN2021/116217 priority patent/WO2023028944A1/zh
Priority to US17/758,085 priority patent/US20240177659A1/en
Priority to CN202180002425.4A priority patent/CN116097925A/zh
Priority to CN202210014451.5A priority patent/CN114373773A/zh
Publication of WO2023028944A1 publication Critical patent/WO2023028944A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to but not limited to the field of display technology, and in particular relates to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • an embodiment of the present disclosure provides a display substrate, including:
  • a plurality of sub-pixels distributed in an array at least one of the sub-pixels includes a pixel driving circuit and a light-emitting device, and the plurality of sub-pixels form an array of M rows*N columns, and M and N are positive integers greater than or equal to 1;
  • the driving circuit includes a plurality of transistors, the plurality of transistors include driving transistors;
  • the light emitting device includes a first electrode;
  • the base substrate further includes: a first initialization signal line, a second initialization signal line; the first initialization signal line and the second initialization signal line extend along a first direction, and the first direction is the sub-pixel row the direction of extension;
  • the first initialization signal lines are respectively electrically connected to the sub-pixels in the m-th row, and are configured to transmit the first initialization signal to the control electrodes of the drive transistors of the sub-pixels in the m-th row;
  • the second initialization signal lines respectively electrically connected to the sub-pixels in the m-1th row, and configured to transmit a second initialization signal to the first electrode of the light-emitting device of the m-1th row of sub-pixels;
  • the projection of the first initialization signal line on the base substrate is located far away from the projection of the second initialization signal line on the base substrate
  • the second direction is the extension direction of the sub-pixel column, and m is a positive integer greater than or equal to 1 and less than or equal to M;
  • the first initialization signal is different from the second initialization signal.
  • the first initialization signal line and the second initialization signal line are located between the driving transistors of two adjacent rows of sub-pixels, and are located in the same row of the driving transistors in any row in the second direction. side.
  • the width of the first initialization signal line is different from the width of the second initialization signal line.
  • the width of the second initialization signal line is greater than the width of the first initialization signal line.
  • the width of the second initialization signal line is 1.3 to 2.4 times the width of the first initialization signal line.
  • the display substrate further includes: a reset signal line extending along the first direction for transmitting a reset signal to the pixel driving circuit;
  • the plurality of transistors also includes: a first reset transistor and a second reset transistor;
  • the first reset transistor is configured to transmit the first initialization signal on the first initialization signal line to the control electrode of the drive transistor of the m-th row of sub-pixels under the control of the reset signal;
  • the second reset transistor is configured to transmit the second initialization signal on the second initialization signal line to the first electrode of the light emitting device of the m-1th row of sub-pixels under the control of the reset signal.
  • the reset signal line, the second initialization signal line, and the first initialization signal line are arranged in sequence along a direction away from the sub-pixel driving transistors in the m-th row.
  • the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged on the base substrate;
  • the semiconductor layer includes the active layer of the plurality of transistors, the active layer includes the channel region and the source and drain regions of the transistor; the first conductive layer includes the reset signal line and the control electrode of the transistor; The second conductive layer includes the first initialization signal line and the second initialization signal line; the third conductive layer includes a first power line, and the fourth conductive layer includes a second power line and a data signal line.
  • the display substrate further includes: a third initialization signal line extending along the second direction, wherein the third initialization signal line is arranged in a different layer from the first initialization signal line, and the first initialization signal line
  • the three initialization signal lines are electrically connected to the first initialization signal line or the second initialization signal line.
  • the third conductive layer further includes the third initialization signal line.
  • the third initialization signal lines are electrically connected to the first initialization signal lines and distributed in a mesh shape.
  • At least one column of sub-pixels is provided between adjacent third initialization signal lines.
  • At least two first power supply lines are arranged between adjacent third initialization signal lines.
  • the multiple sub-pixels include red sub-pixels that emit red light, blue sub-pixels that emit blue light, and green sub-pixels that emit green light
  • the plurality of pixel columns include red and blue pixel columns and green pixels column;
  • the red and blue pixel column includes red sub-pixels and blue sub-pixels arranged alternately in the second direction;
  • the green pixel column includes green sub-pixels arranged in sequence along the second direction;
  • the third initialization The signal lines are located in the red and blue pixel columns.
  • the shape of the third initialization signal line electrically connected to the red and blue pixel columns in the nth column is the shape of the third initialization signal line electrically connected to the red and blue pixel columns in the n+1th column
  • n is a positive integer greater than or equal to 1 and less than or equal to N.
  • the third initialization signal line includes a first extension, a second extension, and a third extension sequentially connected along the second direction.
  • the first extension part extends along the second direction and is electrically connected to the first initialization signal line through a via hole.
  • the extension direction of the third extension part is different from the extension direction of the first extension part, the second extension part is used to connect the first extension part and the third extension part, and the second extension part The extension direction deviates from the second direction.
  • the projection of the first extension portion on the base substrate has an overlapping area with the projections of the reset signal line, the first initialization signal line, and the second initialization signal line on the base substrate .
  • the first extension part is connected to the first pole of the first transistor through a via hole.
  • the second extension forms an angle greater than 90° and less than 180° with the first extension
  • the third extension forms an angle greater than 90° and less than 180° with the second extension
  • the multiple transistors further include: a second transistor, the first pole of the second transistor is electrically connected to the second pole of the driving transistor, and the second pole of the second transistor is electrically connected to the driving transistor.
  • the control electrode of the transistor is electrically connected;
  • the second conductive layer further includes: a shielding portion, the shielding portion is electrically connected to the first power line, the projection of the shielding portion on the base substrate covers at least part of the source and drain regions of the second transistor and The projection of the data signal line on the base substrate is located between the projections of adjacent data signal lines on the base substrate.
  • the third conductive layer further includes a fourth connection portion and a fifth connection portion
  • the fourth conductive layer further includes a seventh connection portion
  • the seventh connection portion is connected to the fourth connection portion and the fifth connection portion.
  • the fifth connecting part is electrically connected.
  • the shape of the fourth connection part is different from that of the fifth connection part.
  • an embodiment of the present disclosure further provides a display device, including the display substrate as described in any one of the preceding embodiments.
  • the display substrate and the display device described in the embodiments of the present disclosure adopt the first initialization signal line to reset the gate of the sub-pixel driving transistor in the m-th row, and use the second initialization to the first electrode of the sub-pixel light-emitting element in the m-1th row.
  • the signal line is reset, and the first initialization signal and the second initialization signal are different signals, so that the gate of the drive transistor and the first electrode of the light-emitting element can be reset better, so that in the black state, the OLED display substrate can be guaranteed to have Lower brightness improves display uniformity.
  • the embodiments of the present disclosure also provide a display substrate and a display device, which have third initialization signal lines distributed in specific pixel columns, the third initialization signal lines and the first initialization signal lines or the second initialization signal lines form a mesh circuit.
  • the connection can significantly reduce the impedance of the initialization signal line and improve the picture quality.
  • FIG. 1a is a schematic plan view of a display substrate in an embodiment of the present disclosure
  • FIG. 1b is a schematic plan view of another display substrate in an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 3 is a schematic circuit structure diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 4 is a possible timing diagram in a driving method of the pixel driving circuit in FIG. 3;
  • FIG. 5 is a schematic diagram showing the structure of an exemplary embodiment of a substrate in the present disclosure.
  • FIG. 6a is a schematic structural view showing the semiconductor layer of the substrate in FIG. 5;
  • FIG. 6b is an enlarged view of a schematic diagram of a semiconductor layer structure in a sub-pixel region in FIG. 5;
  • FIG. 7 is a schematic structural view showing a first conductive layer of the substrate shown in FIG. 5;
  • FIG. 8 is a schematic structural view showing a second conductive layer of the substrate shown in FIG. 5;
  • FIG. 9 is a schematic structural view showing a third conductive layer of the substrate shown in FIG. 5;
  • FIG. 10 is a schematic structural view showing a fourth conductive layer of the substrate shown in FIG. 5;
  • FIG. 11 is a schematic diagram showing the structure of an exemplary embodiment of a substrate in the present disclosure.
  • FIG. 12a is a schematic structural view showing a third conductive layer of the substrate shown in FIG. 11;
  • FIG. 12b is an enlarged view of a schematic structural diagram of a third conductive layer in a sub-pixel region in FIG. 11;
  • FIG. 13 is a schematic diagram showing the connection of the first initialization signal line and the third initialization signal line in the substrate shown in FIG. 11;
  • Fig. 14 is a schematic diagram showing the stacked structure of the substrate semiconductor layer and the first conductive layer in Fig. 5 and Fig. 11;
  • Fig. 15 is a schematic diagram of the structure in Fig. 11 and the stacked structure of the fifth conductive layer;
  • FIG. 16 is a schematic diagram showing the structure of the fifth conductive layer of the substrate shown in FIG. 15;
  • Fig. 17 is a schematic cross-sectional structure diagram of A-A' in Fig. 15;
  • Fig. 18 is a schematic cross-sectional structure diagram of B-B' in Fig. 15;
  • Fig. 19a, Fig. 19b, Fig. 19c are schematic diagrams of some wiring structures in the peripheral area in Fig. 11 .
  • 21 reset signal line
  • 22 first scanning signal line
  • 221 first protrusion
  • 341 the first through hole; 41—the third initialization signal line; 42—the first power line;
  • 531 the flat portion of the first color
  • 532 the flat portion of the second color
  • 533 the flat portion of the third color
  • 61 first electrode
  • 61a main part
  • 61b auxiliary part
  • 71 the first insulating layer
  • 72 the second insulating layer
  • 73 the third insulating layer
  • 91 luminescent layer
  • 91 second electrode
  • 001 substrate substrate
  • 102 drive circuit layer
  • 103 light emitting structure layer
  • 104 encapsulation layer
  • 401 the first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged, and “source terminal” and “drain terminal” can be interchanged.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • the scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. Adjustment.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure, and the figures described in this disclosure are only structural schematic diagrams.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • shapes such as triangle, rectangle, trapezoid, pentagon or hexagon refer to corresponding shapes such as approximately triangle, rectangle, trapezoid, pentagon or hexagon within the range of process and measurement errors.
  • it may include deformations such as chamfers, arc edges, rounded corners, and bumps that occur within the tolerance range.
  • FIG. 1 a is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first-color sub-pixel P1 that emits light of a first color, and a sub-pixel P1 that emits light of a second color.
  • the second color sub-pixel P2 and two third-color sub-pixels P3 that emit light of the third color, the four sub-pixels may all include a pixel driving circuit and a light emitting device, and the pixel driving circuit in each sub-pixel is respectively connected to the scanning signal line, the data The signal line is connected to the light emitting control signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output corresponding current to the light emitting device under the control of the scanning signal line and the light emitting control signal line.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first color sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the pixel driving circuit of the sub-pixel P1 is electrically connected to the first electrode of the light emitting device that emits red light
  • the second The color sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the pixel driving circuit of the sub-pixel P2 is electrically connected to the first electrode of the light-emitting device that emits blue light
  • the third sub-pixel P3 may be a blue sub-pixel that emits blue light.
  • the pixel driving circuit of the sub-pixel P3 is electrically connected to the first electrode of the light-emitting device that emits green light.
  • the shape of the first electrode of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the first electrodes of the four sub-pixels can be arranged in a square manner to form a GGRB pixel arrangement, as shown in Figure 1a; they can also be arranged in a diamond manner to form an RGBG pixel arrangement, as shown in Figure 1b.
  • the four sub-pixels may be arranged horizontally or vertically.
  • a pixel unit may include three sub-pixels, and the first electrodes of the three sub-pixels may be arranged horizontally or vertically. Straight side by side or arranged in characters, etc., the present disclosure is not limited here.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit.
  • the pixel driving circuit can be a 2T1C, 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, where T represents a thin film transistor and C represents a storage capacitor.
  • T represents a thin film transistor
  • C represents a storage capacitor.
  • FIG. 2 the structure of the pixel driving circuit is simply illustrated by taking only one driving transistor 210 and one storage capacitor 211 as an example.
  • the display substrate has a base substrate 001, and the base substrate 001 can be a flexible base substrate or a rigid base substrate.
  • the light-emitting structure layer 103 of each sub-pixel may include multiple film layers, and the multiple film layers may include a first electrode 301, a pixel definition layer 8, a light-emitting layer 303, and a second electrode 304, and the first electrode 301 communicates with the driving transistor through a via hole.
  • the drain electrode of 210 is connected, the organic light-emitting layer 303 is connected to the first electrode 301, the second electrode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of a corresponding color under the drive of the first electrode 301 and the second electrode 304.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short), and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers of all sub-pixels may be a common layer connected together
  • the electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers of all sub-pixels may be a common layer connected together as The common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light-emitting layer and electron blocking layer of adjacent sub-pixels Layers can have a small amount of overlap, or can be isolated.
  • FIG. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel drive circuit may include seven transistors: a first reset transistor T1, a second transistor T2, a drive transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a second reset transistor T7 , 1 storage capacitor C.
  • the node connected to the gate of the drive transistor is the first node N1
  • the node connected to the first pole of the drive transistor T3 and the fourth transistor T4 is the second node N2
  • the position connected to the second transistor T2 and the drive transistor T3 is the first node N2.
  • the first pole of the first reset transistor T1 is connected to the first initialization signal terminal INIT1
  • the control pole of the first transistor is connected to the first reset signal terminal Re1
  • the second pole of the first reset transistor T1 is connected to the first node N1 ;
  • the control electrode of the second transistor T2 is connected to the first scanning signal terminal S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3; when When the conduction level scanning signal is applied to the first scanning signal terminal S1, the second transistor T2 connects the control electrode of the driving transistor T3 to the second electrode.
  • the control electrode of the drive transistor T3 is connected to the first node N1, that is, the control electrode of the drive transistor T3 is connected to the second plate of the storage capacitor C, the first electrode of the drive transistor T3 is connected to the second node N2, and the first electrode of the drive transistor T3 is connected to the second node N2.
  • the two poles are connected to the third node N3.
  • the driving transistor T3 determines the driving current value flowing between the first power signal terminal VDD and the second power signal terminal VSS according to the potential difference between its control electrode and the first electrode, so as to drive the light emitting device to emit light.
  • the first pole of the fourth transistor T4 is connected to the data signal terminal DATA
  • the second pole of the fourth transistor T4 is connected to the second pole of the driving transistor T3
  • the control pole of the fourth transistor T4 is connected to the first scanning signal terminal S1;
  • the fourth transistor T4 is configured to input the data voltage provided by the data signal terminal DATA to the pixel driving circuit.
  • the control pole of the fifth transistor T5 is connected to the light emitting signal control terminal EM, the first pole of the fifth transistor T5 is connected to the first power signal terminal VDD, the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor T3, That is, the second pole of the fifth transistor T5 is connected to the second node N2; the control pole of the sixth transistor is connected to the light-emitting signal control terminal EM, the first pole of the sixth transistor is connected to the second pole of the driving transistor T3, and the sixth transistor The second pole of the sixth transistor T6 is connected to the first electrode of the light emitting device, and the first pole of the sixth transistor T6 is connected to the third node N3.
  • the fifth transistor T5 and the sixth transistor T6 make the light-emitting device emit light by forming a driving current path between the first power signal terminal VDD and the second power signal terminal VSS .
  • the control pole of the second reset transistor T7 is connected to the second reset signal terminal Re2, the first pole of the second reset transistor T7 is connected to the second initialization signal terminal INIT2, and the second pole of the second reset transistor T7 is connected to the first terminal of the light emitting device. Electrode connection.
  • the second reset transistor T7 transmits the second initialization signal to the first electrode of the light emitting device, so that the amount of charge accumulated in the first electrode of the light emitting device is initialized Or release the amount of charge accumulated in the first electrode of the light emitting device.
  • the storage capacitor C has a first plate and a second plate, the first plate is connected to the first power signal terminal VDD, and the second plate is connected to the first node N1. That is, the second plate of the storage capacitor C is connected to the control electrode of the driving transistor T3.
  • the light emitting device may be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) arranged in a stack, or may be a QLED including a first electrode (anode) arranged in a stack , a quantum dot luminescent layer and a second electrode (cathode).
  • the second electrode of the light-emitting device is connected to the second power signal terminal VSS, the signal of the second power signal terminal VSS is a low-level signal, and the signal of the first power signal terminal VDD is continuously provided with a high level.
  • the second reset signal terminal Re2 is Re(m)
  • the first reset signal terminal Re1 is Re(m-1)
  • the first reset signal terminal Re1 of this display line is connected with the pixel drive circuit of the previous display line
  • the second reset signal terminal Re2 can be the same signal, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the seven transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product.
  • the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the transistor in the pixel circuit may use a low temperature polysilicon thin film transistor, or may use an oxide thin film transistor, or may use a low temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form a low-temperature polysilicon thin-film transistor.
  • Oxide transistor (Low Temperature Poly-Silicon+Oxide, LTPO for short) display substrate can take advantage of the advantages of both, can realize low-frequency drive, can reduce power consumption, and can improve display quality.
  • FIG. 4 is a working timing diagram of a driving method of the pixel driving circuit in FIG. 3 .
  • An exemplary embodiment of the present disclosure will be described below through the working process of the pixel driving circuit illustrated in FIG. 4 .
  • Re1 indicates the timing of the first reset signal terminal
  • Re2 indicates the timing of the second reset signal terminal
  • S1 indicates the timing of the first scanning signal terminal
  • EM indicates the timing of the light control signal terminal
  • DATA indicates the timing of the data signal terminal
  • all 7 transistors are P type transistor.
  • the working process of the pixel driving circuit may include:
  • the first stage t1 is called the reset stage.
  • the first reset signal terminal Re1 outputs a low-level signal to turn on the first reset transistor T1
  • the first initialization signal terminal INIT1 inputs an initial signal to the first node N1, and initializes the storage capacitor C to clear the original data in the storage capacitor Voltage.
  • the second reset signal terminal Re2, the first scanning signal terminal S1 and the light emitting signal control terminal EM output high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the second reset transistor T7 is disconnected, and OLED does not emit light at this stage.
  • the second stage t2 is called a data writing stage or a threshold compensation stage.
  • the first scanning signal terminal S1 outputs a low-level signal
  • the fourth transistor T4, the second transistor T2, and the second reset transistor T7 are turned on, and at the same time, the data signal terminal DATA outputs a driving signal to write a data voltage to the first node N1.
  • the second transistor T2 is turned on so that the driving transistor T3 is in a diode-connected state, and the data voltage is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 , and charge the difference between the data voltage output by the data signal terminal DATA and the threshold voltage of the drive transistor T3 into the storage capacitor C, the voltage of the second plate (second node N2) of the storage capacitor C is Vdata-
  • the second reset transistor T7 is turned on so that the second initialization voltage of the second initialization signal terminal INIT2 is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization, ensuring OLEDs don't emit light.
  • the first reset signal line Re1 outputs a high level signal to turn off the first transistor T1.
  • the light emitting control signal terminal EM outputs a high level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage t3 is called the light-emitting stage.
  • the light emitting control signal terminal EM outputs a low level signal
  • the first reset signal terminal Re1, the second reset signal terminal Re2 and the first scan signal terminal S1 output a high level signal.
  • the signal of the light emission control signal terminal EM is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the first power supply voltage output by the first power supply signal terminal VDD passes through the turned-on fifth transistor T5 and the driving transistor T3. and the sixth transistor T6 provide a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the driving transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the driving transistor T3
  • Vth is the threshold value of the driving transistor T3
  • Vdata is the data voltage output from the data signal terminal DATA
  • Vdd is the first power supply voltage output from the first power signal terminal VDD.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current.
  • the pixel driving circuit can provide the first initialization signal to the first node N1 through the first initialization signal terminal INIT1, and provide the second initialization signal to the first electrode of the light emitting device through the second initialization signal terminal INIT2.
  • the present disclosure provides a display substrate including:
  • a plurality of sub-pixels distributed in an array at least one of the sub-pixels includes a pixel driving circuit and a light-emitting device, and the plurality of sub-pixels form an array of M rows*N columns, and M and N are positive integers greater than or equal to 1;
  • the driving circuit includes a plurality of transistors, the plurality of transistors include driving transistors;
  • the light emitting device includes a first electrode;
  • the base substrate further includes: a first initialization signal line, a second initialization signal line; the first initialization signal line and the second initialization signal line extend along a first direction, and the first direction is the sub-pixel row the direction of extension;
  • the first initialization signal lines are respectively electrically connected to the sub-pixels in the m-th row, and are configured to transmit the first initialization signal to the control electrodes of the drive transistors of the sub-pixels in the m-th row;
  • the second initialization signal lines respectively electrically connected to the sub-pixels in the m-1th row, and configured to transmit a second initialization signal to the first electrode of the light-emitting device of the m-1th row of sub-pixels;
  • the projection of the first initialization signal line on the base substrate is located far away from the projection of the second initialization signal line on the base substrate
  • the second direction is the extension direction of the sub-pixel column, and m is a positive integer greater than or equal to 1 and less than or equal to M;
  • the first initialization signal is different from the second initialization signal.
  • the display substrate includes a base substrate;
  • FIG. 5 shows a specific structural diagram of the display substrate in this embodiment: in a plane parallel to the display substrate, the display substrate may include multiple Sub-pixels, at least one of the sub-pixels distributed in an array includes a pixel driving circuit, the plurality of pixel driving circuits form M pixel rows along the first direction, and the plurality of pixel driving circuits are arranged along the second direction to form N pixel columns, M , N are all positive integers greater than or equal to 1, the first direction intersects with the second direction, and further, the first direction and the second direction may be perpendicular.
  • the pixel driving circuit may include a plurality of transistors and light emitting devices, and the pixel driving circuit can adjust the driving current flowing through the driving transistors to drive the light emitting devices to emit light.
  • the display substrate further includes a first initialization signal line 31 and a second initialization signal line 32 , the first initialization signal line 31 and the second initialization signal line 32 are signal lines extending along the first direction of the main body;
  • a extending along the B direction means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the B direction, and the main part extends along the The length extending in the B direction is greater than the length extending in the other directions of the secondary portion.
  • the first initialization signal line 31 can provide the first initialization signal Vinit1 to the first initialization signal terminal INIT1 in the pixel driving circuit
  • the second initialization signal line 32 can provide the second initialization signal Vinit1 to the second initialization signal terminal INIT2 in the pixel driving circuit. Vinit2.
  • the first initialization signal lines 31 are respectively electrically connected to the sub-pixels of the m-th row, and the first initialization signal lines 31 are configured as the first initialization signal Vinit1 to be transmitted thereon.
  • the second initialization signal line 32 is electrically connected to each sub-pixel in the m-1th row, and the second initialization signal line 32 is It is configured to transmit the second initialization signal Vinit2 transmitted thereon to the first electrode of the light emitting device of the m-1th row of sub-pixels, for example, the first electrode may be an anode, so as to complete the reset of the anode of the light emitting device.
  • the projection of the first initialization signal Vinit1 on the base substrate is located on a side away from the projection of the second initialization signal line Vinit2 on the base substrate away from the pixels in the m-1th row.
  • m is a positive integer greater than or equal to 1 and less than or equal to M.
  • the pixel driving circuit may provide different initialization signals to the first node N1 and the first electrode of the light emitting device according to actual requirements.
  • the effective level voltage of the first initialization signal can be set to -3V
  • the effective level voltage of the second initialization signal can be set to -4V, which can ensure that the display screen has low brightness in the black state and improve the picture display effect.
  • the first initialization signal line 31 and the second initialization signal line 32 are located between the driving transistors of two adjacent rows of sub-pixels, and are located in the second direction between the driving transistors of any row of them. same side. As shown in FIG.
  • the first initialization signal line 31 and the second initialization signal line 32 are located between the pixel driving transistor in the mth row and the driving transistor of the m-1th row of pixels, and are located in the mth row.
  • the same side of the transistor is also located on the same side of the driving transistor in the m-1th row.
  • the width of the first initialization signal line 31 in the second direction is different from the width of the second initialization signal line 32 in the second direction.
  • the "in The "width in two directions” refers to the width in the second direction of the main part of the two signal lines extending along the first direction.
  • the second direction is also the extending direction of the pixel columns.
  • the square resistance value of the signal line has a negative correlation with its width, that is, the larger the line width, the smaller the square resistance. Setting the line width of one of the two signal lines to be wider can effectively reduce the overall resistance of the two signal lines.
  • the width of the second initialization signal line 32 in the second direction may be greater than the width of the first initialization signal line in the second direction.
  • the width of the second initialization signal line 32 is 1.3-2.4 times the width of the first initialization signal line 31 .
  • the display substrate further includes: a reset signal line 21 extending along the first direction, and the plurality of transistors include a first reset transistor T1 and a second reset transistor T7 .
  • the reset signal line 21 is used to provide the first reset signal to the first reset signal terminal Re1 of the sub-pixel driving circuit in the m-th row
  • the reset signal line 21 is used to provide the first reset signal to the sub-pixels in the m-1th row.
  • the second reset signal terminal Re2 of the pixel driving circuit provides a second reset signal.
  • the first reset signal Re1 of the mth row and the second reset signal Re2 of the m ⁇ 1th row are the same signal.
  • the first reset transistor T1 of the pixel circuit in the mth row is turned on, and the first initialization signal Vinit1 can be written through the first reset transistor T1.
  • the second reset transistor T7 is turned on when the second reset signal is low, and the second initialization signal Vinit2 can be written into the m-th row via the second reset transistor T7
  • the reset signal line 21 , the first initialization signal line 31 , and the second initialization signal line 32 are arranged in sequence along the direction away from the mth row of sub-pixel driving transistors.
  • the display substrate in a plane perpendicular to the display substrate, may include a semiconductor layer 1 , a first conductive layer 2 , a second conductive layer sequentially disposed on the base substrate.
  • the semiconductor layer 1 includes the active layer of a plurality of transistors, and the active layer includes the channel region and the source and drain regions of the transistor;
  • the first conductive layer 2 includes the reset signal line 21 and the control electrode of the transistor,
  • the second conductive layer 3 includes the first initialization signal line 31, the second initialization signal line 32;
  • the third conductive layer 4 includes the first power line 42, the first pole and the second pole of the transistor, the second
  • the four conductive layers 5 include second power lines 52 and data signal lines 51 .
  • the display substrate further includes a third initialization signal line 41 extending along the second direction, which is arranged in a different layer from the first initialization signal line 31 .
  • the semiconductor layer, the first metal layer, the second metal layer, and the fourth metal layer in the embodiment shown in FIG. 11 can be set with reference to FIGS. 6 a , 7 , 8 , and 10 , and details are not repeated here.
  • “A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the third initialization signal line 41 is electrically connected to one of the first initialization signal line 31 and the second initialization signal line 32 .
  • the third initialization signal line 41 may be located in the third conductive layer 4; in another possible implementation manner, please refer to FIG. 11, the third initialization signal line 41 may be connected to the first The initialization signal line 31 is electrically connected.
  • the third initialization signal line 41 in different layers with the first initialization signal line 31 and the second initialization signal line 32, and electrically connecting it to one of the two, can make the initialization signal Vinit1 or Vinit2 in different directions on different layers.
  • the transmission is helpful to reduce the transmission voltage drop of the initialization signal and improve the uniformity of the display screen.
  • the third initialization signal line 41 may be connected to the first initialization signal line 31 through a via hole.
  • the third initialization signal line 41 is connected to the first initialization signal line 31 through a via hole to form a mesh distribution structure, as shown in FIG. 13 , using a mesh distribution structure can significantly reduce The voltage drop transmitted by the first initialization signal Vinit1 can significantly improve the uniformity of the picture.
  • At least one column of sub-pixels is arranged between two adjacent third initialization signals 41 . That is, for sub-pixels with a total of M rows and N columns, the third initialization signal line 41 is only arranged in odd columns, such as the first column, the third column, the fifth column, . . . , and so on. Certainly, the third initialization signal line 41 may also be provided only in the even columns, such as the second column, the fourth column, the sixth column, . . . , and so on. Arranging the third initialization signal lines 41 at intervals helps to increase the distance between two adjacent signal lines, reduce parasitic capacitance, and improve display image quality.
  • At least two first power supply lines 42 are disposed between two adjacent initialization signal lines 41 .
  • two first power supply lines 42 with a constant voltage may be arranged between two adjacent third initialization signal lines 41 , and the first power supply lines 42 provide the first power supply voltage Vdd for the first power signal terminal VDD of the pixel driving circuit.
  • Such an arrangement is conducive to maximizing the utilization of the space of the substrate, realizing the dense arrangement of pixels, and at the same time, preventing crosstalk between adjacent third initialization signal lines 41 and improving the display image quality.
  • the shapes of two adjacent third initialization signal lines may be the same or different.
  • the “same shape of A and B” mentioned in the present disclosure means that the shapes of A and B are substantially the same within a reasonable error range or process deviation.
  • the multiple transistors include a first reset transistor T1, a second transistor T2, a drive transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a second reset transistor T7.
  • the semiconductor layer 1 includes: the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the second reset transistor.
  • the active layer of each transistor includes a source-drain region and a channel region, the source-drain region of each transistor includes a first region and a second region, and the channel region of each transistor is located between the first region and the second region of the transistor between.
  • the first active layer 11 includes the channel region 111, the first region 112 and the second region 113 of the first transistor T1
  • the first active layer 12 includes the channel of the second transistor T2.
  • Region 121, first region 122 and second region 123, the third active layer 13 includes the channel region 131, the first region 132 and the second region 133 of the drive transistor T3, the fourth active layer 14 includes the fourth transistor T4
  • the channel region 141, the first region 142 and the second region 143 of the fifth active layer 15 include the channel region 151, the first region 152 and the second region 153 of the fifth transistor T5, and the sixth active layer 16 includes The channel region 161, the first region 162 and the second region 163 of the sixth transistor T6, and the seventh active layer 17 includes the channel region 171, the first region 172 and the second region 173 of the seventh transistor T7.
  • the first region 112 of the first active layer 11 is set independently, the second region 113 of the first active layer 11 serves as the first region 122 of the second active layer 12 at the same time, and the first region 122 of the third active layer 13
  • the area 132 serves as the second area 143 of the fourth active layer 14 and the second area 153 of the fifth active layer 15 at the same time, and the second area 133 of the third active layer 13 serves as the second area of the second active layer 12 at the same time.
  • the region 123 and the first region 162 of the sixth active layer 16 and the second region 163 of the sixth active layer 16 serve as the first region 172 of the seventh active layer 17 at the same time.
  • the first region 142 of the fourth active layer 14, the first region 152 of the fifth active layer 15, and the second region 173 of the seventh active layer are separately disposed.
  • the first active layer 11, the second active layer 12, and the fourth active layer 14 in the m-1th row of pixels are located on the side of the third active layer 13 of the pixel driving circuit away from the mth row of pixels.
  • the first active layer 11 is located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13, the fifth active layer 15 and the sixth active layer in the m-1th pixel row
  • the active layer and the seventh active layer 17 are located on the side of the third active layer 13 close to the m-th pixel row.
  • the first active layer 11 can be in the shape of "n”, which is a double gate structure including two channel regions; the second active layer 12 can be in the shape of "7”, which is a double gate structure including two The double-gate structure in the area; the third active layer 13 can be in the shape of "J" or "I", and the shape of each active layer can be selected according to the process requirements, which is not limited in the present disclosure.
  • the first conductive layer 2 includes a reset signal line 21, a first scan signal line 22, a light emitting signal control line 23 and a first plate 24 of a storage capacitor C.
  • the first conductive layer 2 can be called the first Gate metal layer (Gate1 layer).
  • the reset signal line 21 that provides the first reset signal and the first scan signal line 22 that provides the first scan signal for the pixel driving circuit in the m-1th row are located on the first plate 24 of the pixel row away from the sub-pixel in the m-th row.
  • the first scanning signal line 22 is located on the side away from the first plate 24 of the reset signal line 21 that provides the first reset signal to the pixel row, and the light emission control signal line 23 can be located on the first plate 24 of the pixel row The side near the mth row of pixels.
  • FIG. 14 is a schematic diagram of the stacked structure of the semiconductor layer 1 and the first conductive layer 2.
  • the area on the first conductive layer 2 that overlaps with the projection of the semiconductor layer 1 on the substrate can be used as the control electrode of each transistor, specifically: reset Part of the structure of the signal line 21 can be used to form the control electrode (gate) of the first reset transistor T1 and the control electrode (gate) of the second reset transistor T7.
  • reset signal that provides the first reset signal to the pixels in the mth row Line 21
  • a part of its structure can constitute the control electrode of the first reset transistor T1 in the current row of pixels and the control electrode of the second reset transistor T7 in the m-1th row.
  • the partial structure of the first scanning signal line 22 can be used to form the control electrode (gate) of the second transistor T2 and the fourth transistor T4.
  • the first scanning signal line 22 includes a first protruding portion 221, and the first protruding portion 221 including the gate of the second transistor T2.
  • the light emission control signal line 23 can provide the light emission control signal for the light emission control signal terminal EM of the pixel circuit, and part of the structure of the light emission control signal line 23 can be used to form the control electrodes (gates) of the fifth transistor T5 and the sixth transistor T6.
  • the first plate 24 can serve as the control electrode (gate) of the driving transistor T3 at the same time.
  • the first plate 24 may be in the shape of a rounded rectangle, and its projection on the base substrate and the projection of the driving transistor T3 on the base substrate have an overlapping area.
  • the preparation process of the base substrate may include: depositing a layer of semiconductor layer 1 on the base substrate, and patterning the semiconductor layer 1 to form the active layer of each transistor; depositing a semiconductor layer 1 on the semiconductor layer 1 An insulating layer thin film, and then deposit the first conductive layer 2 on the insulating layer thin film, pattern the first conductive layer 2 to form reset signal line 21, first scanning signal line 22, light emission control signal line EM, first pole plate 24.
  • the second conductive layer 3 includes: a first initialization signal line 31, a second initialization signal line 32, a shielding portion 33, a first conductive portion 34, a second plate including a storage capacitor C, a first conductive The portion 34 is provided with a first through hole 341 .
  • the projection of the second initialization signal line 32 on the substrate overlaps with the projection of at least part of the source and drain regions of the first transistor T1 on the substrate.
  • the second initialization signal line 32 blocks the conductorized part between the two double gates of the first transistor T1, so as to prevent the conductorized part between the double gates from being driven by the pixel The influence of other parts of the circuit to improve the display effect.
  • the third conductive layer 4 may include: a third initialization signal line 41, a first power line 42, a first connection part 43, a second connection part 44, a third connection part 45, a fourth The connection portion 46 and the fifth connection portion 47 ;
  • the third initialization signal line 41 includes a first extension portion 411 , a second extension portion 412 , and a third extension portion 413 sequentially connected along the second direction.
  • the first extension portion 411 extends along the second direction, and is electrically connected to the first initialization signal line 31 through a via hole.
  • the extension direction of the third extension part 413 is different from the extension direction of the first extension part 411 , and the second extension part 412 is used to connect the first extension part 411 and the third extension part 413 .
  • the extending direction of the second extending portion 412 deviates from the second direction.
  • the first extension 411 extends along the second direction, and the second extension 412 is connected to the first extension 411 with an included angle ⁇ 1, and 90° ⁇ ⁇ 1 ⁇ 180°, for example, it can be 130° to 135°; the third extension 413 is connected to the second extension 412 with an included angle ⁇ 2, and 90° ⁇ 2 ⁇ 180°, for example, it can be 125° to 135°
  • the third initialization signal line may further include a fourth extension 414, a fifth extension 415 and a sixth extension 416; wherein, the fourth extension 414 It is connected with the third extension part 413, and the connection position can be a chamfered or rounded corner structure.
  • the fourth extension part 414 extends along the first direction; the fifth extension part 415 is connected with the fourth extension part 414, with an included angle ⁇ 3, and 90 ° ⁇ 3 ⁇ 180°, for example, may be 125° to 135°.
  • the sixth extension 416 is connected to the fifth extension 415, the sixth extension 416 extends along the second direction, the fifth extension 415 and the sixth extension 416 have an included angle ⁇ 4, and 90° ⁇ 4 ⁇ 180°, for example It can be 125° to 135°.
  • each extension refers to the angle between the line segments where each extension is located.
  • the edges of each extension may not be as shown in Figure 12a and those shown in Fig. 12b are all regular straight lines, but can be presented as wavy shapes, curved edge shapes or other irregular edge shapes allowed within the range of process errors, so it can also be understood that the above included angles can actually be There is a certain degree of deviation (eg ⁇ 10°).
  • the projection of the first extension 413 on the base substrate and the projections of the reset signal line 21 , the first initialization signal line 31 , and the second initialization signal line 32 on the base substrate all have overlapping areas.
  • An extension 413 is also electrically connected to the first region of the first transistor T1 through a via hole, that is, the first extension 413 can transmit the first initialization signal Vinit1 by being connected to the first initialization signal line 31 for forming a network structure, reducing the transmission voltage drop, and at the same time, the first extension part 413 can transmit the first initialization signal Vinit1 to the first region of the first transistor T1, and then perform the first plate 24 of the storage capacitor C and the control electrode of the drive transistor reset.
  • the projection of the second extension portion 412 on the base substrate, the projection of the first protruding portion 221 on the base substrate and the projection of the shielding portion 33 on the base substrate all overlap.
  • the second extension 412 and the first extension 411 form an included angle ⁇ 1, and reasonably setting the included angle between the second extension 412 and the first extension 411 can avoid the pixel circuit, under the premise of reasonably occupying the space of the substrate , to minimize parasitic capacitance.
  • the projection of the third extension portion 413 on the base substrate is located on the side where the projection of the driving transistor T3 on the base substrate is away from the projection of the first power line 42 on the base substrate.
  • the second connection part 44 is connected to the second initialization signal line 32 through a via hole, and is connected to the first region of the second reset transistor T7, so as to transmit the second initialization number Vinit2 to the light emitting device reset the first electrode; the first end of the third connection part 45 is connected to the control electrode of the driving transistor T3 through a via hole, and the second end is connected to the first region of the second transistor T2 through a via hole.
  • the first power cord 42 may include: a plurality of seventh extensions 421, the seventh extensions 421 may include parts bent along the first direction, the width of the seventh extensions 421 in the first direction It is larger than the width of other positions of the first power line 42 in the first direction.
  • the seventh extension part 421 is electrically connected with the first region of the fifth transistor T5 and the first conductive part 43, so as to transmit the Vdd signal to the first conductive part 421, and provide the first plate for the second plate of the storage capacitor and the driving transistor.
  • the first conductive part 43 can be connected horizontally in the first direction through the seventh extension part 421 to reduce the voltage drop of the first power supply voltage transmission and improve the display effect.
  • the fourth conductive layer 5 includes a data signal line 51, a second power line 52, a sixth connection portion 54, a seventh connection portion 55, an eighth connection portion 56 and a flat portion 53, wherein the flat portion 53 It also includes a first color flat portion 531 , a second color flat portion 532 and a third color flat portion 533 .
  • the data signal line 51 is used to transmit the data voltage signal Vdata to the data signal terminal DATA of the pixel driving circuit.
  • the data signal line 51 is connected to the first connection portion 43 through the sixth connection portion 54, and the first connection portion 43 is connected to the fourth transistor T4.
  • the first zone 142 is connected.
  • the shielding portion 33 is connected to the first power line 42 through a via hole, and its projection on the base substrate covers the source and drain regions of the second transistor T2, Moreover, the projection of the shielding portion 33 on the base substrate and the projection of the data signal line 51 on the base substrate do not overlap. That is: the shielding portion 33 shields the conductorized region of the second transistor T2. Furthermore, when the second transistor T2 has a double-gate structure, the projection of the shielding portion 33 on the base substrate covers the gap between the double gates of the second transistor T2. The projection of the conductorized part on the substrate substrate.
  • the shielding part 33 has a Vdd voltage, it is beneficial to prevent the conductorization Partial floating connection (Floating) plays a certain role in stabilizing the voltage and improves the picture quality; while at the same time, the projection of the shielding part 33 on the base substrate and the projection of the data signal line 51 on the base substrate do not overlap, reducing The parasitic capacitance between the data signal line 51 and the shielding part 33, meanwhile, the shielding part 33 acts as a voltage regulator, which can prevent the influence of pixel data voltage changes in adjacent columns on the sub-pixels, and improve the picture quality.
  • Floating conductorization Partial floating connection
  • the second power line 52 is electrically connected to the first power line 42 via the eighth connection portion 56 and the seventh extension portion 421 , specifically, through a via hole. That is, the parallel connection of the second power line 52 and the first power line 51 can significantly reduce the voltage drop of the Vdd signal during transmission and improve the display effect.
  • the projection of the second power line 52 and the first power line 42 on the base substrate at least partially overlaps, further, the width of the second power line 52 in the first direction is smaller than that of the seventh extending The width of the portion 421 in the first direction.
  • the seventh connection part 55 is connected to the fourth connection part 46 and the fifth connection part 47 through via holes, the fourth connection part 46 and the fifth connection part 47 are connected to the second region of the sixth transistor T6 through via holes, and the fourth connection part
  • the shapes of the connecting portion 46 and the fifth connecting portion 47 may be different. For example, as shown in FIG. 12 , the length of the fifth connecting portion 47 in the second direction is greater than that of the fourth connecting portion 46.
  • the fourth connecting portion 46 and the first initialization signal line 41 are disposed in the same pixel column. Certainly, the shapes of the fourth connecting portion 46 and the fifth connecting portion 47 may also be the same.
  • the fourth conductive layer also includes a flat portion 53, the flat portion 53 is connected to the second power line 52, that is, the potential of the flat portion 53 is a Vdd signal, and the flat portion 53 is connected to the second power line 52, so that the second power line 52 can be connected.
  • the resistance of the second power line is reduced, reducing the voltage drop of the second power signal line 52 from the first end to the second end, reducing signal transmission loss, and improving display effect.
  • the projection of the flat portion 53 on the base substrate at least partially overlaps with the projection of the first electrode of the light emitting device on the base substrate
  • the first electrode may be an anode
  • flat The part 53 can be used to improve the flatness of the first electrode, improve the color shift, and enhance the display effect.
  • the projection of the first electrode of the light-emitting device on the base substrate completely covers the projection of the flat portion 53 on the base substrate.
  • the projection of A completely covers B It means that the contour of the projection of B in a certain plane is completely inside the contour of the projection of A in the same plane.
  • the shapes of the flat parts 53 of the sub-pixels that emit light of different colors may be different, for example, may include a first color flat part 531, a second color flat part 532 and a second color flat part 532. Three-color flat portion 533 .
  • the shape of the flat portion 53 may also be the same.
  • the area of the flat portion 531 of the first color is greater than the area of the flat portion 532 of the second color and the area of the flat portion 533 of the third color.
  • the multiple sub-pixels include a first color sub-pixel P1 , a second color sub-pixel P2 , and a third color sub-pixel P3 that emit light of different colors.
  • the first color sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the pixel driving circuit of the sub-pixel P1 is electrically connected to the first electrode of the light emitting device that emits red light
  • the second color sub-pixel P2 may be a red light emitting
  • the pixel drive circuit of the sub-pixel P2 is electrically connected to the first electrode of the light-emitting device that emits blue light
  • the third sub-pixel P3 can be a green sub-pixel that emits green light ( G)
  • the pixel driving circuit of the sub-pixel P3 is electrically connected to the first electrode of the light-emitting device that emits green light.
  • the plurality of sub-pixels P include the red sub-pixel R that emits red light, the blue sub-pixel G that emits blue light, and the green sub-pixel B that emit green light are arranged in multiple pixel rows and a plurality of pixel columns, the plurality of pixel columns include red and blue pixel columns RB and green pixel columns GG; the red and blue pixel columns RB include red sub-pixels R and blue sub-pixels B alternately arranged along the second direction; the green pixels
  • the column GG includes green sub-pixels G sequentially arranged along the second direction.
  • the third initialization signal line 41 is only provided in the red and blue pixel columns RB. In another possible implementation manner, the third initialization signal line 41 is only provided in the green sub-pixel column GG. In another possible implementation manner, the third initialization signal line 41 may be provided in the red and blue pixel columns RB and the green pixel column GG at the same time.
  • the shape of the third initialization signal line 31 located in the nth column of red and blue pixel columns RB may be the same as the shape of the third initialization signal line 31 located in the n+1th column, where n is greater than or equal to 1 and a positive integer less than or equal to N.
  • the display substrate further includes a fifth conductive layer 6 , and as shown in FIG. 16 , the fifth conductive layer 6 includes a first electrode 61 of each sub-pixel. Specifically, a first electrode 611 , a second electrode 612 and a third electrode 613 are respectively provided in the sub-pixels of the first color, the sub-pixels of the second color and the sub-pixels of the third color.
  • the display substrate further includes a first insulating layer 7, the third conductive layer 5 is located on the side of the first insulating layer 7 facing the base substrate, the first insulating layer 7 includes a first via hole 711, the first The via hole 711 exposes the first connection part 46 and the first connection part 47 .
  • the first electrode 61 includes a main body portion 61a and an auxiliary portion 61b.
  • the auxiliary part 61b is electrically connected to the third conductive layer 4 through the first via hole 711 .
  • the main part 61a and the auxiliary part 61b in the same sub-pixel have an integrated structure and can be formed simultaneously by one patterning process.
  • the display substrate further includes a pixel definition layer 8 , a light-emitting layer 91 located on the side of the fifth conductive layer 6 away from the base substrate, and a cathode 92 located on the side of the light-emitting layer 91 away from the fifth conductive layer 6 .
  • the pixel definition layer has an opening 81, which exposes at least a partial area of the main body of the first electrode, the light-emitting layer 81 is located in the opening 81 and contacts the area of the main body exposed by the opening, and the area where the light-emitting layer is located in the opening can be It is used to emit light, so that the effective light emitting area EA can be defined by the opening.
  • the partial area where the opening of the pixel definition layer 8 overlaps the main body portion 61 a of the first electrode 61 is the effective light emitting area EA of each sub-pixel.
  • the overlapping area between the opening of the pixel definition layer 8 in the second color sub-pixel P2 and the main body of the first electrode 612 is the second color sub-pixel P2.
  • the overlapping area of the opening of the pixel definition layer 8 in the sub-pixel P1 of the first color and the main part 611a of the first electrode 611 is the effective light-emitting area EA1 of the sub-pixel P1 of the first color
  • the area of the sub-pixel P3 of the third color is the effective light emitting area EA3 of the sub-pixel P3 of the third color.
  • the flat portion 53 is located on a side of the first electrode 61 close to the base substrate.
  • the shape of the first color flat portion 531 is substantially the same as the shape of the main body portion 611a of the first electrode 611 of the first color sub-pixel, and the shape of the second color flat portion 532 is similar to that of the second color sub-pixel.
  • the shape of the main body portion 612a of the first electrode 612 is basically the same, and the shape of the third color flat portion 533 is basically the same shape as the shape of the main body portion 613a of the first electrode 613 of the third color sub-pixel.
  • the shapes of A and B are substantially the same. means that the outlines of A and B have the same shape, and the difference between the areas of A and B does not exceed ⁇ 1%.
  • each flat part corresponds to the shape of each first electrode above it, which helps to make each part of each first electrode uniform and flat, eliminating asymmetry, thereby improving or even eliminating color shift.
  • the areas of the main body parts of the first electrodes of different color sub-pixels may be different.
  • the area of the main body part 611a of the first electrode of the first color sub-pixel may be larger than that of the first electrode of the second color sub-pixel.
  • the area of the main part 612a of the sub-pixel 613a of the third color can also be the same, or can be set according to the required size, which is not limited in the present disclosure.
  • the shape of the main body portion 61 a of the first electrode 61 may be octagonal, and correspondingly, the shape of each flat portion 53 may also be approximately octagonal.
  • the first color flat part 531 includes a first recessed part 5311, and the first recessed part 5311 is used to avoid the via hole electrically connected with the eighth connecting part 56 and the seventh extension part 421;
  • the third color flat part 533 includes a second recess part 5331, the second recessed part 5331 is used to avoid the via hole for electrical connection between the seventh connecting part 55 and the fifth connecting part 47;
  • the shape of the main body part 61a can be hexagonal, rectangular or other shape, which is not limited in the present disclosure.
  • the projection of the flat portion 53 of each sub-pixel on the base substrate at least partially overlaps the projection of the first electrode 61 of the corresponding sub-pixel on the base substrate, specifically, the first color
  • the projection of the flat portion 531 on the base substrate at least partially overlaps the projection of the first electrode 611 of the first color sub-pixel on the base substrate, and the projection of the second color flat portion 532 on the base substrate overlaps with the projection of the second color sub-pixel on the base substrate.
  • the projection of the first electrode 612 of the sub-pixel on the base substrate at least partially overlaps, and the projection of the third-color flat part 533 on the base substrate and the projection of the first electrode 613 of the third-color sub-pixel on the base substrate overlap at least partially. That is, the first electrode of each sub-pixel of different colors has a flat portion on the side close to the base substrate, which can make the first electrode of each sub-pixel flat, reduce color shift, and improve the uniformity of the display screen.
  • the projection of the first electrode 611 of the first color sub-pixel on the base substrate completely covers the projection of the first color flat portion 531 on the base substrate, and the second color sub-pixel
  • the projection of the first electrode 612 of the first electrode 612 on the base substrate completely covers the projection of the second color flat portion 532 on the base substrate, and the projection of the first electrode 613 of the third color sub-pixel on the base substrate completely covers the third color subpixel Projection of the flat portion 533 on the base substrate.
  • the signal lines made of the third conductive layer 4 and the fourth conductive layer 5 located on the side of the first electrode close to the display substrate, such as the first power line 42 and the second power line 52, in the direction perpendicular to the base substrate If the thickness is large, the insulating layer above the signal line cannot be completely planarized, resulting in uneven light-emitting layer above the flat layer, and asymmetric protrusions appear on the first electrode 61 and the light-emitting layer above the first electrode 61, which leads to When viewed from the left and right sides of the normal line of the display substrate at the same angle as the display substrate, color shift occurs.
  • the flat part is provided under the first electrodes of different sub-pixels, and the flat part is completely located inside the projection of the first electrodes, so that the corresponding positions of the first electrodes of each sub-pixel can be flattened, and the color shift can be further improved.
  • the projection of the flat portion 53 on the base substrate and the projection of the first power line 41 on the base substrate have an overlapping portion, specifically Specifically, in the embodiment shown in the present disclosure, the projection of the flat portion 53 on the base substrate at least partially overlaps with the seventh extension portion 421 of the first power line 42 .
  • Such setting helps to reduce the voltage drop of the first power supply voltage transmitted on the signal line and improve the uniformity of the display image.
  • the first color sub-pixel may be a red sub-pixel R that emits red light
  • the second color sub-pixel may be a blue sub-pixel G that emits blue light.
  • the first color flat portion 531 and the second color flat portion 532 at least partially overlap with the seventh extending portion 421 .
  • the first color sub-pixel may be a red sub-pixel R that emits red light
  • the second color sub-pixel may be a blue sub-pixel B that emits blue light.
  • the projections of the first color flat portion 531 and the second color flat portion 532 on the base substrate and the projection of the control electrode 24 of the drive transistor T3 on the base substrate at least partially overlap, so that the potential of the first node N1 Stablize.
  • the third color sub-pixel may be a green sub-pixel G that emits green light
  • the conductive part between the double gates of T1 can reduce the leakage current.
  • the first reset transistor T1 may also be an oxide transistor (IGZO). At this time, the third color flat part 533 blocks the oxide transistor T1, which can further avoid the influence of light on the performance of the transistor.
  • the sub-pixels of the first color, the sub-pixels of the second color, and the sub-pixels of the third color respectively emit red light, blue light and green light.
  • a plurality of red sub-pixels R and blue sub-pixels B are arranged alternately along the second direction to form RB pixel columns, and a plurality of green sub-pixels G are alternately arranged along the second direction to form green pixel columns GG, red and blue pixel columns RB and green pixel columns GG are alternately arranged along the first direction, wherein the projection of the auxiliary part 611b of the first electrode of the red subpixel R on the base substrate is the same as the projection of the source and drain regions of the second transistor T2 of the adjacent green subpixel G on the base substrate The projections are at least partially overlapped.
  • the overlapping position is located in the conductorized region between the double gates, so as to reduce the leakage of the second transistor T2 and improve the uniformity of the display screen.
  • the projection of the auxiliary part of the first electrode of the blue sub-pixel G on the base substrate at least partially overlaps the projection of the source-drain region of the second transistor T2 of the adjacent green sub-pixel G on the base substrate, The principles and technical effects are the same, and will not be repeated here.
  • the display substrate may further include: a light shielding layer (not shown in the figure).
  • the light-shielding layer can be located between the base substrate and the semiconductor layer 1, and the projection of the light-shielding layer on the base substrate at least covers the projection of the active region of one of the transistors on the base substrate.
  • the light-shielding layer on the substrate The projection on the base substrate can cover the projection of the channel region of the driving transistor T3 on the base substrate, which is used to block external light and shield external interference, avoid affecting the performance of the active layer of each transistor, and improve the display effect.
  • the light shielding layer may be a semiconductor material (a-Si) or a metal material (Mo).
  • the light-shielding layer can be electrically connected to a constant potential, so as to prevent the light-shielding layer from being in a floating state, and play a better anti-interference effect on the channel region of the active layer.
  • the light shielding layer may be electrically connected to the first power supply line 41 , and may also be electrically connected to the first initialization signal line 31 or the second initialization signal line 32 .
  • the light-shielding layer may only include the first connection structure extending along the first direction, or may only include the second connection structure extending along the second direction, or may also include The first connecting structure and the second connecting structure extending along the second direction.
  • the first connection structure and the second connection structure can each be connected to the structure to which it is electrically connected in a mesh form, so as to significantly reduce loading.
  • the first connection structure may be electrically connected to the first power line 41 and form a mesh structure.
  • the first connection structure may be electrically connected to the third initialization signal line 41 and form a mesh structure.
  • the second connection structure may be electrically connected to the first initialization signal line 31 or the second initialization signal 32 and form a mesh structure.
  • the second connection structure can be connected in parallel with the third initialization signal line 41 , and the second connection structure can be located only in the red and blue pixel columns, or only in the green and green pixel columns, or in both the red and blue pixel columns and the green and green pixel columns.
  • the first connection structure and the second connection structure may be connected in a mesh shape, that is, the light-shielding layer itself may be in a mesh shape.
  • the display substrate includes a display area AA and a peripheral area NA located outside the display area.
  • the peripheral area NA may include a left frame area NA-L, a right frame area NA-R, and an upper frame area NA-U. and the lower frame area NA-D; in a possible implementation manner, the first initialization signal line bus 31' extending along the second direction and the first initialization signal line bus 31' extending along the second direction are respectively provided in the left frame area NA-L and the right frame area NA-R.
  • Two initialization signal line buses 32', a plurality of first initialization signal lines 31 are electrically connected to the first initialization signal line bus 31', a plurality of second initialization signal lines 32 are electrically connected to the second initialization signal line bus 32', and at the same time
  • the upper frame area NA-U and/or the lower frame area NA-D may be provided with a bus 41 ′ of third initialization signal lines extending along the first direction, and electrically connected to a plurality of third initialization signal lines 41 .
  • Each initialization signal line bus provides initialization signals for corresponding initialization signal lines.
  • the left frame area NA-L and the right frame area NA-R are each provided with a first initialization signal line bus 31' extending along the second direction and a second initialization signal line bus 31' extending along the second direction.
  • a signal line bus 32', a plurality of first initialization signal lines 31 are electrically connected to the first initialization signal line bus 31', and a plurality of second initialization signal lines 32 are electrically connected to the second initialization signal line bus 32';
  • a bus 41' of a third initialization signal line extending along the first direction may be provided in the upper frame area NA-U and/or the lower frame area NA-D. , is electrically connected to a plurality of third initialization signal lines 41, and provides corresponding initialization signals for the third initialization signal lines.
  • the first initialization signal line bus 31', the second initialization signal line bus 32', and the third initialization signal line bus 41' may be located in the same film layer, for example, they may be located in the third conductive layer 4 or in the same film layer.
  • the present disclosure also provides a display device, which includes: the above-mentioned display panel.
  • the display device may be a display device such as a mobile phone or a tablet computer.
  • the present disclosure also provides a method for manufacturing a display substrate, which at least includes the following steps:
  • S1 Deposit a semiconductor layer 1 on the base substrate, and pattern the semiconductor layer 1 to form active layers of each transistor; the first active layer 11 to the seventh active layer 17 are interconnected and integral structures.
  • the first metal layer may also be called a gate metal layer (Gate1 layer).
  • S3 Perform conductorization treatment on the semiconductor layer 1, such as ion implantation, etc., and form the first reset transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, and the fifth transistor T5 in the area covered by the first conductive layer 2 , the channel regions of the sixth transistor T6 and the second reset transistor T7 , the unshielded semiconductor layer 1 is conductorized, that is, the source and drain regions of the seven transistors T1 - T7 are all conductorized.
  • S4 Deposit a third insulating layer 73 on the first conductive layer 2, deposit a second conductive layer 3 on the insulating layer and perform patterning, the second conductive layer 3 includes the first initialization signal line 31, and the second initialization signal line 32, the shielding portion 33, the first conductive portion 34, and the second conductive layer may also become a second gate metal layer (Gate2 layer).
  • Gate2 layer second gate metal layer
  • S5 Deposit a third insulating layer 74 on the second conductive layer 3, deposit and pattern the third conductive layer 4 on the third insulating layer, the third conductive layer includes at least the third initialization signal line 41, the first power supply The wire 42 , the first connection part 43 , the second connection part 44 , the third connection part 45 , the fourth connection part 46 and the fifth connection part 47 .
  • S6 Deposit the first insulating layer 71 on the third conductive layer 4, deposit and pattern the fourth conductive layer 5 on the first insulating layer 71, the fourth conductive layer 5 includes at least the data signal line 51, the second power line 52, the flat part 53.
  • S7 Deposit a fourth insulating layer 75 on the fourth conductive layer 5, deposit and pattern the fifth conductive layer 6 on the fourth insulating layer 75, to form a first electrode pattern of the sub-pixel.
  • the subsequent preparation process may include: forming an organic light-emitting layer by using an inkjet printing or evaporation process, the organic light-emitting layer is connected to the first electrode through the opening of the pixel definition layer, a second electrode is formed on the organic light-emitting layer, the second electrode is connected to the organic light-emitting layer connect.
  • Forming an encapsulation layer the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent external water vapor from invading the light-emitting structure.
  • the substrate substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, poly One or more of styrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo )
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), Can be single layer, multilayer or composite layer.
  • the first insulating layer is called the buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), Materials such as hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the first insulating layer and the fourth insulating layer can be made of organic materials, such as resin.
  • the fifth conductive layer can adopt a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO/Ag/ITO and the like.
  • the pixel definition layer can be polyimide, acrylic or polyethylene terephthalate.
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy.

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Abstract

一种显示基板及显示装置。显示基板包括多个阵列分布的子像素，多个子像素的像素驱动电路形成M个像素行和N个像素列；显示基板还包括沿第一方向延伸的第一初始化信号线和第二初始化信号线；像素驱动电路包括多个晶体管和发光器件，所述多个晶体管包括驱动晶体管；所述发光器件包括第一电极；其中，第一初始化信号线分别与所述第m行子像素电连接，被配置为将第一初始化信号传输至所述第m行像素驱动晶体管的所述控制极；第二初始化信号线分别与所述第m-1行子像素电连接，被配置为将第二初始化信号传输至所述第m-1行子像素的所述发光器件的第一电极,m为大于等于1且小于等于M的正整数；第一初始化信号与第二初始化信号不同。

Description

显示基板及显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode,OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes,QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲等优点。随着显示技术不断发展，以OLED或QLED作为发光器件，采用薄膜晶体管(Thin Film Transistor,TFT)进行信号控制的柔性显示装置已经成为当前显示领域的主流产品，对于画质的日益增高的需求也对当前OLED和QLED技术的发展提出了新的挑战。
发明内容
在一个方面，本公开实施例提供一种显示基板，包括：
衬底基板；
多个阵列分布的子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述多个子像素形成M行*N列的阵列，M和N为大于等于1的正整数；所述像素驱动电路包括多个晶体管，所述多个晶体管包括驱动晶体管；所述发光器件包括第一电极；
所述衬底基板还包括：第一初始化信号线，第二初始化信号线；所述第一初始化信号线和第二初始化信号线沿第一方向延伸，所述第一方向为所述子像素行的延伸方向；
其中，所述第一初始化信号线分别与第m行子像素电连接，被配置为将第一初始化信号传输至所述第m行子像素的驱动晶体管的控制极；所述第二初始化信号线分别与第m-1行子像素电连接，被配置为将第二初始化信号传输至所述第m-1行子像素的所述发光器件的第一电极；
在第二方向上，所述第一初始化信号线在所述衬底基板上的投影位于所述第二初始化信号线在所述衬底基板上的投影远离第m-1行子像素在所述衬 底基板上投影的一侧，所述第二方向为子像素列的延伸方向，m为大于等于1且小于等于M的正整数；
所述第一初始化信号与第二初始化信号不同。
可选的，所述第一初始化信号线和所述第二初始化信号线位于相邻两行子像素的驱动晶体管之间，且在所述第二方向上位于其中任意一行所述驱动晶体管的同侧。
可选的，在第二方向上，所述第一初始化信号线的宽度与所述第二初始化信号线的宽度不同。
可选的，在所述第二方向上，所述第二初始化信号线的宽度大于所述第一初始化信号线的宽度。
可选的，在所述第二方向上，所述第二初始化信号线的宽度是所述第一初始化信号线宽度的1.3～2.4倍。
可选的，所述显示基板还包括：复位信号线，所述复位信号线沿所述第一方向延伸，用于向所述像素驱动电路传输复位信号；
所述多个晶体管还包括：第一复位晶体管和第二复位晶体管；
所述第一复位晶体管被配置为在所述复位信号的控制下，将所述第一初始化信号线上的第一初始化信号传输至所述第m行子像素的驱动晶体管的控制极；所述第二复位晶体管被配置为在所述复位信号的控制下，将所述第二初始化信号线上的第二初始化信号传输至所述第m-1行子像素的发光器件的第一电极。
可选的，在所述第二方向上，所述复位信号线、第二初始化信号线，第一初始化信号线沿远离所述第m行子像素驱动晶体管的方向依次排列。
可选的，在垂直于显示基板的方向上，所述驱动电路层包括在衬底基板上依次设置的半导体层、第一导电层、第二导电层，第三导电层和第四导电层；
所述半导体层包括所述多个晶体管的有源层，所述有源层包括晶体管的沟道区和源漏区；所述第一导电层包括所述复位信号线和晶体管的控制极；所述第二导电层包括所述第一初始化信号线和所述第二初始化信号线；所述第三导电层包括第一电源线，所述第四导电层包括第二电源线和数据信号线。
可选的，所述显示基板还包括：沿所述第二方向延伸的第三初始化信号线，其中，所述第三初始化信号线与所述第一初始化信号线异层设置，且所 述第三初始化信号线与所述第一初始化信号线或所述第二初始化信号线电连接。
可选的，所述第三导电层还包括所述第三初始化信号线。
可选的，所述第三初始化信号线与所述第一初始化信号线电连接并呈网状分布。
可选的，相邻的所述第三初始化信号线之间设有至少一列子像素。
可选的，其中，相邻的所述第三初始化信号线之间设有至少两条所述第一电源线。
可选的，所述多个子像素包括出射红色光线的红色子像素，出射蓝色光线的蓝色子像素和出射绿色光线的绿色子像素，所述多个像素列包括红蓝像素列和绿像素列；所述红蓝像素列包括所述第二方向交替设置的红色子像素和蓝色子像素；所述绿像素列包括沿所述第二方向依次设置的绿色子像素；所述第三初始化信号线位于所述红蓝像素列。
可选的，与第n列所述红蓝像素列电连接的所述第三初始化信号线的形状与第n+1列所述红蓝像素列电连接的所述第三初始化信号线的形状相同，n为大于等于1且小于等于N的正整数。
可选的，所述第三初始化信号线包括沿所述第二方向依次连接的第一延伸部、第二延伸部、和第三延伸部。所述第一延伸部沿所述第二方向延伸，并与所述第一初始化信号线通过过孔电连接。所述第三延伸部的延伸方向与所述第一延伸部的延伸方向不同，所述第二延伸部用于连接所述第一延伸部和所述第三延伸部，所述第二延伸部的延伸方向偏离所述第二方向。
可选的，所述第一延伸部在所述衬底基板上的投影与所述复位信号线、第一初始化信号线、第二初始化信号线在所述衬底基板上的投影具有交叠区域。
可选的，所述第一延伸部与所述第一晶体管的第一极通过过孔连接。
可选的，
所述第二延伸部与所述第一延伸部呈大于90°且小于180°的角度；
所述第三延伸部与所述第二延伸部呈大于90°且小于180°的角度；
可选的，所述多个晶体管还包括：第二晶体管，所述第二晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动晶体管的控制极电连接；
所述第二导电层还包括：遮挡部，所述遮挡部与所述第一电源线电连接，所述遮挡部在衬底基板上的投影覆盖所述第二晶体管的至少部分源漏区且与所述数据信号线在所述衬底基板上的投影位于相邻所述数据信号线在所述衬底基板上的投影之间。
可选的，所述第三导电层还包括第四连接部和第五连接部，所述第四导电层还包括第七连接部，所述第七连接部与所述第四连接部和所述第五连接部电连接。所述第四连接部与所述第五连接部形状不同。
在另一个方面，本公开实施例还提供一种显示装置，包括如前任一项实施例所述的显示基板。
本公开实施例所述的显示基板和显示装置通过对第m行子像素驱动晶体管的栅极采用第一初始化信号线复位，对第m-1行子像素发光元件的第一电极采用第二初始化信号线进行复位，第一初始化信号与第二初始化信号为不同的信号，使得驱动晶体管的栅极和发光元件的第一电极得以更好的复位，从而使得黑态下，能够保证OLED显示基板具有更低的亮度，提升显示均匀性。并且，本公开实施例还提供一种显示基板和显示装置，具有在特定像素列分布的第三初始化信号线，第三初始化信号线与第一初始化信号线或第二初始化信号线呈网状电连接，能够显著降低初始化信号线的阻抗，提高画面质量。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1a为本公开实施例中一种显示基板的平面结构示意图；
图1b为本公开实施例中另一种显示基板的平面结构示意图；
图2为一种显示基板的剖面结构示意图；
图3为本公开一种显示面板的一种示例性实施例中像素驱动电路的电路结构示意图；
图4为图3像素驱动电路一种驱动方法中一种可能的时序图；
图5为本公开显示基板一种示例性实施例的结构的示意图；
图6a为图5中显示基板的半导体层的结构示意图；
图6b为图5中一个子像素区域内半导体层结构示意图的放大图；
图7为图5中显示基板的第一导电层的结构示意图；
图8为图5中显示基板的第二导电层的结构示意图；
图9为图5中显示基板的第三导电层的结构示意图；
图10为图5中显示基板的第四导电层的结构示意图；
图11为本公开显示基板一种示例性实施例的结构的示意图；
图12a为图11中显示基板的第三导电层的结构示意图；
图12b为图11中一个子像素区域内的第三导电层结构示意图的放大图；
图13为图11中显示基板中第一初始化信号线和第三初始化信号线连接示意图；
图14为图5、图11中显示基板半导体层和第一导电层叠层结构示意图；
图15为图11中结构与第五导电层叠层结构示意图；
图16为图15中显示基板的第五导电层结构示意图；
图17为图15中A-A’的剖面结构示意图；
图18为图15中B-B’的剖面结构示意图；
图19a、图19b、图19c为图11中周边区部分走线结构示意图。
附图标记说明:
11—第一有源层；         12—第二有源层；        13—第三有源层；
14—第四有源层；         15—第五有源层；        16—第六有源层；
17—第七有源层；
21—复位信号线；         22—第一扫描信号线；    221—第一凸出部；
23—发光控制信号线；     24—第一极板；          31—第一初始化信号线；
32—第二初始化信号线；   33—遮挡部；            34—第一导电部；
341—第一通孔；          41—第三初始化信号线；  42—第一电源线；
43—第一连接部；         44—第二连接部；        45—第三连接部
46—第四连接部           47—第五连接部；        411—第一延伸部；
412—第二延伸部；        413—第三延伸部；       414—第四延伸部；
415—第五延伸部；        416—第六延伸部；       421—第七延伸部；
51—数据信号线；         52—第二电源线；        53—平坦部；
531—第一颜色平坦部；    532—第二颜色平坦部；   533—第三颜色平坦部；
54—第六连接部；         55—第七连接部；        56—第八连接部；
61—第一电极；           61a—主体部分；         61b—辅助部分；
71—第一绝缘层；         72—第二绝缘层；        73—第三绝缘层；
73—第三绝缘层；         74—第四绝缘层；        75—第五绝缘层；
711—第一过孔；          8—像素定义层；         81—第一开口；
91—发光层；             91—第二电极；          001—衬底基板；
102—驱动电路层；        103—发光结构层；       104—封装层；
401—第一封装层；        402—第二封装层；       403—第三封装层。
具体实施方式
为使本公开实施例的目的、技术方案和优点更为清晰，现将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整的描述。以下所描述的实施例是本公开的一部分实施例而非全部的实施例。基于本公开所描述的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或 两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，三角形、矩形、梯形、五边形或六边形等形状是指在工艺和测量误差范围内呈近似三角形、矩形、梯形、五边形或六边形等相应形状，在实际工艺过程中，可以包括在公差范围内产生的倒角、弧边、圆角、凹凸等变形。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1a为本公开实施例的一种显示基板的平面结构示意图。如图1a所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一颜色子像素P1、一个出射第二颜色光线的第二颜色子像素P2和两个出射第三颜色光线的第三颜色子像素P3，四个子像素可以均包括像素驱动电路和发光器件，每个子像素中的像素驱动电路分别与扫描信号线、数据信号线和发光控制信号线连接，像素驱动电路被配置为在扫描信号线和发光控制信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一颜色子像素P1可以是出射红色光线的红色子像素(R)，该子像素P1的像素驱动电路与出射红色光线的发光器件的第一电极电连接，第二颜色子像素P2可以是出射蓝色光线的蓝色子像素(B)，该子像素P2的像素驱动电路与出射蓝色光线的发光器件的第一电极电连接，第三子像素P3可以是出射绿色光线的绿色子像素(G)，该子像素P3的像素驱动电路与出射绿色光线的发光器件的第一电极电连接。在示例性实施方式中，子像素的第一电极形状可以是矩形状、菱形、五边形或六边形。四个子像素的第一电极可以采用正方形(Square)方式排列，形成GGRB像素排布，如图1a所示；也可以采用钻石(Diamond)方式排列，形成RGBG像素排布，如图1b所示。在示例性实施方式中，四个子像素可以采用水平并列或竖直并列等方式排列，在示例性实施方式中，像素单元可以包括三个子像素，三个子像素的第一电极可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容。像素驱动电路可以是2T1C、3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构，其中T代表薄膜晶体管，C代表存储电容。图2中以仅有一个驱动晶体管210和一个存储电容211为例对像素驱动电路的结构进行简单示意。
如图2所示，显示基板具有衬底基板001，衬底基板001可以为柔性衬底 基板也可以为刚性衬底基板。每个子像素的发光结构层103可以包括多个膜层，多个膜层可以包括第一电极301、像素定义层8、发光层303和第二电极304，第一电极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与第一电极301连接，第二电极304与有机发光层303连接，有机发光层303在第一电极301和第二电极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括层叠设置的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层以是连接在一起的共通层、所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，图3为一种像素驱动电路的等效电路示意图。如图3所示，像素驱动电路可以包括7个晶体管:第一复位晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第二复位晶体管T7、1个存储电容C。其中，与驱动晶体管栅极连接的节点为第一节点N1，驱动晶体管T3的第一极与第四晶体管T4连接的节点为第二节点N2，第二晶体管T2与驱动晶体管T3连接的位置为第三节点N3。
其中，第一复位晶体管T1的第一极与第一初始化信号端INIT1连接，第一晶体管的控制极与第一复位信号端Re1连接，第一复位晶体管T1的第二极与第一节点N1连接；当导通电平扫描信号施加到第一复位信号端Re1时，第一复位晶体管T1将第一初始化信号传输到驱动晶体管T3的控制极，以使驱动晶体管T3的控制极的电压初始化。
第二晶体管T2的控制极与第一扫描信号端S1连接，第二晶体管T2的第 一极与第一节点N1连接，第二晶体管T2的第二极与驱动晶体管T3的第二极连接；当导通电平扫描信号施加到第一扫描信号线端S1时，第二晶体管T2使驱动晶体管T3的控制极与第二极连接。
驱动晶体管T3的控制极与第一节点N1连接，即驱动晶体管T3的控制极与存储电容C的第二极板连接，驱动晶体管T3的第一极与第二节点N2连接，驱动晶体管T3的第二极与第三节点N3连接。驱动晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源信号端VDD与第二电源信号端VSS之间流动的驱动电流值，以驱动发光器件进行发光。
第四晶体管T4的第一极与数据信号端DATA连接，第四晶体管T4的第二极与驱动晶体管T3的第二极连接，第四晶体管T4的控制极与第一扫描信号端S1连接；当导通电平扫描信号施加到第一扫描信号端S1时，第四晶体管T4被配置为将数据信号端DATA提供的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号控制端EM连接，第五晶体管T5的第一极与第一电源信号端VDD连接，第五晶体管T5的第二极与驱动晶体管T3的第一极连接，即第五晶体管T5的第二极与第二节点N2连接；第六晶体管的控制极与发光信号控制端EM连接，第六晶体管的第一极与驱动晶体管T3的第二极连接，第六晶体管的第二极与发光器件的第一电极连接，第六晶体管T6的第一极与第三节点N3连接。当导通电平发光信号施加到发光信号端EM时，第五晶体管T5和第六晶体管T6通过在第一电源信号端VDD与第二电源信号端VSS之间形成驱动电流路径而使发光器件发光。
第二复位晶体管T7的控制极与第二复位信号端Re2连接，第二复位晶体管T7的第一极与第二初始化信号端INIT2连接，第二复位晶体管T7的第二极与发光器件的第一电极连接。当导通电平扫描信号施加到第二复位信号端Re2时，第二复位晶体管T7将第二初始化信号传输到发光器件的第一电极，以使发光器件的第一电极中累积的电荷量初始化或释放发光器件的第一电极中累积的电荷量。
存储电容C具有第一极板和第二极板，第一极板与第一电源信号端VDD连接，第二极板与第一节点N1连接。即存储电容C的第二极板与驱动晶体管T3的控制极连接。
在示例性实施方式中，发光器件可以是OLED，包括层叠设置的第一电极(阳极)、有机发光层和第二电极(阴极)，或者可以是QLED，包括层 叠设置的第一电极(阳极)、量子点发光层和第二电极(阴极)。
在示例性实施方式中，发光器件的第二电极与第二电源信号端VSS连接，第二电源信号端VSS的信号为低电平信号，第一电源信号端VDD的信号为持续提供高电平信号。对于第m显示行，第二复位信号端Re2为Re(m)，第一复位信号端Re1为Re(m-1)，本显示行的第一复位信号端Re1与上一显示行像素驱动电路中的第二复位信号端Re2可为同一信号，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，像素电路中的七个晶体管可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，像素电路中的晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成同时含有低温多晶硅薄膜晶体管和氧化物晶体管的(Low Temperature Poly-Silicon+Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图4为图3像素驱动电路一种驱动方法的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例。其中，Re1表示第一复位信号端的时序，Re2表示第二复位信号端的时序，S1表示第一扫描信号端的时序，EM表示发光控制信号端的时序，DATA表示数据信号端的时序，7个晶体管均为P型晶体管。
在示例性实施方式中，以OLED为例，像素驱动电路的工作过程可以包括：
第一阶段t1，称为复位阶段。第一复位信号端Re1输出低电平信号，使第一复位晶体管T1导通，第一初始化信号端INIT1向第一节点N1输入初始信号，并对存储电容C进行初始化，清除存储电容中原有数据电压。第二复 位信号端Re2、第一扫描信号端S1和发光信号控制端EM输出高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第二复位晶体管T7断开，此阶段OLED不发光。
第二阶段t2，称为数据写入阶段或者阈值补偿阶段。第一扫描信号端S1输出低电平信号，第四晶体管T4、第二晶体管T2、第二复位晶体管T7导通，同时数据信号端DATA输出驱动信号以向第一节点N1写入数据电压，此时，第二晶体管T2打开使驱动晶体管T3处于二极管连接状态，数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号端DATA输出的数据电压与驱动晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二极板(第二节点N2)的电压为Vdata-|Vth|，Vdata为数据信号线DATA输出的数据电压，Vth为驱动晶体管T3的阈值电压。
第二复位晶体管T7导通使得第二初始化信号端INIT2的第二初始化电压提供至OLED的第一电极，对OLED的第一电极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第一复位信号线Re1输出高电平信号，使第一晶体管T1断开。发光控制信号端EM输出高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段t3，称为发光阶段。发光控制信号端EM输出低电平信号，第一复位信号端Re1、第二复位信号端Re2和第一扫描信号端S1输出高电平信号。发光控制信号端EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源信号端VDD输出的第一电源电压通过导通的第五晶体管T5、驱动晶体管T3和第六晶体管T6向OLED的第一电极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过驱动晶体管T3的驱动电流由其控制极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vdata+|Vth|)] 2＝K*[(Vdd-Vdata)] 2
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为驱动晶体管T3的控制极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据信号端DATA输出的数据电压，Vdd为第一电源信号端VDD输出的第一电源电压。该像素驱动电路能够避免 驱动晶体管阈值对其输出电流的影响。
其中，该像素驱动电路可以分别通过第一初始化信号端INIT1向第一节点N1提供第一初始化信号，通过第二初始化信号端INIT2向发光器件的第一电极提供第二初始化信号。
具体地，在示例性实施方式中，本公开提供一种显示基板，包括：
衬底基板；
多个阵列分布的子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述多个子像素形成M行*N列的阵列，M和N为大于等于1的正整数；所述像素驱动电路包括多个晶体管，所述多个晶体管包括驱动晶体管；所述发光器件包括第一电极；
所述衬底基板还包括：第一初始化信号线，第二初始化信号线；所述第一初始化信号线和第二初始化信号线沿第一方向延伸，所述第一方向为所述子像素行的延伸方向；
其中，所述第一初始化信号线分别与第m行子像素电连接，被配置为将第一初始化信号传输至所述第m行子像素的驱动晶体管的控制极；所述第二初始化信号线分别与第m-1行子像素电连接，被配置为将第二初始化信号传输至所述第m-1行子像素的所述发光器件的第一电极；
在第二方向上，所述第一初始化信号线在所述衬底基板上的投影位于所述第二初始化信号线在所述衬底基板上的投影远离第m-1行子像素在所述衬底基板上投影的一侧，所述第二方向为子像素列的延伸方向，m为大于等于1且小于等于M的正整数；
所述第一初始化信号与第二初始化信号不同。
具体地，如图5所示，显示基板包括衬底基板；图5所示为该实施方式中显示基板的具体结构图：在平行于显示基板的平面内，显示基板可以包括多个阵列分布的子像素，多个阵列分布的子像素其中至少一个包括像素驱动电路，多个像素驱动电路沿第一方向形成M个像素行，多个像素驱动电路沿第二方向排列形成N个像素列，M，N均为大于或等于1的正整数，第一方向和第二方向交叉，进一步的，第一方向与第二方向可以垂直。
如图5所示，像素驱动电路可以包括多个晶体管和发光器件，像素驱动电路可调整流经驱动晶体管的驱动电流，以驱动发光器件进行发光。
请继续参考图5，显示基板还包括第一初始化信号线31和第二初始化信 号线32，第一初始化信号线31和第二初始化信号线32均为主体部分沿第一方向延伸的信号线；在本公开中，A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分为线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其他方向伸展的长度。第一初始化信号线31可以向像素驱动电路中的第一初始化信号端INIT1提供第一初始化信号Vinit1，第二初始化信号线32可以向像素驱动电路中的第二初始化信号端INIT2提供第二初始化信号Vinit2。
请继续参照图5，以第m行像素行为例，第一初始化信号线31分别与第m行子像素电连接，第一初始化信号线31被配置为将在其上传输的第一初始化信号Vinit1传输至第m行像素驱动晶体管的控制极，即驱动晶体管的栅电极，将其进行复位；第二初始化信号线32分别与第m-1行各子像素电连接，第二初始化信号线32被配置为将在其上传输的第二初始化信号Vinit2传输至第m-1行子像素的发光器件的第一电极，例如，该第一电极可以为阳极，从而完成对发光器件阳极的复位。在第二方向上，第一初始化信号Vinit1在衬底基板上的投影位于第二初始化信号线Vinit2在衬底基板上的投影远离第m-1行像素的一侧。其中，m为大于等于1且小于等于M的正整数。
其中，第一初始化信号Vinit1与第二初始化信号Vinit2可以不相等，因此，该像素驱动电路可以根据实际需求向第一节点N1和发光器件的第一电极提供不同的初始化信号。例如，可以将第一初始化信号的有效电平电压设置为-3V，将第二初始化信号的有效电平电压设置为-4V，可以确保显示屏幕在黑态下具有低亮度，改善画面显示效果。在另一种可能的实施方式中，第一初始化信号线31和第二初始化信号线32位于相邻两行子像素的驱动晶体管之间，且在第二方向上位于其中任意一行的驱动晶体管的同侧。如图5所示，在列方向上，第一初始化信号线31与第二初始化信号线32位于第m行像素驱动晶体管与第m-1行像素的驱动晶体管之间，且位于第m行驱动晶体管的同侧，也位于第m-1行驱动晶体管的同侧。将第一初始化信号线31和第二初始化信号线32设置于相邻两行子像素之间，可以使得两信号线在分别复位第m行像素的第一节点N1以及第m-1行像素的发光器件的第一电极时，具有相对更短的复位路径，能够更迅速且充分进行复位。同时，这样的设置方式也有助于更好地利用显示基板的空间，使像素排布更为合理，占用空间更小，更容易实现高分辨率的显示。
在另一种可能的实施方式中，第一初始化信号线31在第二方向上的宽度与第二初始化信号线32在第二方向上的宽度不相同，需要说明的是，所述“在第二方向上的宽度”指的是两信号线沿第一方向延伸的主要部分在第二方向上的宽度。第二方向也即像素列的延伸方向。信号线的方块电阻值与其宽度具有负相关的关系，即线宽越大，方块电阻则越小，将两信号线其中之一的线宽设置为更宽，可以有效减小两信号线整体的方块电阻；同时，将两者其中之一设置为线宽更宽，也有助于在降低电阻的同时，充分利用显示基板的空间，以提升显示效果。具体地，在可能的一种实施方式中，第二初始化信号线32在第二方向上的宽度可以大于第一初始化信号线在第二方向上的宽度。更进一步地，在可能的一种实施方式中，第二初始化信号线32的宽度是第一初始化信号线31宽度的1.3～2.4倍。
在另一种可能的实施方式中，请继续参照图5，显示基板还包括：沿第一方向延伸的复位信号线21，多个晶体管包括第一复位晶体管T1和第二复位晶体管T7。以第m行子像素为例：复位信号线21用于向第m行子像素驱动电路的第一复位信号端Re1提供第一复位信号，同时复位信号线21用于向第m-1行子像素驱动电路的第二复位信号端Re2提供第二复位信号，此时，第m行的第一复位信号Re1与第m-1行的第二复位信号Re2为同一信号。具体地，以P型晶体管为例，在第一复位信号Re1为低电平信号时，第m行像素电路的第一复位晶体管T1导通，第一初始化信号Vinit1可经由第一复位晶体管T1写入至第m行子像素的驱动晶体管T3的控制极；第二复位晶体管T7在第二复位信号为低电平时导通，第二初始化信号Vinit2可经由第二复位晶体管T7写入至第m-1行子像素的第一电极。
在示例实施方式中，请继续参照图5，在第二方向上，复位信号线21，第一初始化信号线31，第二初始化信号线32沿远离第m行子像素驱动晶体管的方向依次排列。
在示例性实施方式中，如图6-图10所示，在垂直于显示基板的平面内，显示基板可以包括依次设置在衬底基板上的半导体层1、第一导电层2、第二导电层3、第三导电层4和第四导电层5；半导体层1包括多个晶体管的有源层，有源层包括晶体管的沟道区和源漏区；第一导电层2包括复位信号线21和晶体管的控制极，第二导电层3包括第一初始化信号线31，第二初始化信号线32；第三导电层4包括第一电源线42，晶体管的第一极和第二极，第四 导电层5包括第二电源线52和数据信号线51。
在另一种可能的实施方式中，请参照图11，显示基板还包括沿第二方向延伸的第三初始化信号线41，与第一初始化信号线31不同层设置。图11所示实施例中的半导体层，第一金属层、第二金属层、第四金属层等均可参照图6a、图7、图8、图10进行设置，在此不再赘述。本公开中的“A与B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。第三初始化信号线41与第一初始化信号线31、第二初始化信号线32其中之一电连接。具体地，请参照图12a和图12b，第三初始化信号线41可以位于第三导电层4；在另一种可能的实施方式中，请参照图11，第三初始化信号线41可以与第一初始化信号线31电连接。
将第三初始化信号线41与第一初始化信号线31和第二初始化信号线32异层设置，并将其与两者其中之一电连接，可以使初始化信号Vinit1或Vinit2在不同层的不同方向进行传输，有助于降低初始化信号传输电压降，提升显示画面的均一性。具体地，第三初始化信号线41可以与第一初始化信号线31通过过孔连接。
进一步地，在另一种可能的实施方式中，第三初始化信号线41与第一初始化信号线31通过过孔连接形成网状分布结构，如图13所示，采用网状分布结构能够显著降低第一初始化信号Vinit1传输的电压降，能够更显著改善画面的均一性。
在另一种可能的实施方式中，请继续参考图11，相邻的两条第三初始化信号41之间设置有至少一列子像素。即对于总共为M行N列的子像素，第三初始化信号线41仅设置于奇数列，如第一列、第三列、第五列……，依次类推。当然，第三初始化信号线41也可以仅设置于偶数列，如第二列、第四列、第六列……，依次类推。将第三初始化信号线41间隔列设置，有助于增大相邻两信号线之间的距离，减小寄生电容，提高显示画面质量。
在另一种可能的实施方式中，请继续参考图11，相邻的两条初始化信号线41之间设置有至少两条第一电源线42。例如，相邻两第三初始化信号线41之间可以设置两条电压恒定的第一电源线42，第一电源线42为像素驱动电路的第一电源信号端VDD提供第一电源电压Vdd。这样的设置方式有利于最大化利用衬底基板的空间，实现像素的紧密排布，同时能够防止相邻的第三初始化信号线41之间产生串扰，提高显示画面质量。
在一种可能的实施方式中，相邻两第三初始化信号线的形状可以相同，也可以不相同。本公开中所提到的“A与B形状相同”指的是在合理的误差范围或者工艺偏差内，A与B的形状大致相同。
在一种可能的实施方式中，多个晶体管包括第一复位晶体管T1，第二晶体管T2，驱动晶体管T3，第四晶体管T4，第五晶体管T5，第六晶体管T6和第二复位晶体管T7。
如图6a和图6b所示半导体层1包括：第一晶体管T1的第一有源层11至第二复位晶体管的第七有源层17。每个晶体管的有源层包括源漏区和沟道区，每个晶体管的源漏区包括第一区和第二区，各晶体管的沟道区位于该晶体管的第一区和第二区之间。具体地，如图6b所示，第一有源层11包括第一晶体管T1的沟道区111、第一区112和第二区113,第一有源层12包括第二晶体管T2的沟道区121、第一区122和第二区123，第三有源层13包括驱动晶体管T3的沟道区131、第一区132和第二区133，第四有源层14包括第四晶体管T4的沟道区141、第一区142和第二区143，第五有源层15包括第五晶体管T5的沟道区151、第一区152和第二区153，第六有源层16包括第六晶体管T6的沟道区161、第一区162和第二区163，第七有源层17包括第七晶体管T7的沟道区171、第一区172和第二区173。其中，第一有源层11的第一区112单独设置，第一有源层11的第二区113同时作为第二有源层12的第一区122，第三有源层13的第一区132同时作为第四有源层14的第二区143和第五有源层15的第二区153，第三有源层13的第二区133同时作为第二有源层12的第二区123和第六有源层16的第一区162，第六有源层16的第二区163同时作为第七有源层17的第一区172。在示例性实施例中，第四有源层14的第一区142、第五有源层15的第一区152、第七有源层的第二区173单独设置。
第m-1行像素行中的第一有源层11、第二有源层12、第四有源层14位于本像素驱动电路的第三有源层13远离第m行像素行的一侧，第一有源层11位于第二有源层12和第四有源层14远离第三有源层13的一侧，第m-1行像素行中的第五有源层15、第六有源层和第七有源层17位于第三有源层13靠近第m行像素行的一侧。
其中，示例性地：第一有源层11可以呈现“n”字形，为包含两个沟道区的双栅结构；第二有源层12可以为“7”字形，为包含两个沟道区的双栅 结构；第三有源层13可以为“几”字形，也可为“I”字形，各有源层的形状可以根据工艺需要进行选择，本公开对此不做限制。
如图7所示，第一导电层2包括复位信号线21，第一扫描信号线22，发光信号控制线23以及存储电容C的第一极板24，第一导电层2可以称做第一栅金属层(Gate1层)。
为第m-1行像素驱动电路的提供第一复位信号的复位信号线21和提供第一扫描信号的第一扫描信号线22位于本像素行的第一极板24远离第m行子像素的一侧，第一扫描信号线22位于给本像素行提供第一复位信号的复位信号线21远离第一极板24的一侧，发光控制信号线23可以位于本像素行的第一极板24靠近第m行像素的一侧。
图14所示为半导体层1和第一导电层2的层叠结构示意图，第一导电层2上与半导体层1在衬底基板上投影重叠的区域可以作为各晶体管的控制极，具体地：复位信号线21的部分结构可以用于形成第一复位晶体管T1的控制极(栅极)和第二复位晶体管T7的控制极(栅极)，对于给第m行像素提供第一复位信号的复位信号线21，其部分结构可以构成本行像素行的第一复位晶体管T1的控制极和第m-1行第二复位晶体管T7的控制极。第一扫描信号线22的部分结构可以用于形成第二晶体管T2、第四晶体管T4的控制极(栅极)，第一扫描信号线22包括第一凸出部221，第一凸出部221包括第二晶体管T2的控制极。发光控制信号线23可以为像素电路的发光控制信号端EM提供发光控制信号，发光控制信号线23的部分结构可以用于形成第五晶体管T5和第六晶体管T6的控制极(栅极)。第一极板24可以同时作为驱动晶体管T3的控制极(栅极)。第一极板24可以为圆角矩形形状，其在衬底基板上的投影与驱动晶体管T3在衬底基板上的投影具有重叠区域。
具体地，在衬底基板的制备过程中，可以包括：在衬底基板上沉积一层半导体层1，并对半导体层1进行图案化形成各个晶体管的有源层；在半导体层1上沉积一层绝缘层薄膜，而后在该绝缘层薄膜上沉积第一导电层2，对第一导电层2图案化形成复位信号线21，第一扫描信号线22，发光控制信号线EM，第一极板24；对半导体层1进行导体化处理，被第一导电层2遮挡的区域形成T1T7的沟道区域，未被遮挡的第一导电层1则被导体化，即T1至T7的源漏区均被导体化。
如图8所示，第二导电层3包括：第一初始化信号线31，第二初始化信 号线32，遮挡部33，第一导电部34，包括存储电容C的第二极板，第一导电部34上设置有第一通孔341。请参照图4和图11，在一种可能的实施方式中，第二初始化信号线32在衬底基板上的投影与至少部分第一晶体管T1的源漏区在衬底基板上的投影交叠，具体地，当第一晶体管T1为双栅晶体管时，第二初始化信号线32遮挡第一晶体管T1两个双栅之间的导体化部分，以防止双栅之间的导体化部分受到像素驱动电路其他部分的影响，以提升显示效果。
如图12a和图12b所示，第三导电层4可以包括：第三初始化信号线41，第一电源线42，第一连接部43，第二连接部44，第三连接部45，第四连接部46和第五连接部47；第三初始化信号线41包括沿第二方向依次连接的第一延伸部411，第二延伸部412，第三延伸部413。其中，第一延伸部411沿第二方向延伸，并且与第一初始化信号线31通过过孔电连接。第三延伸部413的延伸方向与第一延伸部411的延伸方向不同，第二延伸部412用于连接第一延伸部411和第三延伸部413。第二延伸部412的延伸方向偏离第二方向。
请继续参考图12a与图12b，在一些可能的实施方式中，第一延伸部411沿第二方向延伸，第二延伸部412与第一延伸部411连接，具有夹角α1，且90°<α1<180°，例如可以为130°到135°；第三延伸部413与第二延伸部412连接，具有夹角α2，且90°<α2<180°，例如可以为125°到135°
在一些可能的实施方式中，请继续参考图12a和图12b，第三初始化信号线还可以包括第四延伸部414，第五延伸部415和第六延伸部416；其中，第四延伸部414和第三延伸部413连接，连接位置可以为倒角或圆角结构，第四延伸部414沿第一方向延伸；第五延伸部415与第四延伸部414连接，具有夹角α3，且90°<α3<180°，例如可以为125°到135°。第六延伸部416与第五延伸部415连接，第六延伸部416沿第二方向延伸，第五延伸部415与第六延伸部416具有夹角α4，且90°<α4<180°，例如可以为125°到135°。
需要说明的是，以上各个延伸部的夹角指的是各个延伸部所在的线段之间的夹角，本领域技术人员可以理解的是，在实际工艺过程中，各个延伸部边缘可以不如图12a和图12b中所呈现的均为规则直线，而可以呈现为波浪形状、曲边形状或其他工艺误差范围内允许的不规则的边缘形状，从而，同 样可以理解的是，以上夹角实际可以是具有一定程度的偏差(例如±10°)。
请参考图12，第一延伸部413在衬底基板上的投影与复位信号线21，第一初始化信号线31，第二初始化信号线32在衬底基板上的投影均具有交叠区域，第一延伸部413还与第一晶体管T1的第一区通过过孔电连接，即，第一延伸部413通过与第一初始化信号线31连接，可以传输第一初始化信号Vinit1，用于形成网状结构，降低传输压降，同时，第一延伸部413可以将第一初始化信号Vinit1传输到第一晶体管T1的第一区，进而对存储电容C的第一极板24和驱动晶体管的控制极进行复位。
请参照图11和图12，第二延伸部412在衬底基板上的投影与第一凸出部221在衬底基板上的投影以及遮挡部33在衬底基板上的投影均有交叠部分。第二延伸部412与第一延伸部411呈夹角α1，合理设置第二延伸部412与第一延伸部411的夹角可以对像素电路进行避让，在合理占用衬底基板的空间的前提下，尽量减小寄生电容。沿第一方向，第三延伸部413在衬底基板上的投影，位于驱动晶体管T3在衬底基板上投影远离第一电源线42在衬底基板上的投影一侧。
请继续参照图11和图12，第二连接部44与第二初始化信号线32通过过孔连接，且与第二复位晶体管T7的第一区连接，以将第二初始化号Vinit2传输至发光器件的第一电极，将其复位；第三连接部45的第一端与驱动晶体管T3的控制极通过过孔连接，第二端与第二晶体管T2的第一区通过过孔连接。
请继续参照图12，第一电源线42可以包括：多个第七延伸部421，第七延伸部421可以包括沿第一方向弯折的部分，第七延伸部421在第一方向上的宽度大于第一电源线42其它位置在第一方向上的宽度。第七延伸部421与第五晶体管T5的第一区及第第一导电部43电连接，以将Vdd信号传输至第一导电部421，为存储电容的第二极板及驱动晶体管提供第一电源电压信号，同时，第一导电部43可以通过第七延伸部421在第一方向上横联，以降低第一电源电压传输的压降，提升显示效果。
如图10所示，第四导电层5包括数据信号线51，第二电源线52，第六连接部54，第七连接部55，第八连接部56和平坦部53，其中，平坦部53还包括第一颜色平坦部531，第二颜色平坦部532和第三颜色平坦部533。数据信号线51用于向像素驱动电路的数据信号端DATA传输数据电压信号Vdata，数据信号线51通过第六连接部54与第一连接部43连接，第一连接部43与 第四晶体管T4的第一区142连接。
在一种可能的实施方式中，请参照图11和图12，遮挡部33与第一电源线42通过过孔连接，且其在衬底基板上的投影覆盖第二晶体管T2的源漏区，并且遮挡部33在衬底基板上的投影与数据信号线51在衬底基板上的投影没有交叠部分。即：遮挡部33对第二晶体管T2的导体化区域进行遮挡，进一步地，当第二晶体管T2为双栅结构时，遮挡部33在衬底基板上的投影覆盖第二晶体管T2双栅之间的导体化部分在衬底基板上的投影。在其它导电结构的耦合下，导体化部分的电位容易产生变化，从而导致其向第二晶体管T2的源极或漏极漏电，因而，当遮挡部33具有Vdd电压时，有利于防止该导体化部分浮接(Floating)，起到一定的稳压作用，提高了画面质量；而同时，遮挡部33在衬底基板上的投影与数据信号线51在衬底基板上的投影不重叠，减小数据信号线51与遮挡部33之间的寄生电容，同时，遮挡部33起到稳压作用，可以防止相邻列的像素数据电压变化对子像素的影响，提升了画面质量。
第二电源线52与第一电源线42经由第八连接部56与第七延伸部421电连接，具体地，可以通过过孔连接。即，第二电源线52和第一电源线51并联，可以显著降低Vdd信号在传输过程中的压降，提高显示效果。
在一种可能的实施方式中，第二电源线52与第一电源线42在衬底基板上的投影至少部分重叠，进一步地，第二电源线52在第一方向上的宽度小于第七延伸部421在第一方向上的宽度。
第七连接部55与第四连接部46、第五连接部47通过过孔连接，第四连接部46、第五连接部47与第六晶体管T6的第二区通过过孔连接，第四连接部46和第五连接部47的形状可以不相同，例如，如图12所示，第五连接部47在第二方向上的长度大于第四连接部46，在一种可能的实施方式中，第四连接部46与第一初始化信号线41设置于相同像素列。当然，第四连接部46和第五连接部47的形状也可以相同。
请继续参考图10，第四导电层还包括平坦部53，平坦部53与第二电源线52连接，即平坦部53电位为Vdd信号，平坦部53与第二电源线52相连，能够使第二电源线的电阻减小，降低第二电源信号线52从第一端到第二端的压降，减小信号传输损失，提高显示效果。
请参考图15，在一种可能的实施方式中，平坦部53在衬底基板上的投影 与发光器件的第一电极在衬底基板上的投影至少部分重叠，第一电极可以为阳极，平坦部53可以用于提高第一电极的平整度，改善色偏，提升显示效果。进一步地，在其他可能的实施方式中，发光器件的第一电极在衬底基板上的投影完全覆盖平坦部53在衬底基板上的投影，在本公开中，“A的投影完全覆盖B”指B在某平面内的投影的轮廓完全位于A在同一平面内投影的轮廓的内部。
请继续参考图10，在一种可能的实施方式中，出射不同颜色光线的子像素的平坦部53的形状可以不相同，例如可以包括第一颜色平坦部531，第二颜色平坦部532和第三颜色平坦部533。当然，平坦部53的形状也可以相同。
请参考图10，在一种可能的实施方式中，第一颜色平坦部531的面积大于第二颜色平坦部532的面积和第三颜色平坦部533的面积。
在一种可能的实施方式中，请参照图1a和图1b，多个子像素包括出射不同颜色光线的第一颜色子像素P1，第二颜色子像素P2和第三颜色子像素P3。第一颜色子像素P1可以是出射红色光线的红色子像素(R)，该子像素P1的像素驱动电路与出射红色光线的发光器件的第一电极电连接，第二颜色子像素P2可以是出射蓝色光线的蓝色子像素(B)，该子像素P2的像素驱动电路与出射蓝色光线的发光器件的第一电极电连接，第三子像素P3可以是出射绿色光线的绿色子像素(G)，该子像素P3的像素驱动电路与出射绿色光线的发光器件的第一电极电连接。
请继续参照图1a和图1b，多个子像素P包括出射红色光线的红色子像素R，出射蓝色光线的蓝色子像素G和出射绿色光线的绿色子像素B阵列排布成多个像素行和多个像素列，多个像素列包括红蓝像素列RB和绿像素列GG；红蓝像素列RB包括沿第二方向交替设置的红色子像素R和蓝色子像素B；所述绿像素列GG中包括沿第二方向依次设置的绿色子像素G。
在一种可能的实施方式中，第三初始化信号线41仅设置于红蓝像素列RB。在另一种可能的实施方式中，第三初始化信号线41仅设置于绿绿子像素列GG。在另一种可能的实施方式中，第三初始化信号线41可同时设置于红蓝像素列RB和绿像素列GG。
在一种可能的实施方式中，位于第n列红蓝像素列RB的第三初始化信号线31的形状与位于第n+1列第三初始化信号线31的形状可以相同，其中n为大于等于1且小于等于N的正整数。
在一种可能的实施方式中，显示基板还包括第五导电层6，如图16所示，第五导电层6包括各子像素的第一电极61。具体地，第一颜色子像素、第二颜色子像素和第三颜色子像素中分别设置有第一电极611，第二电极612和第三电极613。
如图17所示，显示基板还包括第一绝缘层7，第三导电层5位于第一绝缘层7朝向衬底基板的一侧，第一绝缘层7包括第一过孔711，该第一过孔711暴露第连接部46和第连接部47。
第一电极61包括主体部分61a和辅助部分61b。辅助部分61b通过第一过孔711与第三导电层4电连接。在本公开实施例中，同一子像素中的主体部分61a和辅助部分61b为一体结构，可以采用一次构图工艺同时形成。
如图18所示，显示基板还包括像素定义层8，位于第五导电层6背离衬底基板一侧的发光层91，以及位于发光层91背离第五导电层6一侧的阴极92。其中像素定义层具有开口81，该开口暴露第一电极的主体部分的至少部分区域，发光层81位于开口81内且与开口暴露的主体部分的区域接触，开口中的发光层所处于的区域可以用于发光，从而可以通过开口限定出有效发光区EA。换言之，像素定义层8的开口与第一电极61的主体部分61a交叠的部分区域为各子像素的有效发光区EA。具体地，如图18所示，在一种可能的实施方式中，第二颜色子像素P2中的像素定义层8的开口与第一电极612的主体部分交叠区域为第二颜色子像素P2的有效发光区EA2。同理，第一颜色子像素P1中的像素定义层8的开口与第一电极611的主体部分611a交叠区域为第一颜色子像素P1的有效发光区EA1，第三颜色子像素P3中的像素定义层8的开口与第一电极613的主体部分交叠区域为第三颜色子像素P3的有效发光区EA3。
在一种可能的实施方式中，平坦部53位于第一电极61靠近衬底基板的一侧。如图15和图16所示，第一颜色平坦部531的形状与第一颜色子像素的第一电极611的主体部分611a形状基本相同，第二颜色平坦部532的形状与第二颜色子像素的第一电极612的主体部分612a形状基本相同，第三颜色平坦部533的形状与第三颜色子像素的第一电极613的主体部分613a形状基本相同。
在本公开中，“A与B形状基本相同”指A与B的轮廓线形状相同，且A与B的面积差值不超过±1％。
换言之，各个平坦部的形状与其上方的各第一电极的形状一一对应，有助于使各第一电极的各个部分均实现均匀平坦，消除不对称性，从而可改善甚至消除色偏。
在一种可能的实施方式中，不同颜色子像素的第一电极主体部分面积可以不相同，例如，第一颜色子像素第一电极的主体部分611a的面积可以大于第二颜色子像素第一电极的主体部分612a的面积和第三颜色子像素613a的面积；当然，各个颜色主体部分面积也可以相同，或根据需要尺寸进行设置，本公开对此不作限制。
如图15和图16所示，第一电极61的主体部分61a的主体部分的形状可以为八边形，相应的，各平坦部53的形状为也可以为近似八边形。其中第一颜色平坦部531包括第一凹陷部5311，第一凹陷部5311用于避让与第八连接部56与第七延伸部421电连接的过孔；第三颜色平坦部533包括第二凹陷部5331，第二凹陷部5331用于避让第七连接部55与第五连接部47电连接的过孔；在其他可能的实施方式中，主体部分61a的形状可以为六边形、矩形或其他形状，本公开对此不做限制。
在一种可能的实施方式中，各子像素的平坦部53在衬底基板上的投影与相应子像素的第一电极61在衬底基板上的投影至少部分交叠，具体地，第一颜色平坦部531在衬底基板上的投影与第一颜色子像素的第一电极611在衬底基板上的投影至少部分交叠，第二颜色平坦部532在衬底基板上的投影与第二颜色子像素的第一电极612在衬底基板上的投影至少部分交叠，第三颜色平坦部533在衬底基板上的投影与第三颜色子像素的第一电极613在衬底基板上的投影至少部分交叠。即，每个不同颜色子像素第一电极靠近衬底基板的一侧均有平坦部，这样能够使得每个子像素的第一电极均能够实现平坦，减小色偏，提高显示画面的均一性。
进一步地，在一种可能的实施方式中，第一颜色子像素的第一电极611在衬底基板上的投影完全覆盖第一颜色平坦部531在衬底基板上的投影，第二颜色子像素的第一电极612在衬底基板上的投影完全覆盖第二颜色平坦部532在衬底基板上的投影，第三颜色子像素的第一电极613在衬底基板上的投影完全覆盖第三颜色平坦部533在衬底基板上的投影。通常情况下，位于第一电极靠近显示基板一侧的第三导电层4和第四导电层5制作的信号线如第一电源线42和第二电源线52在垂直于衬底基板方向上的厚度较大，信号线 上方的绝缘层不能够实现完全的平坦化，从而导致平坦层上方的发光层不平整，第一电极61和第一电极61上方的发光层出现不对称凸起，进而导致从显示基板的法线左右两侧以与显示基板呈相同的角度观察时会产生色偏现象。而在不同的子像素的第一电极下方设置平坦部，且平坦部完全位于第一电极的投影内部，可以使各个子像素的第一电极的相应位置均能够实现平坦化，进一步改善色偏。
在一种可能的实施方式中，平坦部53在衬底基板上的投影与第一电源线41在衬底基板上的投影第一电源线41在衬底基板上的投影具有交叠部分，具体地，在本公开所示的实施例中，平坦部53在衬底基板上的投影与第一电源线42的第七延伸部421至少部分交叠。如此设置，有助于减小第一电源电压在信号线上传输的压降，提高显示画面均一性。
请参考图1a与图15，在一种可能的实施方式中，第一颜色子像素可以为出射红色光线的红色子像素R，第二颜色子像素可以为出射蓝色光线的蓝色子像素G，相对应的，第一颜色平坦部531和第二颜色平坦部532与第七延伸部421至少部分交叠。
请继续参考图15，在一种可能的实施方式中，第一颜色子像素可以为出射红色光线的红色子像素R，第二颜色子像素可以为出射蓝色光线的蓝色子像素B，此时，第一颜色平坦部531和第二颜色平坦部532在衬底基板上的投影与驱动晶体管T3的控制极24在衬底基板上的投影至少部分交叠，可以使第一节点N1的电位稳定。
请继续参考图15，在一种可能的实施方式中，第三颜色子像素可以为出射绿色光线的绿色子像素G，此时，第三颜色平坦部533在衬底基板上的投影与第一晶体管T1的源漏区和/或沟道区在衬底基板上的投影至少部分交叠，具体地，在第一复位晶体管T1为双栅晶体管时，第三颜色平坦部533遮挡第一复位晶体管T1双栅之间的导体化部分，可以起到减小漏电流的作用。在另一种可能的实施方式中，第一复位晶体管T1还可以是氧化物晶体管(IGZO)，此时第三颜色平坦部533遮挡氧化物晶体管T1，可以进一步避免光照对晶体管性能的影响。
请继续参考图1a和图15，在一种可能的实施方式中，第一颜色子像素，第二颜色子像素，第三颜色子像素分别出射红色光线、蓝色光线和绿色光线。多个红色子像素R和蓝色子像素B沿第二方向交替排列成RB像素列，多个 绿色子像素G沿第二方向交替排列呈绿像素列GG,红蓝像素列RB和绿像素列GG沿第一方向交替排列，其中，红色子像素R的第一电极的辅助部分611b在衬底基板上的投影与相邻绿色子像素G第二晶体管T2的源漏区在衬底基板上的投影至少部分交叠，在第二晶体管T2为双栅结构时，该交叠位置位于双栅之间的导体化区域，以减小第二晶体管T2的漏电，提高显示画面的均一性。同样地，蓝色子像素G的第一电极的辅助部分在衬底基板上的投影与相邻绿色子像素G的第二晶体管T2的源漏区在衬底基板上的投影至少部分交叠，原理和技术效果相同，此处不再赘述。
在一种可能的实施方式中，显示基板还可以包括：遮光层(图中未示出)。遮光层可以位于衬底基板与半导体层1之间，遮光层在衬底基板上的投影至少覆盖多个晶体管中的一个晶体管的有源区在衬底基板上的投影，例如，遮光层在衬底基板上的投影可以覆盖驱动晶体管T3的沟道区在衬底基板上的投影，用于遮挡外界光线以及屏蔽外界干扰，避免影响到各晶体管有源层的性能，提高显示效果。
更进一步地，在一种可能的实施方式中，遮光层可以为半导体材料(a-Si)或金属材料(Mo)。遮光层可以与恒定电位电连接，以避免遮光层处于浮接状态，对有源层的沟道区起到更好的抗干扰作用。具体地，遮光层可以与第一电源线41电连接，也可以与第一初始化信号线31或第二初始化信号线32电连接。
在另一种可能的实施方式中，遮光层可以仅包括沿第一方向延伸的第一连接结构，也可以仅包括第二方向延伸的第二连接结构，也可以同时包括沿第一方向延伸的第一连接结构和沿第二方向延伸的第二连接结构。
第一连接结构和第二连接结构可各自和其所电连接的结构呈网状连接，以显著降低loading。例如：第一连接结构可以与第一电源线41电连接并呈网状结构。又例如，第一连接结构可以与第三初始化信号线41电连接并呈网状结构。又例如，第二连接结构可以与第一初始化信号线31或第二初始化信号32电连接并呈网状结构。又例如，第二连接结构可以与第三初始化信号线41并联，且第二连接结构可以仅位于红蓝像素列，或仅位于绿绿像素列，或同时位于红蓝像素列和绿绿像素列。又例如，第一连接结构与第二连接结构可以呈网状连接，即遮光层本身可以呈网状。
如图1a和图19a所示，显示基板包括显示区AA和位于显示区外的周边 区NA，周边区NA可以包括左边框区NA-L,右边框区NA-R，上边框区NA-U和下边框区NA-D；在一种可能的实施方式中，在左边框区NA-L和右边框区NA-R各设置有沿第二方向延伸的第一初始化信号线总线31’和第二初始化信号线总线32’，多条第一初始化信号线31与第一初始化信号线总线31’电连接，多条第二初始化信号线32与第二初始化信号线总线32’电连接，同时在上边框区NA-U和/或下边框区NA-D可以设置有沿第一方向延伸的第三初始化信号线的总线41’，与多条第三初始化信号线41电连接。各初始化信号线总线为相应的初始化信号线提供初始化信号。
在另一种可能的实施方式中，如图19b所示，左边框区NA-L和右边框区NA-R各设置有沿第二方向延伸的第一初始化信号线总线31’和第二初始化信号线总线32’，多条第一初始化信号线31与第一初始化信号线总线31’电连接，多条第二初始化信号线32与第二初始化信号线总线32’电连接；
在另一种可能的实施方式中，如图19c所示，在上边框区NA-U和/或下边框区NA-D可以设置有沿第一方向延伸的第三初始化信号线的总线41’，与多条第三初始化信号线41电连接，为第三初始化信号线提供相应的初始化信号。
在可能的实施方式中，第一初始化信号线总线31’，第二初始化信号线总线32’，第三初始化信号线总线41’可以位于相同膜层，如可以均位于第三导电层4或均位于第四导电层5；当然也可以位于不同膜层，例如，第一初始化信号线总线31’可以位于第三导电层4，第二初始化信号线32’和第三初始化信号线总线41’可以位于第四导电层5，当然也可以根据具体需要进行设计，本公开对此不做限制。
本公开还提供一种显示装置，该显示装置包括：上述的显示面板。该显示装置可以为手机、平板电脑等显示装置。
本公开还提供一种显示基板的制作方法，至少包括以下步骤：
S1：在衬底基板上沉积一层半导体层1，并对半导体层1进行图案化形成各个晶体管的有源层；第一有源层11至第七有源层17为相互连接的一体结构。
S2：在半导体层1上沉积第二绝缘层72，而后在该第二绝缘层12上沉积第一导电层2，对第一导电层2图案化形成复位信号线21，第一扫描信号线22，发光控制信号线EM，第一极板24；如图7所示，第一金属层还可以称 为栅金属层(Gate1层)。
S3：对半导体层1进行导体化处理，如离子注入等，被第一导电层2遮挡的区域形成第一复位晶体管T1，第二晶体管T2，驱动晶体管T3，第四晶体管T4，第五晶体管T5，第六晶体管T6以及第二复位晶体管T7的沟道区域，未被遮挡的半导体层1则被导体化，即7个晶体管T1～T7的源漏区均被导体化。
S4：在第一导电层2上沉积第三绝缘层73，在该绝缘层上方沉积第二导电层3并进行图案化，第二导电层3包括第一初始化信号线31，第二初始化信号线32，遮挡部33，第一导电部34，第二导电层也可以成为第二栅金属层(Gate2层)。
S5：在第二导电层3上沉积第三绝缘层74，在第三绝缘层上方沉积第三导电层4并进行图案化，第三导电层至少包括，第三初始化信号线41，第一电源线42，第一连接部43，第二连接部44，第三连接部45，第四连接部46和第五连接部47。
S6：在第三导电层4上方沉积第一绝缘层71，在第一绝缘层71上沉积第四导电层5并进行图案化，第四导电层5至少包括数据信号线51，第二电源线52，平坦部53。
S7：在第四导电层5上沉积一层第四绝缘层75，在第四绝缘层75上方沉积第五导电层6并图案化，形成子像素的第一电极图案。
后续制备流程可以包括：采用喷墨打印或蒸镀工艺形成有机发光层，有机发光层通过像素定义层开口与第一电极连接，在有机发光层上形成第二电极，第二电极与有机发光层连接。形成封装层，封装层可以包括层叠设置的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以阻挡外界水汽入侵发光结构。
在示例性实施方式中，衬底基板可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层， 第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。第一绝缘层和第四绝缘层可以采用有机材料，如树脂等。第五导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种显示基板，包括：
    衬底基板；
    多个阵列分布的子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述多个子像素形成M行*N列的阵列，M和N为大于等于1的正整数；所述像素驱动电路包括多个晶体管，所述多个晶体管包括驱动晶体管；所述发光器件包括第一电极；
    所述衬底基板还包括：第一初始化信号线，第二初始化信号线；所述第一初始化信号线和第二初始化信号线沿第一方向延伸，所述第一方向为所述子像素行的延伸方向；
    其中，所述第一初始化信号线分别与第m行子像素电连接，被配置为将第一初始化信号传输至所述第m行子像素的驱动晶体管的控制极；所述第二初始化信号线分别与第m-1行子像素电连接，被配置为将第二初始化信号传输至所述第m-1行子像素的所述发光器件的第一电极；
    在第二方向上，所述第一初始化信号线在所述衬底基板上的投影位于所述第二初始化信号线在所述衬底基板上的投影远离第m-1行子像素在所述衬底基板上投影的一侧，所述第二方向为子像素列的延伸方向，m为大于等于1且小于等于M的正整数；
    所述第一初始化信号与第二初始化信号不同。
  2. 根据权利要求1所述的显示基板，其中，所述第一初始化信号线和所述第二初始化信号线位于相邻两行子像素的驱动晶体管之间，且在所述第二方向上位于其中任意一行所述驱动晶体管的同侧。
  3. 根据权利要求2所述的显示基板，其中，在第二方向上，所述第一初始化信号线的宽度与所述第二初始化信号线的宽度不同。
  4. 根据权利要求3所述的显示基板，其中，在所述第二方向上，所述第二初始化信号线的宽度大于所述第一初始化信号线的宽度。
  5. 根据权利要求4所述的显示基板，其中，在所述第二方向上，所述第二初始化信号线的宽度是所述第一初始化信号线宽度的1.3～2.4倍。
  6. 根据权利要求1～5中任一项所述的显示基板，其中，所述显示基板还包括：复位信号线，所述复位信号线沿所述第一方向延伸，用于向所述像素驱动电路传输复位信号；
    所述多个晶体管还包括：第一复位晶体管和第二复位晶体管；
    所述第一复位晶体管被配置为在所述复位信号的控制下，将所述第一初始化信号线上的第一初始化信号传输至所述第m行子像素的驱动晶体管的控制极；所述第二复位晶体管被配置为在所述复位信号的控制下，将所述第二初始化信号线上的第二初始化信号传输至所述第m-1行子像素的发光器件的第一电极。
  7. 根据权利要求6所述的显示基板，其中，在所述第二方向上，所述复位信号线、第二初始化信号线，第一初始化信号线沿远离所述第m行子像素驱动晶体管的方向依次排列。
  8. 根据权利要求1-7任一项所述的显示基板，其中，在垂直于显示基板的方向上，所述驱动电路层包括在衬底基板上依次设置的半导体层、第一导电层、第二导电层，第三导电层和第四导电层；
    所述半导体层包括所述多个晶体管的有源层，所述有源层包括晶体管的沟道区和源漏区；所述第一导电层包括所述复位信号线和晶体管的控制极；所述第二导电层包括所述第一初始化信号线和所述第二初始化信号线；所述第三导电层包括第一电源线，所述第四导电层包括第二电源线和数据信号线。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板还包括：沿所述第二方向延伸的第三初始化信号线，其中，所述第三初始化信号线与所述第一初始化信号线异层设置，且所述第三初始化信号线与所述第一初始化信号线或所述第二初始化信号线电连接。
  10. 根据权利要求9所述的显示基板，其中，所述第三导电层还包括所述第三初始化信号线。
  11. 根据权利要求9所述的显示基板，其中，所述第三初始化信号线与所述第一初始化信号线电连接并呈网状分布。
  12. 根据权利要求11所述的显示基板，其中，相邻的所述第三初始化信号线之间设有至少一列子像素。
  13. 根据权利要求12所述的显示基板，其中，相邻的所述第三初始化信号线之间设有至少两条所述第一电源线。
  14. 根据权利要求11所述的显示基板，其中，所述多个子像素包括出射红色光线的红色子像素，出射蓝色光线的蓝色子像素和出射绿色光线的绿色子像素，所述多个像素列包括红蓝像素列和绿像素列；所述红蓝像素列包括 所述第二方向交替设置的红色子像素和蓝色子像素；所述绿像素列包括沿所述第二方向依次设置的绿色子像素；所述第三初始化信号线位于所述红蓝像素列。
  15. 根据权利要求14所述的显示基板，其中，与第n列所述红蓝像素列电连接的所述第三初始化信号线的形状与第n+1列所述红蓝像素列电连接的所述第三初始化信号线的形状相同，n为大于等于1且小于等于N的正整数。
  16. 根据权利要求15所述的显示基板，其中，所述第三初始化信号线包括沿所述第二方向依次连接的第一延伸部、第二延伸部、和第三延伸部。所述第一延伸部沿所述第二方向延伸，并与所述第一初始化信号线通过过孔电连接。所述第三延伸部的延伸方向与所述第一延伸部的延伸方向不同，所述第二延伸部用于连接所述第一延伸部和所述第三延伸部，所述第二延伸部的延伸方向偏离所述第二方向。
  17. 根据权利要求16所述的显示基板，其中，所述第一延伸部在所述衬底基板上的投影与所述复位信号线、第一初始化信号线、第二初始化信号线在所述衬底基板上的投影具有交叠区域。
  18. 根据权利要求17所述的显示基板，其中，所述第一延伸部与所述第一晶体管的第一极通过过孔连接。
  19. 根据权利要求16所述的显示基板，其中，
    所述第二延伸部与所述第一延伸部呈大于90°且小于180°的角度；
    所述第三延伸部与所述第二延伸部呈大于90°且小于180°的角度；
  20. 根据权利要求8所述的显示基板，所述多个晶体管还包括：第二晶体管，所述第二晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动晶体管的控制极电连接；
    所述第二导电层还包括：遮挡部，所述遮挡部与所述第一电源线电连接，所述遮挡部在衬底基板上的投影覆盖所述第二晶体管的至少部分源漏区且与所述数据信号线在所述衬底基板上的投影位于相邻所述数据信号线在所述衬底基板上的投影之间。
  21. 根据权利要求8所述的显示基板，其中，所述第三导电层还包括第四连接部和第五连接部，所述第四导电层还包括第七连接部，所述第七连接部与所述第四连接部和所述第五连接部电连接。所述第四连接部与所述第五连接部形状不同。
  22. 一种显示装置，包括如权利要求1-21任一项所述的显示基板。
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