WO2022226801A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022226801A1
WO2022226801A1 PCT/CN2021/090323 CN2021090323W WO2022226801A1 WO 2022226801 A1 WO2022226801 A1 WO 2022226801A1 CN 2021090323 W CN2021090323 W CN 2021090323W WO 2022226801 A1 WO2022226801 A1 WO 2022226801A1
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WIPO (PCT)
Prior art keywords
light
pixel circuit
transistor
pixel circuits
initial signal
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PCT/CN2021/090323
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English (en)
French (fr)
Inventor
黄耀
程羽雕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/638,862 priority Critical patent/US20240038163A1/en
Priority to PCT/CN2021/090323 priority patent/WO2022226801A1/zh
Priority to CN202180000952.1A priority patent/CN115529844A/zh
Publication of WO2022226801A1 publication Critical patent/WO2022226801A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • This article relates to, but is not limited to, the field of display technology, especially a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • the under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of the display device.
  • Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device.
  • an embodiment of the present disclosure provides a display substrate, comprising: a base substrate having a first display area and a second display area, a plurality of second area light-emitting elements located in the second display area, and a plurality of light emitting elements located in the first display area a plurality of second type pixel circuits.
  • the first display area is located on at least one side of the second display area.
  • the plurality of second-type pixel circuits include a plurality of pixel circuits of the first structure and a plurality of pixel circuits of the second structure.
  • At least one pixel circuit in the plurality of pixel circuits of the first structure and at least one light-emitting element in the plurality of second-area light-emitting elements are connected by a first group of conductive lines. At least one pixel circuit of the plurality of pixel circuits of the second structure is connected to at least one light-emitting element of the plurality of second area light-emitting elements through a second group of conductive lines. The length of the second set of conductive lines is greater than the length of the first set of conductive lines.
  • the pixel circuit of the first structure is connected to a first initial signal line
  • the pixel circuit of the second structure is connected to the first initial signal line and the second initial signal line; the first The initial signal line and the second initial signal line provide different initial signals.
  • the display substrate further includes: a plurality of first area light emitting elements and a plurality of first type pixel circuits located in the first display area. At least one first-type pixel circuit of the plurality of first-type pixel circuits is connected to at least one first-area light-emitting element of the plurality of first-area light-emitting elements, and the at least one first-type pixel circuit is The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the at least one first area light-emitting element on the base substrate.
  • the plurality of first type pixel circuits are all pixel circuits of the first structure.
  • the pixel circuit of the first structure includes: a driving transistor, a first reset transistor and a second reset transistor.
  • the gate of the first reset transistor is connected to the first reset control line
  • the first pole of the first reset transistor is connected to the gate of the driving transistor
  • the second pole of the first reset transistor is connected to the first initial signal line connection.
  • the gate of the second reset transistor is connected to the second reset control line
  • the first electrode of the second reset transistor is connected to the first electrode of the light-emitting element
  • the second electrode of the second reset transistor is connected to the first initial electrode. Signal line connection.
  • the pixel circuit of the second structure includes: a driving transistor, a first reset transistor and a second reset transistor.
  • the gate of the first reset transistor is connected to the first reset control line
  • the first pole of the first reset transistor is connected to the gate of the driving transistor
  • the second pole of the first reset transistor is connected to the first initial signal line connection.
  • the gate of the second reset transistor is connected to the second reset control line
  • the first electrode of the second reset transistor is connected to the first electrode of the light-emitting element
  • the second electrode of the second reset transistor is connected to the second initial electrode.
  • Signal line connection The second initial signal provided by the second initial signal line is different from the first initial signal provided by the first initial signal line.
  • the first initial signal provided by the first initial signal line is a constant voltage signal.
  • the second initial signal provided by the second initial signal line is a constant voltage signal, and the second initial signal is greater than the first initial signal provided by the first initial signal line.
  • the magnitude of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure, the size of the second group of conductive lines connected to the pixel circuit of the second structure is proportional.
  • the pixel circuit of the first structure or the pixel circuit of the second structure further includes: a data writing transistor, a threshold compensation transistor, a first light emission control transistor and a second light emission control transistor.
  • the gate of the data writing transistor is connected to the scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor.
  • the gate of the threshold compensation transistor is connected to the scan line, the first electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor.
  • the gate of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power supply line, and the second electrode of the first light-emitting control transistor is connected to the first power line of the driving transistor.
  • One pole connection The gate of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the light-emitting element the first pole connection.
  • the display substrate in a plane perpendicular to the display substrate, includes at least: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer disposed on the base substrate.
  • the semiconductor layer includes at least: active layers of a plurality of transistors.
  • the first conductive layer at least includes: gates of a plurality of transistors and first electrodes of storage capacitors, scan lines, light emission control lines, first reset control lines and second reset control lines.
  • the second conductive layer at least includes: a second electrode of the storage capacitor, a first initial signal line, and a second initial signal line.
  • the third conductive layer at least includes: first and second electrodes of a plurality of transistors, a first power supply line, and a data line.
  • the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the first structure are of an integrated structure; the second reset transistor of the pixel circuit of the nth row of the first structure and the The active layers of the first reset transistors of the pixel circuits in the n+1 rows have an integrated structure, and n is a positive integer.
  • the first reset transistor of the pixel circuit of the second structure and the active layer of the second reset transistor are of an integrated structure; the second reset transistor of the pixel circuit of the nth row of the second structure has The source layer is not connected to the active layer of the first reset transistor of the pixel circuit in the n+1th row, and n is a positive integer.
  • the third conductive layer includes: a second electrode of the second reset transistor of the pixel circuit of the second structure, a second electrode of the second reset transistor of the pixel circuit of the first structure pole.
  • the second electrode of the second reset transistor of the pixel circuit of the second structure is connected to the second initial signal line through the via hole.
  • the second pole of the second reset transistor of the pixel circuit of the first structure is not connected to the second initial signal line.
  • the first set of conductive lines and the second set of conductive lines employ transparent conductive materials.
  • the plurality of second-type pixel circuits are spaced apart among the plurality of first-type pixel circuits.
  • the size of any pixel circuit in the first direction is smaller than the size of the first area light-emitting element in the first direction .
  • the plurality of second area light emitting elements include a plurality of groups of second area light emitting elements, the second area light emitting elements in each group are arranged along the first direction, and the plurality of groups of second area light emitting elements are arranged along the first direction. Arrangement in the second direction.
  • the plurality of second type pixel circuits include a plurality of groups of second type pixel circuits, the second type pixel circuits in each group are arranged along the first direction, and the plurality of groups of second type pixel circuits are arranged along the second direction.
  • the plurality of second area light-emitting elements at least include: a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of third light-emitting elements.
  • the plurality of second-type pixel circuits include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits; a plurality of first light-emitting elements are connected to the plurality of first pixel circuits, and a plurality of second light-emitting elements The elements are connected to the plurality of second pixel circuits, and the plurality of third light-emitting elements are connected to the plurality of third pixel circuits.
  • the plurality of first pixel circuits connected to the plurality of first light-emitting elements are smaller than the plurality of second pixels connected to the plurality of second light-emitting elements
  • Each of the circuits is closer to the second display area and is closer to the second display area than each of the plurality of third pixel circuits connected to the plurality of third light emitting elements.
  • the second pixel circuit connected to the second light-emitting element through the second group of conductive lines is a pixel circuit of the second structure
  • the third pixel circuit connected to the third light-emitting element through the second group of conductive lines It is the pixel circuit of the second structure
  • the first pixel circuit connected to the first light-emitting element through the first group of conductive lines is the pixel circuit of the first structure
  • the first pixel circuit connected to the first light-emitting element through the second group of conductive lines It is the pixel circuit of the second structure.
  • the first light emitting element is configured to emit green light
  • one of the second light emitting element and the third light emitting element is configured to emit red light
  • the second light emitting element and the third light emitting element are configured to emit red light.
  • Another configuration of the light emitting element is to emit blue light.
  • the length of the first set of conductive lines is less than a length cutoff value
  • the length of the second set of conductive lines is greater than or equal to the length cutoff value.
  • the ratio of the length cutoff value to the maximum length of the second set of conductive lines is about 0.25 to 0.35.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.
  • the display device further includes: a photosensitive sensor located on one side of the display substrate, and an orthographic projection of the photosensitive sensor on the display substrate intersects with the second display area of the display substrate stack.
  • an embodiment of the present disclosure provides a method for fabricating a display substrate, including: forming a plurality of second-type pixel circuits in a first display area of a base substrate, and forming a plurality of second-area light-emitting elements in the second display area , the first display area is located on at least one side of the second display area.
  • the plurality of pixel circuits of the second type include a plurality of pixel circuits of the first structure and a plurality of pixel circuits of the second structure; at least one pixel circuit of the plurality of pixel circuits of the first structure and a plurality of second regions At least one of the light-emitting elements is connected by a first set of conductive lines.
  • At least one pixel circuit of the plurality of pixel circuits of the second structure is connected to at least one light-emitting element of the plurality of second-area light-emitting elements through a second group of conductive lines.
  • the length of the second group of conductive lines is greater than the length of the first group of conductive lines.
  • FIG. 1A is a schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 1B is another schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 3 is another schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • 4A to 4F are schematic partial plan views of a display substrate according to at least one embodiment of the disclosure.
  • 5A is a partial schematic diagram of a row of light-emitting elements located in a second display area and a second-type pixel circuit connected thereto of a display substrate of at least one embodiment of the disclosure;
  • 5B is a schematic diagram of capacitances of light-emitting elements that emit light of different colors in the same row of light-emitting elements located in the second display area of the display substrate according to at least one embodiment of the disclosure;
  • 6A is a schematic diagram of a pixel circuit of a first structure according to at least one embodiment of the disclosure.
  • 6B is a schematic diagram of a pixel circuit of a second structure according to at least one embodiment of the disclosure.
  • 6C is an operation timing diagram of the pixel circuit of the first structure and the pixel circuit of the second structure according to at least one embodiment of the disclosure;
  • FIG. 7A is a schematic plan view of a pixel circuit of a first structure according to at least one embodiment of the disclosure.
  • FIG. 7B is a schematic partial cross-sectional view along the P-P direction in FIG. 7A;
  • FIG. 7C is a schematic diagram of a pixel circuit of a first structure after forming a semiconductor layer according to at least one embodiment of the disclosure.
  • FIG. 7D is a schematic diagram of a pixel circuit of a first structure after forming a first conductive layer according to at least one embodiment of the disclosure
  • FIG. 7E is a schematic diagram of a pixel circuit of a first structure after forming a second conductive layer according to at least one embodiment of the disclosure.
  • 7F is a schematic diagram of the pixel circuit of the first structure after forming the fourth insulating layer according to at least one embodiment of the disclosure.
  • 7G is a schematic diagram of a pixel circuit of a first structure after forming a third conductive layer according to at least one embodiment of the disclosure.
  • 7H is a schematic diagram of a pixel circuit of the first structure after forming a fifth insulating layer according to at least one embodiment of the disclosure.
  • FIG. 7I is a schematic diagram of a pixel circuit of a first structure after forming a fourth conductive layer according to at least one embodiment of the disclosure.
  • FIG. 8A is a schematic plan view of a pixel circuit of a second structure according to at least one embodiment of the disclosure.
  • FIG. 8B is a schematic partial cross-sectional view along the Q-Q direction in FIG. 8A;
  • 8C is a schematic diagram of a pixel circuit of a second structure after forming a semiconductor layer according to at least one embodiment of the disclosure.
  • 8D is a schematic diagram of a pixel circuit of a second structure after forming a first conductive layer according to at least one embodiment of the disclosure
  • 8E is a schematic diagram of a pixel circuit of a second structure after forming a second conductive layer according to at least one embodiment of the disclosure.
  • 8F is a schematic diagram of a pixel circuit of a second structure after forming a fourth insulating layer according to at least one embodiment of the present disclosure
  • 8G is a schematic diagram of a pixel circuit of a second structure after forming a third conductive layer according to at least one embodiment of the disclosure.
  • 8H is a schematic diagram of a pixel circuit of a second structure after forming a fifth insulating layer according to at least one embodiment of the disclosure.
  • 8I is a schematic diagram of a pixel circuit of a second structure after forming a fourth conductive layer according to at least one embodiment of the disclosure.
  • FIG. 9 is another partial schematic diagram of a row of light-emitting elements located in a second display area and a second-type pixel circuit connected thereto of a display substrate of at least one embodiment of the disclosure;
  • FIG. 10 is another partial schematic diagram of a row of light-emitting elements located in a second display area and a second-type pixel circuit connected thereto of a display substrate of at least one embodiment of the disclosure;
  • FIG. 11 is another schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a display device according to at least one embodiment of the disclosure.
  • ordinal numbers such as “first”, “second”, and “third” are provided to avoid confusion of constituent elements, and are not intended to be limited in quantity.
  • a “plurality” in this disclosure means a quantity of two or more.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed e.g., it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate, a drain, and a source.
  • a transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of “source” and “drain” may be interchanged with each other. Therefore, in this specification, “source” and “drain” may be interchanged with each other.
  • connection includes a case where constituent elements are connected together by means of an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • Embodiments of the present disclosure provide a display substrate, including: a base substrate having a first display area and a second display area, a plurality of second area light-emitting elements located in the second display area, and a plurality of second area light-emitting elements located in the first display area Two types of pixel circuits.
  • the first display area is located on at least one side of the second display area.
  • the plurality of second-type pixel circuits include a plurality of pixel circuits of the first structure and a plurality of pixel circuits of the second structure.
  • At least one pixel circuit in the plurality of pixel circuits of the first structure and at least one light-emitting element in the plurality of second-area light-emitting elements are connected by a first group of conductive lines. At least one pixel circuit of the plurality of pixel circuits of the second structure is connected to at least one light-emitting element of the plurality of second area light-emitting elements through a second group of conductive lines. The length of the second set of conductive lines is greater than the length of the first set of conductive lines.
  • the first display area may be a non-light-transmitting display area
  • the second display area may be a light-transmitting display area.
  • the pixel circuits that drive the light-emitting elements in the second display area are arranged in the first display area but not in the second display area, which can ensure better light transmittance in the second display area.
  • the display defects caused by the difference in the length of the conductive lines can be reduced or eliminated. That is, when designing the second type pixel circuit connected to the second area light emitting element, the length of the conductive line connecting the second area light emitting element and the second type pixel circuit is considered.
  • the pixel circuit of the first structure is connected to the first initial signal line
  • the pixel circuit of the second structure is connected to the first initial signal line and the second initial signal line.
  • the first initial signal line and the second initial signal line provide different initial signals.
  • the pixel circuit of the first structure adopts a single initial signal design
  • the pixel circuit of the second structure adopts a double initial signal design.
  • the display substrate further includes: a plurality of first area light emitting elements and a plurality of first type pixel circuits located in the first display area. At least one first-type pixel circuit of the plurality of first-type pixel circuits is connected to at least one first-area light-emitting element of the plurality of first-area light-emitting elements, and the at least one first-type pixel circuit is in the The orthographic projection on the base substrate at least partially overlaps the orthographic projection of the at least one first area light-emitting element on the base substrate.
  • the plurality of pixel circuits of the first type are all pixel circuits of the first structure.
  • the pixel circuit of the first structure includes: a driving transistor, a first reset transistor, and a second reset transistor.
  • the gate of the first reset transistor is connected to the first reset control line
  • the first pole of the first reset transistor is connected to the gate of the driving transistor
  • the second pole of the first reset transistor is connected to the first initial signal line.
  • the gate of the second reset transistor is connected to the second reset control line
  • the first electrode of the second reset transistor is connected to the first electrode of the light emitting element
  • the second electrode of the second reset transistor is connected to the first initial signal line.
  • the pixel circuit of the first structure may adopt the design of a single initial signal.
  • the pixel circuit of the second structure includes: a driving transistor, a first reset transistor, and a second reset transistor.
  • the gate of the first reset transistor is connected to the first reset control line
  • the first pole of the first reset transistor is connected to the gate of the driving transistor
  • the second pole of the first reset transistor is connected to the first initial signal line.
  • the gate of the second reset transistor is connected to the second reset control line
  • the first electrode of the second reset transistor is connected to the first electrode of the light emitting element
  • the second electrode of the second reset transistor is connected to the second initial signal line.
  • the second initial signal provided by the second initial signal line is different from the first initial signal provided by the first initial signal line.
  • the pixel circuit of the second structure can adopt the design of two initial signals.
  • the first initial signal provided by the first initial signal line is a constant voltage signal.
  • the first initial signal may be about -3V.
  • this embodiment does not limit this.
  • the second initial signal provided by the second initial signal line may be a constant voltage signal, and the second initial signal may be greater than the first initial signal provided by the first initial signal line.
  • the first initial signal may be about -3.0V
  • the second initial signal may be about -2.0V, -1.5V, -1.0V, or -0.5V.
  • this embodiment does not limit this.
  • the magnitude of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is proportional to the length of the second group of conductive lines connected to the pixel circuit of the second structure .
  • the greater the length of the second group of conductive lines connected to the pixel circuits of the second structure the greater the second initial signal provided by the second initial signal lines connected to the pixel circuits of the second structure.
  • this embodiment does not limit this.
  • the pixel circuit of the first structure or the pixel circuit of the second structure may further include: a data writing transistor, a threshold compensation transistor, a first light emission control transistor and a second light emission control transistor.
  • the gate of the data writing transistor is connected to the scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor.
  • the gate of the threshold compensation transistor is connected to the scan line, the first electrode of the threshold compensation transistor is connected to the gate of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor.
  • the gate of the first light-emitting control transistor is connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power line, and the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor.
  • the gate of the second light-emitting control transistor is connected to the light-emitting control line, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element.
  • the pixel circuit of the first structure and the pixel circuit of the second structure may both have a 7T1C structure, that is, include 7 transistors and 1 capacitor.
  • this embodiment does not limit this.
  • the pixel circuits of the first configuration and the pixel circuits of the second configuration may include other numbers of transistors and capacitors.
  • the display substrate in a plane perpendicular to the display substrate, includes at least: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer disposed on the base substrate.
  • the semiconductor layer includes at least: active layers of a plurality of transistors.
  • the first conductive layer at least includes: gates of a plurality of transistors and first electrodes of storage capacitors, scan lines, light emission control lines, first reset control lines and second reset control lines.
  • the second conductive layer at least includes: a second electrode of the storage capacitor, a first initial signal line, and a second initial signal line.
  • the third conductive layer at least includes: first and second electrodes of a plurality of transistors, a first power supply line, and a data line.
  • the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the first structure may have an integrated structure; the second reset transistor of the pixel circuit of the nth row of the first structure and the nth reset transistor The active layers of the first reset transistors of the pixel circuits in the +1 row may have an integrated structure, and n is a positive integer.
  • the active layers of the first reset transistor and the second reset transistor of the pixel circuit of the second structure are of an integrated structure; the active layer of the second reset transistor of the pixel circuit of the nth row of the second structure is of an integrated structure; It is not connected to the active layer of the first reset transistor of the pixel circuit in the n+1th row, and n is a positive integer.
  • the third conductive layer includes: a second electrode of the second reset transistor of the pixel circuit of the second structure, and a second electrode of the second reset transistor of the pixel circuit of the first structure.
  • the second electrode of the second reset transistor of the pixel circuit of the second structure is connected to the second initial signal line through the via hole.
  • the second pole of the second reset transistor of the pixel circuit of the first structure is not connected to the second initial signal line.
  • the first set of conductive lines and the second set of conductive lines employ transparent conductive materials, eg, indium tin oxide (ITO), indium zinc oxide (IZO), and the like.
  • transparent conductive materials eg, indium tin oxide (ITO), indium zinc oxide (IZO), and the like.
  • the plurality of second-type pixel circuits are spaced apart among the plurality of first-type pixel circuits.
  • the size of any pixel circuit in the first direction is smaller than the size of the first area light-emitting element in the first direction .
  • the difference between the size of the first area light-emitting element in the first direction and the size of any pixel circuit in the first direction may be about 4 microns. However, this embodiment does not limit this.
  • the plurality of second area light emitting elements includes a plurality of groups of second area light emitting elements, the second area light emitting elements in each group are arranged along the first direction, and the plurality of groups of second area light emitting elements are arranged along the second Orientation arrangement.
  • the plurality of second type pixel circuits include a plurality of groups of second type pixel circuits, the second type pixel circuits in each group are arranged along the first direction, and the plurality of groups of second type pixel circuits are arranged along the second direction.
  • the plurality of second area light-emitting elements at least include: a plurality of first light-emitting elements, a plurality of second light-emitting elements, and a plurality of third light-emitting elements.
  • the plurality of second-type pixel circuits include: a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits.
  • the plurality of first light-emitting elements are connected to the plurality of first pixel circuits
  • the plurality of second light-emitting elements are connected to the plurality of second pixel circuits
  • the plurality of third light-emitting elements are connected to the plurality of third pixel circuits.
  • the plurality of first pixel circuits connected to the plurality of first light-emitting elements are smaller than the plurality of second pixels connected to the plurality of second light-emitting elements
  • Each of the circuits is closer to the second display area and is closer to the second display area than each of the plurality of third pixel circuits connected to the plurality of third light emitting elements.
  • the second pixel circuit connected to the second light-emitting element through the second group of conductive lines is a pixel circuit of the second structure
  • the third pixel circuit connected to the third light-emitting element through the second group of conductive lines It is the pixel circuit of the second structure
  • the first pixel circuit connected to the first light-emitting element through the first group of conductive lines is the pixel circuit of the first structure
  • the first pixel circuit connected to the first light-emitting element through the second group of conductive lines It is the pixel circuit of the second structure.
  • this embodiment does not limit this.
  • the first light emitting element is configured to emit green light
  • one of the second light emitting element and the third light emitting element is configured to emit red light
  • the other of the second light emitting element and the third light emitting element is configured to emit light Blu-ray.
  • this embodiment does not limit this.
  • the length of the first set of conductive lines is less than the length cutoff value, and the length of the second set of conductive lines is greater than or equal to the length cutoff value.
  • the ratio of the length cutoff value to the maximum length of the second set of conductive lines is about 0.25 to 0.35.
  • the maximum length of the second set of conductive lines is about 10,000 microns, and the length cutoff value is about 3,000 microns.
  • this embodiment does not limit this.
  • the lengths of the first group of conductive lines and the second group of conductive lines vary with the size of the display substrate.
  • FIG. 1A is a schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • FIG. 1B is another schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate includes a first display region R1 and a second display region R2, and the first display region R1 may be located on at least one side of the second display region R2.
  • the first display region R1 partially surrounds the second display region R2.
  • the second display area R2 shown in FIG. 1A is located at the top middle of the display substrate, one side of the second display area R2 is adjacent to the peripheral area, and the other three sides are surrounded by the first display area R1.
  • this embodiment does not limit this.
  • the second display region R2 may be located at other positions such as the upper left corner or the upper right corner of the display substrate.
  • the first display area R1 may surround the second display area R2 .
  • the second display region R2 may be located in the middle position of the upper half of the display substrate.
  • the setting position of the second display area R2 can be determined as required.
  • the first display region R1 and the second display region R2 may both be rectangular, such as rounded rectangles.
  • this embodiment does not limit this.
  • the first display region R1 may be in other shapes such as a circle or an ellipse
  • the second display region R2 may be in other shapes such as a circle, a quadrangle or a pentagon.
  • the shapes of the first display area R1 and the second display area R2 may be the same or different.
  • the second display area R2 may be a light-transmitting display area.
  • the orthographic projection of hardware such as a photosensitive sensor (eg, a camera) on the display substrate may be located in the second display region R2 of the display substrate.
  • the display substrate of this example does not need to be punched, and on the premise of ensuring the practicability of the display substrate, a true full screen can be made possible.
  • the display substrate may include a plurality of sub-pixels disposed on the base substrate, and at least one sub-pixel includes a pixel circuit and a light-emitting element.
  • the pixel circuit is configured to drive the light-emitting element.
  • the pixel circuit is configured to provide a drive current to drive the light-emitting element to emit light.
  • the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit.
  • OLED organic light-emitting diode
  • the color of the light-emitting element can be determined as required.
  • the pixel circuits driving the light-emitting elements of the second display area R2 may be arranged in the second display area R2.
  • FIG. 2 is a schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • the display substrate includes: a plurality of first-type pixel circuits 10 , a plurality of second-type pixel circuits 20 and a plurality of first-region light-emitting elements located in the first display region R1 30, and a plurality of second region light emitting elements 40 located in the second display region R2.
  • a plurality of second-type pixel circuits 20 may be distributed among a plurality of first-type pixel circuits 10 at intervals.
  • At least one first-type pixel circuit 10 of the plurality of first-type pixel circuits 10 may be connected to at least one first-area light-emitting element 30 of the plurality of first-area light-emitting elements 30, and the at least one first-type pixel circuit 10 is
  • the orthographic projection on the base substrate and the orthographic projection of the at least one first region light emitting element 30 on the base substrate may at least partially overlap.
  • the at least one first-type pixel circuit 10 may be configured to provide a driving signal to the connected first-area light-emitting element 30 to drive the first-area light-emitting element 30 to emit light.
  • At least one second type pixel circuit 20 of the plurality of second type pixel circuits 20 may be connected to at least one second area light emitting element 40 of the plurality of second area light emitting elements 40 through the conductive line L, the at least one second type light emitting element 40
  • the pixel circuit 20 may be configured to provide a driving signal to the connected second area light emitting element 40 to drive the second area light emitting element 40 to emit light. Since the second-area light-emitting element 40 and the second-type pixel circuit 20 are located in different regions, the orthographic projection of the at least one second-type pixel circuit 20 on the base substrate is the same as the orthographic projection of the at least one second-area light-emitting element 40 on the base substrate. Projections do not overlap.
  • the first display area R1 may be set as a non-transmissive display area
  • the second display area R2 may be set as a light-transmissive display area. That is, the first display region R1 of the present exemplary embodiment cannot transmit light, and the second display region R2 can transmit light. In this way, there is no need to perform hole-digging processing on the display substrate, and required hardware structures such as photosensitive sensors can be directly disposed in the second display area R2, which lays a solid foundation for the realization of a true full screen.
  • the second display region R2 since the second display region R2 only includes light-emitting elements and does not include pixel circuits, it can also ensure that the light transmittance of the second display region R2 is good.
  • the first area light-emitting element 30 may be referred to as an in-situ light-emitting element
  • the first type of pixel circuit 10 may be referred to as an in-situ pixel circuit
  • the second type of pixel circuit 20 may be referred to as an ex-situ pixel circuit .
  • the second-area light-emitting element 40 and the second-type pixel circuit 20 connected to the second-area light-emitting element 40 are located in the same row. That is, the light-emitting signals of the second-area light-emitting elements 40 come from the second-type pixel circuits 20 in the same row. For example, pixel circuits of sub-pixels in the same row are connected to the same gate line.
  • the second type pixel circuit 20 is connected to the second area light emitting element 40 through a conductive line L.
  • the conductive line L can be made of transparent conductive material.
  • the conductive line L can be made of conductive oxide material.
  • the conductive oxide material may include, but is not limited to, indium tin oxide (ITO).
  • ITO indium tin oxide
  • One end of the conductive line L is connected to the second type pixel circuit 20 , and the other end of the conductive line L is connected to the second area light-emitting element 40 .
  • the conductive lines L extend from the first display region R1 to the second display region R2 .
  • FIG. 3 is another schematic structural diagram of a display substrate according to at least one embodiment of the disclosure.
  • the first display region R1 includes not only a plurality of pixel units, but also a plurality of columns of second-type pixel circuits, and the second display region R2 only includes a plurality of second-region light-emitting elements .
  • at least one pixel unit may include: a red sub-pixel R, two green sub-pixels G1 and G2, and one blue sub-pixel B, and the red sub-pixel R and the blue sub-pixel B are located in the same column, and the two The green sub-pixels G1 and G2 are located in the same column.
  • one pixel unit may also include other colors and other numbers of sub-pixels, and the arrangement of the plurality of sub-pixels is not limited to the structure shown in FIG. 3 .
  • a pixel unit may include three sub-pixels (eg, a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), and the three sub-pixels may be arranged in a horizontal juxtaposition, a vertical juxtaposition, or a fringe pattern .
  • one pixel unit may include four sub-pixels (one red sub-pixel R, one blue sub-pixel B, one green sub-pixel G, and one white sub-pixel), and the four sub-pixels may be arranged in a horizontal, vertical or square manner arrangement.
  • the present disclosure is not limited herein.
  • FIGS. 4A and 4B are schematic partial plan views of a display substrate according to at least one embodiment of the disclosure.
  • the second display region R2 is a light-transmitting display region
  • the first display region R1 is a non-light-transmitting display region.
  • the density of the second area light emitting elements 40 of the second display area R2 may be approximately equal to the density of the first area light emitting elements 30 of the first display area R1 . That is, the resolution of the second display region R2 may be approximately the same as the resolution of the first display region R1. However, this embodiment does not limit this.
  • the density of the second area light emitting elements 40 may be greater or less than the density of the first area light emitting elements 30 . That is, the resolution of the second display region R2 may be larger or smaller than that of the first display region R1.
  • the light-emitting area of the second-area light-emitting element 40 is smaller than the light-emitting area of the first-area light-emitting element 30 . That is, the light emitting area of the first area light emitting element 30 is larger than the light emitting area of the second area light emitting element 40 .
  • the light emitting area of the second area light emitting element 40 and the light emitting area of the first area light emitting element 30 are shown by dotted lines in FIG. 4C .
  • the light emitting area of the light emitting element may correspond to the area of the opening of the pixel definition layer.
  • a light-transmitting region R0 is provided between adjacent second-region light-emitting elements 40 .
  • a plurality of light-transmitting regions R0 are connected to each other to form continuous light-transmitting regions separated by a plurality of second-region light-emitting elements 40 .
  • the conductive lines L can be made of transparent conductive materials to improve the light transmittance of the light-transmitting region R0 as much as possible.
  • the regions in the second display region R2 other than the second region light-emitting element 40 may be all light-transmitting regions.
  • setting the second type pixel in the first display region R1 , can be obtained by reducing the size of the first type pixel circuit 10 in the first direction X circuit 20 area.
  • the size of the first type pixel circuit 10 in the first direction X may be smaller than the size of the first area light emitting element 30 in the first direction X.
  • the first direction X is, for example, the row direction, but not limited thereto. In other embodiments, the first direction X may be a column direction. This exemplary embodiment is described by taking the first direction X as the row direction as an example.
  • the size of the first type pixel circuit 10 and the second type pixel circuit 20 in the first direction X may be the same, and the size of each pixel circuit in the first direction X is the same as the size of the first area light emitting element 30 in the first direction
  • the dimensions on X may differ by about 4 micrometers ( ⁇ m).
  • the size of each pixel circuit in the second direction Y is substantially the same as the size of the first area light-emitting element 30 in the second direction Y.
  • the first direction X is perpendicular to the second direction Y.
  • FIG. 4D to 4F are schematic partial structural views of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 4D shows a schematic structural diagram of the light-emitting element in the first region of the first display region R1 .
  • 4E shows a schematic diagram of a partial structure (including only pixel circuits) of the first display area R1 in FIG. 4A
  • FIG. 4F shows a schematic diagram of a partial structure (including only light-emitting elements) of the first display area R1 in FIG. 4A .
  • the size of the pixel circuit in the first direction X is smaller than the size of the light-emitting element in the first direction X, so that the second direction from right to left can be made.
  • the pixel circuits of the column and the ninth column are not connected to any first area light emitting elements 30, and belong to multi-column pixel circuits, which can be used as the second type pixel circuits 20 to connect the second area light emitting elements 40 in the second display area R2.
  • any one of the light-emitting elements 30 in the first region may be one of four types of light-emitting elements RG1BG2 in total.
  • the first electrode E1 of the first region light-emitting element 30 may be connected to the first transfer electrode CE1 of the first type pixel circuit 10 through the second transfer electrode CE2.
  • R represents a light emitting element that emits red light
  • G1 represents a light emitting element that emits green light
  • B represents a light emitting element that emits blue light
  • G2 represents a light emitting element that emits green light.
  • At least one second type pixel circuit 20 may have a first transfer electrode
  • at least one second area light emitting element 40 may have a second transfer electrode.
  • connecting the at least one second-type pixel circuit 20 and the at least one second-area light-emitting element 40 through the conductive line L may include: the conductive line L connects the first transfer electrode of the at least one second-type pixel circuit 20 and the at least one first transfer electrode respectively.
  • the second transition electrode of the two-area light-emitting element 40 may be located on a straight line. However, this embodiment does not limit this.
  • G includes Gl or G2.
  • a repeating unit RP includes two Gs arranged in the second direction Y and R and B respectively arranged on both sides of the two Gs in the first direction X, wherein R and G It forms a pixel, and borrows B from another repeating unit adjacent to it to form a virtual pixel for display, B and G form a pixel, and borrows R from another repeating unit adjacent to it to form a virtual pixel to form a virtual pixel. to display.
  • this embodiment does not limit this.
  • 5A is a partial schematic diagram of a row of light-emitting elements located in a second display area and a second-type pixel circuit connected thereto of a display substrate of at least one embodiment of the disclosure.
  • 5B is a schematic diagram illustrating capacitances of light-emitting elements emitting light of different colors in the same row of light-emitting elements in the second display area of the display substrate according to at least one embodiment of the disclosure.
  • the second display area R2 is symmetrical about the central axis in the first direction X. As shown in FIG. FIG. 5A only illustrates the connection relationship between a row of light-emitting elements in the left half of the second display region R2 and the second-type pixel circuit in the first display region R1.
  • the plurality of second-region light-emitting elements 40 include: a plurality of first light-emitting elements 41 , a plurality of second light-emitting elements 42 , a plurality of Three light-emitting elements 43 and a plurality of fourth light-emitting elements 44 .
  • the first light-emitting element 41 is configured to emit light of a first color
  • the second light-emitting element 42 is configured to emit light of a second color
  • the third light-emitting element 43 is configured to emit light of a third color
  • the fourth light-emitting element 44 is configured to emit light of a fourth color Light.
  • the first color light and the fourth color light are both green (G) light
  • the second color light is red (R) light
  • the third color light is blue (B) light.
  • this embodiment does not limit this.
  • the plurality of second-type pixel circuits 20 include: a plurality of first pixel circuits 21 , a plurality of second pixel circuits 22 , a plurality of Three pixel circuits 23 and a plurality of fourth pixel circuits 24 .
  • the plurality of first light-emitting elements 41 and the plurality of first pixel circuits 21 are connected by a plurality of first conductive lines La, and the plurality of second light-emitting elements 42 and the plurality of second pixel circuits 22 are connected by a plurality of second conductive lines Lb,
  • the plurality of third light emitting elements 43 and the plurality of third pixel circuits 23 are connected by a plurality of third conductive lines Lc, and the plurality of fourth light emitting elements 44 and the plurality of fourth pixel circuits 24 are connected by a plurality of fourth conductive lines Ld.
  • a first light-emitting element 41 and a first pixel circuit 21 are connected by a first conductive line La
  • a second light-emitting element 42 and a second pixel circuit 22 are connected by a second conductive line Lb
  • a third light-emitting element 42 is connected with a second conductive line Lb.
  • the element 43 is connected to a third pixel circuit 23 through a third conductive line Lc
  • a fourth light-emitting element 44 is connected to a fourth pixel circuit 24 through a fourth conductive line Ld.
  • this embodiment does not limit this.
  • At least one of the first conductive line La, the second conductive line Lb, the third conductive line Lc, and the fourth conductive line Ld may be made of a transparent conductive material.
  • the plurality of second area light emitting elements 40 in the second display region R2 include a plurality of groups of second area light emitting elements 40, and the second area light emitting elements 40 in each group are arranged along the first direction X, The plurality of groups of second area light emitting elements 40 are arranged along the second direction Y.
  • the plurality of second-type pixel circuits 20 include a plurality of groups of second-type pixel circuits 20, the second-type pixel circuits 20 in each group are arranged along the first direction X, and the plurality of groups of second-type pixel circuits 20 are arranged along the second direction Y cloth.
  • the first type pixel circuits 10 are arranged between the second type pixel circuits 20 in each group.
  • a set of second area light emitting elements 40 and a set of second type pixel circuits 20 are illustrated in FIG. 5A .
  • a group of the second area light emitting elements 40 may be a row of the second area light emitting elements 40
  • a group of the second type pixel circuits 20 may be a row of the second type pixel circuits 20 .
  • a row of light-emitting elements may refer to that the pixel circuits connected to the row of light-emitting elements are all connected to the same gate line (eg, scan line).
  • a row of pixel circuits may refer to that the row of pixel circuits are all connected to the same gate line.
  • a row of sub-pixels may refer to that the pixel circuits connected to the row of sub-pixels are all connected to the same gate line.
  • this embodiment does not limit this.
  • a plurality of first pixel circuits connected to a plurality of first light-emitting elements 41 21 is closer to the second display region R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light emitting elements 42 and is closer to the plurality of third pixel circuits 22 connected to the plurality of third light emitting elements 43
  • Each of the 23 is closer to the second display area R2.
  • the plurality of fourth pixel circuits 24 connected to the plurality of fourth light emitting elements 44 are closer to the second display region R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light emitting elements 42
  • Each of the plurality of third pixel circuits 23 connected to the plurality of third light emitting elements 43 is closer to the second display region R2.
  • the order of G priority is adopted, that is, the second-type pixel circuit connected to the green-emitting light-emitting element is preferentially close to the second display Area R2 is arranged.
  • two adjacent second-type pixel circuits 20 are arranged between two adjacent ones. At least one of the plurality of pixel circuits 10 of the first type.
  • At least one set of the second In the area light-emitting element 40 and at least one group of second-type pixel circuits 20, the plurality of second pixel circuits 22 connected to the plurality of second conductive lines Lb and the plurality of third pixel circuits connected to the plurality of third conductive lines Lc 23 Alternate settings.
  • this embodiment does not limit this.
  • the plurality of fourth pixel circuits 24 connected to the plurality of fourth conductive lines Ld and the plurality of first pixel circuits 21 connected to the plurality of first conductive lines La are alternately arranged .
  • this embodiment does not limit this.
  • the abscissa represents the position of the second display region R2 of the display substrate in the first direction X
  • the ordinate represents the electrical power of the conductive line connected to the light-emitting element at the position.
  • the capacitance of the conductive line connected to the light-emitting element that emits green light is the smallest, and as shown in the left half of FIG. 5B , the capacitance of the conductive line connected to the light-emitting element that emits green light shows a gradual increase.
  • the difference in capacitance between the two conductive lines connected to the adjacent green-emitting light-emitting elements is smaller. Since the structure of the second display region R2 of the display substrate is symmetrically arranged with respect to the first direction X, the right half shown in FIG. 5B will not be described in detail. As shown in FIG. 5B, the capacitance of the conductive wire connected to the green light-emitting element is smaller than that of the conductive wire connected to the red light-emitting element, and the capacitance of the conductive wire connected to the green light-emitting element is smaller than that of the conductive wire connected to the green light-emitting element.
  • the capacitance of the conductive wire connected to the blue-emitting light-emitting element As shown in FIG. 5B , the capacitance of the conductive wire connected to the red-emitting light-emitting element showed a gradually increasing trend, and the capacitance of the conductive wire connected to the blue-emitting light-emitting element showed a gradually increasing trend, and the capacitance of the conductive wire connected to the red-emitting light-emitting element showed a gradually increasing trend.
  • the capacitance of the conductive wire connected to the light-emitting element is not much different from that of the conductive wire connected to the blue-emitting light-emitting element.
  • the plurality of second-type pixel circuits 20 in the first display region R1 include: a plurality of pixel circuits of the first structure and a plurality of pixel circuits of the second structure.
  • the plurality of first type pixel circuits 10 in the first display region R1 are all pixel circuits of the first structure.
  • the pixel circuits of the first structure and the pixel circuits of the second structure may both be 7T1C structures, ie, including 7 transistors and 1 capacitor. However, this embodiment does not limit this.
  • the pixel circuit of the first structure and the pixel circuit of the second structure of the present exemplary embodiment will be described in detail below.
  • 6A is a schematic diagram of a pixel circuit of a first structure according to at least one embodiment of the disclosure.
  • 6B is a schematic diagram of a pixel circuit of a second structure according to at least one embodiment of the disclosure.
  • 6C is an operation timing diagram of the pixel circuit of the first structure and the pixel circuit of the second structure according to at least one embodiment of the disclosure.
  • the pixel circuit of the first structure and the pixel circuit of the second structure each include six switching transistors ( T1 , T2 , T4 to T7 ), one driving transistor T3 and a storage capacitor Cst.
  • the six switching transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7.
  • the light-emitting element EL includes a first electrode E1, a second electrode E2, and an organic light-emitting layer located between the first electrode E1 and the second electrode E2.
  • the first electrode E1 may be an anode
  • the second electrode E2 may be a cathode.
  • the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.
  • the drive transistor and the six switch transistors may include P-type transistors and N-type transistors.
  • the driving transistor and the six switching transistors may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide).
  • the low temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • Low Temperature Polycrystalline Oxide display substrate, can take advantage of both, can achieve low frequency drive, can reduce power consumption, can improve display quality.
  • the display substrate includes scan lines GT, data lines DT, first power supply lines PL1 , second power supply lines PL2 , light emission control lines EML, and first initial signal lines INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2.
  • the first power supply line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power supply line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit
  • the first voltage signal VDD is greater than The second voltage signal VSS.
  • the scan line GT is configured to provide the pixel circuit with the scan signal SCAN
  • the data line DT is configured to provide the pixel circuit with the data signal DATA
  • the light emission control line EML is configured to provide the pixel circuit with the light emission control signal EM
  • the first reset control line RST1 is configured to provide the pixel circuit with the light emission control signal EM.
  • the pixel circuit provides a first reset control signal RESET1
  • the second reset control line RST2 is configured to provide a scan signal SCAN to the pixel circuit.
  • the second reset control line RST2 may be connected to the scan line GT to be input with the scan signal SCAN.
  • this embodiment does not limit this.
  • the second reset control signal line RST2 may be input with the second reset control signal RESET2.
  • the first reset control line RST1 may be connected to the scan line GT of the pixel circuit of the n-1th row to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1 (n) is the same as the scan signal SCAN(n-1). In this way, the signal lines of the display substrate can be reduced, and a narrow frame of the display substrate can be realized.
  • the first initial signal line INIT1 is configured to provide the first initial signal Vinit1 to the pixel circuit.
  • the second initial signal line INIT2 is configured to supply the second initial signal Vinit2 to the pixel circuit.
  • the first initial signal Vinit1 and the second initial signal Vinit2 may be constant voltage signals, and their magnitudes may be between, for example, but not limited to, the first voltage signal VDD and the second voltage signal VSS.
  • the first initial signal Vinit1 and the second initial signal Vinit2 may be less than or equal to the second voltage signal VSS.
  • the driving transistor T3 is electrically connected to the light-emitting element EL, and is connected to the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the first Under the control of two voltage signals VSS and other signals, a driving current is output to drive the light-emitting element EL to emit light.
  • the gate of the data writing transistor T4 is connected to the scan line GT, the first pole of the data writing transistor T4 is connected to the data line DT, and the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T3.
  • the gate of the threshold compensation transistor T2 is connected to the scan line GT, the first electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is connected to the second electrode of the driving transistor T3.
  • the gate of the first light-emitting control transistor T5 is connected to the light-emitting control line EML, the first electrode of the first light-emitting control transistor T5 is connected to the first power line PL1, and the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T3.
  • the gate of the second light-emitting control transistor T6 is connected to the light-emitting control line EML, the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode of the second light-emitting control transistor T6 is connected to the light-emitting element EL
  • the first pole E1 is connected.
  • the first reset transistor T1 is connected to the gate of the driving transistor T3, and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is connected to the first pole E1 of the light-emitting element EL, and is configured to reset the light-emitting element EL.
  • the first electrode E1 is reset.
  • the gate of the first reset transistor T1 is connected to the first reset control line RST1, the first pole of the first reset transistor T1 is connected to the first initial signal line INIT1, and the second pole of the first reset transistor T1 is connected to the gate of the driving transistor T3.
  • the gate of the second reset transistor T7 is connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is connected to the first initial signal line INIT1, and the second electrode of the second reset transistor T7 is connected to the first electrode of the light-emitting element EL.
  • One pole E1 is connected.
  • the first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, and the second node N2 is the first light-emitting control transistor T5, the data writing transistor T4 and The connection point of the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light emission control transistor T6, the fourth node N4 is the second light emission control transistor T6, the second reset transistor T7 and the light emission Connection point for element EL.
  • the operation process of the pixel circuit of the first structure illustrated in FIG. 6A will be described below with reference to FIG. 6C .
  • the description is given by taking as an example that the plurality of transistors included in the pixel circuit of the first structure are all P-type transistors.
  • the working process of the pixel circuit of the first structure includes: a first stage A1, a second stage A2 and a third stage A3.
  • the first stage A1 is called the reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low level signal, so that the first reset transistor T1 is turned on, and the first initial signal Vinit1 provided by the first initial signal line INIT1 is provided to the first node N1,
  • the first node N1 is initialized to clear the original data voltage in the storage capacitor Cst.
  • the scan signal SCAN provided by the scan line GT is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the data writing transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the first light-emitting control transistor T5, and the third
  • the two light-emitting control transistors T6 and the second reset transistor T7 are turned off. At this stage, the light-emitting element EL does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the scan signal SCAN provided by the scan line GT is a low-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 and the light-emitting control signal EM provided by the light-emitting control line EML are both high-level signals
  • the data line DT outputs data signal DATA.
  • the driving transistor T3 since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on.
  • the scan signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7.
  • the threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DT is provided to the first node through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2.
  • a node N2 and the difference between the data voltage Vdata output by the data line DT and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the second electrode of the storage capacitor Cst (ie the first node N1) is Vdata-
  • the second reset transistor T7 is turned on, so that the first initial signal Vinit1 provided by the first initial signal line INIT1 is provided to the first electrode E1 of the light-emitting element EL, initializes (resets) the first electrode E1 of the light-emitting element EL, and clears the first electrode E1 of the light-emitting element EL.
  • the internal pre-stored voltage completes initialization and ensures that the light-emitting element EL does not emit light.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, so that the first reset transistor T1 is turned off.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, so that the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage.
  • the light emission control signal EM provided by the light emission control signal line EML is a low level signal
  • the scan signal SCAN provided by the scan line GT and the first reset control signal RESET1 provided by the first reset control line RST1 are high level signals.
  • the light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, so that the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the first voltage signal VDD output by the first power supply line PL1 passes through the turned on.
  • the first light emitting control transistor T5, the driving transistor T3 and the second light emitting control transistor T6 supply a driving voltage to the first electrode E1 of the light emitting element EL to drive the light emitting element EL to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the first node N1 is Vdata-
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3
  • Vth is the driving transistor T3
  • the threshold voltage of , Vdata is the data voltage output by the data line DT, and VDD is the first voltage signal output by the first power line PL1.
  • the pixel circuit of the first structure of this embodiment can better compensate the threshold voltage of the driving transistor T3.
  • the gate of the second reset transistor T7 is connected to the second reset control line RST2, and the first electrode of the second reset transistor T7 is connected to the second reset control line RST2.
  • the second initial signal line INIT2 is connected, and the second electrode of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element EL.
  • the first initial signal line INIT1 and the second initial signal line INIT2 are insulated from each other, and are configured to input signals, respectively.
  • the second reset transistor T7 is turned on, so that the second initial signal line INIT2
  • the provided second initial signal Vinit2 is provided to the first electrode E1 of the light-emitting element EL to initialize (reset) the first electrode E1 of the light-emitting element EL, clear its internal pre-stored voltage, complete the initialization, and ensure that the light-emitting element EL does not emit light.
  • the pixel circuit of the first structure adopts a single initial signal design, wherein the first reset transistor and the second reset transistor receive the same initial signal (ie, the first initial signal); the pixel circuit of the second structure A two initial signal design is adopted, wherein the first reset transistor and the second reset transistor receive different initial signals (ie, the first reset transistor receives the first initial signal, and the second reset transistor receives the second initial signal).
  • the second-type pixel circuits and the light-emitting elements in the second area are connected by conductive lines, and the length of the conductive lines is too large.
  • the capacitance of the fourth node N4 in the pixel circuit shown is too large, so that after the fourth node N4 is reset to the second initial signal Vinit2 in the second stage A2, it takes a long time to charge to reach the predetermined potential.
  • the turn-on duration of the light-emitting elements in the second area will be affected, resulting in a dark display, resulting in a difference in display brightness between the first display area R1 and the second display area R2.
  • the charging amount of the fourth node N4 can be effectively reduced. Under the condition of a certain current, the amount of electricity is proportional to the duration. Therefore, by increasing the second initial signal Vinit2, the charging duration can be effectively reduced, so that the charging duration can be effectively reduced. Increase the light-emitting time and improve the brightness difference caused by too long conductive lines. However, increasing the second initial signal Vinit2 has a risk of leakage of the light-emitting element EL.
  • the second initial signal Vinit2 provides the anode voltage of the light-emitting element EL
  • the second voltage signal VSS provides the cathode voltage of the light-emitting element EL
  • the structure of the pixel circuit is designed in consideration of the length of the conductive line, so as to improve the display effect.
  • the first type pixel circuit in the first display area and the light-emitting element in the first area do not need to be connected by conductive lines.
  • the first type pixel circuit can be designed with a single initial signal, for example , the first type of pixel circuit may be the pixel circuit of the first structure shown in FIG. 6A .
  • the second-type pixel circuits in the first display area and the second-area light-emitting elements in the second display area are connected by conductive wires, and the conductive wires connected to the different second-area light-emitting elements are connected by conductive wires.
  • the length boundary value of the conductive line that causes the brightness difference between the first display area and the second display area can be determined through simulation, and the conductive line connecting the light-emitting element in the second area and the pixel circuit of the second type can be divided into first One set of conductive lines and a second set of conductive lines.
  • the length of the first group of conductive lines may be less than the length cutoff value.
  • the length of the second group of conductive lines may be greater than or equal to the length threshold, which will cause a difference in brightness between the first display area and the second display area.
  • the second-type pixel circuit connected to the light-emitting element in the second region through the first group of conductive lines can be designed with a single initial signal, for example, the pixel circuit of the first structure shown in FIG. 6A to avoid increasing the second initial signal Vinit2 This causes the light-emitting element to be easily turned on.
  • the second type of pixel circuit connected to the second region light emitting element through the second group of conductive lines may adopt a dual initial signal design, for example, may be the pixel circuit of the second structure shown in FIG. 6B .
  • the light-emitting element in the second area connected to the second group of conductive lines may be difficult to turn on due to the excessive capacitance of the conductive lines.
  • the charging time of the fourth node N4 can be reduced and poor display can be improved.
  • a constant second initialization signal can be provided, and then the length cutoff value can be determined according to the influence of the brightness of the display substrate on the length of the conductive line.
  • the capacitance of the conductive line can be calculated, and the length cutoff value can be determined based on the display effect at low gray levels.
  • this embodiment does not limit this.
  • the length of the first conductive line La connecting the first light-emitting element 41 and the first pixel circuit 21 is about 100 ⁇ m to 6000 ⁇ m
  • the length of the second conductive line Lb of the pixel circuit 22 is about 5000 ⁇ m to 10000 ⁇ m
  • the length of the third conductive line Lc connecting the third light emitting element 43 and the third pixel circuit 23 is about 5000 ⁇ m to 10000 ⁇ m
  • the length of the fourth conductive line Ld of the fourth pixel circuit 24 is about 100 ⁇ m to 6000 ⁇ m.
  • the cut-off value of the length of the conductive line obtained by the simulation may be about 3000 ⁇ m.
  • the conductive lines with a length of less than 3000 ⁇ m may be referred to as the first group of conductive lines, and the conductive lines with a length of greater than or equal to 3000 ⁇ m may be referred to as the second group of conductive lines.
  • the second-type pixel circuits connected to the first group of conductive lines may be pixel circuits of the first structure, and the second-type pixel circuits connected to the second group of conductive lines may be pixel circuits of the second structure.
  • adjusting the structure of the pixel circuit can avoid the situation of poor display caused by the increase of the second initial signal when the capacitance of the conductive lines is small, and the capacitance of the conductive lines can be adjusted. In larger cases, display defects are improved by boosting the second initial signal.
  • This embodiment does not limit the length of the conductive wire. When the size of the display substrate changes, the length boundary value and the length of the conductive lines will also change.
  • the first pixel circuit 21 connected to the first conductive line La with a length of about 100 ⁇ m to 3000 ⁇ m may be a pixel circuit of the first structure, and the length of about 3000 ⁇ m to 6000 ⁇ m
  • the first pixel circuit 21 connected by the first conductive line La may be a pixel circuit of the second structure; the second pixel circuit 22 connected by the second conductive line Lb and the third pixel circuit 23 connected by the third conductive line Lc are both.
  • the fourth pixel circuit 24 connected to the fourth conductive line Ld with a length of about 100 ⁇ m to 3000 ⁇ m can be a pixel circuit of the first structure, and the fourth conductive line Ld with a length of about 3000 ⁇ m to 6000 ⁇ m is connected.
  • the connected fourth pixel circuit 24 may be a pixel circuit of the second structure.
  • the first region light-emitting element 30 and the first type pixel circuit 10 do not need to be connected by conductive lines, and the first type pixel circuit 10 may be both
  • the pixel circuit of the first structure avoids the situation that the light-emitting element is easily turned on by raising the second initial signal.
  • the first initial signal Vinit1 provided by the first initial signal line INIT1 may be a constant voltage signal, for example, about -3V.
  • the second initial signal Vinit2 provided by the second initial signal line INIT2 may be a constant voltage signal and is greater than the first initial signal Vinit1.
  • the second initial signal Vinit2 may be greater than -3V, such as about -2V, -1.5V, -1V or -0.5V.
  • the plurality of second initial signal lines INIT2 may provide different second initial signals.
  • the magnitude of the second initial signal provided by the second initial signal line connected to the pixel circuit of the second structure is the same as that of the second group of conductive lines connected between the pixel circuit of the second structure and the light-emitting element of the second area.
  • the length is proportional. For example, the longer the second group of conductive lines connected to the pixel circuit of the second structure, the larger the second initial signal provided by the second initial signal line connected to the pixel circuit.
  • this embodiment does not limit this.
  • FIG. 7A is a schematic plan view of a pixel circuit of a first structure according to at least one embodiment of the disclosure.
  • FIG. 7B is a schematic partial cross-sectional view along the P-P direction in FIG. 7A .
  • the first direction X may be the direction (horizontal direction) of sub-pixel rows
  • the second direction Y may be the direction (vertical direction) of sub-pixel columns.
  • the display substrate in a plane parallel to the display substrate, is provided with scan lines GT, light emission control lines EML, first reset control lines RST1 , first initial signal lines INIT1 , The second initial signal line INIT2, the first power supply line PL1, the data line DT and the pixel circuit of the first structure.
  • the pixel circuit of the first structure may include a plurality of transistors and a storage capacitor Cst, and the plurality of transistors may include a driving transistor T3, a data writing transistor T4, a threshold compensation transistor T2, a first reset transistor T1, a second reset transistor T7, and a first light emitting transistor.
  • the control transistor T5 and the second light emission control transistor T6 in a plane parallel to the display substrate.
  • a plurality of transistors T1 to T7 of the pixel circuit of the nth row, a second reset transistor T7' of the pixel circuit of the n-1th row, and a first reset transistor T1' of the pixel circuit of the n+1th row are illustrated in FIG. 7A .
  • the first reset transistor T1 of the pixel circuit in the nth row is connected to the first reset control line RST1(n), and the first reset control line RST1(n) is connected with the pixel circuit in the n ⁇ 1th row.
  • the line GT(n-1) is connected, and the second reset transistor T7' of the pixel circuit in the n-1th row is connected with the first reset control line RST1(n) to realize the input scan signal SCAN(n-1).
  • the first reset transistor T1' of the pixel circuit in the n+1th row is connected to the first reset control line RST1(n+1), and the first reset control line RST1(n+1) is connected to the scan line connected to the pixel circuit in the nth row GT(n) is connected, and the second reset transistor T7 of the pixel circuit in the nth row is connected to the first reset control line RST1(n+1) to realize the input scan signal SCAN(n).
  • the display substrate in a plane perpendicular to the display substrate, may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base substrate 50 conductive layer.
  • the semiconductor layer may include active layers of multiple transistors.
  • the first conductive layer may include a scan line GT, a first reset control line RST1, an emission control line EML, a first electrode of the storage capacitor Cst, and gates of a plurality of transistors.
  • the second conductive layer may include a first initial signal line INIT1, a second initial signal line INIT2, a second electrode of the storage capacitor Cst, and a first shield electrode BK.
  • the third conductive layer may include a first power line PL1, a data line DT, and first and second electrodes of a plurality of transistors.
  • the fourth conductive layer may include: a second shield electrode SE and a first connection electrode CE1.
  • the display substrate may include a first insulating layer 51 , a second insulating layer 52 , a third insulating layer 53 , a fourth insulating layer 54 and a fifth insulating layer 55 .
  • the first insulating layer 51 is provided between the base substrate 50 and the semiconductor layer
  • the second insulating layer 52 is provided between the semiconductor layer and the first conductive layer
  • the third insulating layer 53 is provided between the first conductive layer and the second conductive layer
  • the fourth insulating layer 54 is provided between the second conductive layer and the third conductive layer
  • the fifth insulating layer 55 is provided between the third conductive layer and the fourth conductive layer.
  • the first insulating layer 51 , the second insulating layer 52 , the third insulating layer 53 and the fourth insulating layer 54 may be inorganic insulating layers, and the fifth insulating layer 55 may be an organic insulating layer.
  • this embodiment does not limit this.
  • the semiconductor layer of at least one sub-pixel may include: a first active layer T10 of a first reset transistor T1 , a second active layer T20 of a threshold compensation transistor T2 , a driving The third active layer T30 of the transistor T3, the fourth active layer T40 of the data writing transistor T4, the fifth active layer T50 of the first light emission control transistor T5, the sixth active layer T60 of the second light emission control transistor T6 and the seventh active layer T70 of the second reset transistor T7.
  • the first active layer T10 to the seventh active layer T70 are integral structures connected to each other.
  • the first active layer T10 has an integrated structure with the seventh active layer T70' of the pixel circuits in the previous row, and the seventh active layer T10 has an integrated structure with the first active layer T10' of the pixel circuits in the next row.
  • the shapes of the first active layers T10 and T10 ′ may be in the shape of “n”, the shape of the second active layer T20 may be in the shape of “7”, and the third active layer T10 ′ may be in the shape of “7”.
  • the shape of the active layer T30 may be in the shape of a "ji"
  • the shape of the fourth active layer T40 may be in the shape of a "1”
  • the fifth active layer T50, the sixth active layer T06, the seventh active layers T70 and T70' can be in the shape of an "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region T10 - 1 of the first active layer T10 simultaneously serves as the first region of the seventh active layer T70 ′ of the seventh transistor T7 ′ of the pixel circuit in the previous row
  • the The second region T10-2 of an active layer T10 simultaneously serves as the first region T20-1 of the second active layer T20
  • the first region T30-1 of the third active layer T30 simultaneously serves as the first region T30-1 of the fourth active layer T40.
  • the second region T40-2 and the second region T50-2 of the fifth active layer T50, and the second region T30-2 of the third active layer T30 simultaneously serve as the second region T20-2 and the second region T20-2 of the second active layer T20.
  • the first region T60-1 of the sixth active layer T60 and the second region T60-2 of the sixth active layer T60 simultaneously serve as the second region T70-2 of the seventh active layer T70.
  • the first conductive layer at least includes: a first electrode Cst-1 of the storage capacitor Cst, a scan line GT extending along the first direction X, an emission control line EML, a first Reset control lines RST1(n) and RST1(n+1).
  • the first electrode Cst-1 of the storage capacitor Cst may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first electrode Cst-1 on the base substrate and the third active layer T30 of the driving transistor T3 The orthographic projections on the base substrate have overlapping regions.
  • the first electrode Cst-1 of the storage capacitor Cst also serves as the gate T33 of the driving transistor T3.
  • the scan line GT, the gate T43 of the data writing transistor T4, and the gate T23 of the threshold compensation transistor T2 may have an integrated structure.
  • the light emitting control line EML, the gate T53 of the first light emitting control transistor T5, and the gate T63 of the second light emitting control transistor T6 may be integrated.
  • the first reset control line RST1(n), the gate T13 of the first reset transistor T1, and the gate T73' of the second reset transistor T7' of the pixel circuit in the previous row may be an integral structure.
  • the first reset control line RST1(n+1), the gate T73 of the second reset transistor T7, and the gate T13' of the first reset transistor T1' of the pixel circuit of the next row may have an integrated structure.
  • the second conductive layer at least includes: a first initial signal line INIT1, a second initial signal line INIT2, a second electrode Cst-2 of the storage capacitor Cst, and a first shield electrode BK.
  • the first initial signal line INIT1 and the second initial signal line INIT2 extend along the first direction X and are located on one side of the scan line GT.
  • the second electrode Cst-2 of the storage capacitor Cst is located between the scan line GT and the light emission control line EML.
  • the second electrode Cst-2 is provided with an opening OP1, the opening OP1 exposes the third insulating layer 53 covering the first electrode Cst-1, and the orthographic projection of the first electrode Cst-1 on the base substrate includes the opening OP1 on the substrate Orthographic projection on the base substrate.
  • the opening OP1 is configured to accommodate the first via hole H1 formed later, the first via hole H1 is located in the opening OP1 and exposes the first electrode Cst-1, so that the first via hole H1 of the subsequently formed first reset transistor T1 is The diode is connected to the first electrode Cst-1.
  • the first shield electrode BK is located on a side of the scan line GT away from the storage capacitor Cst.
  • the first shielding electrode BK is configured to shield the influence of the data voltage jump on the key nodes, so as to prevent the data voltage jump from affecting the potential of the key nodes of the pixel circuit and improve the display effect.
  • FIG. 7F is a schematic diagram of the pixel circuit of the first structure after forming the fourth insulating layer according to at least one embodiment of the disclosure.
  • a first via hole H1 a plurality of second via holes V1 to V4 , and a plurality of third via holes K1 to K8 are formed on the fourth insulating layer 54 .
  • the fourth insulating layer 54 and the third insulating layer 53 in the first via hole H1 are etched away, exposing the surface of the first conductive layer.
  • the fourth insulating layer 54 in the plurality of second via holes V1 to V4 is etched away to expose the surface of the second conductive layer.
  • the fourth insulating layer 54 , the third insulating layer 53 and the second insulating layer 52 in the plurality of third vias K1 to K8 are etched away to expose the surface of the semiconductor layer.
  • the third conductive layer may include: a data line DT, a first power line PL1 , a first pole T11 of the first reset transistor T1 , a first electrode of the second reset transistor T7 pole T71, the first pole T21 of the threshold compensation transistor T2, the second pole T62 of the second light-emitting control transistor T6, the first pole T11' of the first reset transistor T1' of the pixel circuit of the next row, the second pole of the pixel circuit of the previous row The first pole T71' of the reset transistor T7'.
  • the data line DT and the first power supply line PL1 extend along the second direction Y.
  • the data line DT is connected to the first region T40 - 1 of the fourth active layer T40 of the data writing transistor T4 through the third via hole K2 .
  • the first power line PL1 is connected to the second electrode Cst-2 of the storage capacitor Cst through the second via hole V1, is connected to the first shield electrode BK through the second via hole V2, and is connected to the first light-emitting control transistor through the third via hole K3
  • the first regions T50-1 of the fifth active layer T50 of T5 are connected.
  • the first electrode T21 of the threshold compensation transistor T2 is connected to the first electrode Cst-1 of the storage capacitor Cst through the first via hole H1, and is connected to the first region of the second active layer T20 of the threshold compensation transistor T2 through the third via hole K1 T20-1 is connected.
  • the second electrode T62 of the second light-emitting control transistor T6 is connected to the second region T60-2 of the sixth active layer T60 of the second light-emitting control transistor T6 through the third via hole K4.
  • the first pole T11 of the first reset transistor T1 is connected to the first initial signal line INIT1 through the second via hole V3, and is connected to the first region T10- of the first active layer T10 of the first reset transistor T1 through the third via hole K5. 1 is connected.
  • the first electrode T71 of the second reset transistor T7 is connected to the first region T70-1 of the seventh active layer T70 of the second reset transistor T7 through the third via hole K8.
  • the first pole T11' of the first reset transistor T1' of the pixel circuit in the next row is connected to the first initial signal line INIT1 through the second via hole V4, and is connected to the first active line of the first reset transistor T1' through the third via hole K7.
  • the first regions of the layer T10' are connected.
  • the first electrode T71' of the second reset transistor T7' of the pixel circuit in the upper row is connected to the first region of the first active layer T80' of the second reset transistor T7' through the third via hole K6.
  • the first pole of the second reset transistor is not connected to the second initial signal line INIT2. Since the active layers of the second reset transistor of the pixel circuit of the current row and the first reset transistor of the pixel circuit of the next row are of an integrated structure, and the first reset transistor of the pixel circuit of the next row is connected to the first initial signal line INIT1, the present invention is realized.
  • the second reset transistor of the row pixel circuit is also connected to the first initial signal line INIT1.
  • FIG. 7H is a schematic diagram of a pixel circuit of the first structure after forming a fifth insulating layer according to at least one embodiment of the disclosure.
  • a plurality of fourth via holes F1 to F2 are formed on the fifth insulating layer 55 .
  • the fifth insulating layer 55 in the plurality of fourth via holes F1 to F2 is removed to expose the surface of the third conductive layer.
  • the fourth conductive layer includes at least: a second shield electrode SE and a first transition electrode CE1.
  • the first transfer electrode CE1 is connected to the second electrode T62 of the second light-emitting control transistor T6 through the fourth via hole F1.
  • the first transition electrode CE1 can be directly connected to the first area light-emitting element, or connected to the second transition electrode of the first area light-emitting element, or connected to the second transition electrode of the second area light-emitting element through a conductive wire .
  • the second shield electrode SE is connected to the first power line PL1 through the fourth via hole F2.
  • the orthographic projection of the second shield electrode SE on the base substrate partially overlaps the orthographic projection of the driving transistor T3 on the base substrate.
  • the second shielding electrode SE is configured to shield the influence of the conductive line on the driving transistor T3 to improve the display effect.
  • FIG. 8A is a schematic plan view of a pixel circuit of a second structure according to at least one embodiment of the disclosure.
  • FIG. 8B is a schematic partial cross-sectional view along the Q-Q direction in FIG. 8A .
  • 8C is a schematic diagram of a pixel circuit of a second structure after forming a semiconductor layer according to at least one embodiment of the disclosure.
  • 8D is a schematic diagram of a pixel circuit of a second structure after forming a first conductive layer according to at least one embodiment of the disclosure.
  • 8E is a schematic diagram of a pixel circuit of a second structure after forming a second conductive layer according to at least one embodiment of the disclosure.
  • 8F is a schematic diagram of the pixel circuit of the second structure after forming the fourth insulating layer according to at least one embodiment of the disclosure.
  • 8G is a schematic diagram of a pixel circuit of the second structure after forming the third conductive layer according to at least one embodiment of the disclosure.
  • 8H is a schematic diagram of a pixel circuit of the second structure after forming the fifth insulating layer according to at least one embodiment of the disclosure.
  • 8I is a schematic diagram of a pixel circuit of a second structure after forming a fourth conductive layer according to at least one embodiment of the disclosure.
  • a plurality of transistors T1 to T7 of the pixel circuit of the nth row, a second reset transistor T7' of the pixel circuit of the n-1th row, and a first reset transistor T1' of the pixel circuit of the n+1th row are illustrated in FIG. 8A.
  • the first reset transistor T1 of the pixel circuit in the nth row is connected to the first reset control line RST1(n), and the first reset control line RST1(n) is connected with the pixel circuit in the n ⁇ 1th row.
  • the line GT(n-1) is connected, and the second reset transistor T7' of the pixel circuit in the n-1th row is connected with the first reset control line RST1(n) to realize the input scan signal SCAN(n-1).
  • the first reset transistor T1' of the pixel circuit in the n+1th row is connected to the first reset control line RST1(n+1), and the first reset control line RST1(n+1) is connected to the scan line connected to the pixel circuit in the nth row GT(n) is connected, and the second reset transistor T7 of the pixel circuit in the nth row is connected to the first reset control line RST1(n+1) to realize the input scan signal SCAN(n).
  • the seventh active layer T70 is an interconnected one-piece structure.
  • the first active layer T10 of the pixel circuit in this row is independent from the seventh active layer T70' of the pixel circuit in the previous row, and the seventh active layer T10 of the pixel circuit in the row is independent from the first active layer T10 of the pixel circuit in the next row. 'Independent.
  • the first electrode T71 of the second reset transistor T7 of the pixel circuit of the second structure is connected to the second initial signal line INIT2 through the second via hole V5, and is connected to the seventh active layer of the second reset transistor T7 through the third via hole K8
  • the first area T70-1 of the T70 is connected.
  • the first electrode T11 of the first reset transistor T1 of the pixel circuit of the second structure is connected to the first initial signal line INIT1 through the second via hole V3, and is connected to the first active layer of the first reset transistor T1 through the third via hole K5
  • the first area T10-1 of T10 is connected.
  • the first pole T71' of the second reset transistor T7' of the pixel circuit in the previous row is connected to the second initial signal line INIT2 through the second via V6, and is connected to the seventh active line of the second reset transistor T7' through the third via K6.
  • the first regions of the layer T70' are connected.
  • the first pole T11' of the first reset transistor T1' of the pixel circuit in the next row is connected to the first initial signal line INIT1 through the second via hole V4, and is connected to the first active line of the first reset transistor T1' through the third via hole K7.
  • the first regions of the layer T10' are connected.
  • the active layer of the second reset transistor of the pixel circuit of the first structure is connected to the active layer of the first reset transistor of the pixel circuit of the next row, so as to realize that the second reset transistor is connected to the first initial signal line, the active layer of the second reset transistor of the pixel circuit of the second structure is disconnected from the active layer of the first reset transistor of the pixel circuit of the next row, and the active layer of the second reset transistor is directly connected to the second initial signal line , the second reset transistor is connected to the second initial signal line.
  • the layout design of the pixel circuit provided by this exemplary embodiment can realize the spaced arrangement of the pixel circuit of the first type and the pixel circuit of the second type on the base substrate.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • A's orthographic projection includes B's orthographic projection means that the boundary of B's orthographic projection falls within the boundary of A's orthographic projection, or the boundary of A's orthographic projection overlaps with the boundary of B's orthographic projection.
  • the manufacturing process of the display substrate may include the following operations.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the base substrate 50 , and patterning the semiconductor film through a patterning process to form a first insulating film covering the base substrate 50 .
  • An insulating layer 51, and a semiconductor layer disposed on the first insulating layer 51, are shown in FIGS. 7B and 8B.
  • the display substrate includes a first insulating layer 51 disposed on the base substrate 50 and a semiconductor layer disposed on the first insulating layer 51, and the semiconductor layer may include active layers of a plurality of transistors of the pixel circuit, As shown in Figure 7C and Figure 8C.
  • the active layer of the second reset transistor of the pixel circuit of the first structure is integrally formed with the active layer of the first reset transistor of the adjacent pixel circuit, and the second structure of the pixel circuit of the second structure has an integrated structure.
  • the active layer of the reset transistor is independent of the active layer of the first reset transistor of the adjacent pixel circuit.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the base substrate 50 on which the foregoing pattern is formed, and performing a patterning process on the first metal film patterning to form a second insulating layer 52 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 52 .
  • the first conductive layer pattern at least includes: a first reset control line RST1 , a scan line GT, an emission control line EML, and a first electrode Cst-1 of the storage capacitor Cst.
  • the first reset control line RST1, the scan line GT and the light emission control line EML extend along the first direction X, and the first electrode Cst-1 of the storage capacitor Cst is located between the scan line GT and the light emission control line EML.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layer may be used as a shield to conduct conductorization processing on the semiconductor layer, and the semiconductor layer in the region shielded by the first conductive layer forms the channels of the plurality of transistors
  • the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer T10 to the seventh active layer T70 are both conductorized.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate 50 on which the foregoing pattern is formed, and patterning the second metal film by a patterning process , forming a third insulating layer 53 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 53 .
  • the second conductive layer pattern at least includes: a first initial signal line INIT1 , a second initial signal line INIT2 , a second electrode Cst-2 of the storage capacitor Cst, and a first shield electrode BK.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the base substrate 50 on which the foregoing pattern is formed, and patterning the fourth insulating film by a patterning process to form a covering The fourth insulating layer 54 of the two conductive layers. As shown in FIG. 7F and FIG. 8F , a plurality of first via holes, a plurality of second via holes and a plurality of third via holes are provided on the fourth insulating layer.
  • the fourth insulating layer 54 and the third insulating layer 53 in the plurality of first vias are etched away, exposing the surface of the first conductive layer, and the fourth insulating layer 54 in the plurality of second vias is etched away , the surface of the second conductive layer is exposed, the fourth insulating layer 54 , the third insulating layer 53 and the second insulating layer 52 in the plurality of third vias are etched away to expose the surface of the semiconductor layer.
  • forming the third conductive layer may include: depositing a third metal thin film on the base substrate 50 on which the aforementioned patterns are formed, patterning the third metal thin film by a patterning process, and forming a third metal thin film disposed on the first The third conductive layer on the four insulating layers 54 .
  • the third conductive layer at least includes: a data line DT, a first power line PL1 , and first and second electrodes of a plurality of transistors.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the first pole T71 of the second reset transistor T7 of the pixel circuit of the first structure is not connected to the second initial signal line INIT2.
  • the first electrode T71 of the second reset transistor T7 of the pixel circuit of the second structure is connected to the second initial signal line INIT2 through the second via hole V5 .
  • forming the fifth insulating layer pattern may include: coating a flat film on the base substrate 50 on which the foregoing pattern is formed, and patterning the flat film by a patterning process to form a covering third conductive layer the fifth insulating layer 55 .
  • a plurality of fourth via holes F1 and F2 are formed on the fifth insulating layer 55 .
  • the fifth insulating layer 55 in the plurality of fourth via holes is removed to expose the surface of the third conductive layer.
  • the fifth insulating layer 55 may be referred to as a flat layer.
  • forming the fourth conductive layer pattern may include: depositing a fourth metal thin film on the base substrate 50 on which the foregoing pattern is formed, patterning the fourth metal thin film by a patterning process, and forming a The fourth conductive layer on the fifth insulating layer 55 .
  • the fourth conductive layer pattern at least includes: a first connection electrode CE1 and a second shield electrode SE.
  • the second shield electrode SE is connected to the first power line PL1 through the fourth via hole F2, and the first connection electrode CE1 is connected to the second electrode T62 of the second light-emitting control transistor T6 through the fourth via hole F1.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD1) layer.
  • the subsequent fabrication process may include: forming a conductive line layer.
  • the plurality of conductive lines connecting the second type pixel circuit of the first display area and the second area light emitting element of the second display area may be of the same layer structure.
  • Forming the conductive line layer may include: coating a flat film on the base substrate on which the fourth conductive layer is formed, and patterning the flat film by a patterning process to form a sixth insulating layer covering the fourth conductive layer; then, depositing a transparent For the conductive film, the transparent conductive film is patterned by a patterning process to form a conductive line layer disposed on the sixth insulating layer.
  • the first connection electrode CE1 of the second type pixel circuit of the first display region R1 is connected to a conductive line, and the conductive line may extend from the first display region R1 to the second display region R2 so as to connect with the second region of the second display region R2 Light emitting element connection.
  • the plurality of conductive lines connecting the second type pixel circuits of the first display region R1 and the second region light emitting elements of the second display region R2 may be of a hetero-layer structure.
  • at least one conductive line may be formed by connecting a plurality of conductive line segments located in different conductive line layers.
  • the preparation process after forming the conductive line layer may include: forming a flat layer covering the conductive line layer; depositing a transparent conductive film, and patterning the transparent conductive film by a patterning process to form a flat layer disposed on the flat layer.
  • the organic light-emitting layer is formed by vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of organic materials, and the third encapsulation layer can be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light-emitting element.
  • the base substrate 50 may be a flexible base substrate, or may be a rigid base substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible base substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, etc.
  • the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the base substrate
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/ Mo et al.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may be any one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). or multiple layers, which can be a single layer, multiple layers or composite layers.
  • the first insulating layer 51 is called a buffer layer, which is used to improve the water and oxygen resistance of the base substrate
  • the second insulating layer 52 and the third insulating layer 53 are called gate insulating (GI) layers
  • the fourth insulating layer 54 It is called an interlayer insulating (ILD) layer.
  • the flat layer may use an organic material.
  • the transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the active layer can use polysilicon (p-Si), that is, this embodiment is suitable for LTPS thin film transistors. However, this embodiment does not limit this.
  • the transistors in the pixel circuit of the first structure and the pixel circuit of the second structure may both use oxide thin film transistors.
  • the structure of the display substrate and the manufacturing process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs.
  • the pixel circuit of the first structure and the pixel circuit of the second structure may include other numbers of transistors and storage capacitors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, or the number of transistors is less than seven.
  • the first reset transistor T1 and the threshold compensation transistor T2 may use oxide thin film transistors, and the remaining transistors (ie, the driving transistor T3, the data writing transistor The input transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6 and the second reset transistor T7) can be low-temperature polysilicon thin film transistors, thereby forming an LTPO display substrate.
  • the active layers of the first reset transistor T1 and the threshold compensation transistor T2 may be of the same layer structure, and the active layers of the remaining transistors may be of a different layer structure.
  • the active layers of the second reset transistor T7 of the pixel circuit with the first structure in the nth row and the active layers of the first reset transistor T1 of the pixel circuit in the n+1th row are of different-layer structures and isolated from each other.
  • the reset transistor T7 and the first reset transistor T1 are each connected to the first initial signal line INIT1.
  • the active layers of the second reset transistor T7 of the pixel circuit of the nth row with the second structure and the active layers of the first reset transistor T1 of the pixel circuit of the n+1th row are of different-layer structures and isolated from each other.
  • the reset transistor T7 is connected to the second initial signal line INIT2, and the first reset transistor T1 is connected to the first initial signal line INIT1.
  • the first reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors, and the remaining transistors may be P-type transistors.
  • the display substrate may include: a first semiconductor layer, a first conductive layer, a second semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the base substrate Floor.
  • the first semiconductor layer at least includes: active layers of a plurality of P-type transistors; the first conductive layer at least includes: gates of a plurality of P-type transistors, a first electrode of a storage capacitor, a scan line, a light-emitting control line, and a first electrode of a storage capacitor.
  • the second semiconductor layer at least includes: a plurality of active layers of N-type transistors; the second conductive layer at least includes: a second electrode of a storage capacitor and a first reset control line; the third conductive layer at least includes: a plurality of The first electrode and the second electrode of each transistor, the first power supply line, the data line, the first initial signal line and the second initial signal line; the fourth conductive layer at least includes: a first connection electrode.
  • An insulating layer is arranged between adjacent semiconductor layers and conductive layers, and an insulating layer is arranged between adjacent conductive layers. However, this embodiment does not limit this.
  • FIG. 9 is another schematic diagram of a row of light-emitting elements located in a second display area and a second-type pixel circuit connected thereto of a display substrate of at least one embodiment of the disclosure.
  • the second display area R2 is symmetrical about the central axis in the first direction X. As shown in FIG. FIG. 9 only illustrates the connection relationship between a row of light-emitting elements in the left half of the second display area R2 and the second type pixel circuit in the first display area R1.
  • the plurality of second-region light-emitting elements 40 include: a plurality of first light-emitting elements 41 , a plurality of second light-emitting elements 42 , a plurality of Three light-emitting elements 43 .
  • the first light-emitting element 41 is configured to emit light of the first color
  • the second light-emitting element 42 is configured to emit light of the second color
  • the third light-emitting element 43 is configured to emit light of the third color.
  • the first color light is green (G) light
  • the second color light is red (R) light
  • the third color light is blue (B) light.
  • this embodiment does not limit this.
  • the plurality of second-type pixel circuits 20 include: a plurality of first pixel circuits 21 , a plurality of second pixel circuits 22 , a plurality of Three pixel circuit 23 .
  • the plurality of first light-emitting elements 41 and the plurality of first pixel circuits 21 are connected by a plurality of first conductive lines La
  • the plurality of second light-emitting elements 42 and the plurality of second pixel circuits 22 are connected by a plurality of second conductive lines Lb
  • the plurality of third light emitting elements 43 and the plurality of third pixel circuits 23 are connected by a plurality of third conductive lines Lc.
  • a first light-emitting element 41 and a first pixel circuit 21 are connected by a first conductive line La
  • a second light-emitting element 42 and a second pixel circuit 22 are connected by a second conductive line Lb
  • a third light-emitting element 42 is connected with a second conductive line Lb.
  • the element 43 is connected to a third pixel circuit 23 through a third conductive line Lc.
  • this embodiment does not limit this.
  • a plurality of first pixel circuits connected to a plurality of first light-emitting elements 41 21 is closer to the second display region R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light emitting elements 42 and is closer to the plurality of third pixel circuits 22 connected to the plurality of third light emitting elements 43
  • Each of the 23 is closer to the second display area R2.
  • the second pixel circuit 22 connected to the second light-emitting element 42 and the third pixel circuit 23 connected to the third light-emitting element 43 may both be pixel circuits of the second structure, the second conductive line Lb and the third The lengths of the conductive lines Lc are all greater than the length threshold.
  • the first pixel circuit 21 connected to the first conductive line La whose length is less than the length threshold value may be the pixel circuit of the first structure, and the first pixel circuit 21 connected to the first conductive line La whose length is greater than the length threshold value may be the first pixel circuit 21.
  • Two-structure pixel circuit does not limit this.
  • the first conductive line La connected to the first conductive line La is a pixel circuit of the first structure, the pixel circuit connected to the second conductive line Lb and the third conductive line Lc whose length is less than the length demarcation value is the pixel circuit of the first structure, and the second conductive line whose length is greater than the length demarcation value.
  • the pixel circuit connected to the line Lb and the third conductive line Lc is a pixel circuit of the second structure.
  • FIG. 10 is another schematic diagram of a row of light-emitting elements located in a second display area and a second-type pixel circuit connected thereto of a display substrate of at least one embodiment of the disclosure.
  • the second display area R2 is symmetrical about the central axis in the first direction X.
  • FIG. 9 only illustrates the connection relationship between a row of light-emitting elements in the left half of the second display area R2 and the second type pixel circuit in the first display area R1.
  • a plurality of second pixel circuits connected to a plurality of second light-emitting elements 42 22.
  • a plurality of first pixel circuits 21 connected to a plurality of first light-emitting elements 41 and a plurality of third pixel circuits 23 connected to a plurality of third light-emitting elements 43 are arranged alternately in sequence.
  • the first pixel circuit 21 connected to the first conductive line La with a length smaller than the length threshold may be a pixel circuit of the first structure, and the first pixel connected to the first conductive line La with a length greater than the length threshold
  • the circuit 21 may be a pixel circuit of the second structure.
  • the second pixel circuit 22 connected to the second conductive line Lb whose length is less than the length threshold may be the pixel circuit of the first structure, and the second pixel circuit 21 connected to the second conductive line Lb whose length is greater than the length threshold may be the first pixel circuit.
  • the third pixel circuit 23 connected to the third conductive line Lc whose length is less than the length threshold may be the pixel circuit of the first structure, and the third pixel circuit 23 connected to the third conductive line Lc whose length is greater than the length threshold may be the first pixel circuit.
  • FIG. 11 is a schematic diagram of a display substrate according to at least one embodiment of the disclosure.
  • the first display area R1 includes the auxiliary area Ra.
  • the area of the auxiliary area Ra may be smaller than that of the area of the first display area R1 excluding the auxiliary area Ra.
  • the auxiliary area Ra surrounds the second display area R2.
  • a plurality of first type pixel circuits and a plurality of first region light emitting elements are located in the first display region R1.
  • At least one first-type pixel circuit in the plurality of first-type pixel circuits may be connected to at least one first-area light-emitting element in the plurality of first-area light-emitting elements, and the at least one first-type pixel circuit is on the base substrate.
  • the orthographic projection and the orthographic projection of the at least one first area light-emitting element on the base substrate may at least partially overlap.
  • the first type of pixel circuit may be a pixel circuit of the first structure.
  • a plurality of second type pixel circuits are located in the auxiliary region Ra.
  • a plurality of second area light emitting elements are located in the second display area.
  • At least one second-type pixel circuit in the plurality of second-type pixel circuits may be connected with at least one second-area light-emitting element in the plurality of second-area light-emitting elements through a conductive line.
  • the second-type pixel circuit connected to the conductive line whose length is less than the length threshold value can be the pixel circuit of the first structure, and the second-type pixel circuit connected to the conductive line whose length is greater than or equal to the length threshold value can be the pixel circuit of the second structure circuit.
  • Embodiments of the present disclosure also provide a method for fabricating a display substrate, including: forming a plurality of second-type pixel circuits in a first display area of a base substrate, forming a plurality of second-area light-emitting elements in the second display area, and forming a first The display area is located on at least one side of the second display area.
  • the plurality of pixel circuits of the second type include a plurality of pixel circuits of the first structure and a plurality of pixel circuits of the second structure. At least one pixel circuit in the plurality of pixel circuits of the first structure and at least one light-emitting element in the plurality of second-area light-emitting elements are connected by a first group of conductive lines.
  • At least one pixel circuit of the plurality of pixel circuits of the second structure is connected to at least one light-emitting element of the plurality of second area light-emitting elements through a second group of conductive lines.
  • the length of the second set of conductive lines is greater than the length of the first set of conductive lines.
  • FIG. 12 is a schematic diagram of a display device according to at least one embodiment of the disclosure. As shown in FIG. 12 , this embodiment provides a display device 91 including the display substrate 910 of the previous embodiment.
  • the display substrate 910 may be an OLED display substrate.
  • the display device 91 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. However, this embodiment does not limit this.

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Abstract

一种显示基板，包括：具有第一显示区和第二显示区的衬底基板、位于第二显示区的多个第二区域发光元件、位于第一显示区的多个第二类型像素电路。第一显示区位于第二显示区的至少一侧。多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路。多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接。多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接。第二组导电线的长度大于第一组导电线的长度。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(TFT，Thin Film Transistor)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
屏下摄像头技术是为了提高显示装置的屏占比所提出的一种全新的技术。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及其制备方法、显示装置。
一方面，本公开实施例提供一种显示基板，包括：具有第一显示区和第二显示区的衬底基板、位于第二显示区的多个第二区域发光元件、位于第一显示区的多个第二类型像素电路。第一显示区位于第二显示区的至少一侧。多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路。多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接。多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接。第二组导电线的长度大于第一组导电线的长度。
在一些示例性实施方式中，所述第一结构的像素电路与第一初始信号线连接，所述第二结构的像素电路与第一初始信号线和第二初始信号线连接； 所述第一初始信号线和第二初始信号线提供不同的初始信号。
在一些示例性实施方式中，显示基板还包括：位于第一显示区的多个第一区域发光元件和多个第一类型像素电路。所述多个第一类型像素电路中的至少一个第一类型像素电路与所述多个第一区域发光元件中的至少一个第一区域发光元件连接，且所述至少一个第一类型像素电路在所述衬底基板上的正投影与所述至少一个第一区域发光元件在所述衬底基板上的正投影至少部分重叠。所述多个第一类型像素电路均为第一结构的像素电路。
在一些示例性实施方式中，所述第一结构的像素电路包括：驱动晶体管、第一复位晶体管和第二复位晶体管。所述第一复位晶体管的栅极与第一复位控制线连接，所述第一复位晶体管的第一极与驱动晶体管的栅极连接，所述第一复位晶体管的第二极与第一初始信号线连接。所述第二复位晶体管的栅极与第二复位控制线连接，所述第二复位晶体管的第一极与发光元件的第一极连接，所述第二复位晶体管的第二极与第一初始信号线连接。
在一些示例性实施方式中，所述第二结构的像素电路包括：驱动晶体管、第一复位晶体管和第二复位晶体管。所述第一复位晶体管的栅极与第一复位控制线连接，所述第一复位晶体管的第一极与驱动晶体管的栅极连接，所述第一复位晶体管的第二极与第一初始信号线连接。所述第二复位晶体管的栅极与第二复位控制线连接，所述第二复位晶体管的第一极与发光元件的第一极连接，所述第二复位晶体管的第二极与第二初始信号线连接。所述第二初始信号线提供的第二初始信号不同于所述第一初始信号线提供的第一初始信号。
在一些示例性实施方式中，所述第一初始信号线提供的第一初始信号为恒压信号。
在一些示例性实施方式中，所述第二初始信号线提供的第二初始信号为恒压信号，且所述第二初始信号大于第一初始信号线提供的第一初始信号。
在一些示例性实施方式中，所述第二结构的像素电路所连接的第二初始信号线提供的第二初始信号的大小，与所述第二结构的像素电路连接的第二组导电线的长度呈正比。
在一些示例性实施方式中，所述第一结构的像素电路或第二结构的像素 电路还包括：数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管和第二发光控制晶体管。所述数据写入晶体管的栅极与扫描线连接，所述数据写入晶体管的第一极与数据线连接，所述数据写入晶体管的第二极与驱动晶体管的第一极连接。所述阈值补偿晶体管的栅极与扫描线连接，所述阈值补偿晶体管的第一极与驱动晶体管的栅极连接，所述阈值补偿晶体管的第二极与驱动晶体管的第二极连接。所述第一发光控制晶体管的栅极与发光控制线连接，所述第一发光控制晶体管的第一极与第一电源线连接，所述第一发光控制晶体管的第二极与驱动晶体管的第一极连接。所述第二发光控制晶体管的栅极与发光控制线连接，所述第二发光控制晶体管的第一极与驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与发光元件的第一极连接。
在一些示例性实施方式中，在垂直于显示基板的平面内，所述显示基板至少包括：设置在衬底基板上的半导体层、第一导电层、第二导电层和第三导电层。所述半导体层至少包括：多个晶体管的有源层。所述第一导电层至少包括：多个晶体管的栅极和存储电容的第一电极、扫描线、发光控制线、第一复位控制线和第二复位控制线。所述第二导电层至少包括：存储电容的第二电极、第一初始信号线、第二初始信号线。所述第三导电层至少包括：多个晶体管的第一极和第二极、第一电源线、数据线。
在一些示例性实施方式中，所述第一结构的像素电路的第一复位晶体管和第二复位晶体管的有源层为一体结构；第n行第一结构的像素电路的第二复位晶体管与第n+1行像素电路的第一复位晶体管的有源层为一体结构，n为正整数。
在一些示例性实施方式中，所述第二结构的像素电路的第一复位晶体管和第二复位晶体管的有源层为一体结构；第n行第二结构的像素电路的第二复位晶体管的有源层与第n+1行像素电路的第一复位晶体管的有源层没有连接，n为正整数。
在一些示例性实施方式中，所述第三导电层包括：所述第二结构的像素电路的第二复位晶体管的第二极、所述第一结构的像素电路的第二复位晶体管的第二极。所述第二结构的像素电路的第二复位晶体管的第二极通过过孔与第二初始信号线连接。所述第一结构的像素电路的第二复位晶体管的第二 极没有与第二初始信号线连接。
在一些示例性实施方式中，所述第一组导电线和第二组导电线采用透明导电材料。
在一些示例性实施方式中，多个第二类型像素电路间隔分布在多个第一类型像素电路之间。
在一些示例性实施方式中，在多个第一类型像素电路和多个第二类型像素电路中，任一像素电路在第一方向上的尺寸小于第一区域发光元件在第一方向上的尺寸。
在一些示例性实施方式中，所述多个第二区域发光元件包括多组第二区域发光元件，每组中的第二区域发光元件沿第一方向排布，多组第二区域发光元件沿第二方向排布。多个第二类型像素电路包括多组第二类型像素电路，每组中的第二类型像素电路沿第一方向排布，多组第二类型像素电路沿第二方向排布。多个第二区域发光元件至少包括：多个第一发光元件、多个第二发光元件和多个第三发光元件。多个第二类型像素电路包括：多个第一像素电路、多个第二像素电路、多个第三像素电路；多个第一发光元件与多个第一像素电路连接，多个第二发光元件与多个第二像素电路连接，多个第三发光元件与多个第三像素电路连接。在至少一组第二区域发光元件和至少一组第二类型像素电路中，与多个第一发光元件相连的多个第一像素电路比与多个第二发光元件相连的多个第二像素电路中的每一个都更靠近所述第二显示区，且比与多个第三发光元件相连的多个第三像素电路中的每一个都更所述靠近第二显示区。
在一些示例性实施方式中，通过第二组导电线与第二发光元件相连的第二像素电路为第二结构的像素电路，通过第二组导电线与第三发光元件连接的第三像素电路为第二结构的像素电路，通过第一组导电线与第一发光元件连接的第一像素电路为第一结构的像素电路，通过第二组导电线与第一发光元件连接的第一像素电路为第二结构的像素电路。
在一些示例性实施方式中，所述第一发光元件配置为发绿光，所述第二发光元件和第三发光元件之一配置为发红光，所述第二发光元件和所述第三发光元件之另一配置为发蓝光。
在一些示例性实施方式中，所述第一组导电线的长度小于长度分界值，所述第二组导电线的长度大于或等于所述长度分界值。所述长度分界值与所述第二组导电线的最大长度的比值约为0.25至0.35。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
在一些示例性实施方式中，显示装置还包括：感光传感器，位于所述显示基板的一侧，所述感光传感器在所述显示基板上的正投影与所述显示基板的第二显示区存在交叠。
另一方面，本公开实施例提供一种显示基板的制备方法，包括：在衬底基板的第一显示区形成多个第二类型像素电路，在第二显示区形成多个第二区域发光元件，第一显示区位于第二显示区的至少一侧。所述多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路；所述多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接。所述多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接。所述第二组导电线的长度大于所述第一组导电线的长度。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为本公开至少一实施例的显示基板的示意图；
图1B为本公开至少一实施例的显示基板的另一示意图；
图2为本公开至少一实施例的显示基板的结构示意图；
图3为本公开至少一实施例的显示基板的另一结构示意图；
图4A至图4F为本公开至少一实施例的显示基板的局部平面示意图；
图5A为本公开至少一实施例的显示基板的位于第二显示区的一行发光 元件和与其相连的第二类型像素电路的局部示意图；
图5B为本公开至少一实施例的显示基板的位于第二显示区的同一行发光元件中发不同颜色光的发光元件的电容量的示意图；
图6A为本公开至少一实施例的第一结构的像素电路的示意图；
图6B为本公开至少一实施例的第二结构的像素电路的示意图；
图6C为本公开至少一实施例的第一结构的像素电路和第二结构的像素电路的工作时序图；
图7A为本公开至少一实施例的第一结构的像素电路的平面示意图；
图7B为图7A中沿P-P方向的局部剖面示意图；
图7C为本公开至少一实施例的形成半导体层后的第一结构的像素电路示意图；
图7D为本公开至少一实施例的形成第一导电层后的第一结构的像素电路的示意图；
图7E为本公开至少一实施例的形成第二导电层后的第一结构的像素电路的示意图；
图7F为本公开至少一实施例的形成第四绝缘层后的第一结构的像素电路的示意图；
图7G为本公开至少一实施例的形成第三导电层后的第一结构的像素电路的示意图；
图7H为本公开至少一实施例的形成第五绝缘层后的第一结构的像素电路的示意图；
图7I为本公开至少一实施例的形成第四导电层后的第一结构的像素电路的示意图；
图8A为本公开至少一实施例的第二结构的像素电路的平面示意图；
图8B为图8A中沿Q-Q方向的局部剖面示意图；
图8C为本公开至少一实施例的形成半导体层后的第二结构的像素电路示意图；
图8D为本公开至少一实施例的形成第一导电层后的第二结构的像素电路的示意图；
图8E为本公开至少一实施例的形成第二导电层后的第二结构的像素电路的示意图；
图8F为本公开至少一实施例的形成第四绝缘层后的第二结构的像素电路的示意图；
图8G为本公开至少一实施例的形成第三导电层后的第二结构的像素电路的示意图；
图8H为本公开至少一实施例的形成第五绝缘层后的第二结构的像素电路的示意图；
图8I为本公开至少一实施例的形成第四导电层后的第二结构的像素电路的示意图；
图9为本公开至少一实施例的显示基板的位于第二显示区的一行发光元件和与其相连的第二类型像素电路的另一局部示意图；
图10为本公开至少一实施例的显示基板的位于第二显示区的一行发光元件和与其相连的第二类型像素电路的另一局部示意图；
图11为本公开至少一实施例的显示基板的另一示意图；
图12为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中 一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、 电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
随着显示技术的发展，已有的刘海屏或水滴屏设计均逐渐不能满足用户对显示装置高屏占比的需求，一系列具有透光显示区的显示装置应运而生。该类显示装置中，可以将感光传感器(如，摄像头)等硬件设置于透光显示区，因无需打孔，故在确保显示装置实用性的前提下，使真全面屏成为可能。
本公开实施例提供一种显示基板，包括：具有第一显示区和第二显示区的衬底基板、位于第二显示区的多个第二区域发光元件、位于第一显示区的多个第二类型像素电路。第一显示区位于第二显示区的至少一侧。多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路。多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接。多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接。第二组导电线的长度大于第一组导电线的长度。
在一些示例性实施方式中，第一显示区可以为非透光显示区，第二显示区可以为透光显示区。将驱动第二显示区内发光元件的像素电路设置在第一显示区而不设置在第二显示区，可以确保第二显示区的透光率较好。
本公开实施例提供的显示基板，通过调整第二类型像素电路的结构，可以减轻或消除因导电线的长度差异而带来的显示不良。即，在设计与第二区域发光元件相连的第二类型像素电路时，考虑连接第二区域发光元件和第二类型像素电路的导电线的长度。
在一些示例性实施方式中，第一结构的像素电路与第一初始信号线连接，第二结构的像素电路与第一初始信号线和第二初始信号线连接。第一初始信号线和第二初始信号线提供不同的初始信号。在本示例中，第一结构的像素 电路采用单初始信号设计，第二结构的像素电路采用双初始信号设计。
在一些示例性实施方式中，显示基板还包括：位于第一显示区的多个第一区域发光元件和多个第一类型像素电路。多个第一类型像素电路中的至少一个第一类型像素电路与所述多个第一区域发光元件中的至少一个第一区域发光元件连接，且所述至少一个第一类型像素电路在所述衬底基板上的正投影与所述至少一个第一区域发光元件在所述衬底基板上的正投影至少部分重叠。多个第一类型像素电路均为第一结构的像素电路。
在一些示例性实施方式中，第一结构的像素电路包括：驱动晶体管、第一复位晶体管和第二复位晶体管。第一复位晶体管的栅极与第一复位控制线连接，第一复位晶体管的第一极与驱动晶体管的栅极连接，第一复位晶体管的第二极与第一初始信号线连接。第二复位晶体管的栅极与第二复位控制线连接，第二复位晶体管的第一极与发光元件的第一极连接，第二复位晶体管的第二极与第一初始信号线连接。在本示例中，第一结构的像素电路可以采用单个初始信号的设计。
在一些示例性实施方式中，第二结构的像素电路包括：驱动晶体管、第一复位晶体管和第二复位晶体管。第一复位晶体管的栅极与第一复位控制线连接，第一复位晶体管的第一极与驱动晶体管的栅极连接，第一复位晶体管的第二极与第一初始信号线连接。第二复位晶体管的栅极与第二复位控制线连接，第二复位晶体管的第一极与发光元件的第一极连接，第二复位晶体管的第二极与第二初始信号线连接。第二初始信号线提供的第二初始信号不同于第一初始信号线提供的第一初始信号。在本示例中，第二结构的像素电路可以采用两个初始信号的设计。
在一些示例性实施方式中，第一初始信号线提供的第一初始信号为恒压信号。例如，第一初始信号可以约为-3V。然而，本实施例对此并不限定。
在一些示例性实施方式中，第二初始信号线提供的第二初始信号可以为恒压信号，且第二初始信号可以大于第一初始信号线提供的第一初始信号。比如，第一初始信号可以约为-3.0V，第二初始信号可以约为-2.0V、-1.5V、-1.0V或-0.5V。然而，本实施例对此并不限定。
在一些示例性实施方式中，第二结构的像素电路所连接的第二初始信号 线提供的第二初始信号的大小，与该第二结构的像素电路连接的第二组导电线的长度呈正比。在本示例中，第二结构的像素电路连接的第二组导电线的长度越大，该第二结构的像素电路连接的第二初始信号线提供的第二初始信号越大。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一结构的像素电路或第二结构的像素电路还可以包括：数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管和第二发光控制晶体管。数据写入晶体管的栅极与扫描线连接，数据写入晶体管的第一极与数据线连接，数据写入晶体管的第二极与驱动晶体管的第一极连接。阈值补偿晶体管的栅极与扫描线连接，阈值补偿晶体管的第一极与驱动晶体管的栅极连接，阈值补偿晶体管的第二极与驱动晶体管的第二极连接。第一发光控制晶体管的栅极与发光控制线连接，第一发光控制晶体管的第一极与第一电源线连接，第一发光控制晶体管的第二极与驱动晶体管的第一极连接。第二发光控制晶体管的栅极与发光控制线连接，第二发光控制晶体管的第一极与驱动晶体管的第二极连接，第二发光控制晶体管的第二极与发光元件的第一极连接。在本示例中，第一结构的像素电路和第二结构的像素电路可以均为7T1C结构，即包括7个晶体管和1个电容器。然而，本实施例对此并不限定。例如，第一结构的像素电路和第二结构的像素电路可以包括其他数目的晶体管和电容器。
在一些示例性实施方式中，在垂直于显示基板的平面内，显示基板至少包括：设置在衬底基板上的半导体层、第一导电层、第二导电层和第三导电层。半导体层至少包括：多个晶体管的有源层。第一导电层至少包括：多个晶体管的栅极和存储电容的第一电极、扫描线、发光控制线、第一复位控制线和第二复位控制线。第二导电层至少包括：存储电容的第二电极、第一初始信号线、第二初始信号线。第三导电层至少包括：多个晶体管的第一极和第二极、第一电源线、数据线。
在一些示例性实施方式中，第一结构的像素电路的第一复位晶体管和第二复位晶体管的有源层可以为一体结构；第n行第一结构的像素电路的第二复位晶体管与第n+1行像素电路的第一复位晶体管的有源层可以为一体结构，n为正整数。
在一些示例性实施方式中，第二结构的像素电路的第一复位晶体管和第二复位晶体管的有源层为一体结构；第n行第二结构的像素电路的第二复位晶体管的有源层与第n+1行像素电路的第一复位晶体管的有源层没有连接，n为正整数。
在一些示例性实施方式中，第三导电层包括：第二结构的像素电路的第二复位晶体管的第二极、第一结构的像素电路的第二复位晶体管的第二极。第二结构的像素电路的第二复位晶体管的第二极通过过孔与第二初始信号线连接。第一结构的像素电路的第二复位晶体管的第二极没有与第二初始信号线连接。
在一些示例性实施方式中，第一组导电线和第二组导电线采用透明导电材料，例如，氧化铟锡(ITO)、氧化铟锌(IZO)等。
在一些示例性实施方式中，多个第二类型像素电路间隔分布在多个第一类型像素电路之间。
在一些示例性实施方式中，在多个第一类型像素电路和多个第二类型像素电路中，任一像素电路在第一方向上的尺寸小于第一区域发光元件在第一方向上的尺寸。例如，第一区域发光元件在第一方向上的尺寸与任一像素电路在第一方向上的尺寸之差可以约为4微米。然而，本实施例对此并不限定。
在一些示例性实施方式中，多个第二区域发光元件包括多组第二区域发光元件，每组中的第二区域发光元件沿第一方向排布，多组第二区域发光元件沿第二方向排布。多个第二类型像素电路包括多组第二类型像素电路，每组中的第二类型像素电路沿第一方向排布，多组第二类型像素电路沿第二方向排布。多个第二区域发光元件至少包括：多个第一发光元件、多个第二发光元件和多个第三发光元件。多个第二类型像素电路包括：多个第一像素电路、多个第二像素电路、多个第三像素电路。多个第一发光元件与多个第一像素电路连接，多个第二发光元件与多个第二像素电路连接，多个第三发光元件与多个第三像素电路连接。在至少一组第二区域发光元件和至少一组第二类型像素电路中，与多个第一发光元件相连的多个第一像素电路比与多个第二发光元件相连的多个第二像素电路中的每一个都更靠近第二显示区，且比与多个第三发光元件相连的多个第三像素电路中的每一个都更靠近第二显 示区。
在一些示例性实施方式中，通过第二组导电线与第二发光元件连接的第二像素电路为第二结构的像素电路，通过第二组导电线与第三发光元件连接的第三像素电路为第二结构的像素电路，通过第一组导电线与第一发光元件连接的第一像素电路为第一结构的像素电路，通过第二组导电线与第一发光元件连接的第一像素电路为第二结构的像素电路。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一发光元件配置为发绿光，第二发光元件和第三发光元件之一配置为发红光，第二发光元件和第三发光元件之另一配置为发蓝光。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一组导电线的长度小于长度分界值，第二组导电线的长度大于或等于长度分界值。长度分界值与第二组导电线的最大长度的比值约为0.25至0.35。例如，第二组导电线的最大长度约为10000微米，长度分界值约为3000微米。然而，本实施例对此并不限定。第一组导电线和第二组导电线的长度会随着显示基板的尺寸变化而变化。
下面通过一些示例对本实施例的方案进行举例说明。
图1A为本公开至少一实施例的显示基板的示意图。图1B为本公开至少一实施例的显示基板的另一示意图。
在一些示例性实施方式中，显示基板包括：第一显示区R1和第二显示区R2，第一显示区R1可以位于第二显示区R2的至少一侧。在一些示例中，第一显示区R1部分围绕第二显示区R2。例如，图1A示出的第二显示区R2位于显示基板的顶部正中间位置，第二显示区R2的一侧与周边区域相邻，其余三侧由第一显示区R1围绕。然而，本实施例对此并不限定。例如，第二显示区R2可以位于显示基板的左上角位置或右上角位置等其他位置。
在一些示例性实施方式中，如图1B所示，第一显示区R1可以围绕第二显示区R2。其中，第二显示区R2可以位于显示基板的上半部的正中间位置。然而，本实施例对此并不限定。第二显示区R2的设置位置可根据需要而定。
在一些示例性实施方式中，如图1A和图1B所示，第一显示区R1和第 二显示区R2可以均为矩形，例如圆角矩形。然而，本实施例对此并不限定。例如，第一显示区R1可以为圆形或椭圆形等其他形状，第二显示区R2可以为圆形、四边形或五边形等其他形状。例如，第一显示区R1和第二显示区R2的形状可以相同，或者不同。
在一些示例性实施方式中，第二显示区R2可以为透光显示区。例如，感光传感器(如，摄像头)等硬件在显示基板上的正投影可以位于显示基板的第二显示区R2内。本示例的显示基板无需打孔，在确保显示基板实用性的前提下，可以使真全面屏成为可能。
在一些示例性实施方式中，显示基板可以包括设置在衬底基板上的多个子像素，至少一个子像素包括像素电路和发光元件。像素电路配置为驱动发光元件。例如，像素电路配置为提供驱动电流以驱动发光元件发光。例如，发光元件可以为有机发光二极管(OLED)，发光元件在其对应的像素电路的驱动下发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。
在一些示例性实施方式中，为了提高第二显示区R2的光透过率，可以在第二显示区R2仅设置发光元件，而将驱动第二显示区R2的发光元件的像素电路设置在第一显示区R1。即，通过发光元件和像素电路分离设置的方式来提高第二显示区R2的光透过率。在本示例中，在第二显示区R2，不设置像素电路。
图2为本公开至少一实施例的显示基板的结构示意图。在一些示例性实施方式中，如图2所示，显示基板包括：位于第一显示区R1的多个第一类型像素电路10、多个第二类型像素电路20和多个第一区域发光元件30，以及位于第二显示区R2的多个第二区域发光元件40。多个第二类型像素电路20可以间隔分布于多个第一类型像素电路10之间。多个第一类型像素电路10中的至少一个第一类型像素电路10可以与多个第一区域发光元件30中的至少一个第一区域发光元件30连接，且至少一个第一类型像素电路10在衬底基板上的正投影与至少一个第一区域发光元件30在衬底基板上的正投影可以至少部分重叠。该至少一个第一类型像素电路10可以配置为给所连接的第一区域发光元件30提供驱动信号，以驱动该第一区域发光元件30发光。 多个第二类型像素电路20中的至少一个第二类型像素电路20可以与多个第二区域发光元件40中的至少一个第二区域发光元件40通过导电线L连接，该至少一个第二类型像素电路20可以配置为给所连接的第二区域发光元件40提供驱动信号，以驱动该第二区域发光元件40发光。由于第二区域发光元件40与第二类型像素电路20位于不同区域，至少一个第二类型像素电路20在衬底基板上的正投影与至少一个第二区域发光元件40在衬底基板上的正投影不存在重叠部分。
在本示例性实施方式中，可以设置该第一显示区R1为非透光显示区，以及设置该第二显示区R2为透光显示区。即，本示例性实施方式的第一显示区R1不可透光，第二显示区R2可透光。如此，无需在显示基板上进行挖孔处理，可以将感光传感器等所需硬件结构直接设置于第二显示区R2，为真全面屏的实现奠定坚实的基础。并且，由于第二显示区R2内仅包括发光元件，而不包括像素电路，还可以确保第二显示区R2的透光率较好。
在本示例性实施方式中，第一区域发光元件30可称作原位发光元件，第一类型像素电路10可称作原位像素电路，第二类型像素电路20可称作非原位像素电路。
在一些示例性实施方式中，如图2所示，第二区域发光元件40和与该第二区域发光元件40相连的第二类型像素电路20位于同一行。即，第二区域发光元件40的发光信号来自于同一行的第二类型像素电路20。例如，同一行子像素的像素电路与同一条栅线相连。
在一些示例性实施方式中，如图2所示，第二类型像素电路20通过导电线L与第二区域发光元件40相连。例如，导电线L可以采用透明导电材料制作。例如，导电线L可以采用导电氧化物材料制作。例如，导电氧化物材料可以包括氧化铟锡(ITO)，但不限于此。导电线L的一端与第二类型像素电路20相连，导电线L的另一端与第二区域发光元件40相连。如图2所示，导电线L从第一显示区R1延伸至第二显示区R2。
图3为本公开至少一实施例的显示基板的另一结构示意图。在一些示例性实施方式中，如图3所示，第一显示区R1不仅包括多个像素单元，还包括多列第二类型像素电路，第二显示区R2仅包括多个第二区域发光元件。 在本示例中，至少一个像素单元可以包括：红色子像素R、两个绿色子像素G1和G2、以及一个蓝色子像素B，且红色子像素R和蓝色子像素B位于同一列，两个绿色子像素G1和G2位于同一列。然而，本实施例对此并不限定。在一些示例中，一个像素单元也可以包括其他颜色以及其他数量的子像素，且多个子像素的排列方式不限于图3所示结构。
例如，一个像素单元可以包括三个子像素(例如，一个红色子像素R、一个蓝色子像素B，以及一个绿色子像素G)，三个子像素可以采用水平并列、竖直并列或品字方式排列。例如，一个像素单元可以包括四个子像素(一个红色子像素R、一个蓝色子像素B、一个绿色子像素G以及一个白色子像素)，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本公开在此不做限定。
图4A至图4C为本公开至少一实施例的显示基板的局部平面示意图。在一些示例性实施方式中，如图4A所示，第二显示区R2为透光显示区，第一显示区R1为非透光显示区。如图4A和图4B所示，第二显示区R2的第二区域发光元件40的密度可以约等于第一显示区R1的第一区域发光元件30的密度。即，第二显示区R2的分辨率可以与第一显示区R1的分辨率大致相同。然而，本实施例对此并不限定。例如，第二区域发光元件40的密度可大于或小于第一区域发光元件30的密度。即，第二显示区R2的分辨率可大于或小于第一显示区R1的分辨率。如图4B和图4C所示，第二区域发光元件40的发光面积小于第一区域发光元件30的发光面积。即，第一区域发光元件30的发光面积大于第二区域发光元件40的发光面积。图4C中用虚线示出了第二区域发光元件40的发光面积和第一区域发光元件30的发光面积。例如，发光元件的发光面积可对应于像素定义层的开口的面积。
在一些示例性实施方式中，如图4C所示，在第二显示区R2中，相邻的第二区域发光元件40之间设有透光区R0。例如，多个透光区R0彼此相连，形成被多个第二区域发光元件40间隔的连续透光区。导电线L可以采用透明导电材料制作以尽可能地提高透光区R0的透光率。如图4C所示，第二显示区R2内除了设置第二区域发光元件40之外的区域可均为透光区。
在一些示例性实施方式中，如图4B和图4D所示，在第一显示区R1内， 可以通过减小第一类型像素电路10在第一方向X上的尺寸来获得设置第二类型像素电路20的区域。例如，第一类型像素电路10在第一方向X上的尺寸可以小于第一区域发光元件30在第一方向X上的尺寸。第一方向X例如为行方向，但不限于此。在另一些实施例中，第一方向X可以为列方向。本示例性实施方式以第一方向X为行方向为例进行说明。例如，第一类型像素电路10和第二类型像素电路20在第一方向X上的尺寸可以相同，且每个像素电路在第一方向X上的尺寸与第一区域发光元件30在第一方向X上的尺寸可以相差约4微米(μm)。每个像素电路在第二方向Y上的尺寸与第一区域发光元件30在第二方向Y上的尺寸大致相同。其中，第一方向X与第二方向Y垂直。
图4D至图4F为本公开至少一实施例的显示基板的局部结构示意图。为了进一步体现出压缩像素电路后，多出多列像素电路，图4D示出了第一显示区R1的第一区域发光元件的一种结构示意图。图4E示出了图4A中第一显示区R1的部分结构(仅包括像素电路)的示意图，图4F示出了图4A中第一显示区R1的部分结构(仅包括发光元件)的示意图。
在一些示例性实施方式中，如图4D至图4F所示，像素电路在第一方向X上的尺寸较发光元件在第一方向X上的尺寸小，如此，可以使得从右往左第2列和第9列的像素电路不连接任何第一区域发光元件30，属于多出列像素电路，其可以作为第二类型像素电路20以连接第二显示区R2内的第二区域发光元件40。如图4E和图4F所示，任一第一区域发光元件30可以为RG1BG2共4种发光元件的一种。第一区域发光元件30的第一极E1可以通过第二转接电极CE2与第一类型像素电路10的第一转接电极CE1连接。R表示发红光的发光元件，G1表示发绿光的发光元件，B表示发蓝光的发光元件，G2表示发绿光的发光元件。至少一个第二类型像素电路20可以具有第一转接电极，至少一个第二区域发光元件40可以具有第二转接电极。例如，至少一个第二类型像素电路20和至少一个第二区域发光元件40通过导电线L连接可以包括：导电线L分别连接至少一个第二类型像素电路20的第一转接电极以及至少一个第二区域发光元件40的第二转接电极。为了具有充足的空间用来设置导电线L，同一行子像素中的第一转接电极和第二转接电极的 轴线可以位于一条直线上。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图4F所示，G包括G1或G2。图4F所示的像素排列中，一个重复单元RP包括在第二方向Y上排列的两个G和分设在该两个G在第一方向X上的两侧的R和B，其中R和G构成一个像素，并借用与其相邻的另一重复单元中的B构成一个虚拟像素以进行显示，B和G构成一个像素，并借用与其相邻的另一重复单元中的R构成一个虚拟像素以进行显示。然而，本实施例对此并不限定。
图5A为本公开至少一实施例的显示基板的位于第二显示区的一行发光元件和与其相连的第二类型像素电路的局部示意图。图5B为本公开至少一实施例的显示基板的位于第二显示区的同一行发光元件中发不同颜色光的发光元件的电容量的示意图。在一些示例性实施方式中，第二显示区R2关于在第一方向X上的中轴线对称。图5A仅示意了第二显示区R2左半部分的一行发光元件与第一显示区R1内的第二类型像素电路的连接关系。
在一些示例性实施方式中，如图5A所示，在第二显示区R2，多个第二区域发光元件40包括：多个第一发光元件41、多个第二发光元件42、多个第三发光元件43以及多个第四发光元件44。第一发光元件41配置为发第一颜色光，第二发光元件42配置为发第二颜色光，第三发光元件43配置为发第三颜色光，第四发光元件44配置为发第四颜色光。在一些示例中，第一颜色光和第四颜色光均为绿(G)光，第二颜色光为红(R)光，第三颜色光为蓝(B)光。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5A所示，在第一显示区R1，多个第二类型像素电路20包括：多个第一像素电路21、多个第二像素电路22、多个第三像素电路23和多个第四像素电路24。多个第一发光元件41与多个第一像素电路21通过多条第一导电线La连接，多个第二发光元件42与多个第二像素电路22通过多条第二导电线Lb连接，多个第三发光元件43与多个第三像素电路23通过多条第三导电线Lc连接，多个第四发光元件44与多个第四像素电路24通过多条第四导电线Ld连接。例如，一个第一发光元件41与一个第一像素电路21通过一条第一导电线La连接，一个第二发光元件42与一个第二像素电路22通过一条第二导电线Lb连接，一个第三发光元件 43与一个第三像素电路23通过一条第三导电线Lc连接，一个第四发光元件44与一个第四像素电路24通过一条第四导电线Ld连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一导电线La、第二导电线Lb、第三导电线Lc、以及第四导电线Ld中的至少之一可以由透明导电材料制作。
在一些示例性实施方式中，第二显示区R2的多个第二区域发光元件40包括多组第二区域发光元件40，每组中的第二区域发光元件40沿第一方向X排布，多组第二区域发光元件40沿第二方向Y排布。多个第二类型像素电路20包括多组第二类型像素电路20，每组中的第二类型像素电路20沿第一方向X排布，多组第二类型像素电路20沿第二方向Y排布。在每组中的第二类型像素电路20之间排布第一类型像素电路10。图5A中示意了一组第二区域发光元件40和一组第二类型像素电路20。在本示例中，一组第二区域发光元件40可以为一行第二区域发光元件40，一组第二类型像素电路20可以为一行第二类型像素电路20。在图5A所示的一行第二区域发光元件40的上侧、下侧或者上侧和下侧，还包括与示出的一行第二区域发光元件40相同的多行第二区域发光元件。
在本公开实施例中，一行发光元件可以指与该行发光元件相连的像素电路均与同一条栅线(例如，扫描线)相连。一行像素电路可以指该行像素电路均与同一条栅线相连。一行子像素可指与该行子像素相连的像素电路均与同一条栅线相连。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5A所示，在一组第二区域发光元件40和一组第二类型像素电路20中，与多个第一发光元件41相连的多个第一像素电路21比与多个第二发光元件42相连的多个第二像素电路22中的每一个都更靠近第二显示区R2，且比与多个第三发光元件43相连的多个第三像素电路23中的每一个都更靠近第二显示区R2。与多个第四发光元件44相连的多个第四像素电路24比与多个第二发光元件42相连的多个第二像素电路22中的每一个都更靠近第二显示区R2，且比与多个第三发光元件43相连的多个第三像素电路23中的每一个都更靠近第二显示区R2。在本示例中，在设计与第二区域发光元件40相连的第二类型像素电路20时，采用G优先的顺 序，即与发绿光的发光元件相连的第二类型像素电路优先靠近第二显示区R2排布。
在一些示例性实施方式中，如图5A所示，在至少一组第二区域发光元件40和至少一组第二类型像素电路20中，两个相邻的第二类型像素电路20之间设置多个第一类型像素电路10中的至少一个。在一些示例中，在至少一组第二区域发光元件40和至少一组第二类型像素电路20中，与相邻两条第一导电线La相连的两个第一像素电路21之间不设置其他的第二类型像素电路20。该种设置方式利于减小第一导电线La的长度，也利于减小第一导电线La之间的长度差异。
在一些示例性实施方式中，如图5A所示，为了使得第二导电线Lb具有较小的电容量差异和为了使得第三导电线Lc具有较小的电容量差异，在至少一组第二区域发光元件40和至少一组第二类型像素电路20中，与多条第二导电线Lb相连的多个第二像素电路22和与多条第三导电线Lc相连的多个第三像素电路23交替设置。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5A所示，为了使得第一导电线La具有较小的电容量差异和使得第四导电线Ld具有较小的电容量差异，在至少一组第二区域发光元件和至少一组第二类型像素电路中，与多条第四导电线Ld相连的多个第四像素电路24和与多条第一导电线La相连的多个第一像素电路21交替设置。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5B所示，横坐标表示显示基板的第二显示区R2在第一方向X上的位置，纵坐标表示与该位置处的发光元件相连的导电线的电容量占总电容量的比值。如图5B所示，与发绿光的发光元件相连的导电线的电容量最小，并且如图5B的左半部分所示，与发绿光的发光元件相连的导电线的电容量呈现逐渐增加的趋势，从而，与相邻的发绿光的发光元件相连的两条导电线的电容量差异较小。由于显示基板的第二显示区R2的结构关于第一方向X对称设置，图5B所示的右半部分不做详细描述。如图5B所示，与发绿光的发光元件相连的导电线的电容量小于与发红光的发光元件相连的导电线的电容量，与发绿光的发光元件相连的导电线的电容量小于与发蓝光的发光元件相连的导电线的电容量。如图5B所示，与 发红光的发光元件相连的导电线的电容量呈现逐渐增加的趋势，且与发蓝光的发光元件相连的导电线的电容量呈现逐渐增加的趋势，且与发红光的发光元件相连的导电线的电容量和与发蓝光的发光元件相连的导电线的电容量相差不大。
在一些示例性实施方式中，第一显示区R1内的多个第二类型像素电路20包括：多个第一结构的像素电路和多个第二结构的像素电路。第一显示区R1内的多个第一类型像素电路10均为第一结构的像素电路。在一些示例中，第一结构的像素电路和第二结构的像素电路可以均为7T1C结构，即包括7个晶体管和1个电容器。然而，本实施例对此并不限定。
下面对本示例性实施方式的第一结构的像素电路和第二结构的像素电路进行详细说明。
图6A为本公开至少一实施例的第一结构的像素电路的示意图。图6B为本公开至少一实施例的第二结构的像素电路的示意图。图6C为本公开至少一实施例的第一结构的像素电路和第二结构的像素电路的工作时序图。
在一些示例性实施方式中，如图6A和图6B所示，第一结构的像素电路和第二结构的像素电路均包括六个开关晶体管(T1、T2、T4至T7)、一个驱动晶体管T3和一个存储电容Cst。六个开关晶体管分别为数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1、以及第二复位晶体管T7。发光元件EL包括第一极E1、第二极E2以及位于第一极E1和第二极E2之间的有机发光层。例如，第一极E1可以为阳极，第二极E2可以为阴极。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，驱动晶体管和六个开关晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，驱动晶体管和六个开关晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的 有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，如图6A和图6B所示，显示基板包括扫描线GT、数据线DT、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一复位控制线RST1和第二复位控制线RST2。在一些示例中，第一电源线PL1配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。扫描线GT配置为向像素电路提供扫描信号SCAN，数据线DT配置为向像素电路提供数据信号DATA，发光控制线EML配置为向像素电路提供发光控制信号EM，第一复位控制线RST1配置为向像素电路提供第一复位控制信号RESET1，第二复位控制线RST2配置为向像素电路提供扫描信号SCAN。例如，在一行像素电路中，第二复位控制线RST2可以与扫描线GT相连，以被输入扫描信号SCAN。然而，本实施例对此并不限定。例如，第二复位控制信号线RST2可以被输入第二复位控制信号RESET2。例如，在第n行像素电路中，第一复位控制线RST1可以与第n-1行像素电路的扫描线GT连接，以被输入扫描信号SCAN(n-1)，即第一复位控制信号RESET1(n)与扫描信号SCAN(n-1)相同。如此，可以减少显示基板的信号线，实现显示基板的窄边框。
在一些示例性实施方式中，第一初始信号线INIT1配置为向像素电路提供第一初始信号Vinit1。第二初始信号线INIT2配置为向像素电路提供第二初始信号Vinit2。例如，第一初始信号Vinit1和第二初始信号Vinit2可以为恒压信号，其大小例如可以介于第一电压信号VDD和第二电压信号VSS之间，但不限于此。例如，第一初始信号Vinit1和第二初始信号Vinit2可以小于或等于第二电压信号VSS。
在一些示例性实施方式中，如图6A所示，在第一结构的像素电路中， 驱动晶体管T3与发光元件EL电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号VDD、第二电压信号VSS等信号的控制下输出驱动电流以驱动发光元件EL发光。数据写入晶体管T4的栅极与扫描线GT相连，数据写入晶体管T4的第一极与数据线DT相连，数据写入晶体管T4的第二极与驱动晶体管T3的第一极相连。阈值补偿晶体管T2的栅极与扫描线GT相连，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极相连，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极相连。第一发光控制晶体管T5的栅极与发光控制线EML相连，第一发光控制晶体管T5的第一极与第一电源线PL1相连，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极相连。第二发光控制晶体管T6的栅极与发光控制线EML相连，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极相连，第二发光控制晶体管T6的第二极与发光元件EL的第一极E1相连。第一复位晶体管T1与驱动晶体管T3的栅极相连，并配置为对驱动晶体管T3的栅极进行复位，第二复位晶体管T7与发光元件EL的第一极E1相连，并配置为对发光元件EL的第一电极E1进行复位。第一复位晶体管T1的栅极与第一复位控制线RST1相连，第一复位晶体管T1的第一极与第一初始信号线INIT1相连，第一复位晶体管T1的第二极与驱动晶体管T3的栅极相连。第二复位晶体管T7的栅极与第二复位控制线RST2相连，第二复位晶体管T7的第一极与第一初始信号线INIT1相连，第二复位晶体管T7的第二极与发光元件EL的第一极E1相连。存储电容Cst的第一电极与驱动晶体管T3的栅极相连，存储电容Cst的第二电极与第一电源线PL1相连。在本示例中，第一节点N1为存储电容Cst、第一复位晶体管T1、驱动晶体管T3和阈值补偿晶体管T2的连接点，第二节点N2为第一发光控制晶体管T5、数据写入晶体管T4和驱动晶体管T3的连接点，第三节点N3为驱动晶体管T3、阈值补偿晶体管T2和第二发光控制晶体管T6的连接点，第四节点N4为第二发光控制晶体管T6、第二复位晶体管T7和发光元件EL的连接点。
下面参照图6C对图6A示意的第一结构的像素电路的工作过程进行说明。以第一结构的像素电路包括的多个晶体管均为P型晶体管为例进行说明。
在一些示例性实施方式中，如图6C所示，在一帧显示时间段，第一结 构的像素电路的工作过程包括：第一阶段A1、第二阶段A2和第三阶段A3。
第一阶段A1，称为复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，使第一复位晶体管T1导通，第一初始信号线INIT1提供的第一初始信号Vinit1被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。扫描线GT提供的扫描信号SCAN为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6以及第二复位晶体管T7断开。此阶段发光元件EL不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。扫描线GT提供的扫描信号SCAN为低电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1和发光控制线EML提供的发光控制信号EM均为高电平信号，数据线DT输出数据信号DATA。此阶段由于存储电容Cst的第二电极为低电平，因此，驱动晶体管T3导通。扫描信号SCAN为低电平信号，使阈值补偿晶体管T2、数据写入晶体管T4和第二复位晶体管T7导通。阈值补偿晶体管T2和数据写入晶体管T4导通，使得数据线DT输出的数据电压Vdata经过第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的阈值补偿晶体管T2提供至第一节点N2，并将数据线DT输出的数据电压Vdata与驱动晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第二电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DT输出的数据电压，Vth为驱动晶体管T3的阈值电压。第二复位晶体管T7导通，使得第一初始信号线INIT1提供的第一初始信号Vinit1提供至发光元件EL的第一极E1，对发光元件EL的第一极E1进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，使第一复位晶体管T1断开。发光控制信号线EML提供的发光控制信号EM为高电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6断开。
第三阶段A3，称为发光阶段。发光控制信号线EML提供的发光控制信号EM为低电平信号，扫描线GT提供的扫描信号SCAN和第一复位控制线 RST1提供的第一复位控制信号RESET1为高电平信号。发光控制信号线EML提供的发光控制信号EM为低电平信号，使第一发光控制晶体管T5和第二发光控制晶体管T6导通，第一电源线PL1输出的第一电压信号VDD通过导通的第一发光控制晶体管T5、驱动晶体管T3和第二发光控制晶体管T6向发光元件EL的第一极E1提供驱动电压，驱动发光元件EL发光。
在像素电路驱动过程中，流过驱动晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(VDD-Vdata+|Vth|)-Vth]2＝K*[(VDD-Vdata)] 2
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为驱动晶体管T3的栅极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据线DT输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与驱动晶体管T3的阈值电压无关。因此，本实施例的第一结构的像素电路可以较好地补偿驱动晶体管T3的阈值电压。
在一些示例性实施方式中，如图6B所示，在第二结构的像素电路中，第二复位晶体管T7的栅极与第二复位控制线RST2相连，第二复位晶体管T7的第一极与第二初始信号线INIT2相连，第二复位晶体管T7的第二极与发光元件EL的第一极E1相连。第一初始信号线INIT1和第二初始信号线INIT2彼此绝缘，并配置为分别输入信号。关于第二结构的像素电路的其余晶体管和存储电容的结构可以参照图6A所示的第一结构的像素电路的相关说明，故于此不再赘述。
在一些示例性实施方式中，如图6B和图6C所示，在第二结构的像素电路的工作过程中，在第二阶段A2，第二复位晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号Vinit2提供至发光元件EL的第一极E1，对发光元件EL的第一极E1进行初始化(复位)，清空其内部的预存电压，完成初始化，确保发光元件EL不发光。关于第二结构的像素电路的其余工作过程可以参照第一结构的像素电路的工作过程的相关说明，故于此不再赘 述。
在本示例性实施方式中，第一结构的像素电路采用单个初始信号设计，其中，第一复位晶体管和第二复位晶体管接收相同的初始信号(即第一初始信号)；第二结构的像素电路采用两个初始信号设计，其中，第一复位晶体管和第二复位晶体管接收不同的初始信号(即第一复位晶体管接收第一初始信号，第二复位晶体管接收第二初始信号)。
以第一显示区R1的像素电路均为图6B所示的像素电路为例，第二类型像素电路和第二区域发光元件之间通过导电线连接，而导电线的长度过大会导致图6B所示的像素电路中的第四节点N4电容过大，从而使得第四节点N4在第二阶段A2重置为第二初始信号Vinit2后，需要较长时间充电才能达到预定电位。如此一来，会影响第二区域发光元件的启亮时长，导致显示发暗，造成第一显示区R1和第二显示区R2之间的显示亮度差异。通过提高第二初始信号Vinit2，可以有效减小第四节点N4的充电量，在电流一定的情况下，电量与时长成正比，因此，通过提高第二初始信号Vinit2可以有效减少充电时长，从而可以增加发光时长，改善由于导电线过长造成的亮度差异。然而，提高第二初始信号Vinit2存在发光元件EL漏电风险。由于第二初始信号Vinit2提供发光元件EL的阳极电压，第二电压信号VSS提供发光元件EL的阴极电压，第二初始信号Vinit2过高会出现对比度下降、无法显示黑画面、发光元件EL易被点亮等问题。
本示例性实施方式中，考虑导电线的长度来设计像素电路的结构，以提升显示效果。在第一显示区的第一类型像素电路和第一区域发光元件之间无需通过导电线连接，为了避免提高第二初始信号Vinit2产生的不良，第一类型像素电路可以采用单初始信号设计，例如，第一类型像素电路可以为图6A所示的第一结构的像素电路。
在本示例性实施方式中，在第一显示区的第二类型像素电路和第二显示区的第二区域发光元件之间通过导电线连接，且不同第二区域发光元件所连接的导电线的长度存在差异。通过仿真模拟可以确定造成第一显示区和第二显示区之间亮度差异的导电线的长度分界值，以此长度分界值将连接第二区域发光元件和第二类型像素电路的导电线分成第一组导电线和第二组导电线。 第一组导电线的长度可以小于该长度分界值。第二组导电线的长度可以大于或等于该长度分界值，会造成第一显示区和第二显示区之间的亮度差异。通过第一组导电线与第二区域发光元件连接的第二类型像素电路可以采用单初始信号设计，例如，可以为图6A所示的第一结构的像素电路，以避免提高第二初始信号Vinit2造成发光元件容易被启亮的情况。通过第二组导电线与第二区域发光元件连接的第二类型像素电路可以采用双初始信号设计，例如，可以为图6B所示的第二结构的像素电路。连接第二组导电线的第二区域发光元件由于导电线电容过大存在启亮困难的情况，通过提高第二初始信号Vinit2可以减少第四节点N4的充电时长，改善显示不良。
在一些示例中，在确定长度分界值的仿真模拟过程中，可以提供恒定的第二初始化信号，然后根据显示基板的亮度随导电线的长度变化的影响来确定长度分界值。或者，可以计算导电线的电容，并基于低灰阶下的显示效果来确定长度分界值。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5A所示，连接在第一发光元件41和第一像素电路21的第一导电线La的长度约为100μm至6000μm，连接第二发光元件42和第二像素电路22的第二导电线Lb的长度约为5000μm至10000μm，连接第三发光元件43和第三像素电路23的第三导电线Lc的长度约为5000μm至10000μm，连接第四发光元件44和第四像素电路24的第四导电线Ld的长度约为100μm至6000μm。在本示例中，通过仿真模拟得到的导电线的长度分界值可以约为3000μm。其中，长度小于3000μm的导电线可以称为第一组导电线，长度大于等于3000μm的导电线可以称为第二组导电线。第一组导电线所连接的第二类型像素电路可以为第一结构的像素电路，第二组导电线所连接的第二类型像素电路可以为第二结构的像素电路。在区分第一组导电线和第二组导电线的基础上，调整像素电路的结构，可以避免导电线电容较小情况下，提升第二初始信号产生显示不良的情况，又可以在导电线电容较大情况下，通过提升第二初始信号来改善显示缺陷。本实施例对于导电线的长度并不限定。在显示基板的尺寸变化时，长度分界值以及导电线的长度均会发生变化。
在一些示例性实施方式中，如图5A所示，长度约为100μm至3000μm 的第一导电线La所连接的第一像素电路21可以为第一结构的像素电路，长度约为3000μm至6000μm的第一导电线La所连接的第一像素电路21可以为第二结构的像素电路；第二导电线Lb所连接的第二像素电路22、第三导电线Lc所连接的第三像素电路23均为第二结构的像素电路；长度约为100μm至3000μm的第四导电线Ld所连接的第四像素电路24可以为第一结构的像素电路，长度约为3000μm至6000μm的第四导电线Ld所连接的第四像素电路24可以为第二结构的像素电路。
在一些示例性实施方式中，如图5A所示，在第一显示区R1内，第一区域发光元件30和第一类型像素电路10无需通过导电线连接，第一类型像素电路10可以均为第一结构的像素电路，以避免提升第二初始信号而导致发光元件容易被启亮的情况。
在一些示例性实施方式中，第一初始信号线INIT1提供的第一初始信号Vinit1可以为恒压信号，例如，约为-3V。第二初始信号线INIT2提供的第二初始信号Vinit2可以为恒压信号，且大于第一初始信号Vinit1。例如，第二初始信号Vinit2可以大于-3V，比如约为-2V、-1.5V、-1V或-0.5V。在一些示例中，多条第二初始信号线INIT2可以提供不同的第二初始信号。例如，第二结构的像素电路所连接的第二初始信号线提供的第二初始信号的大小，与连接在该第二结构的像素电路和第二区域发光元件之间的第二组导电线的长度呈正比。例如，第二结构的像素电路连接的第二组导电线越长，与该像素电路连接的第二初始信号线提供的第二初始信号越大。然而，本实施例对此并不限定。
图7A为本公开至少一实施例的第一结构的像素电路的平面示意图。图7B为图7A中沿P-P方向的局部剖面示意图。其中，第一方向X可以是子像素行的方向(水平方向)，第二方向Y可以是子像素列的方向(竖直方向)。
在一些示例性实施方式中，如图7A所示，在平行于显示基板的平面内，显示基板设置有扫描线GT、发光控制线EML、第一复位控制线RST1、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线PL1、数据线DT以及第一结构的像素电路。第一结构像素电路可以包括多个晶体管和存储电容Cst，多个晶体管可以包括驱动晶体管T3、数据写入晶体管T4、阈值补偿 晶体管T2、第一复位晶体管T1、第二复位晶体管T7、第一发光控制晶体管T5和第二发光控制晶体管T6。
在图7A中示意了第n行像素电路的多个晶体管T1至T7、第n-1行像素电路的第二复位晶体管T7’、以及第n+1行像素电路的第一复位晶体管T1’。如图7A所示，第n行像素电路的第一复位晶体管T1与第一复位控制线RST1(n)连接，第一复位控制线RST1(n)与第n-1行像素电路所连接的扫描线GT(n-1)连接，第n-1行像素电路的第二复位晶体管T7’与第一复位控制线RST1(n)连接，实现输入扫描信号SCAN(n-1)。第n+1行像素电路的第一复位晶体管T1’与第一复位控制线RST1(n+1)连接，第一复位控制线RST1(n+1)与第n行像素电路所连接的扫描线GT(n)连接，第n行像素电路的第二复位晶体管T7与第一复位控制线RST1(n+1)连接，实现输入扫描信号SCAN(n)。
在一些示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括在衬底基板50上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。在一些示例中，半导体层可以包括多个晶体管的有源层。第一导电层可以包括扫描线GT、第一复位控制线RST1、发光控制线EML、存储电容Cst的第一电极、多个晶体管的栅极。第二导电层可以包括第一初始信号线INIT1、第二初始信号线INIT2、存储电容Cst的第二电极、第一屏蔽电极BK。第三导电层可以包括第一电源线PL1、数据线DT、多个晶体管的第一极和第二极。第四导电层可以包括：第二屏蔽电极SE、第一连接电极CE1。
在一些示例性实施方式中，如图7B所示，显示基板可以包括第一绝缘层51、第二绝缘层52、第三绝缘层53、第四绝缘层54和第五绝缘层55。第一绝缘层51设置在衬底基板50与半导体层之间，第二绝缘层52设置在半导体层和第一导电层之间，第三绝缘层53设置在第一导电层与第二导电层之间，第四绝缘层54设置在第二导电层与第三导电层之间，第五绝缘层55设置在第三导电层和第四导电层之间。在一些示例中，第一绝缘层51、第二绝缘层52、第三绝缘层53和第四绝缘层54可以为无机绝缘层，第五绝缘层55可以为有机绝缘层。然而，本实施例对此并不限定。
图7C为本公开至少一实施例的形成半导体层后的第一结构的像素电路的示意图。在一些示例性实施方式中，如图7C所示，至少一个子像素的半导体层可以包括：第一复位晶体管T1的第一有源层T10、阈值补偿晶体管T2的第二有源层T20、驱动晶体管T3的第三有源层T30、数据写入晶体管T4的第四有源层T40、第一发光控制晶体管T5的第五有源层T50、第二发光控制晶体管T6的第六有源层T60、第二复位晶体管T7的第七有源层T70。其中，第一有源层T10至第七有源层T70为相互连接的一体结构。第一有源层T10与上一行像素电路的第七有源层T70’为一体结构，第七有源层T10与下一行像素电路的第一有源层T10’为一体结构。
在一些示例性实施方式中，如图7C所示，第一有源层T10和T10’的形状可以呈“n”字形，第二有源层T20的形状可以呈“7”字形，第三有源层T30的形状可以呈“几”字形，第四有源层T40的形状可以呈“1”字形，第五有源层T50、第六有源层T06、第七有源层T70和T70’的形状可以呈“L”字形。
在一些示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在一些示例中，如图7C所示，第一有源层T10的第一区T10-1同时作为上一行像素电路的第七晶体管T7’的第七有源层T70’的第一区，第一有源层T10的第二区T10-2同时作为第二有源层T20的第一区T20-1，第三有源层T30的第一区T30-1同时作为第四有源层T40的第二区T40-2和第五有源层T50的第二区T50-2，第三有源层T30的第二区T30-2同时作为第二有源层T20的第二区T20-2和第六有源层T60的第一区T60-1，第六有源层T60的第二区T60-2同时作为第七有源层T70的第二区T70-2。
图7D为本公开至少一实施例的形成第一导电层后的第一结构的像素电路的示意图。在一些示例性实施例中，如图7D所示，第一导电层至少包括：存储电容Cst的第一电极Cst-1、沿第一方向X延伸的扫描线GT、发光控制线EML、第一复位控制线RST1(n)和RST1(n+1)。存储电容Cst的第一电极Cst-1可以为矩形状，矩形状的角部可以设置倒角，第一电极Cst-1在衬底基板上的正投影与驱动晶体管T3的第三有源层T30在衬底基板上的正投 影存在重叠区域。存储电容Cst的第一电极Cst-1同时作为驱动晶体管T3的栅极T33。扫描线GT、数据写入晶体管T4的栅极T43、以及阈值补偿晶体管T2的栅极T23可以为一体结构。发光控制线EML、第一发光控制晶体管T5的栅极T53、第二发光控制晶体管T6的栅极T63可以为一体结构。第一复位控制线RST1(n)、第一复位晶体管T1的栅极T13、以及上一行像素电路的第二复位晶体管T7’的栅极T73’可以为一体结构。第一复位控制线RST1(n+1)、第二复位晶体管T7的栅极T73、以及下一行像素电路的第一复位晶体管T1’的栅极T13’可以为一体结构。
图7E为本公开至少一实施例的形成第二导电层后的第一结构的像素电路的示意图。在一些示例性实施方式中，如图7E所示，第二导电层至少包括：第一初始信号线INIT1、第二初始信号线INIT2、存储电容Cst的第二电极Cst-2、第一屏蔽电极BK。第一初始信号线INIT1和第二初始信号线INIT2沿第一方向X延伸，位于扫描线GT的一侧。存储电容Cst的第二电极Cst-2位于扫描线GT和发光控制线EML之间。存储电容Cst的第二电极Cst-2在衬底基板上的正投影与第一电极Cst-1在衬底基板上的正投影存在重叠区域。第二电极Cst-2上设置有开口OP1，开口OP1暴露出覆盖第一电极Cst-1的第三绝缘层53，且第一电极Cst-1在衬底基板上的正投影包含开口OP1在衬底基板上的正投影。在一些示例中，开口OP1配置为容置后续形成的第一过孔H1，第一过孔H1位于开口OP1内并暴露出第一电极Cst-1，使后续形成的第一复位晶体管T1的第二极与第一电极Cst-1连接。
在一些示例性实施方式中，如图7E所示，第一屏蔽电极BK位于扫描线GT远离存储电容Cst的一侧。第一屏蔽电极BK配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素电路的关键节点的电位，提高显示效果。
图7F为本公开至少一实施例的形成第四绝缘层后的第一结构的像素电路的示意图。在一些示例性实施方式中，如图7F所示，第四绝缘层54上形成有第一过孔H1、多个第二过孔V1至V4、以及多个第三过孔K1至K8。第一过孔H1内的第四绝缘层54和第三绝缘层53被刻蚀掉，暴露出第一导电层的表面。多个第二过孔V1至V4内的第四绝缘层54被刻蚀掉，暴露出 第二导电层的表面。多个第三过孔K1至K8内的第四绝缘层54、第三绝缘层53和第二绝缘层52被刻蚀掉，暴露出半导体层的表面。
图7G为本公开至少一实施例的形成第三导电层后的第一结构的像素电路的示意图。在一些示例性实施方式中，如图7G所示，第三导电层可以包括：数据线DT、第一电源线PL1、第一复位晶体管T1的第一极T11、第二复位晶体管T7的第一极T71、阈值补偿晶体管T2的第一极T21、第二发光控制晶体管T6的第二极T62、下一行像素电路的第一复位晶体管T1’的第一极T11’、上一行像素电路的第二复位晶体管T7’的第一极T71’。数据线DT和第一电源线PL1沿第二方向Y延伸。
在一些示例性实施方式中，如图7F和图7G所示，数据线DT通过第三过孔K2与数据写入晶体管T4的第四有源层T40的第一区T40-1相连。第一电源线PL1通过第二过孔V1与存储电容Cst的第二电极Cst-2相连，通过第二过孔V2与第一屏蔽电极BK相连，通过第三过孔K3与第一发光控制晶体管T5的第五有源层T50的第一区T50-1相连。阈值补偿晶体管T2的第一极T21通过第一过孔H1与存储电容Cst的第一电极Cst-1相连，通过第三过孔K1与阈值补偿晶体管T2的第二有源层T20的第一区T20-1相连。第二发光控制晶体管T6的第二极T62通过第三过孔K4与第二发光控制晶体管T6的第六有源层T60的第二区T60-2相连。第一复位晶体管T1的第一极T11通过第二过孔V3与第一初始信号线INIT1相连，通过第三过孔K5与第一复位晶体管T1的第一有源层T10的第一区T10-1相连。第二复位晶体管T7的第一极T71通过第三过孔K8与第二复位晶体管T7的第七有源层T70的第一区T70-1相连。下一行像素电路的第一复位晶体管T1’的第一极T11’通过第二过孔V4与第一初始信号线INIT1相连，通过第三过孔K7与第一复位晶体管T1’的第一有源层T10’的第一区相连。上一行像素电路的第二复位晶体管T7’的第一极T71’通过第三过孔K6与第二复位晶体管T7’的第一有源层T80’的第一区相连。在本示例性实施方式中，第二复位晶体管的第一极没有连接到第二初始信号线INIT2。由于本行像素电路的第二复位晶体管和下一行像素电路的第一复位晶体管的有源层为一体结构，且下一行像素电路的第一复位晶体管与第一初始信号线INIT1相连，从而实现本行像素电路的第二复位 晶体管也连接第一初始信号线INIT1。
图7H为本公开至少一实施例的形成第五绝缘层后的第一结构的像素电路的示意图。在一些示例性实施方式中，第五绝缘层55上形成有多个第四过孔F1至F2。多个第四过孔F1至F2内的第五绝缘层55被去掉，暴露出第三导电层的表面。
图7I为本公开至少一实施例的形成第四导电层后的第一结构的像素电路的示意图。在一些示例性实施方式中，第四导电层至少包括：第二屏蔽电极SE和第一转接电极CE1。第一转接电极CE1通过第四过孔F1与第二发光控制晶体管T6的第二极T62连接。第一转接电极CE1可以直接连接至第一区域发光元件，或者，与第一区域发光元件的第二转接电极连接，或者，通过导电线与第二区域发光元件的第二转接电极连接。第二屏蔽电极SE通过第四过孔F2与第一电源线PL1相连。第二屏蔽电极SE在衬底基板上的正投影与驱动晶体管T3在衬底基板上的正投影部分交叠。第二屏蔽电极SE配置为屏蔽导电线对驱动晶体管T3的影响，提高显示效果。
图8A为本公开至少一实施例的第二结构的像素电路的平面示意图。图8B为图8A中沿Q-Q方向的局部剖面示意图。图8C为本公开至少一实施例的形成半导体层后的第二结构的像素电路示意图。图8D为本公开至少一实施例的形成第一导电层后的第二结构的像素电路的示意图。图8E为本公开至少一实施例的形成第二导电层后的第二结构的像素电路的示意图。图8F为本公开至少一实施例的形成第四绝缘层后的第二结构的像素电路的示意图。图8G为本公开至少一实施例的形成第三导电层后的第二结构的像素电路的示意图。图8H为本公开至少一实施例的形成第五绝缘层后的第二结构的像素电路的示意图。图8I为本公开至少一实施例的形成第四导电层后的第二结构的像素电路的示意图。
在图8A中示意了第n行像素电路的多个晶体管T1至T7、第n-1行像素电路的第二复位晶体管T7’、以及第n+1行像素电路的第一复位晶体管T1’。如图7A所示，第n行像素电路的第一复位晶体管T1与第一复位控制线RST1(n)连接，第一复位控制线RST1(n)与第n-1行像素电路所连接的扫描线GT(n-1)连接，第n-1行像素电路的第二复位晶体管T7’与第一复位控制线 RST1(n)连接，实现输入扫描信号SCAN(n-1)。第n+1行像素电路的第一复位晶体管T1’与第一复位控制线RST1(n+1)连接，第一复位控制线RST1(n+1)与第n行像素电路所连接的扫描线GT(n)连接，第n行像素电路的第二复位晶体管T7与第一复位控制线RST1(n+1)连接，实现输入扫描信号SCAN(n)。
在一些示例性实施方式中，如图8A至图8I所示，第一复位晶体管T1的第一有源层T10、阈值补偿晶体管T2的第二有源层T20、驱动晶体管T3的第三有源层T30、数据写入晶体管T4的第四有源层T40、第一发光控制晶体管T5的第五有源层T50、第二发光控制晶体管T6的第六有源层T60、第二复位晶体管T7的第七有源层T70为相互连接的一体结构。本行像素电路的第一有源层T10与上一行像素电路的第七有源层T70’相互独立，本行像素电路的第七有源层T10与下一行像素电路的第一有源层T10’相互独立。第二结构的像素电路的第二复位晶体管T7的第一极T71通过第二过孔V5与第二初始信号线INIT2相连，通过第三过孔K8与第二复位晶体管T7的第七有源层T70的第一区T70-1相连。第二结构的像素电路的第一复位晶体管T1的第一极T11通过第二过孔V3与第一初始信号线INIT1相连，通过第三过孔K5与第一复位晶体管T1的第一有源层T10的第一区T10-1相连。上一行像素电路的第二复位晶体管T7’的第一极T71’通过第二过孔V6与第二初始信号线INIT2相连，通过第三过孔K6与第二复位晶体管T7’的第七有源层T70’的第一区相连。下一行像素电路的第一复位晶体管T1’的第一极T11’通过第二过孔V4与第一初始信号线INIT1相连，通过第三过孔K7与第一复位晶体管T1’的第一有源层T10’的第一区相连。
关于第二结构的像素电路的其余平面结构可以参照第一结构的像素电路的相关说明，故于此不再赘述。
在本示例性实施方式中，第一结构的像素电路的第二复位晶体管的有源层与下一行像素电路的第一复位晶体管的有源层连接，来实现第二复位晶体管连接第一初始信号线，第二结构的像素电路的第二复位晶体管的有源层与下一行像素电路的第一复位晶体管的有源层断开，由第二复位晶体管的有源层直接连接第二初始信号线，实现第二复位晶体管连接第二初始信号线。本 示例性实施方式提供的像素电路的版图设计，可以在衬底基板上实现第一类型的像素电路和第二类型的像素电路的间隔设置。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在衬底基板上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、形成半导体层图案。
在一些示例性实施方式中，形成半导体层图案可以包括：在衬底基板50上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖衬底基板50的第一绝缘层51，以及设置在第一绝缘层51上的半导体层，如图7B和图8B所示。
在本次工艺后，显示基板包括设置在衬底基板50上的第一绝缘层51和设置在第一绝缘层51上的半导体层，半导体层可以包括像素电路的多个晶体管的有源层，如图7C和图8C所示。在本示例性实施方式中，第一结构的像素电路的第二复位晶体管的有源层与相邻像素电路的第一复位晶体管的有源 层为一体结构，第二结构的像素电路的第二复位晶体管的有源层与相邻像素电路的第一复位晶体管的有源层相互独立。
(2)、形成第一导电层图案。
在一些示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的衬底基板50上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层52，以及设置在第二绝缘层52上的第一导电层图案。如图7D和图8D所示，第一导电层图案至少包括：第一复位控制线RST1、扫描线GT、发光控制线EML、存储电容Cst的第一电极Cst-1。第一复位控制线RST1、扫描线GT和发光控制线EML沿第一方向X延伸，存储电容Cst的第一电极Cst-1位于扫描线GT和发光控制线EML之间。在一些示例中，第一导电层可以称为第一栅金属(GATE 1)层。
在一些示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成多个晶体管的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层T10至第七有源层T70的第一区和第二区均被导体化。
(3)、形成第二导电层图案。
在一些示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基50上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层53，以及设置在第三绝缘层53上的第二导电层图案。如图7E和图8E所示，第二导电层图案至少包括：第一初始信号线INIT1、第二初始信号线INIT2、存储电容Cst的第二电极Cst-2、第一屏蔽电极BK。在一些示例中，第二导电层可以称为第二栅金属(GATE 2)层。
(4)、形成第四绝缘层图案。
在一些示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的衬底基板50上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层54。如图7F和图8F所示，第四绝缘层上设置有多个第一过孔、多个第二过孔以及多个第三过孔。多个 第一过孔内的第四绝缘层54和第三绝缘层53被刻蚀掉，暴露出第一导电层的表面，多个第二过孔内的第四绝缘层54被刻蚀掉，暴露出第二导电层的表面，多个第三过孔内的第四绝缘层54、第三绝缘层53和第二绝缘层52被刻蚀掉，暴露出半导体层的表面。
(5)、形成第三导电层图案。
在一些示例性实施方式中，形成第三导电层可以包括：在形成前述图案的衬底基板50上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层54上的第三导电层。如图7G和图8G所示，第三导电层至少包括：数据线DT、第一电源线PL1、多个晶体管的第一极和第二极。在一些示例中，第三导电层可以称为第一源漏金属(SD1)层。
在本示例中，如图7G所示，第一结构的像素电路的第二复位晶体管T7的第一极T71没有连接到第二初始信号线INIT2。如图8G所示，第二结构的像素电路的第二复位晶体管T7的第一极T71通过第二过孔V5与第二初始信号线INIT2连接。
(6)、形成第五绝缘层图案。
在一些示例性实施方式中，形成第五绝缘层图案可以包括：在形成前述图案的衬底基板50上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第三导电层的第五绝缘层55。如图7H和图8H所示，第五绝缘层55上形成有多个第四过孔F1和F2。多个第四过孔内的第五绝缘层55被去掉，暴露出第三导电层的表面。在一些示例中，第五绝缘层55可以称为平坦层。
(7)、形成第四导电层图案。
在一些示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的衬底基板50上，沉积第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成设置在第五绝缘层55上的第四导电层。如图7I和图8I所示，第四导电层图案至少包括：第一连接电极CE1、第二屏蔽电极SE。第二屏蔽电极SE通过第四过孔F2与第一电源线PL1连接，第一连接电极CE1通过第四过孔F1与第二发光控制晶体管T6的第二极T62连接。在一些示例中，第四导电层可以称为第二源漏金属(SD1)层。
在一些示例性实施方式中，后续制备流程可以包括：形成导电线层。在一些示例中，连接第一显示区的第二类型像素电路和第二显示区的第二区域发光元件的多条导电线可以为同层结构。形成导电线层可以包括：在形成第四导电层的衬底基板上涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第四导电层的第六绝缘层；然后，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第六绝缘层上的导电线层。第一显示区R1的第二类型像素电路的第一连接电极CE1与导电线连接，导电线可以从第一显示区R1延伸到第二显示区R2，以便与第二显示区R2的第二区域发光元件连接。然而，本实施例对此并不限定。在一些示例中，连接第一显示区R1的第二类型像素电路和第二显示区R2的第二区域发光元件的多条导电线可以为异层结构。或者，至少一条导电线可以由位于不同导电线层的多个导电线段连接形成。
在一些示例性实施方式中，在形成导电线层之后的制备流程可以包括：形成覆盖导电线层的平坦层；沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在平坦层上的阳极；涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。采用蒸镀或喷墨打印工艺形成有机发光层，在有机发光层上形成阴极。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件。
在一些示例性实施方式中，衬底基板50可以是柔性衬底基板，或者可以是刚性衬底基板。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一些示例中，柔性衬底基板可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料， 第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在一些示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层51、第二绝缘层52、第三绝缘层53和第四绝缘层54可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层51称为缓冲(Buffer)层，用于提高衬底基板的抗水氧能力，第二绝缘层52和第三绝缘层53称为栅绝缘(GI)层，第四绝缘层54称为层间绝缘(ILD)层。平坦层可以采用有机材料。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)。有源层可以采用多晶硅(p-Si)，即本实施例适用于LTPS薄膜晶体管。然而，本实施例对此并不限定。例如，第一结构的像素电路和第二结构的像素电路中的晶体管可以均采用氧化物薄膜晶体管。
本实施例的显示基板的结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，第一结构的像素电路和第二结构的像素电路可以包括其他数量的晶体管和存储电容，比如，7T2C结构、6T1C结构、6T2C结构或者9T2C结构、或者晶体管的数目小于7个。
本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
在一些示例性实施方式中，第一结构的像素电路和第二结构的像素电路中，第一复位晶体管T1和阈值补偿晶体管T2可以采用氧化物薄膜晶体管，其余晶体管(即驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6和第二复位晶体管T7)可以采用低温多晶硅薄膜晶体管，从而形成LTPO显示基板。在本示例中，第一复位晶体管T1和阈值补偿晶体管T2的有源层可以为同层结构，且与其余晶体管的有源层为 异层结构。第n行第一结构的像素电路的第二复位晶体管T7与第n+1行像素电路的第一复位晶体管T1的有源层为异层结构且相互隔离，第一结构的像素电路的第二复位晶体管T7和第一复位晶体管T1各自与第一初始信号线INIT1连接。第n行第二结构的像素电路的第二复位晶体管T7与第n+1行像素电路的第一复位晶体管T1的有源层为异层结构且相互隔离，第二结构的像素电路的第二复位晶体管T7与第二初始信号线INIT2连接，第一复位晶体管T1与第一初始信号线INIT1连接。在一些示例中，第一复位晶体管T1和阈值补偿晶体管T2可以为N型晶体管，其余晶体管可以为P型晶体管。在垂直于显示基板的平面内，显示基板可以包括：依次设置在衬底基板上的第一半导体层、第一导电层、第二半导体层、第二导电层、第三导电层以及第四导电层。其中，第一半导体层至少包括：多个P型晶体管的有源层；第一导电层至少包括：多个P型晶体管的栅极、存储电容的第一电极、扫描线、发光控制线以及第二复位控制线；第二半导体层至少包括：多个N型晶体管的有源层；第二导电层至少包括：存储电容的第二电极、第一复位控制线；第三导电层至少包括：多个晶体管的第一极和第二极、第一电源线、数据线、第一初始信号线和第二初始信号线；第四导电层至少包括：第一连接电极。相邻半导体层和导电层之间设置有绝缘层，相邻导电层之间设置有绝缘层。然而，本实施例对此并不限定。
图9为本公开至少一实施例的显示基板的位于第二显示区的一行发光元件和与其相连的第二类型像素电路的另一示意图。在一些示例性实施方式中，第二显示区R2关于在第一方向X上的中轴线对称。图9仅示意了第二显示区R2左半部分的一行发光元件与第一显示区R1内的第二类型像素电路的连接关系。
在一些示例性实施方式中，如图9所示，在第二显示区R2，多个第二区域发光元件40包括：多个第一发光元件41、多个第二发光元件42、多个第三发光元件43。第一发光元件41配置为发第一颜色光，第二发光元件42配置为发第二颜色光，第三发光元件43配置为发第三颜色光。在一些示例中，第一颜色光为绿(G)光，第二颜色光为红(R)光，第三颜色光为蓝(B)光。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图9所示，在第一显示区R1，多个第二类型像素电路20包括：多个第一像素电路21、多个第二像素电路22、多个第三像素电路23。多个第一发光元件41与多个第一像素电路21通过多条第一导电线La连接，多个第二发光元件42与多个第二像素电路22通过多条第二导电线Lb连接，多个第三发光元件43与多个第三像素电路23通过多条第三导电线Lc连接。例如，一个第一发光元件41与一个第一像素电路21通过一条第一导电线La连接，一个第二发光元件42与一个第二像素电路22通过一条第二导电线Lb连接，一个第三发光元件43与一个第三像素电路23通过一条第三导电线Lc连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图9所示，在一组第二区域发光元件40和一组第二类型像素电路20中，与多个第一发光元件41相连的多个第一像素电路21比与多个第二发光元件42相连的多个第二像素电路22中的每一个都更靠近第二显示区R2，且比与多个第三发光元件43相连的多个第三像素电路23中的每一个都更靠近第二显示区R2。在一些示例中，与第二发光元件42相连的第二像素电路22、与第三发光元件43相连的第三像素电路23可以均为第二结构的像素电路，第二导电线Lb和第三导电线Lc的长度均大于长度分界值。长度小于长度分界值的第一导电线La所连接的第一像素电路21可以为第一结构的像素电路，长度大于长度分界值的第一导电线La所连接的第一像素电路21可以为第二结构的像素电路。然而，本实施例对此并不限定。在一些示例中，当第一导电线La的长度均小于长度分界值，一部分第二导电线Lb和一部分第三导电线Lc的长度大于长度分界值，则第一导电线La所连接的第一像素电路21为第一结构的像素电路，长度小于长度分界值的第二导电线Lb和第三导电线Lc所连接的像素电路为第一结构的像素电路，长度大于长度分界值的第二导电线Lb和第三导电线Lc所连接的像素电路为第二结构的像素电路。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图10为本公开至少一实施例的显示基板的位于第二显示区的一行发光 元件和与其相连的第二类型像素电路的另一示意图。在一些示例性实施方式中，第二显示区R2关于在第一方向X上的中轴线对称。图9仅示意了第二显示区R2左半部分的一行发光元件与第一显示区R1内的第二类型像素电路的连接关系。
在一些示例性实施方式中，如图10所示，在一组第二区域发光元件40和一组第二类型像素电路20中，与多个第二发光元件42相连的多个第二像素电路22、与多个第一发光元件41相连的多个第一像素电路21以及与多个第三发光元件43相连的多个第三像素电路23依次交替设置。在本示例中，长度小于长度分界值的第一导电线La所连接的第一像素电路21可以为第一结构的像素电路，长度大于长度分界值的第一导电线La所连接的第一像素电路21可以为第二结构的像素电路。长度小于长度分界值的第二导电线Lb所连接的第二像素电路22可以为第一结构的像素电路，长度大于长度分界值的第二导电线Lb所连接的第二像素电路21可以为第二结构的像素电路。长度小于长度分界值的第三导电线Lc所连接的第三像素电路23可以为第一结构的像素电路，长度大于长度分界值的第三导电线Lc所连接的第三像素电路23可以为第二结构的像素电路。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
图11为本公开至少一实施例的显示基板的示意图。在一些示例性实施方式中，第一显示区R1包括辅助区Ra。辅助区Ra的面积可以小于第一显示区R1除辅助区Ra之外区域的面积。辅助区Ra围绕在第二显示区R2周围。多个第一类型像素电路和多个第一区域发光元件位于第一显示区R1。多个第一类型像素电路中的至少一个第一类型像素电路可以与多个第一区域发光元件中的至少一个第一区域发光元件连接，且至少一个第一类型像素电路在衬底基板上的正投影与至少一个第一区域发光元件在衬底基板上的正投影可以至少部分重叠。第一类型像素电路可以为第一结构的像素电路。多个第二类型像素电路位于辅助区Ra。多个第二区域发光元件位于第二显示区。多个第二类型像素电路中的至少一个第二类型像素电路可以与多个第二区域发光元 件中的至少一个第二区域发光元件通过导电线连接。长度小于长度分界值的导电线所连接的第二类型像素电路可以为第一结构的像素电路，长度大于或等于长度分界值的导电线所连接的第二类型像素电路可以为第二结构的像素电路。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。本实施方式所示的结构(或方法)可以与其它实施方式所示的结构(或方法)适当地组合。
本公开实施例还提供一种显示基板的制备方法，包括：在衬底基板的第一显示区形成多个第二类型像素电路，在第二显示区形成多个第二区域发光元件，第一显示区位于第二显示区的至少一侧。其中，多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路。多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接。多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接。第二组导电线的长度大于第一组导电线的长度。
关于本实施例的显示基板的制备方法可以参照前述实施例的说明，故于此不再赘述。
图12为本公开至少一实施例的显示装置的示意图。如图12所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (23)

  1. 一种显示基板，包括：
    衬底基板，具有第一显示区和第二显示区，所述第一显示区位于所述第二显示区的至少一侧；
    多个第二区域发光元件，位于所述第二显示区；
    多个第二类型像素电路，位于所述第一显示区；
    所述多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路；所述多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接；
    所述多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接；所述第二组导电线的长度大于所述第一组导电线的长度。
  2. 根据权利要求1所述的显示基板，其中，所述第一结构的像素电路与第一初始信号线连接，所述第二结构的像素电路与第一初始信号线和第二初始信号线连接；所述第一初始信号线和第二初始信号线提供不同的初始信号。
  3. 根据权利要求1或2所述的显示基板，还包括：
    多个第一区域发光元件，位于所述第一显示区；
    多个第一类型像素电路，位于所述第一显示区；
    所述多个第一类型像素电路中的至少一个第一类型像素电路与所述多个第一区域发光元件中的至少一个第一区域发光元件连接，且所述至少一个第一类型像素电路在所述衬底基板上的正投影与所述至少一个第一区域发光元件在所述衬底基板上的正投影至少部分重叠；
    所述多个第一类型像素电路均为第一结构的像素电路。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述第一结构的像素电路包括：驱动晶体管、第一复位晶体管和第二复位晶体管；
    所述第一复位晶体管的栅极与第一复位控制线连接，所述第一复位晶体管的第一极与驱动晶体管的栅极连接，所述第一复位晶体管的第二极与第一 初始信号线连接；
    所述第二复位晶体管的栅极与第二复位控制线连接，所述第二复位晶体管的第一极与发光元件的第一极连接，所述第二复位晶体管的第二极与第一初始信号线连接。
  5. 根据权利要求1至4中任一项所述的显示基板，其中，所述第二结构的像素电路包括：驱动晶体管、第一复位晶体管和第二复位晶体管；
    所述第一复位晶体管的栅极与第一复位控制线连接，所述第一复位晶体管的第一极与驱动晶体管的栅极连接，所述第一复位晶体管的第二极与第一初始信号线连接；
    所述第二复位晶体管的栅极与第二复位控制线连接，所述第二复位晶体管的第一极与发光元件的第一极连接，所述第二复位晶体管的第二极与第二初始信号线连接；
    所述第二初始信号线提供的第二初始信号不同于所述第一初始信号线提供的第一初始信号。
  6. 根据权利要求5所述的显示基板，其中，所述第一初始信号线提供的第一初始信号为恒压信号。
  7. 根据权利要求5所述的显示基板，其中，所述第二初始信号线提供的第二初始信号为恒压信号，且所述第二初始信号大于所述第一初始信号线提供的第一初始信号。
  8. 根据权利要求5所述的显示基板，其中，所述第二结构的像素电路所连接的第二初始信号线提供的第二初始信号的大小，与所述第二结构的像素电路连接的第二组导电线的长度呈正比。
  9. 根据权利要求5至8中任一项所述的显示基板，其中，所述第一结构的像素电路或第二结构的像素电路还包括：数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管和第二发光控制晶体管；
    所述数据写入晶体管的栅极与扫描线连接，所述数据写入晶体管的第一极与数据线连接，所述数据写入晶体管的第二极与驱动晶体管的第一极连接；
    所述阈值补偿晶体管的栅极与扫描线连接，所述阈值补偿晶体管的第一 极与驱动晶体管的栅极连接，所述阈值补偿晶体管的第二极与驱动晶体管的第二极连接；
    所述第一发光控制晶体管的栅极与发光控制线连接，所述第一发光控制晶体管的第一极与第一电源线连接，所述第一发光控制晶体管的第二极与驱动晶体管的第一极连接；
    所述第二发光控制晶体管的栅极与发光控制线连接，所述第二发光控制晶体管的第一极与驱动晶体管的第二极连接，所述第二发光控制晶体管的第二极与发光元件的第一极连接。
  10. 根据权利要求9所述的显示基板，其中，在垂直于显示基板的平面内，所述显示基板至少包括：设置在衬底基板上的半导体层、第一导电层、第二导电层和第三导电层；
    所述半导体层至少包括：多个晶体管的有源层；
    所述第一导电层至少包括：多个晶体管的栅极和存储电容的第一电极、扫描线、发光控制线、第一复位控制线和第二复位控制线；
    所述第二导电层至少包括：存储电容的第二电极、第一初始信号线、第二初始信号线；
    所述第三导电层至少包括：多个晶体管的第一极和第二极、第一电源线、数据线。
  11. 根据权利要求10所述的显示基板，其中，所述第一结构的像素电路的第一复位晶体管和第二复位晶体管的有源层为一体结构；第n行第一结构的像素电路的第二复位晶体管与第n+1行像素电路的第一复位晶体管的有源层为一体结构，n为正整数。
  12. 根据权利要求10或11所述的显示基板，其中，所述第二结构的像素电路的第一复位晶体管和第二复位晶体管的有源层为一体结构；第n行第二结构的像素电路的第二复位晶体管的有源层与第n+1行像素电路的第一复位晶体管的有源层没有连接，n为正整数。
  13. 根据权利要求10至12中任一项所述的显示基板，其中，所述第三导电层包括：所述第二结构的像素电路的第二复位晶体管的第二极、所述第 一结构的像素电路的第二复位晶体管的第二极；
    所述第二结构的像素电路的第二复位晶体管的第二极通过过孔与第二初始信号线连接；
    所述第一结构的像素电路的第二复位晶体管的第二极没有与第二初始信号线连接。
  14. 根据权利要求1至13中任一项所述的显示基板，其中，所述第一组导电线和第二组导电线采用透明导电材料。
  15. 根据权利要求1至14中任一项所述的显示基板，其中，多个第二类型像素电路间隔分布在多个第一类型像素电路之间。
  16. 根据权利要求15所述的显示基板，其中，在多个第一类型像素电路和多个第二类型像素电路中，任一像素电路在第一方向上的尺寸小于第一区域发光元件在第一方向上的尺寸。
  17. 根据权利要求15或16所述的显示基板，其中，所述多个第二区域发光元件包括多组第二区域发光元件，每组中的第二区域发光元件沿第一方向排布，多组第二区域发光元件沿第二方向排布；
    多个第二类型像素电路包括多组第二类型像素电路，每组中的第二类型像素电路沿第一方向排布，多组第二类型像素电路沿第二方向排布；
    多个第二区域发光元件至少包括：多个第一发光元件、多个第二发光元件和多个第三发光元件；
    多个第二类型像素电路包括：多个第一像素电路、多个第二像素电路、多个第三像素电路；多个第一发光元件与多个第一像素电路连接，多个第二发光元件与多个第二像素电路连接，多个第三发光元件与多个第三像素电路连接；
    在至少一组第二区域发光元件和至少一组第二类型像素电路中，与多个第一发光元件相连的多个第一像素电路比与多个第二发光元件相连的多个第二像素电路中的每一个都更靠近所述第二显示区，且比与多个第三发光元件相连的多个第三像素电路中的每一个都更所述靠近第二显示区。
  18. 根据权利要求17所述的显示基板，其中，通过第二组导电线与第二 发光元件连接的第二像素电路为第二结构的像素电路，通过第二组导电线与第三发光元件连接的第三像素电路为第二结构的像素电路，通过第一组导电线与第一发光元件连接的第一像素电路为第一结构的像素电路，通过第二组导电线与第一发光元件连接的第一像素电路为第二结构的像素电路。
  19. 根据权利要求18所述的显示基板，其中，所述第一发光元件配置为发绿光，所述第二发光元件和第三发光元件之一配置为发红光，所述第二发光元件和所述第三发光元件之另一配置为发蓝光。
  20. 根据权利要求1至19中任一项所述的显示基板，其中，所述第一组导电线的长度小于长度分界值，所述第二组导电线的长度大于或等于所述长度分界值；所述长度分界值与所述第二组导电线的最大长度的比值约为0.25至0.35。
  21. 一种显示装置，包括如权利要求1至20中任一项所述的显示基板。
  22. 根据权利要求21所述的显示装置，还包括：感光传感器，位于所述显示基板的一侧，所述感光传感器在所述显示基板上的正投影与所述显示基板的第二显示区存在交叠。
  23. 一种显示基板的制备方法，包括：
    在衬底基板的第一显示区形成多个第二类型像素电路，在第二显示区形成多个第二区域发光元件，所述第一显示区位于第二显示区的至少一侧；
    其中，所述多个第二类型像素电路包括多个第一结构的像素电路和多个第二结构的像素电路；所述多个第一结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第一组导电线连接；所述多个第二结构的像素电路中的至少一个像素电路与多个第二区域发光元件中的至少一个发光元件通过第二组导电线连接；所述第二组导电线的长度大于所述第一组导电线的长度。
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CN111969027A (zh) * 2020-08-28 2020-11-20 合肥维信诺科技有限公司 显示面板以及显示装置
CN112259589A (zh) * 2020-10-22 2021-01-22 Oppo广东移动通信有限公司 显示屏、电子装置和制造方法

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