WO2022179189A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022179189A1
WO2022179189A1 PCT/CN2021/130250 CN2021130250W WO2022179189A1 WO 2022179189 A1 WO2022179189 A1 WO 2022179189A1 CN 2021130250 W CN2021130250 W CN 2021130250W WO 2022179189 A1 WO2022179189 A1 WO 2022179189A1
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layer
metal layer
transistor
insulating layer
signal line
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PCT/CN2021/130250
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English (en)
French (fr)
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丁录科
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/799,918 priority Critical patent/US20240032355A1/en
Publication of WO2022179189A1 publication Critical patent/WO2022179189A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • the large-screen terminal can improve the user's gaming and entertainment experience, which is conducive to split-screen display, and the whole machine has a higher sense of technology, which can bring a stronger visual impact to the user.
  • Under-screen camera products have become a more potential display device design due to their high screen-to-body ratio and less impact on visual images from cameras.
  • the display panel will block the light entering the camera, the Selfie and face recognition functions of the front camera will be affected.
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a buffer layer disposed on the base substrate, a semiconductor layer disposed on the buffer layer, a first insulating layer covering the semiconductor layer, a first gate metal layer arranged on the first insulating layer, a second insulating layer covering the first gate metal layer, arranged on the second insulating layer a second gate metal layer, a third insulating layer covering the second gate metal layer, a first source-drain metal layer disposed on the third insulating layer, and a flat layer covering the first source-drain metal layer ; At least one of the first gate metal layer and the second gate metal layer includes a first power supply line, the first power supply line extends along a first direction, the first source-drain metal layer includes a data line, so The data line extends along a second direction, and the first direction intersects with the second direction.
  • At least one of the first gate metal layer and the second gate metal layer further includes a light emission control signal line and at least one scan signal line, and both the light emission control signal line and the scan signal line are Extending along a first direction, the first power supply line is located between the light emission control signal line and at least one scan signal line.
  • the first power cord includes at least one first bent portion extending along the second direction.
  • the first source-drain metal layer further includes a second power supply line extending along a second direction, the first power supply line passing through an overpass on the third insulating layer A hole, or a via hole on the third insulating layer and the second insulating layer, is electrically connected to the second power line.
  • the first source-drain metal layer further includes an eighth connection line extending along the second direction, and the eighth connection line is on the base substrate.
  • the orthographic projection intersects with the orthographic projection of the first power line on the base substrate.
  • the semiconductor layer includes a third channel region, a fourth channel region, a fifth channel region, a sixth channel region and a seventh channel region, the third channel region, The fourth channel region and the sixth channel region both extend along the first direction, the seventh channel region extends along the second direction, and the fifth channel region includes first sub-channels connected to each other A channel region and a second sub-channel region, the first sub-channel region extending along the first direction, and the second sub-channel region extending along the second direction.
  • the semiconductor layer includes a reference signal line for providing a reference voltage signal, the reference signal line extending along the first direction.
  • the second gate metal layer includes an initial signal line, and the initial signal line is used to provide an initial voltage signal; the initial signal line includes at least one third bent portion, the third bent portion The fold extends along the second direction.
  • the display substrate includes a display area and a mounting area
  • the mounting area includes a first pixel circuit
  • the display area includes a second pixel circuit
  • the first pixel circuit and the first pixel circuit The two pixel circuits each include at least one transistor, and the number of transistors in the first pixel circuit is less than the number of transistors in the second pixel circuit.
  • the display substrate further includes an anode disposed on the flat layer, wherein: the anode includes a first anode and a second anode, the first anode is located in the mounting area, the The second anode is located in the display area, and the area of the orthographic projection of the first anode on the base substrate is smaller than the area of the orthographic projection of the second anode on the base substrate.
  • An embodiment of the present disclosure also provides a display device, including: the display substrate as described above.
  • An embodiment of the present disclosure also provides a method for manufacturing a display substrate, including: forming a driving structure layer on a base substrate, the driving structure layer including a buffer layer disposed on the base substrate, and a buffer layer disposed on the buffer layer. a semiconductor layer on the layer, a first insulating layer covering the semiconductor layer, a first gate metal layer disposed on the first insulating layer, a second insulating layer covering the first gate metal layer, a second gate metal layer on the second insulating layer, a third insulating layer covering the second gate metal layer, a first source-drain metal layer disposed on the third insulating layer, and covering the first source a flat layer of the drain metal layer; at least one of the first gate metal layer and the second gate metal layer includes a first power line extending along a first direction, the first source-drain metal
  • the layer includes data lines extending along a second direction, and the first direction intersects with the second direction; and a light-emitting element is formed on the driving structure layer.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure
  • Fig. 2 is the enlarged structure schematic diagram of A area in Fig. 1;
  • FIG. 3 is a schematic cross-sectional structural diagram of a display substrate according to an embodiment of the disclosure.
  • FIG. 4 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a semiconductor layer of a display substrate according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a first gate metal layer of a display substrate according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a second gate metal layer of a display substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a first source-drain metal layer of a display substrate according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of an anode layer of a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a pixel definition layer of a display substrate according to an embodiment of the present disclosure
  • FIG. 11 is a schematic structural diagram of a first pixel circuit according to an embodiment of the present disclosure.
  • FIG. 12 is an equivalent circuit diagram of a first pixel circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a second pixel circuit according to an embodiment of the present disclosure.
  • FIG. 14 is an equivalent circuit diagram of a second pixel circuit according to an embodiment of the present disclosure.
  • FIG. 15 is a working timing diagram of the second pixel circuit shown in FIG. 14;
  • FIG. 16 is a flowchart of a method for fabricating a display substrate according to an embodiment of the present disclosure
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is an enlarged schematic structural schematic diagram of area A in FIG. 1
  • FIG. 3 is a schematic cross-sectional structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display substrate including a display area 100 .
  • the display substrate On a plane perpendicular to the display substrate, the display substrate includes a base substrate 201, a buffer layer disposed on the base substrate 201, a semiconductor layer disposed on the buffer layer, a first insulating layer covering the semiconductor layer, a first insulating layer disposed on the first a first gate metal layer on the insulating layer, a second insulating layer covering the first gate metal layer, a second gate metal layer arranged on the second insulating layer, a third insulating layer covering the second gate metal layer, a first source-drain metal layer on the third insulating layer and a flat layer covering the first source-drain metal layer.
  • At least one of the first gate metal layer and the second gate metal layer includes a first power supply line VDD1, the first power supply line VDD1 extends along the first direction X, and the first source-drain metal layer includes a data line (as shown in FIG. 2 ).
  • the first data line Data1 or the second data line Data2), the data lines extend along the second direction Y, and the first direction X and the second direction Y intersect.
  • the first direction X and the second direction Y may lie in the same plane, and the first direction X may be perpendicular to the second direction Y.
  • the first direction X may be the row direction, which is parallel to the extension direction of the scan lines; the second direction Y may be the column direction, which is parallel to the extension direction of the data lines.
  • At least one of the first gate metal layer and the second gate metal layer further includes an emission control signal line EM and at least one scan signal line (as shown in FIG. 4 )
  • the first scanning signal line G1, the second scanning signal line G2 and the third scanning signal line G3), the light-emitting control signal line EM and the scanning signal line all extend along the first direction X, and the first power line VDD1 is located on the light-emitting control signal line EM and at least one scan signal line.
  • the first source-drain metal layer further includes an eighth connection line L8 , the eighth connection line L8 extends along the second direction Y, and the eighth connection line L8 is located on the base substrate 201 .
  • the orthographic projection on the first power supply line VDD1 intersects with the orthographic projection of the first power supply line VDD1 on the base substrate 201 .
  • the first source-drain metal layer further includes a second power supply line VDD2, the second power supply line VDD2 extends along the second direction Y, and the first power supply line VDD1 passes through the third insulating layer
  • the via hole on the third insulating layer and the via hole on the second insulating layer are electrically connected to the second power line VDD2.
  • the first power line VDD1 includes at least one first bending portion, and the first bending portion extends along the second direction Y, that is, the extending direction of the first bending portion is the same as that of the first bending portion.
  • the extending directions of the second power supply lines VDD2 are parallel.
  • the semiconductor layer includes a reference signal line REF for providing a reference voltage signal, and the reference signal line REF extends along the first direction X.
  • the semiconductor layer includes a third channel region, a fourth channel region, a fifth channel region, a sixth channel region and a seventh channel region, the third channel region
  • the channel region, the fourth channel region and the sixth channel region all extend along the first direction X
  • the seventh channel region extends along the second direction Y
  • the fifth channel region includes the first sub-channel region and
  • the first sub-channel region extends along the first direction X
  • the second sub-channel region extends along the second direction Y.
  • the display area includes a plurality of sub-pixels arranged in an array, and each sub-pixel is divided into a first area and a second area along the second direction Y from top to bottom. and the third region, wherein the fifth channel region and the sixth channel region are located in the I region, the seventh channel region is located in the II region, the third channel region, the fourth channel region and the reference signal line REF are located in Zone III.
  • the fifth channel region is located on the side of the sixth channel region close to the second region, and the seventh channel region is located on the edge of the second region along the first direction X.
  • the third channel region is located on the side of the third region close to the edge of the II region, and the fourth channel region is located between the reference signal line REF and the third channel region.
  • the first gate metal layer includes a first scan signal line G1 , a second scan signal line G2 , a third scan signal line G3 , a first power supply line VDD1 , a light emission control signal Line EM and the third plate C2-1 of the second capacitor C2, wherein the light-emitting control signal line EM, the first power line VDD1 and the third scanning signal line G3 are located in the first region, and the third plate of the second capacitor C2 C2-1 is located in the second area, and the first scan signal line G1 and the second scan signal line G2 are located in the third area.
  • the light emission control signal line EM is located on the side of the first power supply line VDD1 away from the second region, and the first power supply line VDD1 is located on the side of the third scan signal line G3 away from the second region.
  • the third scan signal line G3 is located on the side of the first area close to the edge of the second area, and the first scan signal line G1 is located on the side of the second scan signal line G2 close to the second area.
  • the first scan signal line G1 includes at least two first protrusions, and the two first protrusions are both located at a portion of the first scan signal line G1 close to the second region II. side, the orthographic projection of the two first protrusions on the base substrate and the orthographic projection of the third channel region on the base substrate include an overlapping area, and the two first protrusions form the third transistor T3 the double gate structure.
  • the second scan signal line G2 includes at least two second protrusions, both of which are located at a portion of the second scan signal line G2 close to the second region II. side, the orthographic projection of the two second protrusions on the base substrate and the orthographic projection of the fourth channel region on the base substrate include an overlapping area, and the two second protrusions form the fourth transistor T4 the double gate structure.
  • the third scan signal line G3 includes at least two third protrusions, and the two third protrusions include an upper sub-bump and a lower sub-bump, wherein, The upper sub-bump is located on the side of the third scanning signal line G3 away from the second region, and the orthographic projection of the upper sub-bump on the substrate is the same as the first sub-channel region in the fifth channel region on the substrate
  • the orthographic projection on the substrate includes an overlapping area
  • the lower sub-bump is located on the side of the third scanning signal line G3 close to the second region
  • the orthographic projection of the lower sub-bump on the base substrate is the same as the second sub-bump in the fifth channel region.
  • the orthographic projections of the two sub-channel regions on the base substrate include overlapping regions, and the two third protrusions form the double gate structure of the fifth transistor T5.
  • the third scan signal line G3 includes at least one second bending portion G3-3, and the second bending portion G3-3 extends along the second direction Y, that is, the third The extension direction of the bent portion INT-3 is parallel to the extension direction of the second power supply line VDD2.
  • the side of the light-emitting control signal line EM close to the second region includes at least one fourth protrusion, wherein the fourth protrusion is located at the light-emitting control signal line EM near the second region
  • the orthographic projection of the fourth protrusion on the base substrate and the orthographic projection of the sixth channel region on the base substrate include an overlapping area, that is, the fourth protrusion forms the control of the sixth transistor T6 Pole 61.
  • the third electrode plate C2-1 includes a first body region C2-11, a writing potential region C2-12, and an enlarged overlapping area region C2-13, the enlarged overlapping area
  • the area C2-13 is located on the side of the third pole plate C2-1 close to the first area
  • the first main body area C2-11 and the write potential area C2-12 are located on the side of the third pole plate C2-1 close to the third area
  • the first body region C2-11, the writing potential region C2-12 and the enlarged overlapping area region C2-13 form a "concave" shape structure.
  • the third electrode plate C2-1 is disposed between the first power supply line VDD1 and at least one scan signal line.
  • the third electrode plate C2-1 is disposed Between the first power supply line VDD1 and the first scanning signal line G1, or, the third electrode plate C2-1 is disposed between the first power supply line VDD1 and the second scanning signal line G2.
  • the second gate metal layer includes a fourth electrode plate C2-2 of the second capacitor C2, wherein the fourth electrode plate C2-2 is located in the second region.
  • the fourth electrode plate C2-2 includes a second body region C2-21 and a signal connection region C2-22, and the signal connection region C2-22 is located on the fourth electrode plate C2- 2.
  • the signal connection region C2-22 is connected to the seventh connection line L7 through the via hole on the third insulating layer, for transmitting the signal to the seventh connection line L7, and through the seventh connection Line L7 transmits the signal to the anode of the organic light emitting diode.
  • the second gate metal layer further includes an initial signal line INT, wherein the initial signal line INT extends along the first direction X, and the first source-drain metal layer includes data lines (such as For the first data line Data1 or the second data line Data2) in FIG. 2 , the data line extends along the second direction Y, and the first direction X and the second direction Y intersect.
  • the initial signal line INT extends along the first direction X
  • the first source-drain metal layer includes data lines (such as For the first data line Data1 or the second data line Data2) in FIG. 2 , the data line extends along the second direction Y, and the first direction X and the second direction Y intersect.
  • the initial signal line INT includes at least one third bending part INT-3, and the third bending part INT-3 extends along the second direction Y, that is, the third bending part
  • the extending direction of the portion INT-3 is parallel to the extending direction of the second power supply line VDD2.
  • the first source-drain metal layer includes a second power line VDD2 , a second data line Data2 , at least one connection line, and source and drain electrodes of at least one transistor, wherein , both the second power line VDD2 and the second data line Data2 extend along the second direction Y, and the second power line VDD2 and the second data line Data2 are located on one side of the sub-pixel, and the second power line VDD2 is located on the second data line Data2 The side near the edge of the subpixel.
  • the first source-drain metal layer includes a fifth connection line L5, a sixth connection line L6, a seventh connection line L7, an eighth connection line L8, and a
  • the second pole 63, the first pole 72 and the second pole 73 of the seventh transistor T7, the first pole 32 of the third transistor T3 and the second data signal line Data2 are connected to each other to form an integral structure, and the second pole of the third transistor T3 33.
  • the second pole 43 of the fourth transistor T4 and the fifth connecting line L5 are connected to each other to form an integral structure, and the fifth connecting line L5 is connected to the control electrode of the seventh transistor T7 through the second insulating layer and the via hole on the third insulating layer. 71.
  • the third plate C2-1 of the second capacitor C2 is connected.
  • the first electrode 42 of the fourth transistor T4 and the sixth connection line L6 are connected to each other to form an integral structure, and the sixth connection line L6 is connected to the reference signal line REF through the via holes on the first insulating layer, the second insulating layer and the third insulating layer. connect.
  • the first pole 52 of the fifth transistor T5 is electrically connected to the initial signal line INT through the via hole on the third insulating layer, the second pole 53 of the fifth transistor T5 and the seventh connection line L7 are connected to each other to form an integral structure, and the seventh connection The line L7 is electrically connected to the fourth plate C2-2 of the second capacitor C2 through the via hole on the third insulating layer.
  • the first electrode 72 of the seventh transistor T7 is electrically connected to the fourth electrode plate C2-2 of the second capacitor C2 through a via hole on the third insulating layer.
  • the first pole 62 of the sixth transistor T6 is electrically connected to the first power supply line VDD1 through the via holes on the second insulating layer and the third insulating layer, and the second pole 63 of the sixth transistor T6 is connected to the eighth connection lines L8, seventh
  • the second poles 73 of the transistor T7 are connected to each other to form an integral structure.
  • the display substrate further includes a mounting area 101 located in the display area 100 .
  • the installation area 101 may be an under-screen camera area.
  • the pixel resolution of the display area 100 is greater than the pixel resolution of the installation area 101.
  • the pixel resolution of the display area 100 may be 2K resolution
  • the pixel resolution of the installation area 101 may be 1080 resolution.
  • the display area 100 includes a plurality of first metal wires
  • the installation area 101 includes a plurality of second metal wires corresponding to the plurality of first metal wires of the display area 100 one-to-one, wherein , the line width of each second metal trace is smaller than or equal to that of the corresponding first metal trace.
  • the display substrate on a plane perpendicular to the display substrate, includes a base substrate 201, a plurality of metal layers on the base substrate 201, and a plurality of metal layers disposed between the plurality of metal layers
  • the plurality of metal layers include a first power line VDD1 and a second power line VDD2, the first power line VDD1 extends along the first direction X, the second power line VDD2 extends along the second direction Y, the first direction X and the The second direction Y intersects;
  • the second power supply line VDD2 is only located in the display area 100, and the first power supply line VDD1 includes a first connection part VDD1-1 located in the mounting area 101 and a second connection part VDD1-1 located in the display area 100 and connected to the first connection part VDD1-1
  • the connection part VDD1-2, the second connection part VDD1-2 and the second power supply line VDD2 are connected to each other through via holes on the insulating layer.
  • the display substrate provided by the embodiment of the present disclosure, by not arranging the second power supply line VDD2 in the installation area 101, the area occupied by the metal traces in the installation area 101 is effectively reduced, the light transmittance of the installation area 101 is increased, and the front Camera Selfie, face recognition and other camera functions.
  • the sub-pixel of the mounting area 101 includes a first anode AN1
  • the sub-pixel of the display area 100 includes a second anode AN2
  • the first anode AN1 is connected to the thirteenth via V13 through the thirteenth via V13
  • the fourth connection line L4 is connected
  • the second anode AN2 is connected to the seventh connection line L7 through the fourteenth via hole V14.
  • the area of the orthographic projection of the first anode AN1 on the base substrate is smaller than the area of the orthographic projection of the second anode AN2 on the base substrate.
  • the mounting area 101 includes a plurality of first pixel opening areas 1011
  • the display area 100 includes a plurality of second pixel opening areas 1001 .
  • the opening size of the first pixel opening area 1011 and the opening size of the second pixel opening area 1001 may be the same.
  • the first power line VDD1 further includes a first bending portion VDD1-3 connected between the first connection portion VDD1-1 and the second connection portion VDD1-2,
  • the first bent portion VDD1-3 is configured such that the distance h1 between the first connection portion VDD1-1 and the first pixel opening region 1011 is smaller than the distance between the second connection portion VDD1-2 and the second pixel opening region 1001 h2.
  • the display substrate may include a driving structure layer 202 disposed on a base substrate 201 , and the driving structure layer 202 is disposed away from the substrate.
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the base substrate 201 may be a flexible substrate, or may be a rigid substrate.
  • the driving structure layer 202 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit.
  • each sub-pixel includes one driving transistor 210 and one storage capacitor 211 as an example for illustration.
  • the driving structure layer 202 of each sub-pixel may include: a buffer layer disposed on the base substrate 201; an active layer disposed on the buffer layer; a first insulating layer covering the active layer; a first gate metal layer arranged on the first insulating layer; a second insulating layer covering the first gate metal layer; a second gate metal layer arranged on the second insulating layer; a third insulating layer covering the second gate metal layer layer, the first insulating layer, the second insulating layer and the third insulating layer are provided with via holes, and the via holes expose the active layer; the first source-drain metal layer disposed on the third insulating layer, the first source-drain metal layer
  • the layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer through via holes; the flat layer covering the aforementioned structure is provided with via holes, and the via holes expose the drain electrode of the driving transistor 210 .
  • the driving structure layer of the mounting area 101 includes a first pixel circuit
  • the driving structure layer of the display area 100 includes a second pixel circuit
  • the first pixel circuit and the second pixel circuit are respectively At least one transistor is included, and the number of transistors in the first pixel circuit is less than the number of transistors in the second pixel circuit.
  • the display substrate provided by the embodiment of the present disclosure, by arranging the first pixel circuit in the driving structure layer of the mounting area 101, and arranging the second pixel circuit in the driving structure layer of the display area 100, the number of transistors in the first pixel circuit is small.
  • the number of transistors in the second pixel circuit effectively reduces the area occupied by metal traces in the installation area 101 , increases the light transmittance of the installation area 101 , and improves the camera functions such as Selfie and face recognition of the front camera.
  • the first pixel circuit may adopt a design structure such as 2T1C, 3T1C, or 5T1C
  • the second pixel circuit may adopt a design structure such as 3T1C, 5T1C, or 7T1C, which is not limited in this embodiment of the present disclosure.
  • the first pixel circuit may include a first writing sub-circuit and a first driving sub-circuit.
  • the first writing sub-circuit is respectively connected to the first data signal line Data1, the first scanning signal line G1, the first node N1 and the second node N2, and is configured to be controlled by the signal of the first scanning signal line G1 , the signal of the first data signal line Data1 is supplied to the first node N1, and the voltage between the first node N1 and the second node N2 is stored.
  • the first driving sub-circuit is respectively connected to the first power supply line VDD1, the first node N1 and the second node N2, and is configured to generate a driving current for driving the first light-emitting element D1 to emit light.
  • the first writing sub-circuit includes a first transistor T1 and a first capacitor C1
  • the first driving sub-circuit includes a second transistor T2, wherein the first transistor T1 is a switch
  • the second transistor T2 is a driving transistor
  • the first capacitor C1 is a storage capacitor.
  • the control electrode of the first transistor T1 is electrically connected to the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected to the first data signal line Data1, and the second electrode of the first transistor T1 is electrically connected to the first node N1 Electrical connection;
  • the control pole of the second transistor T2 is electrically connected to the first node N1, the first pole of the second transistor T2 is electrically connected to the first power supply line VDD1, and the second pole of the second transistor T2 is electrically connected to the second node N2
  • One end of the first light-emitting element D1 is electrically connected to the second node N2, and the other end of the first light-emitting element D1 is electrically connected to the voltage regulator line VSS;
  • one end of the first capacitor C1 is electrically connected to the first node N1, and the first capacitor C1 The other end is electrically connected to the second node N2.
  • the working process of the first pixel circuit may include: a scan signal of the first scan signal line G1
  • the first transistor T1 is controlled to be turned on, and the data signal of the first data signal line Data1 enters the control electrode of the second transistor T2 and the first capacitor C1 through the first transistor T1, and then the first transistor T1 is closed.
  • the gate voltage of the second transistor T2 can continue to maintain the data signal voltage, so that the second transistor T2 is turned on, and the driving current enters the first light-emitting element D1 through the second transistor T2 to drive the first light-emitting element D1 to emit light.
  • the second pixel circuit may include a second writing subcircuit, a second driving subcircuit, a reset subcircuit, a compensation subcircuit, and a light emission control subcircuit.
  • the second writing sub-circuit is respectively connected to the second data signal line Data1, the first scanning signal line G1, the third node N3 and the fourth node N4, and is configured to be controlled by the signal of the first scanning signal line G1 , the signal of the second data signal line Data2 is supplied to the third node N3, and the voltage between the third node N3 and the second node N4 is stored.
  • the second driving subcircuit is respectively connected to the third node N3, the fourth node N4 and the fifth node N5, and is configured to compensate the voltage of the fourth node N4 under the control of the third node N3 and the fifth node N5; And under the control of the third node N3 and the fourth node N4, a driving current for driving the first light-emitting element D1 to emit light is generated.
  • the reset sub-circuit is respectively connected with the third scanning signal line G3, the initial signal line INT and the fourth node N4, and is configured to provide the fourth node N4 with the signal of the initial signal line INT under the control of the signal of the third scanning signal line G3. Signal.
  • the compensation sub-circuit is respectively connected to the second scanning signal line G2, the reference signal line REF and the third node N3, and is configured to provide the third node N3 with the reference signal line REF under the control of the signal of the second scanning signal line G2.
  • the light emission control sub-circuit is respectively connected to the light emission control signal line EM, the second power supply line VDD2 and the fifth node N5, and is configured to provide the second power supply line VDD2 to the fifth node N5 under the control of the signal of the light emission control signal line EM supply voltage.
  • the second writing sub-circuit includes a third transistor T3 and a second capacitor C2
  • the compensation sub-circuit includes a fourth transistor T4
  • the reset sub-circuit includes a fifth transistor T5, and emits light
  • the control sub-circuit includes a sixth transistor T6, and the second driving sub-circuit includes a seventh transistor T7.
  • the third transistor T3, the fourth transistor T4, the fifth transistor T5 to the sixth transistor T6 are switching transistors
  • the seventh transistor T7 is a driving transistor
  • the second capacitor C2 is a storage capacitor.
  • the control electrode of the third transistor T3 is electrically connected to the first scan signal line G1, the first electrode of the third transistor T3 is electrically connected to the second data signal line Data2, and the second electrode of the third transistor T3 is electrically connected to the third node N3 Electrical connection;
  • the control electrode of the fourth transistor T4 is electrically connected to the second scan signal line G2, the first electrode of the fourth transistor T4 is electrically connected to the reference signal line REF, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3 connected;
  • the control electrode of the fifth transistor T5 is electrically connected to the third scan signal line G3, the first electrode of the fifth transistor T5 is electrically connected to the initial signal line INT, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4 ;
  • the control electrode of the sixth transistor T6 is electrically connected to the light-emitting control signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the second power supply line VDD2, and the second electrode
  • the working process of the second pixel circuit may include:
  • the first stage A1 is called the reset stage.
  • the signal of the first scanning signal line G1 is a low-level signal, and the signals of the second scanning signal line G2, the third scanning signal line G3 and the light-emitting control signal line EM are high-level signals.
  • the signal of the third scanning signal line G3 is a high-level signal, which turns on the fifth transistor T5, and the initial voltage signal of the initial signal line INT is supplied to the fourth node N4 to initialize the second capacitor C2 and clear the second capacitor C2 Central data voltage.
  • the signal of the first scanning signal line G1 is a low level signal, so that the third transistor T3 is turned off, and the second light-emitting element D2 does not emit light at this stage.
  • the second stage A2 is called the threshold compensation stage, the signals of the first scanning signal line G1 and the third scanning signal line G3 are low-level signals, and the signals of the second scanning signal line G2 and the light-emitting control signal line EM are high-level signals Signal.
  • the second scanning signal line G2 is a high-level signal, which turns on the fourth transistor T4, and the reference voltage signal of the reference signal line REF is written into the third node N3, thereby turning on the seventh transistor T7.
  • the signal of the light-emitting control signal line EM is a high-level signal, so that the sixth transistor T6 is turned on.
  • the power supply voltage of the second power line VDD2 is charged to the seventh transistor T7, and the voltage of the fourth node N4 is continuously raised until the seventh
  • the gate-source voltage Vgs of the transistor T7 reaches the threshold voltage Vth of the seventh transistor T7, the seventh transistor T7 is automatically turned off.
  • the third stage A3 is called the data writing stage.
  • the signals of the second scanning signal line G2, the third scanning signal line G3 and the light-emitting control signal line EM are low-level signals, and the signals of the first scanning signal line G1 are high-level signals. flat signal.
  • the signal of the light-emitting control signal line EM is a low-level signal, so that the sixth transistor T6 is turned off, and the signal of the first scanning signal line G1 is a high-level signal, so that the third transistor T3 is turned on, and the second data signal line Data2 is turned on.
  • the data signal is written into the third node N3 through the third transistor T3.
  • the fourth stage A4 is called the light-emitting stage.
  • the signals of the first scanning signal line G1, the second scanning signal line G2 and the third scanning signal line G3 are low-level signals, and the signals of the light-emitting control signal line EM are high-level signals. .
  • the signal of the light-emitting control signal line EM is a high-level signal, so that the sixth transistor T6 is turned on. Due to the storage function of the second capacitor C2, the control electrode voltage of the seventh transistor T7 can continue to maintain the data signal voltage, so that the seventh transistor T7 is in a conducting state, and the power supply voltage output from the second power line VDD2 passes through the conducting sixth transistor T7.
  • the transistor T6 and the seventh transistor T7 provide a driving voltage to one end of the second light-emitting element D2 to drive the second light-emitting element D2 to emit light.
  • the driving current flowing through the seventh transistor T7 (driving transistor) is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the seventh transistor T7, that is, the driving current driving the second light-emitting element D2
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the seventh transistor T7
  • Vth is the threshold voltage of the seventh transistor T7
  • Vdata is the data voltage output by the second data signal line Data2
  • Vdd is the power supply voltage output by the second power line VDD2.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • FIG. 4 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate in a plane parallel to the display substrate, the display substrate includes a display area and a mounting area, and in a plane perpendicular to the display substrate, the display substrate includes a base substrate and a driving structure layer disposed on the base substrate and a light-emitting element disposed on the driving structure layer.
  • the drive structure layer of the installation area includes a first pixel circuit
  • the drive structure layer of the display area includes a second pixel circuit
  • the first pixel circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1
  • the second pixel circuit includes a first pixel circuit.
  • Each transistor includes an active layer, a control electrode, a first electrode and a second electrode, and each capacitor includes two oppositely arranged electrode plates.
  • the driving structure layer includes a semiconductor layer, a first insulating layer, a first gate metal layer, a second insulating layer, a second gate metal layer, a third insulating layer, a first source-drain metal layer and a fourth insulating layer.
  • the semiconductor layer includes a reference signal line REF and active layers of multiple transistors;
  • the first gate metal layer includes control electrodes of multiple transistors, a first power supply line VDD1, a first scanning signal line G1, and a second scanning signal line G2 , the third scanning signal line G3, the light-emitting control signal line EM, the first plate C1-1 of the first capacitor C1, the third plate C2-1 of the second capacitor C2;
  • the second gate metal layer includes the first capacitor C1 The second plate C1-2 of the second capacitor C2, the fourth plate C2-2 of the second capacitor C2 and the initial signal line INT;
  • the first source-drain metal layer includes the first and second electrodes of a plurality of transistors, the first connection line L1, second connection line L2, third connection line L3, fourth connection line L4, fifth connection line L5, sixth connection line L6, seventh connection line L7, eighth connection line L8, first data signal line Data1 , the second data signal line Data2 and the second power supply line VDD2;
  • control electrode 11 of the first transistor T1, the control electrode 31 of the third transistor T3 and the first scan signal line G1 are connected to each other to form an integral structure, and the first transistor T1 One pole 12 and the first data signal line Data1 are connected to each other to form an integral structure, and the second pole 13 of the first transistor T1 and the first connection line L1 are connected to each other to form an integral structure.
  • the first connection line L1 passes through the second insulating layer and the third The via hole on the insulating layer is connected to the control electrode 21 of the second transistor T2 and the first electrode plate C1-1 of the first capacitor C1; the first electrode 22 of the second transistor T2 and the third connection line L3 are connected to each other to form an integrated structure , the third connection line L3 is connected to the first power supply line VDD1 through the second insulating layer and the via hole on the third insulating layer, and the second power supply line VDD2 is connected to the first power supply line VDD2 through the second insulating layer and the via hole on the third insulating layer.
  • the power line VDD1 is electrically connected, the second pole 23 of the second transistor T2 and the second connecting line L2 are connected to each other to form an integral structure, and the second connecting line L2 is connected to the second pole of the first capacitor C1 through the via hole on the third insulating layer.
  • Board C1-2 is connected.
  • the first pole 32 of the third transistor T3 and the second data signal line Data2 are connected to each other to form an integral structure
  • the second pole 43 and the fifth connecting line L5 are connected to each other to form an integral structure
  • the fifth connecting line L5 is connected to the control electrode 71 of the seventh transistor T7 and the second capacitor C2 through the via holes on the second insulating layer and the third insulating layer.
  • the third plate C2-1 is connected.
  • the first electrode 42 of the fourth transistor T4 and the sixth connection line L6 are connected to each other to form an integral structure, and the sixth connection line L6 is connected to the reference signal line REF through the via holes on the first insulating layer, the second insulating layer and the third insulating layer. connect.
  • the control electrode 51 of the fifth transistor T5 and the third scanning signal line G3 are connected to each other to form an integral structure
  • the first electrode 52 of the fifth transistor T5 is electrically connected to the initial signal line INT through the via hole on the third insulating layer
  • the fifth transistor T5 The second pole 53 of T5 and the seventh connecting line L7 are connected to each other to form an integral structure
  • the seventh connecting line L7 is electrically connected to the fourth electrode plate C2-2 of the second capacitor C2 through the via hole on the third insulating layer.
  • the first electrode 72 of the seventh transistor T7 is electrically connected to the fourth electrode plate C2-2 of the second capacitor C2 through a via hole on the third insulating layer.
  • the control electrode 61 of the sixth transistor T6 and the light-emitting control signal line EM are connected to each other to form an integral structure, and the first electrode 62 of the sixth transistor T6 is electrically connected to the first power supply line VDD1 through the via holes on the second insulating layer and the third insulating layer.
  • the second pole 63 of the sixth transistor T6 is connected with the eighth connection line L8 and the second pole 73 of the seventh transistor T7 to form an integrated structure.
  • the structure of the display substrate according to the embodiment of the present disclosure is exemplarily described below through the preparation process of the display substrate.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing film layers, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • Deposition can be selected from any one or more of sputtering, evaporation and chemical vapor deposition, coating can be selected from any one or more of spray coating and spin coating, and etching can be selected from dry etching. and any one or more of wet engraving.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process.
  • the "film” can also be referred to as a "layer”.
  • the "film” before the patterning process it is called a "film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B falls within the range of the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.
  • the manufacturing process of the display substrate shown in FIG. 4 may include the following steps:
  • a semiconductor layer pattern is formed on the base substrate.
  • Forming the semiconductor layer pattern on the base substrate includes: firstly depositing a buffer film on the base substrate to form a buffer layer pattern covering the entire base substrate. Subsequently, a layer of active layer thin film is deposited, and the active layer thin film is patterned through a patterning process to form a semiconductor layer pattern disposed on the buffer layer, as shown in FIG. 5 .
  • the semiconductor layer pattern may include the active layer 10 of the first transistor T1, the active layer 20 of the second transistor T2, the active layer 30 of the third transistor T3, the active layer 40 of the fourth transistor T4, and the fifth transistor T4.
  • the active layer 10 of the first transistor T1 and the active layer 20 of the second transistor T2 are disposed in the mounting region 101 , the active layer 30 of the third transistor T3 , the second transistor T2
  • the active layer 40 of the four transistors T4 , the active layer 50 of the fifth transistor T5 , the active layer 60 of the sixth transistor T6 and the active layer 70 of the seventh transistor T7 are disposed in the display area 100 .
  • the active layer 10 of the first transistor T1 includes a first channel region
  • the active layer 30 of the third transistor T3 includes a third channel region
  • the fourth transistor T4 The active layer 40 includes a fourth channel region
  • the active layer 60 of the sixth transistor T6 includes a sixth channel region, a first channel region, a third channel region, a fourth channel region and a sixth channel region The regions all extend along the first direction X.
  • the active layer 20 of the second transistor T2 includes a second channel region
  • the active layer 70 of the seventh transistor T7 includes a seventh channel region, and both the second channel region and the seventh channel region extend along the second direction Y .
  • the active layer 50 of the fifth transistor T5 includes a fifth channel region, the fifth channel region includes a first sub-channel region and a second sub-channel region connected to each other, and the first sub-channel region is along the first direction X extending, the second sub-channel region extends along the second direction Y.
  • the semiconductor layer pattern may further include a reference signal line REF for providing a reference voltage signal for the second pixel circuit.
  • Forming the first gate metal layer pattern includes: depositing a first insulating film and a first metal film in sequence on the base substrate on which the above structure is formed, and patterning the first metal film through a patterning process to form a first insulating film covering the semiconductor layer layer and a first gate metal layer pattern disposed on the first insulating layer.
  • the first gate metal layer pattern includes: the gate electrode of the first transistor T1 to the gate electrode of the seventh transistor T7, the first scan signal line G1, the second scan signal line G2, and the third scan signal line G3 , the light emission control signal line EM, the first plate C1-1 of the first capacitor C1, and the third plate C2-1 of the second capacitor C2.
  • the first gate metal layer pattern further includes: a first power line VDD1 , the first power line VDD1 extends along the first direction X, and the first power line VDD1 includes a first power line VDD1 located in the mounting area The first connection part VDD1-1 in 101, the second connection part VDD1-2 in the display area 100, and the first bending part VDD1 for connecting the first connection part VDD1-1 and the second connection part VDD1-2 -3.
  • the first power supply line VDD1 is connected with the subsequently formed second power supply line VDD2, and the first pole 62 of the sixth transistor T6 is connected with the first pole 22 of the second transistor T2.
  • the first scan signal line G1 is connected with the control electrode 11 of the first transistor T1 and the control electrode 31 of the third transistor T3 to form an integral structure
  • the second scan signal line G2 It is connected with the control electrode 21 of the second transistor T2 to form an integral structure
  • the third scanning signal line G3 and the control electrode 51 of the fifth transistor T5 are connected to each other to form an integral structure
  • the light emission control signal line EM and the control electrode 61 of the sixth transistor T6 connected to each other into a single structure.
  • the first transistor T1 , the third transistor T3 , the fourth transistor T4 and the fifth transistor T5 are all dual-gate thin film transistors.
  • the control electrode 11 of the first transistor T1, the control electrode 31 of the third transistor T3, the control electrode 41 of the fourth transistor T4 and the control electrode 51 of the fifth transistor T5 respectively include two protrusions, thereby forming Thin film transistor with double gate structure.
  • the third scan signal line G3 includes a third connection part G3-1 located in the mounting area, a fourth connection part G3-2 located in the display area, and A second bent portion G3-3 for connecting the third connecting portion G3-1 and the fourth connecting portion G3-2, the second bent portion G3-3 is configured such that the third connecting portion G3-1 and the first connecting portion G3-1 are The distance h3 between the pixel opening areas 1011 is smaller than the distance h4 between the fourth connection portion G3 - 2 and the second pixel opening area 1001 .
  • control electrode 21 of the second transistor T2 and the control electrode 71 of the seventh transistor T7 are disposed between the first scan signal line G1 and the third scan signal line G3.
  • control electrode 21 of the second transistor T2 and the first electrode plate C1-1 of the first capacitor C1 are connected to each other to form an integral structure
  • control electrode 71 of the seventh transistor T7 and the first electrode plate C1-1 of the second capacitor C2 The three-pole plates C2-1 are connected to each other to form an integral structure.
  • the first metal layer may be used as a shield to conduct conduction processing on the semiconductor layer, and the semiconductor layer in the region shielded by the first metal layer forms the first transistors T1 to T In the channel region of the active layer of the seven transistor T7, the semiconductor layer in the region not shielded by the first metal layer is conductive.
  • Forming the pattern of the second gate metal layer includes: depositing a second insulating film and a second metal film in sequence on the base substrate on which the above structure is formed, and patterning the second metal film through a patterning process to form a metal layer covering the first gate and a metal film.
  • the second gate metal layer pattern includes: a second electrode plate C1-2 and a fourth electrode plate C2-2, wherein the position of the second electrode plate C1-2 is the same as that of the first electrode plate C1-1.
  • the positions correspond to each other, forming the first capacitor C1; the position of the third pole plate C2-1 corresponds to the position of the fourth pole plate C2-2, forming the second capacitor C2.
  • the second gate metal layer pattern may further include: an initial signal line INT, where the initial signal line INT is used to provide an initial voltage signal for the second pixel circuit.
  • the initial signal line INT includes a fifth connection part INT-1 located in the mounting area, a sixth connection part INT-2 located in the display area, and a A third bending part INT-3 connecting the fifth connection part INT-1 and the sixth connection part INT-2, the third bending part INT-3 is configured such that the fifth connection part INT-1 is open to the first pixel
  • the distance h5 between the regions 1011 is smaller than the distance h6 between the sixth connection portion INT-2 and the second pixel opening region 1001 .
  • a third insulating layer pattern is formed.
  • Forming the third insulating layer pattern includes: depositing a third insulating film on the base substrate on which the above structure is formed, patterning the third insulating film through a patterning process, and forming a third insulating layer pattern with a plurality of via holes, and a plurality of via holes are formed.
  • the vias include: first via V1, second via V2, third via V3, fourth via V4, fifth via V5, sixth via V6, seventh via V7, and eighth via The hole V8, the ninth via V9, the tenth via V10, the eleventh via V11 and the twelfth via V12 are shown in FIG. 8 .
  • the first via hole V1 is configured so that the first electrodes 12-72 and the second electrodes 13-73 of the plurality of transistors T1-T7 and the active layers of the plurality of transistors T1-T7 formed subsequently Both ends of 10-70 are electrically connected, and the second via V2 is configured to electrically connect the subsequently formed first connection line L1 to the control electrode 21 of the second transistor T2 and the first plate C1-1 of the first capacitor C1,
  • the third via hole V3 is configured to electrically connect the subsequently formed third connection line L3 to the first power supply line VDD1
  • the fourth via hole V4 is configured to connect the subsequently formed second connection line L2 to the second pole of the first capacitor C1
  • the plate C1-2 is electrically connected
  • the fifth via hole V5 is configured to connect the fourth connection line L4 formed subsequently to the second electrode plate C1-2 of the first capacitor C1.
  • the sixth via hole V6 is configured to connect the subsequently formed fifth connection line L5 to the gate 71 of the seventh transistor T7 and the third electrode plate C2-1 of the second capacitor C2, and the seventh via hole V7 is configured to allow the subsequent formation of
  • the sixth connection line L6 is connected to the reference signal line REF
  • the eighth via hole V8 is configured to electrically connect the first pole 52 of the fifth transistor T5 formed subsequently with the initial signal line INT
  • the ninth via hole V9 is configured to enable the subsequent
  • the formed seventh connection line L7 is electrically connected to the fourth electrode plate C2-2 of the second capacitor C2
  • the tenth via hole V10 is configured to connect the first electrode 72 of the seventh transistor T7 to be formed later and the first electrode plate C2-2 of the second capacitor C2.
  • the quadrupole plate C2-2 is electrically connected, the eleventh via hole V11 is configured to electrically connect the first pole 62 of the sixth transistor T6 to be formed subsequently to the first power line VDD1, and the twelfth via hole V12 is configured to enable the subsequent formation of the first power line VDD1.
  • the second power line VDD2 is electrically connected to the first power line VDD1.
  • Forming the first source-drain metal layer pattern includes: depositing a third metal film on the base substrate having the above-mentioned structure, and patterning the third metal film through a patterning process to form the first source-drain metal layer pattern. As shown in FIG.
  • the first source-drain metal layer includes the first electrode 12 of the first transistor T1 to the first electrode 72 of the seventh transistor T7 , the second electrode 13 of the first transistor T1 to the second electrode of the seventh transistor T7 Pole 73, first connection line L1, second connection line L2, third connection line L3, fourth connection line L4, fifth connection line L5, sixth connection line L6, seventh connection line L7, eighth connection line L8 , the second power supply line VDD2, the first data signal line Data1 and the second data signal line Data2, the first electrodes and the second electrodes of the plurality of transistors are respectively connected to their corresponding active layers through two first via holes.
  • the first electrodes 12-72 and the second electrodes 13-73 of the plurality of transistors T1-T7 pass through the plurality of first via holes V1 and the active layers 10-70 of the plurality of transistors T1-T7
  • the two ends of the first transistor T1 are connected to each other, the first pole 12 of the first transistor T1 and the first data signal line Data1 are connected to each other to form an integrated structure, the second pole 13 of the first transistor T1 and the first connection line L1 are connected to each other to form an integrated structure, and the first The connecting line L1 is connected to the control electrode 21 of the second transistor T2 and the first electrode plate C1-1 of the first capacitor C1 through the second via hole V2.
  • the first pole 22 of the second transistor T2 and the third connection line L3 are connected to each other to form an integral structure.
  • the third connection line L3 is connected to the first power supply line VDD1 through the third via V3, and the second pole 23 of the second transistor T2 is connected to the first power supply line VDD1.
  • the second connection lines L2 are connected to each other to form an integral structure, and the second connection lines L2 are connected to the second plate C1-2 of the first capacitor C1 through the fourth via hole V4.
  • the fourth connection line L4 is connected to the second electrode plate C1-2 of the first capacitor C1 through the fifth via hole V5.
  • the first electrode 32 of the third transistor T3 and the second data signal line Data2 are connected to each other to form an integral structure, and the second electrode 33 of the third transistor T3 and the second electrode 43 of the fourth transistor T4 are connected to each other.
  • the fifth connection lines L5 are connected to each other to form an integral structure, and the fifth connection lines L5 are connected to the control electrode 71 of the seventh transistor T7 and the third electrode plate C2-1 of the second capacitor C2 through the sixth via hole V6.
  • the first pole 42 of the fourth transistor T4 and the sixth connection line L6 are connected to each other to form an integral structure, and the sixth connection line L6 is connected to the reference signal line REF through the seventh via hole V7.
  • the first pole 52 of the fifth transistor T5 is electrically connected to the initial signal line INT through the eighth via V8, the second pole 53 of the fifth transistor T5 and the seventh connection line L7 are connected to each other to form an integral structure, and the seventh connection line L7 passes through
  • the ninth via hole V9 is electrically connected to the fourth electrode plate C2-2 of the second capacitor C2.
  • the first electrode 72 of the seventh transistor T7 is electrically connected to the fourth electrode plate C2-2 of the second capacitor C2 through the tenth via V10.
  • the first pole 62 of the sixth transistor T6 is electrically connected to the first power supply line VDD1 through the eleventh via V11, the second pole 63 of the sixth transistor T6 is connected to the eighth connection line L8, and the second pole 73 of the seventh transistor T7 connected to each other into a single structure.
  • the second power line VDD2 is electrically connected to the first power line VDD1 through the twelfth via V12.
  • the driving structure layer includes a semiconductor layer arranged on the base substrate, a first insulating layer arranged on the semiconductor layer, a first gate metal layer arranged on the first insulating layer, and a gate metal layer arranged on the first gate metal layer.
  • a sub-pixel is defined by perpendicularly crossing the data line, and a thin film transistor composed of an active layer, a control electrode, a first electrode and a second electrode is arranged in the sub-pixel.
  • the first insulating layer and the second insulating layer are also called gate insulating layers (GI), and the third insulating layer is also called interlayer insulating layer (ILD).
  • a fourth insulating layer pattern is formed.
  • Forming the fourth insulating layer pattern includes: coating a fourth insulating film on the substrate on which the aforementioned pattern is formed, and forming a fourth insulating layer pattern covering the first source-drain metal layer through a photolithography process of mask exposure and development, and the fourth insulating layer
  • a thirteenth via hole V13 and a fourteenth via hole V14 are opened.
  • the thirteenth via hole V13 exposes the fourth connection line L4
  • the fourteenth via hole V14 exposes the seventh connection line L7 , as shown in FIG. 9 .
  • the fourth insulating layer is also called a planarization layer (PLN).
  • Forming the anode pattern includes: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film through a patterning process to form patterns of the first anode AN1 and the second anode AN2, the first anode AN1 is located in the mounting area, and the second anode is AN2 is located in the display area, the first anode AN1 is connected to the fourth connection line L4 through the thirteenth via hole V13, and the second anode AN2 is connected to the seventh connection line L7 through the fourteenth via hole V14, as shown in FIG. 4 and FIG. 9 .
  • the transparent conductive film can be indium tin oxide ITO or indium zinc oxide IZO.
  • the area of the orthographic projection of the first anode AN1 on the base substrate is smaller than the area of the orthographic projection of the second anode AN2 on the base substrate.
  • a pixel definition layer pattern is formed.
  • Forming the pixel definition layer pattern includes: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, forming a pixel definition layer (Pixel Define Layer) pattern by a photolithography process, and the pixel definition layer pattern defines a pixel opening exposing the anode in each sub-pixel
  • the pixel definition layer pattern defines a first pixel opening area 1011 in the mounting area 101 and a second pixel opening area 1001 in the display area 100 .
  • the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate, etc.
  • the sizes of the first pixel opening area 1011 and the second pixel opening area 1001 can be defined according to actual needs. , the opening size of the first pixel opening area 1011 may be the same as the opening size of the second pixel opening area 1001 , which is not limited in this embodiment of the present disclosure.
  • the subsequent preparation process may include: using an evaporation process to form an organic light-emitting layer, the organic light-emitting layer is at least partially disposed in the pixel opening, and the organic light-emitting layer is connected to the anode; forming a cathode on the organic light-emitting layer, the cathode It is connected with the organic light-emitting layer; the organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode. Then, an encapsulation layer is formed.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. , the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light-emitting device.
  • the organic light emitting layer may include at least a hole injection layer, a hole transport layer, a light emitting layer and a hole blocking layer stacked on the anode.
  • the hole injection layers of all subpixels are a common layer connected together
  • the hole transport layers of all subpixels are a common layer connected together
  • the light emitting layers of adjacent subpixels may have a small amount of Overlapping, or possibly isolated, hole blocking layers are common layers that are joined together.
  • the base substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, etc.
  • the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first gate metal layer, the second gate metal layer, and the first source-drain metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo Wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) One or more, it can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer and the second insulating layer are called a gate insulating (GI) layer, and the third insulating layer is called an interlayer insulating (ILD) layer.
  • GI gate insulating
  • ILD interlayer insulating
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • the fourth insulating layer can be made of organic material
  • the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO
  • the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals. alloy.
  • the mounting area 101 does not need to be provided with a second power line parallel to the data line.
  • the power line VDD2 effectively reduces the area occupied by the metal wiring in the installation area 101, increases the light transmittance of the installation area 101, and improves the camera functions such as Selfie and face recognition of the front camera.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the first pixel circuit is arranged in the driving structure layer of the mounting area 101
  • the second pixel circuit is arranged in the driving structure layer of the display area
  • the number of transistors in the first pixel circuit is The number of transistors in the second pixel circuit is less than that of the second pixel circuit, which further reduces the area occupied by metal traces in the installation area 101 , increases the light transmittance of the installation area 101 , and improves the camera functions such as Selfie and face recognition of the front camera.
  • the present disclosure also provides a method for preparing a display substrate, so as to prepare the display substrate provided by the above embodiments.
  • the preparation method of the display substrate may include the following steps:
  • Step S1 forming a driving structure layer on the base substrate, the driving structure layer comprising a buffer layer arranged on the base substrate, a semiconductor layer arranged on the buffer layer, a first insulating layer covering the semiconductor layer, and a first insulating layer arranged on the first insulating layer.
  • first gate metal layer on an insulating layer, a second insulating layer covering the first gate metal layer, a second gate metal layer disposed on the second insulating layer, a third insulating layer covering the second gate metal layer, a first source-drain metal layer on the third insulating layer and a flat layer covering the first source-drain metal layer; at least one of the first gate metal layer and the second gate metal layer includes a first power line, the first power The line extends along a first direction, the first source-drain metal layer includes a data line, the data line extends along a second direction, and the first direction intersects the second direction;
  • Step S2 forming a light-emitting element on the driving structure layer.
  • At least one of the first gate metal layer and the second gate metal layer further includes a light emission control signal line and at least one scan signal line, and both the light emission control signal line and the scan signal line are along the first extending in the direction, the first power line is located between the light-emitting control signal line and at least one scan signal line.
  • the first power cord includes at least one first bent portion, and the first bent portion extends in the second direction.
  • the first source-drain metal layer further includes a second power line extending along the second direction, the first power line passing through the via hole on the third insulating layer, or passing through The third insulating layer and the via hole on the second insulating layer are electrically connected to the second power line.
  • the display substrate includes a display area and a mounting area
  • the mounting area includes a first pixel circuit
  • the display area includes a second pixel circuit
  • the first pixel circuit and the The second pixel circuits each include at least one transistor, and the number of transistors in the first pixel circuit is less than the number of transistors in the second pixel circuit.
  • the realization principle and effect of the display substrate prepared by the method for preparing a display substrate provided by the present disclosure are similar to those of the aforementioned display substrate, and are not repeated here.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which is not limited in the embodiment of the present invention.

Abstract

一种显示基板及其制备方法、显示装置，在垂直于显示基板的平面内，显示基板包括衬底基板以及依次叠层设置在所述衬底基板上的缓冲层、半导体层、第一绝缘层、第一栅金属层、第二绝缘层、第二栅金属层、第三绝缘层、第一源漏金属层以及平坦层，第一栅金属层和第二栅金属层中的至少一层包括第一电源线，第一电源线沿第一方向延伸，第一源漏金属层包括数据线，数据线沿第二方向延伸，第一方向与第二方向相交。本公开通过设置与数据线相交的第一电源线，安装区域不需要设置与数据线平行的第二电源线，有效减少了安装区域的金属走线占用面积，增加了安装区域的光透过率。

Description

显示基板及其制备方法、显示装置
本申请要求于2021年2月26日提交中国专利局、申请号为202110221026.9、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
随着技术的发展，移动终端的外观越来越受到人们的关注，其中，屏占比相对较大的大屏幕终端，逐渐成为移动终端的主流设计之一。大屏幕终端可以提升用户的游戏娱乐体验，有利于分屏显示，且整机的科技感更高，从而可以为用户带来更强的视觉冲击。
屏下摄像头产品，由于屏占比较高、摄像头对视觉画面影响较小等特点，成为当下比较有潜力的显示装置设计。但是，在将摄像头放置在显示面板下方时，由于显示面板会遮挡进入摄像头的光线，从而使得前置摄像头的自拍、人脸识别等功能受到影响。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，在垂直于所述显示基板的平面上，所述显示基板包括设置在所述衬底基板上的缓冲层、设置在所述缓冲层上的半导体层、覆盖所述半导体层的第一绝缘层、设置在所述第一绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第二绝缘层、设置在所述第二绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第三绝缘层、设置在所述第三 绝缘层上的第一源漏金属层以及覆盖所述第一源漏金属层的平坦层；所述第一栅金属层和第二栅金属层中的至少一层包括第一电源线，所述第一电源线沿第一方向延伸，所述第一源漏金属层包括数据线，所述数据线沿第二方向延伸，所述第一方向与所述第二方向相交。
在示例性实施例中，所述第一栅金属层和第二栅金属层中的至少一层还包括发光控制信号线和至少一根扫描信号线，所述发光控制信号线和扫描信号线均沿第一方向延伸，所述第一电源线位于所述发光控制信号线和至少一根扫描信号线之间。
在示例性实施例中，所述第一电源线包括至少一个第一弯折部，所述第一弯折部沿所述第二方向延伸。
在示例性实施例中，所述第一源漏金属层还包括第二电源线，所述第二电源线沿第二方向延伸，所述第一电源线通过所述第三绝缘层上的过孔，或者，通过所述第三绝缘层和第二绝缘层上的过孔与所述第二电源线电连接。
在示例性实施例中，所述第一源漏金属层还包括第八连接线，所述第八连接线沿所述第二方向延伸，所述第八连接线在所述衬底基板上的正投影与所述第一电源线在所述衬底基板上的正投影相交。
在示例性实施例中，所述半导体层包括第三沟道区域、第四沟道区域、第五沟道区域、第六沟道区域和第七沟道区域，所述第三沟道区域、第四沟道区域以及第六沟道区域均沿所述第一方向延伸，所述第七沟道区域沿所述第二方向延伸，所述第五沟道区域包括相互连接的第一子沟道区域和第二子沟道区域，所述第一子沟道区域沿所述第一方向延伸，所述第二子沟道区域沿所述第二方向延伸。
在示例性实施例中，所述半导体层包括参考信号线，所述参考信号线用于提供参考电压信号，所述参考信号线沿所述第一方向延伸。
在示例性实施例中，所述第二栅金属层包括初始信号线，所述初始信号线用于提供初始电压信号；所述初始信号线包括至少一个第三弯折部，所述第三弯折部沿所述第二方向延伸。
在示例性实施例中，所述显示基板包括显示区域和安装区域，所述安装 区域包括第一像素电路，所述显示区域包括第二像素电路，其中：所述第一像素电路和所述第二像素电路分别包括至少一个晶体管，所述第一像素电路中的晶体管数量少于第二像素电路中的晶体管数量。
在示例性实施例中，所述显示基板还包括设置在所述平坦层上的阳极，其中：所述阳极包括第一阳极和第二阳极，所述第一阳极位于所述安装区域，所述第二阳极位于所述显示区域，所述第一阳极在所述衬底基板上的正投影的面积小于所述第二阳极在所述衬底基板上的正投影的面积。
本公开实施例还提供了一种显示装置，包括：如上任一所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，包括：在衬底基板上形成驱动结构层，所述驱动结构层包括设置在所述衬底基板上的缓冲层、设置在所述缓冲层上的半导体层、覆盖所述半导体层的第一绝缘层、设置在所述第一绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第二绝缘层、设置在所述第二绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第三绝缘层、设置在所述第三绝缘层上的第一源漏金属层以及覆盖所述第一源漏金属层的平坦层；所述第一栅金属层和第二栅金属层中的至少一层包括第一电源线，所述第一电源线沿第一方向延伸，所述第一源漏金属层包括数据线，所述数据线沿第二方向延伸，所述第一方向与所述第二方向相交；在所述驱动结构层上形成发光元件。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开实施例一种显示基板的结构示意图；
图2为图1中A区域的放大结构示意图；
图3为本公开实施例一种显示基板的剖面结构示意图；
图4为本公开实施例提供的一种显示基板的平面结构示意图；
图5为本公开实施例提供的一种显示基板的半导体层的结构示意图；
图6为本公开实施例提供的一种显示基板的第一栅金属层的结构示意图；
图7为本公开实施例提供的一种显示基板的第二栅金属层的结构示意图；
图8为本公开实施例提供的一种显示基板的第一源漏金属层的结构示意图；
图9为本公开实施例提供的一种显示基板的阳极层的结构示意图；
图10为本公开实施例提供的一种显示基板的像素定义层的结构示意图；
图11为本公开实施例提供的第一像素电路的结构示意图；
图12为本公开实施例提供的第一像素电路的等效电路图；
图13为本公开实施例提供的第二像素电路的结构示意图；
图14为本公开实施例提供的第二像素电路的等效电路图；
图15为图14所示的第二像素电路的工作时序图；
图16为本公开实施例提供的一种显示基板的制备方法的流程图
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接 在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为本公开实施例提供的显示基板的结构示意图，图2为图1中A区域的放大结构示意图，图3为本公开实施例提供的显示基板的剖面结构示意图。如图1、图2和图3所示，本公开实施例提供了一种显示基板，包括显示区域100。
在垂直于显示基板的平面上，显示基板包括衬底基板201、设置在衬底基板201上的缓冲层、设置在缓冲层上的半导体层、覆盖半导体层的第一绝缘层、设置在第一绝缘层上的第一栅金属层、覆盖第一栅金属层的第二绝缘层、设置在第二绝缘层上的第二栅金属层、覆盖第二栅金属层的第三绝缘层、设置在第三绝缘层上的第一源漏金属层以及覆盖第一源漏金属层的平坦层。
第一栅金属层和第二栅金属层中的至少一层包括第一电源线VDD1，第一电源线VDD1沿第一方向X延伸，第一源漏金属层包括数据线(如图2中的第一数据线Data1或第二数据线Data2)，数据线沿第二方向Y延伸，第一方向X与第二方向Y相交。
在一些示例性实施例中，第一方向X和第二方向Y可以位于同一平面内，且第一方向X可以垂直于第二方向Y。例如，第一方向X可以为行方向，平 行于扫描线的延伸方向；第二方向Y可以为列方向，平行于数据线的延伸方向。
在一些示例性实施例中，如图4所示，第一栅金属层和第二栅金属层中的至少一层还包括发光控制信号线EM和至少一根扫描信号线(如图4中的第一扫描信号线G1、第二扫描信号线G2和第三扫描信号线G3)，发光控制信号线EM和扫描信号线均沿第一方向X延伸，第一电源线VDD1位于发光控制信号线EM和至少一根扫描信号线之间。
在一些示例性实施例中，如图4所示，第一源漏金属层还包括第八连接线L8，第八连接线L8沿第二方向Y延伸，第八连接线L8在衬底基板201上的正投影与第一电源线VDD1在衬底基板201上的正投影相交。
在一些示例性实施例中，如图4所示，第一源漏金属层还包括第二电源线VDD2，第二电源线VDD2沿第二方向Y延伸，第一电源线VDD1通过第三绝缘层上的过孔，或者，通过第三绝缘层和第二绝缘层上的过孔与第二电源线VDD2电连接。
在一些示例性实施例中，如图4所示，第一电源线VDD1包括至少一个第一弯折部，第一弯折部沿第二方向Y延伸，即第一弯折部的延伸方向与第二电源线VDD2的延伸方向平行。
在一些示例性实施例中，如图5所示，半导体层包括参考信号线REF，参考信号线REF用于提供参考电压信号，参考信号线REF沿第一方向X延伸。
在一些示例性实施例中，如图5所示，半导体层包括第三沟道区域、第四沟道区域、第五沟道区域、第六沟道区域和第七沟道区域，第三沟道区域、第四沟道区域以及第六沟道区域均沿第一方向X延伸，第七沟道区域沿第二方向Y延伸，第五沟道区域包括相互连接的第一子沟道区域和第二子沟道区域，第一子沟道区域沿第一方向X延伸，第二子沟道区域沿第二方向Y延伸。
在一些示例性实施例中，如图1和图5所示，显示区域包括呈阵列排布的多个子像素，每个子像素沿第二方向Y从上至下分为第I区、第II区和第 III区，其中，第五沟道区域和第六沟道区域位于第I区，第七沟道区域位于第II区，第三沟道区域、第四沟道区域和参考信号线REF位于第III区。
在一些示例性实施例中，如图5所示，第五沟道区域位于第六沟道区域靠近第II区的一侧，第七沟道区域位于第II区沿第一方向X的边缘的一侧，第三沟道区域位于第III区靠近第II区的边缘的一侧，第四沟道区域位于参考信号线REF和第三沟道区域之间。
在一些示例性实施例中，如图6所示，第一栅金属层包括第一扫描信号线G1、第二扫描信号线G2、第三扫描信号线G3、第一电源线VDD1、发光控制信号线EM和第二电容C2的第三极板C2-1，其中，发光控制信号线EM、第一电源线VDD1和第三扫描信号线G3位于第I区，第二电容C2的第三极板C2-1位于第II区，第一扫描信号线G1和第二扫描信号线G2位于第III区。
在一些示例性实施例中，如图6所示，发光控制信号线EM位于第一电源线VDD1远离第II区的一侧，第一电源线VDD1位于第三扫描信号线G3远离第II区的一侧，第三扫描信号线G3位于第I区靠近第II区的边缘的一侧，第一扫描信号线G1位于第二扫描信号线G2靠近第II区的一侧。
在一些示例性实施例中，如图6所示，第一扫描信号线G1包括至少两个第一凸起，该两个第一凸起均位于第一扫描信号线G1靠近第II区的一侧，该两个第一凸起在衬底基板上的正投影，与第三沟道区域在衬底基板上的正投影包含交叠区域，该两个第一凸起形成了第三晶体管T3的双栅结构。
在一些示例性实施例中，如图6所示，第二扫描信号线G2包括至少两个第二凸起，该两个第二凸起均位于第二扫描信号线G2靠近第II区的一侧，该两个第二凸起在衬底基板上的正投影，与第四沟道区域在衬底基板上的正投影包含交叠区域，该两个第二凸起形成了第四晶体管T4的双栅结构。
在一些示例性实施例中，如图6所示，第三扫描信号线G3包括至少两个第三凸起，该两个第三凸起包括一个上子凸起和一个下子凸起，其中，上子凸起位于第三扫描信号线G3远离第II区的一侧，该上子凸起在衬底基板 上的正投影，与第五沟道区域中的第一子沟道区域在衬底基板上的正投影包含交叠区域，下子凸起位于第三扫描信号线G3靠近第II区的一侧，该下子凸起在衬底基板上的正投影，与第五沟道区域中的第二子沟道区域在衬底基板上的正投影包含交叠区域，该两个第三凸起形成了第五晶体管T5的双栅结构。
在一些示例性实施例中，如图6所示，第三扫描信号线G3包括至少一个第二弯折部G3-3，第二弯折部G3-3沿第二方向Y延伸，即第三弯折部INT-3的延伸方向与第二电源线VDD2的延伸方向平行。
在一些示例性实施例中，如图6所示，发光控制信号线EM靠近第II区的一侧包括至少一个第四凸起，其中，第四凸起位于发光控制信号线EM靠近第II区的一侧，该第四凸起在衬底基板上的正投影，与第六沟道区域在衬底基板上的正投影包含交叠区域，即第四凸起形成了第六晶体管T6的控制极61。
在一些示例性实施例中，如图6所示，第三极板C2-1包括第一主体区C2-11、写电位区C2-12和扩大交叠面积区C2-13，扩大交叠面积区C2-13位于第三极板C2-1靠近第I区的一侧，第一主体区C2-11和写电位区C2-12位于第三极板C2-1靠近第III区的一侧，第一主体区C2-11、写电位区C2-12和扩大交叠面积区C2-13形成“凹”字形结构。
在一些示例性实施例中，如图6所示，第三极板C2-1设置在第一电源线VDD1和至少一根扫描信号线之间，示例性的，第三极板C2-1设置在第一电源线VDD1和第一扫描信号线G1之间，或者，第三极板C2-1设置在第一电源线VDD1和第二扫描信号线G2之间。
在一些示例性实施例中，如图7所示，第二栅金属层包括第二电容C2的第四极板C2-2，其中，第四极板C2-2位于第II区。
在一些示例性实施例中，如图7所示，第四极板C2-2包括第二主体区C2-21和信号连接区C2-22，信号连接区C2-22位于第四极板C2-2靠近第I区的边缘的一侧，信号连接区C2-22通过第三绝缘层上的过孔与第七连接线L7连接，用于传递信号至第七连接线L7，并通过第七连接线L7将信号传递至有机发光二极管的阳极。
在一些示例性实施例中，如图7所示，第二栅金属层还包括初始信号线INT，其中，初始信号线INT沿第一方向X延伸，第一源漏金属层包括数据线(如图2中的第一数据线Data1或第二数据线Data2)，数据线沿第二方向Y延伸，第一方向X与第二方向Y相交。
在一些示例性实施例中，如图7所示，初始信号线INT包括至少一个第三弯折部INT-3，第三弯折部INT-3沿第二方向Y延伸，即第三弯折部INT-3的延伸方向与第二电源线VDD2的延伸方向平行。
在一些示例性实施例中，如图8所示，第一源漏金属层包括第二电源线VDD2、第二数据线Data2、至少一根连接线以及至少一个晶体管的源电极和漏电极，其中，第二电源线VDD2和第二数据线Data2均沿第二方向Y延伸，且第二电源线VDD2和第二数据线Data2位于子像素的一侧，第二电源线VDD2位于第二数据线Data2靠近子像素边缘的一侧。
在一些示例性实施例中，如图8所示，第一源漏金属层包括第五连接线L5、第六连接线L6、第七连接线L7、第八连接线L8、第三晶体管T3的第一极32和第二极33、第四晶体管T4的第一极42和第二极43、第五晶体管T5的第一极52和第二极53、第六晶体管T6的第一极62和第二极63以及第七晶体管T7的第一极72和第二极73，第三晶体管T3的第一极32与第二数据信号线Data2相互连接成一体结构，第三晶体管T3的第二极33、第四晶体管T4的第二极43与第五连接线L5相互连接成一体结构，第五连接线L5通过第二绝缘层和第三绝缘层上的过孔与第七晶体管T7的控制极71、第二电容C2的第三极板C2-1连接。第四晶体管T4的第一极42与第六连接线L6相互连接成一体结构，第六连接线L6通过第一绝缘层、第二绝缘层和第三绝缘层上的过孔与参考信号线REF连接。第五晶体管T5的第一极52通过第三绝缘层上的过孔与初始信号线INT电连接，第五晶体管T5的第二极53与第七连接线L7相互连接成一体结构，第七连接线L7通过第三绝缘层上的过孔与第二电容C2的第四极板C2-2电连接。第七晶体管T7的第一极72通过第三绝缘层上的过孔与第二电容C2的第四极板C2-2电连接。第六晶体管T6的第一极62通过第二绝缘层和第三绝缘层上的过孔与第一电源线VDD1电连接，第六晶体管T6的第二极63与第八连接线L8、第七晶体管T7的第 二极73相互连接成一体结构。
在一些示例性实施例中，如图1、图2和图4所示，该显示基板还包括位于显示区域100中的安装区域101。
在一些示例性实施例中，安装区域101可以为屏下摄像头区域。
在一些示例性实施例中，显示区域100的像素分辨率大于安装区域101的像素分辨率，示例性的，显示区域100的像素分辨率可以为2K分辨率，安装区域101的像素分辨率可以为1080分辨率。
在另一些示例性实施例中，显示区域100包括多条第一金属走线，安装区域101包括多条与显示区域100的多条第一金属走线一一对应的第二金属走线，其中，每条第二金属走线的线宽小于或等于对应的第一金属走线的线宽。
在示例性实施例中，如图2所示，在垂直于显示基板的平面上，显示基板包括衬底基板201、位于衬底基板201上的多个金属层以及设置在多个金属层之间的绝缘层；多个金属层包括第一电源线VDD1和第二电源线VDD2，第一电源线VDD1沿第一方向X延伸，第二电源线VDD2沿第二方向Y延伸，第一方向X与第二方向Y相交；
第二电源线VDD2仅位于显示区域100内，第一电源线VDD1包括位于安装区域101内的第一连接部VDD1-1和位于显示区域100内且与第一连接部VDD1-1连接的第二连接部VDD1-2，第二连接部VDD1-2与第二电源线VDD2通过绝缘层上的过孔相互连接。
本公开实施例提供的显示基板，通过在安装区域101不设置第二电源线VDD2，有效减少了安装区域101的金属走线占用面积，增加了安装区域101的光透过率，提高了前置摄像头的自拍、人脸识别等摄像功能。
在一些示例性实施例中，如图9所示，安装区域101的子像素包括第一阳极AN1，显示区域100的子像素包括第二阳极AN2，第一阳极AN1通过第十三过孔V13与第四连接线L4连接，第二阳极AN2通过第十四过孔V14与第七连接线L7连接。
在一些示例性实施例中，第一阳极AN1在衬底基板上的正投影的面积 小于第二阳极AN2在衬底基板上的正投影的面积。在一些示例性实施例中，如图2和图10所示，安装区域101包括多个第一像素开口区1011，显示区域100包括多个第二像素开口区1001。
在一些示例性实施例中，如图2和图10所示，第一像素开口区1011的开口大小与第二像素开口区1001开口大小可以相同。
在一些示例性实施例中，如图2所示，第一电源线VDD1还包括连接在第一连接部VDD1-1和第二连接部VDD1-2之间的第一弯折部VDD1-3，第一弯折部VDD1-3被配置为使得第一连接部VDD1-1与第一像素开口区1011之间的距离h1小于第二连接部VDD1-2与第二像素开口区1001之间的距离h2。
在一些示例性实施例中，如图3所示，在垂直于该显示基板的平面上，该显示基板可以包括设置在衬底基板201上的驱动结构层202、设置在驱动结构层202远离衬底基板201一侧的发光元件203以及设置在发光元件203远离衬底基板201一侧的封装层204。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，衬底基板201可以是柔性基底，或者可以是刚性基底。每个子像素的驱动结构层202可以包括构成像素驱动电路的多个晶体管和存储电容，图3中以每个子像素中包括一个驱动晶体管210和一个存储电容211为例进行示意。在一些可能的实现方式中，每个子像素的驱动结构层202可以包括：设置在衬底基板201上的缓冲层；设置在缓冲层上的有源层；覆盖有源层的第一绝缘层；设置在第一绝缘层上的第一栅金属层；覆盖第一栅金属层的第二绝缘层；设置在第二绝缘层上的第二栅金属层；覆盖第二栅金属层的第三绝缘层，第一绝缘层、第二绝缘层和第三绝缘层上开设有过孔，过孔暴露出有源层；设置在第三绝缘层上的第一源漏金属层，第一源漏金属层包括源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接；覆盖前述结构的平坦层，平坦层上开设有过孔，过孔暴露出驱动晶体管210的漏电极。
在一些示例性实施例中，如图4所示，安装区域101的驱动结构层包括第一像素电路，显示区域100的驱动结构层包括第二像素电路，第一像素电 路和第二像素电路分别包括至少一个晶体管，第一像素电路中的晶体管数量少于第二像素电路中的晶体管数量。
本公开实施例提供的显示基板，通过在安装区域101的驱动结构层中设置第一像素电路，在显示区域100的驱动结构层中设置第二像素电路，且第一像素电路中的晶体管数量少于第二像素电路中的晶体管数量，有效减少了安装区域101的金属走线占用面积，增加了安装区域101的光透过率，提高了前置摄像头的自拍、人脸识别等摄像功能。
在一些示例性实施例中，第一像素电路可以采用2T1C、3T1C或5T1C等等的设计结构，第二像素电路可以采用3T1C、5T1C或7T1C等等的设计结构，本公开实施例对此不作限定。
在一些示例性实施例中，如图11所示，第一像素电路可以包括第一写入子电路和第一驱动子电路。其中，第一写入子电路分别与第一数据信号线Data1、第一扫描信号线G1、第一节点N1和第二节点N2连接，被配置为在第一扫描信号线G1的信号的控制下，向第一节点N1提供第一数据信号线Data1的信号，并存储第一节点N1和第二节点N2间的电压。第一驱动子电路分别与第一电源线VDD1、第一节点N1和第二节点N2连接，被配置为产生驱动第一发光元件D1发光的驱动电流。
在一些示例性实施例中，如图12所示，第一写入子电路包括第一晶体管T1和第一电容C1，第一驱动子电路包括第二晶体管T2，其中，第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第一电容C1为存储电容。
其中，第一晶体管T1的控制极与第一扫描信号线G1电连接，第一晶体管T1的第一极与第一数据信号线Data1电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一电源线VDD1电连接，第二晶体管T2的第二极与第二节点N2电连接；第一发光元件D1的一端与第二节点N2电连接，第一发光元件D1的另一端与稳压线VSS电连接；第一电容C1的一端与第一节点N1电连接，第一电容C1的另一端与第二节点N2电连接。
在示例性实施方式中，以第一像素电路中第一晶体管T1至第二晶体管T2均为N型薄膜晶体管为例，第一像素电路的工作过程可以包括：第一扫 描信号线G1的扫描信号控制第一晶体管T1打开，第一数据信号线Data1的数据信号经过第一晶体管T1进入到第二晶体管T2的控制极及第一电容C1，然后第一晶体管T1闭合，由于第一电容C1的存储作用，第二晶体管T2的控制极电压仍可继续保持数据信号电压，使得第二晶体管T2处于导通状态，驱动电流通过第二晶体管T2进入第一发光元件D1，驱动第一发光元件D1发光。
在一些示例性实施例中，如图13所示，第二像素电路可以包括第二写入子电路、第二驱动子电路、复位子电路、补偿子电路和发光控制子电路。
其中，第二写入子电路分别与第二数据信号线Data1、第一扫描信号线G1、第三节点N3和第四节点N4连接，被配置为在第一扫描信号线G1的信号的控制下，向第三节点N3提供第二数据信号线Data2的信号，并存储第三节点N3和第二节点N4间的电压。第二驱动子电路分别与第三节点N3、第四节点N4和第五节点N5连接，被配置为在第三节点N3和第五节点N5的控制下，对第四节点N4的电压进行补偿；并在第三节点N3和第四节点N4的控制下，产生驱动第一发光元件D1发光的驱动电流。复位子电路分别与第三扫描信号线G3、初始信号线INT和第四节点N4连接，被配置为在第三扫描信号线G3的信号的控制下，向第四节点N4提供初始信号线INT的信号。补偿子电路分别与第二扫描信号线G2、参考信号线REF和第三节点N3连接，被配置为在第二扫描信号线G2的信号的控制下，向第三节点N3提供参考信号线REF的信号。发光控制子电路分别与发光控制信号线EM、第二电源线VDD2和第五节点N5连接，被配置为在发光控制信号线EM的信号的控制下，向第五节点N5提供第二电源线VDD2的电源电压。
在一些示例性实施例中，如图14所示，第二写入子电路包括第三晶体管T3和第二电容C2，补偿子电路包括第四晶体管T4，复位子电路包括第五晶体管T5，发光控制子电路包括第六晶体管T6，第二驱动子电路包括第七晶体管T7。其中，第三晶体管T3、第四晶体管T4、第五晶体管T5至第六晶体管T6为开关晶体管，第七晶体管T7为驱动晶体管，第二电容C2为存储电容。
其中，第三晶体管T3的控制极与第一扫描信号线G1电连接，第三晶体 管T3的第一极与第二数据信号线Data2电连接，第三晶体管T3的第二极与第三节点N3电连接；第四晶体管T4的控制极与第二扫描信号线G2电连接，第四晶体管T4的第一极与参考信号线REF电连接，第四晶体管T4的第二极与第三节点N3电连接；第五晶体管T5的控制极与第三扫描信号线G3电连接，第五晶体管T5的第一极与初始信号线INT电连接，第五晶体管T5的第二极与第四节点N4电连接；第六晶体管T6的控制极与发光控制信号线EM电连接，第六晶体管T6的第一极与第二电源线VDD2电连接，第六晶体管T6的第二极与第五节点N5电连接；第七晶体管T7的控制极与第三节点N3电连接，第七晶体管T7的第一极与第四节点N4电连接，第七晶体管T7的第二极与第五节点N5电连接；第二电容C2的一端与第三节点N3电连接，第二电容C2的另一端与第四节点N4电连接；第二发光元件D2的一端与第四节点N4电连接，第二发光元件D2的另一端与稳压线VSS电连接。
在示例性实施方式中，如图15所示，以第二像素电路中第三晶体管T3至第七晶体管T7均为N型薄膜晶体管为例，第二像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第一扫描信号线G1的信号为低电平信号，第二扫描信号线G2、第三扫描信号线G3和发光控制信号线EM的信号为高电平信号。第三扫描信号线G3的信号为高电平信号，使第五晶体管T5导通，初始信号线INT的初始电压信号提供至第四节点N4，对第二电容C2进行初始化，清除第二电容C2中原有数据电压。第一扫描信号线G1的信号为低电平信号，使第三晶体管T3断开，此阶段第二发光元件D2不发光。
第二阶段A2，称为阈值补偿阶段，第一扫描信号线G1和第三扫描信号线G3的信号为低电平信号，第二扫描信号线G2和发光控制信号线EM的信号为高电平信号。第二扫描信号线G2为高电平信号，使第四晶体管T4导通，参考信号线REF的参考电压信号写入第三节点N3，进而使得第七晶体管T7导通。发光控制信号线EM的信号为高电平信号，使得第六晶体管T6导通，此时第二电源线VDD2的电源电压向第七晶体管T7充电，不断抬升第四节点N4的电压，直到第七晶体管T7的栅源电压Vgs达到第七晶体管T7的阈值电压Vth，第七晶体管T7自动断开。
第三阶段A3，称为数据写入阶段，第二扫描信号线G2、第三扫描信号线G3和发光控制信号线EM的信号为低电平信号，第一扫描信号线G1的信号为高电平信号。发光控制信号线EM的信号为低电平信号，使第六晶体管T6断开，第一扫描信号线G1的信号为高电平信号，使第三晶体管T3导通，第二数据信号线Data2的数据信号经过第三晶体管T3写入第三节点N3。
第四阶段A4，称为发光阶段，第一扫描信号线G1、第二扫描信号线G2和第三扫描信号线G3的信号为低电平信号，发光控制信号线EM的信号为高电平信号。发光控制信号线EM的信号为高电平信号，使第六晶体管T6导通。由于第二电容C2的存储作用，第七晶体管T7的控制极电压仍可继续保持数据信号电压，使得第七晶体管T7处于导通状态，第二电源线VDD2输出的电源电压通过导通的第六晶体管T6和第七晶体管T7向第二发光元件D2的一端提供驱动电压，驱动第二发光元件D2发光。
在第二像素电路驱动过程中，流过第七晶体管T7(驱动晶体管)的驱动电流由其控制极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第七晶体管T7的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vdata+|Vth|)-Vth] 2＝K*[(Vdd-Vdata] 2
其中，I为流过第七晶体管T7的驱动电流，也就是驱动第二发光元件D2的驱动电流，K为常数，Vgs为第七晶体管T7的栅电极和第一极之间的电压差，Vth为第七晶体管T7的阈值电压，Vdata为第二数据信号线Data2输出的数据电压，Vdd为第二电源线VDD2输出的电源电压。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
图4为本公开示例性实施例一种显示基板的平面结构示意图。如图4所示，在平行于显示基板的平面内，显示基板包括显示区域以及安装区域，在垂直于显示基板的平面内，显示基板包括衬底基板、设置在衬底基板上的驱动结构层以及设置在驱动结构层上的发光元件。安装区域的驱动结构层包括 第一像素电路，显示区域的驱动结构层包括第二像素电路，第一像素电路包括第一晶体管T1、第二晶体管T2及第一电容C1，第二像素电路包括第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7以及第二电容C2。每个晶体管包括有源层、控制极、第一极和第二极，每个电容包括相对设置的两个极板。
在一些示例性实施例中，驱动结构层包括层叠设置在衬底基板上的半导体层、第一绝缘层、第一栅金属层、第二绝缘层、第二栅金属层、第三绝缘层、第一源漏金属层和第四绝缘层。
其中，半导体层包括参考信号线REF以及多个晶体管的有源层；第一栅金属层包括多个晶体管的控制极、第一电源线VDD1、第一扫描信号线G1、第二扫描信号线G2、第三扫描信号线G3、发光控制信号线EM、第一电容C1的第一极板C1-1、第二电容C2的第三极板C2-1；第二栅金属层包括第一电容C1的第二极板C1-2、第二电容C2的第四极板C2-2和初始信号线INT；第一源漏金属层包括多个晶体管的第一极和第二极、第一连接线L1、第二连接线L2、第三连接线L3、第四连接线L4、第五连接线L5、第六连接线L6、第七连接线L7、第八连接线L8、第一数据信号线Data1、第二数据信号线Data2和第二电源线VDD2；多个晶体管的第一极和第二极分别通过第一绝缘层、第二绝缘层和第三绝缘层上的过孔与多个晶体管的有源层的两端连接。
在一些示例性实施例中，如图4所示，第一晶体管T1的控制极11、第三晶体管T3的控制极31与第一扫描信号线G1相互连接成一体结构，第一晶体管T1的第一极12与第一数据信号线Data1相互连接成一体结构，第一晶体管T1的第二极13与第一连接线L1相互连接成一体结构，第一连接线L1通过第二绝缘层和第三绝缘层上的过孔与第二晶体管T2的控制极21、第一电容C1的第一极板C1-1连接；第二晶体管T2的第一极22与第三连接线L3相互连接成一体结构，第三连接线L3通过第二绝缘层和第三绝缘层上的过孔与第一电源线VDD1连接，第二电源线VDD2通过第二绝缘层和第三绝缘层上的过孔与第一电源线VDD1电连接，第二晶体管T2的第二极23与第二连接线L2相互连接成一体结构，第二连接线L2通过第三绝缘层上的过孔 与第一电容C1的第二极板C1-2连接。
在一些示例性实施例中，如图4所示，第三晶体管T3的第一极32与第二数据信号线Data2相互连接成一体结构，第三晶体管T3的第二极33、第四晶体管T4的第二极43与第五连接线L5相互连接成一体结构，第五连接线L5通过第二绝缘层和第三绝缘层上的过孔与第七晶体管T7的控制极71、第二电容C2的第三极板C2-1连接。第四晶体管T4的第一极42与第六连接线L6相互连接成一体结构，第六连接线L6通过第一绝缘层、第二绝缘层和第三绝缘层上的过孔与参考信号线REF连接。第五晶体管T5的控制极51与第三扫描信号线G3相互连接成一体结构，第五晶体管T5的第一极52通过第三绝缘层上的过孔与初始信号线INT电连接，第五晶体管T5的第二极53与第七连接线L7相互连接成一体结构，第七连接线L7通过第三绝缘层上的过孔与第二电容C2的第四极板C2-2电连接。第七晶体管T7的第一极72通过第三绝缘层上的过孔与第二电容C2的第四极板C2-2电连接。第六晶体管T6的控制极61与发光控制信号线EM相互连接成一体结构，第六晶体管T6的第一极62通过第二绝缘层和第三绝缘层上的过孔与第一电源线VDD1电连接，第六晶体管T6的第二极63与第八连接线L8、第七晶体管T7的第二极73相互连接成一体结构。
下面通过显示基板的制备过程，示例性说明本公开实施例显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
在一些示例性实施例中，图4所示的显示基板的制备过程可以包括如下步骤：
(1)在衬底基板上形成半导体层图案。在衬底基板上形成半导体层图案包括：先在衬底基板上沉积一层缓冲薄膜，形成覆盖整个衬底基板的缓冲层图案。随后沉积一层有源层薄膜，通过构图工艺对有源层薄膜进行构图，形成设置在缓冲层上的半导体层图案，如图5所示。其中，半导体层图案可以包括第一晶体管T1的有源层10、第二晶体管T2的有源层20、第三晶体管T3的有源层30、第四晶体管T4的有源层40、第五晶体管T5的有源层50、第六晶体管T6的有源层60和第七晶体管T7的有源层70。
在一些示例性实施例中，如图5所示，第一晶体管T1的有源层10和第二晶体管T2的有源层20设置在安装区域101，第三晶体管T3的有源层30、第四晶体管T4的有源层40、第五晶体管T5的有源层50、第六晶体管T6的有源层60和第七晶体管T7的有源层70设置在显示区域100。
在一些示例性实施例中，如图5所示，第一晶体管T1的有源层10包括第一沟道区域，第三晶体管T3的有源层30包括第三沟道区域，第四晶体管T4的有源层40包括第四沟道区域，第六晶体管T6的有源层60包括第六沟道区域，第一沟道区域、第三沟道区域、第四沟道区域以及第六沟道区域均沿第一方向X延伸。第二晶体管T2的有源层20包括第二沟道区域，第七晶体管T7的有源层70包括第七沟道区域，第二沟道区域以及第七沟道区域均沿第二方向Y延伸。第五晶体管T5的有源层50包括第五沟道区域，第五沟道区域包括相互连接的第一子沟道区域和第二子沟道区域，第一子沟道区域沿第一方向X延伸，第二子沟道区域沿第二方向Y延伸。
在一些示例性实施例中，如图5所示，半导体层图案还可以包括参考信号线REF，参考信号线REF用于为第二像素电路提供参考电压信号。
(2)形成第一栅金属层图案。形成第一栅金属层图案包括：在形成上述结构的衬底基板上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖半导体层的第一绝缘层以及设置在第一绝缘层上的第一栅金属层图案。
如图6所示，第一栅金属层图案包括：第一晶体管T1的控制极至第七晶体管T7的控制极、第一扫描信号线G1、第二扫描信号线G2、第三扫描信号线G3、发光控制信号线EM、第一电容C1的第一极板C1-1、第二电容C2的第三极板C2-1。
在一些示例性实施例中，如图6所示，第一栅金属层图案还包括：第一电源线VDD1，第一电源线VDD1沿第一方向X延伸，第一电源线VDD1包括位于安装区域101内的第一连接部VDD1-1、位于显示区域100内的第二连接部VDD1-2以及用于连接第一连接部VDD1-1与第二连接部VDD1-2的第一弯折部VDD1-3。
在一些示例性实施例中，第一电源线VDD1与后续形成的第二电源线VDD2、第六晶体管T6的第一极62与第二晶体管T2的第一极22连接。
在一些示例性实施例中，如图6所示，第一扫描信号线G1与第一晶体管T1的控制极11、第三晶体管T3的控制极31相互连接成一体结构，第二扫描信号线G2与第二晶体管T2的控制极21相互连接成一体结构，第三扫描信号线G3与第五晶体管T5的控制极51相互连接成一体结构，发光控制信号线EM与第六晶体管T6的控制极61相互连接成一体结构。
在一些示例性实施例中，第一晶体管T1、第三晶体管T3、第四晶体管T4与第五晶体管T5均为双栅薄膜晶体管。如图11所示，第一晶体管T1的控制极11、第三晶体管T3的控制极31、第四晶体管T4的控制极41与第五晶体管T5的控制极51分别包括两个凸起，从而形成了双栅结构的薄膜晶体管。
在一些示例性实施例中，如图2和图6所示，第三扫描信号线G3包括位于安装区域内的第三连接部G3-1、位于显示区域内的第四连接部G3-2以及用于连接第三连接部G3-1和第四连接部G3-2的第二弯折部G3-3，第二弯折部G3-3被配置为使得第三连接部G3-1与第一像素开口区1011之间的距离h3小于第四连接部G3-2与第二像素开口区1001之间的距离h4。
在一些示例性实施例中，第二晶体管T2的控制极21、第七晶体管T7的控制极71设置在第一扫描信号线G1和第三扫描信号线G3之间。
在一些示例性实施例中，第二晶体管T2的控制极21与第一电容C1的第一极板C1-1相互连接成一体结构，第七晶体管T7的控制极71与第二电容C2的第三极板C2-1相互连接成一体结构。
在一些示例性实施例中，形成第一金属层图案后，可以利用第一金属层作为遮挡，对半导体层进行导体化处理，被第一金属层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的有源层的沟道区域，未被第一金属层遮挡区域的半导体层被导体化。
(3)形成第二栅金属层图案。形成第二栅金属层图案包括：在形成上述结构的衬底基板上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层和第一绝缘层的第二绝缘层以及设置在第二绝缘层上的第二栅金属层图案。
如图7所示，第二栅金属层图案包括：第二极板C1-2以及第四极板C2-2，其中，第二极板C1-2的位置与第一极板C1-1的位置相对应，构成第一电容C1；第三极板C2-1的位置与第四极板C2-2的位置相对应，构成第二电容C2。
在一些示例性实施例中，如图7所示，第二栅金属层图案还可以包括：初始信号线INT，初始信号线INT用于为第二像素电路提供初始电压信号。
在一些示例性实施例中，如图2和图7所示，初始信号线INT包括位于安装区域内的第五连接部INT-1、位于显示区域内的第六连接部INT-2以及用于连接第五连接部INT-1和第六连接部INT-2的第三弯折部INT-3，第三弯折部INT-3被配置为使得第五连接部INT-1与第一像素开口区1011之间的距离h5小于第六连接部INT-2与第二像素开口区1001之间的距离h6。
(4)形成第三绝缘层图案。形成第三绝缘层图案包括：在形成上述结构的衬底基板上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成开设有多个过孔的第三绝缘层图案，多个过孔包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11以及第十二过孔V12，如图8所示。
在一些示例性实施例中，第一过孔V1配置为使后续形成的多个晶体管T1～T7的第一极12～72与第二极13～73与多个晶体管T1～T7的有源层10～70的两端电连接，第二过孔V2配置为使后续形成的第一连接线L1与第二晶体管T2的控制极21以及第一电容C1的第一极板C1-1电连接，第三过孔V3配置为使后续形成的第三连接线L3与第一电源线VDD1电连接，第四过孔V4配置为使后续形成的第二连接线L2与第一电容C1的第二极板C1-2电连接，第五过孔V5配置为使后续形成的第四连接线L4与第一电容C1的第二极板C1-2连接。第六过孔V6配置为使后续形成的第五连接线L5与第七晶体管T7的控制极71以及第二电容C2的第三极板C2-1连接，第七过孔V7配置为使后续形成的第六连接线L6与参考信号线REF连接，第八过孔V8配置为使后续形成的第五晶体管T5的第一极52与初始信号线INT电连接，第九过孔V9配置为使后续形成的第七连接线L7与第二电容C2的第四极板C2-2电连接，第十过孔V10配置为使后续形成的第七晶体管T7的第一极72与第二电容C2的第四极板C2-2电连接，第十一过孔V11配置为使后续形成的第六晶体管T6的第一极62与第一电源线VDD1电连接，第十二过孔V12配置为使后续形成的第二电源线VDD2与第一电源线VDD1电连接。
(5)形成第一源漏金属层图案。形成第一源漏金属层图案包括：在形成上述结构的衬底基板上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第一源漏金属层图案。如图8所示，第一源漏金属层包括第一晶体管T1的第一极12至第七晶体管T7的第一极72、第一晶体管T1的第二极13至第七晶体管T7的第二极73、第一连接线L1、第二连接线L2、第三连接线L3、第四连接线L4、第五连接线L5、第六连接线L6、第七连接线L7、第八连接线L8、第二电源线VDD2、第一数据信号线Data1以及第二数据信号线Data2，多个晶体管的第一极和第二极分别通过两个第一过孔与其对应的有源层连接。
在一些示例性实施例中，多个晶体管T1～T7的第一极12～72与第二极13～73通过多个第一过孔V1与多个晶体管T1～T7的有源层10～70的两端连接，第一晶体管T1的第一极12与第一数据信号线Data1相互连接成一体结构，第一晶体管T1的第二极13与第一连接线L1相互连接成一体结构，第 一连接线L1通过第二过孔V2与第二晶体管T2的控制极21、第一电容C1的第一极板C1-1连接。第二晶体管T2的第一极22与第三连接线L3相互连接成一体结构，第三连接线L3通过第三过孔V3与第一电源线VDD1连接，第二晶体管T2的第二极23与第二连接线L2相互连接成一体结构，第二连接线L2通过第四过孔V4与第一电容C1的第二极板C1-2连接。第四连接线L4通过第五过孔V5与第一电容C1的第二极板C1-2连接。
在一些示例性实施例中，第三晶体管T3的第一极32与第二数据信号线Data2相互连接成一体结构，第三晶体管T3的第二极33、第四晶体管T4的第二极43与第五连接线L5相互连接成一体结构，第五连接线L5通过第六过孔V6与第七晶体管T7的控制极71、第二电容C2的第三极板C2-1连接。第四晶体管T4的的第一极42与第六连接线L6相互连接成一体结构，第六连接线L6通过第七过孔V7与参考信号线REF连接。第五晶体管T5的第一极52通过第八过孔V8与初始信号线INT电连接，第五晶体管T5的第二极53与第七连接线L7相互连接成一体结构，第七连接线L7通过第九过孔V9与第二电容C2的第四极板C2-2电连接。第七晶体管T7的第一极72通过第十过孔V10与第二电容C2的第四极板C2-2电连接。第六晶体管T6的第一极62通过第十一过孔V11与第一电源线VDD1电连接，第六晶体管T6的第二极63与第八连接线L8、第七晶体管T7的第二极73相互连接成一体结构。第二电源线VDD2通过第十二过孔V12与第一电源线VDD1电连接。
通过上述过程，在衬底基板上完成了驱动结构层的制备。其中，驱动结构层包括设置在衬底基板上的半导体层、设置在半导体层上的第一绝缘层、设置在第一绝缘层上的第一栅金属层、设置在第一栅金属层上的第二绝缘层以及设置在第二绝缘层上的第二栅金属层、设置在第二栅金属层上的第三绝缘层以及设置在第三绝缘层上的第一源漏金属层，扫描线和数据线垂直交叉限定出子像素，由有源层、控制极、第一极和第二极构成的薄膜晶体管设置在子像素内。其中，第一绝缘层和第二绝缘层也称之为栅绝缘层(GI)，第三绝缘层也称之为层间绝缘层(ILD)。
(6)形成第四绝缘层图案。形成第四绝缘层图案包括：在形成前述图案的基底上涂覆第四绝缘薄膜，通过掩膜曝光显影的光刻工艺形成覆盖第一源 漏金属层的第四绝缘层图案，第四绝缘层开设有第十三过孔V13和第十四过孔V14，第十三过孔V13暴露出第四连接线L4，第十四过孔V14暴露出第七连接线L7，如图9所示。其中，第四绝缘层也称之为平坦化层(PLN)。
(7)形成阳极图案。形成阳极图案包括：在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成第一阳极AN1和第二阳极AN2图案，第一阳极AN1位于安装区域，第二阳极AN2位于显示区域，第一阳极AN1通过第十三过孔V13与第四连接线L4连接，第二阳极AN2通过第十四过孔V14与第七连接线L7连接，如图4和图9所示。其中，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
在一些示例性实施例中，第一阳极AN1在衬底基板上的正投影的面积小于第二阳极AN2在衬底基板上的正投影的面积。
(8)形成像素定义层图案。形成像素定义层图案包括：在形成前述图案的基底上涂覆像素定义薄膜，通过光刻工艺形成像素定义层(Pixel Define Layer)图案，像素定义层图案在每个子像素限定出暴露阳极的像素开口区域，如图10所示，像素定义层图案在安装区域101限定出第一像素开口区1011，在显示区域100限定出第二像素开口区1001。其中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等，第一像素开口区1011和第二像素开口区1001的大小可以根据实际需要进行限定，示例性的，第一像素开口区1011的开口大小可以和第二像素开口区1001的开口大小相同，本公开实施例对此不作限制。
在一些示例性实施例中，后续制备流程可以包括：采用蒸镀工艺形成有机发光层，有机发光层至少部分设置在像素开口内，有机发光层与阳极连接；在有机发光层上形成阴极，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色的光线。随后，形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光器件。
在示例性实施方式中，有机发光层可以至少包括在阳极上叠设的空穴注 入层、空穴传输层、发光层和空穴阻挡层。在示例性实施方式中，所有子像素的空穴注入层是连接在一起的共通层，所有子像素的空穴传输层是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层是连接在一起的共通层。
在示例性实施方式中，衬底基板可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在一些示例性实施例中，第一栅金属层、第二栅金属层和第一源漏金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层和第二绝缘层称为栅绝缘(GI)层，第三绝缘层称为层间绝缘(ILD)层。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。第四绝缘层可以采用有机材料，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做具体的限定。
从以上描述的显示基板的结构以及制备过程可以看出，本公开实施例提供的显示基板，通过设置与数据线相交的第一电源线VDD1，安装区域101不需要设置与数据线平行的第二电源线VDD2，有效减少了安装区域101的金属走线占用面积，增加了安装区域101的光透过率，提高了前置摄像头的自拍、人脸识别等摄像功能。此外，本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
进一步地，本公开实施例的显示基板，通过在安装区域101的驱动结构层中设置第一像素电路，在显示区域的驱动结构层中设置第二像素电路，且第一像素电路中的晶体管数量少于第二像素电路中的晶体管数量，进一步减少了安装区域101的金属走线占用面积，增加了安装区域101的光透过率，提高了前置摄像头的自拍、人脸识别等摄像功能。
本公开还提供一种显示基板的制备方法，以制备上述实施例提供的显示基板。在一些示例性实施例中，如图16所示，该显示基板的制备方法可以包括以下步骤：
步骤S1、在衬底基板上形成驱动结构层，所述驱动结构层包括设置在衬底基板上的缓冲层、设置在缓冲层上的半导体层、覆盖半导体层的第一绝缘层、设置在第一绝缘层上的第一栅金属层、覆盖第一栅金属层的第二绝缘层、设置在第二绝缘层上的第二栅金属层、覆盖第二栅金属层的第三绝缘层、设置在第三绝缘层上的第一源漏金属层以及覆盖第一源漏金属层的平坦层；第一栅金属层和第二栅金属层中的至少一层包括第一电源线，第一电源线沿第一方向延伸，第一源漏金属层包括数据线，数据线沿第二方向延伸，第一方向与所述第二方向相交；
步骤S2、在驱动结构层上形成发光元件。
在一些示例性实施例中，第一栅金属层和第二栅金属层中的至少一层还 包括发光控制信号线和至少一根扫描信号线，发光控制信号线和扫描信号线均沿第一方向延伸，第一电源线位于发光控制信号线和至少一根扫描信号线之间。
在一些示例性实施例中，第一电源线包括至少一个第一弯折部，第一弯折部沿第二方向延伸。
在一些示例性实施例中，第一源漏金属层还包括第二电源线，第二电源线沿第二方向延伸，第一电源线通过所述第三绝缘层上的过孔，或者，通过第三绝缘层和第二绝缘层上的过孔与第二电源线电连接。
在一些示例性实施例中，所述显示基板包括显示区域和安装区域，所述安装区域包括第一像素电路，所述显示区域包括第二像素电路，其中：所述第一像素电路和所述第二像素电路分别包括至少一个晶体管，所述第一像素电路中的晶体管数量少于第二像素电路中的晶体管数量。
本公开提供的显示基板的制备方法所制备的显示基板，其实现原理和实现效果与前述的显示基板的实现原理和实现效果类似，在此不再赘述。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (12)

  1. 一种显示基板，在垂直于所述显示基板的平面上，所述显示基板包括衬底基板、设置在所述衬底基板上的缓冲层、设置在所述缓冲层上的半导体层、覆盖所述半导体层的第一绝缘层、设置在所述第一绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第二绝缘层、设置在所述第二绝缘层上的第二栅金属层、覆盖所述第二栅金属层的第三绝缘层、设置在所述第三绝缘层上的第一源漏金属层以及覆盖所述第一源漏金属层的平坦层；
    所述第一栅金属层和第二栅金属层中的至少一层包括第一电源线，所述第一电源线沿第一方向延伸，所述第一源漏金属层包括数据线，所述数据线沿第二方向延伸，所述第一方向与所述第二方向相交。
  2. 根据权利要求1所述的显示基板，其中，所述第一栅金属层和第二栅金属层中的至少一层还包括发光控制信号线和至少一根扫描信号线，所述发光控制信号线和扫描信号线均沿第一方向延伸，所述第一电源线位于所述发光控制信号线和至少一根扫描信号线之间。
  3. 根据权利要求1所述的显示基板，其中，所述第一电源线包括至少一个第一弯折部，所述第一弯折部沿所述第二方向延伸。
  4. 根据权利要求1所述的显示基板，其中，所述第一源漏金属层还包括第二电源线，所述第二电源线沿第二方向延伸，所述第一电源线通过所述第三绝缘层上的过孔，或者，通过所述第三绝缘层和第二绝缘层上的过孔与所述第二电源线电连接。
  5. 根据权利要求1所述的显示基板，其中，所述第一源漏金属层还包括第八连接线，所述第八连接线沿所述第二方向延伸，所述第八连接线在所述衬底基板上的正投影与所述第一电源线在所述衬底基板上的正投影相交。
  6. 根据权利要求1所述的显示基板，其中，所述半导体层包括第三沟道区域、第四沟道区域、第五沟道区域、第六沟道区域和第七沟道区域，所述第三沟道区域、第四沟道区域以及第六沟道区域均沿所述第一方向延伸，所 述第七沟道区域沿所述第二方向延伸，所述第五沟道区域包括相互连接的第一子沟道区域和第二子沟道区域，所述第一子沟道区域沿所述第一方向延伸，所述第二子沟道区域沿所述第二方向延伸。
  7. 根据权利要求1所述的显示基板，其中，所述半导体层包括参考信号线，所述参考信号线用于提供参考电压信号，所述参考信号线沿所述第一方向延伸。
  8. 根据权利要求1所述的显示基板，其中，所述第二栅金属层包括初始信号线，所述初始信号线用于提供初始电压信号；
    所述初始信号线包括至少一个第三弯折部，所述第三弯折部沿所述第二方向延伸。
  9. 根据权利要求1所述的显示基板，其中，所述显示基板包括显示区域和安装区域，所述安装区域包括第一像素电路，所述显示区域包括第二像素电路，其中：
    所述第一像素电路和所述第二像素电路分别包括至少一个晶体管，所述第一像素电路中的晶体管数量少于第二像素电路中的晶体管数量。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括设置在所述平坦层上的阳极，其中：
    所述阳极包括第一阳极和第二阳极，所述第一阳极位于所述安装区域，所述第二阳极位于所述显示区域，所述第一阳极在所述衬底基板上的正投影的面积小于所述第二阳极在所述衬底基板上的正投影的面积。
  11. 一种显示装置，包括：如权利要求1至10任一所述的显示基板。
  12. 一种显示基板的制备方法，包括：
    在衬底基板上形成驱动结构层，所述驱动结构层包括设置在所述衬底基板上的缓冲层、设置在所述缓冲层上的半导体层、覆盖所述半导体层的第一绝缘层、设置在所述第一绝缘层上的第一栅金属层、覆盖所述第一栅金属层的第二绝缘层、设置在所述第二绝缘层上的第二栅金属层、覆盖所述第二栅 金属层的第三绝缘层、设置在所述第三绝缘层上的第一源漏金属层以及覆盖所述第一源漏金属层的平坦层；所述第一栅金属层和第二栅金属层中的至少一层包括第一电源线，所述第一电源线沿第一方向延伸，所述第一源漏金属层包括数据线，所述数据线沿第二方向延伸，所述第一方向与所述第二方向相交；
    在所述驱动结构层上形成发光元件。
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