WO2023115457A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2023115457A1
WO2023115457A1 PCT/CN2021/140857 CN2021140857W WO2023115457A1 WO 2023115457 A1 WO2023115457 A1 WO 2023115457A1 CN 2021140857 W CN2021140857 W CN 2021140857W WO 2023115457 A1 WO2023115457 A1 WO 2023115457A1
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Prior art keywords
signal line
transistor
reset
sub
pixel
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PCT/CN2021/140857
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English (en)
French (fr)
Inventor
张跳梅
于子阳
陈文波
青海刚
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180004161.6A priority Critical patent/CN116686414B/zh
Priority to PCT/CN2021/140857 priority patent/WO2023115457A1/zh
Publication of WO2023115457A1 publication Critical patent/WO2023115457A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular, refer to a display substrate, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • An embodiment of the present disclosure provides a display substrate, including a plurality of sub-pixels, at least one of the sub-pixels includes a pixel driving circuit and a light emitting device, the pixel driving circuit includes an initial signal line, a reset signal line and a plurality of transistors, the The initial signal line includes a first branch; the plurality of transistors includes a drive transistor, a first reset transistor and a second reset transistor, the drive transistor is configured to provide a drive current for the light emitting device, and the first reset transistor is controlled by Configured to reset the gate of the drive transistor through the first branch of the initial signal line under the control of the reset signal line; the second reset transistor is configured to reset under the control of the reset signal line Next, the first end of the light emitting device is reset through the first branch of the initial signal line; the first reset transistor and the second reset transistor in the same sub-pixel are controlled through the same reset signal line .
  • the first branch of the initial signal line extends along a first direction, and the first branch of the initial signal line is disposed on the same layer as the active layer of the plurality of transistors.
  • the pixel driving circuit further includes a storage capacitor
  • both the first reset transistor and the second reset transistor are located between the first branch of the initial signal line and the storage capacitor.
  • the first reset transistor is located on one side of the second reset transistor along the first direction.
  • the pixel driving circuit further includes a first light emission control transistor, a second light emission control transistor, and an anode connection electrode, and the anode connection electrode is connected to the first light emission control transistor of the first light emission control transistor through an anode via hole. Diode connection, where:
  • the first light emission control transistor, the anode via hole and the second light emission control transistor are arranged along the first direction, and the anode via hole is located between the first light emission control transistor and the second light emission control transistor. between transistors.
  • the active layers of the plurality of transistors include a channel region, a first region on one side of the channel region corresponding to the source electrode, and a first region on the other side of the channel region The side is used for the second region corresponding to the drain electrode, the first region of the active layer of the first reset transistor, the first region of the active layer of the second reset transistor, and the first region of the initial signal line.
  • the branches are connected to each other to form a unified structure.
  • the active layer of the first reset transistor is "L" shaped
  • the reset signal line is provided with a first bump in each sub-pixel
  • the reset signal line and the first A region where a bump overlaps with a channel region of the first reset transistor is used as a gate electrode of a double-gate structure of the first reset transistor.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base. a conductive layer, and an insulating layer disposed between the semiconductor layer and the first conductive layer or between each conductive layer;
  • the semiconductor layer includes active layers of a plurality of transistors and the first branch of the initial signal line, the first conductive layer includes gate electrodes of the plurality of transistors, a reset signal line and a first plate of a storage capacitor, so The second conductive layer includes a second plate of the storage capacitor, the third conductive layer includes a second connection electrode, and the fourth conductive layer includes a second branch of an initial signal line;
  • the second connection electrode is configured to connect the gate electrode of the driving transistor and the second region of the first reset transistor through a via hole on the insulating layer, and the second branch of the initial signal line passes through the via hole on the insulating layer.
  • the via hole is connected to the first branch of the initial signal line;
  • the orthographic projection of the second branch of the initial signal line on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode on the substrate.
  • the second branch of the initial signal line includes a main body and a bent part, the main body extends along the second direction, the bent part includes two first extensions and a A second extension portion between the two first extension portions, the first extension portion extends along a first direction, the second extension portion extends along the second direction, the first direction and the The second direction intersects, and the width of the second extension portion along the first direction is larger than the width of the main body portion along the first direction.
  • the third conductive layer further includes a first power line, a first connection electrode, and a fourth connection electrode
  • the fourth conductive layer further includes an anode connection electrode
  • the light emission control transistor includes a first a light emitting control transistor
  • the anode connection electrode is connected to the first connection electrode and the fourth connection electrode through a via hole in the insulating layer, and the first connection electrode is connected to the first connection electrode of the first light emission control transistor through a via hole in the insulation layer.
  • the second region, the fourth connection electrode is connected to the second region of the second reset transistor through a via hole on the insulating layer;
  • the orthographic projection of the anode connection electrode on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate.
  • the orthographic projection of the anode connection electrode on the substrate at least partially overlaps with the orthographic projection of the second electrode of the first reset transistor on the substrate.
  • the fourth conductive layer further includes a fifth connection electrode and a third branch of the initial signal line;
  • a third branch of the initial signal line extends along a first direction, a second branch of the initial signal line extends along a second direction, and the first direction crosses the second direction;
  • the fifth connection electrode, the second branch of the initial signal line, and the third branch of the initial signal line are connected to each other to form an integrated structure, and the orthographic projection of the third branch of the initial signal line on the substrate is consistent with the Orthographic projections of the first branch of the initial signal line on the substrate at least partially overlap.
  • the display substrate further includes a dummy pixel row between the plurality of sub-pixels, the dummy pixel row includes a plurality of dummy sub-pixels, and the dummy sub-pixel includes a dummy pixel driving circuit,
  • the dummy pixel driving circuit includes a dummy reset transistor and a dummy data write transistor, and the channel region of the dummy reset transistor and the dummy data write transistor are both fracture structures.
  • the dummy pixel driving circuit includes a dummy storage capacitor, a dummy initial signal line, a dummy reset signal line, a dummy light-emitting signal line, and a dummy scan signal line.
  • the first pole plate and the virtual scanning signal line are connected to each other to form an integral structure, and the first pole plate and the second pole plate of the virtual storage capacitor and the virtual reset signal line are respectively connected to the first pole plate and the first pole plate through the via hole on the insulating layer. Power cord connection.
  • An embodiment of the present disclosure also provides a display substrate, including a plurality of sub-pixels and a dummy pixel row between the plurality of sub-pixels, at least one of the sub-pixels includes a pixel driving circuit and a light emitting device, and the pixel driving circuit includes an initial signal line, a reset signal line, a scanning signal line, a light emitting signal line and a plurality of transistors;
  • the plurality of transistors include a driving transistor, a first reset transistor and a second reset transistor, the driving transistor is configured to provide a driving current for the light emitting device, and the first reset transistor is configured to connect to the reset signal line Under the control of the initial signal line, the gate of the driving transistor is reset, and the second reset transistor is configured to reset the gate of the driving transistor through the initial signal line under the control of the scanning signal line.
  • the anode of the device is reset;
  • the display substrate includes a plurality of gate connection electrodes, the plurality of gate connection electrodes straddle the dummy pixel row, and the gate connection electrodes are configured to connect A gate electrode of a reset transistor and a gate electrode of a second reset transistor located on the other side of the dummy pixel row.
  • the gate connection electrode is located on a different conductive layer from the gate electrodes of the plurality of transistors.
  • An embodiment of the present disclosure also provides a display device, including the display substrate as described in any one of the preceding items.
  • An embodiment of the present disclosure also provides a method for driving a display substrate, the display substrate includes a plurality of sub-pixels, at least one of the sub-pixels includes a pixel driving circuit and a light emitting device, and the pixel driving circuit includes a driving sub-circuit, a first The reset subcircuit, the second reset subcircuit, the data writing subcircuit, the compensation subcircuit and the light emission control subcircuit, the driving method includes:
  • the first reset subcircuit resets the control terminal of the driving subcircuit under the control of the reset signal; the second reset subcircuit resets the The first end of the device is reset; the first reset sub-circuit and the second reset sub-circuit in the same sub-pixel are controlled through the same reset signal line;
  • the data writing sub-circuit writes the data signal into the driving sub-circuit under the control of the scanning signal, and the compensation sub-circuit compensates the driving sub-circuit;
  • the light-emitting control subcircuit applies the driving current generated by the driving sub-circuit to the light-emitting device under the control of the light-emitting signal to make it emit light.
  • FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure
  • FIG. 2a and FIG. 2b are schematic diagrams of arrangement structures of two sub-pixels according to an embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of driving timing of the pixel circuit shown in FIG. 3;
  • FIG. 5a is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • Fig. 5b is a schematic diagram of the pixel arrangement structure in area B in Fig. 5a;
  • Fig. 5c is a schematic diagram of a gate driver on array (Gate driver On Array, GOA) load in a display area;
  • FIG. 6a is a schematic diagram of a GOA load in a display area according to an embodiment of the present disclosure
  • 6b is a schematic plan view of a display substrate after forming a fourth conductive layer for a normal pixel according to an embodiment of the present disclosure
  • Fig. 6c is a sectional view of A-A direction in Fig. 6b;
  • FIG. 6d is an equivalent circuit diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6e is a schematic plan view of the display substrate after the fourth conductive layer is formed in the four pixels in the dotted line area in FIG. 5b;
  • 7a is a schematic plan view of a semiconductor layer of a normal pixel
  • FIG. 7b is a schematic plan view of the display substrate after the four pixels in the dotted line area in FIG. 5b form a semiconductor layer;
  • 8a is a schematic plan view of a first conductive layer of a normal pixel
  • 8b is a schematic plan view of a display substrate after forming a first conductive layer for a normal pixel
  • FIG. 8c is a schematic plan view of the display substrate after the first conductive layer is formed for the four pixels in the dotted line area in FIG. 5b;
  • 9a is a schematic plan view of a second conductive layer of a normal pixel
  • 9b is a schematic plan view of a display substrate after forming a second conductive layer for a normal pixel
  • FIG. 9c is a schematic plan view of the display substrate after the second conductive layer is formed for the four pixels in the dotted line area in FIG. 5b;
  • FIG. 10a is a schematic plan view of a fourth insulating layer 94 of a normal pixel
  • FIG. 10b is a schematic plan view of a display substrate after forming a fourth insulating layer 94 for a normal pixel;
  • FIG. 10c is a schematic plan view of the display substrate after the fourth insulating layer 94 is formed in the four pixels in the dotted line area in FIG. 5b;
  • Fig. 11a is a schematic plan view of a third conductive layer of a normal pixel
  • 11b is a schematic plan view of a display substrate after forming a third conductive layer for a normal pixel
  • FIG. 11c is a schematic plan view of a display substrate after forming a third conductive layer for four pixels in the dotted line area in FIG. 5b;
  • Fig. 12a is a schematic plan view of a first flat layer of a normal pixel
  • 12b is a schematic plan view of a display substrate after forming a first flat layer for normal pixels
  • FIG. 12c is a schematic plan view of the display substrate after the four pixels in the dotted line area in FIG. 5b form the first flat layer;
  • FIG. 13 is a schematic plan view of a fourth conductive layer of a normal pixel
  • FIG. 14 is a schematic diagram of GOA load in another display area according to an embodiment of the present disclosure.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emission signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller can provide grayscale values and control signals suitable for the specifications of the data signal driver to the data signal driver, and can provide the clock signal and the scan start signal suitable for the specifications of the scan signal driver. etc.
  • the data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc.
  • the scan signal driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver can be constructed in the form of a shift register, and can generate scans in such a way that a scan start signal supplied in the form of a conduction level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal signal, m can be a natural number.
  • the lighting signal driver may generate emission signals to be supplied to the lighting signal lines E1, E2, E3, . . . , and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission signal driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting signal driver can be configured in the form of a shift register, and can generate the light emitting signal in a manner of sequentially transmitting the light emitting stop signal provided in the form of off-level pulses to the next-stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij, and each sub-pixel Pxij may be connected to a corresponding data signal line, a corresponding scanning signal line, and a corresponding light emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data signal line.
  • FIG. 2a and FIG. 2b are schematic diagrams of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a first sub-pixel P1 that emits light of a second color.
  • each of the four sub-pixels may include circuit units and light emitting devices, and the circuit units may include scanning signal lines, data signal lines and The light emitting signal line and the pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to receive the signal transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line The data voltage is used to output a corresponding current to the light emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • four sub-pixels may be arranged in a square (Square) manner to form a GGRB pixel arrangement, as shown in FIG. 2 a .
  • four sub-pixels may be arranged in a diamond shape (Diamond) to form an RGBG pixel arrangement, as shown in FIG. 2b.
  • the four sub-pixels may be arranged horizontally or vertically.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in the present disclosure.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction is called a pixel row
  • a plurality of sub-pixels arranged in sequence in the vertical direction are called a pixel column
  • a plurality of pixel rows and a plurality of pixel columns constitute a pixel array arranged in an array .
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 3, the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7), a storage capacitor C and a plurality of signal lines (data signal line D, scanning signal line Gate, reset signal line Reset, the initial signal line INIT, the first power line VDD, the second power line VSS and the light emitting signal line EM).
  • the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor T1 is connected to the first node N1 connect.
  • the gate electrode of the second transistor T2 is connected to the scanning signal line Gate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the gate electrode of the fourth transistor T4 is connected to the scanning signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first pole of the sixth transistor T6 is connected to the third node N3, the second pole of the sixth transistor T6 is connected to the fourth node N4 (ie, the first pole of the light emitting device )connect.
  • the gate electrode of the seventh transistor T7 is connected to the scanning signal line Gate, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the first node N1.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is continuously provided with a low level signal, and the signal of the first power line VDD is continuously provided with a high level Signal.
  • the scanning signal line Gate is the scanning signal line in the display row pixel driving circuit
  • the reset signal line Reset is the scanning signal line in the last display row pixel driving circuit, that is, for the nth display row
  • the scanning signal line Gate is Gate(n )
  • the reset signal line Reset is Gate (n-1)
  • the reset signal line Reset of this display row and the scanning signal line Gate in the pixel driving circuit of the previous display row can be the same signal line, so as to reduce the signal lines of the display panel, Realize narrow bezels of the display panel.
  • the scanning signal line Gate, the reset signal line Reset, the light emitting signal line E, and the initial signal line INIT all extend along the horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend along the Extend vertically.
  • the light emitting device may be an organic electroluminescent diode (OLED), including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 4 is a working timing diagram of the pixel driving circuit shown in FIG. 3 .
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 4.
  • the pixel driving circuit in FIG. signal lines (data signal line D, scanning signal line Gate, reset signal line Reset, initial signal line INIT, first power line VDD, second power line VSS and light emitting signal line EM), and 7 transistors are all P-type transistors .
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage, the signal of the reset signal line Reset is a low-level signal, and the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals.
  • the signal of the reset signal line Reset is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the first node N1 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the scanning signal line Gate and the light emitting signal line EM are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light at this stage .
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scanning signal line Gate is a low-level signal
  • the signal of the reset signal line Reset and the light-emitting signal line EM is a high-level signal
  • the data signal line D outputs data voltage.
  • the third transistor T3 is turned on.
  • the signal of the scanning signal line Gate is a low level signal so that the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the first node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. node N1, and charge the sum of the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage of the second terminal (second node N2) of the storage capacitor C is Vdata+Vth, Vdata is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3.
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the reset signal line Reset is a high level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line EM is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line EM is a low-level signal, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata+Vth, the driving current of the third transistor T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vdata is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • the current I flowing through the light emitting device has nothing to do with the threshold voltage Vth of the third transistor T3, which eliminates the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensures the uniformity of brightness.
  • the pixel circuit eliminates the residual positive charge of the light emitting device after the last light emission, realizes the compensation for the gate voltage of the third transistor, and avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light emitting device , improving the uniformity of the displayed image and the display quality of the display panel.
  • the ensuing problem is that the load (Loading) of the gate driver On Array (GOA) signal in the area where the dummy pixel row is not inserted in the effective display area and the area where the dummy pixel row is inserted will be different.
  • An embodiment of the present disclosure provides a display substrate, including a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device, the pixel driving circuit includes an initial signal line, a reset signal line, a light emitting signal line and a plurality of transistors, the initial signal the line includes the first branch;
  • the plurality of transistors include a driving transistor, a first reset transistor and a second reset transistor, the driving transistor is configured to provide a driving current for the light emitting device, and the first reset transistor is configured to pass through the first reset signal line of the initial signal line under the control of the reset signal line.
  • One branch resets the gate of the driving transistor; the second reset transistor is configured to reset the anode of the light emitting device through the first branch of the initial signal line under the control of the reset signal line;
  • the first reset transistor and the second reset transistor in the same sub-pixel are controlled through the same reset signal line.
  • the first reset transistor and the second reset transistor in each row of sub-pixels are controlled by the same reset signal line in the row of sub-pixels, that is, the same-level reset method is adopted. , so that the GOA of each row of sub-pixels drives a row of scanning signal lines and a row of reset signal lines, so that the charging time of different regions is the same, thereby improving the display effect of the display panel.
  • the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device, and the pixel driving circuit includes an initial signal line INIT, a reset signal line Reset, an emission signal line EM and a plurality of transistors ;
  • the plurality of transistors includes a drive transistor (ie, the third transistor T3 in FIG. 6b), a first reset transistor (ie, the first transistor T1 in FIG. 6b) and a second reset transistor (ie, the seventh transistor T7 in FIG. 6b),
  • the driving transistor is configured to provide a driving current for the light emitting device
  • the first reset transistor is configured to reset the gate of the driving transistor through the first branch INIT-1 of the initial signal line under the control of the reset signal line Reset
  • the second The reset transistor is configured to reset the first end of the light emitting device through the first branch INIT-1 of the initial signal line under the control of the reset signal line Reset;
  • the first reset transistor and the second reset transistor in the same sub-pixel are controlled through the same reset signal line Reset.
  • the plurality of transistors further includes a light emission control transistor configured to allow or prohibit the driving current from passing under the control of the light emission signal line.
  • the pixel driving circuit further includes a first light emission control transistor (that is, the fifth transistor T5 in FIG. 6b ), a second light emission control transistor (that is, the fifth transistor T5 in FIG. 6b ).
  • the sixth transistor T6) and the anode connection electrode 52, the anode connection electrode 52 is connected to the second pole of the first light emission control transistor through the anode via hole V14, wherein:
  • the first light emission control transistor, the anode via hole V14 and the second light emission control transistor are arranged along the first direction X, and the anode via hole V14 is located between the first light emission control transistor and the second light emission control transistor.
  • At least one sub-pixel is divided into a first region R1, a second region R2 and a third region R3 along the second direction Y, and the first region R1 and the third region R3 are respectively located in the second region
  • the driving transistor is located in the second region R2
  • the initial signal line INIT connected to the sub-pixel (the initial signal line INIT here includes the first branch INIT-1 of the initial signal line and/or the third branch of the initial signal line INIT-3, the second branch INIT-2 of the initial signal line spans the first region R1, the second region R2 and the third region R3) and the reset transistor is located in the first region R1, and the emission signal line EM connected to the sub-pixel is connected to the emission control
  • the transistor is located in the third region R3.
  • the initial signal line includes a first branch INIT-1, the first branch INIT-1 of the initial signal line extends along the first direction X, the first branch INIT-1 of the initial signal line is connected with a plurality of transistors
  • the active layer is set at the same layer.
  • the initial signal goes directly from the top of each sub-pixel through the semiconductor layer and passes through the shortest path to the first A node N1 is initialized, which effectively utilizes the layout space of pixels.
  • the pixel driving circuit further includes a storage capacitor C, and in the same sub-pixel, both the first reset transistor and the second reset transistor are located between the first branch INIT-1 of the initial signal line and the storage capacitor C .
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7 ) and 1 storage capacitor C. As shown in FIG. 6d , as shown in FIG. 6d , the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7 ) and 1 storage capacitor C. As shown in FIG. 6d , as shown in FIG. 6d , the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7 ) and 1 storage capacitor C. As shown in FIG.
  • the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor T1 is connected to the first node N1.
  • the gate electrode of the second transistor T2 is connected to the scanning signal line Gate, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the gate electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first pole of the sixth transistor T6 is connected to the third node N3, the second pole of the sixth transistor T6 is connected to the fourth node N4 (ie, the first pole of the light emitting device )connect.
  • the gate electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the first node N1.
  • the active layers of the plurality of transistors include a channel region, a first region located on one side of the channel region for corresponding to the source electrode, and a first region located on the other side of the channel region for corresponding to the drain electrode.
  • the first area of the active layer of the first reset transistor, the first area of the active layer of the second reset transistor, and the first branch INIT-1 of the initial signal line are connected to each other to form an integral structure.
  • the active layer of the first reset transistor is "L" shaped
  • the reset signal line Reset is provided with a first bump 21-1 in each sub-pixel
  • the reset signal line Reset and the first bump The area 21-1 overlapping with the channel area of the first reset transistor serves as the gate electrode of the double gate structure of the first reset transistor.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate 10 , and an insulating layer disposed between the semiconductor layer and the first conductive layer or between each conductive layer;
  • the semiconductor layer includes the active layer of a plurality of transistors and the first branch INIT-1 of the initial signal line, the first conductive layer includes the gate electrodes of the plurality of transistors, the reset signal line Reset and the first plate Ce1 of the storage capacitor, and the second The conductive layer includes the second plate Ce2 of the storage capacitor, the third conductive layer includes the second connection electrode 44, and the fourth conductive layer includes the second branch INIT-2 of the initial signal line;
  • the second connection electrode 44 is configured to connect the gate electrode of the driving transistor and the second region of the first reset transistor through the via hole on the insulating layer, and the second branch INIT-2 of the initial signal line is connected through the via hole on the insulating layer. the first branch INIT-1 of the initial signal line;
  • the orthographic projection of the second branch INIT- 2 of the initial signal line on the substrate 10 at least partially overlaps the orthographic projection of the second connection electrode 44 on the substrate 10 .
  • the second branch INIT-2 (located on the fourth conductive layer) of the initial signal line is vertically connected to form a network, and is wound at the position of the second connection electrode 44 (that is, the first node N1).
  • the connection electrode 44 is used for shielding and shielding. Since the pitch between the light-emitting area and the pixel circuit area is different, the environment above the first node N1 of each pixel circuit is different, which leads to the parasitic of the first node N1 of each pixel circuit. Capacitance is different, the embodiment of the present disclosure uses the second branch INIT-2 of the initial signal line to shield the second connection electrode 44 (that is, the first node N1), which reduces the influence of the upper layer metal on the first node N1, and optimizes display effect.
  • the second branch INIT-2 of the initial signal line includes a main part INIT-21 and a bent part, and the main part INIT-21 extends along the second direction Y
  • the bending portion includes two first extensions INIT-22 and a second extension INIT-23 disposed between the two first extensions INIT-22, the first extension INIT-22 extends along the first direction X,
  • the second extension INIT-23 extends along the second direction Y, the first direction X intersects the second direction Y (in an exemplary embodiment, the first direction X and the second direction Y are perpendicular to each other), the second extension INIT -23 has a width d2 along the first direction X greater than the width d1 of the main body INIT-21 along the first direction X.
  • the third conductive layer further includes a first power supply line VDD, a first connection electrode 43 and a fourth connection electrode 46, the fourth conductive layer further includes an anode connection electrode 52, and the light emission control transistor includes a first light emission control transistor.
  • control transistor ie the sixth transistor T6 in FIG. 6b or FIG. 6d;
  • the anode connection electrode 52 is connected to the first connection electrode 43 and the fourth connection electrode 46 through the via hole on the insulating layer, the first connection electrode 43 is connected to the second region of the first light emission control transistor through the via hole on the insulating layer, and the fourth connection The electrode 46 is connected to the second region of the second reset transistor through a via hole on the insulating layer;
  • the orthographic projection of the anode connection electrode 52 on the substrate 10 at least partially overlaps with the orthographic projection of the first power line VDD on the substrate 10 .
  • the first power supply line VDD shields the anode connection electrode 52 , reducing the impact of the metal in the lower layer on the anode connection electrode 52, and optimizing the display effect.
  • the orthographic projection of the anode connection electrode 52 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode of the first reset transistor on the substrate 10 .
  • the display substrate further includes a planar layer (not shown in the figure), an anode (not shown in the figure), an organic A light-emitting layer (not shown in the figure) and a cathode (not shown in the figure);
  • the anode is connected to the anode connection electrode 52 through the anode via hole (ie the fourteenth via V14 in FIG. 6e ) on the planar layer; the anode via hole is located in the third region R3.
  • the fourth conductive layer further includes the third branch INIT-3 connecting the fifth electrode 51 and the initial signal line;
  • the third branch INIT-3 of the initial signal line extends along the first direction X
  • the second branch INIT-2 of the initial signal line extends along the second direction Y
  • the first direction X crosses the second direction Y;
  • the fifth connection electrode 51, the second branch INIT-2 of the initial signal line and the third branch INIT-3 of the initial signal line are connected to form an integrated structure, and the orthographic projection of the third branch INIT-3 of the initial signal line on the substrate 10 , at least partially overlaps with the orthographic projection of the first branch INIT-1 of the initial signal line on the substrate 10 .
  • the third branch INIT-3 (located on the third conductive layer) of the initial signal line is connected in parallel with the first branch INIT-1 (located on the semiconductor layer) of the initial signal line, so as to reduce the signal load of the initial signal line INIT .
  • the display substrate further includes a dummy pixel row between a plurality of sub-pixels, the dummy pixel row includes a plurality of dummy sub-pixels, and the dummy sub-pixel includes a dummy pixel driver circuit, the dummy pixel driving circuit includes a dummy reset transistor, a dummy data write transistor, a channel region of the dummy reset transistor (that is, a region C in FIG. 7 b ) and a dummy data write transistor. area) are fractured structures.
  • the dummy pixel driving circuit includes a dummy storage capacitor, a dummy initial signal line, a dummy reset signal line, a dummy light emitting signal line, and a dummy scanning signal line.
  • the light-emitting signal line, the first pole plate of the virtual storage capacitor and the virtual scanning signal line are connected to each other to form an integrated structure, and the first pole plate and the second pole plate of the virtual storage capacitor and the virtual reset signal line respectively pass through the via holes on the insulating layer ( That is, the first via hole V1, the second via hole V2, and the thirteenth via hole V13) in FIG. 6e are connected to the first power line VDD.
  • the dummy reset transistor includes a dummy first transistor and a dummy seventh transistor, the second pole of the dummy first transistor is connected to the first power supply line VDD through the sixth via V6 in the dummy sub-pixel, and the dummy The second pole of the seventh transistor is connected to the first power line VDD through the seventh via hole V7 in the dummy sub-pixel.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Film” refers to a layer of film produced by deposition, coating or other processes of a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of B's orthographic projection.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations:
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate 10, patterning the semiconductor film through a patterning process, and forming a first insulating film covering the substrate 10.
  • the semiconductor layer of each sub-pixel may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7 and the first branch INIT-1 of the initial signal line, Moreover, the first active layer 11 to the seventh active layer 17 and the first branch INIT-1 of the initial signal line are connected to each other as an integral structure.
  • the first region R1 may include the first branch INIT-1 of the initial signal line, at least part of the first active layer 11 of the first transistor T1, and the second active layer 12 of the second transistor T2.
  • the fourth active layer 14 of the fourth transistor T4 and the seventh active layer 17 of the seventh transistor T7 may include at least part of the third active layer 13 of the third transistor T3, the third region R3 At least part of the fifth active layer 15 of the fifth transistor T5 and the sixth active layer 16 of the sixth transistor T6 may be included.
  • the first branch INIT-1 of the initial signal line, the first active layer 11 and the seventh active layer 17 are arranged on the side away from the second region R2 in the first region R1, and the second active layer 12 and the fourth active layer
  • the source layer 14 is disposed on a side of the first region R1 adjacent to the second region R2.
  • the first branch INIT-1 of the initial signal line is disposed on a side of the first active layer 11 of the first transistor T1 away from the second region R2,
  • the shape of the first active layer 11 may be "Z"
  • the shape of the second active layer 12 may be "7”
  • the shape of the third active layer 13 may be "several”.
  • the shape of the fourth active layer 14 may be "1”
  • the shape of the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first branch INIT-1 of the initial signal line is connected to the first region 11-1 of the first active layer 11 to form an integrated structure; the first branch INIT-1 of the initial signal line is also set There are protrusions on both sides of its extending direction, and the protrusions are also used as the first region 17-1 of the seventh active layer 17; the second region 11-2 of the first active layer 11 is also used as the second active layer 12, the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the second region 15-15 of the fifth active layer 15 2.
  • the second region 13 - 2 of the third active layer 13 serves as the second region 12 - 2 of the second active layer 12 and the first region 16 - 1 of the sixth active layer 16 at the same time.
  • the second region 16-2 of the sixth active layer 16, the second region 17-2 of the seventh active layer 17, the first region 14-1 of the fourth active layer 14, and the second The first regions 15-1 of the five active layers 15 are provided individually.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the aforementioned pattern is formed, and patterning the first metal film through a patterning process to form The second insulating layer 92 covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer 92, the first conductive layer pattern at least includes: scanning signal line Gate, reset signal line Reset, light emitting signal line EM and The first plate Ce1 of the storage capacitor is shown in Figure 8a, Figure 8b and 8c, Figure 8a is a schematic plan view of the first conductive layer of a normal pixel, and Figure 8b is a schematic plan view of a display substrate after the first conductive layer is formed for a normal pixel , FIG.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the scan signal line Gate, the reset signal line Reset, and the light emitting signal line EM extend along the first direction X.
  • the scanning signal line Gate and the reset signal line Reset are arranged in the first region R1, the reset signal line Reset is located on the side of the scanning signal line Gate away from the second region R2, the light emitting signal line EM is arranged in the third region R3, and the storage capacitor
  • the first electrode plate Ce1 is disposed in the second region R2 and is located between the scanning signal line Gate and the light emitting signal line EM.
  • the first plate Ce1 can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first plate Ce1 on the substrate 10 is consistent with the third active layer of the third transistor T3 The orthographic projections on the substrate 10 have overlapping regions.
  • the first plate Ce1 also serves as the gate electrode of the third transistor T3.
  • the reset signal line Reset is provided with a first bump 21-1 protruding toward the side of the scan signal line Gate, and the orthographic projection of the first bump 21-1 on the substrate 10 is the same as that of the first transistor T1
  • the orthographic projection of the first active layer of the first active layer on the substrate 10 has an overlapping area, and the area where the reset signal line Reset and the first bump 21-1 overlap with the first active layer of the first transistor T1 is used as the double layer of the first transistor T1.
  • the gate electrode of the gate structure, the area where the reset signal line Reset overlaps with the seventh active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7.
  • the area where the scanning signal line Gate overlaps with the fourth active layer of the fourth transistor T4 is used as the gate electrode of the fourth transistor T4.
  • the scanning signal line Gate is provided with a second bump 21-2 protruding toward the side of the reset signal line Reset, and the orthographic projection of the second bump 21-2 on the substrate 10 is aligned with the second active layer of the second transistor T2.
  • the area where the light emitting signal line EM overlaps with the fifth active layer of the fifth transistor T5 is used as the gate electrode of the fifth transistor T5, and the area where the light emitting signal line EM overlaps with the sixth active layer of the sixth transistor T6 is used as the sixth transistor T6.
  • Gate electrode of transistor T6 is used as the gate electrode of transistor T6.
  • the semiconductor layer may be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the area blocked by the first conductive layer forms the first transistors T1 to the seventh In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are all conductorized.
  • the display substrate includes a first insulating layer 91 disposed on the base 10, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a second insulating layer 92 disposed on the second insulating layer 92.
  • the first conductive layer, the semiconductor layer may include the first branch INIT-1 of the initial signal line, the first active layer 11 to the seventh active layer 17, the first conductive layer may include the scanning signal line Gate, the reset signal line Reset , the light emitting signal line EM and the first plate Ce1 of the storage capacitor.
  • forming the pattern of the second conductive layer may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the aforementioned pattern is formed, patterning the second metal film by a patterning process, and forming The third insulating layer 93 covering the first conductive layer, and the second conductive layer pattern arranged on the third insulating layer 93, the second conductive layer pattern at least includes: the second pole plate Ce2 of the storage capacitor, the shielding electrode 32 and the pole plate Plate connection line 31, as shown in Figure 9a and Figure 9b, Figure 9a is a schematic plan view of the second conductive layer of a normal pixel, Figure 9b is a schematic plan view of a display substrate after the second conductive layer is formed for a normal pixel, and Figure 9c is a schematic plan view of a display substrate in Figure 5b A schematic plan view of the display substrate after the second conductive layer is formed for the four pixels in the dotted line area.
  • the second plate Ce2 of the storage capacitor is disposed in the second region R2, between the scanning signal line Gate and the light emitting signal line EM.
  • the shielding electrode 32 is disposed in the first region R1, and the shielding electrode 32 is configured to shield the influence of the data voltage jump on key nodes, so as to prevent the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit and improve the display effect.
  • the outline of the second pole plate Ce2 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projections on have overlapping regions.
  • An opening H is disposed on the second pole plate Ce2, and the opening H may be located in the middle of the second region R2.
  • the opening H may be rectangular, so that the second pole plate Ce2 forms a ring structure.
  • the opening H exposes the third insulating layer covering the first plate Ce1 , and the orthographic projection of the first plate Ce1 on the base 10 includes the orthographic projection of the opening H on the base 10 .
  • the opening H is configured to accommodate the subsequently formed first via hole, the first via hole is located in the opening H and exposes the first electrode plate Ce1, so that the subsequently formed second connection electrode 44 is connected to the first via hole.
  • the plate Ce1 is connected.
  • the plate connection line 31 is arranged between the second plate Ce2 of the adjacent sub-pixel in the first direction X, and the first end of the plate connection line 31 is connected to the second plate Ce2 of the sub-pixel. connection, the second end of the electrode plate connection line 31 extends along the first direction X or the opposite direction of the first direction X, and is connected to the second electrode plate Ce2 of the adjacent sub-pixel, that is, the electrode plate connection line 31 is configured so that The second plates of adjacent sub-pixels in the first direction X are connected to each other.
  • the second plate in a sub-pixel row forms an integral structure connected to each other, and the second plate of the integral structure can be multiplexed as a power signal line to ensure a sub-pixel
  • the plurality of second pole plates in the pixel row have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • the orthographic projection of the edge of the second plate Ce2 adjacent to the first region R1 on the substrate 10 overlaps with the orthographic projection of the boundary line between the first region R1 and the second region R2 on the substrate 10, and the second The orthographic projection of the edge of the pole plate Ce2 adjacent to the third region R3 on the substrate 10 overlaps with the orthographic projection of the boundary line between the second region R2 and the third region R3 on the substrate 10, that is, the length of the second pole plate Ce2 is equal to the second The length of the region R2, the length of the second pole plate Ce2 refers to the dimension of the second pole plate Ce2 in the second direction Y.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a second insulating layer 92 disposed on the second insulating layer 92.
  • the first conductive layer on the first conductive layer, the third insulating layer 93 covering the first conductive layer and the second conductive layer disposed on the third insulating layer 93, the semiconductor layer may include the first active layer 11 to the seventh active layer 17
  • the first conductive layer may include the scanning signal line Gate, the reset signal line Reset, the light emitting signal line EM and the first plate Ce1 of the storage capacitor
  • the second conductive layer may include the second plate Ce2 of the storage capacitor, the shielding electrode 32 and Plate connecting wire 31.
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • the fourth insulating layer 94 is provided with a plurality of via holes on the fourth insulating layer 94, and the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, The fifth via hole V5, the sixth via hole V6, the seventh via hole V7, the eighth via hole V8 and the ninth via hole V9, as shown in Figure 10a, Figure 10b and Figure 10c, Figure 10a is the fourth via hole of a normal pixel 10b is a schematic plan view of the display substrate after forming the fourth insulating layer 94 for normal pixels, and FIG. 10c is a schematic plan view of the display substrate after the fourth insulating layer 94 is formed for the four pixels in the dotted line area in FIG. 5b.
  • the first via hole V1 is located in the opening H of the second plate Ce2, and the orthographic projection of the first via hole V1 on the substrate 10 is within the range of the orthographic projection of the opening H on the substrate 10,
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first plate Ce1.
  • the first via hole V1 is configured so that the subsequently formed second connection electrode 44 is connected to the first electrode plate Ce1 through the via hole.
  • the second via hole V2 is located in the area where the second pole plate Ce2 is located, and the orthographic projection of the second via hole V2 on the substrate 10 is within the range of the orthographic projection of the second pole plate Ce2 on the substrate 10 , the fourth insulating layer in the second via hole V2 is etched away, exposing the surface of the second plate Ce2.
  • the second via hole V2 is configured to connect the subsequently formed first power line to the second plate Ce2 through the via hole.
  • the second via hole V2 serving as the power supply via hole may include multiple, and the multiple second via holes V2 may be arranged in sequence along the second direction Y, and the first power line and the second plate Ce2 may be added. connection reliability.
  • the third via hole V3 is located in the third region R3, and the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the fifth active The surface of the first zone of the layer.
  • the third via hole V3 is configured to connect the subsequently formed first power line to the fifth active layer through the via hole.
  • the fourth via hole V4 is located in the third region R3, and the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the sixth active The surface of the second zone of the layer.
  • the fourth via hole V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole.
  • the fifth via hole V5 is located in the first region R1, and the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away, exposing the fourth active The surface of the first zone of the layer.
  • the fifth via hole V5 is configured to connect the subsequently formed data signal line to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.
  • the sixth via hole V6 is located in the first region R1, and the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the first active The surface of the second region of the layer (also the first region of the second active layer).
  • the sixth via hole V6 is configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through the via hole, and connect the first pole of the subsequently formed second transistor T2 to the first active layer through the via hole. Two active layer connections.
  • the seventh via hole V7 is located in the first region R1, and the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away, exposing the seventh active The surface of the second zone of the layer.
  • the seventh via hole V7 is configured to connect the subsequently formed fourth connection electrode 46 to the seventh active layer through the via hole.
  • the eighth via hole V8 is located in the first region R1 , and the fourth insulating layer inside the eighth via hole V8 is etched away, exposing the surface of the shielding electrode 32 .
  • the eighth via hole V8 is configured to connect the subsequently formed first power line to the shielding electrode 32 through the via hole.
  • the ninth via hole V9 is located in the first region R1, and the fourth insulating layer in the ninth via hole V9 is etched away, exposing the first region of the seventh active layer (that is, the initial signal The surface of line 31).
  • the ninth via hole V9 is configured to connect the subsequently formed third connection electrode 45 to the first region of the seventh active layer (ie, the initial signal line 31 ) through the via hole.
  • a thirteenth via hole V13 is also provided on the fourth insulating layer 94.
  • the thirteenth via hole V13 is located on the reset signal line Reset in the dummy pixel row.
  • the thirteenth via hole V13 is located on the reset signal line Reset in the dummy pixel row.
  • the fourth insulating layer and the third insulating layer in the hole V13 are etched away, exposing the surface of the reset signal line Reset in the dummy pixel row, and the thirteenth via hole V13 is configured to allow the subsequently formed first power line VDD to pass through
  • the via hole is connected to the reset signal line Reset in the dummy pixel row.
  • forming the third conductive layer may include: depositing a third metal thin film on the substrate on which the aforementioned pattern is formed, patterning the third metal thin film by a patterning process, and forming the fourth insulating layer 94
  • the third conductive layer on the top, the third conductive layer at least includes: the first power supply line VDD, the data signal line Data, the first connection electrode 43, the second connection electrode 44, the third connection electrode 45 and the fourth connection electrode 46, such as As shown in Figure 11a, Figure 11b and Figure 11c, Figure 11a is a schematic plan view of the third conductive layer of a normal pixel, Figure 11b is a schematic plan view of a display substrate after the third conductive layer is formed for a normal pixel, and Figure 11c is a dotted line area in Figure 5b A schematic plan view of the display substrate after the formation of the third conductive layer for four pixels.
  • the third conductive layer may be referred to as a first source
  • the first power line VDD extends along the second direction Y
  • the first power line VDD is connected to the second plate Ce2 through the second via hole V2 on the one hand, and is connected to the second plate Ce2 through the eighth via hole V8 on the other hand. It is connected to the shielding electrode 32 and connected to the fifth active layer through the third via hole V3, so that the shielding electrode 32 and the second plate Ce2 have the same potential as the first power line VDD. Since the orthographic projection of the shielding electrode 32 on the substrate 10 overlaps with the orthographic projection of the subsequently formed data signal line on the substrate 10, and the shielding electrode 32 is connected to the first power line VDD, it effectively shields the key to the data voltage jump. The impact of the node avoids the data voltage jump from affecting the potential of the key node of the pixel driving circuit, and improves the display effect.
  • the data signal line Data extends along the second direction Y, and the data signal line Data is connected to the first region of the fourth active layer through the fifth via hole V5, so that the data signal transmitted by the data signal line Data Write into the fourth transistor T4.
  • the first connection electrode 43 is connected to the second region of the sixth active layer through the fourth via hole V4. In an exemplary embodiment, the first connection electrode 43 may serve as a second electrode of the sixth transistor T6. In an exemplary embodiment, the first connection electrode 43 is configured to be connected to a subsequently formed anode connection electrode.
  • the second connection electrode 44 extends along the second direction Y, and its first end connects with the second region of the first active layer (which is also the first region of the second active layer) through the sixth via hole V6. area), the second end of which is connected to the first plate Ce1 through the first via hole V1, so that the first plate Ce1, the second pole of the first transistor T1 and the first pole of the second transistor T2 have the same potential .
  • the second connection electrode 44 may function as a second pole of the first transistor T1 and a first pole of the second transistor T2.
  • the third connection electrode 45 is connected to the first region of the seventh active layer through the ninth via hole V9, since the first region of the seventh active layer, the first region of the first active layer
  • the initial signal line 31 is an integral structure connected to each other, and the third connection electrode 45 is connected to the initial signal line 31, so that the first pole of the seventh transistor T7 and the first pole of the first transistor T1 have the same polarity as the initial signal line 31. potential.
  • the third connection electrode 45 may serve as the first pole of the seventh transistor T7 and the first pole of the first transistor T1.
  • the fourth connection electrode 46 is connected to the second region of the seventh active layer through the seventh via hole V7. In an exemplary embodiment, the fourth connection electrode 46 may serve as a second electrode of the seventh transistor T7. In an exemplary embodiment, the fourth connection electrode 46 is configured to be connected to a subsequently formed anode connection electrode.
  • the first power line VDD includes a third bump in the dummy pixel row, the third bump may be of irregular shape, and the third bump may be respectively connected to the virtual storage capacitor through the via hole on the insulating layer.
  • the first plate, the virtual reset signal line, and the second pole of the virtual reset transistor (the second pole of the virtual first transistor and the second pole of the virtual seventh transistor) are connected.
  • the data signal line Data may be a straight line of equal width, or a straight line of unequal width.
  • Forming the first flat layer 95 pattern may include: coating the first planar film on the substrate on which the aforementioned pattern is formed, and patterning the first planar film by a patterning process to form a layer covering the third conductive layer 95.
  • the first planar layer 95 of the layer, the tenth via hole V10, the eleventh via hole V11 and the twelfth via hole V12 are arranged on the first planar layer 95, as shown in Fig. 12a, Fig. 12b and Fig. 12c, Fig. 12a
  • FIG. 12b is a schematic plan view of a display substrate after the first flat layer 95 is formed for a normal pixel.
  • the tenth via hole V10 is located in the area where the fourth connecting electrode 46 is located, the eleventh via hole V11 is located in the area where the first connecting electrode 43 is located, and the first flat layer in the tenth via hole V10 and the eleventh via hole V11 are respectively removed , exposing the surface of the fourth connection electrode 46 and the first connection electrode 43, the tenth via hole V10 and the eleventh via hole V11 are configured so that the subsequently formed anode connection electrode 52 passes through the two via holes and the sixth transistor T6
  • the second pole of the seventh transistor T7 is connected to the second pole.
  • the twelfth via hole V12 is located in the area where the third connection electrode 45 is located.
  • the first planar layer in the twelfth via hole V12 is removed to expose the surface of the third connection electrode 45.
  • the twelfth via hole V12 is configured so that the subsequent The formed second branch and third branch of the initial signal line are connected to the third connection electrode 45 through the via hole.
  • Forming the fourth conductive layer may include: depositing a fourth metal thin film on the substrate on which the aforementioned pattern is formed, patterning the fourth metal thin film by a patterning process, and forming a fourth conductive layer disposed on the first planar layer 95,
  • the fourth conductive layer at least includes: the second branch INIT-2 of the first initial signal line, the third branch INIT-3 of the first initial signal line, the fifth connection electrode 51 and the anode connection electrode 52, as shown in Figure 13 and Figure 6b , as shown in FIG. 6c and FIG. 6e,
  • FIG. 13 is a schematic plan view of the fourth conductive layer of a normal pixel, FIG.
  • FIG. 6b is a schematic plan view of a display substrate after the fourth conductive layer is formed for a normal pixel
  • FIG. 6c is a cross-sectional view of the AA region in FIG. 6b
  • FIG. 6e is a schematic plan view of the display substrate after the fourth conductive layer is formed for the four pixels in the dotted line area in FIG. 5b.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the second branch INIT-2 of the first initial signal line extends along the second direction Y
  • the third branch INIT-3 of the first initial signal line extends along the first direction X
  • the fifth connection The electrode 51 is arranged in the area where the second branch INIT-2 of the first initial signal line overlaps with the third branch INIT-3 of the first initial signal line
  • the fifth connection electrode 51, the second branch of the first initial signal line INIT-2 and the third branch INIT-3 of the first initial signal line are an integral structure connected to each other.
  • the three branches INIT-3 and the first branch INIT-1 of the first initial signal line form a double-layer wiring
  • the fifth connection electrode 51 is connected to the third connection electrode 45 through the twelfth via hole V12.
  • the second branch INIT-2 of the first initial signal line is provided with a plurality of bent portions INIT-21, and the orthographic projection of the bent portions INIT-21 on the substrate 10 is aligned with the second connection electrode 44.
  • the orthographic projections on the substrate 10 have overlapping areas, which are configured to shield the impact of data voltage jumps on key nodes, avoid data voltage jumps from affecting the potential of key nodes of the pixel driving circuit, and improve display effects.
  • the anode connection electrode 52 is connected to the fourth connection electrode 46 and the first connection electrode 43 through the tenth via hole V10 and the eleventh via hole V11, respectively.
  • forming the second planar layer pattern may include: coating a second planar film on the substrate on which the foregoing pattern is formed, and patterning the second planar film by a patterning process to form a layer covering the fourth conductive layer.
  • the second planar layer (not shown in the figure) of the second planar layer is provided with at least an anode via hole (ie, the fourteenth via hole V14 in FIG. 6e ).
  • the fourteenth via hole is located in the area where the anode connection electrode 52 is located, the second planar layer in the fourteenth via hole is removed, exposing the surface of the anode connection electrode 52, and the fourteenth via hole configuration In order to make the subsequently formed anode electrically connect to the anode connection electrode 52 through the via hole.
  • the driving circuit layer pattern is prepared on the substrate 10 .
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a scanning signal line, a reset signal line, a light emitting signal line, a data signal line connected to the pixel driving circuit. line, first power line, initial signal line, etc.
  • the driving circuit layer may include a first insulating layer 91, a semiconductor layer, a second insulating layer 92, a first conductive layer, a third insulating layer 93, a second A conductive layer, a fourth insulating layer 94, a third conductive layer, a first planar layer 95, a fourth conductive layer and a second planar layer.
  • a light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer may include the following operations:
  • a transparent conductive film is deposited on the substrate on which the foregoing pattern is formed, and the transparent conductive film is patterned by a patterning process to form an anode layer disposed on the second flat layer.
  • the pixel definition film is coated, and the pixel definition film is patterned by a patterning process to form a pixel definition layer (PDL).
  • PDL pixel definition layer
  • the pixel definition layer of each sub-pixel is provided with a sub-pixel opening, and the sub-pixel opening exposes the anode.
  • An organic light-emitting layer is formed by vapor deposition or an ink-jet printing process, and a cathode is formed on the organic light-emitting layer.
  • the anode, the pixel definition layer, the organic light emitting layer and the cathode form a light emitting structure layer pattern.
  • an encapsulation layer is prepared on the light-emitting structure layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the The third encapsulation layer can be made of inorganic materials
  • the second encapsulation layer can be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that outside water vapor cannot enter the light-emitting structure layer.
  • the preparation process of the display substrate may include processes such as peeling off the glass carrier, attaching a back film, cutting, etc., and the disclosure is not limited here.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second
  • the material of flexible material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the first inorganic material layer and the second inorganic material layer
  • the material can be silicon nitride (SiNx) or silicon oxide (SiOx), etc. to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum ( Any one or more of Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/ Mo et al.
  • the anode layer can use transparent conductive materials such as indium tin oxide ITO or indium zinc oxide IZO.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), Can be single layer, multilayer or composite layer.
  • the first insulating layer is called the buffer (BUF) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer is called the first gate insulating (GI1) layer
  • the third insulating layer is called the second gate insulating (GI2) layer
  • the fourth insulating layer is called an interlayer insulating (ILD) layer.
  • Organic materials may be used for the first planar (PLN1) layer and the second planar (PLN2) layer.
  • the semiconductor layer may use polysilicon (p-Si) or oxide.
  • the display substrate in the embodiment of the present disclosure makes the reset transistors in each row of sub-pixels controlled by the reset signal lines in the row of sub-pixels, that is, adopts the reset method at the same level, so that the GOA of each row of sub-pixels drives a row of scanning signal lines and a row of scanning signal lines.
  • the signal line is reset, so that the charging time of different regions is the same, thereby improving the display effect of the display panel.
  • the structure of the display substrate and its preparation process shown in the present disclosure are only exemplary illustrations. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs, which is not limited in the present disclosure.
  • an embodiment of the present disclosure also provides a display substrate, including a plurality of sub-pixels and a virtual pixel row H between the plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and A light emitting device, the pixel driving circuit includes an initial signal line INIT, a reset signal line Reset, a scanning signal line Gate, a light emitting signal line EM and a plurality of transistors;
  • the multiple transistors include a drive transistor (ie, the third transistor T3 in FIG. 3 ), a first reset transistor (ie, the first transistor T1 in FIG. 3 ), and a second reset transistor (ie, the seventh transistor T7 in FIG. 3 ),
  • the drive transistor is configured to provide a drive current for the light emitting device
  • the first reset transistor is configured to reset the gate of the drive transistor through the initial signal line INIT under the control of the reset signal line Reset
  • the second reset transistor is configured to Under the control of the scanning signal line Gate, the anode of the light emitting device is reset through the initial signal line INIT;
  • the display substrate includes a plurality of gate connection electrodes 53 straddling the dummy pixel row H, and the gate connection electrodes 53 are configured to connect the gates of the first reset transistors on one side of the dummy pixel row H. electrode and the gate electrode of the second reset transistor located on the other side of the dummy pixel row H.
  • the gate connection electrode 53 is located on a different conductive layer from the gate electrodes of the plurality of transistors.
  • the display substrate in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base, and an insulating layer disposed between the semiconductor layer and the first conductive layer or between the respective conductive layers;
  • the semiconductor layer includes active layers of multiple transistors, the first conductive layer includes gate electrodes of multiple transistors, the scanning signal line Gate, the reset signal line Reset and the first plate of the storage capacitor, and the second conductive layer includes the first plate of the storage capacitor. Diode plate, the third conductive layer includes the first power supply line VDD and the data signal line Data, and the fourth conductive layer includes the anode connection electrode;
  • the gate connection electrode 53 may be located on any one or more layers of the third conductive layer, the fourth conductive layer and the anode layer, which is not limited in the present disclosure.
  • the gate electrode of the second reset transistor in the upper row of sub-pixels of the dummy pixel row is connected to the gate electrode of the first reset transistor in the next row of sub-pixels of the dummy pixel row through the gate connection electrode, so that The second reset transistor in the upper row of sub-pixels of the virtual pixel row and the first reset transistor in the next row of sub-pixels of the virtual pixel row share a reset signal line, so that the GOA of each row of sub-pixels drives a row of scanning signals and a row of reset signal, that is, to drive two lines of signals at the same time, which improves the display effect.
  • the present disclosure also provides a method for preparing a display substrate to prepare the display substrate provided in the above embodiments, the display substrate includes a plurality of sub-pixels, and at least one of the sub-pixels is divided into: a first region, a second region and a second region Three areas, the first area and the third area are respectively located on both sides of the second area.
  • the method for preparing the display substrate may include the following steps:
  • a semiconductor layer is formed on the substrate, the semiconductor layer includes an initial signal line and an active layer of a plurality of transistors, the plurality of transistors include a drive transistor, a reset transistor and a light emission control transistor, and the drive transistor is located in the second region , the initial signal line connected to the sub-pixel and the reset transistor are located in the first area, and the light emission control transistor is located in the third area;
  • a first conductive layer is formed on the semiconductor layer, the first conductive layer includes gate electrodes of a plurality of transistors, a reset signal line and a light emitting signal line, and the reset signal line connected to the sub-pixels is located in the first region, The light-emitting signal line connected to the sub-pixel is located in the third region, the driving transistor is configured to provide a driving current for the light-emitting device, and the reset transistor is configured to pass through under the control of the reset signal line
  • the initial signal line resets the gate of the driving transistor and/or the anode of the light emitting device, and the light emission control transistor is configured to allow or prohibit the driving current under the control of the light emitting signal line pass.
  • the present disclosure also provides a method for driving a display substrate.
  • the display substrate includes a plurality of sub-pixels, and at least one of the sub-pixels includes a pixel driving circuit and a light emitting device.
  • the pixel driving circuit includes: a driving sub-pixel Circuit 101, first reset subcircuit 102, second reset subcircuit 103, data writing subcircuit 104, compensation subcircuit 105 and light emission control subcircuit 106; the driving method includes:
  • the first reset subcircuit 102 resets the control terminal of the drive subcircuit 101 under the control of the reset signal;
  • the second reset subcircuit 103 resets the control terminal of the drive subcircuit 101 under the control of the reset signal. reset the first end of the light emitting device;
  • the data writing sub-circuit 104 writes the data signal into the driving sub-circuit 101 under the control of the scanning signal, and the compensation sub-circuit 105 compensates the driving sub-circuit 101 ;
  • the light-emitting control subcircuit 106 applies the driving current generated by the driving sub-circuit 101 to the light-emitting device to make it emit light under the control of the light-emitting signal;
  • the first reset sub-circuit 102 and the second reset sub-circuit 103 in the same sub-pixel are controlled through the same reset signal line.
  • the driving subcircuit 101 includes a third transistor T3, wherein the gate electrode of the third transistor T3 is connected to the first node N1 (ie, the first end of the storage capacitor C) connected, the first pole of the third transistor T3 is connected to the second node N2 (that is, the second pole of the fourth transistor T4), the second pole of the third transistor T3 is connected to the third node N3 (that is, the first pole of the second transistor T2 pole) connection.
  • the gate electrode of the third transistor T3 is connected to the first node N1 (ie, the first end of the storage capacitor C) connected
  • the first pole of the third transistor T3 is connected to the second node N2 (that is, the second pole of the fourth transistor T4)
  • the second pole of the third transistor T3 is connected to the third node N3 (that is, the first pole of the second transistor T2 pole) connection.
  • the first reset subcircuit 102 includes a first transistor T1, wherein the gate electrode of the first transistor T1 is connected to the reset signal line Reset, and the second transistor T1 of the first transistor T1 One pole is connected to the initial signal line INIT, and the second pole of the first transistor T1 is connected to the first node N1.
  • the second reset subcircuit 103 includes a seventh transistor T7, wherein the gate electrode of the seventh transistor T7 is connected to the reset signal line Reset, and the gate electrode of the seventh transistor T7 One pole is connected to the initial signal line INIT, and the second pole of the seventh transistor T7 is connected to the fourth node N4 (ie, the first terminal of the light emitting device).
  • the data writing sub-circuit 104 includes a fourth transistor T4, wherein the gate electrode of the fourth transistor T4 is connected to the scanning signal line Gate, and the fourth transistor T4 One pole is connected to the data signal line Data, and the second pole of the fourth transistor T4 is connected to the second node N2.
  • the compensation subcircuit 105 includes a second transistor T2 and a storage capacitor C, wherein the gate electrode of the second transistor T2 is connected to the scanning signal line Gate, and the second transistor T2
  • the first pole of the second transistor T2 is connected to the third node N3, the second pole of the second transistor T2 is connected to the first node N1; the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the first power line VDD.
  • a node N1 is connected.
  • the light emission control subcircuit 106 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, and the fifth transistor T5
  • the first pole of the transistor T5 is connected to the first power supply line VDD
  • the second pole of the fifth transistor T5 is connected to the second node N2
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM
  • the first pole of the sixth transistor T6 A pole of the sixth transistor T6 is connected to the third node N3, and a second pole of the sixth transistor T6 is connected to the fourth node N4.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiment of the present invention is not limited thereto.

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Abstract

一种显示基板及其驱动方法、显示装置，显示基板包括多个子像素，子像素包括像素驱动电路和发光器件，像素驱动电路包括初始信号线(INIT)、复位信号线(Reset)和多个晶体管，初始信号线(INIT)包括第一分支(INIT-1)；多个晶体管包括驱动晶体管、第一复位晶体管和第二复位晶体管，驱动晶体管为发光器件提供驱动电流，第一复位晶体管在复位信号线(Reset)的控制下，通过初始信号线的第一分支(INIT-1)对驱动晶体管的栅极进行复位；第二复位晶体管在复位信号线(Reset)的控制下，通过初始信号线的第一分支(INIT-1)对发光器件的第一端进行复位；同一子像素内的第一复位晶体管和第二复位晶体管通过同一根复位信号线(Reset)进行控制。

Description

显示基板及其驱动方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括多个子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述像素驱动电路包括初始信号线、复位信号线和多个晶体管，所述初始信号线包括第一分支；所述多个晶体管包括驱动晶体管、第一复位晶体管和第二复位晶体管，所述驱动晶体管被配置为为所述发光器件提供驱动电流，所述第一复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线的第一分支对所述驱动晶体管的栅极进行复位；所述第二复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线的第一分支对所述发光器件的第一端进行复位；同一子像素内的所述第一复位晶体管和所述第二复位晶体管通过同一根复位信号线进行控制。
在一些示例性实施方式中，所述初始信号线的第一分支沿第一方向延伸， 所述初始信号线的第一分支与所述多个晶体管的有源层同层设置。
在一些示例性实施方式中，所述像素驱动电路还包括存储电容；
在所述同一子像素内，所述第一复位晶体管和所述第二复位晶体管均位于所述初始信号线的第一分支与所述存储电容之间。
在一些示例性实施方式中，在所述同一子像素内，所述第一复位晶体管位于所述第二复位晶体管沿所述第一方向的一侧。
在一些示例性实施方式中，所述像素驱动电路还包括第一发光控制晶体管、第二发光控制晶体管和阳极连接电极，所述阳极连接电极通过阳极过孔与所述第一发光控制晶体管的第二极连接，其中：
所述第一发光控制晶体管、所述阳极过孔以及所述第二发光控制晶体管沿所述第一方向排列，且所述阳极过孔位于所述第一发光控制晶体管与所述第二发光控制晶体管之间。
在一些示例性实施方式中，所述多个晶体管的有源层包括沟道区、位于所述沟道区一侧用于与源电极对应的第一区、以及位于所述沟道区另一侧用于与漏电极对应的第二区，所述第一复位晶体管的有源层的第一区、所述第二复位晶体管的有源层的第一区以及所述初始信号线的第一分支相互连接成一体结构。
在一些示例性实施方式中，所述第一复位晶体管的有源层为“L”形，所述复位信号线在每个子像素内设置有第一凸块，所述复位信号线和所述第一凸块与所述第一复位晶体管的沟道区相重叠的区域作为所述第一复位晶体管的双栅结构的栅电极。
在一些示例性实施方式中，在垂直于所述显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，以及设置在所述半导体层和第一导电层之间或者各个导电层之间的绝缘层；
所述半导体层包括多个晶体管的有源层和所述初始信号线的第一分支，所述第一导电层包括多个晶体管的栅电极、复位信号线和存储电容的第一极板，所述第二导电层包括所述存储电容的第二极板，所述第三导电层包括第 二连接电极，所述第四导电层包括初始信号线的第二分支；
所述第二连接电极被配置为通过绝缘层上的过孔，连接所述驱动晶体管的栅电极与所述第一复位晶体管的第二区，所述初始信号线的第二分支通过绝缘层上的过孔连接所述初始信号线的第一分支；
所述初始信号线的第二分支在基底上的正投影，与所述第二连接电极在基底上的正投影至少部分重叠。
在一些示例性实施方式中，所述初始信号线的第二分支包括主体部和弯折部，所述主体部沿第二方向延伸，所述弯折部包括两个第一延伸部以及设置在所述两个第一延伸部之间的第二延伸部，所述第一延伸部沿第一方向延伸，所述第二延伸部沿所述第二方向延伸，所述第一方向与所述第二方向交叉，所述第二延伸部沿所述第一方向的宽度大于所述主体部沿所述第一方向的宽度。
在一些示例性实施方式中，所述第三导电层还包括第一电源线、第一连接电极和第四连接电极，所述第四导电层还包括阳极连接电极，所述发光控制晶体管包括第一发光控制晶体管；
所述阳极连接电极通过绝缘层上的过孔连接所述第一连接电极和所述第四连接电极，所述第一连接电极通过绝缘层上的过孔连接所述第一发光控制晶体管的第二区，所述第四连接电极通过绝缘层上的过孔连接所述第二复位晶体管的第二区；
所述阳极连接电极在基底上的正投影，与所述第一电源线在基底上的正投影至少部分重叠。
在一些示例性实施方式中，所述阳极连接电极在基底上的正投影，与所述第一复位晶体管的第二极在基底上的正投影至少部分重叠。
在一些示例性实施方式中，所述第四导电层还包括第五连接电极和所述初始信号线的第三分支；
所述初始信号线的第三分支沿第一方向延伸，所述初始信号线的第二分支沿第二方向延伸，所述第一方向与所述第二方向交叉；
所述第五连接电极、所述初始信号线的第二分支与所述初始信号线的第 三分支相互连接成一体结构，所述初始信号线的第三分支在基底上的正投影，与所述初始信号线的第一分支在基底上的正投影至少部分重叠。
在一些示例性实施方式中，所述显示基板还包括位于所述多个子像素之间的虚拟像素行，所述虚拟像素行包括多个虚拟子像素，所述虚拟子像素包括虚拟像素驱动电路，所述虚拟像素驱动电路包括虚拟复位晶体管、虚拟数据写入晶体管，所述虚拟复位晶体管的沟道区以及所述虚拟数据写入晶体管的沟道区均为断裂结构。
在一些示例性实施方式中，所述虚拟像素驱动电路包括虚拟存储电容、虚拟初始信号线、虚拟复位信号线、虚拟发光信号线和虚拟扫描信号线，所述虚拟发光信号线、虚拟存储电容的第一极板与虚拟扫描信号线相互连接成一体结构，所述虚拟存储电容的第一极板和第二极板以及所述虚拟复位信号线分别通过绝缘层上的过孔与所述第一电源线连接。
本公开实施例还提供了一种显示基板，包括多个子像素以及位于所述多个子像素之间的虚拟像素行，至少一个所述子像素包括像素驱动电路和发光器件，所述像素驱动电路包括初始信号线、复位信号线、扫描信号线、发光信号线和多个晶体管；
所述多个晶体管包括驱动晶体管、第一复位晶体管和第二复位晶体管，所述驱动晶体管被配置为为所述发光器件提供驱动电流，所述第一复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线对所述驱动晶体管的栅极进行复位，所述第二复位晶体管被配置为在所述扫描信号线的控制下，通过所述初始信号线对所述发光器件的阳极进行复位；
所述显示基板包括多个栅极连接电极，多个所述栅极连接电极跨设在所述虚拟像素行上，所述栅极连接电极被配置为连接位于所述虚拟像素行一侧的第一复位晶体管的栅电极以及位于所述虚拟像素行另一侧的第二复位晶体管的栅电极。
在一些示例性实施方式中，所述栅极连接电极与所述多个晶体管的栅电极位于不同的导电层上。
本公开实施例还提供了一种显示装置，包括如前任一项所述的显示基板。
本公开实施例还提供了一种显示基板的驱动方法，所述显示基板包括多个子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述像素驱动电路包括驱动子电路、第一复位子电路、第二复位子电路、数据写入子电路、补偿子电路和发光控制子电路，所述驱动方法包括：
在初始化阶段，所述第一复位子电路在复位信号的控制下，对所述驱动子电路的控制端进行复位；所述第二复位子电路在所述复位信号的控制下，对所述发光器件的第一端进行复位；同一子像素内的所述第一复位子电路和第二复位子电路通过同一根复位信号线进行控制；
在数据写入及补偿阶段，所述数据写入子电路在扫描信号的控制下，将数据信号写入所述驱动子电路，所述补偿子电路对所述驱动子电路进行补偿；
在发光阶段，所述发光控制子电路在发光信号的控制下，将所述驱动子电路产生的驱动电流施加至所述发光器件以使其发光。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开实施例一种显示装置的结构示意图；
图2a和图2b为本公开实施例两种子像素的排列结构示意图；
图3为本公开实施例一种像素电路的等效电路图；
图4为图3所示像素电路的驱动时序示意图；
图5a为本公开实施例一种显示基板的平面结构示意图；
图5b为图5a中B区域的像素排列结构示意图；
图5c为一种显示区域的阵列栅极驱动(Gate driver On Array，GOA)负 载示意图；
图6a为本公开实施例一种显示区域的GOA负载示意图；
图6b为本公开实施例一种正常像素形成第四导电层后的显示基板平面示意图；
图6c为图6b中A-A向的剖视图；
图6d为本公开实施例另一种像素电路的等效电路图；
图6e为图5b中虚线区域的四个像素形成第四导电层后的显示基板平面示意图；
图7a为正常像素的半导体层的平面示意图；
图7b为图5b中虚线区域的四个像素形成半导体层后的显示基板平面示意图；
图8a为正常像素的第一导电层的平面示意图；
图8b为正常像素形成第一导电层后的显示基板平面示意图；
图8c为图5b中虚线区域的四个像素形成第一导电层后的显示基板平面示意图；
图9a为正常像素的第二导电层的平面示意图；
图9b为正常像素形成第二导电层后的显示基板平面示意图；
图9c为图5b中虚线区域的四个像素形成第二导电层后的显示基板平面示意图；
图10a为正常像素的第四绝缘层94的平面示意图；
图10b为正常像素形成第四绝缘层94后的显示基板平面示意图；
图10c为图5b中虚线区域的四个像素形成第四绝缘层94后的显示基板平面示意图；
图11a为正常像素的第三导电层的平面示意图；
图11b为正常像素形成第三导电层后的显示基板平面示意图；
图11c为图5b中虚线区域的四个像素形成第三导电层后的显示基板平面示意图；
图12a为正常像素的第一平坦层的平面示意图；
图12b为正常像素形成第一平坦层后的显示基板平面示意图；
图12c为图5b中虚线区域的四个像素形成第一平坦层后的显示基板平面示意图；
图13为正常像素的第四导电层的平面示意图；
图14为本公开实施例另一种显示区域的GOA负载示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述 各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的 数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在一些示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij，每个子像素Pxij可以连接到对应的数据信号线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图2a和图2b为一种显示基板的平面结构示意图。在示例性实施方式中， 显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和二个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和发光信号线和像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一种示例性实施方式中，四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布，如图2a所示。在另一种示例性实施方式中，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布，如图2b所示。在其它示例性实施方式中，四个子像素可以采用水平并列或竖直并列等方式排列。在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
在一些示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图3为本公开示例性实施例一种像素驱动电路的等效电路示意图。如图3所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和多个信号线(数据信号线D、扫描信号线Gate、复位信号线Reset、初始信号线INIT、第一电源线VDD、第二电源线VSS和发光信号线EM)。
在一些示例性实施方式中，第一晶体管T1的栅电极与复位信号线Reset连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管T1的第二极与第一节点N1连接。第二晶体管T2的栅电极与扫描信号线Gate连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接。第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的栅电极与扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4(即发光器件的第一极)连接。第七晶体管T7的栅电极与扫描信号线Gate连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与第四节点N4连接。存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第一节点N1连接。
在一些示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供低电平信号，第一电源线VDD的信号为持续提供高电平信号。扫描信号线Gate为本显示行像素驱动电路中的扫描信号线，复位信号线Reset为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，扫描信号线Gate为Gate(n)，复位信号线Reset为Gate(n-1)，本显示行的复位信号线Reset与上一显示行像素驱动电路中的扫描信号线Gate可以为同一信号线，以减少显示面板的信号线，实现显示面板的窄边框。
在一些示例性实施方式中，扫描信号线Gate、复位信号线Reset、发光 信号线E和初始信号线INIT均沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线D沿竖直方向延伸。
在一些示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图4为图3所示的像素驱动电路的一种工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图3中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C1和7个信号线(数据信号线D、扫描信号线Gate、复位信号线Reset、初始信号线INIT、第一电源线VDD、第二电源线VSS和发光信号线EM)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位信号线Reset的信号为低电平信号，扫描信号线Gate和发光信号线EM的信号为高电平信号。复位信号线Reset的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第一节点N1，对存储电容C进行初始化，清除存储电容中原有数据电压。扫描信号线Gate和发光信号线EM的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为低电平信号，复位信号线Reset和发光信号线EM的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。扫描信号线Gate的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之和充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vdata+Vth，Vdata为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七 晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。复位信号线Reset的信号为高电平信号，使第一晶体管T1断开。发光信号线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线EM的信号为低电平信号，扫描信号线Gate和复位信号线Reset的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata+Vth，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdata+Vth-Vdd)-Vth] 2＝K*[(Vdata–Vdd)] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述公式可以看出，流经发光器件的电流I与第三晶体管T3的阈值电压Vth无关，消除了第三晶体管T3的阈值电压Vth对电流I的影响，保证了亮度的均一性。
基于上述工作时序，该像素电路消除了发光器件在上次发光后残余的正电荷，实现了对第三晶体管栅极电压的补偿，避免了第三晶体管的阈值电压漂移对发光器件驱动电流的影响，提高了显示图像的均匀性和显示面板的显示品质。
近年来，随着显示行业的迅猛发展，消费者对于显示边框的要求越来越严格，窄边框甚至零边框逐渐成为了潮流和趋势，将扇出(Fanout)走线压缩到有效显示(Active Area，AA)区内也已经不再是概念，而是成为了现实。 有一种将扇出走线放入有效显示区内的方法是将有效显示区的像素通过纵向压缩，如图5a和图5b所示，在位于有效显示区靠近边框区域一侧的GOP(Gate On Panel)区采用密排的压缩后的像素，而在有效显示区内的非GOP区采用压缩后的像素插入虚拟(Dummy)像素的方式排列，在图5b中，P表示正常子像素，H表示插入的虚拟像素行，V表示插入的虚拟像素列。
但是，随之而来的问题是，有效显示区内没有插虚拟像素行的区域和插虚拟像素行的区域的阵列栅极驱动(Gate driver On Array，GOA)信号的负载(Loading)会有差别，如图5c所示，如果我们继续采用本行的扫描信号线Gate驱动本行第七晶体管T7的话，在没有插虚拟像素行的区域，一行GOA驱动一行扫描信号线Gate和一行复位信号线Reset，但是在插虚拟像素行的区域，一行GOA驱动一行扫描信号线Gate和两行复位信号线Reset，这就说明插虚拟像素行的区域的GOA比没有插虚拟像素行的区域的GOA的负载增加一行，这对于显示是非常不利的。这是因为，插虚拟像素行的区域的GOA负载较大，会导致其充电时间和没有插虚拟像素行的区域的充电时间有差别，从而使得显示面板的显示效果较差。
本公开实施例提供了一种显示基板，包括多个子像素，至少一个子像素包括像素驱动电路和发光器件，像素驱动电路包括初始信号线、复位信号线、发光信号线和多个晶体管，初始信号线包括第一分支；
多个晶体管包括驱动晶体管、第一复位晶体管和第二复位晶体管，驱动晶体管被配置为为发光器件提供驱动电流，第一复位晶体管被配置为在复位信号线的控制下，通过初始信号线的第一分支对驱动晶体管的栅极进行复位；第二复位晶体管被配置为在复位信号线的控制下，通过初始信号线的第一分支对发光器件的阳极进行复位；
同一子像素内的第一复位晶体管和第二复位晶体管通过同一根复位信号线进行控制。
如图6a所示，本公开实施例的显示基板，通过使每行子像素中的第一复位晶体管和第二复位晶体管均由本行子像素中的同一复位信号线控制，即采用同级复位方式，使得每一行子像素的GOA驱动一行扫描信号线和一行复位信号线，进而使得不同区域的充电时间相同，从而提高了显示面板的显示 效果。
如图6b和图6c所示，显示基板包括多个子像素，至少一个子像素包括像素驱动电路和发光器件，像素驱动电路包括初始信号线INIT、复位信号线Reset、发光信号线EM和多个晶体管；
多个晶体管包括驱动晶体管(即图6b中的第三晶体管T3)、第一复位晶体管(即图6b中的第一晶体管T1)和第二复位晶体管(即图6b中的第七晶体管T7)，驱动晶体管被配置为为发光器件提供驱动电流，第一复位晶体管被配置为在复位信号线Reset的控制下，通过初始信号线的第一分支INIT-1对驱动晶体管的栅极进行复位，第二复位晶体管被配置为在复位信号线Reset的控制下，通过初始信号线的第一分支INIT-1对发光器件的第一端进行复位；
同一子像素内的第一复位晶体管和第二复位晶体管通过同一根复位信号线Reset进行控制。
在一些示例性实施方式中，多个晶体管还包括发光控制晶体管，发光控制晶体管被配置为在发光信号线的控制下，允许或禁止驱动电流通过。
在一些示例性实施方式中，结合图6b和图6e所示，像素驱动电路还包括第一发光控制晶体管(即图6b中的第五晶体管T5)、第二发光控制晶体管(即图6b中的第六晶体管T6)和阳极连接电极52，阳极连接电极52通过阳极过孔V14与第一发光控制晶体管的第二极连接，其中：
第一发光控制晶体管、阳极过孔V14以及第二发光控制晶体管沿第一方向X排列，且阳极过孔V14位于第一发光控制晶体管与第二发光控制晶体管之间。
在一些示例性实施方式中，至少一个子像素沿第二方向Y被划分为：第一区域R1、第二区域R2和第三区域R3，第一区域R1和第三区域R3分别位于第二区域R2的两侧，驱动晶体管位于第二区域R2，子像素连接的初始信号线INIT(此处的初始信号线INIT包括初始信号线的第一分支INIT-1和/或初始信号线的第三分支INIT-3，初始信号线的第二分支INIT-2跨越第一区域R1、第二区域R2和第三区域R3)与复位晶体管位于第一区域R1，子像素连接的发光信号线EM与发光控制晶体管位于第三区域R3。
在一些示例性实施方式中，初始信号线包括第一分支INIT-1，初始信号线的第一分支INIT-1沿第一方向X延伸，初始信号线的第一分支INIT-1与多个晶体管的有源层同层设置。
本实施例中，通过将初始信号线的第一分支INIT-1与多个晶体管的有源层同层设置，初始信号直接从每个子像素的顶端通过半导体层往下，通过最短的路径对第一节点N1进行初始化，有效利用了像素的布局(Layout)空间。
在一些示例性实施方式中，像素驱动电路还包括存储电容C，在同一子像素内，第一复位晶体管和第二复位晶体管均位于初始信号线的第一分支INIT-1与存储电容C之间。
在一些示例性实施方式中，如图6d所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C。
其中，第一晶体管T1的栅电极与复位信号线Reset连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管T1的第二极与第一节点N1连接。第二晶体管T2的栅电极与扫描信号线Gate连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接。第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的栅电极与扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4(即发光器件的第一极)连接。第七晶体管T7的栅电极与复位信号线Reset连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与第四节点N4连接。存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第一节点N1连接。
在一些示例性实施方式中，多个晶体管的有源层包括沟道区、位于沟道 区一侧用于与源电极对应的第一区、以及位于沟道区另一侧用于与漏电极对应的第二区，第一复位晶体管的有源层的第一区、第二复位晶体管的有源层的第一区以及初始信号线的第一分支INIT-1相互连接成一体结构。
在一些示例性实施方式中，第一复位晶体管的有源层为“L”形，复位信号线Reset在每个子像素内设置有第一凸块21-1，复位信号线Reset和第一凸块21-1与第一复位晶体管的沟道区相重叠的区域作为第一复位晶体管的双栅结构的栅电极。
在一些示例性实施方式中，在垂直于显示基板的平面内，该显示基板包括在基底10上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，以及设置在半导体层和第一导电层之间或者各个导电层之间的绝缘层；
半导体层包括多个晶体管的有源层和初始信号线的第一分支INIT-1，第一导电层包括多个晶体管的栅电极、复位信号线Reset和存储电容的第一极板Ce1，第二导电层包括存储电容的第二极板Ce2，第三导电层包括第二连接电极44，第四导电层包括初始信号线的第二分支INIT-2；
第二连接电极44被配置为通过绝缘层上的过孔，连接驱动晶体管的栅电极与第一复位晶体管的第二区，初始信号线的第二分支INIT-2通过绝缘层上的过孔连接初始信号线的第一分支INIT-1；
初始信号线的第二分支INIT-2在基底10上的正投影，与第二连接电极44在基底10上的正投影至少部分重叠。
本实施例中，初始信号线的第二分支INIT-2(位于第四导电层)纵向连接形成网状，并且在第二连接电极44(即第一节点N1)的位置绕线，对第二连接电极44进行屏蔽遮挡，由于发光区和像素电路区的间距(Pitch)不一样，所以每个像素电路的第一节点N1上方的环境不同，因此导致每个像素电路的第一节点N1的寄生电容不同，本公开实施例通过初始信号线的第二分支INIT-2对第二连接电极44(即第一节点N1)进行屏蔽遮挡，减小了上层金属对第一节点N1造成的影响，优化了显示效果。
在一些示例性实施方式中，如图6b和图13所示，初始信号线的第二分 支INIT-2包括主体部INIT-21和弯折部，主体部INIT-21沿第二方向Y延伸，弯折部包括两个第一延伸部INIT-22以及设置在两个第一延伸部INIT-22之间的第二延伸部INIT-23，第一延伸部INIT-22沿第一方向X延伸，第二延伸部INIT-23沿第二方向Y延伸，第一方向X与第二方向Y相交(在示例性实施方式中，第一方向X与第二方向Y相互垂直)，第二延伸部INIT-23沿第一方向X的宽度d2大于主体部INIT-21沿第一方向X的宽度d1。
在一些示例性实施方式中，第三导电层还包括第一电源线VDD、第一连接电极43和第四连接电极46，第四导电层还包括阳极连接电极52，发光控制晶体管包括第一发光控制晶体管(即图6b或图6d中的第六晶体管T6)；
阳极连接电极52通过绝缘层上的过孔连接第一连接电极43和第四连接电极46，第一连接电极43通过绝缘层上的过孔连接第一发光控制晶体管的第二区，第四连接电极46通过绝缘层上的过孔连接第二复位晶体管的第二区；
阳极连接电极52在基底10上的正投影，与第一电源线VDD在基底10上的正投影至少部分重叠。
本实施例中，通过使得阳极连接电极52在基底10上的正投影，与第一电源线VDD在基底10上的正投影至少部分重叠，使得第一电源线VDD对阳极连接电极52进行屏蔽遮挡，减小了下层金属对阳极连接电极52造成的影响，优化了显示效果。
在一些示例性实施方式中，阳极连接电极52在基底10上的正投影，与第一复位晶体管的第二极在基底10上的正投影至少部分重叠。
在一些示例性实施方式中，如图6b和图6e所示，显示基板还包括依次设置在第四导电层上的平坦层(图中未示出)、阳极(图中未示出)、有机发光层(图中未示出)和阴极(图中未示出)；
阳极通过平坦层上的阳极过孔(即图6e中的第十四过孔V14)与阳极连接电极52连接；阳极过孔位于第三区域R3。
在一些示例性实施方式中，第四导电层还包括第五连接电极51和初始信号线的第三分支INIT-3；
初始信号线的第三分支INIT-3沿第一方向X延伸，初始信号线的第二 分支INIT-2沿第二方向Y延伸，第一方向X与第二方向Y交叉；
第五连接电极51、初始信号线的第二分支INIT-2与初始信号线的第三分支INIT-3相互连接成一体结构，初始信号线的第三分支INIT-3在基底10上的正投影，与初始信号线的第一分支INIT-1在基底10上的正投影至少部分重叠。
本实施例中，初始信号线的第三分支INIT-3(位于第三导电层)与初始信号线的第一分支INIT-1(位于半导体层)并联，以减小初始信号线INIT的信号负载。
在一些示例性实施方式中，如图6e和图7b所示，该显示基板还包括位于多个子像素之间的虚拟像素行，虚拟像素行包括多个虚拟子像素，虚拟子像素包括虚拟像素驱动电路，虚拟像素驱动电路包括虚拟复位晶体管、虚拟数据写入晶体管，虚拟复位晶体管的沟道区(即图7b中的C区域)以及虚拟数据写入晶体管的沟道区(即图7b中的D区域)均为断裂结构。
在一些示例性实施方式中，如图6e、图8b和图11c所示，虚拟像素驱动电路包括虚拟存储电容、虚拟初始信号线、虚拟复位信号线、虚拟发光信号线和虚拟扫描信号线，虚拟发光信号线、虚拟存储电容的第一极板与虚拟扫描信号线相互连接成一体结构，虚拟存储电容的第一极板和第二极板以及虚拟复位信号线分别通过绝缘层上的过孔(即图6e中的第一过孔V1、第二过孔V2、第十三过孔V13)与第一电源线VDD连接。
在一些示例性实施方式中，虚拟复位晶体管包括虚拟第一晶体管和虚拟第七晶体管，虚拟第一晶体管的第二极通过虚拟子像素中的第六过孔V6与第一电源线VDD连接，虚拟第七晶体管的第二极通过虚拟子像素中的第七过孔V7与第一电源线VDD连接。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某 一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作：
(1)在示例性实施例中，形成半导体层图案可以包括：在基底10上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底10的第一绝缘层91，以及设置在第一绝缘层91上的半导体层，如图7a和图7b所示，图7a为正常像素的半导体层的平面示意图，图7b为图5b中虚线区域的四个像素形成半导体层后的显示基板平面示意图。
在示例性实施例中，每个子像素的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17以及初始信号线的第一分支INIT-1，且第一有源层11至第七有源层17以及初始信号线的第一分支INIT-1为相互连接的一体结构。
在示例性实施例中，第一区域R1可以包括初始信号线的第一分支INIT-1、至少部分的第一晶体管T1的第一有源层11、第二晶体管T2的第二有源层12、第四晶体管T4的第四有源层14和第七晶体管T7的第七有源层17，第二区域R2可以包括至少部分的第三晶体管T3的第三有源层13，第三区域R3可以包括至少部分的第五晶体管T5的第五有源层15和第六晶体管T6的第六有源层16。初始信号线的第一分支INIT-1、第一有源层11和第七有源层17设置在第一区域R1内远离第二区域R2的一侧，第二有源层12和第四有源层14设置在第一区域R1内邻近第二区域R2的一侧。
在示例性实施例中，初始信号线的第一分支INIT-1设置在第一晶体管 T1的第一有源层11远离第二区域R2的一侧，
在示例性实施例中，第一有源层11的形状可以呈“Z”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，初始信号线的第一分支INIT-1与第一有源层11的第一区11-1相互连接，形成一体结构；初始信号线的第一分支INIT-1还设置有向其延伸方向两侧的凸起，该凸起同时作为第七有源层17的第一区17-1；第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1。在示例性实施例中，第六有源层16的第二区16-2、第七有源层17的第二区17-2、第四有源层14的第一区14-1和第五有源层15的第一区15-1单独设置。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层92，以及设置在第二绝缘层92上的第一导电层图案，第一导电层图案至少包括：扫描信号线Gate、复位信号线Reset、发光信号线EM和存储电容的第一极板Ce1，如图8a、图8b和8c所示，图8a为正常像素的第一导电层的平面示意图，图8b为正常像素形成第一导电层后的显示基板平面示意图，图8c为图5b中虚线区域的四个像素形成第一导电层后的显示基板平面示意图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
在示例性实施例中，扫描信号线Gate、复位信号线Reset和发光信号线EM沿第一方向X延伸。扫描信号线Gate和复位信号线Reset设置在第一区域R1内，复位信号线Reset位于扫描信号线Gate远离第二区域R2的一侧，发光信号线EM设置在第三区域R3内，存储电容的第一极板Ce1设置在第二区域R2内，位于扫描信号线Gate和发光信号线EM之间。
在示例性实施例中，第一极板Ce1可以为矩形状，矩形状的角部可以设置倒角，第一极板Ce1在基底10上的正投影与第三晶体管T3的第三有源层在基底10上的正投影存在重叠区域。在示例性实施例中，第一极板Ce1同时作为第三晶体管T3的栅电极。
在示例性实施例中，复位信号线Reset设置有向扫描信号线Gate一侧凸起的第一凸块21-1，第一凸块21-1在基底10上的正投影与第一晶体管T1的第一有源层在基底10上的正投影存在重叠区域，复位信号线Reset和第一凸块21-1与第一晶体管T1的第一有源层相重叠的区域作为第一晶体管T1双栅结构的栅电极，复位信号线Reset与第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅电极。扫描信号线Gate与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅电极。扫描信号线Gate设置有向复位信号线Reset一侧凸起的第二凸块21-2，第二凸块21-2在基底10上的正投影与第二晶体管T2的第二有源层在基底10上的正投影存在重叠区域，扫描信号线Gate和第二凸块21-2与第二晶体管T2的第二有源层相重叠的区域作为第二晶体管T2双栅结构的栅电极。发光信号线EM与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光信号线EM与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
本次工艺后，显示基板包括设置在基底10上的第一绝缘层91、设置在第一绝缘层91上的半导体层、覆盖半导体层的第二绝缘层92和设置在第二绝缘层92上的第一导电层，半导体层可以包括初始信号线的第一分支INIT-1、第一有源层11至第七有源层17，第一导电层可以包括扫描信号线Gate、复位信号线Reset、发光信号线EM和存储电容的第一极板Ce1。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜， 采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层93，以及设置在第三绝缘层93上的第二导电层图案，第二导电层图案至少包括：存储电容的第二极板Ce2、屏蔽电极32和极板连接线31，如图9a和图9b所示，图9a为正常像素的第二导电层的平面示意图，图9b为正常像素形成第二导电层后的显示基板平面示意图，图9c为图5b中虚线区域的四个像素形成第二导电层后的显示基板平面示意图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
在示例性实施例中，存储电容的第二极板Ce2设置在第二区域R2内，位于扫描信号线Gate和发光信号线EM之间。屏蔽电极32设置在第一区域R1内，屏蔽电极32配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，第二极板Ce2的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板Ce2在基底10上的正投影与第一极板Ce1在基底10上的正投影存在重叠区域。第二极板Ce2上设置有开口H，开口H可以位于第二区域R2的中部。开口H可以为矩形，使第二极板Ce2形成环形结构。开口H暴露出覆盖第一极板Ce1的第三绝缘层，且第一极板Ce1在基底10上的正投影包含开口H在基底10上的正投影。在示例性实施例中，开口H配置为容置后续形成的第一过孔，第一过孔位于开口H内并暴露出第一极板Ce1，使后续形成的第二连接电极44与第一极板Ce1连接。
在示例性实施例中，极板连接线31设置在第一方向X上相邻子像素的第二极板Ce2之间，极板连接线31的第一端与本子像素的第二极板Ce2连接，极板连接线31的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻子像素的第二极板Ce2连接，即极板连接线31配置为使第一方向X上相邻子像素的第二极板相互连接。在示例性实施例中，通过极板连接线31，使一子像素行中的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一子像素行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第二极板Ce2邻近第一区域R1的边缘在基底10上 的正投影与第一区域R1与第二区域R2的交界线在基底10上的正投影重叠，第二极板Ce2邻近第三区域R3的边缘在基底10上的正投影与第二区域R2与第三区域R3的交界线在基底10上的正投影重叠，即第二极板Ce2的长度等于第二区域R2的长度，第二极板Ce2的长度是指第二极板Ce2第二方向Y上的尺寸。
本次工艺后，显示基板包括设置在基底10上的第一绝缘层91、设置在第一绝缘层91上的半导体层、覆盖半导体层上的第二绝缘层92、设置在第二绝缘层92上的第一导电层，覆盖第一导电层的第三绝缘层93和设置在第三绝缘层93上的第二导电层，半导体层可以包括第一有源层11至第七有源层17，第一导电层可以包括扫描信号线Gate、复位信号线Reset、发光信号线EM和存储电容的第一极板Ce1，第二导电层可以包括存储电容的第二极板Ce2、屏蔽电极32和极板连接线31。
(4)形成第四绝缘层94图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层94，第四绝缘层94上设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如图10a、图10b和图10c所示，图10a为正常像素的第四绝缘层94的平面示意图，图10b为正常像素形成第四绝缘层94后的显示基板平面示意图，图10c为图5b中虚线区域的四个像素形成第四绝缘层94后的显示基板平面示意图。
在示例性实施例中，第一过孔V1位于第二极板Ce2的开口H内，第一过孔V1在基底10上的正投影位于开口H在基底10上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板Ce1的表面。第一过孔V1配置为使后续形成的第二连接电极44通过该过孔与第一极板Ce1连接。
在示例性实施例中，第二过孔V2位于第二极板Ce2所在区域，第二过孔V2在基底10上的正投影位于第二极板Ce2在基底10上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板Ce2的表面。 第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板Ce2连接。在示例性实施例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，增加第一电源线与第二极板Ce2的连接可靠性。
在示例性实施例中，第三过孔V3位于第三区域R3，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在示例性实施例中，第四过孔V4位于第三区域R3，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接。
在示例性实施例中，第五过孔V5位于第一区域R1，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在示例性实施例中，第六过孔V6位于第一区域R1，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在示例性实施例中，第七过孔V7位于第一区域R1，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第二区的表面。第七过孔V7配置为使后续形成的第四连接电极46通过该过孔与第七有源层连接。
在示例性实施例中，第八过孔V8位于第一区域R1，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极32的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极32连接。
在示例性实施例中，第九过孔V9位于第一区域R1，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第七有源层的第一区(也即初始信号线31)的表面。第九过孔V9配置为使后续形成的第三连接电极45通过该过孔与第七有源层的第一区(也即初始信号线31)连接。
在示例性实施例中，如图10c所示，第四绝缘层94上还设置第十三过孔V13，第十三过孔V13位于虚拟像素行中的复位信号线Reset上，第十三过孔V13内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出虚拟像素行中的复位信号线Reset的表面，第十三过孔V13配置为使后续形成的第一电源线VDD通过该过孔与虚拟像素行中的复位信号线Reset连接。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层94上的第三导电层，第三导电层至少包括：第一电源线VDD、数据信号线Data、第一连接电极43、第二连接电极44、第三连接电极45和第四连接电极46，如图11a、图11b和图11c所示，图11a为正常像素的第三导电层的平面示意图，图11b为正常像素形成第三导电层后的显示基板平面示意图，图11c为图5b中虚线区域的四个像素形成第三导电层后的显示基板平面示意图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施例中，第一电源线VDD沿着第二方向Y延伸，第一电源线VDD一方面通过第二过孔V2与第二极板Ce2连接，另一方面通过第八过孔V8与屏蔽电极32连接，又一方面通过第三过孔V3与第五有源层连接，使屏蔽电极32和第二极板Ce2具有与第一电源线VDD相同的电位。由于屏蔽电极32在基底10上的正投影与后续形成的数据信号线在基底10上的正投影存在重叠区域，且屏蔽电极32与第一电源线VDD连接，有效屏蔽了数据电压跳变对关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，数据信号线Data沿着第二方向Y延伸，数据信号线Data通过第五过孔V5与第四有源层的第一区连接，使数据信号线Data传输的数据信号写入第四晶体管T4。
在示例性实施例中，第一连接电极43通过第四过孔V4与第六有源层的第二区连接。在示例性实施例中，第一连接电极43可以作为第六晶体管T6的第二极。在示例性实施例中，第一连接电极43配置为与后续形成的阳极连接电极连接。
在示例性实施例中，第二连接电极44沿着第二方向Y延伸，其第一端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板Ce1连接，使第一极板Ce1、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第二连接电极44可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施例中，第三连接电极45通过第九过孔V9与第七有源层的第一区连接，由于第七有源层的第一区、第一有源层的第一区与初始信号线31为相互连接的一体结构，第三连接电极45与初始信号线31连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与初始信号线31相同的电位。在示例性实施例中，第三连接电极45可以作为第七晶体管T7的第一极和第一晶体管T1的第一极。
在示例性实施例中，第四连接电极46通过第七过孔V7与第七有源层的第二区连接。在示例性实施例中，第四连接电极46可以作为第七晶体管T7的第二极。在示例性实施例中，第四连接电极46配置为与后续形成的阳极连接电极连接。
在示例性实施例中，第一电源线VDD在虚拟像素行内包括第三凸块，第三凸块可以为不规则形状，第三凸块可以通过绝缘层上的过孔分别与虚拟存储电容的第一极板、虚拟复位信号线、虚拟复位晶体管的第二极(虚拟第一晶体管的第二极以及虚拟第七晶体管的第二极)连接。
在示例性实施例中，数据信号线Data可以为等宽度直线，或者为非等宽度的直线。
(6)形成第一平坦层95图案。在示例性实施例中，形成第一平坦层95图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层95，第 一平坦层95上设置有第十过孔V10、第十一过孔V11和第十二过孔V12，如图12a、图12b和图12c所示，图12a为正常像素的第一平坦层95的平面示意图，图12b为正常像素形成第一平坦层95后的显示基板平面示意图，图12c为图5b中虚线区域的四个像素形成第一平坦层95后的显示基板平面示意图。
第十过孔V10位于第四连接电极46所在区域，第十一过孔V11位于第一连接电极43所在区域，第十过孔V10和第十一过孔V11内的第一平坦层分别被去掉，暴露出第四连接电极46和第一连接电极43的表面，第十过孔V10和第十一过孔V11配置为使后续形成的阳极连接电极52通过该两个过孔与第六晶体管T6的第二极以及第七晶体管T7的第二极连接。
第十二过孔V12位于第三连接电极45所在区域，第十二过孔V12内的第一平坦层被去掉，暴露出第三连接电极45的表面，第十二过孔V12配置为使后续形成的初始信号线的第二分支和第三分支通过该过孔与第三连接电极45连接。
(7)形成第四导电层图案。形成第四导电层可以包括：在形成前述图案的基底上，沉积第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成设置在第一平坦层95上的第四导电层，第四导电层至少包括：第一初始信号线的第二分支INIT-2、第一初始信号线的第三分支INIT-3、第五连接电极51和阳极连接电极52，如图13、图6b、图6c和图6e所示，图13为正常像素的第四导电层的平面示意图，图6b为正常像素形成第四导电层后的显示基板平面示意图，图6c为图6b中AA区域的剖视图，图6e为图5b中虚线区域的四个像素形成第四导电层后的显示基板平面示意图。在示例性实施例中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施例中，第一初始信号线的第二分支INIT-2沿着第二方向Y延伸，第一初始信号线的第三分支INIT-3沿着第一方向X延伸，第五连接电极51设置在第一初始信号线的第二分支INIT-2与第一初始信号线的第三分支INIT-3相交叠的区域，且第五连接电极51、第一初始信号线的第二分支INIT-2与第一初始信号线的第三分支INIT-3为相互连接的一体结构。第一初始信号线的第三分支INIT-3在基底10上的正投影与第一初始信号线的 第一分支INIT-1在基底10上的正投影存在重叠区域，第一初始信号线的第三分支INIT-3与第一初始信号线的第一分支INIT-1形成双层走线，第五连接电极51通过第十二过孔V12与第三连接电极45连接。
在示例性实施例中，第一初始信号线的第二分支INIT-2设置有多个弯折部INIT-21，弯折部INIT-21在基底10上的正投影与第二连接电极44在基底10上的正投影存在重叠区域，配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，阳极连接电极52通过第十过孔V10和第十一过孔V11分别与第四连接电极46和第一连接电极43连接。
(8)形成第二平坦层图案。在一些示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层(图中未示出)，第二平坦层上至少设置有阳极过孔(即图6e中的第十四过孔V14)。
在一些示例性实施方式中，第十四过孔位于阳极连接电极52所在区域，第十四过孔内的第二平坦层被去掉，暴露出阳极连接电极52的表面，第十四过孔配置为使后续形成的阳极通过该过孔与阳极连接电极52电连接。
至此，在基底10上制备完成驱动电路层图案。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的扫描信号线、复位信号线、发光信号线、数据信号线、第一电源线、初始信号线等。在垂直于显示基板的平面内，驱动电路层可以包括在基底10上依次叠设的第一绝缘层91、半导体层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94、第三导电层、第一平坦层95、第四导电层和第二平坦层。
在示例性实施例中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作：
在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在第二平坦层上的阳极层。
涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成 像素定义层(PDL)，每个子像素的像素定义层设置有子像素开口，子像素开口暴露出阳极。
采用蒸镀或喷墨打印工艺形成有机发光层，在有机发光层上形成阴极。
阳极、像素定义层、有机发光层和阴极构成发光结构层图案。
在示例性实施例中，制备完成发光结构层后，在发光结构层上制备封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，在制备柔性显示基板时，显示基板的制备过程可以包括剥离玻璃载板、贴附背膜、切割等工艺，本公开在此不作限定。
在一些示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在一些示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在一些示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。阳极层可以采用氧化铟锡ITO或氧化铟锌IZO等透明导电材料。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或 复合层。第一绝缘层称为缓冲(BUF)层，用于提高基底的抗水氧能力，第二绝缘层称为第一栅绝缘(GI1)层，第三绝缘层称为第二栅绝缘(GI2)层，第四绝缘层称为层间绝缘(ILD)层。第一平坦(PLN1)层和第二平坦(PLN2)层可以采用有机材料。半导体层可以采用多晶硅(p-Si)或者氧化物。
本公开实施例的显示基板通过使每行子像素中的复位晶体管均由本行子像素中的复位信号线控制，即采用同级复位方式，使得每一行子像素的GOA驱动一行扫描信号线和一行复位信号线，进而使得不同区域的充电时间相同，从而提高了显示面板的显示效果。
本公开所示显示基板的结构及其制备过程仅仅是一种示例性说明，在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
如图3、图5b和图14所示，本公开实施例还提供了一种显示基板，包括多个子像素以及位于多个子像素之间的虚拟像素行H，至少一个子像素包括像素驱动电路和发光器件，像素驱动电路包括初始信号线INIT、复位信号线Reset、扫描信号线Gate、发光信号线EM和多个晶体管；
多个晶体管包括驱动晶体管(即图3中的第三晶体管T3)、第一复位晶体管(即图3中的第一晶体管T1)和第二复位晶体管(即图3中的第七晶体管T7)，驱动晶体管被配置为为发光器件提供驱动电流，第一复位晶体管被配置为在复位信号线Reset的控制下，通过初始信号线INIT对驱动晶体管的栅极进行复位，第二复位晶体管被配置为在扫描信号线Gate的控制下，通过初始信号线INIT对发光器件的阳极进行复位；
显示基板包括多个栅极连接电极53，多个栅极连接电极53跨设在虚拟像素行H上，栅极连接电极53被配置为连接位于虚拟像素行H一侧的第一复位晶体管的栅电极以及位于虚拟像素行H另一侧的第二复位晶体管的栅电极。
在一些示例性实施方式中，栅极连接电极53与多个晶体管的栅电极位于不同的导电层上。
在一些示例性实施方式中，在垂直于显示基板的平面内，该显示基板包 括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，以及设置在半导体层和第一导电层之间或者各个导电层之间的绝缘层；
半导体层包括多个晶体管的有源层，第一导电层包括多个晶体管的栅电极、扫描信号线Gate、复位信号线Reset和存储电容的第一极板，第二导电层包括存储电容的第二极板，第三导电层包括第一电源线VDD和数据信号线Data，第四导电层包括阳极连接电极；
示例性的，栅极连接电极53可以位于第三导电层、第四导电层和阳极层中的任意一层或多层上，本公开对此不作限制。
本实施例中，通过栅极连接电极使得虚拟像素行的上一行子像素中的第二复位晶体管的栅电极和虚拟像素行的下一行子像素中的第一复位晶体管的栅电极连接，从而使得虚拟像素行的上一行子像素中的第二复位晶体管与虚拟像素行的下一行子像素中的第一复位晶体管共用一条复位信号线，进而使得每一行子像素的GOA驱动一行扫描信号和一行复位信号，即同时驱动两行信号，提高了显示效果。
本公开还提供一种显示基板的制备方法，以制备上述实施例提供的显示基板，所述显示基板包括多个子像素，至少一个所述子像素被划分为：第一区域、第二区域和第三区域，所述第一区域和第三区域分别位于所述第二区域的两侧。在一些示例性实施方式中，该显示基板的制备方法可以包括以下步骤：
在基底上形成半导体层，所述半导体层包括初始信号线以及多个晶体管的有源层，所述多个晶体管包括驱动晶体管、复位晶体管和发光控制晶体管，所述驱动晶体管位于所述第二区域，所述子像素连接的初始信号线与所述复位晶体管位于所述第一区域，所述发光控制晶体管位于所述第三区域；
在所述半导体层上形成第一导电层，所述第一导电层包括多个晶体管的栅电极、复位信号线和发光信号线，所述子像素连接的复位信号线位于所述第一区域，所述子像素连接的发光信号线位于所述第三区域，所述驱动晶体管被配置为为所述发光器件提供驱动电流，所述复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线对所述驱动晶体管的栅极和/或所 述发光器件的阳极进行复位，所述发光控制晶体管被配置为在所述发光信号线的控制下，允许或禁止所述驱动电流通过。
本公开提供的显示基板的制备方法所制备的显示基板，其实现原理和实现效果与前述的显示基板的实现原理和实现效果类似，在此不再赘述。
本公开还提供一种显示基板的驱动方法，所述显示基板包括多个子像素，至少一个所述子像素包括像素驱动电路和发光器件，如图6d所示，所述像素驱动电路包括：驱动子电路101、第一复位子电路102、第二复位子电路103、数据写入子电路104、补偿子电路105和发光控制子电路106；所述驱动方法包括：
在初始化阶段，第一复位子电路102在复位信号的控制下，对所述驱动子电路101的控制端进行复位；所述第二复位子电路103在所述复位信号的控制下，对所述发光器件的第一端进行复位；
在数据写入及补偿阶段，所述数据写入子电路104在扫描信号的控制下，将数据信号写入所述驱动子电路101，所述补偿子电路105对所述驱动子电路101进行补偿；
在所述发光阶段，所述发光控制子电路106在发光信号的控制下，将所述驱动子电路101产生的驱动电流施加至所述发光器件以使其发光；
同一子像素内的所述第一复位子电路102和第二复位子电路103通过同一根复位信号线进行控制。
在一些示例性实施方式中，如图6d所示，所述驱动子电路101包括第三晶体管T3，其中，第三晶体管T3的栅电极与第一节点N1(即存储电容C的第一端)连接，第三晶体管T3的第一极与第二节点N2(即第四晶体管T4的第二极)连接，第三晶体管T3的第二极与第三节点N3(即第二晶体管T2的第一极)连接。
在一些示例性实施方式中，如图6d所示，所述第一复位子电路102包括第一晶体管T1，其中，第一晶体管T1的栅电极与复位信号线Reset连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管T1的第二极与第一节点N1连接。
在一些示例性实施方式中，如图6d所示，所述第二复位子电路103包括第七晶体管T7，其中，第七晶体管T7的栅电极与复位信号线Reset连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与第四节点N4(即发光器件的第一端)连接。
在一些示例性实施方式中，如图6d所示，所述数据写入子电路104包括第四晶体管T4，其中，第四晶体管T4的栅电极与扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第二节点N2连接。
在一些示例性实施方式中，如图6d所示，所述补偿子电路105包括第二晶体管T2和存储电容C，其中，第二晶体管T2的栅电极与扫描信号线Gate连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接；存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第一节点N1连接。
在一些示例性实施方式中，如图6d所示，所述发光控制子电路106包括第五晶体管T5和第六晶体管T6，其中，第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接；第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种显示基板，包括多个子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述像素驱动电路包括初始信号线、复位信号线和多个晶体管，所述初始信号线包括第一分支；
    所述多个晶体管包括驱动晶体管、第一复位晶体管和第二复位晶体管，所述驱动晶体管被配置为为所述发光器件提供驱动电流，所述第一复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线的第一分支对所述驱动晶体管的栅极进行复位；所述第二复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线的第一分支对所述发光器件的第一端进行复位；
    同一子像素内的所述第一复位晶体管和所述第二复位晶体管通过同一根复位信号线进行控制。
  2. 根据权利要求1所述的显示基板，其中，所述初始信号线的第一分支沿第一方向延伸，所述初始信号线的第一分支与所述多个晶体管的有源层同层设置。
  3. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括存储电容；
    在所述同一子像素内，所述第一复位晶体管和所述第二复位晶体管均位于所述初始信号线的第一分支与所述存储电容之间。
  4. 根据权利要求1所述的显示基板，其中，在所述同一子像素内，所述第一复位晶体管位于所述第二复位晶体管沿第一方向的一侧。
  5. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括第一发光控制晶体管、第二发光控制晶体管和阳极连接电极，所述阳极连接电极通过阳极过孔与所述第一发光控制晶体管的第二极连接，其中：
    所述第一发光控制晶体管、所述阳极过孔以及所述第二发光控制晶体管沿第一方向排列，且所述阳极过孔位于所述第一发光控制晶体管与所述第二 发光控制晶体管之间。
  6. 根据权利要求1所述的显示基板，其中，所述多个晶体管的有源层包括沟道区、位于所述沟道区一侧用于与源电极对应的第一区、以及位于所述沟道区另一侧用于与漏电极对应的第二区，所述第一复位晶体管的有源层的第一区、所述第二复位晶体管的有源层的第一区以及所述初始信号线的第一分支相互连接成一体结构。
  7. 根据权利要求1所述的显示基板，其中，所述第一复位晶体管的有源层为“L”形，所述复位信号线在每个子像素内设置有第一凸块，所述复位信号线和所述第一凸块与所述第一复位晶体管的沟道区相重叠的区域作为所述第一复位晶体管的双栅结构的栅电极。
  8. 根据权利要求1所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，以及设置在所述半导体层和第一导电层之间或者各个导电层之间的绝缘层；
    所述半导体层包括多个晶体管的有源层和所述初始信号线的第一分支，所述第一导电层包括多个晶体管的栅电极、复位信号线和存储电容的第一极板，所述第二导电层包括所述存储电容的第二极板，所述第三导电层包括第二连接电极，所述第四导电层包括初始信号线的第二分支；
    所述第二连接电极被配置为通过绝缘层上的过孔，连接所述驱动晶体管的栅电极与所述第一复位晶体管的第二区，所述初始信号线的第二分支通过绝缘层上的过孔连接所述初始信号线的第一分支；
    所述初始信号线的第二分支在基底上的正投影，与所述第二连接电极在基底上的正投影至少部分重叠。
  9. 根据权利要求8所述的显示基板，其中，所述初始信号线的第二分支包括主体部和弯折部，所述主体部沿第二方向延伸，所述弯折部包括两个第一延伸部以及设置在所述两个第一延伸部之间的第二延伸部，所述第一延伸部沿第一方向延伸，所述第二延伸部沿所述第二方向延伸，所述第一方向与 所述第二方向交叉，所述第二延伸部沿所述第一方向的宽度大于所述主体部沿所述第一方向的宽度。
  10. 根据权利要求8所述的显示基板，其中，所述第三导电层还包括第一电源线、第一连接电极和第四连接电极，所述第四导电层还包括阳极连接电极，所述发光控制晶体管包括第一发光控制晶体管；
    所述阳极连接电极通过绝缘层上的过孔连接所述第一连接电极和所述第四连接电极，所述第一连接电极通过绝缘层上的过孔连接所述第一发光控制晶体管的第二区，所述第四连接电极通过绝缘层上的过孔连接所述第二复位晶体管的第二区；
    所述阳极连接电极在基底上的正投影，与所述第一电源线在基底上的正投影至少部分重叠。
  11. 根据权利要求10所述的显示基板，其中，所述阳极连接电极在基底上的正投影，与所述第一复位晶体管的第二极在基底上的正投影至少部分重叠。
  12. 根据权利要求8所述的显示基板，其中，所述第四导电层还包括第五连接电极和所述初始信号线的第三分支；
    所述初始信号线的第三分支沿第一方向延伸，所述初始信号线的第二分支沿第二方向延伸，所述第一方向与所述第二方向交叉；
    所述第五连接电极、所述初始信号线的第二分支与所述初始信号线的第三分支相互连接成一体结构，所述初始信号线的第三分支在基底上的正投影，与所述初始信号线的第一分支在基底上的正投影至少部分重叠。
  13. 根据权利要求1所述的显示基板，还包括位于所述多个子像素之间的虚拟像素行，所述虚拟像素行包括多个虚拟子像素，所述虚拟子像素包括虚拟像素驱动电路，所述虚拟像素驱动电路包括虚拟复位晶体管、虚拟数据写入晶体管，所述虚拟复位晶体管的沟道区以及所述虚拟数据写入晶体管的沟道区均为断裂结构。
  14. 根据权利要求13所述的显示基板，还包括第一电源线，所述虚拟像 素驱动电路包括虚拟存储电容、虚拟初始信号线、虚拟复位信号线、虚拟发光信号线和虚拟扫描信号线，所述虚拟发光信号线、虚拟存储电容的第一极板与虚拟扫描信号线相互连接成一体结构，所述虚拟存储电容的第一极板和第二极板以及所述虚拟复位信号线分别通过绝缘层上的过孔与所述第一电源线连接。
  15. 一种显示基板，包括多个子像素以及位于所述多个子像素之间的虚拟像素行，至少一个所述子像素包括像素驱动电路和发光器件，所述像素驱动电路包括初始信号线、复位信号线、扫描信号线、发光信号线和多个晶体管；
    所述多个晶体管包括驱动晶体管、第一复位晶体管和第二复位晶体管，所述驱动晶体管被配置为为所述发光器件提供驱动电流，所述第一复位晶体管被配置为在所述复位信号线的控制下，通过所述初始信号线对所述驱动晶体管的栅极进行复位，所述第二复位晶体管被配置为在所述扫描信号线的控制下，通过所述初始信号线对所述发光器件的阳极进行复位；
    所述显示基板包括多个栅极连接电极，多个所述栅极连接电极跨设在所述虚拟像素行上，所述栅极连接电极被配置为连接位于所述虚拟像素行一侧的第一复位晶体管的栅电极以及位于所述虚拟像素行另一侧的第二复位晶体管的栅电极。
  16. 根据权利要求15所述的显示基板，其中，所述栅极连接电极与所述多个晶体管的栅电极位于不同的导电层上。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的驱动方法，所述显示基板包括多个子像素，至少一个所述子像素包括像素驱动电路和发光器件，所述像素驱动电路包括驱动子电路、第一复位子电路、第二复位子电路、数据写入子电路、补偿子电路和发光控制子电路，所述驱动方法包括：
    在初始化阶段，所述第一复位子电路在复位信号的控制下，对所述驱动子电路的控制端进行复位；所述第二复位子电路在所述复位信号的控制下， 对所述发光器件的第一端进行复位；同一子像素内的所述第一复位子电路和第二复位子电路通过同一根复位信号线进行控制；
    在数据写入及补偿阶段，所述数据写入子电路在扫描信号的控制下，将数据信号写入所述驱动子电路，所述补偿子电路对所述驱动子电路进行补偿；
    在发光阶段，所述发光控制子电路在发光信号的控制下，将所述驱动子电路产生的驱动电流施加至所述发光器件以使其发光。
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