WO2023184352A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023184352A1
WO2023184352A1 PCT/CN2022/084444 CN2022084444W WO2023184352A1 WO 2023184352 A1 WO2023184352 A1 WO 2023184352A1 CN 2022084444 W CN2022084444 W CN 2022084444W WO 2023184352 A1 WO2023184352 A1 WO 2023184352A1
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WIPO (PCT)
Prior art keywords
signal line
initial
layer
driving circuit
transistor
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Application number
PCT/CN2022/084444
Other languages
English (en)
French (fr)
Inventor
杨慧娟
刘庭良
张毅
舒晓青
廖茂颖
王予
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/084444 priority Critical patent/WO2023184352A1/zh
Priority to CN202280000603.4A priority patent/CN117157699A/zh
Publication of WO2023184352A1 publication Critical patent/WO2023184352A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present invention aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate having a display area and a virtual pixel area surrounding the display area; the virtual pixel area includes at least one pixel missing area and is adjacent to the pixel missing area.
  • a driving circuit layer is provided on the substrate, the driving circuit layer includes a plurality of circuit units; at least one of the circuit units includes: a pixel driving circuit and an initial signal line; the pixel driving circuit includes a pixel located in the display area A first pixel driving circuit and a second pixel driving circuit located in the redundant area, and the storage capacitance of the first pixel driving circuit is smaller than the storage capacitance of the second pixel driving circuit;
  • a light-emitting structure layer is provided on the side of the driving circuit layer facing away from the substrate; the light-emitting structure layer includes a plurality of light-emitting devices located in the display area; wherein,
  • the plurality of initial signal lines include a first initial signal line extending along a first direction and a second initial signal line extending along a second direction; the first direction and the second direction intersect, and the first The initial signal line is electrically connected to at least part of the second initial signal line intersecting therewith.
  • the first pixel driving circuit and the second pixel driving circuit each include a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor and the storage capacitor; the first pixel driving circuit
  • the circuit also includes fifth and sixth transistors.
  • the driving circuit layer is sequentially provided with a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer along a side away from the substrate;
  • the semiconductor layer includes the pixel driving circuit the active layer of a plurality of transistors;
  • the first conductive layer includes scanning signal lines, gate electrodes of the plurality of transistors and the first plate of the storage capacitor;
  • the second conductive layer includes the first initial The signal line and the second plate of the storage capacitor;
  • the fourth conductive layer includes the second initial signal line.
  • the second initialization signal includes an extension part and a connection part connected to each other; the extension part extends along the second direction, and the connection part is connected to the first initial signal line.
  • the overlapping area of the orthographic projection of the second plate of the storage capacitor and the extension part on the substrate is the first area; in the circuit unit having the In the circuit unit of the second pixel driving circuit, the overlapping area of the orthographic projection of the second plate of the storage capacitor and the extension part on the substrate is a second area; the area of the first area is smaller than the second area The area of the region.
  • the display substrate includes i rows and j column circuit units; i ⁇ 2; j ⁇ 3, and i and j are integers;
  • the shape of the second initial signal line in the M-th row and N-th column circuit unit is substantially the same as the shape of the second initial signal line in the M+1-th row and N+2-th column circuit unit;
  • the shape of the second initial signal line in the circuit unit of the Nth column of the +1 row is substantially the same as the shape of the second initial signal line of the circuit unit of the N+2th column of the Mth row; where 1 ⁇ M ⁇ i; 1 ⁇ N ⁇ j, and M and N are both integers.
  • the extension part includes a first initial part, a second initial part and a first initial part connected in sequence along the second direction.
  • Three initial parts, the first initial part and the third initial part extend along the second direction, and the extension direction of the second initial part and the second direction have a first included angle ⁇ 1, 0° ⁇ 1 ⁇ 90°.
  • the extension portion includes a fourth initial portion, a fifth initial portion, a fourth initial portion, and a third initial portion connected in sequence along the second direction.
  • the second direction has a second included angle ⁇ 2
  • the extending direction of the seventh initial portion has a third included angle ⁇ 3 with the second direction, 0° ⁇ 2 ⁇ 90°, and 0° ⁇ 3 ⁇ 90°.
  • the circuit unit further includes a plurality of first power lines, one of the extension parts and an orthographic projection of one of the first power lines on the substrate at least partially overlap; the connection part and the first initial Orthographic projections of the signal lines on the substrate at least partially overlap.
  • the first power line is a polygonal line of unequal width; the first power line includes a first power part, a second power part, a third power part, a fourth power part and a power part connected in sequence along the second direction.
  • the fifth power supply part; the first power supply part, the third power supply part and the fifth power supply part extend along the second direction, and the extension directions of the second power supply part and the fourth power supply part are different and are different from The second directions intersect.
  • the first power line is located on the third conductive layer.
  • the second conductive layer further includes a shielding electrode, and the shielding electrode is electrically connected to the first power line through a via hole.
  • an orthographic projection of at least part of the shielding electrode on the substrate is located between an orthographic projection of the second electrode of the first transistor of the pixel driving circuit on the substrate.
  • the circuit unit further includes a plurality of data signal lines; the data signal lines are located on the fourth conductive layer.
  • the circuit unit further includes a plurality of second connection electrodes; the connection part is connected to the second connection electrode through a via hole; the second connection electrode is connected to the first initial signal line through a via hole; The second connection electrode is also connected to the first region of the first transistor and the second region of the seventh transistor in the pixel driving circuit through a via hole.
  • the second connection electrode is located on the third conductive layer.
  • the overlapping area of the first plate and the second plate of the storage capacitor in the first pixel driving circuit is smaller than the first plate and the second plate of the storage capacitor in the second pixel driving circuit.
  • a plurality of the circuit units form a plurality of unit rows arranged side by side along the second direction and a plurality of unit columns arranged side by side along the first direction, and the pixel driving circuits in the unit rows are arranged along the The pixel driving circuits in the unit column are arranged side by side along the second direction;
  • the second initial signal lines in each of the circuit units in at least one of the unit columns are connected to each other.
  • the plurality of unit columns include alternately arranged first unit columns and second unit columns; the second initialization line is provided in the first unit column.
  • an embodiment of the present disclosure further provides a display device, which includes any of the above display substrates.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic diagram of the planar structure of a display substrate
  • Figure 3 is a schematic cross-sectional structural diagram of a display substrate
  • Figure 4a is an equivalent circuit schematic diagram of a pixel driving circuit
  • Figure 4b is a working timing diagram of a pixel driving circuit
  • Figure 5 is a distributed schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • Figure 6a is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 6b is a schematic diagram of an initial signal line in a display substrate according to an exemplary embodiment of the present disclosure
  • Figure 7 is a schematic diagram of the present disclosure after the semiconductor layer pattern is formed on the substrate;
  • Figure 8a is a schematic diagram of the display substrate after forming a first conductive layer pattern
  • Figure 8b is a schematic plan view of the first conductive layer in Figure 8a;
  • Figure 9a is a schematic diagram of the display substrate after forming a second conductive layer pattern
  • Figure 9b is a schematic plan view of the second conductive layer in Figure 9a;
  • Figure 10a is a schematic diagram of the disclosure showing that the fourth insulating layer pattern is formed on the substrate;
  • Figure 10b is a schematic plan view of multiple via holes in Figure 10a;
  • Figure 11a is a schematic diagram of the third conductive layer pattern formed on the display substrate of the present disclosure.
  • Figure 11b is a schematic plan view of the third conductive layer in Figure 11a;
  • Figure 12a is a schematic diagram of the display substrate after forming a first flat layer pattern
  • Figure 12b is a schematic plan view of multiple via holes in Figure 12a;
  • Figure 13a is a schematic diagram of the display substrate of the present disclosure after forming a fourth conductive layer pattern
  • Figure 13b is a schematic plan view of the fourth conductive layer in Figure 13a;
  • Figure 14a is a schematic diagram of the display substrate after forming a second flat layer pattern
  • Figure 14b is a schematic plan view of multiple via holes in Figure 14a;
  • Figure 15 is an equivalent circuit schematic diagram of a second pixel driving circuit of another display substrate of the present disclosure.
  • Figure 16 is a schematic structural diagram of another display substrate according to the present disclosure.
  • Figure 17 is a schematic plan view of a semiconductor layer of another display substrate according to the present disclosure.
  • Figure 18 is a schematic plan view of the first conductive layer of another display substrate according to the present disclosure.
  • Figure 19 is a schematic plan view of the second conductive layer of another display substrate of the present disclosure.
  • Figure 20 is a schematic plan view of the third conductive layer of another display substrate of the present disclosure.
  • Figure 21 is a schematic plan view of the fourth conductive layer of another display substrate of the present disclosure.
  • FIG. 22 is a schematic diagram of the stacking of the third conductive layer and the fourth conductive layer of another display substrate according to the present disclosure.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light-emitting signal line and pixel driving circuit.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample a grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 that emits light of the first color, and a first sub-pixel P1 that emits light of the second color.
  • the four sub-pixels may each include a circuit unit and a light-emitting device.
  • the circuit unit may include a scanning signal line, a data signal line and a light emitting device. A light-emitting signal line and a pixel driving circuit.
  • the pixel driving circuit is connected to the scanning signal line, the data signal line and the light-emitting signal line respectively.
  • the pixel driving circuit is configured to receive the data transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixel may be a rectangular shape, a rhombus shape, a pentagonal shape, or a hexagonal shape.
  • four sub-pixels can be arranged in a square (Square) manner to form a GGRB pixel arrangement, as shown in Figure 2a.
  • four sub-pixels can be arranged in a diamond pattern to form an RGBG pixel arrangement, as shown in Figure 2b.
  • four sub-pixels may be arranged horizontally or vertically.
  • the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction are called pixel rows, and a plurality of sub-pixels arranged in sequence in the vertical direction are called pixel columns.
  • the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. .
  • FIG. 3 is a schematic cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 provided on a substrate 101 , a light-emitting structure layer 103 provided on a side of the driving circuit layer 102 away from the substrate, and a light-emitting structure layer 103 provided on the side of the driving circuit layer 102 away from the substrate.
  • Layer 103 is away from the encapsulation layer 104 on the side of the substrate.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include multiple signal lines and pixel driving circuits, and the pixel driving circuit may include multiple transistors and storage capacitors. In FIG. 3 , only one driving transistor 210 and one storage capacitor 211 are used as an example for illustration.
  • the light-emitting structure layer 103 of each sub-pixel may include multiple film layers that constitute a light-emitting device.
  • the multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 communicates with the driving transistor 210 through a via hole.
  • the drain electrode is connected, the organic light-emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of the corresponding color driven by the anode 301 and the cathode 304.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, referred to as HTL), and an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short) and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron blocking layer
  • EBL Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers and electron injection layers of all sub-pixels may be a common layer connected together
  • the hole transport layers and electron transport layers of all sub-pixels may be a common layer connected together
  • all The hole blocking layers of sub-pixels may be a common layer connected together
  • the light-emitting layers and electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is respectively connected to 7 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power supply line VDD and the second power supply line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor,
  • the first electrode of the second transistor T2 and the control electrode of the third transistor T3 are connected to the second end of the storage capacitor C.
  • the third node N3 is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switching transistor, a scanning transistor, or the like.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth and sixth transistors T5 and T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the second electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the first electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the initial voltage to the first pole of the light-emitting device, so that the amount of charge accumulated in the first pole of the light-emitting device is initialized or released to emit light. The amount of charge accumulated in the first pole of the device.
  • the light-emitting device may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode) , quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scanning signal line Line S1 is S(n), and the second scanning signal line S2 is S(n-1).
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row. Signal lines can reduce the signal lines of the display panel and achieve a narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG 4b is a working timing diagram of a pixel driving circuit.
  • the pixel driving circuit in Figure 4a includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), 7 transistors are It is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, turning on the first transistor T1.
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to turn off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. Node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 to turn off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • FIG. 5 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a display area 01 and a virtual pixel area 02, wherein at least one pixel missing area 021 is provided in the virtual pixel area 02 ( Two are taken as an example in Figure 5), and a redundant area 022 adjacent to the pixel missing area 021.
  • the base substrate at the position of the via hole area 021 is provided with via holes for installing sensor devices such as cameras, so there are no display devices (including pixel driving circuits and light emitting devices) in the pixel missing area 021.
  • Redundant Area 022 In order to avoid as much as possible the problem of poor display uniformity of the display panel due to the setting of the pixel missing area 021, a pixel driving circuit is usually provided in the redundant area 022, but no light-emitting device is provided. Despite this, the setting of the missing pixel area will still cause uneven display of pixels in the row where the missing pixel area 021 is located and other positions in the display area 01 .
  • the first scanning signal line S1 and the second scanning signal line S2 are connected laterally through the first conductive layer winding
  • the initial signal line INIT is laterally connected through the second conductive layer winding
  • the line D is connected vertically through the third conductive layer winding, so that the first scanning signal line S1 and the second scanning signal line S2 on the left and right sides of the virtual pixel area 02 are connected to the initial signal line INIT.
  • the data signal line D Connect up and down. This kind of winding causes the loading of the initial signal line INIT to be very different from the loading in the normal area.
  • the loading of the initial signal line INIT in the via hole area 021 is small, resulting in a low node position of the pixel N4, and the final current is too small, which is biased on the display. dark.
  • Figure 6a is a schematic structural diagram of a driving circuit layer according to an exemplary embodiment of the present disclosure; as shown in Figures 5 and 6, an embodiment of the present disclosure provides a display substrate having a display area 01 and a surrounding display area Virtual pixel area 02 of 01.
  • the display substrate includes a base, a driving circuit layer and a light-emitting structure layer arranged on the base in sequence.
  • the driving circuit layer includes a plurality of circuit units; the plurality of circuit units in the driving circuit layer may form a plurality of unit rows arranged side by side along the second direction and a plurality of unit columns arranged side by side along the first direction.
  • the circuit units in each unit row are arranged side by side in the first direction X, and the circuit units in each unit column are arranged side by side in the second direction Y.
  • the light-emitting structure layer includes a plurality of light-emitting devices located in the display area 01.
  • At least one circuit unit includes a pixel driving circuit and an initial signal line.
  • a pixel driving circuit is electrically connected to a light-emitting device.
  • the pixel driving circuit and the light-emitting device are connected in a one-to-one correspondence.
  • the pixel driving circuit may include a plurality of transistors and storage capacitors.
  • the initial signal line is configured to initialize (reset) at least one of a storage capacitor in the pixel drive circuit and/or a first pole of the light emitting device.
  • the initial signal line in at least one circuit unit may include a first initial signal line 31 with a main part extending along the first direction X and a second initial signal line 52 with a main part extending along the second direction Y, and the An initial signal line 31 and a second initial signal line 52 are connected through via holes.
  • A extends along the direction B. It means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body.
  • the main part extends along the direction B, and the main part extends along the direction B.
  • the length of extension in one direction is greater than the length of the secondary portion extending in other directions.
  • the second initial signal line 52 may include an extension portion 521 and a connection portion 522 connected to each other, the main portion of the extension portion 521 extending along the second direction Y, and the main portion of the connection portion 522 extends along the first direction X.
  • the end of the connecting portion on a side away from the extension portion 521 may be connected to the first initial signal line 31 through a via hole.
  • the orthographic projection of at least part of the connection portion 522 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate.
  • the orthographic projection of at least part of the extension 521 on the substrate is within the range of the orthographic projection of the first power line 41 on the substrate.
  • FIG. 6b is a schematic diagram of an initial signal line in a driving circuit layer according to an exemplary embodiment of the present disclosure.
  • the driving circuit layer may include a plurality of unit rows and a plurality of unit columns, and the first initial signal line may be disposed in each unit row.
  • the second initial signal lines may be arranged in spaced unit columns, that is, between two adjacent second initial signal lines in the first direction X, there is at least one unit column spaced apart.
  • the direction of the unit row may be the first direction X
  • the direction of the unit column may be the second direction Y.
  • the plurality of sub-pixels in the display substrate may include a red sub-pixel R emitting red light, a blue sub-pixel B emitting blue light, a first green sub-pixel G1 emitting green light, and a first green sub-pixel G1 emitting green light.
  • the red sub-pixel R may include a red light-emitting device that emits red light and a first circuit unit Q1 connected to the red light-emitting device
  • the blue sub-pixel B may include a blue light-emitting device that emits blue light and a first circuit unit Q1 connected to the blue light-emitting device.
  • the second circuit unit Q2 and the first green sub-pixel G1 may include a first green light-emitting device that emits green light and a third circuit unit Q3 connected to the first green light-emitting device.
  • the second green sub-pixel G2 may include a first green light-emitting device that emits green light.
  • the second green light-emitting device and the fourth circuit unit Q4 connected to the second green light-emitting device, the first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3 and the fourth circuit unit Q4 form a circuit unit group, at least
  • the four circuit units in a circuit unit group can be arranged in a square manner, that is, the four circuit units are arranged in two unit rows and two unit columns.
  • the sub-pixels mentioned in this disclosure refer to areas divided according to light-emitting devices, and the circuit units mentioned in this disclosure refer to areas divided according to pixel driving circuits.
  • the positions of the subpixel and the circuit unit may correspond, or the positions of the subpixel and the circuit unit may not correspond.
  • the plurality of unit columns may include a first unit column and a second unit column.
  • the first unit column refers to a column formed by a plurality of first circuit units Q1 and second circuit units Q2.
  • the second unit column refers to a column formed by a plurality of first circuit units Q1 and second circuit units Q2.
  • a plurality of third circuit units Q3 and fourth circuit units Q4 form a column.
  • the first circuit unit Q1 and the second circuit unit Q2 in the first unit column are alternately arranged along the second direction Y, and the third circuit unit Q3 and the fourth circuit unit Q4 in the second unit column are alternately arranged along the second direction Y. set up.
  • the second initial signal line 52 may be disposed in the first cell column.
  • the N-th unit column and the N+2-th unit column may be the first unit column
  • the N+1-th unit column and the N+3-th unit column may be the second unit column
  • the second initial signal line 52 may be disposed in the The second initial signal line 52 repeats every second unit column in the N unit column, the N+2-th unit column, the N+4-th unit column, ....
  • the second initial signal line 52 may be provided in the second cell column.
  • the N-th unit column and the N+2-th unit column may be the first unit column
  • the N+1-th unit column and the N+3-th unit column may be the second unit column
  • the second initial signal line 52 may be disposed in the The second initial signal line 52 is repeated every other first unit column in the N+1 unit column, the N+3 unit column, the N+5 unit column, ....
  • the second initial signal line 52 may be provided in the first cell column and the second cell column.
  • the Nth unit column and the N+2th unit column may be the first unit column, and the N+1th unit column and the N+3th unit column may be the second unit column.
  • the circuit unit in the Mth row is the first circuit unit
  • the circuit unit in the M+1th row is the second circuit unit. Therefore, the first circuit unit and the second circuit unit in the Nth unit column are along the The second direction Y is set alternately.
  • the circuit unit in the Mth row is the second circuit unit
  • the circuit unit in the M+1th row is the first circuit unit. Therefore, the second circuit unit in the N+2th unit column and the first circuit unit are The circuit units are alternately arranged along the second direction Y.
  • the second initial signal line in the Mth row and Nth column circuit unit since the Mth row and Nth column circuit unit and the M+1th row and N+2th column circuit unit are both first circuit units, the second initial signal line in the Mth row and Nth column circuit unit The shape of may be the same as the shape of the second initial signal line in the circuit unit of the M+1th row and the N+2th column. Since the circuit unit in row M+1 and column N and the circuit unit in row M and column N+2 are both second circuit units, the shape of the second initial signal line in the circuit unit in row M+1 and column N is the same as The shapes of the second initial signal lines in the M-th row and N+2-th column circuit units may be the same.
  • the extension part 521 may include a first initial part, a second initial part and a third initial part connected in sequence.
  • the first initial part and the third initial part may be parallel to the second direction Y
  • the second initial part may have a first included angle with the second direction Y, and the first included angle may be greater than 0° and less than 90°.
  • ends of the first initial part and/or the third initial part may be connected to the connecting part 522 .
  • the extension part 521 may include a fourth initial part, a fifth initial part, and a sixth initial part connected in sequence.
  • the seventh initial part and the eighth initial part, the fourth initial part, the sixth initial part and the eighth initial part may be parallel to the second direction Y
  • the fifth initial part may have a first included angle with the second direction Y
  • the The initial part may have a second included angle with the second direction Y.
  • the first included angle may be greater than 0° and less than 90°
  • the second included angle may be greater than 0° but less than 90°.
  • the extension direction of the fifth initial portion and the extension direction of the seventh initial portion may be substantially mirror-symmetrical with respect to the first direction X.
  • the second initial signal lines 52 may be disposed in spaced first unit columns or second unit columns, that is, between two adjacent second initial signal lines 52 in the first direction unit column.
  • the second initial signal line 52 can be provided in the Nth unit column, the N+4th unit column, the N+8th unit column, ..., the second initial signal line 52 is arranged in every first unit column and every second unit column. Two units are repeated.
  • the second initial signal line 52 may be provided in the N+1th unit column, the N+5th unit column, the N+9th unit column, ..., the second initial signal line 52 is arranged in every second first unit column and A second unit column is repeated.
  • the number of unit columns spaced between adjacent second initial signal lines 52 has no special requirements and can be set as needed, and is not limited in this disclosure.
  • the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate;
  • the semiconductor layer may include active layers of a plurality of transistors, the first conductive layer may include scanning signal lines and gate electrodes of the plurality of transistors, the second conductive layer may include a first initial signal line 31 , and the third conductive layer may include a first The power supply line and the first and second electrodes of the plurality of transistors, the fourth conductive layer may include a data signal line and a second initial signal line 52 .
  • the third conductive layer may also include second connection electrode 44 .
  • the second connection electrode 44 located on the third conductive layer can be connected to the first initial signal line 31 located on the second conductive layer through a via hole, and the second initial signal line 52 located on the fourth conductive layer can be connected to the first initial signal line 31 located on the third conductive layer through a via hole.
  • the second connection electrode 44 of the conductive layer is connected.
  • the second connection electrode may be called an initial connection electrode.
  • the second connection electrode 44 may be connected to the first active layer region of the first transistor and the first active layer region of the seventh transistor in the pixel driving circuit through a via hole.
  • the second conductive layer may also include a shield electrode 33, and the first power line 41 is connected to the shield electrode through a via hole.
  • the orthographic projection of at least part of the shielding electrode 33 on the substrate is located between the orthographic projection of the data signal line on the substrate and the orthographic projection of the second electrode of the first transistor in the pixel driving circuit on the substrate.
  • the driving circuit layer may also include a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23, and a storage capacitor.
  • the storage capacitor may include a first plate and a second plate, a plurality of transistors. It may include first to seventh transistors, and the third transistor is a driving transistor.
  • the first conductive layer may include a first scan signal line 21, a second scan signal line 22, a light emitting control line 23, a first plate of a storage capacitor, and gate electrodes of a plurality of transistors
  • the second conductive layer may It includes the first initial signal line 31, the second plate 32 of the storage capacitor, the shield electrode 33 and the plate connection line 35.
  • the third conductive layer may include the first power line 41, the data connection electrode, the first connection electrode 43, the The second connection electrode 44 , the third connection electrode 45 and the data connection electrode 43
  • the fourth conductive layer may include a data signal line 51 , a second initial signal line 52 and an anode connection electrode 53 .
  • the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, the first insulating layer being disposed between the substrate and the semiconductor layer, and the second insulating layer
  • the insulating layer is provided between the semiconductor layer and the first conductive layer
  • the third insulating layer is provided between the first conductive layer and the second conductive layer
  • the fourth insulating layer is provided between the second conductive layer and the third conductive layer
  • the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the driving circuit layer may include the following operations.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the first Semiconductor layer on the insulating layer, as shown in Figure 7.
  • the semiconductor layer of each circuit unit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7 , and the first active layer 11 to the seventh active layer 17 of the seventh transistor T7 .
  • the layer 17 is an integral structure connected to each other.
  • the sixth active layer 16 of the M-th row circuit unit in each unit column and the seventh active layer 17 of the M+1-th row circuit unit are connected to each other, that is, in each unit column
  • the semiconductor layers of adjacent circuit units are an integral structure connected to each other.
  • the first active layer 11 , the second active layer 12 , the fourth active layer 14 and the seventh active layer 17 in the M-th row circuit unit are located in the third active layer 13 of this circuit unit.
  • the first active layer 11 and the seventh active layer 17 are located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13,
  • the fifth active layer 15 and the sixth active layer 16 in the M-th row circuit unit are located on the side of the third active layer 13 close to the M+1-th row circuit unit.
  • the shape of the first active layer 11 may be in the shape of an "n"
  • the shape of the second active layer 12 may be in the shape of a "7”
  • the shape of the third active layer 13 may be in the shape of a "ji”.
  • the fourth active layer 14 may be in a "1" shape
  • the fifth active layer 15 , the sixth active layer 16 and the seventh active layer 17 may be in an "L" shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer 11 simultaneously serves as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 simultaneously
  • the first region 12-1 of the second active layer 12 the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the fifth active layer 15.
  • the second area 15-2 of the third active layer 13 serves as the second area 12-2 of the second active layer 12 and the first area 16-1 of the sixth active layer 16 at the same time.
  • the second region 16-2 of the sixth active layer 16 simultaneously serves as the second region 17-2 of the seventh active layer 17.
  • the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are provided separately.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, and patterning the first conductive film through a patterning process to form a covering semiconductor.
  • the second insulating layer of the layer pattern, and the first conductive layer pattern provided on the second insulating layer, the first conductive layer pattern at least includes: a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23 and
  • the first electrode plate 24 is shown in Figures 8a and 8b.
  • Figure 8b is a schematic plan view of the first conductive layer in Figure 8a.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first scanning signal line 21 , the second scanning signal line 22 and the light emitting control line 23 may mainly extend along the first direction X.
  • the first scanning signal line 21 and the second scanning signal line 22 in the M-th row S2 circuit unit are located on the side of the first plate 24 of this circuit unit away from the M+1-th row circuit unit, and the second scanning signal line 22 is located on The first scanning signal line 21 of this circuit unit is on the side away from the first plate 24, and the light-emitting control line 23 can be located on the side of the first plate 24 of this circuit unit close to the M+1th row circuit unit.
  • the first plate 24 may be in a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate 24 on the substrate is consistent with the third active layer of the third transistor T3 on the substrate. There are overlapping areas in the orthographic projections.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the area where the first scanning signal line 21 overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2, and the first scanning signal line 21 is provided with a protrusion toward the second scanning signal line 22.
  • the gate block 21-1 has an overlapping area between the orthographic projection of the gate block 21-1 on the substrate and the orthographic projection of the second active layer 12 on the substrate, forming the second transistor T2 with a double-gate structure.
  • the area where the first scanning signal line 21 overlaps the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps the first active layer 11 serves as the gate electrode of the first transistor T1 in the double-gate structure.
  • the area where the second scanning signal line 22 overlaps the seventh active layer 17 serves as the seventh transistor T1 .
  • the gate electrode of the transistor T7, the area where the light-emitting control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 23 overlaps with the sixth active layer 16 serves as the sixth transistor T6. gate electrode.
  • the first conductive layer can be used as a shield to perform a conductive process on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the first to seventh transistors T1 to T7 In the channel region, the semiconductor layer in the area not blocked by the first conductive layer is conductive, that is, the first region and the second region of the first active layer to the seventh active layer are all conductive.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process to form A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer.
  • the second conductive layer pattern at least includes: a first initial signal line 31, a second electrode plate 32, and a shielding electrode 33. and plate connecting lines 35, as described in Figures 9a and 9b.
  • Figure 9b is a schematic plan view of the second conductive layer in Figure 9a.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the first initial signal line 31 may extend mainly along the first direction
  • the second plate 32 serves as the other plate of the storage capacitor and is located between the first scanning signal line 21 and the light-emitting control line 23 of the circuit unit.
  • the shielding electrode 33 is located on the side of the circuit unit. Between the second scanning signal line 22 and the first scanning signal line 21 of the unit (excluding the main part of the gate block 21-1), the shielding electrode 33 is configured to shield the impact of the data voltage jump on the key node to avoid the data voltage The jump affects the potential of key nodes of the pixel drive circuit and improves the display effect.
  • the outline of the second electrode plate 32 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 32 on the base is the same as the orthographic projection of the first electrode plate 24 on the base.
  • the second electrode plate 32 is provided with an opening 34 , and the opening 34 may be located in the middle of the second electrode plate 32 .
  • the opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located in the opening 34 and exposes the first plate 24 so that the subsequently formed second electrode of the first transistor T1 Connected to the first plate 24.
  • the plate connection line 35 is disposed between the second plates 32 of adjacent circuit units in the first direction X or in the opposite direction to the first direction X, and the first end of the plate connection line 35 is connected to The second plate 32 of this circuit unit is connected, and the second end of the plate connection line 35 extends along the first direction X or the opposite direction of the first direction X, and is connected to the second plate 32 of the adjacent circuit unit, That is, the plate connecting lines 35 are configured to connect the second plates of adjacent circuit units in a unit row to each other.
  • the second plates of multiple circuit units in a unit row can form an integrated structure connected to each other through the plate connection lines 35, and the second plates of the integrated structure can be reused as power signal lines, Ensuring that multiple second electrode plates in a unit row have the same potential is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • each circuit unit is provided with a plurality of via holes.
  • the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V4, and a third via hole V3.
  • Figure 10a is a schematic plan view of the multiple via holes in Figure 10a. .
  • the first via V1 is located within the opening 34 of the second plate 32 , and the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured so that the second electrode of the subsequently formed first transistor T1 is connected to the first plate 24 through the via hole.
  • the second via hole V2 is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, and the orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the second electrode plate 32 on the substrate.
  • the fourth insulating layer in the second via hole V2 is etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured to allow the subsequently formed first power line to be connected to the second plate 32 through the via hole.
  • the second via hole V2 serving as a power via hole may include multiple, and the plurality of second via holes V2 may be arranged sequentially along the second direction Y to increase the connection between the first power line and the second plate 32 . Connection reliability.
  • the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away to expose the surface of the first region of the fifth active layer.
  • the third via hole V3 is configured to allow a subsequently formed first power line to be connected to the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is within the range of the orthographic projection of the sixth active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away, exposing the surface of the second area of the sixth active layer (also the second area of the seventh active layer).
  • the fourth via hole V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the sixth active layer through the via hole. Seven active layer connections.
  • the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the fourth active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away to expose the surface of the first region of the fourth active layer.
  • the fifth via hole V5 is configured to connect a subsequently formed data signal line to the fourth active layer through the via hole.
  • the fifth via hole V5 is called a data writing hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer).
  • the sixth via hole V6 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first active layer through the via hole, and to connect the first electrode of the subsequently formed second transistor T2 to the first active layer through the via hole. Two active layer connections.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away, exposing the surface of the first region of the seventh active layer (also the first region of the first active layer).
  • the seventh via hole V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole, and to connect the first electrode of the subsequently formed first transistor T1 to the seventh active layer through the via hole.
  • An active layer connection is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole, and to connect the first electrode of the subsequently formed first transistor T1 to the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the shield electrode 33 on the substrate, and the fourth insulating layer in the eighth via hole V8 is etched away, exposing the shield. the surface of electrode 33.
  • the eighth via hole V8 is configured so that the first power supply line formed later is connected to the shield electrode 33 through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer in the ninth via hole V9 is etched away, The surface of the first initial signal line 31 is exposed.
  • the ninth via hole V9 is configured so that the first electrode of the subsequently formed seventh transistor T7 (also the first electrode of the first transistor T1 ) is connected to the first initial signal line 31 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive film disposed on the fourth insulating layer.
  • the third conductive layer at least includes: first power line 41, data connection electrode 42, first connection electrode 43, second connection electrode 44 and third connection electrode 45, as shown in Figure 11a and Figure 11b, Figure 11b is a schematic plan view of the third conductive layer in FIG. 11a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the main part of the first power line 41 extends along the second direction Y.
  • the first power line 41 is connected to the second plate 32 through the second via hole V2
  • the first power line 41 is connected to the second plate 32 through the second via hole V2 .
  • the three vias V3 are connected to the fifth active layer
  • the eighth via V8 is connected to the shielding electrode 33 , so that the shielding electrode 33 and the second plate 32 have the same potential as the first power line 41 .
  • the shield electrode 33 is connected to the first power line 41, and the orthographic projection of at least part of the shield electrode 33 (such as the protruding portion on the right side of the shield electrode 33) on the substrate is located at the first connection electrode 43 (as the first transistor T1 Between the orthographic projection of the second pole and the first pole of the second transistor T2, that is, the second node N2) on the substrate and the orthographic projection of the subsequently formed data signal line on the substrate, the data voltage jump pair can be effectively shielded.
  • the influence of key nodes in the pixel driving circuit avoids the data voltage jump from affecting the potential of the key nodes in the pixel driving circuit, thereby improving the display effect.
  • the orthographic projection of at least a portion of the shielding electrode 33 on the substrate may at least partially overlap with the orthographic projection of the subsequently formed data signal line on the substrate.
  • the shield electrodes 33 in adjacent circuit units in the first direction X may be connected to each other to reduce resistance.
  • the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, and the data connection electrode 42 is configured to be connected to a subsequently formed data signal line.
  • the first connection electrode 43 extends along the second direction Y, and its first end passes through the sixth via hole V6 and is connected to the second area of the first active layer (also the first area of the second active layer).
  • the second end of the first electrode plate 24 is connected to the first electrode plate 24 through the first via hole V1, so that the first electrode plate 24, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 43 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the first end of the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, and the second end thereof is connected to the first region of the seventh active layer through the seventh via hole V7 ( (also the first region of the first active layer) are connected so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the first initial signal line 31 .
  • the second connection electrode 44 may serve as a first electrode of the seventh transistor T7 and a first electrode of the first transistor T1, and the second connection electrode 44 is configured to connect a second initial signal line formed subsequently.
  • the present disclosure can reduce the number of via holes and the number of transfer electrodes and save wiring space by arranging the second connection electrode to simultaneously connect the seventh active layer, the first initial signal line and the second initial signal line.
  • the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second electrode of the sixth transistor T6 and The second pole of the seventh transistor T7 has the same potential.
  • the third connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the third connection electrode 45 is configured to be connected to a subsequently formed anode connection electrode.
  • the first power line 41 of at least one circuit unit may be a polygonal line of unequal width.
  • the first power supply line 41 of each circuit unit may include a first power supply part d1 , a second power supply part d2 , a third power supply part d3 , a fourth power supply part d4 and a fifth power supply part connected in sequence.
  • d5 the first power supply part d1, the third power supply part d3 and the fifth power supply part d5 may be parallel to the second direction Y
  • the second power supply part d2 may be bent towards the first direction X
  • the fourth power supply part d4 may be bent towards the first direction Bend in the opposite direction of direction X.
  • the angle between the second power part d2 and the first power part d1 may be greater than 0° and less than 90°, and the angle between the fourth power part d4 and the third power part d3 may be greater than 0° and less than 90°.
  • the fifth power supply part d5 is provided with a connection part d6 extending in the opposite direction of the first direction X, and the connection part d6 is configured to be connected to the fifth active layer through a third via hole.
  • the first power supply line 41 is arranged in a zigzag line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power supply line and the data signal line.
  • the shapes of the first power lines of each circuit unit may be the same, or may be different.
  • the shape of the first power line in the M-th row and N-th column circuit unit may be the same as the shape of the first power line in the M+1-th row and N+2-th column circuit unit.
  • the shape of the first power line in the circuit unit in row 1 and column N+2 may be the same as the shape of the first power line in the circuit unit in row M and column N+2.
  • the shape of the first power line in the circuit unit in row M and column N+1 may be the same.
  • the shape of a power line can be the same as the shape of the first power line in the M+1th row and N+3th column circuit unit.
  • the shape of the first power line in the M+1th row and N+1th column circuit unit is the same as The shapes of the first power lines in the Mth row and N+3rd column circuit units may be the same.
  • the shape of the second connection electrode in each circuit unit in the Nth column may be the same as the shape of the second connection electrode in each circuit unit in the N+2th column, and the shape of the second connection electrode in each circuit unit in the N+1th column may be the same.
  • the shape of the two connection electrodes may be the same as the shape of the second connection electrode in each circuit unit of the N+3th column.
  • the shape of the second connection electrode in the N+1th and N+3th column circuit units may be a strip shape extending along the second direction Y, and the second connection electrode is configured to pass through the ninth via hole and the seventh via hole. are respectively connected to the first initial signal line and the first region of the seventh active layer.
  • the shape of the second connection electrode 44 in the circuit unit of the Nth column and the N+2th column may include a first portion 44-1 and a second portion 44-2 connected to each other.
  • the first portion 44-1 is along the second
  • the second part 44-2 may be in a rectangular shape extending in the direction Y.
  • the second part 44-2 is provided on the opposite side of the first part 44-1 in the first direction X.
  • the first part 44-1 is configured In order to be connected to the first initial signal line and the first region of the seventh active layer through the ninth via hole and the seventh via hole respectively, the second portion 44-2 is configured to be connected to the subsequently formed second portion through the subsequently formed via hole.
  • the initial signal line is connected, thereby realizing the connection between the first initial signal line and the second initial signal line.
  • the shapes of the third connection electrodes of each circuit unit may be the same, or may be different.
  • the shape of the third connection electrode in the M-th row and N-th column circuit unit may be the same as the shape of the third connection electrode in the M+1-th row and N+2-th column circuit unit.
  • the shape of the third connection electrode in the circuit unit of row 1 and column N can be the same as the shape of the third connection electrode in the circuit unit of row M and column N+2.
  • the shape of the third connection electrode in the circuit unit of row M and column N+1 can be the same.
  • the shape of the three connection electrodes can be the same as the shape of the third connection electrode in the M+1th row and N+3th column circuit unit, and the shape of the third connection electrode in the M+1th row and N+1th column circuit unit can be the same as The shapes of the third connection electrodes in the Mth row and N+3th column circuit units may be the same.
  • the shapes of the data connection electrodes and the first connection electrodes of the respective circuit units may be the same, or may be different.
  • forming the first flat layer pattern may include: coating a first flat film on the substrate on which the foregoing pattern is formed, patterning the first flat film using a patterning process, and forming a covering third conductive layer.
  • the first flat layer is provided with an eleventh via hole V11, a twelfth via hole V12 and a thirteenth via hole V13 on the first flat layer, as shown in Figure 12a and Figure 12b.
  • Figure 12b is the multiplexed via hole V11 in Figure 12a.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the data connection electrode 42 on the substrate, and the first flat layer in the eleventh via hole V11 is Removed, the surface of the data connection electrode 42 is exposed, and the eleventh via hole V11 is configured to allow a subsequently formed data signal line to be connected to the data connection electrode 42 through the via hole.
  • the eleventh via hole V11 may be in a strip shape, and the extension length in the second direction Y in the eleventh via hole V11 is greater than the extension length in the first direction X.
  • the eleventh via hole V11 in a strip shape extending along the second direction Y, the width of the eleventh via hole V11 in the first direction X can be reduced, and the inclination of the subsequently formed anode can be reduced.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the second connection electrode 44 on the substrate.
  • the first flat layer in the twelfth via hole V12 is removed, exposing the second connection electrode. 44, the twelfth via hole V12 is configured so that the second initial signal line formed subsequently is connected to the second connection electrode 44 through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the third connection electrode 45 on the substrate.
  • the first flat layer in the thirteenth via hole V13 is removed, exposing the third connection electrode. 45, the thirteenth via hole V13 is configured so that the subsequently formed anode connection electrode is connected to the third connection electrode 45 through the via hole.
  • all circuit units are provided with an eleventh via hole V11 and a thirteenth via hole V13, and each circuit unit in the Nth column and the N+2th column is provided with a twelfth via hole V12.
  • the twelfth via V12 is not provided in each circuit unit in the N+1 column and the N+3 column.
  • the positions of the eleventh via hole V11 and the thirteenth via hole V13 in each circuit unit may be the same, or may be different.
  • Form a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a pattern on the first planar layer.
  • the fourth conductive layer on the top, the fourth conductive layer at least includes: data signal line 51, second initial signal line 52 and anode connection electrode 53, as shown in Figure 13a and Figure 13b, Figure 13b is the fourth conductive layer in Figure 13a schematic plan view.
  • the data signal line 51 is provided in each unit column.
  • the data signal line 51 may extend along the second direction Y, and the data signal line 51 is connected to the data connection electrode 42 through the eleventh via hole V11. Since the data connection electrode 42 is connected to the first area of the fourth active layer through the fifth via hole V5, the data signal line 51 is connected to the first area of the fourth active layer through the data connection electrode 42, and the data signal line 51 is connected to the first area of the fourth active layer through the data connection electrode 42.
  • the second initial signal line 52 is provided in the N-th unit column and the N+2-th unit column, and the second initial signal line 52 of each circuit unit in the unit column is connected to each other.
  • the main part of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second connection electrode 44 through the twelfth via hole V12. Since the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, the second initial signal line 52 is connected to the first initial signal line 31 through the second connection electrode 44, so that the first initial signal Line 31 and second initial signal line 52 have the same potential.
  • This disclosure not only effectively reduces the initial signal line by arranging the first initial signal line 31 whose main part extends along the first direction X and the second initial signal line 52 extending along the second direction Y, so that the initial signal line forms a mesh structure.
  • the resistance of the line reduces the voltage drop of the initial voltage, and effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.
  • anode connection electrode 53 is provided in at least part of the circuit unit.
  • the anode connection electrode 53 is connected to the third connection electrode 45 through the thirteenth via hole V13. Since the third connection electrode 45 is connected to the second area of the sixth active layer (also the second area of the seventh active layer) through the fourth via hole V4, the anode connection electrode 53 is connected to the second area of the sixth active layer through the third connection electrode 45. The second area of the sixth active layer (also the second area of the seventh active layer) is connected.
  • the second initial signal line 52 in one circuit unit may include an extension part 521 and a connection part 522.
  • the extension part 521 may be a fold line with a main part extending along the second direction Y
  • the connecting part 522 may be a straight line with a main part extending along the first direction X.
  • the end of the connection portion 522 on a side away from the extension portion 521 may be connected to the second connection electrode 44 through the twelfth via hole V12 .
  • the orthographic projection of at least part of the extension 521 on the substrate is within the range of the orthographic projection of the first power line 41 on the substrate, which not only allows the first power line 41 to effectively shield the second initial signal line 52 pair
  • the influence of key nodes in the pixel drive circuit prevents the initial signal from affecting the potential of the key nodes in the pixel drive circuit, and the layout space can be fully utilized to avoid the impact of the second initial signal line on the light transmittance, thereby improving the display effect.
  • the orthographic projection of at least part of the connection portion 522 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can fully utilize the layout space and avoid affecting the light due to the provision of the second initial signal line.
  • the transmittance improves the display effect.
  • the shape of the second initial signal line 52 in the M-th row and N-th column circuit unit may be the same as the shape of the second initial signal line 52 in the M+1-th row and N+2-th column circuit unit.
  • the shape of the second initial signal line 52 in the circuit unit of the M+1th row and the N+2th column may be the same as the shape of the second initial signal line 52 in the circuit unit of the Mth row and the N+2th column.
  • the extension part 521 may include a first initial part c1, a first initial part c1, a first initial part c1, a first initial part c1, a first initial part c1, and an N+2-th column circuit unit connected in sequence along the second direction Y.
  • the second initial part c2 and the third initial part c3, the first initial part c1 and the third initial part c3 can be parallel to the second direction Y, the second initial part c2 can deflect in the opposite direction of the first direction X, the second initial part c2 has a first included angle ⁇ 1 with the second direction Y, and the first included angle ⁇ 1 may be greater than 0° and less than 90°.
  • the extension portion 521 may include a fourth initial portion c4, a fourth initial portion c4, a fourth initial portion c4, and an N-th column connected in sequence along the second direction Y.
  • the fifth initial part c5, the sixth initial part c6, the seventh initial part c7 and the eighth initial part c8, the fourth initial part c4, the sixth initial part c6 and the eighth initial part c8 may be parallel to the second direction Y, and the fifth The initial part c5 may have a second included angle ⁇ 2 with the second direction Y, and the seventh initial part c7 may have a third included angle ⁇ 3 with the second direction Y.
  • the second included angle ⁇ 2 may be greater than 0° and less than 90°.
  • the angle ⁇ 3 can be greater than 0° and less than 90°.
  • the extension direction of the fifth initial portion c5 and the extension direction of the seventh initial portion c7 may be substantially mirror-symmetrical with respect to the first direction X.
  • At least some of the circuit units are provided with data signal lines 51 and anode connection electrodes 53, and each circuit unit in the Nth column and N+2th column is provided with a second initial signal line 52, and the N+1th column is provided with a second initial signal line 52.
  • the second initial signal line 52 is not provided in each circuit unit in the N+3th column.
  • the shape of the anode connecting electrode in the Mth row and Nth column circuit unit may be the same as the shape of the anode connecting electrode in the M+1th row and N+2nd column circuit unit, and the shape of the anode connecting electrode may be Rectangular shape.
  • the shape of the anode connecting electrode in the M+1th row and Nth column circuit unit may be the same as the shape of the anode connecting electrode in the Mth row and N+2nd column circuit unit, and the shape of the anode connecting electrode may be a dumbbell shape.
  • the shape of the anode connection electrode in the M-th row and N+1th column circuit unit may be the same as the shape of the anode connection electrode in the M+1th row and N+3th column circuit unit, and the shape of the anode connection electrode may be rectangular.
  • the shape of the anode connection electrode in the M+1th row and N+1th column circuit unit may be the same as the shape of the anode connection electrode in the Mth row and N+3th column circuit unit, and the shape of the anode connection electrode may be rectangular.
  • forming the second flat layer pattern may include: coating a second flat film on the substrate on which the foregoing pattern is formed, patterning the second flat film using a patterning process, and forming a covering fourth conductive layer.
  • the second flat layer is provided with a fourteenth via hole V14 on the second flat layer, as shown in Figures 14a and 14b.
  • Figure 14b is a schematic plan view of the multiple via holes in Figure 14a.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is within the range of the orthographic projection of the anode connection electrode 53 on the substrate, and the second flat layer in the fourteenth via hole V14 is Removed, the surface of the anode connection electrode 53 is exposed, and the fourteenth via hole V14 is configured to allow a subsequently formed anode to be connected to the anode connection electrode 53 through the via hole.
  • the driving circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a light emitting control circuit connected to the pixel driving circuit. line, a data signal line, a first power line, a first initial signal line and a second initial signal line.
  • the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the substrate. Four insulating layers, a third conductive layer, a first planar layer, a fourth conductive layer and a second planar layer.
  • a light-emitting structure layer is prepared on the driving circuit layer.
  • the preparation of the light-emitting structure layer means that a light-emitting device of the light-emitting structure layer is formed on the side of the driving circuit layer facing away from the substrate. Among them, the preparation process of the light-emitting device can adopt any method in the existing technology, so no details will be described here.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, and polyether ether ketone. , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • the materials of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • Any one or more of the above metals, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb) can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Can be single layer, multi-layer or composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate.
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer, and the fourth insulating layer is called the interlayer insulation (interlayer insulation). ILD) layer.
  • the active layer can use amorphous indium gallium zinc oxide materials (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), Materials such as hexathiophene or polythiophene, that is, this disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • the first flat layer and the second flat layer may be made of organic materials, such as resin.
  • the light-emitting structure layer in the embodiment of the present disclosure may include an anode layer, a pixel defining layer, a light-emitting layer, a cathode layer, an encapsulation layer and other structures arranged sequentially on the second planarization layer to form a light-emitting structure layer.
  • Multiple light-emitting devices The formation process of the light-emitting structure layer can adopt conventional process steps, and therefore will not be described in detail here.
  • the display substrate provided by the embodiment of the present disclosure is provided with a first initial signal line whose main part extends along the first direction and a second initial signal line whose main part extends along the second direction.
  • the initial signal line, the first initial signal line and the second initial signal line are connected through vias, so that the initial signal line forms a mesh structure, which not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively
  • the uniformity of the initial voltage in the display substrate is improved, the display uniformity is effectively improved, and the display quality and display quality are improved.
  • the connection part of the second initial signal line At least partially overlapping with the first initial signal line can not only effectively shield the first power line from the impact of the second initial signal line on key nodes in the pixel drive circuit, preventing the initial signal from affecting the potential of key nodes in the pixel drive circuit, but also can fully Utilize the layout space to avoid affecting the light transmittance due to the setting of the second initial signal line.
  • Figure 15 is an equivalent circuit schematic diagram of the second pixel driving circuit of another display substrate of the present disclosure
  • Figure 16 is a structural schematic diagram of another display substrate of the present disclosure; as shown in Figures 15 and 16, embodiments of the present disclosure also provide A display substrate.
  • the virtual pixel area 02 of the display substrate includes at least one pixel missing area 021 and a redundant area 022 arranged adjacent to the pixel missing area 021.
  • the pixel driving circuit in the display substrate includes a first pixel driving circuit located in the display area 01 and a second pixel driving circuit located in the redundant area 022 .
  • the architectures of the first pixel drive circuit and the second pixel drive circuit may be the same or different.
  • the first pixel drive circuit and the second pixel drive circuit both adopt the 7T1C pixel drive circuit architecture; or, the first pixel drive circuit
  • the pixel drive circuit architecture of 7T1C is adopted, and the second pixel drive circuit adopts the pixel drive circuit architecture of 5T1C.
  • the capacitance of the storage capacitor in the first pixel driving circuit is smaller than the storage capacitance in the second pixel driving circuit.
  • the via area 021 is increased
  • the first pixel driving circuit adopts a 7T1C pixel driving circuit architecture
  • the second pixel driving circuit adopts a 5T1C pixel driving circuit architecture. Since the virtual pixel area 02 does not perform display, there is no need to provide a light-emitting device in the redundant area 022 of the virtual pixel area 02. Therefore, compared with the first pixel driving circuit, the second pixel driving circuit lacks the fifth transistor and the fifth transistor for light-emitting control. Sixth transistor.
  • the second pixel driving circuit in the redundant area 022 adopts a 5T1C pixel driving circuit, in which The second transistor T2 and the fourth transistor T4 are connected to the second transistor T2 and the fourth transistor T4 in the first pixel driving circuit, thereby increasing the number of transistors, thus compensating the gate signal.
  • the size of the storage capacitor in the second pixel driving circuit can be designed according to the size of the pixel missing area 021, and the overlapping area of the second initial signal line and the capacitor plate can be changed, for example: the size of the pixel missing area 021 Proportional to the overlapping area of the upper and lower plates of the storage capacitor in the second pixel driving circuit, that is, the larger the pixel missing area 021 is, the overlapping area of the upper and lower plates of the storage capacitor in the second pixel driving circuit is larger than the overlapping area of the upper and lower plates of the storage capacitor in the first pixel driving circuit. The overlapping area of the upper and lower plates of the capacitor is larger.
  • the circuit unit located in the redundant area 022 does not need to be provided with a light-emitting control line.
  • the light-emitting control lines in the circuit units in each unit row where the virtual pixel area 02 is located only extend to the interface between the virtual pixel area 02 and the display area 01 . That is, the first pixel driving circuits located on both sides of the virtual pixel area 02 in each unit row where the virtual pixel area 02 is located use different light-emitting control lines to write light-emitting control signals.
  • the circuit structure of the pixel driving circuit is the same as that in the above embodiment, so the film layer settings in the display area 01 and the circuit unit in the The structural settings are the same as those described above. Therefore, only the circuit units in the dummy pixel area 02 will be described in the following content. That is, the structures included in the so-called display substrate below also refer to the structures in the dummy pixel area 02 .
  • the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged in a direction away from the substrate.
  • the semiconductor layer includes an active layer of a plurality of transistors of the first pixel driving circuit and the second pixel driving circuit.
  • the first conductive layer may include a scanning signal line and gate electrodes of a plurality of transistors
  • the second conductive layer may include a first initial signal line
  • the third conductive layer may include a first power line, a data connection electrode, a first connection electrode and a third
  • the second connecting electrode and the fourth conductive layer may include a data signal line and a second initial signal line.
  • the driving electrode layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer.
  • the first insulating layer is disposed between the substrate and the semiconductor layer
  • the second insulating layer is disposed between the substrate and the semiconductor layer.
  • the insulating layer is provided between the semiconductor layer and the first conductive layer
  • the third insulating layer is provided between the first conductive layer and the second conductive layer
  • the fourth insulating layer is provided between the second conductive layer and the third conductive layer
  • the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the first Semiconductor layer on the insulating layer, as shown in Figure 17.
  • the semiconductor layer of each circuit unit may include a first active layer 11 of the first transistor T1, a second active layer 12 of the second transistor, a third active layer 13 of the third transistor, a fourth The fourth active layer 14 of the transistor and the seventh active layer 17 of the seventh transistor, and the first active layer 11, the second active layer 12, the third active layer 13, the fourth active layer in each circuit unit
  • the source layer 14 and the seventh active layer 17 are an integral structure connected to each other.
  • the first active layer 11 , the second active layer 12 , the fourth active layer 14 and the seventh active layer 17 in the M-th row circuit unit are located in the third active layer 13 of this circuit unit.
  • the first active layer 11 and the seventh active layer 17 are located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13 .
  • the shape of the first active layer 11 may be in the shape of an "n"
  • the shape of the second active layer 12 may be in the shape of a "7”
  • the shape of the third active layer 13 may be in the shape of a "ji”.
  • the shape of the fourth active layer 14 may be a "1" shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer 11 simultaneously serves as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 simultaneously As the first region 12-1 of the second active layer 12, the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14.
  • the third active layer 13 The second area 13-2 simultaneously serves as the second area 12-2 of the second active layer 12.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, and patterning the first conductive film through a patterning process to form a covering semiconductor.
  • the second insulating layer of the layer pattern, and the first conductive layer pattern provided on the second insulating layer, the first conductive layer pattern at least includes: a first scanning signal line 21, a second scanning signal line 22 and a first plate 24 , as shown in Figure 18.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layer located in the redundant area 022 does not need to be provided with a light-emitting control line, and in each circuit unit of the redundant area 022, since the semiconductor layer has no third
  • the fifth active layer and the sixth active layer are arranged, so the area of the first plate in the redundant area 022 is larger than the area of the first plate 24 in the display area 01.
  • the second electrode formed subsequently The area of the plate is also larger than the area of the second plate in the display area 01, so that the storage capacitance in the second pixel driving circuit in the redundant area 022 is larger than the storage capacitance in the first pixel driving circuit in the display area 01. value.
  • the first scanning signal line 21 and the second scanning signal line 22 may mainly extend along the first direction X.
  • the first scanning signal line 21 and the second scanning signal line 22 in the M-th row S2 circuit unit are located on the side of the first plate 24 of this circuit unit away from the M+1-th row circuit unit, and the second scanning signal line 22 is located on The first scanning signal line 21 of this circuit unit is on the side away from the first plate 24 .
  • the first plate 24 may be in a rectangular shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate 24 on the substrate is consistent with the third active layer of the third transistor T3 on the substrate. There are overlapping areas in the orthographic projections.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the area where the first scanning signal line 21 overlaps with the second active layer 12 serves as the gate electrode of the second transistor T2, and the first scanning signal line 21 is provided with a protrusion toward the second scanning signal line 22.
  • the gate block 21-1 has an overlapping area between the orthographic projection of the gate block 21-1 on the substrate and the orthographic projection of the second active layer 12 on the substrate, forming the second transistor T2 with a double-gate structure.
  • the area where the first scanning signal line 21 overlaps the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps the first active layer 11 serves as the gate electrode of the first transistor T1 in the double-gate structure.
  • the area where the second scanning signal line 22 overlaps the seventh active layer 17 serves as the seventh transistor T1 .
  • Gate electrode of transistor T7 is overlapping area between the orthographic projection of the gate block 21-1 on the substrate and the orthographic projection of the second active layer 12 on the substrate, forming the second transistor T2 with a double-gate structure
  • the first conductive layer can be used as a shield to perform a conductive process on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the first to seventh transistors T1 to T7 In the channel region, the semiconductor layer in the area not blocked by the first conductive layer is conductive, that is, the first region and the second region of the first active layer to the seventh active layer are all conductive.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film using a patterning process, and forming a pattern covering the second conductive layer.
  • the second conductive layer pattern at least includes: a first initial signal line 31, a second electrode plate 32, a shield electrode 33 and an electrode. Board connection line 35, as shown in Figure 19.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the first initial signal line 31 may mainly extend along the first direction
  • the second plate 32 serves as the other plate of the storage capacitor and is located between the first scanning signal line 21 of this circuit unit and the first scanning line 21 of the M+1th row.
  • the shielding electrode 33 is located between the second scanning signal line 22 and the first scanning signal line 21 (excluding the main part of the gate block 21-1) of this circuit unit.
  • the shielding electrode 33 is configured to shield the data voltage jump from critical nodes. It avoids the impact of data voltage jumps on the potential of key nodes of the pixel drive circuit and improves the display effect.
  • the outline of the second electrode plate 32 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 32 on the base is the same as the orthographic projection of the first electrode plate 24 on the base.
  • the second electrode plate 32 is provided with an opening 34 , and the opening 34 may be located in the middle of the second electrode plate 32 .
  • the opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located in the opening 34 and exposes the first plate 24 so that the subsequently formed second electrode of the first transistor T1 Connected to the first plate 24.
  • the plate connection line 35 is disposed between the second plates 32 of adjacent circuit units in the first direction X or in the opposite direction to the first direction X, and the first end of the plate connection line 35 is connected to The second plate 32 of this circuit unit is connected, and the second end of the plate connection line 35 extends along the first direction X or the opposite direction of the first direction X, and is connected to the second plate 32 of the adjacent circuit unit, That is, the plate connecting lines 35 are configured to connect the second plates of adjacent circuit units in a unit row to each other.
  • the second plates of multiple circuit units in a unit row can form an integrated structure connected to each other through the plate connection lines 35, and the second plates of the integrated structure can be reused as power signal lines, Ensuring that multiple second electrode plates in a unit row have the same potential is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • each circuit unit is provided with a plurality of via holes.
  • the plurality of via holes at least include: a first via hole V1, a second via hole V2, a fifth via hole V5, a sixth via hole V6, a seventh via hole V6. Via V7, eighth via V8 and ninth via V9, as shown in 20.
  • the first via V1 is located within the opening 34 of the second plate 32 , and the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate.
  • the fourth insulating layer and the third insulating layer in a via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first plate 24 through the via hole.
  • the second via hole V2 is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, and the orthographic projection of the second via hole V2 on the substrate is located within the orthographic projection of the second electrode plate 32 on the substrate.
  • the fourth insulating layer in the second via hole V2 is etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured to allow the subsequently formed first power line to be connected to the second plate 32 through the via hole.
  • the second via hole V2 serving as a power via hole may include multiple, and the plurality of second via holes V2 may be arranged sequentially along the second direction Y to increase the connection between the first power line and the second plate 32 . Connection reliability.
  • the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the fourth active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away, exposing the surface of the first region of the fourth active layer 14 .
  • the fifth via hole V5 is configured to connect a subsequently formed data signal line to the fourth active layer 14 through the via hole.
  • the fifth via hole V5 is called a data writing hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer).
  • the sixth via hole V6 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first active layer through the via hole, and to connect the first electrode of the subsequently formed second transistor T2 to the first active layer through the via hole. Two active layer connections.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate, and the fourth insulating layer, the third insulating layer and the The second insulating layer is etched away, exposing the surface of the first region of the seventh active layer (also the first region of the first active layer).
  • the seventh via hole V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole, and to connect the first electrode of the subsequently formed first transistor T1 to the seventh active layer through the via hole.
  • An active layer connection is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole, and to connect the first electrode of the subsequently formed first transistor T1 to the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the shield electrode 33 on the substrate, and the fourth insulating layer in the eighth via hole V8 is etched away, exposing the shield. the surface of electrode 33.
  • the eighth via hole V8 is configured so that the first power supply line formed later is connected to the shield electrode 33 through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer in the ninth via hole V9 is etched away, The surface of the first initial signal line 31 is exposed.
  • the ninth via hole V9 is configured so that the first electrode of the subsequently formed seventh transistor T7 (also the first electrode of the first transistor T1) is connected to the first initial signal line 31 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive film disposed on the fourth insulating layer.
  • the third conductive layer at least includes: a first power line 41, a data connection electrode 42, a first connection electrode 43, a second connection electrode 44 and a third connection electrode 45, as shown in FIG. 20 .
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the main part of the first power line 41 extends along the second direction Y.
  • the first power line 41 is connected to the second plate 32 through the second via hole V2
  • the first power line 41 is connected to the second plate 32 through the second via hole V2.
  • the via hole V3 is connected to the fifth active layer
  • the eighth via hole V8 is connected to the shield electrode 33 , so that the shield electrode 33 and the second plate 32 have the same potential as the first power line 41 .
  • the shield electrode 33 is connected to the first power line 41, and the orthographic projection of at least part of the shield electrode 33 (such as the protruding portion on the right side of the shield electrode 33) on the substrate is located at the first connection electrode 43 (as the first transistor T1 Between the orthographic projection of the second pole and the first pole of the second transistor T2, that is, the second node N2) on the substrate and the orthographic projection of the subsequently formed data signal line on the substrate, the data voltage jump pair can be effectively shielded.
  • the influence of key nodes in the pixel driving circuit avoids the data voltage jump from affecting the potential of the key nodes in the pixel driving circuit, thereby improving the display effect.
  • the orthographic projection of at least a portion of the shielding electrode 33 on the substrate may at least partially overlap with the orthographic projection of the subsequently formed data signal line on the substrate.
  • the shield electrodes 33 in adjacent circuit units in the first direction X may be connected to each other to reduce resistance.
  • the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, and the data connection electrode 42 is configured to be connected to a subsequently formed data signal line.
  • the first connection electrode 43 extends along the second direction Y, and its first end passes through the sixth via hole V6 and is connected to the second area of the first active layer (also the first area of the second active layer).
  • the second end of the first electrode plate 24 is connected to the first electrode plate 24 through the first via hole V1, so that the first electrode plate 24, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 43 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the first end of the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, and the second end thereof is connected to the first region of the seventh active layer through the seventh via hole V7 ( (also the first region of the first active layer) are connected so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the first initial signal line 31 .
  • the second connection electrode 44 may serve as a first electrode of the seventh transistor T7 and a first electrode of the first transistor T1, and the second connection electrode 44 is configured to connect a second initial signal line formed subsequently.
  • the present disclosure can reduce the number of via holes and the number of transfer electrodes and save wiring space by arranging the second connection electrode to simultaneously connect the seventh active layer, the first initial signal line and the second initial signal line.
  • the first power line 41 of at least one circuit unit may be a polygonal line of unequal width.
  • the first power supply line 41 of each circuit unit may include a first power supply part d1 , a second power supply part d2 , a third power supply part d3 , a fourth power supply part d4 and a fifth power supply part connected in sequence.
  • d5 the first power supply part d1, the third power supply part d3 and the fifth power supply part d5 may be parallel to the second direction Y
  • the second power supply part d2 may be bent towards the first direction X
  • the fourth power supply part d4 may be bent towards the first direction Bend in the opposite direction of direction X.
  • the angle between the second power part d2 and the first power part d1 may be greater than 0° and less than 90°, and the angle between the fourth power part d4 and the third power part d3 may be greater than 0° and less than 90°.
  • the fifth power supply part d5 is provided with a connection part d6 extending in the opposite direction of the first direction X, and the connection part d6 is configured to be connected to the fifth active layer through a third via hole.
  • the first power supply line 41 is arranged in a zigzag line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power supply line and the data signal line.
  • the shapes of the first power lines of each circuit unit may be the same, or may be different.
  • the shape of the first power line in the M-th row and N-th column circuit unit may be the same as the shape of the first power line in the M+1-th row and N+2-th column circuit unit.
  • the shape of the first power line in the circuit unit in row 1 and column N+2 may be the same as the shape of the first power line in the circuit unit in row M and column N+2.
  • the shape of the first power line in the circuit unit in row M and column N+1 may be the same.
  • the shape of a power line can be the same as the shape of the first power line in the M+1th row and N+3th column circuit unit.
  • the shape of the first power line in the M+1th row and N+1th column circuit unit is the same as The shapes of the first power lines in the Mth row and N+3rd column circuit units may be the same.
  • the shape of the second connection electrode in each circuit unit in the Nth column may be the same as the shape of the second connection electrode in each circuit unit in the N+2th column, and the shape of the second connection electrode in each circuit unit in the N+1th column may be the same.
  • the shape of the two connection electrodes may be the same as the shape of the second connection electrode in each circuit unit of the N+3th column.
  • the shape of the second connection electrode in the N+1th and N+3th column circuit units may be a strip shape extending along the second direction Y, and the second connection electrode is configured to pass through the ninth via hole and the seventh via hole. are respectively connected to the first initial signal line and the first region of the seventh active layer.
  • the shape of the second connection electrode 44 in the circuit unit of the Nth column and the N+2th column may include a first portion 44-1 and a second portion 44-2 connected to each other.
  • the first portion 44-1 is along the second
  • the second part 44-2 may be in a rectangular shape extending in the direction Y.
  • the second part 44-2 is provided on the opposite side of the first part 44-1 in the first direction X.
  • the first part 44-1 is configured In order to be connected to the first initial signal line and the first region of the seventh active layer through the ninth via hole and the seventh via hole respectively, the second portion 44-2 is configured to be connected to the subsequently formed second portion through the subsequently formed via hole.
  • the initial signal line is connected, thereby realizing the connection between the first initial signal line and the second initial signal line.
  • the shapes of the third connection electrodes of each circuit unit may be the same, or may be different.
  • the shape of the third connection electrode in the M-th row and N-th column circuit unit may be the same as the shape of the third connection electrode in the M+1-th row and N+2-th column circuit unit.
  • the shape of the third connection electrode in the circuit unit of row 1 and column N can be the same as the shape of the third connection electrode in the circuit unit of row M and column N+2.
  • the shape of the third connection electrode in the circuit unit of row M and column N+1 can be the same.
  • the shape of the three connection electrodes can be the same as the shape of the third connection electrode in the M+1th row and N+3th column circuit unit, and the shape of the third connection electrode in the M+1th row and N+1th column circuit unit can be the same as The shapes of the third connection electrodes in the Mth row and N+3th column circuit units may be the same.
  • the shapes of the data connection electrodes and the first connection electrodes of the respective circuit units may be the same, or may be different.
  • forming the first flat layer pattern may include: coating a first flat film on the substrate on which the foregoing pattern is formed, patterning the first flat film using a patterning process, and forming a covering third conductive layer.
  • the first flat layer is provided with an eleventh via hole V11 and a twelfth via hole V12, as shown in Figures 21 and 22.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the data connection electrode 42 on the substrate, and the first flat layer in the eleventh via hole V11 is removed.
  • the surface of the data connection electrode 42 is exposed, and the eleventh via hole V11 is configured so that a subsequently formed data signal line is connected to the data connection electrode 42 through the via hole.
  • the eleventh via hole V11 may be in a strip shape, and the extension length in the second direction Y in the eleventh via hole V11 is greater than the extension length in the first direction X.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the second connection electrode 44 on the substrate.
  • the first flat layer in the twelfth via hole V12 is removed, exposing the second connection electrode. 44, the twelfth via hole V12 is configured so that the second initial signal line formed subsequently is connected to the second connection electrode 44 through the via hole.
  • all circuit units are provided with an eleventh via hole V11 , and each circuit unit in the Nth column and the N+2th column is provided with a twelfth via hole V12 , and the N+1th column and the Nth column are provided with a twelfth via hole V12 The twelfth via V12 is not provided in each circuit unit in the +3 column.
  • the positions of the eleventh via hole V11 and the thirteenth via hole V13 in each circuit unit may be the same, or may be different.
  • Form a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a pattern on the first planar layer.
  • the fourth conductive layer on the second conductor includes at least: a data signal line 51 and a second initial signal line 52, as shown in Figures 21 and 22.
  • the data signal line 51 is provided in each unit column.
  • the data signal line 51 may extend along the second direction Y, and the data signal line 51 is connected to the data connection electrode 42 through the eleventh via hole V11. Since the data connection electrode 42 is connected to the first area of the fourth active layer through the fifth via hole V5, the data signal line 51 is connected to the first area of the fourth active layer through the data connection electrode 42, and the data signal line 51 is connected to the first area of the fourth active layer through the data connection electrode 42.
  • the second initial signal line 52 is provided in the N-th unit column and the N+2-th unit column, and the second initial signal line 52 of each circuit unit in the unit column is connected to each other.
  • the main part of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second connection electrode 44 through the twelfth via hole V12. Since the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, the second initial signal line 52 is connected to the first initial signal line 31 through the second connection electrode 44, so that the first initial signal Line 31 and second initial signal line 52 have the same potential.
  • This disclosure not only effectively reduces the initial signal line by arranging the first initial signal line 31 whose main part extends along the first direction X and the second initial signal line 52 extending along the second direction Y, so that the initial signal line forms a mesh structure.
  • the resistance of the line reduces the voltage drop of the initial voltage, and effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.
  • the second initial signal line 52 in one circuit unit may include an extension part 521 and a connection part 522.
  • the extension part 521 may be a fold line with a main part extending along the second direction Y
  • the connecting part 522 may be a straight line with a main part extending along the first direction X.
  • the end of the connection portion 522 on a side away from the extension portion 521 may be connected to the second connection electrode 44 through the twelfth via hole V12 .
  • the orthographic projection of at least part of the extension 521 on the substrate is within the range of the orthographic projection of the first power line 41 on the substrate, which not only allows the first power line 41 to effectively shield the second initial signal line 52 pair
  • the influence of key nodes in the pixel drive circuit prevents the initial signal from affecting the potential of the key nodes in the pixel drive circuit, and the layout space can be fully utilized to avoid the impact of the second initial signal line on the light transmittance, thereby improving the display effect.
  • the orthographic projection of at least part of the connection portion 522 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can fully utilize the layout space and avoid affecting the light due to the provision of the second initial signal line.
  • the transmittance improves the display effect.
  • the overlapping area of the orthographic projection of the second plate 32 of the storage capacitor and the extension part 521 on the substrate is the first area; in the circuit unit with the first pixel driving circuit, In the circuit unit of the two-pixel driving circuit, the overlapping area of the orthographic projection of the second plate 32 of the storage capacitor and the extension portion 521 on the substrate is the second area; the area of the first area is smaller than the area of the second area.
  • the display substrate includes i row and j column circuit units; i ⁇ 2; j ⁇ 3, and i and j are integers; the shape of the second initial signal line 52 in the Mth row and Nth column circuit unit is the same as the shape of the second initial signal line 52 in the Mth row and Nth column circuit unit.
  • the shape of the second initial signal line 52 in the circuit unit in the M+1th row and the N+2th column may be the same.
  • the shape of the second initial signal line 52 in the circuit unit in the M+1th row and the Nth column is the same as that in the Mth row and the Nth column.
  • the shapes of the second initial signal lines 52 in the +2 column circuit units may be the same; 1 ⁇ M ⁇ i; 1 ⁇ N ⁇ j, and both M and N are integers.
  • the extension part 521 may include a first initial part c1, a first initial part c1, a first initial part c1, a first initial part c1, a first initial part c1, and an N+2-th column circuit unit connected in sequence along the second direction Y.
  • the second initial part c2 and the third initial part c3, the first initial part c1 and the third initial part c3 can be parallel to the second direction Y, the second initial part c2 can deflect in the opposite direction of the first direction X, the second initial part c2 has a first included angle ⁇ 1 with the second direction Y, and the first included angle ⁇ 1 may be greater than 0° and less than 90°.
  • the extension portion 521 may include a fourth initial portion c4, a fourth initial portion c4, a fourth initial portion c4, and an N-th column connected in sequence along the second direction Y.
  • the fifth initial part c5, the sixth initial part c6, the seventh initial part c7 and the eighth initial part c8, the fourth initial part c4, the sixth initial part c6 and the eighth initial part c8 may be parallel to the second direction Y, and the fifth The initial part c5 may have a first included angle ⁇ 1 with the second direction Y, and the seventh initial part c7 may have a second included angle ⁇ 2 with the second direction Y.
  • the first included angle ⁇ 1 may be greater than 0° and less than 90°.
  • the angle ⁇ 2 can be greater than 0° and less than 90°.
  • the extension direction of the fifth initial portion c5 and the extension direction of the seventh initial portion c7 may be substantially mirror-symmetrical with respect to the first direction X.
  • At least some of the circuit units are provided with data signal lines 51 , and each circuit unit in the Nth column and the N+2th column is provided with a second initial signal line 52 , and the N+1th column and the N+3th column are provided with a second initial signal line 52 The second initial signal line 52 is not provided in each circuit unit in the column.
  • the initial signal line includes a first initial signal line extending along the first direction and a second initial signal line extending along the second direction, but also the second pixel driving circuit located in the redundant area 022
  • the storage capacitance is larger than the storage capacitance of the first pixel driving circuit located in the display area 01, so the problem of uneven display caused by the existence of the dummy pixel area 02 can be alleviated.
  • each film layer of the virtual pixel area 02 are the same as the materials of each film layer of the display area 01 in the above example, so the details are not repeated here.
  • the second initial signal line of the initial signal line is arranged in the fourth conductive layer.
  • the second initial signal line can also be arranged in the third conductive layer, as long as it is ensured
  • the crossed first initial signal line and the second initial signal line may be electrically connected. This setting method can also achieve the above effect, so the description will not be repeated here.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

Abstract

本公开提供一种显示基板及显示装置，属于显示技术领域。本公开的显示基板，具有显示区、虚拟像素区；所述虚拟像素区包括至少一个像素缺失区和冗余区；显示基板包括：基底和驱动电路层；驱动电路层包括多个电路单元；至少一个电路单元包括：像素驱动电路和初始信号线；像素驱动电路包括位于显示区的第一像素驱动电路和位于冗余区的第二像素驱动电路，且第一像素驱动电路的存储电容小于第二像素驱动电路的存储电容；发光结构层设置在驱动电路层背离基底的一侧；多条初始信号线中包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线；第一初始信号线和与之交叉设置的至少部分第二初始信号线电连接。

Description

显示基板及显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示装置。
第一方面，本公开实施例提供一种显示基板，其具有显示区和环绕所述显示区的虚拟像素区；所述虚拟像素区包括至少一个像素缺失区，以及与所述像素缺失区相邻的冗余区；所述显示基板包括：
基底，
驱动电路层，设置在所述基底上，所述驱动电路层包括多个电路单元；至少一个所述电路单元包括：像素驱动电路和初始信号线；所述像素驱动电路包括位于所述显示区的第一像素驱动电路和位于所述冗余区的第二像素驱动电路，且所述第一像素驱动电路的存储电容小于所述第二像素驱动电路的存储电容；
发光结构层，设置在所述驱动电路层背离所述基底的一侧；所述发光结构层包括位于所述显示区的多个发光器件；其中，
所述多条初始信号线中包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线；所述第一方向和所述第二方向交叉，所述第 一初始信号线和与之交叉设置的至少部分第二初始信号线电连接。
其中，所述第一像素驱动电路和所述第二像素驱动电路均包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第七晶体管和所述存储电容；所述第一像素驱动电路还包括第五晶体管和第六晶体管。
其中，所述驱动电路层在沿背离所述基底一侧依次设置半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述半导体层包括所述像素驱动电路中的多个晶体管的有源层；所述第一导电层包括扫描信号线、多个晶体管的栅电极和所述存储电容的第一极板；所述第二导电层包括所述第一初始信号线和所述存储电容的第二极板；所述第四导电层包括所述第二初始信号线。
其中，所述第二初始化信号包括相互连接的延伸部和连接部；所述延伸部沿所述第二方向延伸，所述连接部与所述第一初始信号线连接。
其中，在具有所述第一像素驱动电路的电路单元中，所述存储电容的第二极板与所述延伸部在所述基底上的正投影的重叠区域为第一区域；在具有所述第二像素驱动电路的电路单元中，所述存储电容的第二极板与所述延伸部在所述基底上的正投影的重叠区域为第二区域；所述第一区域的面积小于第二区域的面积。
其中，所述显示基板包括i行j列电路单元；i≥2；j≥3，且i和j为整数；
其中，第M行第N列电路单元中的所述第二初始信号线的形状与第M+1行第N+2列电路单元中的所述第二初始信号线的形状大致相同；第M+1行第N列电路单元中的所述第二初始信号线的形状与第M行第N+2列电路单元中的所述第二初始信号线的形状大致相同；其中，1≤M≤i；1≤N≤j，且M和N均为整数。
其中，在第M行第N列电路单元和第M+1行第N+2列电路单元中，所述延伸部包括沿着第二方向依次连接的第一初始部、第二初始部和第三初始部，所述第一初始部和所述第三初始部沿所述第二方向延伸，且所述第二 初始部的延伸方向与所述第二方向具有第一夹角θ1，0°≤θ1≤90°。
其中，在第M行第N+2列电路单元和第M+1行第N列电路单元中，所述延伸部包括沿着第二方向依次连接的第四初始部、第五初始部、第六初始部、第七初始部和第八初始部，所述第四初始部、所述第六初始部和所述第八初始部沿第二方向延伸，所述第五初始部的延伸方向与所述第二方向具有第二夹角θ2，所述第七初始部的延伸方向与第二方向具有第三夹角θ3，0°≤θ2≤90°，0°≤θ3≤90°。
其中，所述电路单元还包括多条第一电源线，一个所述延伸部与一条所述第一电源线在所述基底上的正投影至少部分重叠；所述连接部与所述第一初始信号线在所述基底上的正投影至少部分重叠。
其中，所述第一电源线为非等宽度的折线；所述第一电源线包括沿着第二方向依次连接的第一电源部、第二电源部、第三电源部、第四电源部和第五电源部；所述第一电源部、第三电源部和第五电源部沿所述第二方向延伸，所述第二电源部和所述第四电源部的延伸方向不同，且均与所述第二方向相交叉。
其中，所述第一电源线位于所述第三导电层。
其中，所述第二导电层还包括屏蔽电极，所述屏蔽电极通过过孔与所述第一电源线电连接。
其中，所述屏蔽电极的至少部分区域在所述基底上的正投影位于所述像素驱动电路的第一晶体管的第二极在所述基底上的正投影之间。
其中，所述电路单元还包括多条数据信号线；所述数据信号线位于所述第四导电层。
其中，所述电路单元还包括多个第二连接电极；所述连接部通过过孔与所述第二连接电极连接；所述第二连接电极通过过孔与所述第一初始信号线连接；所述第二连接电极还通过过孔与所述像素驱动电路中的第一晶体管的第一区和第七晶体管的第二区连接。
其中，所述第二连接电极位于所述第三导电层。
其中，所述第一像素驱动电路中的存储电容的第一极板和第二极板的交叠面积小于所述第二像素驱动电路中的存储电容的第一极板和第二极板。
其中，多个所述电路单元形成沿所述第二方向并排设置的多个单元行和沿所述第一方向并排设置的多个单元列，所述单元行中的所述像素驱动电路沿所述第一方向并排设置；所述单元列中的所述像素驱动电路沿所述第二方向并排设置；
至少一个所述单元列中的各所述电路单元中的第二初始信号线相互连接。
其中，所述多个单元列包括交替设置的第一单元列和第二单元列；所述第二初始化线设置在所述第一单元列中。
第二方面，本公开实施例还一种显示装置，其包括上述任一显示基板。
附图说明
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4a为一种像素驱动电路的等效电路示意图；
图4b为一种像素驱动电路的工作时序图；
图5为本公开实施例的一种显示基板的分布式示意图；
图6a为本公开示例性实施例一种显示基板的结构示意图；
图6b为本公开示例性实施例一种显示基板中初始信号线的示意图；
图7为本公开显示基板形成半导体层图案后的示意图；
图8a为本公开显示基板形成第一导电层图案后的示意图；
图8b为图8a中第一导电层的平面示意图；
图9a为本公开显示基板形成第二导电层图案后的示意图；
图9b为图9a中第二导电层的平面示意图；
图10a为本公开显示基板形成第四绝缘层图案后的示意图；
图10b为图10a中多个过孔的平面示意图；
图11a为本公开显示基板形成第三导电层图案后的示意图；
图11b为图11a中第三导电层的平面示意图；
图12a为本公开显示基板形成第一平坦层图案后的示意图；
图12b为图12a中多个过孔的平面示意图；
图13a为本公开显示基板形成一种第四导电层图案后的示意图；
图13b为图13a中第四导电层的平面示意图；
图14a为本公开显示基板形成第二平坦层图案后的示意图；
图14b为图14a中多个过孔的平面示意图；
图15为本公开另一种显示基板的第二像素驱动电路的等效电路示意图；
图16为本公开另一种显示基板的结构示意图；
图17为本公开另一种显示基板的半导体层的平面示意图；
图18为本公开另一种显示基板的第一导电层的平面示意图；
图19为本公开另一种显示基板的第二导电层的平面示意图；
图20为本公开另一种显示基板的第三导电层的平面示意图；
图21为本公开另一种显示基板的第四导电层的平面示意图；
图22为本公开另一种显示基板的第三导电层和第四导电层的叠层示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描 起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2a和图2b为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和二个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和发光信号线和像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一种示例性实施方式中，四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布，如图2a所示。在另一种示例性实施方式中，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布，如图2b所示。在其它示例性实施方式中，四个子像素可以采用水平并列或竖直并列等方式排列。在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括多个信号线和像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，图3中仅以一个驱动晶体管210和一个存储电容211为例进行示意。每个子像素的发光结构层103可以包括构成发光器件的多个膜层，多个膜层可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在 一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制 极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第二极与初始信号线INIT连接，第七晶体管T7的第一极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线， 第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图4b为一种像素驱动电路的工作时序图。下面通过图4a示例的像素驱动电路的工作过程说明本公开示例性实施例，图4a中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，以OLED为例，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱 动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图5为本公开实施例的一种显示基板的部分示意图，如图5所示，显示基板包括显示区01和虚拟像素区02，其中，虚拟像素区02中设置有至少一个像素缺失区021(图5中以两个为例)，以及与像素缺失区021相邻的冗余区022。过孔区021位置处的衬底基板开设过孔，用以设置摄像头等传感器件，故在像素缺失区021则无显示器件(包括像素驱动电路和发光器件)的设置。冗余区022为了尽可能的避免由于像素缺失区021的设置导致显示面板显示均一性差的问题，通常在冗余区022中设置像素驱动电路，但并不会设置发光器件。尽管如此，由于像素缺失区的设置依旧会造成显示像素缺失区021所在行像素与显示区01其他位置处的显示不均一的问题。例如：由于像素缺失区021的设置，第一扫描信号线S1和第二扫描信号线S2在第一导电层绕线横向连接，初始信号线INIT通过第二导电层绕线横向连接，数据线号线D通过第三导电层绕线竖向连接，从而使得虚拟像素区02左右两侧的第一扫描信号线S1、第二扫描信号线S2信号和初始信号线INIT左右相连接，数据信号线D上下连接。这种绕线使得初始信号线INIT的loading与正常区域loading差异很大，存在过孔区021的初始信号线INIT loading小，导致像素N4结点点位低，最终电流偏小，在显示上即偏暗。
针对上述问题，本公开实施例提供如下技术方案。
第一方面，图6a为本公开示例性实施例一种驱动电路层的结构示意图；如图5和6所示，本公开实施例中提供一种显示基板，其具有显示区01和环绕显示区01的虚拟像素区02。该显示基板包括基底，依次设置在基底上 的驱动电路层和发光结构层。驱动电路层包括多个电路单元；驱动电路层中的多个电路单元可形成沿第二方向并排设置的多个单元行和沿第一方向并排设置的多个单元列。每个单元行中的电路单元在第一方向X并排设置，每个单元列中的电路单元在第二方向Y并排设置。发光结构层包括多个位于显示区01的多个发光器件。
在一些示例中，至少一个电路单元包括像素驱动电路和初始信号线。一个像素驱动电路与一个发光器件电连接，例如：像素驱动电路与发光器件一一对应连接。像素驱动电路可以包括多个晶体管和存储电容。在一些示例中，初始信号线被配置对像素驱动电路中的存储电容和/或发光器件的第一极中的至少一者进行初始化(复位)。
在一些示例中，至少一个电路单元中的初始信号线可以包括主要部分沿第一方向X延伸的第一初始信号线31和主要部分沿第二方向Y延伸的第二初始信号线52，且第一初始信号线31和第二初始信号线52通过过孔连接。本公开中，A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其它方向伸展的长度。
在一些示例中，在至少一个电路单元中，第二初始信号线52可以包括相互连接的延伸部521和连接部522，延伸部521的主要部分沿第二方向Y延伸，连接部522的主要部分沿第一方向X延伸。在示例性实施方式中，连接部远离延伸部521一侧的端部可以通过过孔与第一初始信号线31连接。在一些示例中，至少部分连接部522在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内。在一些示例中，至少部分延伸部521在基底上的正投影位于第一电源线41在基底上的正投影的范围之内。
图6b为本公开示例性实施例一种驱动电路层中初始信号线的示意图。如图6b所示，驱动电路层可以包括多个单元行和多个单元列，第一初始信号线可以设置在每个单元行中。第二初始信号线可以设置在间隔的单元列中，即在第一方向X相邻的两条第二初始信号线之间，间隔有至少一个单元列。在示例性实施方式中，单元行的方向可以是第一方向X，单元列的方 向可以是第二方向Y。
在一些示例中，显示基板中的多个子像素可以包括出射红色光线的红色子像素R、出射蓝色光线的蓝色子像素B、出射绿色光线的第一绿色子像素G1和出射绿色光线的第二绿色子像素G2。红色子像素R可以包括出射红色光线的红色发光器件和与红色发光器件连接的第一电路单元Q1，蓝色子像素B可以包括出射蓝色光线的蓝色发光器件和与蓝色发光器件连接的第二电路单元Q2，第一绿色子像素G1可以包括出射绿色光线的第一绿色发光器件和与第一绿色发光器件连接的第三电路单元Q3，第二绿色子像素G2可以包括出射绿色光线的第二绿色发光器件和与第二绿色发光器件连接的第四电路单元Q4，第一电路单元Q1、第二电路单元Q2、第三电路单元Q3和第四电路单元Q4构成一个电路单元组，至少一个电路单元组中的四个电路单元可以采用正方形(Square)方式排列，即四个电路单元排布在两个单元行和两个单元列中。本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素驱动电路划分的区域。在示例性实施方式中，子像素与电路单元两者的位置可以是对应的，或者，子像素与电路单元两者的位置可以是不对应的。
在一些示例中，多个单元列可以包括第一单元列和第二单元列，第一单元列是指多个第一电路单元Q1和第二电路单元Q2形成的列，第二单元列是指多个第三电路单元Q3和第四电路单元Q4形成的列。第一单元列中的第一电路单元Q1和第二电路单元Q2沿着第二方向Y交替设置，第二单元列中的第三电路单元Q3和第四电路单元Q4沿着第二方向Y交替设置。
在一种示例性实施方式中，第二初始信号线52可以设置在第一单元列中。例如，第N单元列和第N+2单元列为第一单元列，第N+1单元列和第N+3单元列可以为第二单元列，则第二初始信号线52可以设置在第N单元列、第N+2单元列、第N+4单元列、……，第二初始信号线52每隔一第二单元列一重复。
在另一种示例性实施方式中，第二初始信号线52可以设置在第二单元列中。例如，第N单元列和第N+2单元列为第一单元列，第N+1单元列和 第N+3单元列可以为第二单元列，则第二初始信号线52可以设置在第N+1单元列、第N+3单元列、第N+5单元列、……，第二初始信号线52每隔一第一单元列一重复。
在又一种示例性实施方式中，第二初始信号线52可以设置在第一单元列和第二单元列中。
在示例性实施方式中，第N单元列和第N+2单元列可以为第一单元列，第N+1单元列和第N+3单元列可以为第二单元列。第N单元列中，第M行的电路单元为第一电路单元，第M+1行的电路单元为第二电路单元，因而第N单元列中的第一电路单元和第二电路单元沿着第二方向Y交替设置。第N+2单元列中，第M行的电路单元为第二电路单元，第M+1行的电路单元为第一电路单元，因而第N+2单元列中的第二电路单元和第一电路单元沿着第二方向Y交替设置。
在一些示例中，由于第M行第N列电路单元和第M+1行第N+2列电路单元均为第一电路单元，因而第M行第N列电路单元中的第二初始信号线的形状与第M+1行第N+2列电路单元中的第二初始信号线的形状可以相同。由于第M+1行第N列电路单元和第M行第N+2列电路单元均为第二电路单元，因而第M+1行第N列电路单元中的第二初始信号线的形状与第M行第N+2列电路单元中的第二初始信号线的形状可以相同。
在一些示例中，第M行第N列电路单元和第M+1行第N+2列电路单元中，延伸部521可以包括依次连接的第一初始部、第二初始部和第三初始部，第一初始部和第三初始部可以与第二方向Y平行，第二初始部可以与第二方向Y具有第一夹角，第一夹角可以大于0°，小于90°。在示例性实施方式中，第一初始部和/或第三初始部的端部可以连接连接部522。
在一些示例中，第M行第N+2列电路单元和第M+1行第N列电路单元中，延伸部521可以包括依次连接的第四初始部、第五初始部、第六初始部、第七初始部和第八初始部，第四初始部、第六初始部和第八初始部可以与第二方向Y平行，第五初始部可以与第二方向Y具有第一夹角，第七初 始部可以与第二方向Y具有第二夹角，第一夹角可以大于0°，小于90°，第二夹角可以大于0°，小于90°。在示例性实施方式中，第五初始部的延伸方向与第七初始部的延伸方向可以相对于第一方向X大致镜像对称。
在一些示例性中，第二初始信号线52可以设置在间隔的第一单元列或第二单元列中，即在第一方向X相邻的两条第二初始信号线52之间，间隔有三个单元列。例如，第二初始信号线52可以设置在第N单元列、第N+4单元列、第N+8单元列、……，第二初始信号线52每隔一个第一单元列和二个第二单元列一重复。或者，第二初始信号线52可以设置在第N+1单元列、第N+5单元列、第N+9单元列、……，第二初始信号线52每隔二个第一单元列和一个第二单元列一重复。在示例性实施方式中，相邻的第二初始信号线52之间间隔的单元列数没有特殊要求，可以根据需要来设置，本公开在此不做限定。
在示例性实施方式中，在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；半导体层可以包括多个晶体管的有源层，第一导电层可以包括扫描信号线和多个晶体管的栅电极，第二导电层可以包括第一初始信号线31，第三导电层可以包括第一电源线和多个晶体管的第一极和第二极，第四导电层可以包括数据信号线和第二初始信号线52。
在一些示例中，第三导电层还可以包括第二连接电极44。位于第三导电层的第二连接电极44可以通过过孔与位于第二导电层的第一初始信号线31连接，位于第四导电层的第二初始信号线52可以通过过孔与位于第三导电层的第二连接电极44连接。本公开中，第二连接电极可以称为初始连接电极。
在一些示例中，第二连接电极44可以通过过孔与像素驱动电路中第一晶体管的有源层第一区和第七晶体管的有源层第一区连接。
在一些示例中，第二导电层还可以包括屏蔽电极33，第一电源线41通过过孔与屏蔽电极连接。屏蔽电极33的至少部分区域在基底上的正投影位 于数据信号线在基底上的正投影与像素驱动电路中第一晶体管的第二极在基底上的正投影之间。
在一些示例中，驱动电路层还可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容，存储电容可以包括第一极板和第二极板，多个晶体管可以包括第一晶体管至第七晶体管，第三晶体管为驱动晶体管。
在一些示例中，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23、存储电容的第一极板和多个晶体管的栅电极，第二导电层可以包括第一初始信号线31、存储电容的第二极板32、屏蔽电极33和极板连接线35，第三导电层可以包括第一电源线41、数据连接电极、第一连接电极43、第二连接电极44、第三连接电极45和数据连接电极43，第四导电层可以包括数据信号线51、第二初始信号线52和阳极连接电极53。
在一些示例中，驱动电路层可以包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过 同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例中，以八个电路单元(2个单元行4个单元列)为例，驱动电路层的制备过程可以包括如下操作。
(1)形成半导体层图案。在一些示例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图7所示。
在一些示例中，每个电路单元的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构，每个单元列中第M行电路单元的第六有源层16与第M+1行电路单元的第七有源层17相互连接，即每个单元列中相邻电路单元的半导体层为相互连接的一体结构。
在一些示例中，第M行电路单元中的第一有源层11、第二有源层12、第四有源层14和第七有源层17位于本电路单元的第三有源层13远离第M+1行电路单元的一侧，第一有源层11和第七有源层17位于第二有源层12和第四有源层14远离第三有源层13的一侧，第M行电路单元中的第五有源层15和第六有源层16位于第三有源层13靠近第M+1行电路单元的一侧。
在一些示例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在一些示例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一 区11-1同时作为第七有源层17的第一区17-1，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2。在示例性实施例中，第四有源层14的第一区14-1和第五有源层15的第一区15-1单独设置。
(2)形成第一导电层图案。在一些示例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和第一极板24，如图8a和图8b所示，图8b为图8a中第一导电层的平面示意图。在一些示例中，第一导电层可以称为第一栅金属(GATE 1)层。
结合图7至图8b所示，第一扫描信号线21、第二扫描信号线22和发光控制线23可以主要部分沿第一方向X延伸。第M行S2电路单元中的第一扫描信号线21和第二扫描信号线22位于本电路单元的第一极板24远离第M+1行电路单元的一侧，第二扫描信号线22位于本电路单元的第一扫描信号线21远离第一极板24的一侧，发光控制线23可以位于本电路单元的第一极板24靠近第M+1行电路单元的一侧。
在一些示例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在一些示例中，第一扫描信号线21与第二有源层12相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二有源层12在基底上的正投影存在重叠区域，形成双栅结构的第二晶体管T2。第一扫描 信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极。第二扫描信号线22与第一有源层11相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，发光控制线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六有源层16相重叠的区域作为第六晶体管T6的栅电极。
在一些示例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：第一初始信号线31、第二极板32、屏蔽电极33和极板连接线35，如图9a和图9b所述，图9b为图9a中第二导电层的平面示意图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
结合图7至图9b所示，第一初始信号线31可以主要部分沿第一方向X延伸，第M行电路单元中的第一初始信号线31位于本电路单元的第二扫描信号线22远离第M+1行电路单元的一侧，第二极板32作为存储电容的另一个极板，位于本电路单元的第一扫描信号线21和发光控制线23之间，屏蔽电极33位于本电路单元的第二扫描信号线22与第一扫描信号线21(不包含栅极块21-1的主要部分)之间，屏蔽电极33配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在一些示例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域，第一极板24和第二极板32构成像素驱动电路的存储电容。 第二极板32上设置有开口34，开口34可以位于第二极板32的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第一方向X上或第一方向X的反方向上相邻电路单元的第二极板32之间，极板连接线35的第一端与本电路单元的第二极板32连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻电路单元的第二极板32连接，即极板连接线35配置为使一单元行上相邻电路单元的第二极板相互连接。在示例性实施例中，通过极板连接线35可以使一单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如图10a和图10b所示，图10b为图10a中多个过孔的平面示意图。
结合图7至图10b所示，第一过孔V1位于第二极板32的开口34内，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一极板24连接。
在一些示例中，第二过孔V2位于第二极板32在基底上的正投影的范围 之内，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在一些示例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，以增加第一电源线与第二极板32的连接可靠性。
在一些示例中，第三过孔V3在基底上的正投影位于第五有源层在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在一些示例中，第四过孔V4在基底上的正投影位于第六有源层在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在一些示例中，第五过孔V5在基底上的正投影位于第四有源层在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在一些示例中，第六过孔V6在基底上的正投影位于第二有源层在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在一些示例中，第七过孔V7在基底上的正投影位于第七有源层在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接，以及使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在一些示例中，第八过孔V8在基底上的正投影位于屏蔽电极33在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。
在一些示例中，第九过孔V9在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面。第九过孔V9配置为使后续形成的第七晶体管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与第一初始信号线31连接。
(5)形成第三导电层图案。在一些示例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据连接电极42、第一连接电极43、第二连接电极44和第三连接电极45，如图11a和图11b所示，图11b为图11a中第三导电层的平面示意图。在在一些示例中，第三导电层可以称为第一源漏金属(SD1)层。
结合图7至图11b所示，第一电源线41主要部分沿着第二方向Y延伸，第一电源线41一方面通过第二过孔V2与第二极板32连接，另一方面通过第三过孔V3与第五有源层连接，又一方面通过第八过孔V8与屏蔽电极33连接，使屏蔽电极33和第二极板32具有与第一电源线41相同的电位。由于屏蔽电极33与第一电源线41连接，且屏蔽电极33的至少部分区域(如屏蔽电极33右侧的突出部)在基底上的正投影位于第一连接电极43(作为 第一晶体管T1的第二极和第二晶体管T2的第一极，即第二节点N2)在基底上的正投影与后续形成的数据信号线在基底上的正投影之间，可以有效屏蔽了数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在一些示例中，屏蔽电极33的至少部分区域在基底上的正投影可以与后续形成的数据信号线在基底上的正投影至少部分重叠。在示例性实施例中，第一方向X上相邻电路单元中的屏蔽电极33可以相互连接，以降低电阻。
在一些示例中，数据连接电极42通过第五过孔V5与第四有源层的第一区连接，数据连接电极42配置为与后续形成的数据信号线连接。
在一些示例中，第一连接电极43沿着第二方向Y延伸，其第一端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极43可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在一些示例中，第二连接电极44的第一端通过第九过孔V9与第一初始信号线31连接，其第二端通过第七过孔V7与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与第一初始信号线31相同的电位。在示例性实施例中，第二连接电极44可以作为第七晶体管T7的第一极和第一晶体管T1的第一极，第二连接电极配置为连接后续形成的第二初始信号线。本公开通过设置第二连接电极同时连接第七有源层、第一初始信号线和第二初始信号线，可以减小过孔的数量和转接电极的数量，节约布线空间。
在一些示例中，第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极45 可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第三连接电极45配置为与后续形成的阳极连接电极连接。
在一些示例中，至少一个电路单元的第一电源线41可以为非等宽度的折线。沿着第二方向Y，每个电路单元的第一电源线41可以包括依次连接的第一电源部d1、第二电源部d2、第三电源部d3、第四电源部d4和第五电源部d5，第一电源部d1、第三电源部d3和第五电源部d5可以与第二方向Y平行，第二电源部d2可以向着第一方向X弯折，第四电源部d4可以向着第一方向X的反方向弯折。第二电源部d2与第一电源部d1之间的夹角可以大于0°且小于90°，第四电源部d4与第三电源部d3之间的夹角可以大于0°且小于90°。第五电源部d5设置有向着第一方向X的反方向延伸的连接部d6，连接部d6配置为通过通过第三过孔与第五有源层连接。第一电源线41采用折线设置，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在一些示例中，各个电路单元的第一电源线的形状可以相同，或者可以不同。在示例性实施例中，第M行第N列电路单元中的第一电源线的形状与第M+1行第N+2列电路单元中的第一电源线的形状可以相同，第M+1行第N列电路单元中的第一电源线的形状与第M行第N+2列电路单元中的第一电源线的形状可以相同，第M行第N+1列电路单元中的第一电源线的形状与第M+1行第N+3列电路单元中的第一电源线的形状可以相同，第M+1行第N+1列电路单元中的第一电源线的形状与第M行第N+3列电路单元中的第一电源线的形状可以相同。
在一些示例中，第N列各个电路单元中的第二连接电极的形状与第N+2列各个电路单元中的第二连接电极的形状可以相同，第N+1列各个电路单元中的第二连接电极的形状与第N+3列各个电路单元中的第二连接电极的形状可以相同。第N+1列和第N+3列电路单元中的第二连接电极的形状可以为沿着第二方向Y延伸的条形状，第二连接电极配置为通过第九过孔和第七过孔分别与第一初始信号线和第七有源层的第一区连接。第N列和第N+2列电路单元中的第二连接电极44的形状可以包括相互连接的第一部 44-1和第二部44-2，第一部44-1为沿着第二方向Y延伸的条形状，第二部44-2可以为矩形状，第二部44-2设置在第一部44-1第一方向X的反方向的一侧，第一部44-1配置为通过第九过孔和第七过孔分别与第一初始信号线和第七有源层的第一区连接，第二部44-2配置为通过后续形成的过孔与后续形成的第二初始信号线连接，从而实现第一初始信号线与第二初始信号线的连接。
在一些示例中，各个电路单元的第三连接电极的形状可以相同，或者可以不同。在示例性实施例中，第M行第N列电路单元中的第三连接电极的形状与第M+1行第N+2列电路单元中的第三连接电极的形状可以相同，第M+1行第N列电路单元中的第三连接电极的形状与第M行第N+2列电路单元中的第三连接电极的形状可以相同，第M行第N+1列电路单元中的第三连接电极的形状与第M+1行第N+3列电路单元中的第三连接电极的形状可以相同，第M+1行第N+1列电路单元中的第三连接电极的形状与第M行第N+3列电路单元中的第三连接电极的形状可以相同。
在示例性实施例中，各个电路单元的数据连接电极和第一连接电极的形状可以相同，或者可以不同。
(6)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦层上设置有第十一过孔V11、第十二过孔V12和第十三过孔V13，如图12a和图12b所示，图12b为图12a中多个过孔的平面示意图。
结合图7至图12b所示，第十一过孔V11在基底上的正投影位于数据连接电极42在基底上的正投影的范围之内，第十一过孔V11内的第一平坦层被去掉，暴露出数据连接电极42的表面，第十一过孔V11配置为使后续形成的数据信号线通过该过孔与数据连接电极42连接。
在一些示例中，第十一过孔V11可以是条形状，第十一过孔V11中第二方向Y的延伸长度大于第一方向X的延伸长度。本公开通过将第十一过 孔V11设置沿着第二方向Y延伸的条形状，可以减小第十一过孔V11第一方向X上的宽度，可以减少后续形成的阳极的倾斜程度。
第十二过孔V12在基底上的正投影位于第二连接电极44在基底上的正投影的范围之内，第十二过孔V12内的第一平坦层被去掉，暴露出第二连接电极44的表面，第十二过孔V12配置为使后续形成的第二初始信号线通过该过孔与第二连接电极44连接。
第十三过孔V13在基底上的正投影位于第三连接电极45在基底上的正投影的范围之内，第十三过孔V13内的第一平坦层被去掉，暴露出第三连接电极45的表面，第十三过孔V13配置为使后续形成的阳极连接电极通过该过孔与第三连接电极45连接。
在一些示例中，所有电路单元均设置有第十一过孔V11和第十三过孔V13，第N列和第N+2列中的各个电路单元中设置有第十二过孔V12，第N+1列和第N+3列中的各个电路单元中没有设置第十二过孔V12。
在示例性实施例中，各个电路单元中的第十一过孔V11和第十三过孔V13的位置可以相同，或者可以不同。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，第四导电层至少包括：数据信号线51、第二初始信号线52和阳极连接电极53，如图13a和图13b所示，图13b为图13a中第四导电层的平面示意图。
结合图7至图13b所示，数据信号线51设置在每个单元列中。数据信号线51可以沿着第二方向Y延伸，数据信号线51通过第十一过孔V11与数据连接电极42连接。由于数据连接电极42通过第五过孔V5与第四有源层的第一区连接，因而实现了数据信号线51通过数据连接电极42与第四有源层的第一区连接，将数据信号写入第四晶体管T4。
在示例性实施例中，第二初始信号线52设置在第N单元列和第N+2单元列中，单元列中每个电路单元的第二初始信号线52相互连接。第二初始 信号线52主要部分沿着第二方向Y延伸，第二初始信号线52通过第十二过孔V12与第二连接电极44连接。由于第二连接电极44通过第九过孔V9与第一初始信号线31连接，因而实现了第二初始信号线52通过第二连接电极44与第一初始信号线31连接，使得第一初始信号线31和第二初始信号线52具有相同的电位。本公开通过设置主要部分沿第一方向X延伸的第一初始信号线31和沿着第二方向Y延伸的第二初始信号线52，使得初始信号线形成网状结构，不仅有效降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在一些示例中，阳极连接电极53设置在至少部分电路单元中。阳极连接电极53通过第十三过孔V13与第三连接电极45连接。由于第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了阳极连接电极53通过第三连接电极45与第六有源层的第二区(也是第七有源层的第二区)连接。
在一些示例中，一个电路单元中的第二初始信号线52可以包括延伸部521和连接部522。延伸部521可以为主要部分沿着第二方向Y延伸的折线，连接部522可以为主要部分沿着第一方向X延伸的直线。在示例性实施例中，连接部522远离延伸部521一侧的端部可以通过第十二过孔V12与第二连接电极44连接。
在一些示例中，至少部分延伸部521在基底上的正投影位于第一电源线41在基底上的正投影的范围之内，不仅可以使得第一电源线41有效屏蔽第二初始信号线52对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在一些示例中，至少部分连接部522在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在一些示例中，第M行第N列电路单元中的第二初始信号线52的形状与第M+1行第N+2列电路单元中的第二初始信号线52的形状可以相同，第M+1行第N列电路单元中的第二初始信号线52的形状与第M行第N+2列电路单元中的第二初始信号线52的形状可以相同。
在一些示例中，在第M行第N列电路单元和第M+1行第N+2列电路单元中，延伸部521可以包括沿着第二方向Y依次连接的第一初始部c1、第二初始部c2和第三初始部c3，第一初始部c1和第三初始部c3可以与第二方向Y平行，第二初始部c2可以向着第一方向X的反方向偏转，第二初始部c2与第二方向Y具有第一夹角θ1，第一夹角θ1可以大于0°，小于90°。
在一些示例中，在第M行第N+2列电路单元和第M+1行第N列电路单元中，延伸部521可以包括沿着第二方向Y依次连接的第四初始部c4、第五初始部c5、第六初始部c6、第七初始部c7和第八初始部c8，第四初始部c4、第六初始部c6和第八初始部c8可以与第二方向Y平行，第五初始部c5可以与第二方向Y具有第二夹角θ2，第七初始部c7可以与第二方向Y具有第三夹角θ3，第二夹角θ2可以大于0°，小于90°，第三夹角θ3可以大于0°，小于90°。
在一些示例中，第五初始部c5的延伸方向与第七初始部c7的延伸方向可以相对于第一方向X大致镜像对称。
在一些示例中，至少部分电路单元设置有数据信号线51和阳极连接电极53，第N列和第N+2列中的各个电路单元中设置有第二初始信号线52，第N+1列和第N+3列中的各个电路单元中没有设置第二初始信号线52。
在一些示例中，第M行第N列电路单元中的阳极连接电极的形状与第M+1行第N+2列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为矩形状。第M+1行第N列电路单元中的阳极连接电极的形状与第M行第N+2列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为哑铃形状。第M行第N+1列电路单元中的阳极连接电 极的形状与第M+1行第N+3列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为矩形状。第M+1行第N+1列电路单元中的阳极连接电极的形状与第M行第N+3列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为矩形状。
(8)形成第二平坦层图案。在示例性实施例中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有第十四过孔V14，如图14a和图14b所示，图14b为图14a中多个过孔的平面示意图。
结合图7至图14b所示，第十四过孔V14在基底上的正投影位于阳极连接电极53在基底上的正投影的范围之内，第十四过孔V14内的第二平坦层被去掉，暴露出阳极连接电极53的表面，第十四过孔V14配置为使后续形成的阳极通过该过孔与阳极连接电极53连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
在一些示例中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备，也即在驱动电路层背离基底的一侧形成发光结构层的发光器件。其中，发光器件的制备工艺可以采用现有技术中的任一方法，故在此不再赘述。
在一些示例中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、 聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在一些示例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。第一平坦层和第二平坦层可以采用有机材料，如树脂等。
另外，本公开实施例中的发光结构层，其可以包括依次设置在第二平坦化层之上的阳极层、像素限定层、发光层、阴极层、封装层等结构，以形成发光结构层的多个发光器件。对于发光结构层的形成工艺可以采用常规的工艺步骤，故在此不再详细赘述。
从以上描述的显示基板的结构以及制备过程可以看出，本公开实施例提供的显示基板，通过设置主要部分沿第一方向延伸的第一初始信号线和主要部分沿第二方向延伸的第二初始信号线，第一初始信号线和第二初始信号线通过过孔连接，使得初始信号线形成网状结构，不仅有效降低了初始信号线 的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开实施例通过将第一初始信号线和第二初始信号线设置在不同的导电层，且第二初始信号线的延伸部与第一电源线至少部分重叠，第二初始信号线的连接部与第一初始信号线至少部分重叠，不仅可以使得第一电源线有效屏蔽第二初始信号线对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率。
图15为本公开另一种显示基板的第二像素驱动电路的等效电路示意图；图16为本公开另一种显示基板的结构示意图；如图15和16所示，本公开实施例还提供一种显示基板，该显示基板的虚拟像素区02包括至少一个像素缺失区021，以及与像素缺失区021相邻设置的冗余区022。该显示基板中的像素驱动电路包括位于显示区01的第一像素驱动电路和位于冗余区022的第二像素驱动电路。其中，第一像素驱动电路和第二像素驱动电路的架构可以相同也可以不同，例如：第一像素驱动电路和第二像素驱动电路均采用7T1C的像素驱动电路架构；或者，第一像素驱动电路采用7T1C的像素驱动电路架构，第二像素驱动电路均采用5T1C的像素驱动电路架构。特别的是，第一像素驱动电路中的存储电容的电容小于第二像素驱动电路中的存储电容。
在本公开实施例中，由于位于冗余区022的第二像素驱动电路中的存储电容比位于显示区01中的第一像素驱动电路中的存储电容大，因此，增大过孔区021所在单元行的初始信号线与其他膜层的交叠电容，从而补偿初始信号，进而可以有效的缓解过孔区021所在单元行的初始信号线的压降小于正常显示区01(无过孔区021)中的单元行的初始信号线的压降，所导致的低灰阶显示不均匀的问题。
在一些示例中，如图15所示，第一像素驱动电路采用7T1C的像素驱动电路架构，第二像素驱动电路采用5T1C的像素驱动电路架构。由于虚拟像素区02不进行显示，因此在虚拟像素区02的冗余区022的无需设置发光 器件，故第二像素驱动电路相较第一像素驱动电路少了用于发光控制的第五晶体管和第六晶体管。在一些示例中，由于第二像素驱动电路中相较第一像素驱动电路少第五晶体管和第六晶体管，也即冗余区022中的第二像素驱动电路采用5T1C的像素驱动电路，其中的第二晶体管T2和第四晶体管T4与第一像素驱动电路中的第二晶体管T2和第四晶体管T4相连，增加了晶体管数量，因此补偿了栅极信号。
在一些示例中，可以根据像素缺失区021的尺寸大小，设计第二像素驱动电路中的存储电容的大小，改变第二初始信号线与电容极板的交叠面积，例如：像素缺失区的尺寸正比于第二像素驱动电路中存储电容上下极板的交叠面积，也即像素缺失区021越大第二像素驱动电路中的存储电容上下极板的交叠面积比第一像素驱动电路中存储电容上下极板的交叠面积大的更多。
需要说明的是，由于第二像素驱动电路中并无第五晶体管和第六晶体管，因此位于冗余区022的电路单元无需设置发光控制线。相应的，虚拟像素区02所在各单元行中的电路单元中的发光控制线仅延伸至虚拟像素区02和显示区01的交界位置。也即，虚拟像素区02所在各单元行中分设在虚拟像素区02两侧的第一像素驱动电路采用不同的发光控制线进行发光控制信号写入。另外，由于在显示区01中像素驱动电路采用7T1C的第一像素驱动电路，该像素驱动电路的电路与上述实施例中的结构相同，故对于显示区01中的膜层设置、电路单元中的结构设置均与上述结构相同。因此，在下述内容中仅对虚拟像素区02中电路单元进行说明。也即，下述所谓的显示基板所包含的结构也均指虚拟像素区02中的结构。
在一些示例中，显示基板包括沿背离基底方向依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。半导体层包括第一像素驱动电路的和第二像素驱动电路的多个晶体管的有源层。第一导电层可以包括扫描信号线和多个晶体管的栅电极，第二导电层可以包括第一初始信号线，第三导电层可以包括第一电源线、数据连接电极、第一连接电极和第二连接电极，第四导电层可以包括数据信号线和第二初始信号线。
在一些示例中，驱动电极层可以包括第一绝缘层、第二绝缘层、第三绝 缘层、第四绝缘层好第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
为了更清楚本公开实施例中的显示基板结构，以下对虚拟像素区02的驱动电路层的制备过程进行说明。
(1)形成半导体层图案。在一些示例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图17所示。
在一些示例中，每个电路单元的半导体层可以包括第一晶体管T1的第一有源层11、第二晶体管的第二有源层12、第三晶体管的第三有源层13、第四晶体管的第四有源层14和第七晶体管的第七有源层17，且每个电路单元中第一有源层11、第二有源层12、第三有源层13、第四有源层14和第七有源层17为相互连接的一体结构。
在一些示例中，第M行电路单元中的第一有源层11、第二有源层12、第四有源层14和第七有源层17位于本电路单元的第三有源层13远离第M+1行电路单元的一侧，第一有源层11和第七有源层17位于第二有源层12和第四有源层14远离第三有源层13的一侧。
在一些示例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形。
在一些示例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一区11-1同时作为第七有源层17的第一区17-1，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2，第三有源层13的第二区13-2同时作为 第二有源层12的第二区12-2。
(2)形成第一导电层图案。在一些示例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22和第一极板24，如图18所示。在一些示例中，第一导电层可以称为第一栅金属(GATE 1)层。
可以看出的是，位于冗余区022的第一导电层相较于显示区01的第一导电层，无需设置发光控制线，且冗余区022的每个电路单元中由于半导体层无第五有源层和第六有源层的设置，故冗余区022中的第一极板的面积大于显示区01中的第一极板24的面积，同理，后续所形成的第二极板的面积也同样大于显示区01第二极板的面积，以实现冗余区022中的第二像素驱动电路中的存储电容大于显示区01中的第一像素驱动电路中的存储电容的容值。
结合图15-18所示，第一扫描信号线21、第二扫描信号线22可以主要部分沿第一方向X延伸。第M行S2电路单元中的第一扫描信号线21和第二扫描信号线22位于本电路单元的第一极板24远离第M+1行电路单元的一侧，第二扫描信号线22位于本电路单元的第一扫描信号线21远离第一极板24的一侧。
在一些示例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在一些示例中，第一扫描信号线21与第二有源层12相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二有源层12在基底上的正投影存在重叠区域，形成双栅结构的第二晶体管T2。第一扫描 信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极。第二扫描信号线22与第一有源层11相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与第七有源层17相重叠的区域作为第七晶体管T7的栅电极。
在一些示例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在一些示例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：第一初始信号线31、第二极板32、屏蔽电极33和极板连接线35，如图19所示。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
结合图15-19所示，第一初始信号线31可以主要部分沿第一方向X延伸，第M行电路单元中的第一初始信号线31位于本电路单元的第二扫描信号线22远离第M+1行电路单元的一侧，第二极板32作为存储电容的另一个极板，位于本电路单元的第一扫描信号线21和第M+1行的第一扫描线21之间，屏蔽电极33位于本电路单元的第二扫描信号线22与第一扫描信号线21(不包含栅极块21-1的主要部分)之间，屏蔽电极33配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在一些示例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域，第一极板24和第二极板32构成像素驱动电路的存储电容。第二极板32上设置有开口34，开口34可以位于第二极板32的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极 板24的第三绝缘层，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第一方向X上或第一方向X的反方向上相邻电路单元的第二极板32之间，极板连接线35的第一端与本电路单元的第二极板32连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻电路单元的第二极板32连接，即极板连接线35配置为使一单元行上相邻电路单元的第二极板相互连接。在示例性实施例中，通过极板连接线35可以使一单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如20所示。
结合图15-20所示，第一过孔V1位于第二极板32的开口34内，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在一些示例中，第二过孔V2位于第二极板32在基底上的正投影的范围之内，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板32 连接。在一些示例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，以增加第一电源线与第二极板32的连接可靠性。
在一些示例中，第五过孔V5在基底上的正投影位于第四有源层在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层14的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层14连接，第五过孔V5称为数据写入孔。
在一些示例中，第六过孔V6在基底上的正投影位于第二有源层在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在一些示例中，第七过孔V7在基底上的正投影位于第七有源层在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接，以及使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在一些示例中，第八过孔V8在基底上的正投影位于屏蔽电极33在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。
在一些示例中，第九过孔V9在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面。第九过孔V9配置为使后续形成的第七晶体 管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与第一初始信号线31连接。
(5)形成第三导电层图案。在一些示例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据连接电极42、第一连接电极43、第二连接电极44和第三连接电极45，如图20所示。在在一些示例中，第三导电层可以称为第一源漏金属(SD1)层。
结合图15-20所示，第一电源线41主要部分沿着第二方向Y延伸，第一电源线41一方面通过第二过孔V2与第二极板32连接，另一方面通过第三过孔V3与第五有源层连接，又一方面通过第八过孔V8与屏蔽电极33连接，使屏蔽电极33和第二极板32具有与第一电源线41相同的电位。由于屏蔽电极33与第一电源线41连接，且屏蔽电极33的至少部分区域(如屏蔽电极33右侧的突出部)在基底上的正投影位于第一连接电极43(作为第一晶体管T1的第二极和第二晶体管T2的第一极，即第二节点N2)在基底上的正投影与后续形成的数据信号线在基底上的正投影之间，可以有效屏蔽了数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在一些示例中，屏蔽电极33的至少部分区域在基底上的正投影可以与后续形成的数据信号线在基底上的正投影至少部分重叠。在示例性实施例中，第一方向X上相邻电路单元中的屏蔽电极33可以相互连接，以降低电阻。
在一些示例中，数据连接电极42通过第五过孔V5与第四有源层的第一区连接，数据连接电极42配置为与后续形成的数据信号线连接。
在一些示例中，第一连接电极43沿着第二方向Y延伸，其第一端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管 T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极43可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在一些示例中，第二连接电极44的第一端通过第九过孔V9与第一初始信号线31连接，其第二端通过第七过孔V7与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与第一初始信号线31相同的电位。在示例性实施例中，第二连接电极44可以作为第七晶体管T7的第一极和第一晶体管T1的第一极，第二连接电极配置为连接后续形成的第二初始信号线。本公开通过设置第二连接电极同时连接第七有源层、第一初始信号线和第二初始信号线，可以减小过孔的数量和转接电极的数量，节约布线空间。
在一些示例中，至少一个电路单元的第一电源线41可以为非等宽度的折线。沿着第二方向Y，每个电路单元的第一电源线41可以包括依次连接的第一电源部d1、第二电源部d2、第三电源部d3、第四电源部d4和第五电源部d5，第一电源部d1、第三电源部d3和第五电源部d5可以与第二方向Y平行，第二电源部d2可以向着第一方向X弯折，第四电源部d4可以向着第一方向X的反方向弯折。第二电源部d2与第一电源部d1之间的夹角可以大于0°且小于90°，第四电源部d4与第三电源部d3之间的夹角可以大于0°且小于90°。第五电源部d5设置有向着第一方向X的反方向延伸的连接部d6，连接部d6配置为通过通过第三过孔与第五有源层连接。第一电源线41采用折线设置，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在一些示例中，各个电路单元的第一电源线的形状可以相同，或者可以不同。在示例性实施例中，第M行第N列电路单元中的第一电源线的形状与第M+1行第N+2列电路单元中的第一电源线的形状可以相同，第M+1行第N列电路单元中的第一电源线的形状与第M行第N+2列电路单元中的第一电源线的形状可以相同，第M行第N+1列电路单元中的第一电源线的形状与第M+1行第N+3列电路单元中的第一电源线的形状可以相同，第 M+1行第N+1列电路单元中的第一电源线的形状与第M行第N+3列电路单元中的第一电源线的形状可以相同。
在一些示例中，第N列各个电路单元中的第二连接电极的形状与第N+2列各个电路单元中的第二连接电极的形状可以相同，第N+1列各个电路单元中的第二连接电极的形状与第N+3列各个电路单元中的第二连接电极的形状可以相同。第N+1列和第N+3列电路单元中的第二连接电极的形状可以为沿着第二方向Y延伸的条形状，第二连接电极配置为通过第九过孔和第七过孔分别与第一初始信号线和第七有源层的第一区连接。第N列和第N+2列电路单元中的第二连接电极44的形状可以包括相互连接的第一部44-1和第二部44-2，第一部44-1为沿着第二方向Y延伸的条形状，第二部44-2可以为矩形状，第二部44-2设置在第一部44-1第一方向X的反方向的一侧，第一部44-1配置为通过第九过孔和第七过孔分别与第一初始信号线和第七有源层的第一区连接，第二部44-2配置为通过后续形成的过孔与后续形成的第二初始信号线连接，从而实现第一初始信号线与第二初始信号线的连接。
在一些示例中，各个电路单元的第三连接电极的形状可以相同，或者可以不同。在示例性实施例中，第M行第N列电路单元中的第三连接电极的形状与第M+1行第N+2列电路单元中的第三连接电极的形状可以相同，第M+1行第N列电路单元中的第三连接电极的形状与第M行第N+2列电路单元中的第三连接电极的形状可以相同，第M行第N+1列电路单元中的第三连接电极的形状与第M+1行第N+3列电路单元中的第三连接电极的形状可以相同，第M+1行第N+1列电路单元中的第三连接电极的形状与第M行第N+3列电路单元中的第三连接电极的形状可以相同。
在示例性实施例中，各个电路单元的数据连接电极和第一连接电极的形状可以相同，或者可以不同。
(6)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦 层上设置有第十一过孔V11和第十二过孔V12，如图21和22所示。
结合21和22所示，第十一过孔V11在基底上的正投影位于数据连接电极42在基底上的正投影的范围之内，第十一过孔V11内的第一平坦层被去掉，暴露出数据连接电极42的表面，第十一过孔V11配置为使后续形成的数据信号线通过该过孔与数据连接电极42连接。
在一些示例中，第十一过孔V11可以是条形状，第十一过孔V11中第二方向Y的延伸长度大于第一方向X的延伸长度。
第十二过孔V12在基底上的正投影位于第二连接电极44在基底上的正投影的范围之内，第十二过孔V12内的第一平坦层被去掉，暴露出第二连接电极44的表面，第十二过孔V12配置为使后续形成的第二初始信号线通过该过孔与第二连接电极44连接。
在一些示例中，所有电路单元均设置有第十一过孔V11，第N列和第N+2列中的各个电路单元中设置有第十二过孔V12，第N+1列和第N+3列中的各个电路单元中没有设置第十二过孔V12。
在示例性实施例中，各个电路单元中的第十一过孔V11和第十三过孔V13的位置可以相同，或者可以不同。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，第四导电层至少包括：数据信号线51、第二初始信号线52，如图21和22所示。
结合图15-22所示，数据信号线51设置在每个单元列中。数据信号线51可以沿着第二方向Y延伸，数据信号线51通过第十一过孔V11与数据连接电极42连接。由于数据连接电极42通过第五过孔V5与第四有源层的第一区连接，因而实现了数据信号线51通过数据连接电极42与第四有源层的第一区连接，将数据信号写入第四晶体管T4。
在示例性实施例中，第二初始信号线52设置在第N单元列和第N+2单元列中，单元列中每个电路单元的第二初始信号线52相互连接。第二初始 信号线52主要部分沿着第二方向Y延伸，第二初始信号线52通过第十二过孔V12与第二连接电极44连接。由于第二连接电极44通过第九过孔V9与第一初始信号线31连接，因而实现了第二初始信号线52通过第二连接电极44与第一初始信号线31连接，使得第一初始信号线31和第二初始信号线52具有相同的电位。本公开通过设置主要部分沿第一方向X延伸的第一初始信号线31和沿着第二方向Y延伸的第二初始信号线52，使得初始信号线形成网状结构，不仅有效降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在一些示例中，一个电路单元中的第二初始信号线52可以包括延伸部521和连接部522。延伸部521可以为主要部分沿着第二方向Y延伸的折线，连接部522可以为主要部分沿着第一方向X延伸的直线。在示例性实施例中，连接部522远离延伸部521一侧的端部可以通过第十二过孔V12与第二连接电极44连接。
在一些示例中，至少部分延伸部521在基底上的正投影位于第一电源线41在基底上的正投影的范围之内，不仅可以使得第一电源线41有效屏蔽第二初始信号线52对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在一些示例中，至少部分连接部522在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在一些示例中，在具有所述第一像素驱动电路的电路单元中，存储电容的第二极板32与所述延伸部521在基底上的正投影的重叠区域为第一区域；在具有第二像素驱动电路的电路单元中，存储电容的第二极板32与所述延伸部521在基底上的正投影的重叠区域为第二区域；第一区域的面积小于第二区域的面积。
在一些示例中，显示基板包括i行j列电路单元；i≥2；j≥3，且i和j为整数；第M行第N列电路单元中的第二初始信号线52的形状与第M+1行第N+2列电路单元中的第二初始信号线52的形状可以相同，第M+1行第N列电路单元中的第二初始信号线52的形状与第M行第N+2列电路单元中的第二初始信号线52的形状可以相同；1≤M≤i；1≤N≤j，且M和N均为整数。
在一些示例中，在第M行第N列电路单元和第M+1行第N+2列电路单元中，延伸部521可以包括沿着第二方向Y依次连接的第一初始部c1、第二初始部c2和第三初始部c3，第一初始部c1和第三初始部c3可以与第二方向Y平行，第二初始部c2可以向着第一方向X的反方向偏转，第二初始部c2与第二方向Y具有第一夹角θ1，第一夹角θ1可以大于0°且小于90°。
在一些示例中，在第M行第N+2列电路单元和第M+1行第N列电路单元中，延伸部521可以包括沿着第二方向Y依次连接的第四初始部c4、第五初始部c5、第六初始部c6、第七初始部c7和第八初始部c8，第四初始部c4、第六初始部c6和第八初始部c8可以与第二方向Y平行，第五初始部c5可以与第二方向Y具有第一夹角θ1，第七初始部c7可以与第二方向Y具有第二夹角θ2，第一夹角θ1可以大于0°，小于90°，第二夹角θ2可以大于0°，小于90°。
在一些示例中，第五初始部c5的延伸方向与第七初始部c7的延伸方向可以相对于第一方向X大致镜像对称。
在一些示例中，至少部分电路单元设置有数据信号线51，第N列和第N+2列中的各个电路单元中设置有第二初始信号线52，第N+1列和第N+3列中的各个电路单元中没有设置第二初始信号线52。
至此完成驱动电路层的制备。
在本公开实施例中，不仅初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，而且位于冗余区022的第二像素 驱动电路中的存储电容大于位于显示区01的第一像素驱动电路的存储电容的容值，因此可以的缓解虚拟像素区02的存在而引起显示不均的问题。
另外，在本不公开实施例中，虚拟像素区02的各膜层的材料与上述示例中显示区01的各膜层的材料相同，故在此不再重复赘述。
在本上述任一示例中，初始信号线的第二初始信号线均是设置在第四导电层中的，在一些示例中，第二初始信号线还可以设置的第三导电层中，只要保证交叉设置的第一初始信号线和第二初始信号线可以电连接即可。该种设置方式也可以达到上述效果，故在此不再重复描述。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种显示基板，其具有显示区和与所述显示区相邻的虚拟像素区；所述虚拟像素区包括至少一个像素缺失区，以及与所述像素缺失区相邻的冗余区；所述显示基板包括：
    基底，
    驱动电路层，设置在所述基底上，所述驱动电路层包括多个电路单元；至少一个所述电路单元包括：像素驱动电路和初始信号线；所述像素驱动电路包括位于所述显示区的第一像素驱动电路和位于所述冗余区的第二像素驱动电路，且所述第一像素驱动电路的存储电容小于所述第二像素驱动电路的存储电容；
    发光结构层，设置在所述驱动电路层背离所述基底的一侧；所述发光结构层包括位于所述显示区的多个发光器件；其中，
    所述多条初始信号线中包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线；所述第一方向和所述第二方向交叉，所述第一初始信号线和与之交叉设置的至少部分第二初始信号线电连接。
  2. 根据权利要求1所述的显示基板，其中，所述第一像素驱动电路和所述第二像素驱动电路均包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第七晶体管和所述存储电容；所述第一像素驱动电路还包括第五晶体管和第六晶体管。
  3. 根据权利要求1所述的显示基板，其中，所述驱动电路层在沿背离所述基底一侧依次设置半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述半导体层包括所述像素驱动电路中的多个晶体管的有源层；所述第一导电层包括扫描信号线、多个晶体管的栅电极和所述存储电容的第一极板；所述第二导电层包括所述第一初始信号线和所述存储电容的第二极板；所述第四导电层包括所述第二初始信号线。
  4. 根据权利要求3所述的显示基板，其中，所述第二初始化信号包括相互连接的延伸部和连接部；所述延伸部沿所述第二方向延伸，所述连接部 与所述第一初始信号线连接。
  5. 根据权利要求4所述的显示基板，其中，在具有所述第一像素驱动电路的电路单元中，所述存储电容的第二极板与所述延伸部在所述基底上的正投影的重叠区域为第一区域；在具有所述第二像素驱动电路的电路单元中，所述存储电容的第二极板与所述延伸部在所述基底上的正投影的重叠区域为第二区域；所述第一区域的面积小于第二区域的面积。
  6. 根据权利要求4所述的显示基板，其中，所述显示基板包括i行j列电路单元；i≥2；j≥3，且i和j为整数；
    其中，第M行第N列电路单元中的所述第二初始信号线的形状与第M+1行第N+2列电路单元中的所述第二初始信号线的形状大致相同；第M+1行第N列电路单元中的所述第二初始信号线的形状与第M行第N+2列电路单元中的所述第二初始信号线的形状大致相同；其中，1≤M≤i；1≤N≤j，且M和N均为整数。
  7. 根据权利要求6所述的显示基板，其中，在第M行第N列电路单元和第M+1行第N+2列电路单元中，所述延伸部包括沿着第二方向依次连接的第一初始部、第二初始部和第三初始部，所述第一初始部和所述第三初始部沿所述第二方向延伸，且所述第二初始部的延伸方向与所述第二方向具有第一夹角θ1，0°≤θ1≤90°。
  8. 根据权利要求6所述的显示基板，其中，在第M行第N+2列电路单元和第M+1行第N列电路单元中，所述延伸部包括沿着第二方向依次连接的第四初始部、第五初始部、第六初始部、第七初始部和第八初始部，所述第四初始部、所述第六初始部和所述第八初始部沿第二方向延伸，所述第五初始部的延伸方向与所述第二方向具有第二夹角θ2，所述第七初始部的延伸方向与第二方向具有第三夹角θ3，0°≤θ2≤90°，0°≤θ3≤90°。
  9. 根据权利要求4所述的显示基板，其中，所述电路单元还包括多条第一电源线，一个所述延伸部与一条所述第一电源线在所述基底上的正投影至少部分重叠；所述连接部与所述第一初始信号线在所述基底上的正投影至 少部分重叠。
  10. 根据权利要求9所述的显示基板，其中，所述第一电源线为非等宽度的折线；所述第一电源线包括沿着第二方向依次连接的第一电源部、第二电源部、第三电源部、第四电源部和第五电源部；所述第一电源部、第三电源部和第五电源部沿所述第二方向延伸，所述第二电源部和所述第四电源部的延伸方向不同，且均与所述第二方向相交叉。
  11. 根据权利要求9或10所述的显示基板，其中，所述第一电源线位于所述第三导电层。
  12. 根据权利要求9和10所述的显示基板，其中，所述第二导电层还包括屏蔽电极，所述屏蔽电极通过过孔与所述第一电源线电连接。
  13. 根据权利要求12所述的显示基板，其中，所述屏蔽电极的至少部分区域在所述基底上的正投影位于所述像素驱动电路的第一晶体管的第二极在所述基底上的正投影之间。
  14. 根据权利要求3所述的显示基板，其中，所述电路单元还包括多条数据信号线；所述数据信号线位于所述第四导电层。
  15. 根据权利要求3所述的显示基板，其中，所述电路单元还包括多个第二连接电极；所述连接部通过过孔与所述第二连接电极连接；所述第二连接电极通过过孔与所述第一初始信号线连接；所述第二连接电极还通过过孔与所述像素驱动电路中的第一晶体管的第一区和第七晶体管的第二区连接。
  16. 根据权利要求15所述的显示基板，其中，所述第二连接电极位于所述第三导电层。
  17. 根据权利要求1-16中任一项所述的显示基板，其中，所述第一像素驱动电路中的存储电容的第一极板和第二极板的交叠面积小于所述第二像素驱动电路中的存储电容的第一极板和第二极板。
  18. 根据权利要求1-16中任一项所述的显示基板，其中，多个所述电路单元形成沿所述第二方向并排设置的多个单元行和沿所述第一方向并排设置的多个单元列，所述单元行中的所述像素驱动电路沿所述第一方向并排设 置；所述单元列中的所述像素驱动电路沿所述第二方向并排设置；
    至少一个所述单元列中的各所述电路单元中的第二初始信号线相互连接。
  19. 根据权利要求18所述的显示基板，其中，所述多个单元列包括交替设置的第一单元列和第二单元列；所述第二初始化线设置在所述第一单元列中。
  20. 一种显示装置，其包括权利要求1-19中任一项所述的显示基板。
PCT/CN2022/084444 2022-03-31 2022-03-31 显示基板及显示装置 WO2023184352A1 (zh)

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