WO2023226050A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023226050A1
WO2023226050A1 PCT/CN2022/095772 CN2022095772W WO2023226050A1 WO 2023226050 A1 WO2023226050 A1 WO 2023226050A1 CN 2022095772 W CN2022095772 W CN 2022095772W WO 2023226050 A1 WO2023226050 A1 WO 2023226050A1
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WIPO (PCT)
Prior art keywords
area
layer
line
display
connection line
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PCT/CN2022/095772
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English (en)
French (fr)
Inventor
张云鹏
詹裕程
何祥飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/095772 priority Critical patent/WO2023226050A1/zh
Priority to CN202280001521.1A priority patent/CN117480609A/zh
Publication of WO2023226050A1 publication Critical patent/WO2023226050A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area, a binding area located on one side of the display area in the second direction, and a frame area located on other sides of the display area.
  • the frame area at least includes a The upper frame area on the side of the display area away from the binding area and the side frame area on at least one side of the display area in a first direction, where the first direction intersects the second direction;
  • the display substrate includes a base and a driving circuit layer provided on the base.
  • the base at least includes a first flexible layer, a second flexible layer and a drive circuit layer provided on the first flexible layer and the second flexible layer.
  • the upper frame area includes a first encapsulation area and a first non-encapsulation area arranged sequentially in a direction away from the display area, and the first overlapping via hole is disposed in the first non-encapsulation area. Encapsulation area.
  • the upper frame area includes an isolation area and a crack dam area arranged sequentially in a direction away from the display area, the isolation area is provided with an isolation dam, and the crack dam area is provided with a crack dam, The first overlapping via hole is provided between the isolation dam and the crack dam.
  • the driving circuit layer at least includes a shielding conductive layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially provided on the substrate, the second connection line and the Data signal lines are provided in different conductive layers.
  • the data signal line is provided in the third conductive layer; the second connection line is provided in the shielding conductive layer, or the second connection line is provided in the third conductive layer. in a conductive layer, or the second connection line is provided in the second conductive layer.
  • first end of the first connection line is connected to the leading line of the binding area, and the second end of the first connection line extends through the display area to the upper frame area. Finally, the first end of the second connection line is connected through the first overlapping via hole.
  • a first connection block is provided at an end of the first connection line away from the display area, and an orthographic projection of the first overlapping via hole on the substrate is in contact with the first connection block. Orthographic projections of the blocks on the substrate at least partially overlap.
  • the first end of the second connection line is connected to the second end of the first connection line through the first overlapping via hole, and the second end of the second connection line After extending to the display area, it is connected to the data signal line through the second overlapping via hole.
  • a second connection block is provided at an end of the second connection line away from the display area, and an orthographic projection of the first overlapping via hole on the substrate is in contact with the second connection block. Orthographic projections of the blocks on the substrate at least partially overlap.
  • an orthographic projection of the first overlapping via on the substrate does not overlap with an orthographic projection of the second overlapping via on the substrate.
  • the binding area at least includes a lead-out line area, a bending area and a driving chip area arranged sequentially in a direction away from the display area, and the base conductive layer further includes lead-out lines.
  • the first end of the line is connected to the integrated circuit in the driver chip area, and the second end of the lead-out line extends through the bending area to the lead-out area and is connected to the first end of the first connection line. connect.
  • the lead-out wire and the first connection wire are an integral structure connected to each other.
  • the base conductive layer further includes a first power connection line
  • the lead-out area further includes a second power connection line and a power trace
  • the first end of the first power connection line is connected to the The binding pin connection of the driving chip area is connected.
  • the lead-out area includes a second encapsulation area and a second non-encapsulation area sequentially arranged in a direction away from the display area, and the third overlapping via hole is disposed in the second non-encapsulation area. Encapsulation area.
  • an orthographic projection of the side frame area on the substrate does not overlap with an orthographic projection of the base conductive layer on the substrate.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate, which includes a display area, a binding area located on one side of the display area in the second direction, and a frame area located on other sides of the display area.
  • the frame area at least includes an upper frame area located on the side of the display area away from the binding area and a side frame area located on at least one side of the display area in a first direction, and the first direction is related to the third direction.
  • Two directions cross; the preparation method includes:
  • the substrate at least includes a first flexible layer, a second flexible layer and a base conductive layer disposed between the first flexible layer and the second flexible layer, the base conductive layer at least includes a first connection line;
  • a driving circuit layer is formed on the substrate.
  • the driving circuit layer at least includes a data signal line and a second connection line.
  • the second connection line is connected to the first connection line through a first overlapping via hole.
  • the data signal line is connected to the second connection line through a second overlapping via hole, and the first overlapping via hole is provided in the upper frame area.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic plan view of a display area in a display substrate
  • Figure 4 is a schematic cross-sectional structural diagram of a display area in a display substrate
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit
  • 6a and 6b are schematic planar structural views of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 7a and 7b are schematic structural diagrams of an upper frame area according to an exemplary embodiment of the present disclosure.
  • Figure 8 is a schematic plan view of a data connection line according to an exemplary embodiment of the present disclosure.
  • Figure 9 is a schematic cross-sectional structural diagram of a data connection line according to an exemplary embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of a display substrate after forming a substrate according to the present disclosure.
  • Figure 11 is a schematic diagram after forming a first overlapping via hole in a display substrate according to the present disclosure
  • Figure 12 is a schematic diagram after forming a shielding conductive layer in a display substrate according to the present disclosure
  • Figure 13 is a schematic diagram of a semiconductor layer formed in a display substrate according to the present disclosure.
  • Figure 14 is a schematic diagram after forming a first conductive layer in a display substrate according to the present disclosure.
  • Figure 15 is a schematic diagram after forming a second conductive layer in a display substrate of the present disclosure.
  • Figure 16 is a schematic diagram of a fourth insulating layer formed in a display substrate according to the present disclosure.
  • Figure 17 is a schematic diagram after forming a third conductive layer in a display substrate according to the present disclosure.
  • Figure 18 is a schematic cross-sectional structural diagram of another data connection line according to an exemplary embodiment of the present disclosure.
  • Figure 19 is a schematic diagram after forming a shielding conductive layer in another display substrate of the present disclosure.
  • Figure 20 is a schematic diagram after forming a semiconductor layer in another display substrate of the present disclosure.
  • Figure 21 is a schematic diagram after forming a first conductive layer in another display substrate of the present disclosure.
  • Figure 22 is a schematic diagram after forming a first overlapping via hole in another display substrate of the present disclosure.
  • Figure 23 is a schematic diagram after forming a second conductive layer in another display substrate of the present disclosure.
  • Figure 24 is a schematic diagram after forming a fourth insulating layer in another display substrate of the present disclosure.
  • Figure 25 is a schematic plan view of a side frame area according to an embodiment of the present disclosure.
  • Figure 26 is a schematic cross-sectional structural diagram of a side frame area according to an embodiment of the present disclosure.
  • Figures 27 and 28 are schematic cross-sectional structural diagrams of a binding area according to an embodiment of the present disclosure.
  • 10A the first flexible layer
  • 10B the first barrier layer
  • 10C the second flexible layer
  • 10D the second barrier layer
  • 11 the first active layer
  • 12 the second active layer
  • 16 The sixth active layer
  • 17 The seventh active layer
  • 21 The first scanning signal line
  • 43 The third connection electrode; 44—The first power line; 50—Shielding electrode;
  • 60 data signal line
  • 70 first connection line
  • 71 first connection block
  • 201 Lead line area
  • 202 Bending area
  • 203 Driver chip area
  • 303 organic light-emitting layer
  • 304 cathode
  • 310 upper frame area
  • 320 side frame area
  • 330 frame structure layer
  • 331 first gate circuit
  • 332 First gate circuit
  • 333 Flexible gate wiring
  • 334 Flexible gate electrode
  • 401 The first encapsulation layer
  • 402 The second encapsulation layer
  • 403 The third encapsulation layer
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • the word “approximately” in this disclosure refers to a value that does not strictly limit the limit and allows for process and measurement errors.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal. lines, data signal lines and light-emitting signal lines.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample a grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal, m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area 100 .
  • the fan-out area is connected to the display area 100 and may include at least a plurality of data connection lines.
  • the plurality of data connection lines are configured to connect data signal lines of the display area in a fan-out (Fanout) wiring manner.
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area may at least include an integrated circuit (Integrated Circuit, IC for short) configured to be connected to multiple data connection lines.
  • the bonding pin area may include at least a plurality of bonding pins (Bonding Pad), configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning line, the second scanning line and the light emission control line of the pixel driving circuit in the display area 100 .
  • the power line area is connected to the circuit area and may include at least a frame power line.
  • the frame power line extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along Extending in a direction parallel to the edge of the display area, forming a ring-shaped structure surrounding the display area 100, the edge of the display area is an edge on one side of the display area binding area or the frame area.
  • Figure 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a second sub-pixel that emits light of a second color.
  • Pixel P2, third sub-pixel P3 and fourth sub-pixel P4 emitting light of the third color.
  • Each sub-pixel may include a circuit unit and a light-emitting device.
  • the circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to the scanning signal line, the data signal line and the light-emitting signal line respectively.
  • the pixel driving circuit is configured to operate between the scanning signal line and the light-emitting signal line. Under the control of the light-emitting signal line, it receives the data voltage transmitted by the data signal line and outputs the corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagon or hexagon, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged horizontally, vertically, or in a square manner, which is not limited in this disclosure.
  • the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 .
  • the structural layer 103 is away from the packaging structural layer 104 on one side of the substrate 101.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, and the circuit units may include at least a pixel driving circuit.
  • the light-emitting structure layer 103 may have at least a plurality of light-emitting devices.
  • the light-emitting devices may at least include an anode 301, an organic light-emitting layer 303 and a cathode 304.
  • the organic light-emitting layer 303 emits light of corresponding colors under the driving of the anode 301 and the cathode 304.
  • the light-emitting structure layer 103 may also include a pixel definition layer 302 covering the anode 301.
  • the pixel definition layer 302 is provided with a pixel opening, and the pixel opening exposes the surface of the anode 301.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water and oxygen cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together Common layer, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C.
  • the pixel driving circuit is respectively connected to 7 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power supply line VDD and the second power supply line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor,
  • the first electrode of the second transistor T2 and the control electrode of the third transistor T3 are connected to the second end of the storage capacitor C.
  • the third node N3 is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switching transistor, a scanning transistor, or the like.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth and sixth transistors T5 and T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the initial voltage to the first pole of the light-emitting device, so that the amount of charge accumulated in the first pole of the light-emitting device is initialized or released to emit light. The amount of charge accumulated in the first pole of the device.
  • the light-emitting device may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode) , quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal. flat signal.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the working process of the pixel drive circuit can include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned on.
  • the first transistor T1 is turned on so that the initial voltage of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal prestored voltage, and completing the initialization.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 to be turned off. At this stage, the OLED does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, causing the second transistor T2 and the fourth transistor T4 to be turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • Node N2 and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the data fan-out lines are set in the fan-out area of the binding area. Since the width of the fan-out area is smaller than the width of the display area, the data fan-out lines need to be introduced into the wider display area through fan-out routing. The greater the width difference between the display area and the binding area, the more oblique fan-out lines in the fan-shaped area, and the larger the space occupied by the fan-shaped area. In addition, as the resolution of the display screen gradually increases, the occupied width of the fan-out line will gradually increase, making it more difficult to design a narrower bottom border, which has been maintained at around 2.0mm.
  • Exemplary embodiments of the present disclosure provide a display substrate that adopts a structure in which data connection lines are located in a display area (Fanout in AA, FIAA for short).
  • One end of a plurality of data connection lines is correspondingly connected to a plurality of data signal lines in the display area.
  • the other ends of the plurality of data connection lines extend to the binding area and are correspondingly connected to the integrated circuits in the binding area. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, effectively reducing the width of the bottom border.
  • the display substrate may at least include a display area, a binding area located on one side of the display area, and a frame area located on other sides of the display area.
  • the frame area may include a display area located on one side of the display area. The upper border area on the side away from the binding area and the side border area on both sides of the display area.
  • the display substrate may include a driving circuit layer disposed on the substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. Encapsulation structure layer on one side.
  • the substrate may include at least a first flexible layer, a second flexible layer, and a base conductive layer disposed between the first flexible layer and the second flexible layer.
  • the driving circuit layer of the display area may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns. At least one circuit unit may include a pixel driving circuit configured to output a corresponding current to the connected light-emitting device. .
  • the light-emitting structure layer of the display area may include a plurality of sub-pixels constituting a pixel array. At least one sub-pixel may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit. The light-emitting device is configured to respond to the output of the connected pixel driving circuit. The current emits light with corresponding brightness.
  • the sub-pixels mentioned in this disclosure refer to areas divided according to light-emitting devices, and the circuit units mentioned in this disclosure refer to areas divided according to pixel driving circuits.
  • the orthographic projection position of the sub-pixel on the substrate may correspond to the orthographic projection position of the circuit unit on the substrate, or the orthographic projection position of the sub-pixel on the substrate corresponds to the orthographic projection position of the circuit unit on the substrate. The positions may not correspond.
  • a display substrate may include a display area, a binding area located on one side of the display area in the second direction, and a frame area located on other sides of the display area.
  • the frame area It includes at least an upper frame area located on the side of the display area away from the binding area and a side frame area located on at least one side of the display area in a first direction, where the first direction intersects the second direction; in On a plane perpendicular to the display substrate, the display substrate includes a base and a drive circuit layer provided on the base.
  • the base at least includes a first flexible layer, a second flexible layer and a drive circuit layer provided on the first flexible layer.
  • the overlapping via hole is connected to the first connection line
  • the data signal line is connected to the second connection line through the second overlapping via hole
  • the first overlapping via hole is provided in the upper frame area.
  • the upper frame area includes a first encapsulation area and a first non-encapsulation area arranged sequentially in a direction away from the display area, and the first overlapping via hole is disposed in the first non-encapsulation area. Encapsulation area.
  • the upper frame area includes an isolation area and a crack dam area arranged sequentially in a direction away from the display area, the isolation area is provided with an isolation dam, and the crack dam area is provided with a crack dam, The first overlapping via hole is provided between the isolation dam and the crack dam.
  • the binding area at least includes a lead-out line area, a bending area and a driving chip area arranged sequentially in a direction away from the display area, and the base conductive layer further includes lead-out lines.
  • the first end of the line is connected to the integrated circuit in the driver chip area, and the second end of the lead-out line extends through the bending area to the lead-out area and is connected to the first end of the first connection line. connect.
  • the base conductive layer further includes a first power connection line
  • the lead-out area further includes a second power connection line and a power trace
  • the first end of the first power connection line is connected to the The binding pin connection of the driving chip area is connected.
  • the lead-out area includes a second encapsulation area and a second non-encapsulation area sequentially arranged in a direction away from the display area, and the third overlapping via hole is disposed in the second non-encapsulation area. Encapsulation area.
  • an orthographic projection of the side frame area on the substrate does not overlap with an orthographic projection of the base conductive layer on the substrate.
  • the driving circuit layer at least includes a shielding conductive layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged on the substrate, the second connection line and the data signal
  • the wires are arranged in different conductive layers.
  • the data signal line is provided in the third conductive layer; the second connection line is provided in the shielding conductive layer, or the second connection line is provided in the third conductive layer. in a conductive layer, or the second connection line is provided in the second conductive layer.
  • Figures 6a and 6b are schematic planar structural views of a display substrate according to an exemplary embodiment of the present disclosure.
  • the data connection lines in the display substrate adopt a FIAA structure.
  • Figure 6a illustrates the structure of the first connection line
  • Figure 6b illustrates the data signal line. and the structure of the second connecting line.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame located on other sides of the display area 100 Area 300.
  • the display area 100 may include at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include at least a pixel driving circuit.
  • the binding area 200 may at least include a lead-out area 201 and a bending area 202 arranged sequentially in a direction away from the display area 100.
  • the lead-out area 201 may include a plurality of lead-out lines 220, the first ends of which are connected to the binding area.
  • the integrated circuit in the area 200 is connected, and the second end of the lead wire 220 extends to the lead wire area 201 through the bending area 202 .
  • the frame area 300 may include an upper frame area 310 located on the opposite side of the second direction Y of the display area 100 (the display area 100 is away from the binding area 200 ) and side frame areas 320 located on both sides of the first direction X of the display area 100 .
  • a plurality of circuit units sequentially arranged along the first direction X may be called a unit row
  • a plurality of circuit units sequentially arranged along the second direction Y may be called a unit column.
  • a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X and the second direction Y intersect.
  • the second direction Y may be an extending direction of the data signal line (vertical direction)
  • the first direction X may be perpendicular to the second direction Y (horizontal direction).
  • the display area 100 may include a plurality of data connection lines 60 , the data signal lines 60 may be in the shape of a line with a main body portion extending along the second direction Y, and the plurality of data signal lines 60 may be in the first direction X. Arranged in sequence at set intervals, each data signal line 60 is connected to the pixel driving circuits of multiple circuit units in one unit column.
  • the display substrate may further include a plurality of first connection lines 70 and second connection lines 80 , and the first connection lines 70 and the second connection lines 80 constitute data connection lines.
  • the first ends of the plurality of first connection lines 70 are correspondingly connected to the plurality of lead lines 220 of the lead line area 201 , and the second ends of the plurality of first connection lines 70 extend from the lead line area 201 through the display area 100 to the upper frame area.
  • the first ends of the plurality of second connection lines 80 are connected correspondingly through the first overlapping via hole DV1.
  • the second ends of the plurality of second connection lines 80 extend from the upper frame area 310 to the display area 100, they are correspondingly connected to the plurality of data signal lines 60 through the second overlapping via holes DV2, forming a first overlapping via hole DV1.
  • the second overlapping via DV2 is provided in the data connection line structure of the display area 100.
  • the lead-out line 220 is connected to the integrated circuit in the bonding area 200
  • the first connection line 70 is connected to the lead-out line 220
  • the second connection line 80 is connected to the first connection line 70
  • the data signal line 60 It is connected to the second connection line 80, so the data signal line 60 in the display area is connected to the integrated circuit in the binding area through the second connection line 80, the first connection line 70 and the lead line 220, realizing the integration of the integrated circuit to the data signal.
  • Line 60 provides the data signal. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, which can effectively reduce the width of the bottom border.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length extending in direction B is greater than the length of the secondary portion extending in other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • the number of data connection lines may be the same as the number of data signal lines, or the number of data connection lines may be less than the number of data signal lines, which is not limited by the present disclosure.
  • Figure 7a is a schematic structural diagram of an upper frame area according to an exemplary embodiment of the present disclosure. It is an enlarged view of area A in Figures 6a and 6b.
  • Figure 7b is a cross-sectional view along the A-A direction in Figure 7a.
  • the upper frame area 310 of the frame area 300 may be located on a side of the display area 100 away from the binding area 200 , and the upper frame area 310 may include a package formed by the first package.
  • Line FX1 divides the first encapsulation area and the first non-encapsulation area.
  • the first encapsulation line FX1 may be the boundary where the encapsulation structure layer covers the upper frame area 310.
  • the first encapsulation line FX1 may divide the upper frame area 310 into areas along the distance away from the display.
  • the first packaging area and the first non-encapsulation area are arranged sequentially in the direction of the area 100.
  • the side of the first packaging line FX1 close to the display area 100 is the first packaging area, and the side of the first packaging line FX1 away from the display area 100 is the first packaging area. Unencapsulated area.
  • the first encapsulation area may be provided with a first isolation dam 410 and a second isolation dam 420
  • the first non-encapsulation area may include a crack dam area and a cutting area sequentially arranged in a direction away from the display area 100
  • the crack dam area is connected to the first encapsulation area, and may at least include a plurality of cracks provided on the composite insulation layer to form a crack dam
  • the crack dam is configured to reduce the stress on the display area 100 during the cutting process and intercept the direction of the cracks.
  • the cutting area is connected to the crack dam area, which may at least include cutting grooves provided on the composite insulating layer.
  • the cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment proceeds along the cutting grooves respectively. cutting.
  • a plurality of first overlapping vias DV1 may be disposed in the isolation area, that is, a plurality of first overlapping vias DV1 may be disposed on a side of the first packaging line FX away from the display area 100 .
  • a plurality of first overlapping vias DV1 may be disposed between the second isolation dam and the crack dam.
  • the first connection line 70 may be connected to the second connection line 80 through a plurality of first overlapping vias DV1 to reduce overlapping resistance and improve connection reliability.
  • the plurality of first overlapping vias DV1 may be sequentially disposed in a direction away from the display area.
  • a first connection line 70 may be connected to a second connection line 80 through two first overlapping vias DV1, and the length L1 of the first overlapping via DV1 may be approximately 4 ⁇ m to 8 ⁇ m.
  • the distance L2 between the two first overlapping vias DV1 may be approximately 8 ⁇ m to 12 ⁇ m, the length L1 may be the size of the first overlapping via hole in the second direction Y, and the distance L2 may be the distance between the two first overlapping via holes.
  • the distance between edges For example, the shape of the first overlapping via DV1 may be rectangular, the length L1 of the first overlapping via DV1 may be approximately 6 ⁇ m, and the distance L2 between the two first overlapping vias DV1 may be approximately 10 ⁇ m.
  • the occupied length L of the plurality of first overlapping via holes DV1 may be approximately 20 ⁇ m to 50 ⁇ m, and the occupied length L may be between one and one of the first overlapping via holes DV1 close to the display area. The maximum distance between the edge of the first overlapping via hole and the edge of the side away from the display area.
  • the shape of the first overlapping via DV1 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and Oval.
  • the display substrate may include a substrate 101 and a driving circuit layer 102 disposed on the substrate 101 .
  • the substrate 101 may include at least a first connection line 70
  • the driving circuit layer 102 may include at least a data signal line 60 and a second connection line 80.
  • the first connection line 70 is connected to the second connection line 80 through the first overlapping via DV1
  • the second connection line 80 is connected to the data signal line 60 through the second overlapping via hole DV2.
  • the upper frame area 310 may also include an isolation structure layer disposed on the side of the driving circuit layer 102 away from the substrate.
  • the isolation structure layer may include at least a first isolation dam 410, a second isolation dam 420 and a first package.
  • Layer 401, the first isolation dam 410 and the second isolation dam 420 may be disposed on a side of the first packaging line FX close to the display area 100, the first packaging layer 401 covers the first isolation dam 410 and the second isolation dam 420, the first The encapsulation layer 401 forms a first encapsulation line FX away from the boundary of the display area 100, and the first encapsulation line FX may be called a CVD boundary.
  • the first connection line 70 may be provided in the base conductive layer of the substrate 101
  • the data signal line 60 may be provided in the source-drain metal layer (SD) of the driving circuit layer 102
  • the second connection line 80 may is provided in the shielding conductive layer (SHL) of the driving circuit layer 102
  • the second connection line 80 can be provided in the first gate metal layer (GATE1) of the driving circuit layer 102
  • the second connection line 80 can be provided in In the second gate metal layer (GATE2) of the driving circuit layer 102.
  • FIG. 8 is a schematic plan view of the data connection line according to an exemplary embodiment of the present disclosure, and is an enlarged view of area B in FIGS. 6a and 6b.
  • the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns
  • the upper frame area 310 may include a circuit unit divided by the first packaging line FX1
  • the first encapsulation area and the first non-encapsulation area, the first encapsulation area and the first non-encapsulation area can be arranged sequentially along the direction away from the display area 100, and the side of the first encapsulation line FX1 close to the display area 100 is the first encapsulation area, The side of the first packaging line FX1 away from the display area 100 is the first non-encapsulation area.
  • At least one circuit unit may include a pixel driving circuit.
  • the pixel driving circuit may include at least a plurality of transistors and a storage capacitor.
  • the data signal line 60 is connected to a plurality of pixel driving circuits of one unit column.
  • the data signal line 60 Configured to provide data signals to the pixel drive circuit.
  • the display area 100 may include at least a first connection line 70
  • the upper frame area 310 may include at least a second connection line 80
  • the hole DV1 may be disposed in the upper frame area 310
  • the first overlapping via DV1 may be disposed on a side of the first packaging line FX1 away from the display area 100 to connect the second connecting line 80 and the second overlapping of the data signal line 60
  • the via DV2 may be provided in the display area 100
  • the second overlapping via DV2 may be provided in the upper frame area 310
  • the second overlapping via DV2 may be provided in the boundary area between the display area 100 and the upper frame area 310 .
  • first connection line 70 extends through the display area 100 to the upper frame area 310
  • second connection line 80 is connected to the first overlapping via DV1.
  • the second connection line 80 extends from the upper frame area 310 After extending to the display area 100, it is connected to the data signal line 60 through the second overlapping via DV2.
  • FIG. 9 is a schematic cross-sectional structural view of a data connection line according to an exemplary embodiment of the present disclosure, which is a cross-sectional view along the B-B direction in FIG. 8 .
  • the display substrate may at least include a driving circuit layer 102 disposed on the substrate 101 .
  • the substrate 101 may include at least a first flexible layer 10A, a second flexible layer 10C, and a base conductive layer disposed between the first flexible layer 10A and the second flexible layer 10C.
  • the base conductive layer may at least include The first connection line 70.
  • the driving circuit layer 102 may at least include a data signal line 60 and a second connection line 80.
  • the data signal line 60 is connected to the second connection line 80 through the second overlapping via hole DV2, and the second connection line 80 passes through the first overlapping via hole.
  • DV1 is connected to the first connection line 70 .
  • the driving circuit layer 102 may at least include a shielding conductive layer, a first insulating layer 91 , a semiconductor layer, a second insulating layer 92 , a first conductive layer, and a third insulating layer 93 sequentially disposed on the substrate 101 , the second conductive layer, the fourth insulating layer 94 and the third conductive layer.
  • the shielding conductive layer may include at least the second connection line 80
  • the semiconductor layer may include at least the active layer of a plurality of transistors of the pixel driving circuit
  • the first conductive layer may at least include gate electrodes of the plurality of transistors and a first plate of the storage capacitor.
  • the second conductive layer may include at least the second plate of the storage capacitor
  • the third conductive layer may at least include the data signal line 60 .
  • the substrate 101 may further include a first barrier layer 10B and a second barrier layer 10D.
  • the first barrier layer 10B is disposed between the first flexible layer 10A and the base conductive layer.
  • the second barrier layer 10D is disposed between The second flexible layer 10C is away from the side of the first flexible layer 10A.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them, this disclosure is not limited here.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • this exemplary embodiment shows that the preparation process of the substrate may include the following operations.
  • preparing the substrate may include: first coating a layer of first flexible material on a glass carrier, curing the film to form a first flexible layer 10A. Then, a first barrier film and a base conductive film are sequentially deposited on the first flexible layer 10A, and the base conductive film is patterned through a patterning process to form a first barrier layer 10B covering the first flexible layer 10A, and set The base conductive layer pattern on the first barrier layer 10B. Then, a layer of second flexible material is coated and cured to form a film to form a second flexible layer 10C covering the pattern of the base conductive layer.
  • the base conductive layer may be referred to as a 0th source-drain metal (SDO) layer.
  • SDO source-drain metal
  • the base conductive layer pattern may include at least a plurality of first connection lines 70 disposed in the display area 100 and the upper frame area 310 .
  • the shape of the first connecting line 70 may be a line shape in which the main body portion extends along the second direction Y, the first end of the first connecting line 70 is connected to the lead-out line in the binding area, and the first The second end of the connecting line 70 extends across the display area 100 to the upper frame area 310 .
  • the end of the first connection line 70 away from the display area 100 (the second end of the first connection line 70) is provided with a first connection block 71, and the shape of the first connection block 71 may be a rectangle,
  • the first connection block 71 and the first connection line 70 may be an integral structure connected to each other, and the first connection block 71 is configured to be connected to a subsequently formed second connection line through a first overlapping via hole.
  • the first connection block 71 may be disposed on a side of the first packaging line FX1 away from the display area.
  • the plurality of first connection lines 70 may be spaced apart along the first direction .
  • materials of the first flexible layer and the second flexible layer may include, but are not limited to, polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene , one or more of polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the materials of the first barrier layer and the second barrier layer may include but are not limited to any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, Multiple layers or composite layers are used to improve the water and oxygen resistance of the substrate.
  • the base conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals.
  • the base conductive layer can be made of metal molybdenum.
  • the base conductive layer may adopt a titanium/aluminum/titanium (Ti/Al/Ti) composite structure, which is beneficial to reducing the resistance of the first connection line.
  • Ti/Al/Ti titanium/aluminum/titanium
  • Exemplary embodiments of the present disclosure display substrates, by arranging a base conductive layer between double flexible layers of the base, and the base conductive layer includes a first connection line that implements a fan-out function in the display area and the upper frame area, which is beneficial to reducing binding.
  • the trace density of the area is beneficial to reducing binding.
  • forming the first overlapping via pattern may include: patterning the second barrier layer and the second flexible layer through a patterning process to form a plurality of first overlapping vias DV1, as shown in FIG. 11 shown.
  • a plurality of first overlapping vias DV1 may be disposed on a side of the first packaging line FX1 away from the display area 100 , that is, the first overlapping vias DV1 may be disposed on a side other than the upper frame area 310 . Encapsulation area.
  • the orthographic projection of the first overlapping via hole DV1 on the substrate may be located within the range of the orthogonal projection of the first connecting block 71 on the substrate, and the second barrier in the first overlapping via hole DV1 The layer and the second flexible layer are removed to expose the surface of the first connection block 71 , and the first overlapping via hole DV1 is configured to allow the subsequently formed second connection line to be connected to the first connection block 71 through the via hole.
  • the shape of the first overlapping via DV1 may be any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse.
  • forming the shielding conductive layer pattern may include: depositing a shielding film on the substrate, patterning the shielding film through a patterning process, and forming a shielding conductive layer (SHL) pattern on the second barrier layer, as shown in FIG. 12 shown.
  • SHL shielding conductive layer
  • the shielding conductive layer pattern may include at least the shielding electrode 50 provided in the display area 100 and the second connection line 80 provided in the display area 100 and the upper frame area 310 .
  • the shielding electrode 50 may be rectangular in shape and may be disposed in each circuit unit of the display area 100 .
  • the shielding electrode 50 is configured to shield at least one transistor of the pixel driving circuit and reduce the impact of light on Effect on the electrical properties of transistors.
  • the shielding electrode 50 may also be configured to suppress the accumulation of electrons generated by impact ionization inside the channel and to reduce the accumulation of Joule heat in the channel.
  • the shape of the second connection line 80 may be a line shape in which the main body part extends along the second direction Y, and the end of the second connection line 80 away from the display area 100 (the first end of the second connection line 80 end) is provided with a second connection block 81.
  • the shape of the second connection block 81 may be a rectangular shape.
  • the second connection block 81 is connected to the first connection block 71 through the first overlapping via hole DV1.
  • the second end of the second connection line 80 extends to the display area 100, and the second end of the second connection line 80 is configured to be connected to a subsequently formed data signal line.
  • Form a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the shielding conductive layer, and The semiconductor layer pattern provided on the first insulating layer is as shown in Figure 13.
  • the semiconductor layer pattern of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7.
  • the layer 11 to the seventh active layer 17 are an integral structure connected to each other.
  • the sixth active layer 16 in the circuit unit of this unit row and the seventh active layer 17 in the circuit unit of the next unit row are connected to each other.
  • the second active layer 12 and the sixth active layer 16 may be located on the same side of the third active layer 13 in this circuit unit, and the fourth active layer 14 and The fifth active layer 15 may be located on the same side of the third active layer 13 in this circuit unit, and the second active layer 12 and the fourth active layer 14 may be located on different sides of the third active layer 13 of this circuit unit.
  • the first active layer 11 , the second active layer 12 , the fourth active layer 14 and the seventh active layer 17 may be located in the third active layer 13 of the circuit unit in the second direction Y.
  • the fifth active layer 15 and the sixth active layer 16 may be located on the side of the third active layer 13 in the second direction Y in this circuit unit.
  • the orthographic projection of the third active layer 13 on the substrate may be within the range of the orthographic projection of the shielding electrode 50 on the substrate, and the shielding electrode 50 may shield the third active layer 13 to reduce Effect of light on the electrical properties of drive transistors.
  • the first active layer 11 may be in an "n" shape
  • the second active layer 12 and the fifth active layer 15 may be in an "L” shape
  • the third active layer 13 may be in an "L” shape.
  • the shapes of the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 can be in the shape of "I”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer 11 may serve as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 may As the first region 12-1 of the second active layer 12, the first region 13-1 of the third active layer 13 may simultaneously serve as the second region 14-2 and the fifth active layer of the fourth active layer 14.
  • the second region 15-2 of 15 and the second region 13-2 of the third active layer 13 can simultaneously serve as the second region 12-2 of the second active layer 12 and the first region 16 of the sixth active layer 16.
  • the second region 16-2 of the sixth active layer 16 can be used as the second region 17-2 of the seventh active layer 17, the first region 14-1 of the fourth active layer 14 and the fifth active layer 14.
  • the first zone 15-1 of the layer 15 can be provided separately.
  • the orthographic projection of the semiconductor layer on the substrate does not overlap with the orthographic projection of the second connection line 80 on the substrate.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming A second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG. 14 .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit in the display area at least includes: a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23, and a first plate 24 of a storage capacitor. .
  • the shape of the first plate 24 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the orthographic projections of the layers on the substrate at least partially overlap.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scanning signal line 21 may be a line shape with the main body extending along the first direction X, and the first scanning signal line 21 may be located in the second direction of the first plate 24 of the circuit unit. The side in the opposite direction of Y.
  • the first scanning signal line 21 of each circuit unit is provided with a gate block, the first end of the gate block is connected to the first scanning signal line 21 , and the second end of the gate block extends in a direction away from the first plate 24 .
  • the area where the first scanning signal line 21 and the gate block overlap with the second active layer of this circuit unit serves as the gate electrode of the second transistor T2 of the double-gate structure.
  • the first scanning signal line 21 and the fourth active layer of this circuit unit The area where the active layers overlap serves as the gate electrode of the fourth transistor T4.
  • the shape of the second scanning signal line 22 may be a line shape with the main part extending along the first direction X, and the second scanning signal line 22 may be located away from the first scanning signal line 21 of the circuit unit.
  • the area where the second scanning signal line 22 overlaps with the first active layer of this circuit unit serves as the gate electrode of the first transistor T1 of the double-gate structure.
  • the second scanning signal line 22 and this circuit unit The overlapping area of the seventh active layer of the cell serves as the gate electrode of the seventh transistor T7.
  • the shape of the light-emitting control line 23 may be a line shape with the main body extending along the first direction X, and the light-emitting control line 23 may be located on one side of the first plate 24 of the circuit unit in the second direction Y. , the area where the light-emitting control line 23 overlaps with the fifth active layer of this circuit unit serves as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 23 overlaps with the sixth active layer of this circuit unit serves as the sixth transistor. Gate electrode of T6.
  • the first scanning signal line 21 , the second scanning signal line 22 and the light emitting control line 23 may be designed with equal widths, or may be designed with unequal widths, may be straight lines, or may be polygonal lines, not only It facilitates the layout of the pixel structure and can reduce the parasitic capacitance between signal lines. This disclosure is not limited here.
  • the first conductive layer can be used as a shield to perform a conductive process on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the first to seventh transistors T1 to T1.
  • the channel region of the transistor T7 and the semiconductor layer in the region not blocked by the first conductive layer are conductive, that is, the first and second regions of the first to seventh active layers of the first transistor T1 are all conductive.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process to form A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG. 15 .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit in the display area at least includes: an initial signal line 31 , a second plate 32 of the storage capacitor, and a plate connection line 33 .
  • the outline of the second electrode plate 32 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 32 on the base is consistent with the orthographic projection of the first electrode plate 24 on the base.
  • the orthographic projection at least partially overlaps, the second plate 32 can serve as another plate of the storage capacitor, and the first plate 24 and the second plate 32 constitute the storage capacitor of the pixel driving circuit.
  • the second electrode plate 32 is provided with an opening 34 .
  • the opening 34 may be rectangular in shape and may be located in the middle of the second electrode plate 32 , so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located within the opening 34 and exposes the first plate 24 so that the subsequently formed second via hole of the first transistor T1
  • the pole is connected to the first pole plate 24 .
  • the second plates 32 in two adjacent sub-pixels in a unit row may be connected to each other through plate connection lines 33 .
  • the second electrode plate 32 in the N-1th column and the second electrode plate 32 in the Nth column may be connected to each other through the electrode plate connection line 33 .
  • the second electrode plate 32 in the Nth column and the second electrode plate 32 in the N+1th column are connected to each other through the electrode plate connection line 33 .
  • the second plate 32 in each circuit unit is connected to the subsequently formed first power line, by forming the second plate 32 of adjacent circuit units into an integrated structure connected to each other, the integrated structure
  • the second electrode plate can be reused as a power signal line, which can ensure that multiple second electrode plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display substrate's display effect.
  • the shape of the initial signal line 31 may be a line shape with the main body portion extending along the first direction X, and the initial signal line 31 may be located away from the first scanning signal line 22 of the circuit unit.
  • the initial signal line 31 is configured to be connected to the first pole of the subsequently formed first transistor T1 (also the first pole of the seventh transistor T7 ).
  • Form a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • the fourth insulating layer is provided with multiple via holes, as shown in Figure 16.
  • the plurality of via holes of each circuit unit in the display area at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, and a fifth via hole.
  • V5 the sixth via V6, the seventh via V7 and the eighth via V8.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 34 on the substrate, and the fourth insulating layer and the third insulating layer in the first via hole V1 are etched Etched away to expose the surface of the first plate 24, the first via hole V1 is configured to allow the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) to pass through the via hole V1 and the first electrode of the second transistor T2.
  • the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate, and the fourth insulating layer in the second via hole V2 is etched away. , exposing the surface of the second electrode plate 32 , and the second via hole V2 is configured to allow the subsequently formed first power line to be connected to the second electrode plate 32 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the fourth insulating layer in the third via hole V3 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer, and the third via hole V3 is configured to allow the subsequently formed first power line to pass through the via hole and The first area of the fifth active layer is connected.
  • the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the surface of the second region of the sixth active layer, and the fourth via hole V4 is configured to make
  • the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) is connected to the second region of the sixth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, and the fourth insulating layer in the fifth via hole V5 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer, and the fifth via hole V5 is configured to allow the subsequently formed data signal line to pass through the via hole and the third insulating layer.
  • the first zone of the four active layers is connected.
  • the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the surface of the second region of the first active layer, and the sixth via hole V6 is configured to make
  • the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) is connected to the second region of the first active layer (also the first region of the second active layer) through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first region of the first active layer (also the first region of the seventh active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away, exposing the first area surface of the first active layer, and the seventh via hole V7 is configured to make
  • the first electrode of the subsequently formed first transistor T1 (also the first electrode of the seventh transistor T7) is connected to the first region of the first active layer (also the first region of the seventh active layer) through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the initial signal line 31 on the substrate, and the fourth insulating layer in the eighth via hole V8 is etched away, The surface of the initial signal line 31 is exposed, and the eighth via hole V8 is configured so that the first pole of the subsequently formed first transistor T1 (also the first pole of the seventh transistor T7) is connected to the initial signal line 31 through the via hole. .
  • the plurality of vias further include second overlapping vias DV2, and the second overlapping vias DV2 may be provided in some circuit units.
  • the orthographic projection of the second overlapping via hole DV2 on the substrate is located within the range of the orthographic projection of the second end of the second connecting line 80 on the substrate.
  • the fourth insulating layer and the third insulating layer in the second overlapping via hole DV2 The insulating layer, the second insulating layer and the first insulating layer are etched away to expose the surface of the second end of the second connection line 80, and the second overlapping via hole DV2 is configured to allow the subsequently formed data signal line to pass through the via hole DV2.
  • the hole is connected to the second connection line 80 .
  • the orthographic projection of the second overlapping via hole DV2 on the substrate does not overlap with the orthographic projection of the first overlapping via hole on the substrate.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer is shown in Figure 17.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer of each circuit unit in the display area includes at least: a first connection electrode 41 , a second connection electrode 42 , a third connection electrode 43 , a first power supply line 44 and a data signal line 60 .
  • the shape of the first connection electrode 41 may be a straight line with the main body extending along the second direction Y.
  • the first end of the first connection electrode 41 passes through the first via hole V1 and the first plate 24 connection, the second end of the first connection electrode 41 is connected to the second area of the first active layer (also the first area of the second active layer) through the sixth via hole V6, so that the first plate 24 and the first The second region of the active layer and the first region of the second active layer have the same potential.
  • the first connection electrode 41 may simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the shape of the second connection electrode 42 may be a polyline shape with the main body portion extending along the second direction Y, and the first end of the second connection electrode 42 is connected to the initial signal line 31 through the eighth via hole V8 , the second end of the second connection electrode 42 is connected to the first region of the first active layer (also the first region of the seventh active layer) through the seventh via hole V7.
  • the second connection electrode 42 may simultaneously serve as the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7.
  • the shape of the third connection electrode 43 may be a block shape, and the third connection electrode 43 communicates with the second area of the sixth active layer (also the second area of the seventh active layer) through the fourth via hole V4. area) connection.
  • the third connection electrode 43 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 at the same time, and the third connection electrode 43 is configured to be connected to a subsequently formed anode connection electrode.
  • the shape of the first power line 44 may be a straight line with the main part extending along the second direction Y.
  • the first power line 44 is connected to the second plate 32 through the second via hole V2
  • the first power line 44 is connected to the first area of the fifth active layer through the third via V3, realizing writing the power signal into the first pole of the fifth transistor T5, and the second plate 32 It has the same potential as the first pole of the fifth transistor T5.
  • the shape of the data signal line 60 may be a straight line with the main part extending along the second direction Y, and the data signal line 60 is connected to the first area of the fourth active layer through the fifth via V5, Writing the data signal to the first pole of the fourth transistor T4 is achieved.
  • the data signal line 60 is also connected to the second connection line 80 through the second overlapping via DV2. Since the second connection line 80 is connected to the first connection line 70 through the first overlapping via hole, the data signal line 60 of the display area 100 is led out to the binding area through the first connection line 70 and the second connection line 80 line connection.
  • the subsequent preparation process may include processes such as forming a first planar layer, forming a fourth conductive layer, forming a second planar layer, etc., to prepare the driving circuit layer on the glass substrate.
  • the driving circuit layer of the display area may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and the pixel driving circuits are respectively connected to the first scanning signal line 21 , the second scanning signal line 22, the light emission control line 23, the initial signal line 31, the first power supply line 44 and the data signal line 60 are connected.
  • the driving circuit layer of the display area and the upper frame area may include a plurality of first connection lines 70 and a plurality of second connection lines 80.
  • the second connection lines 80 are connected to the first connection lines 70 through the first overlapping via DV1, and the data The signal line 60 passes through the second overlapping via DV2 and the second connection line 80 .
  • the driving circuit layer may be disposed on the substrate on a plane perpendicular to the display substrate.
  • the substrate may include a stacked first flexible layer 10A, a first barrier layer 10B, a base conductive layer, a second flexible layer 10C and a second barrier layer 10D.
  • the base conductive layer may at least include a first layer located in the display area and the upper frame area.
  • the driving circuit layer may at least include a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer and a third insulating layer sequentially disposed on the substrate.
  • the shielding conductive layer may at least include a second connection line 80 located in the display area and the upper frame area, and the second connection line 80 is connected to the first connection line 70 through the first overlapping via DV1.
  • the semiconductor layer may include at least the active layers of the first to seventh transistors, and the first conductive layer may include at least the first scanning signal line 21, the second scanning signal line 22, the light emitting control line 23 and the first plate of the storage capacitor. 24.
  • the second conductive layer may include at least the initial signal line 31, the second plate 32 of the storage capacitor, and the plate connection line 33.
  • the third conductive layer may include at least the first connection electrode 41, the second connection electrode 42, the third The electrode 43, the first power line 44 and the data signal line 60 are connected, and the data signal line 60 is connected to the second connection line 80 through the second overlapping hole DV2.
  • the shielding conductive layer, the first conductive layer, the second conductive layer and the third conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). Any one or more of them, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc. .
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). Any one or more of them, or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc. .
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Can be single layer, multi-layer or composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer and the third insulating layer may be called gate insulating (GI) layers
  • the fourth insulating layer may be called an interlayer insulating (ILD) layer.
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, embodiments of the present invention are suitable for thin film transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • six Materials such as thiophene or polythiophene, that is, embodiments of the present invention are suitable for thin film transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a light-emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer.
  • preparing the light-emitting structure layer may include: first forming an anode conductive layer, and the anode conductive layer may at least include a plurality of anode patterns. A pixel definition layer is then formed, and a pixel opening is provided on the pixel definition layer of each circuit unit. The pixel definition layer in the pixel opening is removed, exposing the anode of the circuit unit. An evaporation or inkjet printing process is then used to form an organic light-emitting layer, and then a cathode is formed on the organic light-emitting layer.
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of Organic material
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water and oxygen cannot enter the light-emitting structure layer.
  • the packaging structure layer may be formed in the display area and the upper frame area, and the packaging structure layer in the upper frame area may be located on a side of the first packaging line FX1 close to the display area.
  • the display substrate provided by the present disclosure provides a base conductive layer between the double flexible layers of the base.
  • the base conductive layer includes a first connection line, and the first connection line passes through
  • the second connection line is connected to the data signal line, and the data routing is implemented in the display area, which can reduce the width of the lower frame and facilitate full-screen display.
  • a first overlapping via hole for connecting a first connecting line to a second connecting line and a second overlapping hole for connecting a second connecting line to a data signal line are both provided in the display area .
  • the hole-digging film layer of the first overlapping via hole includes a second flexible layer, the depth of the first overlapping via hole is large, with a depth of approximately 5 ⁇ m to 8 ⁇ m, making the first overlapping via hole area prone to packaging failure. , external water and oxygen will invade the light-emitting structure layer through the first overlapping via hole, affecting the reliability and life of the display device.
  • the first overlapping via hole connecting the first connection line and the second connection line is provided on the side of the first packaging line away from the display area, that is, the overlapping hole is provided on the package Outside the area, it can not only avoid packaging failure caused by the first overlapping via hole and reduce design risks, but also effectively reduce the difficulty of the packaging process, reduce the reliability risk of the packaging, and maximize the process quality and product quality.
  • the first overlapping via hole is arranged in the upper frame area and is located between the isolation dam and the crack dam. Since there are fewer film layers in the area between the isolation dam and the crack dam, the first overlapping via hole can be effectively ensured. In terms of the process quality of the via hole, the deeper first overlapping via hole has less impact on the film structure of the display area, takes up less space, and has low production cost.
  • the display substrate provided by the exemplary embodiment of the present disclosure uses the shielding conductive layer to connect to the base conductive layer through the first overlapping via hole, and the porous film layer is the second flexible layer and the second barrier layer, effectively reducing the first overlapping
  • the depth of the connecting via hole and the depth of the first overlapping via hole can be reduced by about 1 ⁇ m, which not only reduces the process difficulty, but also improves the connection quality and reliability of the first connecting line and the second connecting line, and improves product quality. Rate.
  • the display substrate usually includes a shielding conductive layer, the solution of using the shielding conductive layer for connection does not add a new film layer and uses a mature process, which can be well compatible with the existing preparation process. The process is simple to implement and easy to implement. , high production efficiency, low production cost and high yield rate.
  • FIG. 18 is a schematic cross-sectional structural view of another data connection line according to an exemplary embodiment of the present disclosure, which is a cross-sectional view along the B-B direction in FIG. 8 .
  • the main structure of the display substrate of this exemplary embodiment is basically similar to the main structure shown in Figure 9. The difference is that the first connection line 70 of this exemplary embodiment is provided on the base conductive layer.
  • the second connection line 80 is provided on the second conductive layer.
  • the first overlapping via DV1 may be provided in the upper frame area 310 , and the first overlapping via DV1 may be provided on a side of the first packaging line FX1 away from the display area 100 , and the second overlapping via DV1 may be disposed on a side of the first packaging line FX1 away from the display area 100 .
  • the via DV2 may be provided in the display area 100 , the data signal line 60 is connected to the second connection line 80 through the second overlapping via DV2, and the second connection line 80 is connected to the first connection line 70 through the first overlapping via DV1 .
  • this exemplary embodiment shows that the preparation process of the substrate may include the following operations.
  • the substrate may include a first flexible layer, a first barrier layer, a base conductive layer, and a second layer stacked on a glass carrier.
  • the flexible layer and the second barrier layer, and the base conductive layer pattern may at least include a plurality of first connection lines 70 provided in the display area 100 and the upper frame area 310 , and the end of the first connection line 70 away from the display area 100 is provided with a first connection line 70 .
  • the connection block 71, the first connection block 71 can be disposed on the side of the first packaging line FX1 away from the display area, as shown in Figure 10.
  • the process of forming the shielding conductive layer pattern may be basically the same as step (13) of the previous embodiment, except that the shielding conductive layer pattern may only include the shielding electrode 50 disposed in the display area 100, such as As shown in Figure 19.
  • the process of forming the semiconductor layer pattern may be substantially the same as step (14) of the foregoing embodiment, and the structure of the formed semiconductor layer may be substantially the same as that of the foregoing embodiment, as shown in FIG. 20 .
  • first conductive layer pattern Form a first conductive layer pattern.
  • the process of forming the first conductive layer pattern may be substantially the same as step (15) of the foregoing embodiment, and the structure of the formed first conductive layer may be substantially the same as that of the foregoing embodiment, as shown in FIG. 21 Show.
  • forming the first overlapping via pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed, patterning the third insulating film through a patterning process, and forming a layer covering the first conductive film.
  • the third insulating layer of The orthographic projection of the via hole DV1 on the substrate may be within the range of the orthographic projection of the first connection block 71 on the substrate, and the third insulating layer, the second insulating layer, and the first insulating layer in the first overlapping via hole DV1 , the second barrier layer and the second flexible layer are removed, exposing the surface of the first connection block 71, and the first overlapping via DV1 is configured to allow the subsequently formed second connection line to pass through the via hole and the first connection line 70 connection, as shown in Figure 22.
  • the process of forming the second conductive layer pattern may be basically the same as step (16) of the previous embodiment.
  • the formed second conductive layer pattern not only includes the initial signal line 31 and the second plate of the storage capacitor. 32 and the plate connection line 33, and includes a second connection line 80, as shown in Figure 23.
  • the structures of the initial signal line 31, the second plate 32 and the plate connection line 33 of this embodiment are basically the same as those of the previous embodiment.
  • the shape of the second connection line 80 may be a line shape in which the main body part extends along the second direction Y, and the end of the second connection line 80 away from the display area 100 (the first end of the second connection line 80 end) is provided with a second connection block 81.
  • the shape of the second connection block 81 may be a rectangular shape.
  • the second connection block 81 is connected to the first connection block 71 through the first overlapping via hole DV1.
  • the second end of the second connection line 80 extends to the display area 100, and the second end of the second connection line 80 is configured to be connected to a subsequently formed data signal line.
  • the process of forming the pattern of the fourth insulating layer may be basically the same as step (17) of the foregoing embodiment.
  • Multiple via holes are provided on the fourth insulating layer, and the structure of the multiple via holes may be the same as the foregoing implementation.
  • the example is basically the same, except that the fourth insulating layer in the second overlapping via hole DV2 is etched away, exposing the surface of the second end of the second connecting line 80, and the second overlapping via hole DV2 is configured In order to connect the subsequently formed data signal line to the second connection line 80 through the via hole, as shown in FIG. 24 .
  • the orthographic projection of the second overlapping via hole DV2 on the substrate does not overlap with the orthographic projection of the first overlapping via hole on the substrate.
  • the process of forming the third conductive layer pattern may be substantially the same as step (18) of the previous embodiment, and the structure of the formed third conductive layer may be substantially the same as that of the previous embodiment, as shown in FIG. 17 Show.
  • the first overlapping via connecting the first connection line and the second connection line is provided on the side of the first packaging line away from the display area, that is, the overlapping point is located in the packaging area.
  • it can not only avoid packaging failure caused by the first overlapping via hole and reduce design risks, but also effectively reduce the difficulty of the packaging process, reduce the reliability risk of the packaging, and maximize the process quality and product quality.
  • Figure 25 is a schematic plan view of a side frame area according to an exemplary embodiment of the present disclosure.
  • the side frame area 320 may include a circuit area 320A, a power line area 320B, a crack dam area 320C and a cutting area 320D sequentially arranged in a direction away from the display area 100 .
  • the circuit area 320A is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning signal line, the second scanning signal line and the light emission control line of the pixel driving circuit in the display area 100 .
  • the power line area 320B is connected to the circuit area 320A, and may include at least a frame power trace.
  • the frame power trace may be connected to the cathode of the light-emitting structure layer in the display area 100 through a plurality of frame overlapping electrodes.
  • the crack dam area 320C is connected to the power line area 320B, and may at least include a plurality of cracks provided on the composite insulation layer to form a crack dam, and the crack dam is configured to reduce the stress on the display area 100 and the circuit area 320A during the cutting process. , intercepting the cracks and propagating toward the display area 100 .
  • the cutting area 320D is connected to the crack dam area 320C and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the power line area 320B in the side frame area 320 may also be provided with a first isolation dam 410 and a second isolation dam 420.
  • the first isolation dam 410 and the second isolation dam 420 may be along a line parallel to the display screen. The direction of the area edge extends, and the distance between the second isolation dam 420 and the edge of the display area is greater than the distance between the first isolation dam 410 and the edge of the display area.
  • FIG. 26 is a schematic cross-sectional structural view of a side frame area according to an exemplary embodiment of the present disclosure, which is a cross-sectional view along the C-C direction in FIG. 25 .
  • the side frame area 320 of the display substrate may at least include a frame structure layer 330 disposed on the substrate 101 .
  • the substrate 101 of the side frame area 320D may include a stacked first flexible layer, a first barrier layer, a second flexible layer and a second barrier layer.
  • the side frame area 320 does not have a base conductive layer, and the base conductive layer Layers may be provided in the display area 100.
  • the frame structure layer 330 of the side frame area 320 may include at least a first gate circuit 331 , a second gate circuit 332 , a frame power supply trace 333 and a frame overlapping electrode 334 .
  • the first gate circuit 331 and the second gate circuit 332 may include a plurality of transistors and storage capacitors.
  • the first gate circuit 331 and the second gate circuit 332 are connected with the first scanning signal line and the second scanning signal line of the display area.
  • the line is connected to the light-emitting control line and configured to provide scanning signals and light-emitting control signals to the pixel driving circuit in the display area.
  • the frame overlapping electrode 334 overlaps with the frame power trace 333.
  • the cathode 304 of the display area 100 extends to the side frame area 320 and then overlaps with the frame overlapping electrode 334, thus realizing the connection between the cathode 304 of the display area and the side frame area 320. Connections between frame power traces 333.
  • the first gate circuit 331 and the second gate circuit 332 of the side frame area 320 and the pixel driving circuit of the display area 100 can be formed simultaneously through the same patterning process, and the frame overlapping electrode 334 can be formed with The anodes in the display area are arranged on the same layer and formed simultaneously through the same patterning process.
  • the frame structure layer 330 of the side frame area 320 may also include a first isolation dam 410, a second isolation dam 420, and a first encapsulation layer 401.
  • the first encapsulation layer 401 covers the first isolation dam 410 and the first isolation dam 410.
  • Figures 27 and 28 are schematic cross-sectional structural diagrams of a binding area according to an exemplary embodiment of the present disclosure.
  • Figure 27 illustrates the cross-sectional structure where the lead wires are located
  • Figure 28 illustrates the cross-sectional structure where the bonded power traces are located.
  • the binding area 200 may include at least a lead-out area 201 , a bending area 202 and a driving chip area 203 that are sequentially arranged in a direction away from the display area 100 .
  • the lead wire area 201 is connected to the display area 100 and may include at least a plurality of lead wires 220 and bound power traces 221.
  • the lead wires 220 and the first connection line 70 may be an integral structure connected to each other.
  • the bending area 202 is connected to the lead-out area 201 and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area 203 may at least include an integrated circuit and bonding pins.
  • the integrated circuit is configured to be connected to a plurality of lead lines 220 , and the bonding pins are configured to be bonded to an external flexible circuit board.
  • the bonding area 200 may include a second encapsulation area and a second non-encapsulation area divided by the second encapsulation line FX2 , and the second encapsulation area and the second non-encapsulation area may be along a direction away from the display area 100 Arranged in sequence, the side of the second packaging line FX2 close to the display area 100 is the second packaging area, and the side of the second packaging line FX2 away from the display area 100 is the second non-encapsulation area.
  • the first encapsulation layer 401 forms a second encapsulation line FX2 away from the boundary of the display area 100, and the second encapsulation line FX2 may be called a CVD boundary.
  • the binding area 200 of the display substrate may at least include the binding structure layer 210 disposed on the substrate 101 .
  • the substrate 101 may include a stacked first flexible layer, a first barrier layer, a base conductive layer, a second flexible layer, and a second barrier layer.
  • the base conductive layer may at least include The integrated structure of the first connection line 70 and the lead-out line 220 , that is, the lead-out line 220 (the first connection line 70 ) crosses the bending area 202 and the lead-out line area 201 from the driver chip area 203 and directly enters the display area 100 .
  • the lead wires By arranging the lead wires on the base conductive layer, the present disclosure can effectively reduce the bending radius of the binding area, which is beneficial to reducing the width of the lower frame.
  • the bonding structure layer 210 of the bonding area 200 may at least include a bonding power trace 221 and a bonding bonding electrode 222, the bonding bonding electrode 222 overlaps the bonding power trace 221,
  • the cathode 304 of the display area 100 extends to the bonding area 200 and overlaps with the bonding bonding electrode 222 , thus realizing the connection between the cathode 304 of the display area and the bonding power trace 221 of the bonding area 200 .
  • the bonding power traces 221 of the bonding region 200 and the frame power traces 333 of the side frame region 320 may be arranged on the same layer and formed simultaneously through the same patterning process.
  • the bonding bonding electrode 222 of the bonding area 200 can be placed on the same layer as the anode of the display area and formed simultaneously through the same patterning process.
  • the binding structure layer 210 of the binding area 200 may further include a first isolation dam 410 and a second isolation dam 420 , and the first isolation of the binding area 200 , the upper frame area 310 and the side frame area 320 The dam and the second isolation dam may be connected to each other to form a ring structure surrounding the display area 100 .
  • the base conductive layer of the binding area may further include a first power connection line 223
  • the binding structure layer 210 of the binding area may further include a second power connection line 224 .
  • the first end of the first power connection line 223 is connected to the binding pin, and the second end of the first power connection line 223 extends from the driver chip area 203 across the bending area 202 to the lead line area 201 and passes through the third bridge.
  • the via hole DV3 is connected to the second power connection line 224, and the second power connection line 224 is connected to the binding power trace 221 through the fourth overlapping via hole DV4.
  • the third overlapping via DV3 may be disposed in the second non-packaging area of the binding area 200 , that is, the third overlapping via DV3 may be disposed at a distance away from the second packaging line FX2 from the display area 100 . side.
  • the first power connection line 223 may be disposed in the base conductive layer of the substrate 101, and the second power connection line 224 may be disposed in the shielding conductive layer of the binding structure layer 210, or the second power connection line 223 may be disposed in the base conductive layer of the substrate 101.
  • the line 224 may be disposed in the first gate metal layer (GATE1) of the bonding structure layer 210, or the second power connection line 224 may be disposed in the second gate metal layer (GATE2) of the bonding structure layer 210.
  • the present disclosure can not only avoid packaging failure caused by the third overlapping via hole, but also reduce design risks. , and can effectively reduce the difficulty of the packaging process, reduce the reliability risk of packaging, and maximize the process quality and product quality.
  • the display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc., and the disclosure is not limited here.
  • the present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiments.
  • the display substrate includes a display area, a binding area located on one side of the display area in the second direction, and a frame area located on other sides of the display area, and the frame area at least includes
  • the display area has an upper frame area on one side away from the binding area and a side frame area located on at least one side of the display area in a first direction, where the first direction intersects the second direction;
  • the preparation method may include :
  • the substrate at least includes a first flexible layer, a second flexible layer and a base conductive layer disposed between the first flexible layer and the second flexible layer, the base conductive layer at least includes a first connection line;
  • a driving circuit layer is formed on the substrate.
  • the driving circuit layer at least includes a second connection line and a data signal line.
  • the second connection line is connected to the first connection line through a first overlapping via hole.
  • the data signal line is connected to the second connection line through a second overlapping via hole, and the first overlapping via hole is provided in the upper frame area.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板。包括显示区域(100)和边框区域(300)，边框区域(300)包括上边框区(310)和侧边框区(320)；在垂直于显示基板的平面上，显示基板包括基底(101)和驱动电路层(102)，基底(101)包括设置在第一柔性层(10A)和第二柔性层(10C)之间的基底导电层，基底导电层包括第一连接线(70)，驱动电路层(102)包括数据信号线(60)和第二连接线(80)，第二连接线(80)通过第一搭接过孔(DV1)与第一连接线(70)连接，数据信号线(60)通过第二搭接过孔(DV2)与第二连接线(80)连接，第一搭接过孔(DV1)设置在上边框区(310)。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域、位于所述显示区域第二方向一侧的绑定区域以及位于所述显示区域其它侧的边框区域，所述边框区域至少包括位于所述显示区域远离所述绑定区域一侧的上边框区和位于所述显示区域第一方向至少一侧的侧边框区，所述第一方向与所述第二方向交叉；在垂直于所述显示基板的平面上，所述显示基板包括基底和设置在所述基底上的驱动电路层，所述基底至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层，所述基底导电层至少包括第一连接线，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述上边框区。
在示例性实施方式中，所述上边框区包括沿着远离所述显示区域方向依次设置的第一封装区和第一非封装区，所述第一搭接过孔设置在所述第一非封装区。
在示例性实施方式中，所述上边框区包括沿着远离所述显示区域方向依次设置的隔离区和裂缝坝区，所述隔离区设置有隔离坝，所述裂缝坝区设置有裂缝坝，所述第一搭接过孔设置在所述隔离坝和所述裂缝坝之间。
在示例性实施方式中，所述驱动电路层至少包括在所述基底上依次设置的遮挡导电层、第一导电层、第二导电层和第三导电层，所述第二连接线和所述数据信号线设置在不同的导电层中。
在示例性实施方式中，所述数据信号线设置在所述第三导电层中；所述第二连接线设置在所述遮挡导电层中，或者，所述第二连接线设置在所述第一导电层中，或者，所述第二连接线设置在所述第二导电层中。
在示例性实施方式中，所述第一连接线的第一端与所述绑定区域的引出线连接，所述第一连接线的第二端经过所述显示区域延伸到所述上边框区后，通过所述第一搭接过孔与所述第二连接线的第一端连接。
在示例性实施方式中，所述第一连接线远离所述显示区域的端部设置有第一连接块，所述第一搭接过孔在所述基底上的正投影与所述第一连接块在所述基底上的正投影至少部分交叠。
在示例性实施方式中，所述第二连接线的第一端通过所述第一搭接过孔与所述第一连接线的第二端连接，所述第二连接线的的第二端延伸到所述显示区域后，通过所述第二搭接过孔与所述数据信号线连接。
在示例性实施方式中，所述第二连接线远离所述显示区域的端部设置有第二连接块，所述第一搭接过孔在所述基底上的正投影与所述第二连接块在所述基底上的正投影至少部分交叠。
在示例性实施方式中，所述第一搭接过孔在所述基底上的正投影与所述第二搭接过孔在所述基底上的正投影没有交叠。
在示例性实施方式中，所述绑定区域至少包括沿着远离所述显示区域方 向依次设置的引出线区、弯折区和驱动芯片区，所述基底导电层还包括引出线，所述引出线的第一端与所述驱动芯片区的集成电路连接，所述引出线的第二端经过所述弯折区延伸到所述引出线区后，与所述第一连接线的第一端连接。
在示例性实施方式中，所述引出线和所述第一连接线为相互连接的一体结构。
在示例性实施方式中，所述基底导电层还包括第一电源连接线，所述引出线区还包括第二电源连接线和电源走线，所述第一电源连接线的第一端与所述驱动芯片区的绑定引脚连接，所述第一电源连接线的第二端经过所述弯折区延伸到所述引出线区后，通过第三搭接过孔与所述第二电源连接线连接，所述第二电源连接线通过第四搭接过孔与所述电源走线连接。
在示例性实施方式中，所述引出线区包括沿着远离所述显示区域方向依次设置的第二封装区和第二非封装区，所述第三搭接过孔设置在所述第二非封装区。
在示例性实施方式中，所述侧边框区在所述基底上的正投影与所述基底导电层在所述基底上的正投影没有交叠。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括显示区域、位于所述显示区域第二方向一侧的绑定区域以及位于所述显示区域其它侧的边框区域，所述边框区域至少包括位于所述显示区域远离所述绑定区域一侧的上边框区和位于所述显示区域第一方向至少一侧的侧边框区，所述第一方向与所述第二方向交叉；所述制备方法包括：
形成基底，所述基底至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层，所述基底导电层至少包括第一连接线；
在所述基底上形成驱动电路层，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔 设置在所述上边框区。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6a和图6b为本公开示例性实施例一种显示基板的平面结构示意图；
图7a和图7b为本公开示例性实施例一种上边框区的结构示意图；
图8为本公开示例性实施例数据连接线的平面结构示意图；
图9为本公开示例性实施例一种数据连接线的剖面结构示意图；
图10为本公开一种显示基板中形成基底后的示意图；
图11为本公开一种显示基板中形成第一搭接过孔后的示意图；
图12为本公开一种显示基板中形成遮挡导电层后的示意图；
图13为本公开一种显示基板中形成半导体层后的示意图；
图14为本公开一种显示基板中形成第一导电层后的示意图；
图15为本公开一种显示基板中形成第二导电层后的示意图；
图16为本公开一种显示基板中形成第四绝缘层后的示意图；
图17为本公开一种显示基板中形成第三导电层后的示意图；
图18为本公开示例性实施例另一种数据连接线的剖面结构示意图；
图19为本公开另一种显示基板中形成遮挡导电层后的示意图；
图20为本公开另一种显示基板中形成半导体层后的示意图；
图21为本公开另一种显示基板中形成第一导电层后的示意图；
图22为本公开另一种显示基板中形成第一搭接过孔后的示意图；
图23为本公开另一种显示基板中形成第二导电层后的示意图；
图24为本公开另一种显示基板中形成第四绝缘层后的示意图；
图25为本公开实施例一种侧边框区的平面结构示意图；
图26为本公开实施例一种侧边框区的剖面结构示意图；
图27和图28为本公开实施例一种绑定区域的剖面结构示意图。
附图标记说明:
10A—第一柔性层；       10B—第一阻挡层；       10C—第二柔性层；
10D—第二阻挡层；       11—第一有源层；        12—第二有源层；
13—第三有源层；        14—第四有源层；        15—第五有源层；
16—第六有源层；        17—第七有源层；        21—第一扫描信号线；
22—第二扫描信号线；    23—发光控制线；        24—第一极板；
31—初始信号线；        32—第二极板；          33—极板连接线；
34—开口；              41—第一连接电极；      42—第二连接电极；
43—第三连接电极；      44—第一电源线；        50—遮挡电极；
60—数据信号线；        70—第一连接线；        71—第一连接块；
80—第二连接线；        81—第二连接块；        91—第一绝缘层；
92—第二绝缘层；        93—第三绝缘层；        94—第四绝缘层；
100—显示区域；         101—基底；             102—驱动电路层；
103—发光结构层；       104—封装结构层；       200—绑定区域；
201—引出线区；         202—弯折区；           203—驱动芯片区；
210—绑定结构层；       220—引出线；           221—绑定电源走线；
222—绑定搭接电极；     223—第一电源连接线；   224—第二电源连接线；
300—边框区域；         301—阳极；             302—像素定义层；
303—有机发光层；       304—阴极；             310—上边框区；
320—侧边框区；         330—边框结构层；       331—第一栅极电路；
332—第一栅极电路；     333—边框电源走线；     334—边框搭接电极；
401—第一封装层；       402—第二封装层；       403—第三封装层；
410—第一隔离坝；       420—第二隔离坝。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的 一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域100的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。扇出区连接到显示区域100，可以至少包括多条数据连接线，多条数据连接线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以至少包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据连接线连接。绑定引脚区可以至少包括多个绑定引脚(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描线、第二扫描线和发光控制线连接。电源线区连接到电路区，可以至少包括边框电源走线，边框电源走线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示 基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2、出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路。发光结构层103可以至少多个发光器件，发光器件可以至少包括阳极301、有机发光层303和阴极304，有机发光层303在阳极301和阴极304的驱动下出射相应颜色的光线。发光结构层103还可以包括像素定义层302， 像素定义层302覆盖阳极301，像素定义层302上设置有像素开口，像素开口暴露出阳极301的表面。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水氧无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。 当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第二扫描信号线S2连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第二扫描信号线S2时，第七晶体管T7将初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
下面以7个晶体管均为P型晶体管为例，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号使第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得初始信号线INIT的初始电压提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线 S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5和第六晶体管T6断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越 高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，数据扇出线设置在绑定区域的扇出区，由于扇出区的宽度小于显示区域的宽度，因而数据扇出线需要通过扇出走线方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，扇形区占用空间越大。此外，随着显示屏分辨率逐渐增加，扇出线的占用宽度会逐渐增加，导致下边框的窄化设计难度较大，下边框一直维持在2.0mm左右。
本公开示例性实施例提供了一种显示基板，采用数据连接线位于显示区域(Fanout in AA，简称FIAA)结构，多条数据连接线的一端与显示区域中的多条数据信号线对应连接，多条数据连接线的另一端延伸到绑定区域，与绑定区域的集成电路对应连接。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，有效减小了下边框宽度。
在示例性实施方式中，在平行于显示基板的平面上，显示基板可以至少包括显示区域、位于显示区域一侧的绑定区域和位于显示区域其它侧的边框区域，边框区域可以包括位于显示区域远离绑定区域一侧的上边框区和位于显示区域两侧的侧边框区。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。
在示例性实施方式中，基底可以至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层。显示区域的驱动电路层可以包括构成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路被配置为向所连接的发光器件输出相应的电流。显示区域的发光结构层可以包括构成像素阵列的多个子像素，至少一个子像素可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素驱动电路划分的区域。在 示例性实施方式中，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施方式中，本公开示例性实施例显示基板可以包括显示区域、位于所述显示区域第二方向一侧的绑定区域以及位于所述显示区域其它侧的边框区域，所述边框区域至少包括位于所述显示区域远离所述绑定区域一侧的上边框区和位于所述显示区域第一方向至少一侧的侧边框区，所述第一方向与所述第二方向交叉；在垂直于所述显示基板的平面上，所述显示基板包括基底和设置在所述基底上的驱动电路层，所述基底至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层，所述基底导电层至少包括第一连接线，所述驱动电路层至少包括第二连接线和数据信号线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述上边框区。
在示例性实施方式中，所述上边框区包括沿着远离所述显示区域方向依次设置的第一封装区和第一非封装区，所述第一搭接过孔设置在所述第一非封装区。
在示例性实施方式中，所述上边框区包括沿着远离所述显示区域方向依次设置的隔离区和裂缝坝区，所述隔离区设置有隔离坝，所述裂缝坝区设置有裂缝坝，所述第一搭接过孔设置在所述隔离坝和裂缝坝所述之间。
在示例性实施方式中，所述绑定区域至少包括沿着远离所述显示区域方向依次设置的引出线区、弯折区和驱动芯片区，所述基底导电层还包括引出线，所述引出线的第一端与所述驱动芯片区的集成电路连接，所述引出线的第二端经过所述弯折区延伸到所述引出线区后，与所述第一连接线的第一端连接。
在示例性实施方式中，所述基底导电层还包括第一电源连接线，所述引出线区还包括第二电源连接线和电源走线，所述第一电源连接线的第一端与所述驱动芯片区的绑定引脚连接，所述第一电源连接线的第二端经过所述弯折区延伸到所述引出线区后，通过第三搭接过孔与所述第二电源连接线连接， 所述第二电源连接线通过第四搭接过孔与所述电源走线连接。
在示例性实施方式中，所述引出线区包括沿着远离所述显示区域方向依次设置的第二封装区和第二非封装区，所述第三搭接过孔设置在所述第二非封装区。
在示例性实施方式中，所述侧边框区在所述基底上的正投影与所述基底导电层在所述基底上的正投影没有交叠。
在示例性实施方式中，所述驱动电路层至少包括在所述基底上依次设置的遮挡导电层、第一导电层、第二导电层和第三导电层，所述第二连接线和数据信号线设置在不同的导电层中。
在示例性实施方式中，所述数据信号线设置在所述第三导电层中；所述第二连接线设置在所述遮挡导电层中，或者，所述第二连接线设置在所述第一导电层中，或者，所述第二连接线设置在所述第二导电层中。
图6a和图6b为本公开示例性实施例一种显示基板的平面结构示意图，显示基板中的数据连接线采用FIAA结构，图6a示意了第一连接线的结构，图6b示意了数据信号线和第二连接线的结构。如图6a和图6b所示，在平行于显示基板的平面上，显示基板可以包括显示区域100、位于显示区域100第二方向Y一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。
在示例性实施方式中，显示区域100可以至少包括构成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以至少包括像素驱动电路。绑定区域200可以至少包括沿着远离显示区域100的方向依次设置的引出线区201和弯折区202，引出线区201可以包括多条引出线220，引出线220的第一端与绑定区域200中的集成电路连接，引出线220的第二端经过弯折区202延伸到引出线区201。边框区域300可以包括位于显示区域100第二方向Y的反方向(显示区域100远离绑定区域200)一侧的上边框区310和位于显示区域100第一方向X两侧的侧边框区320。
在示例性实施方式中，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向 Y交叉。在示例性实施方式中，第二方向Y可以是数据信号线的延伸方向(竖直方向)，第一方向X可以与第二方向Y垂直(水平方向)。
在示例性实施方式中，显示区域100可以包括多条数据连接线60，数据信号线60可以为主体部分沿着第二方向Y延伸的线形状，多条数据信号线60在第一方向X上以设定的间隔依次设置，每条数据信号线60与一个单元列中多个电路单元的像素驱动电路连接。
在示例性实施方式中，显示基板还可以包括多条第一连接线70和第二连接线80，第一连接线70和第二连接线80构成数据连接线。多条第一连接线70的第一端与引出线区201的多条引出线220对应连接，多条第一连接线70的第二端从引出线区201经过显示区域100延伸到上边框区310后，通过第一搭接过孔DV1与多条第二连接线80的第一端对应连接。多条第二连接线80的第二端从上边框区310延伸到显示区域100后，通过第二搭接过孔DV2与多条数据信号线60对应连接，形成第一搭接过孔DV1设置在上边框区310、第二搭接过孔DV2设置在显示区域100的数据连接线结构。
在示例性实施方式中，由于引出线220与绑定区域200中的集成电路连接，第一连接线70与引出线220连接，第二连接线80与第一连接线70连接，数据信号线60与第二连接线80连接，因而显示区域中的数据信号线60通过第二连接线80、第一连接线70和引出线220与绑定区域中的集成电路连接，实现了集成电路向数据信号线60提供数据信号。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，可以有效减小下边框宽度。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
在示例性实施方式中，数据连接线的数量与数据信号线的数量可以相同，或者，数据连接线的数量可以小于数据信号线的数量，本公开在此不做限定。
图7a为本公开示例性实施例一种上边框区的结构示意图，为图6a和图 6b中A区域的放大图，图7b为图7a中A-A向的剖视图。如图7a和图7b所示，在平行于显示基板的平面上，边框区域300的上边框区310可以位于显示区域100远离绑定区域200的一侧，上边框区310可以包括由第一封装线FX1划分的第一封装区和第一非封装区，第一封装线FX1可以是封装结构层覆盖上边框区310的边界，第一封装线FX1可以将上边框区310划分为沿着远离显示区域100方向依次设置的第一封装区和第一非封装区，第一封装线FX1靠近显示区域100的一侧为第一封装区，第一封装线FX1远离显示区域100的一侧为第一非封装区。在示例性实施方式中，第一封装区可以设置有第一隔离坝410和第二隔离坝420，第一非封装区可以包括沿着远离显示区域100的方向依次设置的裂缝坝区和切割区，裂缝坝区连接到第一封装区，可以至少包括在复合绝缘层上设置的多个裂缝，形成裂缝坝，裂缝坝被配置为在切割过程中减小显示区域100的受力，截断裂纹向显示区域100方向传递，切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，多个第一搭接过孔DV1可以设置在隔离区，即多个第一搭接过孔DV1可以设置在第一封装线FX远离显示区域100的一侧。
在示例性实施方式中，多个第一搭接过孔DV1可以设置在第二隔离坝和裂缝坝之间。
在示例性实施方式中，第一连接线70可以通过多个第一搭接过孔DV1与第二连接线80连接，以减小搭接电阻并提高连接可靠性。多个第一搭接过孔DV1可以沿着远离显示区域的方向依次设置。
在示例性实施方式中，一条第一连接线70可以通过两个第一搭接过孔DV1与一条第二连接线80连接，第一搭接过孔DV1的长度L1可以约为4μm至8μm，两个第一搭接过孔DV1之间的间距L2可以约为8μm至12μm，长度L1可以为第一搭接过孔第二方向Y的尺寸，间距L2可以为两个第一搭接过孔边缘之间的距离。例如，第一搭接过孔DV1的形状可以为矩形状，第一搭接过孔DV1的长度L1可以约为6μm，两个第一搭接过孔DV1之间的间距L2可以约为10μm。
在示例性实施方式中，沿着远离显示区域的方向，多个第一搭接过孔DV1的占用长度L可以约为20μm至50μm，占用长度L可以为第一搭接过孔靠近显示区域一侧的边缘与第一搭接过孔远离显示区域一侧的边缘之间的最大距离。
在示例性实施方式中，在平行于显示基板的平面上，第一搭接过孔DV1的形状可以包括如下任意一种或多种：三角形、矩形、五边形、六边形、圆形和椭圆形。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以包括基底101以及设置在基底101上的驱动电路层102。基底101可以至少包括第一连接线70，驱动电路层102可以至少包括数据信号线60和第二连接线80，第一连接线70通过第一搭接过孔DV1与第二连接线80连接，第二连接线80通过第二搭接过孔DV2与数据信号线60连接。
在示例性实施方式中，上边框区310还可以包括设置在驱动电路层102远离基底一侧的隔离结构层，隔离结构层可以至少包括第一隔离坝410、第二隔离坝420以及第一封装层401，第一隔离坝410和第二隔离坝420可以设置在第一封装线FX靠近显示区域100的一侧，第一封装层401覆盖第一隔离坝410和第二隔离坝420，第一封装层401远离显示区域100的边界形成第一封装线FX，第一封装线FX可以称为CVD边界。
在示例性实施方式中，第一连接线70可以设置在基底101的基底导电层中，数据信号线60可以设置在驱动电路层102的源漏金属层(SD)中，第二连接线80可以设置在驱动电路层102的遮挡导电层(SHL)中，或者，第二连接线80可以设置在驱动电路层102的第一栅金属层(GATE1)中，或者，第二连接线80可以设置在驱动电路层102的第二栅金属层(GATE2)中。
图8为本公开示例性实施例数据连接线的平面结构示意图，为图6a和图6b中B区域的放大图。如图8所示，在平行于显示基板的平面上，显示区域100可以包括构成多个单元行和多个单元列的多个电路单元，上边框区310可以包括由第一封装线FX1划分的第一封装区和第一非封装区，第一封装区和第一非封装区可以沿着远离显示区域100方向依次设置，第一封装线FX1 靠近显示区域100的一侧为第一封装区，第一封装线FX1远离显示区域100的一侧为第一非封装区。
在示例性实施方式中，至少一个电路单元可以包括像素驱动电路，像素驱动电路可以至少包括多个晶体管和存储电容，数据信号线60与一个单元列的多个像素驱动电路连接，数据信号线60被配置为向像素驱动电路提供数据信号。
在示例性实施方式中，显示区域100可以至少包括第一连接线70，上边框区310可以至少包括第二连接线80，连接第一连接线70和第二连接线80的第一搭接过孔DV1可以设置在上边框区310，且第一搭接过孔DV1可以设置在第一封装线FX1远离显示区域100的一侧，连接第二连接线80和数据信号线60的第二搭接过孔DV2可以设置在显示区域100，或者，第二搭接过孔DV2可以设置在上边框区310，或者，第二搭接过孔DV2可以设置在显示区域100和上边框区310的交界区域。
在示例性实施方式中，第一连接线70经过显示区域100延伸到上边框区310后，通过第一搭接过孔DV1与第二连接线80连接，第二连接线80从上边框区310延伸到显示区域100后，通过第二搭接过孔DV2与数据信号线60连接。
图9为本公开示例性实施例一种数据连接线的剖面结构示意图，为图8中B-B向的剖视图。如图9所示，在垂直于显示基板的平面上，显示基板可以至少包括设置在基底101上的驱动电路层102。在示例性实施方式中，基底101可以至少包括第一柔性层10A、第二柔性层10C以及设置在第一柔性层10A和第二柔性层10C之间的基底导电层，基底导电层可以至少包括第一连接线70。驱动电路层102可以至少包括数据信号线60和第二连接线80，数据信号线60通过第二搭接过孔DV2与第二连接线80连接，第二连接线80通过第一搭接过孔DV1与第一连接线70连接。
在示例性实施方式中，驱动电路层102可以至少包括在基底101上依次设置的遮挡导电层、第一绝缘层91、半导体层、第二绝缘层92、第一导电层、第三绝缘层93、第二导电层、第四绝缘层94和第三导电层。遮挡导电层可以至少包括第二连接线80，半导体层可以至少包括像素驱动电路的多个晶体 管的有源层，第一导电层可以至少包括多个晶体管的栅电极和存储电容的第一极板，第二导电层可以至少包括存储电容的第二极板，第三导电层可以至少包括数据信号线60。
在示例性实施方式中，基底101还可以包括第一阻挡层10B和第二阻挡层10D，第一阻挡层10B设置在第一柔性层10A和基底导电层之间，第二阻挡层10D设置在第二柔性层10C远离第一柔性层10A的一侧。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开在此不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以图6a和图6b中B区域为例，本示例性实施例显示基板的制备过程可以包括如下操作。
(11)制备基底。在示例性实施方式中，制备基底可以包括：先在玻璃载板上涂布一层第一柔性材料，固化成膜后形成第一柔性层10A。然后在第一柔性层10A上依次沉积第一阻挡薄膜和基底导电薄膜，通过图案化工艺对基底导电薄膜进行图案化，形成覆盖第一柔性层10A的第一阻挡(Barrier)层10B，以及设置在第一阻挡层10B上的基底导电层图案。然后再涂布一层第二柔性材料，固化成膜后形成覆盖基底导电层图案的第二柔性层10C。然 后，再沉积第二阻挡薄膜，形成覆盖第二柔性层10C的第二阻挡层10D，如10所示。在示例性实施方式中，基底导电层可以称为第0源漏金属(SD0)层。
在示例性实施方式中，基底导电层图案可以至少包括设置在显示区域100和上边框区310的多条第一连接线70。
在示例性实施方式中，第一连接线70的形状可以为主体部分沿着第二方向Y延伸的线形状，第一连接线70的第一端与绑定区域中的引出线连接，第一连接线70的第二端跨过显示区域100延伸到上边框区310。
在示例性实施方式中，第一连接线70远离显示区域100的端部(第一连接线70的第二端)设置有第一连接块71，第一连接块71的形状可以为矩形状，第一连接块71与第一连接线70可以为相互连接的一体结构，第一连接块71被配置为通过第一搭接过孔与后续形成的第二连接线连接。
在示例性实施方式中，第一连接块71可以设置在第一封装线FX1远离显示区域的一侧。
在示例性实施方式中，多个第一连接线70可以沿着第一方向X间隔设置，多个第一连接线70的设置位置可以根据走线均匀性进行设置，本公开在此不做限定。
在示例性实施方式中，第一柔性层和第二柔性层的材料可以包括但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。第一阻挡层和第二阻挡层的材料可以包括但不限于硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，用于提高基底的抗水氧能力。基底导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料。例如，基底导电层可以采用金属钼。
在示例性实施方式中，基底导电层可以采用钛/铝/钛(Ti/Al/Ti)的复合结构，有利于降低第一连接线的电阻。虽然第一连接线延伸到上边框区增加了第一连接线的长度，但通过多膜层和多条并联等结构设计，可以有效降低 第一连接线的电阻。
本公开示例性实施例显示基板，通过在基底的双柔性层之间设置基底导电层，基底导电层包括在显示区域和上边框区实现扇出功能的第一连接线，有利于减小绑定区域的走线密度。
(12)形成第一搭接过孔图案。在示例性实施方式中，形成第一搭接过孔图案可以包括：通过图案化工艺对第二阻挡层和第二柔性层进行图案化，形成多个第一搭接过孔DV1，如图11所示。
在示例性实施方式中，多个第一搭接过孔DV1可以设置在第一封装线FX1远离显示区域100的一侧，即第一搭接过孔DV1可以设置在上边框区310内的非封装区。
在示例性实施方式中，第一搭接过孔DV1在基底上的正投影可以位于第一连接块71在基底上的正投影的范围之内，第一搭接过孔DV1内的第二阻挡层和第二柔性层被去掉，暴露出第一连接块71的表面，第一搭接过孔DV1被配置为使后续形成的第二连接线通过该过孔与第一连接块71连接。
在示例性实施方式中，第一搭接过孔DV1的形状可以为如下任意一种或多种：三角形、矩形、五边形、六边形、圆形和椭圆形。
(13)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在第二阻挡层上形成遮挡导电层(SHL)图案，如图12所示。
在示例性实施方式中，遮挡导电层图案可以至少包括设置在显示区域100的遮挡电极50，以及设置在显示区域100和上边框区310的第二连接线80。
在示例性实施方式中，遮挡电极50的形状可以为矩形状，可以设置在显示区域100的每个电路单元中，遮挡电极50被配置为对像素驱动电路的至少一个晶体管进行遮挡，减少光线对晶体管电学特性的影响。此外，遮挡电极50还可以被配置为抑制碰撞电离产生的电子在沟道内部的聚集与减弱沟道焦耳热的聚集等。
在示例性实施方式中，第二连接线80的形状可以为主体部分沿着第二 方向Y延伸的线形状，第二连接线80远离显示区域100的端部(第二连接线80的第一端)设置有第二连接块81，第二连接块81的形状可以为矩形状，第二连接块81通过第一搭接过孔DV1与第一连接块71连接。第二连接线80的第二端延伸到显示区域100，第二连接线80的第二端被配置为与后续形成的数据信号线连接。
(14)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖遮挡导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图13所示。
在示例性实施方式中，显示区域中每个电路单元的半导体层图案可以至少包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构。在第二方向Y上，本单元行电路单元中的第六有源层16与下一单元行电路单元中的第七有源层17相互连接。
在示例性实施方式中，在第一方向X上，第二有源层12和第六有源层16可以位于本电路单元中第三有源层13的同一侧，第四有源层14和第五有源层15可以位于本电路单元中第三有源层13的同一侧，第二有源层12和第四有源层14可以位于本电路单元的第三有源层13的不同侧。在第二方向Y上，第一有源层11、第二有源层12、第四有源层14和第七有源层17可以位于本电路单元中第三有源层13第二方向Y的反方向的一侧，第五有源层15和第六有源层16可以位于本电路单元中第三有源层13第二方向Y的一侧。
在示例性实施方式中，第三有源层13在基底上的正投影可以位于遮挡电极50在基底上的正投影的范围之内，遮挡电极50可以对第三有源层13进行遮挡，减少光线对驱动晶体管电学特性的影响。
在示例性实施方式中，第一有源层11的形状可以呈“n”字形，第二有源层12和第五有源层15的形状可以呈“L”字形，第三有源层13的形状可以呈“Ω”字形，第四有源层14、第六有源层16和第七有源层17的形状可以呈“I”字形。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层11的第一区11-1可以作为第七有源层17的第一区17-1，第一有源层11的第二区11-2可以作为第二有源层12的第一区12-1，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2可以同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2可以作为第七有源层17的第二区17-2，第四有源层14的第一区14-1和第五有源层15的第一区15-1可以单独设置。
在示例性实施方式中，半导体层在基底上的正投影与第二连接线80在基底上的正投影没有交叠。
(15)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图14所示。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，显示区域中每个电路单元的第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24。
在示例性实施方式中，第一极板24的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的线形状，第一扫描信号线21可以位于本电路单元的第一极板24第二方向Y的反方向的一侧。每个电路单元的第一扫描信号线21设置有栅极块，栅极块的第一端与第一扫描信号线21连接，栅极块的第二端向着远离第一极板24的方向延伸。第一扫描信号线21和栅极块与本电路单元的第二有源层相重叠的区域作为双栅结构的第二晶体管T2的栅电极，第一扫 描信号线21与本电路单元的第四有源层相重叠的区域作为第四晶体管T4的栅电极。
在示例性实施方式中，第二扫描信号线22的形状可以为主体部分沿着第一方向X延伸的线形状，第二扫描信号线22可以位于本电路单元的第一扫描信号线21远离第一极板24的一侧，第二扫描信号线22与本电路单元的第一有源层相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与本电路单元的第七有源层相重叠的区域作为第七晶体管T7的栅电极。
在示例性实施方式中，发光控制线23的形状可以为主体部分沿着第一方向X延伸的线形状，发光控制线23可以位于本电路单元的第一极板24第二方向Y的一侧，发光控制线23与本电路单元的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与本电路单元的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22和发光控制线23可以为等宽度设计，或者可以为非等宽度设计，可以为直线，或者可以为折线，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第七有源层的第一区和第二区均被导体化。
(16)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图15所示。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，显示区域中每个电路单元的第二导电层图案至少包括：初始信号线31、存储电容的第二极板32和极板连接线33。
在示例性实施方式中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影至少部分交叠，第二极板32可以作为存储电容的另一个极板，第一极板24和第二极板32构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板32上设置有开口34，开口34的形状可以为矩形状，可以位于第二极板32的中部，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施方式中，开口34被配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施方式中，一个单元行中相邻两个子像素中的第二极板32可以通过极板连接线33相互连接。例如，第N-1列的第二极板32和第N列的第二极板32可以通过极板连接线33相互连接。又如，第N列的第二极板32和第N+1列的第二极板32通过极板连接线33相互连接。在示例性实施方式中，由于每个电路单元中的第二极板32与后续形成的第一电源线连接，通过将相邻电路单元的第二极板32形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，可以保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，初始信号线31的形状可以为主体部分沿着第一方向X延伸的线形状，初始信号线31可以位于本电路单元的第二扫描信号线22远离第一扫描信号线21的一侧，初始信号线31被配置为与后续形成的第一晶体管T1的第一极(也是第七晶体管T7的第一极)连接。
(17)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图16所示。
在示例性实施方式中，显示区域中每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第 六过孔V6、第七过孔V7和第八过孔V8。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一极板24连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面，第二过孔V2被配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在示例性实施方式中，第二过孔V2可以是多个，多个第二过孔V2可以沿着第二方向Y依次设置，以提高连接可靠性。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第一电源线通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极(也是第七晶体管T7的第二极)通过该过孔与第六有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的数据信号线通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第六 过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第六过孔V6被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第一有源层的第一区(也是第七有源层的第一区)在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出的第一有源层的第一区表面，第七过孔V7被配置为使后续形成的第一晶体管T1的第一极(也是第七晶体管T7的第一极)通过该过孔与第一有源层的第一区(也是第七有源层的第一区)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于初始信号线31在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面，第八过孔V8被配置为使后续形成的第一晶体管T1的第一极(也是第七晶体管T7的第一极)通过该过孔与初始信号线31连接。
在示例性实施方式中，多个过孔还包括第二搭接过孔DV2，第二搭接过孔DV2可以设置在部分电路单元中。第二搭接过孔DV2在基底上的正投影位于第二连接线80的第二端在基底上的正投影的范围之内，第二搭接过孔DV2内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第二连接线80的第二端的表面，第二搭接过孔DV2被配置为使后续形成的数据信号线通过该过孔与第二连接线80连接。
在示例性实施方式中，第二搭接过孔DV2在基底上的正投影与第一搭接过孔在基底上的正投影没有交叠。
(18)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图17所示。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，显示区域中每个电路单元的第三导电层至少包括：第一连接电极41、第二连接电极42、第三连接电极43、第一电源线44和数 据信号线60。
在示例性实施方式中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的直线状，第一连接电极41的第一端通过第一过孔V1与第一极板24连接，第一连接电极41的第二端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，使第一极板24、第一有源层的第二区和第二有源层的第一区具有相同的电位。在示例性实施方式中，第一连接电极41可以同时作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施方式中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的折线状，第二连接电极42的第一端通过第八过孔V8与初始信号线31连接，第二连接电极42的第二端通过第七过孔V7与第一有源层的第一区(也是第七有源层的第一区)连接。在示例性实施方式中，第二连接电极42可以同时作为第一晶体管T1的第一极和第七晶体管T7的第一极。
在示例性实施方式中，第三连接电极43的形状可以为块形状，第三连接电极43通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第三连接电极43可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第三连接电极43被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第一电源线44的形状可以为主体部分沿着第二方向Y延伸的直线状，一方面，第一电源线44通过第二过孔V2与第二极板32连接，另一方面，第一电源线44通过第三过孔V3与第五有源层的第一区连接，实现了将电源信号写入第五晶体管T5的第一极，且第二极板32和第五晶体管T5的第一极具有相同的电位。
在示例性实施方式中，数据信号线60的形状可以为主体部分沿着第二方向Y延伸的直线状，数据信号线60通过第五过孔V5与第四有源层的第一区连接，实现了将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，数据信号线60还通过第二搭接过孔DV2与第二连接线80连接。由于第二连接线80通过第一搭接过孔与第一连接线70连接，因而实现了显示区域100的数据信号线60通过第一连接线70和第二连接线80与绑定区域的引出线的连接。
后续制备工艺中，可以包括形成第一平坦层、形成第四导电层和形成第二平坦层等工艺，在玻璃载板上制备完成驱动电路层。
在示例性实施方式中，在平行于显示基板的平面上，显示区域的驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，像素驱动电路分别与第一扫描信号线21、第二扫描信号线22、发光控制线23、初始信号线31、第一电源线44和数据信号线60连接。显示区域和上边框区的驱动电路层可以包括多条第一连接线70和多条第二连接线80，第二连接线80通过第一搭接过孔DV1与第一连接线70连接，数据信号线60通过第二搭接过孔DV2与第二连接线80。
在示例性实施方式中，在垂直于显示基板的平面上，驱动电路层可以设置在基底上。基底可以包括叠设的第一柔性层10A、第一阻挡层10B、基底导电层、第二柔性层10C和第二阻挡层10D，基底导电层可以至少包括位于显示区域和上边框区的第一连接线70。驱动电路层可以至少包括在基底上依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层和第三导电层。遮挡导电层可以至少包括位于显示区域和上边框区的第二连接线80，第二连接线80通过第一搭接过孔DV1与第一连接线70连接。半导体层可以至少包括第一晶体管至第七晶体管的有源层，第一导电层可以至少包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24，第二导电层可以至少包括初始信号线31、存储电容的第二极板32和极板连接线33，第三导电层可以至少包括第一连接电极41、第二连接电极42、第三连接电极43、第一电源线44和数据信号线60，数据信号线60通过第二搭接孔DV2与第二连接线80连接。
在示例性实施方式中，遮挡导电层、第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、 多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层和第三绝缘层可以称为栅绝缘(GI)层，第四绝缘层可以称为层间绝缘(ILD)层。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或者聚噻吩等材料，即本发明实施例适用于基于氧化物(Oxide)技术、硅技术或者有机物技术制造的薄膜晶体管。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层依次制备发光结构层和封装结构层。
在示例性实施方式中，制备发光结构层可以包括：先形成阳极导电层，阳极导电层可以至少包括多个阳极图案。随后形成像素定义层，每个电路单元的像素定义层上设置有像素开口，像素开口内的像素定义层被去掉，暴露出所在电路单元的阳极。随后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水氧无法进入发光结构层。
在示例性实施方式中，封装结构层可以形成在显示区域和上边框区，上边框区中的封装结构层可以位于第一封装线FX1靠近显示区域的一侧。
从以上描述的显示基板的结构以及制备过程可以看出，本公开提供的显示基板，通过在基底的双柔性层之间设置基底导电层，基底导电层包括第一连接线，第一连接线通过第二连接线与数据信号线连接，在显示区域实现了数据走线，可以缩减下边框宽度，有利于实现全面屏显示。
一种采用FIAA结构的显示基板中，实现第一连接线与第二连接线连接的第一搭接过孔以及实现第二连接线与数据信号线连接的第二搭接孔均设置在显示区域。研究表明，由于第一搭接过孔的挖孔膜层包括第二柔性层，第一搭接过孔的深度大，深度约为5μm至8μm，使得第一搭接过孔区域易导致封装失效，外界水氧会通过第一搭接过孔侵入发光结构层，影响显示装置的信赖性寿命。本公开示例性实施例提供的显示基板，通过将连接第一连接线 和第二连接线的第一搭接过孔设置在第一封装线远离显示区域的一侧，即将搭接孔设置在封装区之外，不仅可以避免第一搭接过孔引起的封装失效，降低设计风险，而且可以有效降低封装工艺的难度，降低封装的信耐性风险，最大限度地提高了工艺质量和产品质量。
本公开通过将第一搭接过孔设置在上边框区，且位于隔离坝和裂缝坝之间，由于隔离坝和裂缝坝之间区域的膜层较少，因而可以有效保证开设第一搭接过孔的工艺质量，开设较深的第一搭接过孔对显示区域的膜层结构影响较小，占用空间小，生产成本低。
本公开示例性实施例提供的显示基板，利用遮挡导电层通过第一搭接过孔与基底导电层连接，挖孔膜层为第二柔性层和第二阻挡层，有效减小了第一搭接过孔的深度，第一搭接过孔的深度可以减小约1μm左右，不仅降低了工艺难度，而且提高了第一连接线和第二连接线的连接质量和可靠性，提高了产品良品率。由于显示基板中通常包括遮挡导电层，因而利用遮挡导电层进行连接的方案，既没有增加新的膜层，又采用成熟工艺，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图18为本公开示例性实施例另一种数据连接线的剖面结构示意图，为图8中B-B向的剖视图。如图18所示，本示例性实施例显示基板的主体结构与前述图9所示主体结构基本上相近，所不同的是，本示例性实施例的第一连接线70设置在基底导电层，第二连接线80设置在第二导电层。
在示例性实施方式中，第一搭接过孔DV1可以设置在上边框区310，且第一搭接过孔DV1可以设置在第一封装线FX1远离显示区域100的一侧，第二搭接过孔DV2可以设置在显示区域100，数据信号线60通过第二搭接过孔DV2与第二连接线80连接，第二连接线80通过第一搭接过孔DV1与第一连接线70连接。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括如下操作。
(21)制备基底。在示例性实施方式中，制备基底的过程与前述实施例步骤(11)可以基本上相同，基底可以包括在玻璃载板叠设的第一柔性层、 第一阻挡层、基底导电层、第二柔性层和第二阻挡层，基底导电层图案可以至少包括设置在显示区域100和上边框区310的多条第一连接线70，第一连接线70远离显示区域100的端部设置有第一连接块71，第一连接块71可以设置在第一封装线FX1远离显示区域的一侧，如图10所示。
(22)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案的过程与前述实施例步骤(13)可以基本上相同，所不同的是，遮挡导电层图案可以仅包括设置在显示区域100的遮挡电极50，如图19所示。
(23)形成半导体层图案。在示例性实施方式中，形成半导体层图案的过程与前述实施例步骤(14)可以基本上相同，所形成的半导体层的结构可以与前述实施例基本上相同，如图20所示。
(24)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案的过程与前述实施例步骤(15)可以基本上相同，所形成的第一导电层的结构可以与前述实施例基本上相同，如图21所示。
(25)形成第一搭接过孔图案。在示例性实施方式中，形成第一搭接过孔图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，第三绝缘层上开设有多个第一搭接过孔DV1，多个第一搭接过孔DV1可以设置在上边框区310内的非封装区，第一搭接过孔DV1在基底上的正投影可以位于第一连接块71在基底上的正投影的范围之内，第一搭接过孔DV1内的第三绝缘层、第二绝缘层、第一绝缘层、第二阻挡层和第二柔性层被去掉，暴露出第一连接块71的表面，第一搭接过孔DV1被配置为使后续形成的第二连接线通过该过孔与第一连接线70连接，如图22所示。
(26)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案的过程与前述实施例步骤(16)可以基本上相同，所形成的第二导电层图案不仅包括初始信号线31、存储电容的第二极板32和极板连接线33，而且包括第二连接线80，如图23所示。
在示例性实施方式中，本实施例初始信号线31、第二极板32和极板连接线33的结构与前述实施例基本上相同。
在示例性实施方式中，第二连接线80的形状可以为主体部分沿着第二方向Y延伸的线形状，第二连接线80远离显示区域100的端部(第二连接线80的第一端)设置有第二连接块81，第二连接块81的形状可以为矩形状，第二连接块81通过第一搭接过孔DV1与第一连接块71连接。第二连接线80的第二端延伸到显示区域100，第二连接线80的第二端被配置为与后续形成的数据信号线连接。
(27)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案的过程与前述实施例步骤(17)可以基本上相同，第四绝缘层上设置有多个过孔，多个过孔的结构可以与前述实施例基本上相同，所不同的是，第二搭接过孔DV2内的第四绝缘层被刻蚀掉，暴露出第二连接线80的第二端的表面，第二搭接过孔DV2被配置为使后续形成的数据信号线通过该过孔与第二连接线80连接，如图24所示。
在示例性实施方式中，第二搭接过孔DV2在基底上的正投影与第一搭接过孔在基底上的正投影没有交叠。
(28)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案的过程与前述实施例步骤(18)可以基本上相同，所形成的第三导电层的结构可以与前述实施例基本上相同，如图17所示。
本公开示例性实施例提供的显示基板，通过将连接第一连接线和第二连接线的第一搭接过孔设置在第一封装线远离显示区域的一侧，即将搭接点位于封装区之外，不仅可以避免第一搭接过孔引起的封装失效，降低设计风险，而且可以有效降低封装工艺的难度，降低封装的信耐性风险，最大限度地提高了工艺质量和产品质量。
图25为本公开示例性实施例一种侧边框区的平面结构示意图。如图25所示，在平行于显示基板的平面上，侧边框区320可以包括沿着远离显示区域100的方向依次设置的电路区320A、电源线区320B、裂缝坝区320C和切割区320D。电路区320A连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描信号线、第二扫描信号线和发光控制线连接。电源线区320B连接到电路区320A，可以至少包括边框电源走线，边框电源走线可以通过多个边框搭接电极与显示区域 100中发光结构层的阴极连接。裂缝坝区320C连接到电源线区320B，可以至少包括在复合绝缘层上设置的多个裂缝，形成裂缝坝，裂缝坝被配置为在切割过程中减小显示区域100和电路区320A的受力，截断裂纹向显示区域100方向传递。切割区320D连接到裂缝坝区320C，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，侧边框区320中的电源线区320B还可以设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420可以沿着平行于显示区域边缘的方向延伸，第二隔离坝420与显示区域边缘的距离大于第一隔离坝410与显示区域边缘的距离。
图26为本公开示例性实施例一种侧边框区的剖面结构示意图，为图25中C-C向的剖视图。如图26所示，在垂直于显示基板的平面上，显示基板的侧边框区320可以至少包括设置在基底101上的边框结构层330。
在示例性实施方式中，侧边框区320D的基底101可以包括叠设的第一柔性层、第一阻挡层、第二柔性层和第二阻挡层，侧边框区320没有基底导电层，基底导电层可以设置在显示区域100。
在示例性实施方式中，侧边框区320的边框结构层330可以至少包括第一栅极电路331、第二栅极电路332、边框电源走线333和边框搭接电极334。第一栅极电路331和第二栅极电路332可以包括多个晶体管和存储电容组成，第一栅极电路331和第二栅极电路332与显示区域的第一扫描信号线、第二扫描信号线和发光控制线连接，被配置为向显示区域的像素驱动电路提供扫描信号和发光控制信号。边框搭接电极334与边框电源走线333搭接，显示区域100的阴极304延伸到侧边框区320后与边框搭接电极334搭接，因而实现了显示区域的阴极304与侧边框区320的边框电源走线333之间的连接。
在示例性实施方式中，侧边框区320的第一栅极电路331和第二栅极电路332与显示区域100的像素驱动电路可以通过相同的图案化工艺同步形成，边框搭接电极334可以与显示区域的阳极同层设置，且通过同一次图案化工艺同步形成。
在示例性实施方式中，侧边框区320的边框结构层330还可以包括第一 隔离坝410、第二隔离坝420以及第一封装层401，第一封装层401覆盖第一隔离坝410和第二隔离坝420。
图27和图28为本公开示例性实施例一种绑定区域的剖面结构示意图，图27示意了引出线所在位置的剖面结构，图28示意了绑定电源走线所在位置的剖面结构。在示例性实施方式中，绑定区域200可以至少包括沿着远离显示区域100的方向依次设置的引出线区201、弯折区202和驱动芯片区203。引出线区201连接到显示区域100，可以至少包括多条引出线220和绑定电源走线221，引出线220与第一连接线70可以为相互连接的一体结构。弯折区202连接到引出线区201，可以包括设置有凹槽的复合绝缘层，凹槽被配置为使绑定区域弯折到显示区域的背面。驱动芯片区203可以至少包括集成电路和绑定引脚，集成电路被配置为与多条引出线220连接，绑定引脚被配置为与外部的柔性线路板绑定连接。
在示例性实施方式中，绑定区域200可以包括由第二封装线FX2划分的第二封装区和第二非封装区，第二封装区和第二非封装区可以沿着远离显示区域100方向依次设置，第二封装线FX2靠近显示区域100的一侧为第二封装区，第二封装线FX2远离显示区域100的一侧为第二非封装区。在示例性实施方式中，第一封装层401远离显示区域100的边界形成第二封装线FX2，第二封装线FX2可以称为CVD边界。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板的绑定区域200可以至少包括设置在基底101上的绑定结构层210。
如图27所示，在示例性实施方式中，基底101可以包括叠设的第一柔性层、第一阻挡层、基底导电层、第二柔性层和第二阻挡层，基底导电层可以至少包括一体结构的第一连接线70和引出线220，即引出线220(第一连接线70)从驱动芯片区203跨过弯折区202和引出线区201，直接进入显示区域100。本公开通过将引出线设置在基底导电层，可以有效减小绑定区域的弯折半径，有利于减小下边框宽度。
在示例性实施方式中，绑定区域200的绑定结构层210可以至少包括绑定电源走线221和绑定搭接电极222，绑定搭接电极222与绑定电源走线221搭接，显示区域100的阴极304延伸到绑定区域200后与绑定搭接电极222 搭接，因而实现了显示区域的阴极304与绑定区域200的绑定电源走线221之间的连接。
在示例性实施方式中，绑定区域200的绑定电源走线221与侧边框区320的边框电源走线333可以同层设置，且通过同一次图案化工艺同步形成。绑定区域200的绑定搭接电极222可以与显示区域的阳极同层设置，且通过同一次图案化工艺同步形成。
在示例性实施方式中，绑定区域200的绑定结构层210还可以包括第一隔离坝410和第二隔离坝420，绑定区域200、上边框区310和侧边框区320的第一隔离坝和第二隔离坝可以相互连接，形成环绕显示区域100的环形结构。
如图28所示，在示例性实施方式中，绑定区域的基底导电层还可以包括第一电源连接线223，绑定区域的绑定结构层210还可以包括第二电源连接线224。第一电源连接线223的第一端与绑定引脚连接，第一电源连接线223的第二端从驱动芯片区203跨过弯折区202延伸到引出线区201后，通过第三搭接过孔DV3与第二电源连接线224连接，第二电源连接线224通过第四搭接过孔DV4与绑定电源走线221连接。
在示例性实施方式中，第三搭接过孔DV3可以设置在绑定区域200的第二非封装区，即第三搭接过孔DV3可以设置在第二封装线FX2远离显示区域100的一侧。
在示例性实施方式中，第一电源连接线223可以设置在基底101的基底导电层中，第二电源连接线224可以设置在绑定结构层210的遮挡导电层中，或者，第二电源连接线224可以设置在绑定结构层210的第一栅金属层(GATE1)中，或者，第二电源连接线224可以设置在绑定结构层210的第二栅金属层(GATE2)中。
本公开通过将连接第一电源连接线223和第二电源连接线224的第三搭接过孔DV3设置在封装区之外，不仅可以避免第三搭接过孔引起的封装失效，降低设计风险，而且可以有效降低封装工艺的难度，降低封装的信耐性风险，最大限度地提高了工艺质量和产品质量。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括显示区域、位于所述显示区域第二方向一侧的绑定区域以及位于所述显示区域其它侧的边框区域，所述边框区域至少包括位于所述显示区域远离所述绑定区域一侧的上边框区和位于所述显示区域第一方向至少一侧的侧边框区，所述第一方向与所述第二方向交叉；所述制备方法可以包括：
形成基底，所述基底至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层，所述基底导电层至少包括第一连接线；
在所述基底上形成驱动电路层，所述驱动电路层至少包括第二连接线和数据信号线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述上边框区。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种显示基板，包括显示区域、位于所述显示区域第二方向一侧的绑定区域以及位于所述显示区域其它侧的边框区域，所述边框区域至少包括位于所述显示区域远离所述绑定区域一侧的上边框区和位于所述显示区域第一方向至少一侧的侧边框区，所述第一方向与所述第二方向交叉；在垂直于所述显示基板的平面上，所述显示基板包括基底和设置在所述基底上的驱动电路层，所述基底至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层，所述基底导电层至少包括第一连接线，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述上边框区。
  2. 根据权利要求1所述的显示基板，其中，所述上边框区包括沿着远离所述显示区域方向依次设置的第一封装区和第一非封装区，所述第一搭接过孔设置在所述第一非封装区。
  3. 根据权利要求1所述的显示基板，其中，所述上边框区包括沿着远离所述显示区域方向依次设置的隔离区和裂缝坝区，所述隔离区设置有隔离坝，所述裂缝坝区设置有裂缝坝，所述第一搭接过孔设置在所述隔离坝和所述裂缝坝之间。
  4. 根据权利要求1所述的显示基板，其中，所述驱动电路层至少包括在所述基底上依次设置的遮挡导电层、第一导电层、第二导电层和第三导电层，所述第二连接线和所述数据信号线设置在不同的导电层中。
  5. 根据权利要求4所述的显示基板，其中，所述数据信号线设置在所述第三导电层中；所述第二连接线设置在所述遮挡导电层中，或者，所述第二连接线设置在所述第一导电层中，或者，所述第二连接线设置在所述第二导电层中。
  6. 根据权利要求1所述的显示基板，其中，所述第一连接线的第一端与所述绑定区域的引出线连接，所述第一连接线的第二端经过所述显示区域延伸到所述上边框区后，通过所述第一搭接过孔与所述第二连接线的第一端 连接。
  7. 根据权利要求6所述的显示基板，其中，所述第一连接线远离所述显示区域的端部设置有第一连接块，所述第一搭接过孔在所述基底上的正投影与所述第一连接块在所述基底上的正投影至少部分交叠。
  8. 根据权利要求6所述的显示基板，其中，所述第二连接线的第一端通过所述第一搭接过孔与所述第一连接线的第二端连接，所述第二连接线的的第二端延伸到所述显示区域后，通过所述第二搭接过孔与所述数据信号线连接。
  9. 根据权利要求8所述的显示基板，其中，所述第二连接线远离所述显示区域的端部设置有第二连接块，所述第一搭接过孔在所述基底上的正投影与所述第二连接块在所述基底上的正投影至少部分交叠。
  10. 根据权利要求1所述的显示基板，其中，所述第一搭接过孔在所述基底上的正投影与所述第二搭接过孔在所述基底上的正投影没有交叠。
  11. 根据权利要求1至10任一项所述的显示基板，其中，所述绑定区域至少包括沿着远离所述显示区域方向依次设置的引出线区、弯折区和驱动芯片区，所述基底导电层还包括引出线，所述引出线的第一端与所述驱动芯片区的集成电路连接，所述引出线的第二端经过所述弯折区延伸到所述引出线区后，与所述第一连接线的第一端连接。
  12. 根据权利要求11所述的显示基板，其中，所述引出线和所述第一连接线为相互连接的一体结构。
  13. 根据权利要求11所述的显示基板，其中，所述基底导电层还包括第一电源连接线，所述引出线区还包括第二电源连接线和电源走线，所述第一电源连接线的第一端与所述驱动芯片区的绑定引脚连接，所述第一电源连接线的第二端经过所述弯折区延伸到所述引出线区后，通过第三搭接过孔与所述第二电源连接线连接，所述第二电源连接线通过第四搭接过孔与所述电源走线连接。
  14. 根据权利要求13所述的显示基板，其中，所述引出线区包括沿着远离所述显示区域方向依次设置的第二封装区和第二非封装区，所述第三搭 接过孔设置在所述第二非封装区。
  15. 根据权利要求1至10任一项所述的显示基板，其中，所述侧边框区在所述基底上的正投影与所述基底导电层在所述基底上的正投影没有交叠。
  16. 一种显示装置，包括如权利要求1至15任一项所述的显示基板。
  17. 一种显示基板的制备方法，所述显示基板包括显示区域、位于所述显示区域第二方向一侧的绑定区域以及位于所述显示区域其它侧的边框区域，所述边框区域至少包括位于所述显示区域远离所述绑定区域一侧的上边框区和位于所述显示区域第一方向至少一侧的侧边框区，所述第一方向与所述第二方向交叉；所述制备方法包括：
    形成基底，所述基底至少包括第一柔性层、第二柔性层以及设置在所述第一柔性层和第二柔性层之间的基底导电层，所述基底导电层至少包括第一连接线；
    在所述基底上形成驱动电路层，所述驱动电路层至少包括数据信号线和第二连接线，所述第二连接线通过第一搭接过孔与所述第一连接线连接，所述数据信号线通过第二搭接过孔与所述第二连接线连接，所述第一搭接过孔设置在所述上边框区。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783889A (zh) * 2017-01-13 2017-05-31 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN112582452A (zh) * 2020-12-04 2021-03-30 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN114156289A (zh) * 2021-12-29 2022-03-08 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114203739A (zh) * 2021-12-30 2022-03-18 京东方科技集团股份有限公司 显示基板及显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783889A (zh) * 2017-01-13 2017-05-31 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN112582452A (zh) * 2020-12-04 2021-03-30 上海天马有机发光显示技术有限公司 显示面板和显示装置
CN114156289A (zh) * 2021-12-29 2022-03-08 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN114203739A (zh) * 2021-12-30 2022-03-18 京东方科技集团股份有限公司 显示基板及显示装置

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