WO2023206339A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023206339A1
WO2023206339A1 PCT/CN2022/090203 CN2022090203W WO2023206339A1 WO 2023206339 A1 WO2023206339 A1 WO 2023206339A1 CN 2022090203 W CN2022090203 W CN 2022090203W WO 2023206339 A1 WO2023206339 A1 WO 2023206339A1
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WIPO (PCT)
Prior art keywords
line
connection
conductive layer
connection line
area
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Application number
PCT/CN2022/090203
Other languages
English (en)
French (fr)
Inventor
陈文波
王梦奇
于子阳
蒋志亮
胡明
邱海军
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/090203 priority Critical patent/WO2023206339A1/zh
Priority to CN202280001022.2A priority patent/CN115004376B/zh
Priority to GB2406978.3A priority patent/GB2627603A/en
Publication of WO2023206339A1 publication Critical patent/WO2023206339A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically refers to a display substrate and a display device.
  • OLED Organic light emitting diodes
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • this embodiment provides a display substrate, including: a display area and a binding area located on one side of the display area.
  • the display area includes: a base substrate and a driving circuit layer provided on the base substrate.
  • the driving circuit layer includes: a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines and a plurality of data connection lines. At least one data signal line among the plurality of data signal lines is electrically connected to one unit column.
  • At least one data connection line among the plurality of data connection lines includes: a first connection line extending along a first direction and a second connection line extending along a second direction, and the second connection line extends toward the binding area. Extend, the first direction and the second direction intersect.
  • the first connection line is electrically connected to the second connection line and the data signal line respectively; the first connection line and the second connection line are located on different conductive layers.
  • a first end of at least one first connection line is electrically connected to the data signal line, and a second end is electrically connected to the second connection line.
  • At least one first connection line runs through the display area along the first direction.
  • At least one second connection line runs through the display area along the second direction.
  • the first connection line in a direction perpendicular to the display substrate, is located on a side of the second connection line away from the base substrate.
  • the display area further includes: a plurality of first compensation traces extending along the first direction and a plurality of second compensation traces extending along the second direction; the plurality of first compensation traces extending along the second direction; At least one of the second compensation traces is electrically connected to at least one of the first compensation traces.
  • the display substrate further includes: a frame area located on other sides of the display area, the frame area is provided with frame power leads, and the frame power leads are connected to a plurality of first compensation lines of the display area.
  • the trace is electrically connected to a plurality of second compensation traces.
  • the first compensation trace and the first connection line are arranged on the same layer, and at least one circuit unit includes a first break, and the first break is disposed between the first compensation trace and the first connection line. between the first connecting lines.
  • the orthographic projection of the first fracture on the base substrate is covered by the orthographic projection of the conductive film layer other than the film layer where the first connection line is located on the base substrate.
  • the second compensation trace and the second connection line are arranged on the same layer, and at least one circuit unit includes a second break, and the second break is disposed between the second compensation trace and the second connection line. between the second connecting lines.
  • the orthographic projection of the second fracture on the base substrate is covered by the orthographic projection of the conductive film layer other than the film layer where the second connection line is located on the base substrate.
  • At least one circuit unit includes: a dummy electrode; the dummy electrode is electrically connected to the data signal line or the second connection line through a via hole, and the dummy electrode is between a front projection of the substrate substrate and The data signal lines or the second connection lines at least partially overlap in the orthographic projection of the base substrate.
  • At least one circuit unit includes: a dummy electrode and a first data connection electrode; the first data connection electrode is electrically connected to the first connection line, and the dummy electrode is connected to the first data connection line through a via hole.
  • the first data connection electrode is electrically connected, and the orthographic projection of the dummy electrode on the base substrate at least partially overlaps the orthographic projection of the first data connection electrode on the base substrate.
  • the circuit unit at least includes a pixel driving circuit including a storage capacitor and a plurality of transistors.
  • the driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer provided on the base substrate; the semiconductor layer at least includes the The active layer of the plurality of transistors, the first conductive layer at least includes the gates of the plurality of transistors and the first plate of the storage capacitor, the second conductive layer at least includes the third plate of the storage capacitor.
  • the third conductive layer at least includes a plurality of connecting electrodes.
  • the second conductive layer further includes the first connection line
  • the third conductive layer further includes the second connection line and the data signal line.
  • the driving circuit layer further includes: a fourth conductive layer located on a side of the third conductive layer away from the base substrate; the fourth conductive layer includes: the data signal line and the second connection line; the third conductive layer further includes: the first connection line.
  • the driving circuit layer further includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate; A fifth conductive layer on one side of the substrate; the fourth conductive layer includes: the data signal line and the second connection line; the fifth conductive layer includes: the first connection line.
  • the binding area at least includes a lead area
  • the lead area includes a plurality of lead lines
  • the data signal lines include a first data signal line group and a second data signal line group
  • the data signal lines in the first data signal line group are electrically connected to the lead-out lines through the data connection lines
  • the data signal lines in the second data signal line group are directly electrically connected to the lead-out lines.
  • the binding area at least includes a lead area
  • the lead area includes a plurality of lead lines
  • the plurality of data signal lines are connected to the plurality of lead lines through the plurality of data connection lines. Electrical connection.
  • At least two second connection lines are provided between two adjacent data signal lines.
  • At least one unit column includes a plurality of inactive pixel driving circuits, and at least one second connection line is in an orthographic projection of the substrate and the inactive pixel driving circuit of the unit column is located on the substrate. There is overlap in the orthographic projection of the substrate.
  • this embodiment provides a display device including the display substrate as described above.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic plan view of a display area in a display substrate
  • Figure 4 is a schematic cross-sectional structural diagram of a display area of a display substrate
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit
  • Figure 6 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 7A is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 7B is a partially enlarged schematic diagram of area C1 in Figure 7A;
  • Figure 8 is a schematic plan view of the compensation wiring according to at least one embodiment of the present disclosure.
  • Figure 9A is a partially enlarged schematic view of the display substrate after the semiconductor layer is formed in the region C1 in Figure 7A;
  • Figure 9B is a partially enlarged schematic view of the display substrate after the first conductive layer is formed in the region C1 in Figure 7A;
  • Figure 9C is a partially enlarged schematic view of the display substrate after the second conductive layer is formed in the region C1 in Figure 7A;
  • Figure 9D is a partially enlarged schematic view of the display substrate after the third insulating layer is formed in the region C1 in Figure 7A;
  • Figure 9E is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in the region C1 in Figure 7A;
  • Figure 9F is a partially enlarged schematic view of the display substrate after the fourth insulating layer is formed in the region C1 in Figure 7A;
  • Figure 9G is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in the area C1 in Figure 7A;
  • Figure 9H is a partially enlarged schematic diagram of the third conductive layer and the fourth conductive layer in area C1 in Figure 7A;
  • Figure 9I is a schematic cross-sectional view along Q-Q’ in Figure 9G;
  • Figure 10A is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in area C2 in Figure 7A;
  • Figure 10B is a partially enlarged schematic view of the display substrate after the fourth insulating layer is formed in area C2 in Figure 7A;
  • Figure 10C is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C2 in Figure 7A;
  • Figure 11A is another partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in the region C1 in Figure 7A;
  • FIG. 11B is another partially enlarged schematic diagram of the display substrate after the fifth insulating layer is formed in the region C1 in FIG. 7A;
  • Figure 11C is another partially enlarged schematic diagram of the display substrate after the fifth conductive layer is formed in the region C1 in Figure 7A;
  • Figure 11D is a partially enlarged schematic diagram of the fourth conductive layer and the fifth conductive layer in area C1 in Figure 7A;
  • Figure 11E is a schematic cross-sectional view along the U-U’ direction in Figure 11C;
  • Figure 12A is another partially enlarged schematic view of the display substrate after the second conductive layer is formed in the region C1 in Figure 7A;
  • Figure 12B is another partially enlarged schematic diagram of the display substrate after the third insulating layer is formed in the region C1 in Figure 7A;
  • Figure 12C is another partially enlarged schematic diagram of the display substrate after the third conductive layer is formed in the region C1 in Figure 7A;
  • Figure 12D is a partially enlarged schematic diagram of the second conductive layer and the third conductive layer in area C1 in Figure 7A;
  • Figure 12E is a schematic cross-sectional view along the R-R’ direction in Figure 12C;
  • Figure 13 is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 14 is a partial enlarged schematic diagram of the driving circuit layer in area C3 in Figure 13;
  • Figure 15 is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 16 is a schematic diagram of the arrangement of circuit units according to at least one embodiment of the present disclosure.
  • Figure 17 is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 18A is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in area C4 in Figure 17;
  • Figure 18B is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C4 in Figure 17;
  • Figure 18C is a schematic diagram of the third conductive layer and the fourth conductive layer in Figure 18B;
  • Figure 19 is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 20 is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 21 is another planar structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 22 is a planar structural view of a compensation trace according to at least one embodiment of the present disclosure.
  • Figure 23A is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in area C5 in Figure 21;
  • Figure 23B is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C5 in Figure 21;
  • Figure 23C is a partially enlarged schematic view of the display substrate after the fifth insulating layer is formed in area C5 in Figure 21;
  • Figure 23D is a partially enlarged schematic view of the display substrate after the fifth conductive layer is formed in area C5 in Figure 21;
  • Figure 23E is a partially enlarged schematic diagram of the third conductive layer, the fourth conductive layer and the fifth conductive layer in area C5 in Figure 21;
  • Figure 24 is a schematic diagram of the appearance of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 25A is another partially enlarged schematic diagram of the display substrate after the third conductive layer is formed in area C5 in FIG. 21;
  • Figure 25B is another partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C5 in Figure 21;
  • Figure 25C is a partially enlarged schematic diagram of the third conductive layer and the fourth conductive layer in area C5 in Figure 21;
  • FIG. 26A is another partially enlarged schematic diagram of the display substrate after the second conductive layer is formed in area C5 in FIG. 21;
  • FIG. 26B is another partially enlarged schematic diagram of the display substrate after the third conductive layer is formed in area C5 in FIG. 21;
  • FIG. 26C is a partially enlarged schematic diagram of the second conductive layer and the third conductive layer in area C5 in FIG. 21 .
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components.
  • elements with some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate can also be called the control electrode.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include: a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, scan driver and light-emitting driver respectively.
  • the data driver is respectively connected to a plurality of data signal lines (for example, D1 to Dn)
  • the scan driver is respectively connected to a plurality of scan signal lines (for example, S1 to Sm)
  • the light emitting driver is respectively connected to a plurality of light emitting control lines (for example, E1 to Eo) connection.
  • n, m and o can be natural numbers.
  • the pixel array may include multiple sub-pixels Pxij, and i and j may be natural numbers. At least one sub-pixel Pxij may include: a circuit unit and a light-emitting element connected to the circuit unit.
  • the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit may be connected to the scanning signal line, the light emission control line, and the data signal line respectively.
  • the timing controller may provide grayscale values and control signals suitable for specifications of the data driver to the data driver, and may provide clock signals, scan start signals, etc. suitable for specifications of the scan driver.
  • the scan driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data driver may sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal .
  • the light-emitting driver may generate light-emitting control signals to be provided to the light-emitting control lines E1, E2, E3, . . .
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting control lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the light-emitting control signal in a manner that sequentially transmits an emission stop signal provided in the form of an off-level pulse to a next-stage circuit under the control of a clock signal.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij that constitute a pixel array.
  • the plurality of sub-pixels Pxij may be configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area 100 .
  • the fan-out area is connected to the display area 100 and includes at least data fan-out lines.
  • the plurality of data fan-out lines are configured to connect data signal lines of the display area 100 in a fan-out wiring manner.
  • the bending area is connected to the fan-out area, may include a composite insulating layer provided with grooves, and is configured to bend the driver chip area and the bonding pin area to the back of the display area 100 .
  • the driver chip area can be provided with an integrated circuit (IC, Integrated Circuit), and the integrated circuit can be configured to be connected to multiple data fan-out lines.
  • the bonding pin area can include a bonding pad, and the bonding pad can be configured to be bonded to an external flexible circuit board (FPC, Flexible Printed Circuit).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning line, the second scanning line and the light emission control line to which the pixel driving circuit in the display area 100 is connected.
  • the power line area is connected to the circuit area and may include at least a frame power lead.
  • the frame power lead extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along the extending in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100 .
  • the edge of the display area is the edge of the display area 100 close to the binding area 200 or the frame area 300 .
  • Figure 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and third and fourth sub-pixels P3 and P4 emitting light of a third color.
  • Each sub-pixel may include a circuit unit and a light-emitting element.
  • the circuit unit may include at least a pixel driving circuit.
  • the pixel driving circuit is connected to the scanning signal line, the data signal line and the light-emitting control line respectively.
  • the pixel driving circuit may be configured to operate on the scanning signal line.
  • the light-emitting control line Under the control of the light-emitting control line, it receives the data voltage transmitted by the data signal line and outputs the corresponding current to the light-emitting element.
  • the light-emitting element in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting element is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • the shape of the light-emitting elements of the sub-pixels can be rectangular, rhombus, pentagon or hexagon, and the light-emitting elements of the four sub-pixels can be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the light-emitting elements of the four sub-pixels may be arranged horizontally, vertically, or in a square manner, which is not limited in this disclosure.
  • the pixel unit may include three sub-pixels, and the light-emitting elements of the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of a display area of a display substrate.
  • FIG. 4 illustrates the structure of three sub-pixels in the display area 100.
  • the display substrate may include: a base substrate 101, a driving circuit layer 102, a light-emitting structure layer 103 and a packaging structure layer 104 sequentially provided on the base substrate 101.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • the substrate substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the light-emitting structure layer 103 of each sub-pixel may at least include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304.
  • the anode 301 is connected to the pixel driving circuit
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light emitting layer 303 may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). , hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together through a common layer. Layers, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel circuit of this exemplary embodiment is explained by taking the 7T1C structure as an example. However, this embodiment is not limited to this.
  • the pixel driving circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7 ) and one storage capacitor Cst.
  • the pixel driving circuit is respectively connected to nine signal lines (for example, including: data signal line DL, first scanning signal line GL, second scanning signal line RST1, third scanning signal line RST2, light emission control line EML, first initial signal line INIT1 , the second initial signal line INIT2, the first power line VDD and the second power line VSS) are connected.
  • the seven transistors of the pixel driving circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield. In some possible implementations, the seven transistors of the pixel driving circuit may include P-type transistors and N-type transistors.
  • the seven transistors of the pixel driving circuit may use low-temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate, that is, LTPS+Oxide (LTPO for short)
  • the display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the first power line VDD may be configured to provide a constant first voltage signal to the pixel driving circuit
  • the second power line VSS may be configured to provide a constant second voltage signal to the pixel driving circuit
  • the One voltage signal is greater than the second voltage signal.
  • the first scanning signal line GL may be configured to provide the first scanning signal SCAN to the pixel driving circuit
  • the data signal line DL may be configured to provide the data signal DATA to the pixel driving circuit
  • the emission control line EML may be configured to provide emission control to the pixel driving circuit Signal EM.
  • the second scanning signal line RST1 may be electrically connected to the first scanning signal line GL of the n-1th row of pixel driving circuits to be input with the first scanning signal SCAN(n -1).
  • the third scanning signal line RST2 of the n-th row pixel driving circuit may be electrically connected to the first scanning signal line GL of the n-th row pixel driving circuit so as to be input with the first scanning signal SCAN(n).
  • the third scanning signal line RST2 electrically connected to the pixel driving circuit of the nth row and the second scanning signal line RST1 electrically connected to the pixel driving circuit of the n+1th row may be an integrated structure.
  • n is an integer greater than 0. In this way, the signal lines of the display substrate can be reduced and the narrow frame design of the display substrate can be achieved. However, this embodiment is not limited to this.
  • the first initial signal line INIT1 may be configured to provide a first initial signal to the pixel driving circuit
  • the second initial signal line INIT2 may be configured to provide a second initial signal to the pixel driving circuit.
  • the first initial signal may be different from the second initial signal.
  • the first initial signal and the second initial signal may be constant voltage signals, and their magnitudes may be between, for example, the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, but are not limited to this.
  • the first initial signal and the second initial signal may be the same, and only the first initial signal line may be provided to provide the first initial signal.
  • the gate electrode of the first transistor T1 is electrically connected to the second scanning signal line RST1
  • the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1
  • the first transistor T1 is electrically connected to the first initial signal line INIT1.
  • the second electrode of a transistor T1 is electrically connected to the gate electrode of the third transistor T3.
  • the gate electrode of the second transistor T2 is electrically connected to the first scanning signal line GL.
  • the first electrode of the second transistor T2 is electrically connected to the gate electrode of the third transistor T3.
  • the second electrode of the second transistor T2 is electrically connected to the gate electrode of the third transistor T3.
  • the second pole is electrically connected.
  • the gate electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its gate electrode and the first electrode.
  • the gate electrode of the fourth transistor T4 is electrically connected to the first scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. connect.
  • the gate electrode of the fifth transistor T5 is electrically connected to the light-emitting control line EML
  • the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD
  • the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3.
  • the gate electrode of the sixth transistor T6 is electrically connected to the light-emitting control line EML
  • the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. connect.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the gate electrode of the seventh transistor T7 is electrically connected to the third scanning signal line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. connect.
  • the first plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second plate of the storage capacitor Cst is electrically connected to the first power line VDD.
  • the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, and the second node N2 is the fifth transistor T5, the fourth transistor T4 and the third transistor.
  • the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.
  • the light-emitting element EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (cathode) anode), quantum dot light-emitting layer and the second electrode (cathode).
  • the second pole of the light-emitting element is connected to the second power line VSS.
  • the signal of the second power line VSS is a continuously provided low-level signal
  • the signal of the first power line VDD is a continuously provided high-level signal.
  • the working process of the pixel driving circuit may include the following stages.
  • the first phase A1 is called the reset phase.
  • the low-level signal provided by the second scanning signal line RST1 turns on the first transistor T1
  • the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize and clear the first node N1.
  • the first scanning signal line GL provides a high-level signal
  • the light-emitting control line EML provides a high-level signal to turn off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. At this stage, the light-emitting element EL does not emit light.
  • the second stage A2 is called the data writing stage or threshold compensation stage.
  • the first scanning signal line GL provides a low-level signal
  • the second scanning signal line RST1 and the light-emitting control line EML both provide high-level signals
  • the data signal line DL outputs the data signal DATA.
  • the third transistor T3 is turned on.
  • the first scanning signal line GL provides a low level signal to turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage Vdata output by the data signal line DL is provided to
  • the first node N1 charges the difference between the data voltage Vdata output by the data signal line DL and the threshold voltage of the third transistor T3 into the storage capacitor Cst.
  • the voltage of the first plate of the storage capacitor Cst (ie, the first node N1) is Vdata-
  • the seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, which initializes (resets) the anode of the light-emitting element EL, clears its internal pre-stored voltage, and completes the initialization. Make sure that the light-emitting element EL does not emit light.
  • the second scanning signal line RST1 provides a high level signal to turn off the first transistor T1.
  • the light-emitting control line EML provides a high-level signal to turn off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the luminous stage.
  • the light-emitting control line EML provides a low-level signal, and both the first scanning signal line GL and the second scanning signal line RST1 provide high-level signals.
  • the light-emitting control line EML provides a low-level signal to turn on the fifth transistor T5 and the sixth transistor T6.
  • the first voltage signal output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 supplies a driving voltage to the anode of the light-emitting element EL to drive the light-emitting element EL to emit light.
  • the driving current flowing through the third transistor T3 (ie, the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K ⁇ [Vdd-Vdata] 2 .
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the light-emitting element EL
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • the threshold voltage of the three transistors T3, Vdata is the data voltage output by the data signal line DL
  • Vdd is the first voltage signal output by the first power supply line VDD.
  • the current flowing through the light-emitting element EL has nothing to do with the threshold voltage of the third transistor T3.
  • the pixel driving circuit of this embodiment can better compensate the threshold voltage of the third transistor T3.
  • the bonding area usually includes a fan-out area, a bending area, a driver chip area and a bonding pin area that are sequentially arranged in a direction away from the display area. Since the width of the bonding area is smaller than the width of the display area, the signal lines of the integrated circuits and bonding pads in the bonding area need to be introduced into the wider display area through the fan-out area in the fanout routing method.
  • the sector area takes up a larger space, resulting in a narrower design of the lower border. It is quite difficult, as the lower border has been maintained at around 2.0 millimeters (mm).
  • Embodiments of the present disclosure provide a display substrate, including: a display area and a binding area located on one side of the display area.
  • the display area includes: a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along the second direction, and a plurality of data connection lines. At least one data signal line among the plurality of data signal lines is electrically connected to one unit column.
  • At least one data connection line includes: a first connection line extending along a first direction and a second connection line extending along a second direction. The first direction intersects the second direction. The first connection line is electrically connected to the second connection line and the data signal line respectively.
  • the first connection line and the second connection line are located on different conductive layers.
  • the orthographic projection of the first connection line on the base substrate may overlap with the orthographic projection of a cell row on the base substrate
  • the orthographic projection of the second connection line on the base substrate may overlap with the orthographic projection of a cell column on the base substrate. There is overlap in the orthographic projection of the base substrate.
  • A extends along the direction B. It means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along the direction B, and the main part The length of the portion extending along direction B is greater than the length of the minor portion extending along the other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • the lead wires in the binding area can be electrically connected to the data signal lines through the data connection lines, so that there is no need to set fan-shaped diagonal lines in the binding area. , effectively reducing the length of the lead area in the binding area, greatly reducing the width of the lower border, increasing the screen-to-body ratio, and helping to achieve full-screen display. Furthermore, in the display substrate of this embodiment, by arranging the first connection line and the second connection line extending in two different directions of the data connection lines in different conductive layers, it is possible to prevent the data connection lines from being densely packed in the same conductive layer. The setting allows different areas of the display area to achieve basically the same display effect under transmitted light and reflected light, effectively eliminating shadowing, effectively avoiding poor appearance of the display substrate, and improving display quality and display quality.
  • a first end of at least one first connection line may be electrically connected to the data signal line, and a second end may be electrically connected to the second connection line.
  • the length of the first connection line along the first direction may be determined according to the spacing between the electrically connected data signal line and the second connection line in the first direction.
  • the length of the second connection line along the second direction may be determined according to the distance between the boundaries of the display area and the binding area and the first connection line to which the second connection line is electrically connected.
  • At least one first connection line may penetrate the display area along the first direction.
  • the two ends of the first connection line respectively extend to the boundaries of the display area and the frame areas on both sides, and the middle part of the first connection line is electrically connected to the data signal line and the second connection line.
  • the lengths of the plurality of first connection lines along the first direction may be substantially the same. In this example, by setting first connecting lines with approximately the same length, the uniformity of wiring in different areas of the display area can be ensured.
  • At least one second connection line may penetrate the display area along the second direction.
  • the two ends of the second connection line may respectively extend to the boundary between the display area and the upper side frame area and the boundary between the display area and the binding area.
  • the lengths of the plurality of second connection lines along the second direction may be substantially the same. In this example, by setting second connecting lines with approximately the same length, the uniformity of wiring in different areas of the display area can be ensured.
  • FIG. 6 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include a driving circuit layer disposed on the substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base.
  • the display substrate in a plane parallel to the display substrate, may at least include: a display area 100 , a binding area 200 located on one side of the display area 100 along the second direction Y, and a binding area 200 located on other sides of the display area 100 . Border area 300.
  • the driving circuit layer of the display area 100 may include: a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 60 , and a plurality of data connection lines 70 .
  • At least one circuit unit may include: a pixel driving circuit, and the pixel driving circuit may be configured to output a corresponding current to the connected light-emitting element.
  • the light-emitting structure layer of the display area 100 may include a plurality of light-emitting elements. The light-emitting elements are connected to the pixel driving circuit of the corresponding circuit unit. The light-emitting elements are configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the circuit units may be areas divided according to pixel driving circuits.
  • the position of the orthographic projection of the light-emitting element on the base substrate may correspond to the orthographic projection of the circuit unit on the base substrate, or the position of the orthographic projection of the light-emitting element on the base substrate corresponds to the orthographic position of the circuit unit on the base substrate. Locations may not correspond.
  • At least one data signal line 60 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 60 may be configured to provide data signals to the connected pixel driving circuits.
  • At least one data connection line 70 is correspondingly connected to the data signal line 60 , and the data connection line 70 may be configured such that the data signal line 60 is correspondingly connected to the lead line 80 in the binding area 200 through the data connection line 70 .
  • a plurality of circuit units arranged sequentially along the first direction X may be called a unit row
  • a plurality of circuit units arranged sequentially along the second direction Y may be called a unit column
  • multiple unit rows and multiple The unit columns constitute an array of circuit units arranged in an array
  • the first direction X and the second direction Y intersect.
  • the second direction Y may be an extending direction of the data signal line 60 (eg, a vertical direction)
  • the first direction X may be perpendicular to the second direction Y (eg, a horizontal direction).
  • the bonding area 200 may include: a lead area 201 , a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area.
  • the lead area 201 is connected to the display area 100, and the bending area is connected to the lead area 201.
  • the lead area 201 may be provided with a plurality of lead lines 80 .
  • the plurality of lead lines 80 may extend along the second direction Y away from the display area 100 .
  • the first ends of some of the lead lines 80 are correspondingly connected to the data connection lines 70 in the display area 100 .
  • the first end of another part of the lead wires is connected to the data signal line 60 in the display area 100
  • the second ends of all the lead wires 80 are connected to the integrated circuits in the composite circuit area across the bending area, so that the integrated circuits pass through the lead wires 80
  • the data connection line 70 applies the data signal to the data signal line 60 . Since the data connection line 70 is disposed in the display area 100, the length of the lead area 201 in the second direction Y can be effectively reduced, the width of the lower frame can be greatly reduced, and the screen-to-body ratio can be improved, which is beneficial to realizing a full-screen display.
  • the plurality of data signal lines 60 of the display area 100 may extend along the second direction Y and be sequentially arranged at set intervals along the first direction X in an increasing numbered manner.
  • the plurality of data signal lines 60 can be divided into a first data signal line group and a second data signal line group according to whether they are connected to data connection lines.
  • the plurality of data signal lines 60 in the first data signal line group correspond to the data connection lines 70 connection, the plurality of data signal lines 60 in the second data signal line group are not connected to the data connection lines 70 .
  • the plurality of lead lines 80 in the lead area 201 can be divided into a first lead line group and a second lead line group according to whether they are connected to the data connection line 70 or the data signal line 60.
  • the plurality of lead lines in the first lead line group 80 is correspondingly connected to the data connection line 70
  • the plurality of lead lines 80 in the second lead line group are correspondingly connected to the data signal line 60
  • the lead wire 80 and the data signal line 60, and the lead wire 80 and the data connection line 70 may be directly connected, or may be connected through via holes, which is not limited in this disclosure.
  • the data connection line 70 of the display area 100 may include a first connection line 71 and a second connection line 72 .
  • the first connection line 71 and the second connection line 72 are connected to each other.
  • the first connection line 71 may extend along the first direction X
  • the second connection line 72 may extend along the second direction Y.
  • the first end of the first connection line 71 can be connected correspondingly to the data signal line 60 of the first data signal line group, and the second end of the first connection line 71 can extend along the first direction X or the opposite direction of the first direction X. Then, it is connected to the first end of the second connection line 72.
  • the second end of the second connection line 72 can extend in the direction of the binding area 200 and cross the display area boundary B, and connect with the first lead line group in the lead area 201.
  • the lead-out lines 80 are connected correspondingly, so that the data signal lines 60 of the first data signal line group in the display area 100 can be indirectly connected to the lead-out lines 80 through the data connection lines 70 .
  • the plurality of data signal lines 60 of the second data signal line group may extend in the direction of the binding area 200 and cross the display area boundary B, and be connected correspondingly to the plurality of lead lines 80 of the second lead line group in the lead area 201, so that The plurality of data signal lines 60 of the second data signal line group in the display area 100 are directly connected to the lead-out lines 80 .
  • the display area boundary B may be the junction of the display area 100 and the binding area 200 .
  • first connection line 71 and the second connection line 72 may be provided in different conductive layers, and the first connection line 71 and the data signal line 60 may be provided in different conductive layers.
  • first end of the first connection line 71 can be connected to the data signal line 60 through the first connection hole K1
  • second end of the first connection line 71 can extend along the first direction X or the opposite direction of the first direction X.
  • first end of the second connection wire 72 is connected through the second connection hole K2.
  • the second end of the second connection wire 72 can extend along the second direction Y toward the lead area 201 and then be connected to the lead wire 80.
  • At least one data signal line 60 may be disposed between two adjacent second connection lines 72 in the first direction X.
  • a data signal line may be provided between adjacent second connection lines 72 .
  • two data signal lines may be provided between adjacent second connection lines 72 .
  • the plurality of second connection lines 72 may be disposed parallel to the data signal line 60
  • the plurality of first connection lines 71 may be disposed perpendicular to the data signal line 60 .
  • the spacing between adjacent second connection lines 72 may be approximately the same, and the spacing between adjacent first connection lines 71 may be approximately the same, which is not limited in this disclosure.
  • the display area 100 may have a center line O, and the plurality of data signal lines 60 , the plurality of data connection lines 70 in the display area 100 and the plurality of lead lines 80 in the lead area 201 may be symmetrical with respect to the center line O It is provided that the center line O may be a straight line bisecting the plurality of unit columns of the display area 100 and extending along the second direction Y. As shown in FIG.
  • the lines in the first data signal line group far away from the center line O are
  • the second connection line 72 connected to the data signal line 60 may be located on a side close to the center line O of the second connection line 72 connected to the data signal line 60 .
  • the length of the plurality of second connection lines 72 along the second direction Y may gradually increase in the first direction X in a direction close to the center line O.
  • the first connection line 71 connected to the data signal line 60 far away from the center line O in the first data signal line group may be located away from the binding area 200 one side.
  • the lengths of the plurality of first connection lines 71 along the first direction X may gradually decrease in the second direction Y.
  • This exemplary embodiment not only facilitates the layout of the data connection lines without sudden changes in the load, but also further compresses the space occupied by the data connection lines by arranging a data signal line between adjacent second connection lines and minimizes the Data signal loading differences.
  • this embodiment is not limited to this.
  • the second connection line connected to the data signal line far away from the center line O in the first data signal line group may be located on the side away from the center line O to the second connection line connected to the data signal line close to the center line O.
  • the first connection line connected to the data signal line far away from the center line O in the first data signal line group may be located near the binding area 200 of the first connection line connected to the data signal line close to the center line O. side.
  • FIG. 7A is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 7B is a partially enlarged schematic diagram of area C1 in FIG. 7A.
  • the driving circuit layer of the display area 100 may include: a plurality of circuit units constituting a circuit unit array, a plurality of data signal lines 60 , a plurality of data connection lines 70 and a compensation line 90 .
  • the layout and structure of the plurality of circuit units, the plurality of data signal lines 60 and the plurality of data connection lines 70 are substantially the same as those shown in FIG. 6 .
  • the compensation traces 90 may include a plurality of first compensation traces 91 extending along the first direction X and a plurality of second compensation traces extending along the second direction Y. 92.
  • a plurality of first compensation traces 91 may be arranged in sequence along the second direction Y, and a plurality of second compensation traces 92 may be arranged in sequence along the first direction X.
  • the first compensation trace 91 and the second compensation trace 92 may be provided in different conductive layers.
  • the second compensation trace 92 may be disposed between adjacent data signal lines 60 .
  • the orthographic projections of the plurality of first compensation traces 91 and the plurality of second compensation traces 92 on the substrate may intersect, thereby forming a mesh structure.
  • at least one second compensation wire 92 may be electrically connected to at least one first compensation wire 91 through the third connection hole K3, so that a plurality of first compensation wires 91 and a plurality of second compensation wires 92 Can form a network connection structure.
  • the first compensation line 91 and the first connection line 71 may be provided on the same layer and formed simultaneously through the same patterning process.
  • the second compensation line 92 and the second connection line 72 may be provided on the same layer and formed simultaneously through the same patterning process.
  • the appearance compensation effect can be provided for the data connection line 70, so that different areas of the display area can achieve basically the same display effect under transmitted light and reflected light, effectively eliminating ghosting. situation, effectively avoiding the poor appearance of the display substrate and improving the display quality and display quality.
  • only the first compensation wire 91 may be provided in at least one unit row, and the first connection line 71 may not be provided in the unit row.
  • At least one first compensation line 91 and at least one first connection line 71 may be provided in at least one unit row.
  • the first compensation trace 91 and the first connection line 71 in at least one unit row may be aligned in the first direction between the first compensation line 91 and the first connection line 71 .
  • the first break DF1 may be configured to achieve no electrical connection between the first compensation line 91 and the first connection line 71 .
  • only the second compensation trace 92 may be provided in at least one cell column, and the second connection line 72 is not provided in the cell column. At least one second compensation line 92 and at least one second connection line 72 may be provided in at least one unit column.
  • the second compensation trace 92 and the second connection line 72 in at least one unit column may be aligned in the second direction Y, and one circuit unit of the unit column may include a second break DF2, and the second break DF2 may be disposed in between the second compensation trace 92 and the second connection line 72 .
  • the second break DF2 may be configured to achieve no electrical connection between the second compensation trace 92 and the second connection line 72 .
  • the first compensation trace 91 and the second compensation trace 91 may be electrically connected to the second power line to continuously receive low-level signals.
  • FIG. 8 is a schematic plan view of a compensation trace according to at least one embodiment of the present disclosure.
  • the second power line may include a binding power lead 410 located in the binding area 200 and a frame power lead 510 located in the frame area 300 .
  • the binding power lead 410 of the binding area 200 and the frame power lead 510 of the frame area 300 may be an integral structure connected to each other.
  • at least one first compensation trace 91 may be connected to the frame power lead 510 at one or both ends in the first direction X.
  • At least one end of the second compensation trace 92 in the opposite direction of the second direction Y may be connected to the frame power lead 510 .
  • At least one second compensation trace 92 may be connected to the frame power lead 510 at one end in the second direction Y. In other examples, at least one second compensation trace 92 can be connected to the bonding power lead 410 at one end in the second direction Y, and can be connected to the frame power lead 510 at an end in the opposite direction of the second direction Y. However, this embodiment is not limited to this.
  • the first compensation trace 91 and the second compensation trace 92 may be disposed in different conductive layers.
  • at least one second compensation wire 92 can be electrically connected to at least one first compensation wire 91 through the third connection hole K3, so that a plurality of second compensation wires 92 and a plurality of first compensation wires 91 can have the same potential.
  • a compensation trace electrically connected to the second power line in the display area not only the resistance of the second power line can be effectively reduced, but also the voltage drop of the low-voltage power signal can be effectively reduced, thereby achieving low power consumption.
  • it can effectively improve the uniformity of the power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the data connection line 70 is disposed in a partial area of the display area 100 , and the data connection line 70 includes a first connection line 71 extending along the first direction X and a first connection line 71 extending along the second direction Y.
  • the extended second connection line 72 can therefore divide the display area 100 into the first area 110, the second area 120 and the third area 130 according to the presence or absence of the data connection line and the extension direction of the data connection line.
  • the first area 110 may be an area where the first connection lines 71 are provided (a fan-out line lateral routing area), and the second area 120 may be an area where the second connection lines 72 are provided (a fan-out line vertical routing area),
  • the third area 130 may be an area (normal area) in which the first connection line 71 and the second connection line 72 are not provided.
  • the first compensation trace 91 and the second compensation trace 92 may be disposed in the third region 130 .
  • the first area 110 may include a plurality of circuit units, and the orthographic projection of the first connection line 71 on the display substrate plane is consistent with the orthogonal projection of the pixel driving circuits in the plurality of circuit units of the first area 110 on the display substrate plane. Projections can at least partially overlap.
  • the second area 120 may include a plurality of circuit units, and the orthographic projection of the second connection line 72 on the display substrate plane may at least partially intersect with the orthographic projection of the pixel driving circuits in the plurality of circuit units of the second area 120 on the display substrate plane.
  • Stack may include a plurality of circuit units. In the plurality of circuit units in the third area 130, the orthographic projection of the pixel driving circuit on the display substrate plane is consistent with the orthographic projection of the first connection line 71 and the second connection line 72 on the display substrate plane. Orthographic projections can have no overlap.
  • the division of multiple areas shown in FIG. 7A is only an exemplary illustration. Since the first area 110, the second area 120 and the third area 130 are divided according to the presence or absence of data connection lines and the extension direction of the data connection lines, the shapes of the three areas may be regular polygons or irregular. Polygonally, the display area 100 may be divided into one or more first areas 110, one or more second areas 120, and one or more third areas 130, which is not limited by the present disclosure.
  • the display substrate in a direction perpendicular to the display substrate, may include: a base substrate, a driving circuit layer, a light-emitting structure layer and a packaging structure layer sequentially disposed on the base substrate.
  • the driving circuit layer may include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially provided on the base substrate.
  • the third conductive layer includes at least a first connection line
  • the fourth conductive layer includes at least a data signal line and a second connection line.
  • the data signal line can be connected to the first end of the first connection line through the first connection hole
  • the second connection line can be connected to the second end of the first connection line through the second connection hole.
  • the driving circuit layer may further include at least a first insulation layer, a second insulation layer, a third insulation layer, and a fourth insulation layer.
  • the first insulating layer may be disposed between the semiconductor layer and the first conductive layer
  • the second insulating layer may be disposed between the first conductive layer and the second conductive layer
  • the third insulating layer may be disposed between the second conductive layer and the third conductive layer.
  • the fourth insulating layer may be disposed between the third conductive layer and the fourth conductive layer.
  • FIG. 9A is a partially enlarged schematic view of the display substrate after the semiconductor layer is formed in the region C1 in FIG. 7A.
  • FIG. 9B is a partially enlarged schematic view of the display substrate after the first conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 9C is a partially enlarged schematic view of the display substrate after the second conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 9D is a partially enlarged schematic view of the display substrate after the third insulating layer is formed in the region C1 in FIG. 7A.
  • FIG. 9A is a partially enlarged schematic view of the display substrate after the semiconductor layer is formed in the region C1 in FIG. 7A.
  • FIG. 9B is a partially enlarged schematic view of the display substrate after the first conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 9C is a partially enlarged schematic view of the display substrate after the second conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 9E is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 9F is a partially enlarged schematic view of the display substrate after the fourth insulating layer is formed in the region C1 in FIG. 7A.
  • FIG. 9G is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 9H is a partially enlarged schematic diagram of the third conductive layer and the fourth conductive layer in the region C1 in FIG. 7A.
  • Figure 9I is a schematic cross-sectional view along Q-Q' in Figure 9G. In FIGS.
  • FIG. 10A is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in area C2 in FIG. 7A.
  • FIG. 10B is a partially enlarged schematic view of the display substrate after the fourth insulating layer is formed in area C2 in FIG. 7A .
  • FIG. 10C is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C2 in FIG. 7A .
  • the circuit units of two unit rows and two unit columns (for example, the 1st to 4th columns) in the area C2 are taken as an example.
  • the "patterning process” mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate.
  • the "thin film” can also be called a "layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • the semiconductor layer of each circuit unit in the display area 100 may include at least: a first active layer 11 of the first transistor T1 to a seventh active layer 17 of the seventh transistor T7 .
  • the first to seventh active layers 11 to 17 may be an integral structure connected to each other.
  • the first active layer 11 , the second active layer 12 , and the fourth active layer 14 may be located on one side of the third active layer 13 of the circuit unit in the second direction Y.
  • the active layer 16 and the seventh active layer 17 may be located on the other side of the third active layer 13 of the present circuit unit in the second direction Y.
  • the first active layer 11 may be in an "n" shape
  • the second active layer 12 and the fifth active layer 15 may be in an "L” shape
  • the third active layer 11 may be in an "L” shape
  • the active layer 13 may be in an " ⁇ " shape
  • the fourth active layer 14 , the sixth active layer 16 and the seventh active layer 17 may be in an "I" shape.
  • this embodiment is not limited to this.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11 - 1 of the first active layer 11 the first region 14 - 1 of the fourth active layer 14 , the first region 15 - 1 of the fifth active layer 15 and the seventh active layer 11 - 11 - 1 .
  • the first region 17-1 of the source layer 17 may be provided independently, the second region 11-2 of the first active layer 11 may be used as the first region 12-1 of the second active layer 12, and the third region 12-1 of the third active layer 13 may be The first region 13-1 can simultaneously serve as the second region 14-2 of the fourth active layer 14, the second region 15-2 of the fifth active layer 15, and the second region 13-2 of the third active layer 13.
  • the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16 can be simultaneously used.
  • the second region 16-2 of the sixth active layer 16 can be used as a seventh active layer.
  • the lead area of the bonding area may not be provided with a semiconductor layer.
  • a first insulating film and a first conductive film are sequentially deposited on the base substrate on which the foregoing pattern is formed, and the first conductive film is patterned through a patterning process to form a first layer covering the semiconductor layer.
  • the insulating layer 111 and the first conductive layer disposed on the first insulating layer 111 are shown in FIG. 9B.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer of each circuit unit in the display area includes at least: a first scanning signal line 21 , a second scanning signal line 22 , a light emitting control line 24 and a first storage capacitor. Plate 25.
  • the third scanning signal line 23 to which the pixel driving circuit of one unit row is electrically connected is the second scanning signal line 22 to which the pixel driving circuit of the next unit row is electrically connected.
  • the shape of the first plate 25 of the storage capacitor may be a rectangle, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate 25 on the base substrate is consistent with the third transistor T3 There is an overlapping area in the orthographic projections of the three active layers 13 on the base substrate.
  • the first plate 25 can simultaneously serve as a plate of the storage capacitor and the gate of the third transistor T3.
  • the first scanning signal line 21 may be provided with a gate block 21-1 protruding toward the second scanning signal line 22 side, and the first scanning signal line 21 and the gate block 21-1 are connected to the second scanning signal line 22.
  • the overlapping area of the source layers 12 can serve as the gate electrode of the second transistor T2, forming the second transistor T2 with a double-gate structure.
  • the area where the first scanning signal line 21 overlaps the fourth active layer 14 may serve as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps the first active layer 11 may serve as the gate electrode of the first transistor T1 in the double-gate structure.
  • the area where the third scanning signal line 23 overlaps the seventh active layer 17 may serve as the gate electrode of the seventh transistor T7.
  • the area where the light-emitting control line 24 overlaps the fifth active layer 15 may serve as the gate electrode of the fifth transistor T5
  • the area where the light-emitting control line 24 overlaps the sixth active layer 16 may serve as the gate electrode of the sixth transistor T6.
  • the first scanning signal line 21 and the third scanning signal line 23 may be connected to the same signal source, that is, the output signals of the first scanning signal line 21 and the third scanning signal line 23 are the same.
  • the first conductive layer can be used as a shield to conduct conduction processing on the semiconductor layer.
  • the semiconductor layer in the area blocked by the first conductive layer forms the first transistor T1 to the seventh transistor T7.
  • the channel region and the semiconductor layer in the region not blocked by the first conductive layer are conductive, that is, the first and second regions of the first active layer 11 to the seventh active layer 17 are all conductive.
  • a second insulating film and a second conductive film are sequentially deposited on the base substrate on which the foregoing pattern is formed, and a patterning process is used to pattern the second conductive film to form a layer covering the first conductive layer.
  • the second insulating layer 112, and the second conductive layer disposed on the second insulating layer, are shown in FIG. 9C.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer of each circuit unit in the display area at least includes: a first initial signal line 31, a second initial signal line 32, a second plate 33 of the storage capacitor Cst, Plate connection wire 34 and shield electrode 35.
  • the shape of the first initial signal line 31 and the second initial signal line 32 may be a line shape in which the main body part may extend along the first direction X.
  • the first initial signal line 31 may be located between the first scanning signal line 21 and the second scanning signal line 22 of this circuit unit, and the second initial signal line 32 may be located between the third scanning signal line 23 of this circuit unit and close to the light-emitting control line. 24 on one side.
  • the outline shape of the second electrode plate 33 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 33 on the substrate is consistent with the position of the first electrode plate 25 on the substrate. There is an overlapping area in the orthographic projection on the substrate.
  • the second plate 33 serves as the other plate of the storage capacitor and is located between the first scanning signal line 21 and the light-emitting control line 24 of the circuit unit.
  • the first plate 25 and the second plate 33 The plate 33 constitutes the storage capacitor of the pixel driving circuit.
  • the plate connecting line 34 may be disposed on one side of the second plate 33 in the first direction X or in the opposite direction to the first direction
  • the pole plates 33 are connected, and the second end of the pole plate connection line 34 extends along the first direction X or the opposite direction of the first direction
  • the second plates 33 of adjacent circuit units are connected to each other.
  • the second plates of multiple circuit units in a unit row can form an integrated structure connected to each other through plate connection lines.
  • the second plates of the integrated structure can be reused as power signal connection lines to ensure a
  • the plurality of second electrode plates in the unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second pole plate 33 is provided with an opening 36 , the opening 36 may be located in the middle of the second pole plate 33 , and the opening 36 may be rectangular, so that the second pole plate 33 forms an annular structure.
  • the opening 36 exposes the second insulating layer 112 covering the first electrode plate 25 , and the orthographic projection of the first electrode plate 25 on the base substrate includes the orthographic projection of the opening 36 on the base substrate.
  • the opening 36 is configured to accommodate a subsequently formed seventh via hole.
  • the seventh via hole may be located within the opening 36 and expose the first plate 25 so that the subsequently formed second electrode of the first transistor T1 Connected to the first plate 25.
  • the shield electrode 35 may be located on a side of the first initial signal line 31 close to the first scanning signal line 21 and connected to the first initial signal line 31 .
  • the shield electrode 35 and the first initial signal line 31 may have an integrated structure.
  • the orthographic projection of the shield electrode 35 on the base substrate at least partially overlaps the orthographic projection of the first region 12 - 1 of the second active layer 12 on the base substrate.
  • the shielding electrode 35 can be configured to shield the impact of data voltage jumps on key nodes, prevent data voltage jumps from affecting the potential of key nodes of the pixel drive circuit, and improve the display effect.
  • a third insulating film is deposited on the base substrate on which the foregoing pattern is formed, and a patterning process is used to pattern the third insulating film to form a third insulating layer 113 covering the second conductive layer, As shown in Figure 9D.
  • multiple vias may be provided in a single circuit unit.
  • the plurality of via holes of each circuit unit in the display area may include at least: first to tenth via holes V1 to V10. Among them, the third insulating layer 113, the second insulating layer 112 and the first insulating layer 111 in the first to sixth via holes V1 to V6 are removed, exposing the surface of the semiconductor layer.
  • the third insulating layer 113 and the second insulating layer 112 in the seventh via hole V7 are removed, exposing the surface of the first plate 25 of the storage capacitor located on the first conductive layer.
  • the third insulating layer 113 in the eighth to tenth via holes V8 to V10 is removed, exposing the surface of the second conductive layer.
  • a third conductive film is deposited on the base substrate on which the foregoing pattern is formed, and a patterning process is used to pattern the third conductive film to form a third conductive film disposed on the third insulating layer 113 .
  • layer as shown in Figure 9E and Figure 10A.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layers of multiple circuit units in the display area may include: first connection electrodes 41 , second connection electrodes 42 , third connection electrodes 43 , and fourth connection electrodes 44 , the fifth connection electrode 45 and the sixth connection electrode 46.
  • one end of the first connection electrode 41 may be connected to the first region 11 - 1 of the first active layer 11 through the first via hole V1 , and the other end of the first connection electrode 41 may be connected through the eighth via hole V8 Connected to the first initial signal line 31 .
  • One end of the second connection electrode 42 can be connected to the second region 11 - 2 of the first active layer 11 through the second via hole V2, and the other end can be connected to the first plate 25 through the seventh via hole V7.
  • the third connection electrode 43 may be connected to the first region 14-1 of the fourth active layer 14 through the third via hole V3.
  • connection electrode 44 can be connected to the first region 15 - 1 of the fifth active layer 15 through the fourth via hole V4 , and the other end can be connected to the second plate 33 through the ninth via hole V9 .
  • the fifth connection electrode 45 may be connected to the second region 16 - 2 of the sixth active layer 16 through the fifth via hole V5.
  • One end of the sixth connection electrode 46 may be connected to the first region 17 - 1 of the seventh active layer 17 through the sixth via hole V6 , and the other end may be connected to the second initial signal line 32 through the tenth via hole V10 .
  • the third conductive layer in the first area of the display area may further include: a plurality of first connection lines 71 and a plurality of first data connection electrodes 81 .
  • the third conductive layer in the third area of the display area may further include: a plurality of first compensation traces 91 and a plurality of first compensation connection electrodes 82 .
  • the third conductive layer in the frame area may include: a plurality of first compensation connection lines 83 .
  • the shape of the first connection line 71 may be a line shape in which the main body portion extends along the first direction X.
  • at least one first data connection electrode 81 may be provided on one side of the first connection line 71 in the second direction Y.
  • two first data connection electrodes 81 may be located on the same side of the first connection line 71 in the second direction Y.
  • the first connection line 71 is electrically connected to the plurality of first data connection electrodes 81 and may, for example, have an integrated structure.
  • the orthographic projection of the first connection line 71 on the base substrate may be located between the orthographic projection of the light-emitting control line 24 and the second initial signal line 32 on the base substrate that are electrically connected to the unit row.
  • the orthographic projection of the first connection line 71 and the plurality of first data connection electrodes 81 on the base substrate may not overlap with the orthographic projection of the light emission control line 24 and the second initial signal line 32 on the base substrate.
  • the shape of the first compensation trace 91 may be a line shape in which the main body portion extends along the first direction X.
  • at least one first compensation connection electrode 82 may be provided on one side of the first compensation trace 91 in the second direction Y.
  • the two first compensation connection electrodes 82 may be located on the same side of the first compensation trace 91 in the second direction Y.
  • the first compensation trace 91 is electrically connected to the plurality of first compensation connection electrodes 82, and may be an integrated structure, for example.
  • the front projection of the first compensation trace 91 on the base substrate may be located between the front projection of the light emitting control line 24 and the second initial signal line 32 electrically connected to the cell row on the base substrate.
  • the front projection of the first compensation trace 91 and the plurality of first compensation connection electrodes 82 on the base substrate may not overlap with the front projection of the light emission control line 24 and the second initial signal line 32 on the base substrate.
  • a plurality of data connection electrodes 81 and a plurality of first compensation connection electrodes 82 located in the same cell row may be sequentially arranged along the first direction X.
  • the shapes and sizes of the plurality of first compensation connection electrodes 82 and the plurality of data connection electrodes 81 may be the same.
  • a first break DF1 is provided between the first compensation trace 91 and the first connection line 71 located in the same cell row and aligned in the first direction X.
  • the first break DF1 cuts off the first connection line 71 and the first compensation line 91 in the same unit row.
  • the first connecting line 71 is adjacent to the first break DF1 on opposite sides in the first direction
  • the side opposite to the direction X is the first compensation trace 91 .
  • the other side of the first break DF1 is the first compensation trace 91 .
  • the first compensation trace 91 is provided between the first compensation trace 91 and the first connection line 71 located in the same cell row and aligned in the first direction X.
  • the first break DF1 cuts off the first connection line 71 and the first compensation line 91 in the same unit row.
  • the first connecting line 71 is adjacent to the first break DF1 on opposite sides in the first direction
  • the side opposite to the direction X is the first compensation trace 91 .
  • one end of at least one first compensation trace 91 may extend to the frame area and be electrically connected to the first compensation connection line 83 in the frame area.
  • the first compensation trace 91 and the first compensation connection line 83 may be an integral structure.
  • the first compensation connection line 8381 may first extend in the opposite direction of the second direction Y, and then extend in the first direction X or the opposite direction of the first direction X.
  • a fourth insulating layer is coated on the base substrate on which the foregoing pattern is formed, and a patterning process is used to pattern the first flat film to form the fourth insulating layer 114, as shown in FIG. 9F and FIG. As shown in 10B.
  • the fourth insulating layer 114 may also be called a first planar layer.
  • a plurality of via holes are provided on the fourth insulating layer 114 .
  • the multiple via holes of each circuit unit in the display area may include: eleventh via hole V11 to thirteenth via hole V13.
  • the fourth insulating layer 114 in the eleventh to thirteenth via holes V11 to V13 is removed, exposing the surface of the third conductive layer.
  • the plurality of circuit units in the first region and the plurality of circuit units in the second region may further include fourteenth to sixteenth via holes V14 to V16.
  • the fourth insulating layer 114 in the fourteenth to sixteenth via holes V14 to V16 may be removed, exposing the surface of the first data connection electrode 81 of the third conductive layer.
  • the plurality of circuit units in the third area may also include: a seventeenth via hole V17 and an eighteenth via hole V18.
  • the fourth insulating layer 114 in the seventeenth via hole V17 and the eighteenth via hole V18 is removed, exposing the surface of the first compensation connection electrode 82 of the third conductive layer.
  • the frame area may also include a nineteenth via V19.
  • the fourth insulating layer 114 in the nineteenth via hole V19 is removed, exposing the surface of the first compensation connection line 83 .
  • a fourth conductive film is deposited on the base substrate on which the foregoing pattern is formed, and a patterning process is used to pattern the fourth conductive film to form a fourth conductive film disposed on the fourth insulating layer 114 . layer, as shown in Figure 9G and Figure 10C.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the fourth conductive layers of multiple circuit units in the display area may each include: a first power supply line 51 , an anode connection electrode 52 and a data signal line 60 .
  • the shape of the first power line 51 may be a polyline shape with the main body portion extending along the second direction Y.
  • the first power line 51 can be electrically connected to the fourth connection electrode 44 through the twelfth via hole V12 in the display area, because the fourth connection electrode 44 can be connected to the second plate 33 and the fifth active electrode of the storage capacitor respectively through the via hole.
  • the first area 15-1 of the layer 15 is connected, thus realizing the first power line 51 writing the power signal to the first pole of the fifth transistor T5, and the second plate 33 of the storage capacitor has the same function as the first power line 51. potential.
  • the first power line 51 can also extend to the lead area and be electrically connected to the high-voltage lead in the lead area to achieve continuous reception of high-level signals.
  • the orthographic projection of the first power line 51 on the base substrate and the orthographic projection of the second connection electrode 42 on the base substrate may at least partially overlap.
  • the line 51 can effectively shield the impact of the data voltage jump on the key nodes in the pixel driving circuit, avoid the data voltage jump affecting the potential of the key nodes in the pixel driving circuit, and improve the display effect.
  • the first power lines 51 may be designed with unequal widths.
  • the first power lines 51 designed with unequal widths can not only facilitate the layout of the pixel structure, but also reduce the cost of the first power supply. Parasitic capacitance between the line and the data signal line.
  • the anode connection electrode 52 may be rectangular in shape.
  • the anode connection electrode 52 may be electrically connected to the fifth connection electrode 45 through the eleventh via hole V11.
  • the anode connection electrode 52 may be configured to be connected to a subsequently formed anode. Since the fifth connection electrode 45 may be connected to the second region 16 - 2 of the sixth active layer 16 through a via hole, the anode is realized.
  • the second electrode of the sixth transistor T6 is electrically connected through the anode connection electrode 52 and the fifth connection electrode 45 .
  • the shape of the data signal line 60 may be a straight line with the main part extending along the second direction Y.
  • the data signal line 60 may be electrically connected to the third connection electrode 43 through the thirteenth via hole V13. Since the third connection electrode 43 can be connected to the first region 14-1 of the fourth active layer 14 through the via hole, the data signal line 60 is realized to write the data signal into the first electrode of the fourth transistor T4.
  • One data signal line 60 may be configured to provide data signals to multiple pixel driving circuits of one unit column.
  • the fourth conductive layer of the plurality of circuit units in the first region may further include: second data connection electrodes 86 and a plurality of dummy electrodes 85.
  • the fourth conductive layer of the plurality of circuit units in the second region may further include: second connection lines 72 , second data connection electrodes 86 and a plurality of dummy electrodes 85 .
  • the fourth conductive layer of the plurality of circuit units in the third region may further include: second compensation traces 92 , a plurality of second compensation connection electrodes 87 and a plurality of dummy electrodes 85 .
  • the shape of the second connecting line 72 may be a straight line with the main body portion extending along the second direction Y.
  • the first power line 51 , the second connection line 72 and the data signal line 60 are sequentially arranged along the first direction X.
  • the second connection line 72 may be located between the first power line 51 and the data signal line 60 .
  • a second data connection electrode 86 or a dummy electrode 85 may be provided between the first power line 51 and the second connection line 72 .
  • the second connection line 72 may be electrically connected to the adjacent second data connection electrode 86, and may be an integral structure, for example.
  • a second data connection electrode 86 or a dummy electrode 85 may be provided on one side of the data signal line 60 along the first direction X.
  • the data signal line 60 may be electrically connected to the adjacent second data connection electrode 86, and may be an integral structure, for example.
  • the second data connection electrode 86 located at the Nth column and Mth row may be electrically connected to the first data connection electrode 81 through the fifteenth via V15 , thereby realizing the second data connection electrode 86 located at the Nth column.
  • the data signal line 60 is electrically connected to the first connection line 71 located in the M-th row.
  • the second data connection electrode 86 located in the N+1th row M can be electrically connected to the first data connection electrode 81 through the sixteenth via V16, thereby realizing the second connection line 72 located in the N+1th column and the second data connection electrode 86 located in the N+1th column.
  • the first connection line 71 of the Mth row is electrically connected.
  • the data signal line 60 located in the Nth column and the second connection line 72 located in the N+1th column can be electrically connected through the first connection line 71 located in the Mth row.
  • the fifteenth via hole V15 may be called a first connection hole
  • the sixteenth via hole V16 may be called a second connection hole.
  • the dummy electrodes 85 in the first region and the second region may be electrically connected to the first data connection electrode 81 through the fourteenth via hole V14.
  • the shape of the second compensation trace 92 may be a straight line with the main part extending along the second direction Y.
  • the first power supply line 51 , the second compensation line 92 and the data signal line 60 may be arranged in sequence along the first direction X.
  • the second compensation trace 92 may be located between the first power line 51 and the data signal line 60 .
  • a second compensation connection electrode 87 or a dummy electrode 85 may be provided between the first power supply line 51 and the second compensation trace 92.
  • the second compensation trace 92 may be electrically connected to the adjacent second compensation connection electrode 87 , and may be an integral structure, for example.
  • a dummy electrode 85 may be provided on one side of the data signal line 60 along the first direction X.
  • At least one second compensation connection electrode 87 may be electrically connected to the first compensation connection electrode 82 through the eighteenth via hole V18, thereby realizing the first compensation trace 91 and the second compensation trace. Electrical connection of line 92.
  • the eighteenth via hole V18 may be called a third connection hole.
  • a plurality of second compensation traces 92 and a plurality of first compensation traces 91 may be connected to each other to form a mesh connection structure.
  • the dummy electrode 85 in the third region may be electrically connected to the first compensation connection electrode 82 through the seventeenth via hole V17.
  • the orthographic projection of the dummy electrode 85 on the base substrate may overlap with the orthographic projection of the first data connection electrode 81 or the first compensation connection electrode 82 on the base substrate.
  • the dummy electrode 85 may have the same morphology and structure as the second compensation connection electrode 87 and the second data connection electrode 86, which not only improves the uniformity of the preparation process, but also allows different areas to have substantially the same transfer connection structure. Different areas can achieve basically the same display effect under transmitted light and reflected light, effectively eliminating shadowing, effectively avoiding poor appearance of the display substrate, and improving display quality and display quality.
  • the orthographic projection of the fourth conductive layer on the base substrate may cover the first fracture DF1 .
  • the orthographic projection of the first power line 51 of the fourth conductive layer on the base substrate may cover the first fracture DF1.
  • the orthographic projection of the first conductive layer (for example, the light emission control line 24 ) on the base substrate may cover the second fracture DF2 .
  • different areas can achieve basically the same display effect under transmitted light and reflected light, ensuring that the display substrate Appearance consistency.
  • the fourth conductive layer in the frame area may include: a plurality of second compensation connection lines 84 and the frame power lead 510 .
  • the second compensation connection line 84 may extend along the first direction X, and one end may be electrically connected to the frame power lead 510 , and the other end may be electrically connected to the first compensation connection line 83 through the nineteenth via V19 .
  • the second compensation connection line 84 and the edge power lead 510 may be an integral structure.
  • the frame power lead 510 may be located on the third conductive layer, and the second compensation connection line 84 may be electrically connected to the frame power lead 510 through a via hole opened in the fourth insulating layer.
  • the electrical connection between the first compensation trace 91 and the frame power lead 510 can be achieved through the first compensation connection line 83 and the second compensation connection line 84 .
  • the connection structure between the second compensation trace 92 and the frame power lead 510 or the binding power lead 410 is similar, and therefore will not be described again.
  • the driving circuit layer is prepared on the base substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a third scanning signal line connected to the pixel driving circuit. scanning signal line, light emitting control line, first power supply line, first initial signal line and second initial signal line.
  • the driving circuit layer may at least include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially stacked on the substrate. The third conductive layer, the fourth insulating layer, and the fourth conductive layer.
  • the substrate substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polyether One or more of styrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • the materials of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be Single layer, multi-layer or composite layer.
  • the first insulating layer 111 and the second insulating layer 112 are called gate insulating (GI) layers, and the third insulating layer 113 is called an interlayer insulating (ILD) layer.
  • the fourth insulating layer 114 may be made of organic material, such as resin.
  • the active layer can use amorphous indium gallium zinc oxide materials (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), Materials such as hexathiophene or polythiophene, that is, this disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide materials
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • a light-emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer, which will not be described again.
  • the lead lines of the binding area are connected to the data signal lines through the data connection lines, so that the lead area There is no need to set a fan-shaped diagonal line, which effectively reduces the length of the lead area, greatly reduces the width of the lower border, improves the screen-to-body ratio, and is conducive to achieving a full-screen display.
  • the first connection line and the second connection line of the data connection line are arranged on different conductive layers, which can facilitate the layout of the data connection line and avoid a large number of wires to be arranged together, so that different areas can see evenly under transmitted light and reflected light.
  • the trace arrangement in the display area can be further balanced, effectively eliminating ghosting and effectively avoiding poor appearance of the display substrate.
  • the compensation traces into a mesh connection structure, it can not only effectively reduce the resistance of the power traces, effectively reduce the voltage drop of the low-voltage power signal, achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate. , effectively improving display uniformity, improving display quality and display quality.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • a buffer layer may be provided between the semiconductor layer and the base substrate.
  • FIG. 11A is another partially enlarged schematic diagram of the display substrate after the fourth conductive layer is formed in the region C1 in FIG. 7A .
  • FIG. 11B is another partially enlarged schematic diagram of the display substrate after the fifth insulating layer is formed in the region C1 in FIG. 7A .
  • FIG. 11C is another partially enlarged schematic diagram of the display substrate after the fifth conductive layer is formed in the region C1 in FIG. 7A .
  • FIG. 11D is a partially enlarged schematic diagram of the fourth conductive layer and the fifth conductive layer in the region C1 in FIG. 7A.
  • Figure 11E is a schematic cross-sectional view along the U-U' direction in Figure 11C.
  • the driving circuit layer may include: a first conductive layer and a second conductive layer sequentially disposed on the base substrate 101 , a third conductive layer, a fourth conductive layer and a fifth conductive layer.
  • the fourth conductive layer may include: the data signal line 60 , the second connection line 72 and the second compensation line 92
  • the fifth conductive layer may include: the first connection line 71 and the first compensation line 91 .
  • the first insulating layer 111 may be disposed between the semiconductor layer and the first conductive layer
  • the second insulating layer 112 may be disposed between the first conductive layer and the second conductive layer
  • the third insulating layer 113 may be disposed on the second conductive layer.
  • the fourth insulating layer 114 may be disposed between the third conductive layer and the fourth conductive layer.
  • the fifth insulating layer 115 may be disposed between the fourth conductive layer and the fifth conductive layer.
  • the driving circuit layer of this example may include three source and drain metal layers.
  • the fourth conductive layers of multiple circuit units in the display area may include: a first power line 51 , an anode connection electrode 52 , and a data signal line 60 .
  • the fourth conductive layer of the display area may further include: second connection lines 72 , second data connection electrodes 86 , second compensation wires 92 , second compensation connection electrodes, and a plurality of dummy electrodes 85 .
  • the fifth insulation layer 115 of the display area may be provided with a plurality of via holes.
  • the plurality of circuit units in the first region and the plurality of circuit units in the second region may include: twenty-first to twenty-third via holes V21 to V23.
  • the plurality of circuit units in the third region may include at least the twenty-fourth via V24.
  • the fifth insulating layer 115 in the twenty-first via hole V21 to the twenty-fourth via hole V24 is removed, exposing the surface of the fourth conductive layer.
  • the fifth conductive layer of the display area may include: a first connection line 71 , a first compensation trace 91 , a first data connection electrode 81 and a first compensation connection electrode 82 .
  • the first connection line 71 and the plurality of first data connection electrodes 81 may have an integrated structure.
  • the first compensation trace 91 and the plurality of first compensation connection electrodes 82 may be an integral structure.
  • the first data connection electrode 81 located in the Nth column and Mth row can be electrically connected to the second data connection electrode 86 through the twenty-first via V21, thereby realizing the first connection line 71 located in the Mth row. It is electrically connected to the data signal line 60 located in the Nth column.
  • the first data connection electrode 81 located in the N+1th column and the Mth row can be electrically connected to the second data connection electrode 86 through the 22nd via V22, thereby realizing the first connection line 71 located in the Mth column and the first data connection electrode 81 located in the Mth row.
  • the second connection lines 72 in the N+1 column are electrically connected.
  • the twenty-first via hole V21 may be called a first connection hole
  • the twenty-second via hole V22 may be called a second connection hole.
  • the first data connection electrode 81 may be electrically connected to the dummy electrode 85 through the twenty-third via hole V23.
  • the first compensation connection electrode 82 may be electrically connected to the dummy electrode 85 through the twenty-fourth via hole V24.
  • the first compensation connection electrode may also be electrically connected to the second compensation connection electrode to achieve electrical connection between the first compensation wiring and the second compensation wiring.
  • the orthographic projection of the first fracture DF1 provided between the first compensation trace 91 and the first connecting line 71 of the substrate may be located within the orthographic projection range of the fourth conductive layer, For example, it may be covered by the front projection of the first power line 51 .
  • the orthographic projection of the second fracture DF2 provided between the second compensation line 92 and the second connecting line 72 on the substrate can be located within the orthographic projection range of the first conductive layer, and can be controlled by luminescence, for example. Orthographic projection coverage of lines.
  • this embodiment is not limited to this.
  • a second flat film may be coated, and a patterning process may be used to pattern the second flat film to form the fifth insulating layer 115, and then , deposit a fifth conductive film, and pattern the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the fifth insulating layer 115 .
  • the fifth conductive layer may be called a third source-drain metal (SD3) layer.
  • SD3 source-drain metal
  • the fifth insulating layer may be called a second planarization layer.
  • the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals,
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals,
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the fifth insulating layer can be made of organic materials, such as resin.
  • the display substrate provided in this example can reduce the load of the first connection line by arranging the first connection line on the fifth conductive layer, and is suitable for display substrates with higher refresh rates.
  • FIG. 12A is another partially enlarged schematic diagram of the display substrate after the second conductive layer is formed in the region C1 in FIG. 7A.
  • FIG. 12B is another partially enlarged schematic diagram of the display substrate after the third insulating layer is formed in the region C1 in FIG. 7A.
  • FIG. 12C is another partially enlarged schematic diagram of the display substrate after the third conductive layer is formed in the region C1 in FIG. 7A .
  • FIG. 12D is a partially enlarged schematic diagram of the second conductive layer and the third conductive layer in the region C1 in FIG. 7A.
  • Figure 12E is a schematic cross-sectional view along the R-R' direction in Figure 12C.
  • the driving circuit layer may include: a first conductive layer and a second conductive layer sequentially disposed on the base substrate 101 and a third conductive layer.
  • the first insulating layer 111 may be disposed between the semiconductor layer and the first conductive layer
  • the second insulating layer 112 may be disposed between the first conductive layer and the second conductive layer
  • the third insulating layer 113 may be disposed on the second conductive layer. and the third conductive layer.
  • the second conductive layer of each circuit unit in the display area may include: a first initial signal line 31 , a second initial signal line 32 , a second plate 33 of the storage capacitor, and The plate connection wire 34 and the shield electrode 35 are connected.
  • the plurality of circuit units in the first area of the display area may include: first connection lines 71 and a plurality of first data connection electrodes 81 .
  • the plurality of circuit units in the third area of the display area may include: first compensation wires 91 and a plurality of first compensation connection electrodes 82 .
  • the third insulating layer may be provided with multiple via holes.
  • the plurality of circuit units in the first region and the plurality of circuit units in the second region may further include: twenty-sixth to twenty-eighth via holes V26 to V28.
  • the multiple circuit units in the third area may also include: a twenty-ninth via V29.
  • the third insulating layer 113 in the twenty-sixth via hole V26 to the twenty-ninth via hole V29 is removed, exposing the surface of the second conductive layer.
  • the third conductive layer of the plurality of circuit units in the first region and the second region may further include: second connection lines 72 , second data connection electrodes 86 and a plurality of dummy electrodes 85 .
  • the third conductive layer of the plurality of circuit units in the third region may also include: second compensation traces 92 , second compensation connection electrodes, and a plurality of dummy electrodes 85 .
  • the first power line 51 may be located on the third conductive layer, and the shape of the first power line 51 may be a straight segment whose main body portion extends along the second direction Y.
  • the second compensation line 92 and the second connection line 72 may be located on a side of the data signal line 60 away from the first power line 51 .
  • the second data connection electrode 86 located in the Nth column and Mth row can be electrically connected to the first data connection electrode 81 through the twenty-sixth via V26, thereby realizing the first connection line 71 located in the Mth row. It is electrically connected to the data signal line 60 located in the Nth column.
  • the second data connection electrode 87 located at the N+1th column and the Mth row can be electrically connected to the first data connection electrode 81 through the twenty-seventh via hole V27, thereby realizing the first connection line 71 located at the Mth column and the first data connection electrode 87 located at the Mth row.
  • the second connection lines 72 in the N+1 column are electrically connected.
  • the twenty-sixth via hole V26 may be called a first connection hole, and the twenty-seventh via hole V27 may be called a second connection hole.
  • the dummy electrode 85 may be electrically connected to the first data connection electrode 81 through the twenty-eighth via V28.
  • the dummy electrode 85 can be electrically connected to the first compensation connection electrode 82 through the twenty-ninth via hole V29.
  • the first compensation connection electrode may also be electrically connected to the second compensation connection electrode to achieve electrical connection between the first compensation wiring and the second compensation wiring.
  • the orthographic projection of the first fracture DF1 provided between the first compensation trace 91 and the first connecting line 71 of the substrate may be located within the orthographic projection range of the third conductive layer, For example, it may be covered by the front projection of the first power line 51 .
  • the second fracture DF2 provided between the second compensation line 92 and the second connection line 72 can be located within the orthographic projection range of the first conductive layer on the substrate substrate, and can be controlled by luminescence, for example. Orthographic projection coverage of lines.
  • this embodiment is not limited to this.
  • the driving circuit layer only includes three conductive layers, which can reduce the process flow, reduce the use of masks and production materials, thereby reducing costs.
  • FIG. 13 is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • only the first compensation line 91 may be provided in at least one unit row
  • only at least one first connection line 71 may be provided in at least one unit row.
  • the first connection line 71 may extend toward the center line O from a side close to the left or right frame area.
  • One end of the first connection line 71 may extend to the boundary between the left or right frame area and the display area, and the other end may extend to the center line O.
  • At least two first connection lines 71 in at least one unit row can be aligned in the first direction, and breaks can be provided between adjacent first connection lines 71 to realize the connection between different data signal lines 60 and data connection lines 70 Connection.
  • only the second compensation wiring 92 may be provided in at least one unit column, and only the second connection line 72 may be provided in at least one unit column.
  • the second connection line 72 may penetrate the display area 100 along the second direction D2.
  • One end of the second connection line 72 may extend to the boundary between the upper frame area and the display area, and the other end may extend to the boundary B between the binding area and the display area.
  • FIG. 14 is a partially enlarged schematic diagram of the driving circuit layer in area C3 in FIG. 13 .
  • the driving circuit layer includes three source and drain metal layers as an example.
  • the first connection line 71, the first compensation line 91, the first data connection electrode 81 and the first compensation connection electrode 82 may be located on the fifth conductive layer, the second connection line 72, the second compensation line 92.
  • the data signal line 60, the first power line 51, the second data connection electrode, the second compensation connection electrode and the dummy electrode may be located on the fourth conductive layer.
  • the load of the first connection line can be reduced, thereby increasing the length of the first connection line and simplifying the wiring arrangement.
  • FIG. 15 is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • the first connection line 71 may penetrate the display area 100 along the first direction X.
  • One end of the first connection line 71 may extend to the boundary between the left frame area and the display area, and the other end may extend to the boundary between the right frame area and the display area.
  • At least one unit row may be provided with only one first connection line 71 .
  • the first connection line 71 may be electrically connected to the data signal line 60 and the second connection line 72 .
  • the first compensation line 91 may be arranged in parallel and on the same layer as the first connection line 71 , and the first compensation line 91 may extend from the left frame area to the right frame area.
  • the second connection line 72 may penetrate the display area along the second direction Y. One end of the second connection line 72 may extend to the boundary between the upper frame area and the display area, and the other end may extend to the boundary between the binding area and the display area.
  • the second compensation trace 92 may be parallel to the second connection line 72 and arranged on the same layer. The second compensation trace 92 may extend from the upper side frame area to the binding area.
  • first connection line 71 and the first compensation line 91 may be located on the fifth conductive layer
  • second connection line 72 , the second compensation line 92 and the data signal line 60 may be located on the fourth conductive layer.
  • this embodiment is not limited to this.
  • At least one circuit unit of the display area may include a plurality of invalid pixel circuits.
  • An orthographic projection of the at least one second connection line on the base substrate may overlap with an orthographic projection of the ineffective pixel driving circuit of at least one unit column on the base substrate.
  • the display area of the display substrate may include an under-display camera (UDC, Under Display Camera) area and a normal display area, and the orthographic projection of the photosensitive sensor (such as a camera and other hardware) on the display substrate may be located in the under-screen camera area. .
  • UDC Under Display Camera
  • the orthographic projection of the photosensitive sensor such as a camera and other hardware
  • FIG. 16 is a schematic diagram of the arrangement of circuit units according to at least one embodiment of the present disclosure.
  • the plurality of unit columns of the display area may include: a plurality of first unit columns 75 and a plurality of second unit columns 76 .
  • the first unit column 75 may include a plurality of effective pixel driving circuits.
  • the second unit column 76 may include a plurality of inactive pixel driving circuits.
  • the first unit column 75 and the second unit column 76 may be arranged at intervals along the first direction X.
  • four first unit columns 75 may be provided between two adjacent second unit columns 76 .
  • this embodiment is not limited to this.
  • one or more first unit columns may be provided between two adjacent second unit columns.
  • FIG. 17 is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 18A is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in area C4 in FIG. 17 .
  • FIG. 18B is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C4 in FIG. 17 .
  • FIG. 18C is a schematic diagram of the third conductive layer and the fourth conductive layer in FIG. 18B.
  • the second connection lines 72 may be arranged in a unit column including an inactive pixel driving circuit (ie, the aforementioned second unit column).
  • At least one second cell column may include at least one second connection line 72 and at least one second compensation trace 92 .
  • at least one second cell column may include a second connection line 72 and a second compensation trace 92 .
  • this embodiment is not limited to this.
  • the driving circuit layer of the display substrate may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially provided on the base substrate.
  • conductive layer A first insulating layer is disposed between the semiconductor layer and the first conductive layer.
  • a second insulating layer is disposed between the first conductive layer and the second conductive layer.
  • a third insulating layer is disposed between the second conductive layer and the third conductive layer.
  • a fourth insulating layer is disposed between the third conductive layer and the fourth conductive layer.
  • the driving circuit layer of this example may include two source and drain metal layers.
  • the third conductive layer of the display area may include at least: a first connection line 71 , a first compensation trace 91 , a first data connection electrode 81 , and a first compensation connection electrode 82 .
  • the shape of the first connecting line 71 may be a polyline shape with the main body portion extending along the second direction Y.
  • the first connecting line 71 may be a curve or an S-shaped line.
  • the first connection line 71 and the plurality of first data connection electrodes 81 may have an integrated structure.
  • the shape of the first compensation trace 91 may be a polyline shape with the main part extending along the second direction Y.
  • the first compensation trace 91 may be a curve or an S-shaped line.
  • the first compensation trace 91 and the plurality of first compensation connection electrodes 82 may be an integral structure.
  • the fourth conductive layer of the display area may include at least: a second connection line 72 , a second compensation line 92 , a data signal line 60 , a first power line 51 , and a second data connection. Electrode 86, dummy electrode 85 and second compensation connection electrode.
  • the second connection line 72 may have an integral structure with one of its adjacent second data connection electrodes 86 .
  • the data signal line 60 may have an integrated structure with its adjacent second data connection electrode 86 .
  • the second unit column ie, the unit column including the inactive pixel circuit
  • the second unit column may arrange at least one second connection line and a second compensation line.
  • the anode connection electrode and the first power line of the fourth conductive layer of the second unit column may not be electrically connected to the third conductive layer.
  • this embodiment is not limited to this.
  • the Nth column and the N+5th column may be second unit columns.
  • the N-4th to N-1th columns and the N+1st to N+4th columns may be the first unit columns.
  • the fourth conductive layer of the Nth column and the N+5th column may include: a first power line 51 , a second connection line 72 , a second compensation line 92 , a second data connection electrode 86 and a dummy electrode 85 .
  • the first power line of the fourth conductive layer of the second unit column may not be electrically connected to the third conductive layer.
  • the first power line 51 may be adjacent to the second connection line 72 and the second compensation trace 92 .
  • the fourth conductive layer in the N-4th to N-1th columns and the N+1th to N+4th columns may include: a first power line 51 and a data signal line 60, a dummy electrode 85, and a second data connection. Electrode 86.
  • the second connection line 72 located in the Nth column may be connected to the data signal line 60 located in the N-1th column through the first connection line 71 located in the M+1th row. Electrical connection.
  • the second connection line 72 located in the N+5th column may be electrically connected to the data signal line 60 located in the N-2th column through the first connection line 71 located in the Mth row.
  • one end of the first connection line 71 can be integrated with the first data connection electrode 81, and the first data connection electrode 81 can be electrically connected to the second data connection electrode 86 through the via hole of the fourth insulating layer.
  • connection electrode 86 may be an integral structure with the data signal line 60 to achieve electrical connection between the first connection line 71 and the data signal line 60 .
  • the other end of the first connection line 71 may have an integral structure with another first data connection electrode 81, and the first data connection electrode 81 may be electrically connected to another second data connection electrode 86 through a via hole of the fourth insulating layer, Since the second data connection electrode 86 can be integrated with the second connection line 72 , the first connection line 71 and the second connection line 72 are electrically connected.
  • the dummy electrode 85 may have the same morphology and structure as the second compensation connection electrode and the second data connection electrode 86 , which not only improves the uniformity of the preparation process, but also allows different areas to have substantially the same transformation. With the continuous connection structure, different areas can achieve basically the same display effect under transmitted light and reflected light, effectively eliminating shadowing, effectively avoiding poor appearance of the display substrate, and improving display quality and display quality.
  • the second connection line and the second compensation line in the second unit column, a large number of lines can be avoided to be arranged together, so that different areas can achieve substantially the same quality under transmitted light and reflected light.
  • the display effect effectively eliminates shadow elimination, effectively avoids the poor appearance of the display substrate, and improves the display quality and display quality.
  • FIG. 19 is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • the plurality of data signal lines 60 of the display area 100 may extend along the second direction Y and be arranged at set intervals along the first direction X in an increasing numbered manner. Sequence settings.
  • the plurality of data signal lines 60 in the display area can be connected to the data connection lines 70 correspondingly.
  • the multiple lead lines 80 of the lead area 201 can all be connected to the data connection lines 70 correspondingly.
  • all lead-out lines 80 may not be directly connected to the data signal line 60 , but may be connected through the data connection line 70 .
  • all the data signal lines 60 are connected to the lead lines 80 through the data connection lines 70 .
  • the data connection line 70 may include a first connection line 71 extending along the first direction X and a second connection line 72 extending along the second direction Y.
  • the display area has a center line O in the first direction X.
  • the first connection line 71 electrically connected to the data signal line 60 close to the center line O can be located far away from the first connection line 71 electrically connected to the data signal line 60 far away from the center line O.
  • the second connection line 72 electrically connected to the data signal line 60 close to the center line O may be located on a side close to the center line O to the second connection line 72 electrically connected to the data signal line 60 far away from the center line O.
  • the lengths of the plurality of first connection lines 71 along the first direction X may gradually increase along the second direction.
  • the length of the plurality of second connection lines 72 along the second direction Y may gradually increase along the first direction X.
  • this embodiment is not limited to this.
  • FIG. 20 is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • a plurality of second connection lines 72 may penetrate the display area 100 along the second direction Y.
  • One end of the second connection line 72 may extend to the boundary between the upper frame area and the display area 100 , and the other end may extend to the boundary between the display area 100 and the binding area 200 .
  • FIG. 21 is another schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 22 is a plan structural view of a compensation trace according to at least one embodiment of the present disclosure.
  • the driving circuit layer of the display area 100 may include: multiple circuit units constituting a circuit unit array, multiple data signal lines 60 , multiple data connection lines 70 and compensation lines. Line 90.
  • the layout and structure of the plurality of circuit units, the plurality of data signal lines 60 and the plurality of data connection lines 70 are substantially the same as those shown in FIG. 20 .
  • the compensation trace 90 may include a plurality of first compensation traces 91 extending along the first direction X and a plurality of second compensation traces 92 extending along the second direction Y.
  • a plurality of first compensation traces 91 may be arranged in sequence along the second direction Y, and a plurality of second compensation traces 92 may be arranged in sequence along the first direction X.
  • the first compensation trace 91 and the second compensation trace 92 may be provided in different conductive layers.
  • the first compensation line 91 and the first connection line 71 may be arranged on the same layer
  • the second compensation line 92 and the second connection line 72 may be arranged on the same layer.
  • FIG. 23A is a partially enlarged schematic view of the display substrate after the third conductive layer is formed in area C5 in FIG. 21 .
  • FIG. 23B is a partially enlarged schematic view of the display substrate after the fourth conductive layer is formed in area C5 in FIG. 21 .
  • FIG. 23C is a partially enlarged schematic view of the display substrate after the fifth insulating layer is formed in area C5 in FIG. 21 .
  • FIG. 23D is a partially enlarged schematic view of the display substrate after the fifth conductive layer is formed in area C5 in FIG. 21 .
  • FIG. 23E is a partially enlarged schematic diagram of the third conductive layer, the fourth conductive layer and the fifth conductive layer in area C5 in FIG. 21 .
  • FIG. 23A to FIG. 23E only illustrate the structure of several unit rows (for example, including the M-1th row and the Mth row) and several unit columns (for example, including the N-1th column to the N+3th column) in the area C5.
  • the driving circuit layer of the display substrate may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially disposed on the base substrate.
  • conductive layer A first insulating layer is disposed between the semiconductor layer and the first conductive layer.
  • a second insulating layer is provided between the first conductive layer and the second conductive layer.
  • a third insulating layer is disposed between the second conductive layer and the third conductive layer.
  • a fourth insulating layer is provided between the third conductive layer and the fourth conductive layer.
  • a fifth insulating layer is disposed between the fourth conductive layer and the fifth conductive layer.
  • the driving circuit layer of this example may include three source and drain metal layers.
  • the third conductive layer of the display area may include: a plurality of connection electrodes and a first power line 51 .
  • the first power line 51 may be connected to the second plate 33 of the storage capacitor and the first region of the fifth active layer through a via hole opened in the third insulating layer.
  • the fourth conductive layer of the display area may include at least: an anode connection electrode 52 , a shielding electrode 53 , a data signal line 60 , a second connection line 72 and a second compensation trace.
  • the shielding electrode 53 can be electrically connected to the first power line 51 through a via hole opened in the fourth insulation layer.
  • the gate electrode of the third transistor T3 of the pixel driving circuit, the second electrode of the first transistor T1 , the first electrode of the second transistor T2 and the first plate of the storage capacitor are electrically connected to the first node N1 .
  • At least one unit column may be provided with one data signal line 60 and at least two second connection lines 72 .
  • the two second connection lines 72 may be adjacent to the data signal line 60 .
  • the orthographic projection of the data signal line 60 on the base substrate may be located between the orthographic projections of the first power line 51 and the second connection line 72 on the base substrate.
  • this embodiment is not limited to this.
  • at least one cell column may include a plurality of second connection lines.
  • two adjacent unit columns may include three second connection lines.
  • the fifth insulation layer of the display area may be provided with multiple via holes.
  • the plurality of via holes opened in the fifth insulating layer may include: the thirty-first via hole V31 to the thirty-third via hole V33.
  • the fifth insulating layer in the thirty-first to thirty-third via holes V31 to V33 can be removed to expose the surface of the fourth conductive layer.
  • the plurality of via holes opened in the fifth insulating layer may be arranged sequentially along the first direction X.
  • the orthographic projection of the plurality of via holes in a unit row on the base substrate may overlap with the orthographic projection of the second scan line 22 of the unit row on the base substrate. In this example, setting multiple regularly arranged vias helps to improve the uniformity of the preparation process.
  • the fifth conductive layer of the display area may include: a first connection line 71 and a first compensation trace 91 extending along the first direction X, a first data connection electrode 81 and a dummy electrode. 85.
  • the first connection line 71 and the first compensation line 91 may be straight lines extending along the first direction X. Both ends of the first connection line 71 may be electrically connected to the first data connection electrode 81 respectively, and may be of an integrated structure, for example.
  • the first end of the first connection line 71 located in the M-1th row may be electrically connected to the data signal line 60 located in the N+2th column through the first data connection electrode 81 via the thirty-first via V31.
  • the two ends can be electrically connected to a second connection line 72 located in the N+3th column through another first data connection electrode 81 through the thirty-second via V32.
  • the first end of the first connection line 71 located in the M-th row can be electrically connected to the data signal line 60 located in the N+1-th column through a first data connection electrode 81 through the thirty-first via V31, and the second end can The other first data connection electrode 81 is electrically connected to another second connection line 72 located in the N+3th column through the thirty-second via hole V32.
  • the data signal line 60 located in the N+3th column can be electrically connected to a second connection line 72 on the right side of the data signal line 60 through another first connection line 71 located in the M-1th row.
  • the first data connection electrode can be directly electrically connected to the data signal line or the second connection line without the need for transfer through other connection electrodes, thereby saving arrangement space.
  • the fourth conductive layer may further include: a second data connection electrode and a second compensation connection electrode.
  • the second data connection electrode may have an integral structure with the data signal line or the second connection line
  • the second compensation connection electrode may have an integral structure with the second compensation wiring.
  • the first data connection electrode may be electrically connected to the second data connection electrode
  • the second compensation connection electrode may be electrically connected to the first compensation connection electrode.
  • the plurality of first data connection electrodes 81 and the plurality of dummy electrodes 85 may be located on the same side of the first connection line 71 in the second direction Y. In one unit row, a plurality of first data connection electrodes 81 and a plurality of dummy electrodes 85 may be aligned and arranged along the first direction X. The dummy electrode 85 may be electrically connected to the data signal line 60 or the second connection line 72 through the thirty-third via hole V33. The orthographic projection of the dummy electrode 85 on the base substrate may at least partially overlap with the orthographic projection of the data signal line 60 or the second connection line 72 on the base substrate.
  • the morphology and structure of the dummy electrode 85 can be the same as that of the first data connection electrode 81, which not only improves the uniformity of the preparation process, but also allows different areas to have basically the same transfer connection structure, and different areas have different differences in transmitted light and reflection. Basically the same display effect can be achieved under light, effectively eliminating shadowing, effectively avoiding poor appearance of the display substrate, and improving display quality and display quality.
  • the fifth conductive layer of the display area may further include a plurality of first compensation connection electrodes.
  • the first compensation trace 91 may be an integral structure with a plurality of first compensation connection electrodes.
  • the first compensation wire 91 may be electrically connected to the second compensation wire 92 through the first compensation connection electrode.
  • the morphology and structure of the first compensation connection electrode may be the same as the first data connection electrode 81, thereby improving the uniformity of the preparation process.
  • a first break DF1 is provided between the first connection line 71 and the first compensation line 91 .
  • the orthographic projection of the first fracture DF1 on the base substrate may be located in the area covered by the third conductive layer or the fourth conductive layer.
  • the orthographic projection of the first fracture DF1 on the base substrate may be covered by the orthographic projection of the second connection line of the fourth conductive layer on the base substrate.
  • the orthographic projection of the first fracture DF1 on the base substrate may be covered by the orthographic projection of the first power line 51 of the third conductive layer on the base substrate.
  • FIG. 24 is a schematic diagram of the appearance of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate of this embodiment arranges the first connection lines and the second connection lines on different conductive layers, and also sets the first compensation traces and the second compensation lines in the display area. Except for the small differences in the breaks of the data connection lines and the compensation lines, the wiring in different areas of the display area can be consistent, so that different areas can achieve basically the same display under transmitted light and reflected light. The effect effectively eliminates shadowing, effectively avoids poor appearance of the display substrate, and improves display quality and display quality.
  • FIG. 25A is another partially enlarged schematic diagram of the display substrate after the third conductive layer is formed in area C5 in FIG. 21 .
  • FIG. 25B is another partially enlarged schematic diagram of the display substrate after the fourth conductive layer is formed in area C5 in FIG. 21 .
  • FIG. 25C is a partially enlarged schematic diagram of the third conductive layer and the fourth conductive layer in area C5 in FIG. 21 .
  • FIGS. 25A to 25C only illustrate the structures of several unit rows (for example, including the M-1th row and the Mth row) and several unit columns (for example, including the N-1th column to the N+3th column) in the area C5.
  • the driving circuit layer of the display substrate may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the base substrate.
  • a first insulating layer is disposed between the semiconductor layer and the first conductive layer.
  • a second insulating layer is provided between the first conductive layer and the second conductive layer.
  • a third insulating layer is provided between the second conductive layer and the third conductive layer.
  • a fourth insulating layer is provided between the third conductive layer and the fourth conductive layer.
  • the driving circuit layer of this example may include two source and drain metal layers.
  • the third conductive layer of the display area may include: a plurality of connection electrodes, a first connection line 71 , a first compensation trace 91 , a first data connection electrode 81 and a plurality of dummy electrodes. 85.
  • the orthographic projection of the first connection line 71 and the first compensation trace 91 on the substrate may be located between the orthographic projection of the light-emitting control line 24 and the second initial signal line 32 of the unit row on the substrate.
  • a plurality of dummy electrodes 85 may be provided in at least one circuit unit, or the dummy electrodes 85 and the first data connection electrode 81 may be provided.
  • a plurality of dummy electrodes 85 and a plurality of first data connection electrodes 81 are arranged along the first direction X.
  • the plurality of dummy electrodes 85 and the plurality of first data connection electrodes 81 may be located on the same side of the first connection line 71 of the current unit row in the second direction Y.
  • the first connection line 71 may be an integral structure with the plurality of first data connection electrodes 81 .
  • the third conductive layer may further include: a plurality of first compensation connection electrodes.
  • the plurality of first compensation connection electrodes may be integrated with the first compensation wiring.
  • the morphology and structure of the first compensation connection electrode may be the same as the first data connection electrode 81 and the dummy electrode 85, thereby improving the uniformity of the preparation process.
  • the fourth conductive layer of the display area may include: an anode connection electrode, a data signal line 60 , a second connection line 72 , a first power supply line 51 and a second compensation trace.
  • At least one unit column may be provided with one data signal line 60 and at least two second connection lines 72 .
  • the two second connection lines 72 may be adjacent to the data signal line 60 .
  • the orthographic projection of the data signal line 60 on the base substrate may be located between the orthographic projections of the first power line 51 and the second connection line 72 on the base substrate.
  • the first power line 51 may be disposed on the third conductive layer.
  • a first break DF1 is provided between the first connection line 71 and the first compensation line 91 .
  • the orthographic projection of the first fracture DF1 on the base substrate may be located in the area covered by the fourth conductive layer.
  • the orthographic projection of the first fracture DF1 on the base substrate may be covered by the orthographic projection of the second connection line, data signal line or first power line of the fourth conductive layer on the base substrate.
  • FIG. 26A is another partially enlarged schematic diagram of the display substrate after the second conductive layer is formed in the region C5 in FIG. 21 .
  • FIG. 26B is another partially enlarged schematic diagram of the display substrate after the third conductive layer is formed in area C5 in FIG. 21 .
  • FIG. 26C is a partially enlarged schematic diagram of the second conductive layer and the third conductive layer in area C5 in FIG. 21 .
  • FIGS. 26A to 26C only illustrate the structures of several unit rows (for example, including the M-1th row and the Mth row) and several unit columns (for example, including the N-1th column to the N+3th column) in the area C5.
  • the driving circuit layer of the display substrate may include: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the base substrate.
  • a first insulating layer is disposed between the semiconductor layer and the first conductive layer.
  • a second insulating layer is provided between the first conductive layer and the second conductive layer.
  • a third insulating layer is provided between the second conductive layer and the third conductive layer.
  • the driving circuit layer of this example may include a single source-drain metal layer.
  • the second conductive layer of the display area may include: a first initial signal line 31 , a second initial signal line 32 , a second plate 33 of a storage capacitor, a plate connection electrode, a shield electrodes, first connection lines 72 , first compensation lines 91 , first data connection electrodes 81 , and a plurality of dummy electrodes 85 .
  • the orthographic projection of the first connection line 71 and the first compensation trace 91 on the substrate may be located between the orthographic projection of the light-emitting control line 24 and the second initial signal line 32 of the unit row on the substrate. .
  • a plurality of dummy electrodes 85 may be provided in at least one circuit unit, or the dummy electrodes 85 and the first data connection electrode 81 may be provided. In one unit row, a plurality of dummy electrodes 85 and a plurality of first data connection electrodes 81 are arranged along the first direction X. The plurality of dummy electrodes 85 and the plurality of first data connection electrodes 81 may be located on the same side of the first connection line 71 of the current unit row in the second direction Y. The first connection line 71 may be an integral structure with the plurality of first data connection electrodes 81 .
  • the second conductive layer may further include: a plurality of first compensation connection electrodes. The plurality of first compensation connection electrodes may be integrated with the first compensation wiring. The morphology and structure of the first compensation connection electrode may be the same as the first data connection electrode 81 and the dummy electrode 85, thereby improving the uniformity of the preparation process.
  • the third conductive layer of the display area may include: a plurality of connection electrodes, the data signal line 60 , the first connection line 72 , the first power line 51 and the second compensation trace.
  • the two second connection lines 72 , the first power line 51 and the data signal line 60 may be arranged sequentially along the first direction X.
  • the two second connection lines 72 may be adjacent to the data signal line 60 .
  • the orthographic projection of the data signal line 60 on the base substrate may be located between the orthographic projection of the first power line 51 and the second connection line 72 on the base substrate.
  • a first break DF1 is provided between the first connection line 71 and the first compensation line 91 .
  • the orthographic projection of the first fracture DF1 on the base substrate may be located in the area covered by the third conductive layer.
  • the orthographic projection of the first fracture DF1 on the base substrate may be covered by the orthographic projection of the second connection line, data signal line or first power line of the third conductive layer on the base substrate.
  • the first connection line and the first compensation trace may be located on the fourth conductive layer, and the first power line, the second connection line, the data signal line and the second compensation trace may be located on the third conductive layer. layer.
  • the first connection line and the first compensation line may be located on the fourth conductive layer, and the second connection line and the second compensation line may be located on the fifth conductive layer.
  • the data signal line and the first power line can both be located on the third conductive layer, or both can be located on the fifth conductive layer; or, the data signal line can be located on the third conductive layer, and the first power line can be located on the fifth conductive layer; or, The data signal line may be located on the fifth conductive layer, and the first power supply line may be located on the third conductive layer.
  • the lead lines in the binding area are connected to the data signal lines through the data connection lines, so that there is no need to set fan-shaped diagonal lines in the lead area, effectively reducing the
  • the length of the lead area greatly reduces the width of the lower border and increases the screen-to-body ratio, which is conducive to achieving full-screen display.
  • the first connection line and the second connection line of the data connection line are arranged on different conductive layers, which can facilitate the layout of the data connection line and avoid a large number of wires to be arranged together, so that different areas can see evenly under transmitted light and reflected light.
  • the trace arrangement in the display area can be further balanced, effectively eliminating ghosting and effectively avoiding poor appearance of the display substrate.
  • the compensation traces into a mesh connection structure, it can not only effectively reduce the resistance of the power traces, effectively reduce the voltage drop of the low-voltage power signal, achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate. , effectively improving display uniformity, improving display quality and display quality.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the display substrate of the embodiment of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot Light emitting diode display (QDLED), etc., this disclosure is not limited here.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot Light emitting diode display (QDLED), etc.
  • An embodiment of the present disclosure also provides a display device, which may include the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板，包括：显示区域(100)和位于显示区域(100)一侧的绑定区域(200)。显示区域(100)包括：衬底基板(101)以及设置在衬底基板(101)上的驱动电路层。驱动电路层包括：构成多个单元行和多个单元列的多个电路单元、多条数据信号线(60)和多条数据连接线(70)。数据连接线(70)包括：沿第一方向延伸的第一连接线(71)和沿第二方向延伸的第二连接线(72)。第一连接线(71)分别与第二连接线(72)和数据信号线(60)电连接。第一连接线(60)和第二连接线(70)位于不同的导电层。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diodes)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(TFT，Thin Film Transistor)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：显示区域和位于所述显示区域一侧的绑定区域。所述显示区域包括：衬底基板以及设置在所述衬底基板上的驱动电路层。所述驱动电路层包括：构成多个单元行和多个单元列的多个电路单元、多条数据信号线和多条数据连接线。所述多条数据信号线中的至少一条数据信号线与一个单元列电连接。所述多条数据连接线中的至少一条数据连接线包括：沿第一方向延伸的第一连接线和沿第二方向延伸的第二连接线，所述第二连接线向所述绑定区域延伸，所述第一方向和所述第二方向交叉。所述第一连接线分别与所述第二连接线和所述数据信号线电连接；所述第一连接线和所述第二连接线位于不同的导电层。
在一些示例性实施方式中，至少一条第一连接线的第一端与所述数据信号线电连接，第二端与所述第二连接线电连接。
在一些示例性实施方式中，至少一条第一连接线沿所述第一方向贯通所述显示区域。
在一些示例性实施方式中，至少一条第二连接线沿所述第二方向贯通所述显示区域。
在一些示例性实施方式中，在垂直于显示基板的方向上，所述第一连接线位于所述第二连接线远离所述衬底基板的一侧。
在一些示例性实施方式中，所述显示区域还包括：沿所述第一方向延伸的多条第一补偿走线、沿所述第二方向延伸的多条第二补偿走线；所述多条第二补偿走线中的至少一条第二补偿走线与所述多条第一补偿走线中的至少一条第一补偿走线电连接。
在一些示例性实施方式中，显示基板还包括：位于所述显示区域其它侧的边框区域，所述边框区域设置有边框电源引线，所述边框电源引线与所述显示区域的多条第一补偿走线和多条第二补偿走线电连接。
在一些示例性实施方式中，所述第一补偿走线和所述第一连接线同层设置，至少一个电路单元包括第一断口，所述第一断口设置在所述第一补偿走线和所述第一连接线之间。
在一些示例性实施方式中，所述第一断口在所述衬底基板的正投影被所述第一连接线所在膜层以外的导电膜层在衬底基板的正投影覆盖。
在一些示例性实施方式中，所述第二补偿走线和所述第二连接线同层设置，至少一个电路单元包括第二断口，所述第二断口设置在所述第二补偿走线和所述第二连接线之间。
在一些示例性实施方式中，所述第二断口在所述衬底基板的正投影被所述第二连接线所在膜层以外的导电膜层在衬底基板的正投影覆盖。
在一些示例性实施方式中，至少一个电路单元包括：虚设电极；所述虚设电极通过过孔与数据信号线或第二连接线电连接，所述虚设电极在所述衬底基板的正投影与所述数据信号线或第二连接线在所述衬底基板的正投影至少部分交叠。
在一些示例性实施方式中，至少一个电路单元包括：虚设电极和第一数 据连接电极；所述第一数据连接电极与所述第一连接线电连接，所述虚设电极通过过孔与所述第一数据连接电极电连接，所述虚设电极在所述衬底基板的正投影与所述第一数据连接电极在所述衬底基板的正投影至少部分交叠。
在一些示例性实施方式中，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个晶体管。在垂直于显示基板的方向上，所述驱动电路层包括：在所述衬底基板上设置的半导体层、第一导电层、第二导电层和第三导电层；所述半导体层至少包括所述多个晶体管的有源层，所述第一导电层至少包括所述多个晶体管的栅极和所述存储电容的第一极板，所述第二导电层至少包括所述存储电容的第二极板，所述第三导电层至少包括多个连接电极。
在一些示例性实施方式中，所述第二导电层还包括：所述第一连接线，所述第三导电层还包括：所述第二连接线和所述数据信号线。
在一些示例性实施方式中，所述驱动电路层还包括：位于所述第三导电层远离所述衬底基板一侧的第四导电层；所述第四导电层包括：所述数据信号线和所述第二连接线；所述第三导电层还包括：所述第一连接线。
在一些示例性实施方式中，所述驱动电路层还包括：位于所述第三导电层远离所述衬底基板一侧的第四导电层、以及位于所述第四导电层远离所述衬底基板一侧的第五导电层；所述第四导电层包括：所述数据信号线和所述第二连接线；所述第五导电层包括：所述第一连接线。
在一些示例性实施方式中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述数据信号线包括第一数据信号线组和第二数据信号线组，所述第一数据信号线组中的数据信号线通过所述数据连接线与所述引出线电连接，所述第二数据信号线组中的数据信号线直接与所述引出线电连接。
在一些示例性实施方式中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述多条数据信号线通过所述多条数据连接线与所述多条引出线电连接。
在一些示例性实施方式中，相邻两条数据信号线之间设置有至少两条第二连接线。
在一些示例性实施方式中，至少一个单元列包括多个无效像素驱动电路，至少一条第二连接线在所述衬底基板的正投影与所述单元列的无效像素驱动电路在所述衬底基板的正投影存在交叠。
另一方面，本实施例提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板的显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为本公开至少一实施例的显示基板的平面结构示意图；
图7A为本公开至少一实施例的显示基板的另一平面结构示意图；
图7B为图7A中区域C1的局部放大示意图；
图8为本公开至少一实施例的补偿走线的平面结构示意图；
图9A为图7A中区域C1形成半导体层后的显示基板的局部放大示意图；
图9B为图7A中区域C1形成第一导电层后的显示基板的局部放大示意图；
图9C为图7A中区域C1形成第二导电层后的显示基板的局部放大示意图；
图9D为图7A中区域C1形成第三绝缘层后的显示基板的局部放大示意图；
图9E为图7A中区域C1形成第三导电层后的显示基板的局部放大示意图；
图9F为图7A中区域C1形成第四绝缘层后的显示基板的局部放大示意图；
图9G为图7A中区域C1形成第四导电层后的显示基板的局部放大示意图；
图9H为图7A中区域C1的第三导电层和第四导电层的局部放大示意图；
图9I为图9G中沿Q-Q’的剖面示意图；
图10A为图7A中区域C2形成第三导电层后的显示基板的局部放大示意图；
图10B为图7A中区域C2形成第四绝缘层后的显示基板的局部放大示意图；
图10C为图7A中区域C2形成第四导电层后的显示基板的局部放大示意图；
图11A为图7A中区域C1形成第四导电层后的显示基板的另一局部放大示意图；
图11B为图7A中区域C1形成第五绝缘层后的显示基板的另一局部放大示意图；
图11C为图7A中区域C1形成第五导电层后的显示基板的另一局部放大示意图；
图11D为图7A中区域C1的第四导电层和第五导电层的局部放大示意图；
图11E为图11C中沿U-U’方向的剖面示意图；
图12A为图7A中区域C1形成第二导电层后的显示基板的另一局部放大示意图；
图12B为图7A中区域C1形成第三绝缘层后的显示基板的另一局部放大示意图；
图12C为图7A中区域C1形成第三导电层后的显示基板的另一局部放大示意图；
图12D为图7A中区域C1的第二导电层和第三导电层的局部放大示意图；
图12E为图12C中沿R-R’方向的剖面示意图；
图13为本公开至少一实施例的显示基板的另一平面结构示意图；
图14为图13中区域C3的驱动电路层的局部放大示意图；
图15为本公开至少一实施例的显示基板的另一平面结构示意图；
图16为本公开至少一实施例的电路单元的排布示意图；
图17为本公开至少一实施例的显示基板的另一平面结构示意图；
图18A为图17中区域C4形成第三导电层后的显示基板的局部放大示意图；
图18B为图17中区域C4形成第四导电层后的显示基板的局部放大示意图；
图18C为图18B中第三导电层和第四导电层的示意图；
图19为本公开至少一实施例的显示基板的另一平面结构示意图；
图20为本公开至少一实施例的显示基板的另一平面结构示意图；
图21为本公开至少一实施例的显示基板的另一平面结构示意图；
图22为本公开至少一实施例的补偿走线的平面结构视图；
图23A为图21中区域C5形成第三导电层后的显示基板的局部放大示意图；
图23B为图21中区域C5形成第四导电层后的显示基板的局部放大示意图；
图23C为图21中区域C5形成第五绝缘层后的显示基板的局部放大示意图；
图23D为图21中区域C5形成第五导电层后的显示基板的局部放大示意 图；
图23E为图21中区域C5的第三导电层、第四导电层和第五导电层的局部放大示意图；
图24为本公开至少一实施例的显示基板的外观效果的示意图；
图25A为图21中区域C5形成第三导电层后的显示基板的另一局部放大示意图；
图25B为图21中区域C5形成第四导电层后的显示基板的另一局部放大示意图；
图25C为图21中区域C5的第三导电层和第四导电层的局部放大示意图；
图26A为图21中区域C5形成第二导电层后的显示基板的另一局部放大示意图；
图26B为图21中区域C5形成第三导电层后的显示基板的另一局部放大示意图；
图26C为图21中区域C5的第二导电层和第三导电层的局部放大示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多 个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂 直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”是指数值相差10％以内的情况。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括：时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列。时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接。数据驱动器分别与多个数据信号线(例如，D1到Dn)连接，扫描驱动器分别与多个扫描信号线(例如，S1到Sm)连接，发光驱动器分别与多个发光控制线(例如，E1到Eo)连接。其中，n、m和o可以是自然数。像素阵列可以包括多个子像素Pxij，i和j可以是自然数。至少一个子像素Pxij可以包括：电路单元和与电路单元连接的发光元件。电路单元可以至少包括像素驱动电路，像素驱动电路可以分别与扫描信号线、发光控制线和数据信号线连接。
在一些示例性实施例中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输 到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光控制线E1、E2、E3、……和Eo的发光控制信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光控制线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发光控制信号。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在一些示例中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij可以被配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在一些示例中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例性实施例中，绑定区域200可以包括沿着远离显示区域100的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。扇出区连接到显示区域100，至少包括数据扇出线，多条数据扇出线被配置为以扇出走线方式连接显示区域100的数据信号线。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使驱动芯片区和绑定引脚区弯折到显示区域100的背面。驱动芯片区可以设置集成电路(IC，Integrated Circuit)，集成电路可以被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，绑定焊盘可以被配置为与外部的柔性线路板(FPC，Flexible Printed Circuit)绑定连接。
在一些示例性实施例中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路所连接的第一扫描线、第二扫描线和发光控制线连接。电源线区连接到电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝 坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在一些示例性实施例中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构。显示区域边缘是显示区域100靠近绑定区域200或者边框区域300一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P。至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光元件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光控制线连接，像素驱动电路可以被配置为在扫描信号线和发光控制线的控制下，接收数据信号线传输的数据电压，向发光元件输出相应的电流。每个子像素中的发光元件分别与所在子像素的像素驱动电路连接，发光元件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在一些示例性实施例中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在一些示例中，子像素的发光元件的形状可以是矩形状、菱形、五边形或六边形，四个子像素的发光元件可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施例中，四个子像素的发光元件可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在另一些示例性实施例中，像素单元可以包括三个子像素，三个子像素的发光元件可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板的显示区域的剖面结构示意图。图4示意了显示区域100中三个子像素的结构。如图4所示，在垂直于显示基板的方向上，显 示基板可以包括：衬底基板101、依次设置在衬底基板101上的驱动电路层102、发光结构层103以及封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在一些示例性实施例中，衬底基板101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括由多个晶体管和存储电容构成的像素驱动电路。每个子像素的发光结构层103可以至少包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301与像素驱动电路连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在一些示例性实施例中，有机发光层303可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在一些示例中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是各自连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在一些示例性实施例中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。本示例性实施例的像素电路以7T1C结构为例进行说明。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5所示，本示例的像素驱动电路可以包括七个晶体管(即第一晶体管T1至第七晶体管T7)和一个存储电容Cst。像素驱动电路分别与九个信号线(例如包括：数据信号线DL、第一扫描信号线GL、第二扫描信号线RST1、第三扫描信号线RST2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD和第二电 源线VSS)连接。
在一些示例性实施方式中，像素驱动电路的七个晶体管可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。在一些可能的实现方式中，像素驱动电路的七个晶体管可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，像素驱动电路的七个晶体管可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，即LTPS+Oxide(简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，第一电源线VDD可以配置为向像素驱动电路提供恒定的第一电压信号，第二电源线VSS可以配置为向像素驱动电路提供恒定的第二电压信号，并且第一电压信大于第二电压信号。第一扫描信号线GL可以配置为向像素驱动电路提供第一扫描信号SCAN，数据信号线DL可以配置为向像素驱动电路提供数据信号DATA，发光控制线EML可以配置为向像素驱动电路提供发光控制信号EM。在一些示例中，在第n行像素驱动电路中，第二扫描信号线RST1可以与第n-1行像素驱动电路的第一扫描信号线GL电连接，以被输入第一扫描信号SCAN(n-1)。第n行像素驱动电路的第三扫描信号线RST2可以与第n行像素驱动电路的第一扫描信号线GL电连接，以被输入第一扫描信号SCAN(n)。在一些示例中，第n行像素驱动电路所电连接的第三扫描信号线RST2与第n+1行像素驱动电路所电连接的第二扫描信号线RST1可以为一体结构。其中，n为大于0的整数。如此，可以减少显示基板的信号线，实现显示基板的窄边框设计。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一初始信号线INIT1可以配置为向像素驱 动电路提供第一初始信号，第二初始信号线INIT2可以配置为向像素驱动电路提供第二初始信号。例如，第一初始信号可以不同于第二初始信号。第一初始信号和第二初始信号可以为恒压信号，其大小例如可以介于第一电源线VDD提供的第一电压信号和第二电源线VSS提供的第二电压信号之间，但不限于此。在另一些示例中，第一初始信号与第二初始信号可以相同，可以仅设置第一初始信号线来提供第一初始信号。
在一些示例性实施方式中，如图5所示，第一晶体管T1的栅极与第二扫描信号线RST1电连接，第一晶体管T1的第一极与第一初始信号线INIT1电连接，第一晶体管T1的第二极与第三晶体管T3的栅极电连接。第二晶体管T2的栅极与第一扫描信号线GL电连接，第二晶体管T2的第一极与第三晶体管T3的栅极电连接，第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第三晶体管T3的栅极与第一节点N1电连接，第一极与第二节点N2电连接，第二极与第三节点N3电连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。第四晶体管T4的栅极与第一扫描线GL电连接，第四晶体管T4的第一极与数据信号线DL电连接，第四晶体管T4的第二极与第三晶体管T3的第一极电连接。第五晶体管T5的栅极与发光控制线EML电连接，第五晶体管T5的第一极与第一电源线VDD电连接，第五晶体管T5的第二极与第三晶体管T3的第一极电连接。第六晶体管T6的栅极与发光控制线EML电连接，第六晶体管T6的第一极与第三晶体管T3的第二极电连接，第六晶体管T6的第二极与发光元件EL的阳极电连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。第七晶体管T7的栅极与第三扫描信号线RST2电连接，第七晶体管T7的第一极与第二初始信号线INIT2电连接，第七晶体管T7的第二极与发光元件EL的阳极电连接。存储电容Cst的第一极板与第三晶体管T3的栅极电连接，存储电容Cst的第二极板与第一电源线VDD电连接。
在本示例中，第一节点N1为存储电容Cst、第一晶体管T1、第三晶体管T3和第二晶体管T2的连接点，第二节点N2为第五晶体管T5、第四晶体管T4和第三晶体管T3的连接点，第三节点N3为第三晶体管T3、第二晶体 管T2和第六晶体管T6的连接点，第四节点N4为第六晶体管T6、第七晶体管T7和发光元件EL的连接点。
在一些示例性实施例中，发光元件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。发光元件的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在一些示例性实施方式中，以像素驱动电路包括的第一晶体管T1至第七晶体管T7均为P型晶体管为例，像素驱动电路的工作过程可以包括以下阶段。
第一阶段A1，称为复位阶段。第二扫描信号线RST1提供的低电平信号，使第一晶体管T1导通，第一初始信号线INIT1提供的第一初始信号被提供至第一节点N1，对第一节点N1进行初始化，清除存储电容Cst中原有数据电压。第一扫描信号线GL提供高电平信号，发光控制线EML提供高电平信号，使第四晶体管T4、第二晶体管T2、第五晶体管T5、第六晶体管T6以及第七晶体管T7断开。此阶段发光元件EL不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。第一扫描信号线GL提供低电平信号，第二扫描信号线RST1和发光控制线EML均提供高电平信号，数据信号线DL输出数据信号DATA。此阶段由于存储电容Cst的第一极板为低电平，因此第三晶体管T3导通。第一扫描信号线GL提供低电平信号，使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通，使得数据信号线DL输出的数据电压Vdata经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据信号线DL输出的数据电压Vdata与第三晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一极板(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据信号线DL输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号提供至发光元件EL的阳极，对发光元件EL的阳极进行初始化(复位)，清空其内部的预存电压，完成初始 化，确保发光元件EL不发光。第二扫描信号线RST1提供高电平信号，使第一晶体管T1断开。发光控制线EML提供高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3，称为发光阶段。发光控制线EML提供低电平信号，第一扫描信号线GL和第二扫描信号线RST1均提供高电平信号。发光控制线EML提供低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的第一电压信号通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素驱动电路的驱动过程中，流过第三晶体管T3(即驱动晶体管)的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K×(Vgs-Vth) 2＝K×[(Vdd-Vdata+|Vth|)-Vth] 2＝K×[Vdd-Vdata] 2。
其中，I为流过第三晶体管T3的驱动电流，也就是驱动发光元件EL的驱动电流，K为常数，Vgs为第三晶体管T3的栅极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线DL输出的数据电压，Vdd为第一电源线VDD输出的第一电压信号。
由上式中可以看到流经发光元件EL的电流与第三晶体管T3的阈值电压无关。本实施例的像素驱动电路可以较好地补偿第三晶体管T3的阈值电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，绑定区域通常包括沿着远离显示区域的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。由于绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出(Fanout)走线方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，因而扇形区占用空间较大，导致下边框的窄化设计难度较大，下边框一直维持在2.0毫米(mm)左右。
本公开实施例提供一种显示基板，包括：显示区域和位于显示区域一侧的绑定区域。显示区域包括：构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、以及多条数据连接线。多条数据信号线中的至少一条数据信号线与一个单元列电连接。至少一条数据连接线包括：沿第一方向延伸的第一连接线和沿第二方向延伸的第二连接线。第一方向与第二方向交叉。第一连接线分别与第二连接线和数据信号线电连接。第一连接线和第二连接线位于不同的导电层。在一些示例中，第一连接线在衬底基板的正投影可以与一个单元行在衬底基板的正投影存在交叠，第二连接线在衬底基板的正投影可以与一个单元列在衬底基板的正投影存在交叠。
在本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在一些示例中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
本实施例提供的显示基板，通过在显示区域内设置数据连接线，可以使得绑定区域的引出线通过数据连接线与数据信号线电连接，使得绑定区域中不需要设置扇形状的斜线，有效减小了绑定区域的引线区的长度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。而且，本实施例的显示基板中，通过将数据连接线的沿两个不同方向延伸的第一连接线和第二连接线设置在不同的导电层，可以避免数据连接线在同一个导电层密集设置，使得显示区域的不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
在一些示例性实施方式中，至少一条第一连接线的第一端可以与数据信号线电连接，第二端可以与第二连接线电连接。在本示例中，第一连接线沿第一方向的长度可以根据所电连接的数据信号线和第二连接线在第一方向的间距来确定。在一些示例中，第二连接线沿第二方向的长度可以根据显示区域和绑定区域的边界与所述第二连接线所电连接的第一连接线之间的距离来 确定。
在一些示例性实施方式中，至少一条第一连接线可以沿第一方向贯通显示区域。在本示例中，第一连接线的两个端部分别延伸至显示区域与两侧边框区域的边界，由第一连接线的中间部分与数据信号线和第二连接线电连接。在一些示例中，多条第一连接线沿第一方向的长度可以大致相同。本示例通过设置长度大致相同的第一连接线可以保证显示区域的不同区域的走线均一性。
在一些示例性实施方式中，至少一条第二连接线可以沿第二方向贯通显示区域。在本示例中，第二连接线的两个端部可以分别延伸至显示区域与上侧边框区域的边界以及显示区域与绑定区域的边界。在一些示例中，多条第二连接线沿第二方向的长度可以大致相同。本示例通过设置长度大致相同的第二连接线可以保证显示区域的不同区域的走线均一性。
图6为本公开至少一实施例的显示基板的平面结构示意图。在垂直于显示基板的平面内，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。如图6所示，在平行于显示基板的平面内，显示基板可以至少包括：显示区域100、沿第二方向Y位于显示区域100一侧的绑定区域200、以及位于显示区域100其它侧的边框区域300。在一些示例中，显示区域100的驱动电路层可以包括：构成多个单元行和多个单元列的多个电路单元、多条数据信号线60、多条数据连接线70。至少一个电路单元可以包括：像素驱动电路，像素驱动电路可以被配置为向所连接的发光元件输出相应的电流。显示区域100的发光结构层可以包括多个发光元件，发光元件与对应电路单元的像素驱动电路连接，发光元件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。在一些示例中，电路单元可以是按照像素驱动电路划分的区域。发光元件在衬底基板的正投影的位置与电路单元在衬底基板的正投影可以是对应的，或者，发光元件在衬底基板的正投影的位置与电路单元在衬底基板的正投影的位置可以是不对应的。
在一些示例中，至少一条数据信号线60与一个单元列中的多个像素驱动电路连接，数据信号线60可以被配置为向所连接的像素驱动电路提供数据信 号。至少一条数据连接线70与数据信号线60对应连接，数据连接线70可以被配置为使数据信号线60通过数据连接线70与绑定区域200中的引出线80对应连接。
在一些示例中，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。例如，第二方向Y可以是数据信号线60的延伸方向(例如，竖直方向)，第一方向X可以与第二方向Y垂直(例如，水平方向)。
在一些示例中，如图6所示，绑定区域200可以包括：沿着远离显示区域方向依次设置的引线区201、弯折区、驱动芯片区和绑定引脚区。引线区201连接到显示区域100，弯折区连接到引线区201。引线区201可以设置多条引出线80，多条引出线80可以沿着远离显示区域100的第二方向Y延伸，一部分引出线80的第一端与显示区域100中的数据连接线70对应连接，另一部分引出线的第一端与显示区域100中的数据信号线60对应连接，所有引出线80的第二端跨过弯折区连接复合电路区的集成电路，使得集成电路通过引出线80和数据连接线70将数据信号施加到数据信号线60。由于数据连接线70设置在显示区域100，因而可以有效减小引线区201在第二方向Y的长度，大大缩减下边框宽度，提高了屏占比，有利于实现全面屏显示。
在一些示例中，显示区域100的多条数据信号线60可以沿着第二方向Y延伸，并按照编号递增的方式沿着第一方向X以设定的间隔顺序设置。多条数据信号线60可以按照是否与数据连接线连接划分为第一数据信号线组和第二数据信号线组，第一数据信号线组中的多条数据信号线60与数据连接线70对应连接，第二数据信号线组中的多条数据信号线60不与数据连接线70连接。引线区201的多条引出线80可以按照是与数据连接线70连接还是与数据信号线60连接划分为第一引出线组和第二引出线组，第一引出线组中的多条引出线80与数据连接线70对应连接，第二引出线组中的多条引出线80与数据信号线60对应连接。在一些示例中，引出线80与数据信号线60、引出线80与数据连接线70可以直接连接，或者可以通过过孔连接，本公开在此不做限定。
在一些示例中，如图6所示，显示区域100的数据连接线70可以包括第一连接线71和第二连接线72。第一连接线71和第二连接线72相互连接。第一连接线71可以沿第一方向X延伸，第二连接线72可以沿第二方向Y延伸。第一连接线71的第一端可以与第一数据信号线组的数据信号线60对应连接，第一连接线71的第二端可以沿着第一方向X或者第一方向X的反方向延伸后，与第二连接线72的第一端连接，第二连接线72的第二端可以向着绑定区域200的方向延伸并跨过显示区域边界B，与引线区201中第一引出线组的引出线80对应连接，使得显示区域100中第一数据信号线组的数据信号线60可以通过数据连接线70与引出线80间接连接。第二数据信号线组的多条数据信号线60可以向着绑定区域200的方向延伸并跨过显示区域边界B，与引线区201中第二引出线组的多条引出线80对应连接，使得显示区域100中第二数据信号线组的多条数据信号线60与引出线80直接连接。在本示例中，显示区域边界B可以是显示区域100和绑定区域200的交界处。
在一些示例中，第一连接线71和第二连接线72可以设置在不同的导电层中，第一连接线71和数据信号线60可以设置在不同的导电层中。例如，第一连接线71的第一端可以通过第一连接孔K1与数据信号线60连接，第一连接线71的第二端可以沿着第一方向X或者第一方向X的反方向延伸后，通过第二连接孔K2与第二连接线72的第一端连接，第二连接线72的第二端可以沿着第二方向Y向着引线区201的方向延伸后与引出线80连接。
在一些示例中，在第一方向X上相邻的两条第二连接线72之间可以设置至少一条数据信号线60。例如，相邻第二连接线72之间可以设置一条数据信号线。又如，相邻第二连接线72之间可以设置两条数据信号线。
在一些示例中，多条第二连接线72可以设置成与数据信号线60平行，多条第一连接线71可以设置成与数据信号线60垂直。
在一些示例中，相邻第二连接线72之间的间距可以大致相同，相邻第一连接线71之间的间距可以大致相同，本公开在此不做限定。
在一些示例中，显示区域100可以具有中心线O，显示区域100中的多条数据信号线60、多条数据连接线70和引线区201中的多条引出线80可以相对于中心线O对称设置，中心线O可以为平分显示区域100的多个单元列 并沿着第二方向Y延伸的直线。如图6所示，以位于中心线O左侧的第一数据信号线组中的多条数据信号线60、多条数据连接线70为例，第一数据信号线组中远离中心线O的数据信号线60所连接的第二连接线72，可以位于靠近中心线O的数据信号线60所连接的第二连接线72靠近中心线O的一侧。在本示例中，多条第二连接线72沿第二方向Y的长度可以在第一方向X上沿着靠近中心线O的方向逐渐增加。第一数据信号线组中远离中心线O的数据信号线60所连接的第一连接线71，可以位于靠近中心线O的数据信号线60所连接的第一连接线71远离绑定区域200的一侧。在本示例中，多条第一连接线71沿第一方向X的长度可以在第二方向Y上逐渐减小。本示例性实施例不仅可以方便数据连接线的布局和负载无突变，而且可以通过在相邻的第二连接线之间设置一条数据信号线，可以进一步压缩数据连接线的占用空间，可以最小化数据信号负载差异。然而，本实施例对此并不限定。例如，第一数据信号线组中远离中心线O的数据信号线所连接的第二连接线，可以位于靠近中心线O的数据信号线所连接的第二连接线远离中心线O的一侧。又如，第一数据信号线组中远离中心线O的数据信号线所连接的第一连接线，可以位于靠近中心线O的数据信号线所连接的第一连接线靠近绑定区域200的一侧。
图7A为本公开至少一实施例的显示基板的另一平面结构示意图。图7B为图7A中区域C1的局部放大示意图。显示区域100的驱动电路层可以包括：组成电路单元阵列的多个电路单元、多条数据信号线60、多条数据连接线70和补偿走线90。多个电路单元、多条数据信号线60和多条数据连接线70的布局和结构与前述图6所示布局和结构大致相同。
在一些示例中，如图7A和图7B所示，补偿走线90可以包括多条沿第一方向X延伸的第一补偿走线91和多条沿第二方向Y延伸的第二补偿走线92。多条第一补偿走线91可以沿着第二方向Y依次设置，多条第二补偿走线92可以沿着第一方向X依次设置。第一补偿走线91和第二补偿走线92可以设置在不同的导电层中。第二补偿走线92可以设置在相邻的数据信号线60之间。多条第一补偿走线91和多条第二补偿走线92在衬底基板的正投影可以交叉，从而构成网状结构。在一些示例中，至少一条第二补偿走线92 可以通过第三连接孔K3与至少一条第一补偿走线91电连接，使得多条第一补偿走线91和多条第二补偿走线92可以构成网状连通结构。
在一些示例中，第一补偿走线91和第一连接线71可以同层设置，且通过同一次图案化工艺同步形成。第二补偿走线92和第二连接线72可以同层设置，且通过同一次图案化工艺同步形成。在本示例中，通过设置补偿走线90可以对数据连接线70提供外观补偿效果，使得显示区域的不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
在一些示例中，至少一个单元行中可以仅设置有第一补偿走线91，且该单元行中没有设置第一连接线71。至少一个单元行中可以设置有至少一条第一补偿走线91和至少一条第一连接线71。例如，至少一个单元行中的第一补偿走线91和第一连接线71可以在第一方向X上对齐，该单元行的一个电路单元可以包括第一断口DF1，第一断口DF1可以设置在第一补偿走线91和第一连接线71之间。第一断口DF1可以配置为实现第一补偿走线91和第一连接线71之间没有电连接关系。
在一些示例中，至少一个单元列中可以仅设置第二补偿走线92，且该单元列中没有设置第二连接线72。至少一个单元列中可以设置有至少一条第二补偿走线92和至少一条第二连接线72。例如，至少一个单元列中的第二补偿走线92和第二连接线72可以在第二方向Y上对齐，该单元列的一个电路单元可以包括第二断口DF2，第二断口DF2可以设置在第二补偿走线92和第二连接线72之间。第二断口DF2可以配置为实现第二补偿走线92和第二连接线72之间没有电连接关系。
在一些示例中，第一补偿走线91和第二补偿走线91可以与第二电源线电连接，以持续接收低电平信号。
图8为本公开至少一实施例的补偿走线的平面结构示意图。在一些示例中，如图8所示，第二电源线可以包括位于绑定区域200的绑定电源引线410、以及位于边框区域300的边框电源引线510。绑定区域200的绑定电源引线410和边框区域300的边框电源引线510可以为相互连接的一体结构。在一些示例中，至少一条第一补偿走线91在第一方向X的一端或两端可以与边 框电源引线510连接。至少一条第二补偿走线92在第二方向Y的反方向的一端可以与边框电源引线510连接。在一些示例中，至少一条第二补偿走线92在第二方向Y的一端可以与边框电源引线510连接。在另一些示例中，至少一条第二补偿走线92在第二方向Y的一端可以与绑定电源引线410连接，在第二方向Y的反方向的一端可以与边框电源引线510连接。然而，本实施例对此并不限定。
在一些示例中，第一补偿走线91和第二补偿走线92可以设置在不同的导电层中。如图7B所示，至少一条第二补偿走线92可以通过第三连接孔K3与至少一条第一补偿走线91电连接，使得多条第二补偿走线92和多条第一补偿走线91可以具有相同的电位。在本示例中，通过在显示区域内设置与第二电源线电连接的补偿走线，不仅可以有效降低第二电源走线的电阻，有效降低低电压电源信号的压降，实现低功耗，而且可以有效提升显示基板中电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在一些示例中，如图7A所示，由于数据连接线70设置在显示区域100中的部分区域，且数据连接线70包括沿第一方向X延伸的第一连接线71和沿第二方向Y延伸的第二连接线72，因而可以按照有无数据连接线以及数据连接线的延伸方向作为划分依据，将显示区域100划分为第一区域110、第二区域120和第三区域130。其中，第一区域110可以是设置有第一连接线71的区域(扇出线横向走线区域)，第二区域120可以是设置有第二连接线72的区域(扇出线纵向走线区域)，第三区域130可以是没有设置第一连接线71和第二连接线72的区域(正常区域)。在一些示例中，第一补偿走线91和第二补偿走线92可以设置在第三区域130。
在一些示例中，第一区域110可以包括多个电路单元，第一连接线71在显示基板平面上的正投影与第一区域110的多个电路单元中像素驱动电路在显示基板平面上的正投影可以至少部分交叠。第二区域120可以包括多个电路单元，第二连接线72在显示基板平面上的正投影与第二区域120的多个电路单元中像素驱动电路在显示基板平面上的正投影可以至少部分交叠。第三区域130可以包括多个电路单元，第三区域130的多个电路单元中像素驱动电路在显示基板平面上的正投影与第一连接线71和第二连接线72在显示 基板平面上的正投影可以均没有重叠。
在一些示例中，图7A所示多个区域的划分仅仅是一种示例性说明。由于第一区域110、第二区域120和第三区域130是按照有无数据连接线和数据连接线的延伸方向作为划分依据，因而三个区域的形状可以是规则的多边形，或者是不规则的多边形，显示区域100可以划分出一个或多个第一区域110、一个或多个第二区域120以及一个或多个第三区域130，本公开在此并不限定。
在一些示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括：衬底基板、依次设置在衬底基板上的驱动电路层、发光结构层和封装结构层。驱动电路层可以包括在衬底基板上依次设置的第一导电层、第二导电层、第三导电层和第四导电层。在一些示例中，第三导电层至少包括第一连接线，第四导电层至少包括数据信号线和第二连接线。数据信号线可以通过第一连接孔与第一连接线的第一端连接，第二连接线可以通过第二连接孔与第一连接线的第二端连接。
在一些示例性实施方式中，驱动电路层还可以至少包括第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。第一绝缘层可以设置在半导体层和第一导电层之间，第二绝缘层可以设置在第一导电层与第二导电层之间，第三绝缘层可以设置在第二导电层与第三导电层之间，第四绝缘层可以设置在第三导电层与第四导电层之间。
下面参照图9A至图10C通过显示基板的制备过程进行示例性说明。其中，图9A为图7A中区域C1形成半导体层后的显示基板的局部放大示意图。图9B为图7A中区域C1形成第一导电层后的显示基板的局部放大示意图。图9C为图7A中区域C1形成第二导电层后的显示基板的局部放大示意图。图9D为图7A中区域C1形成第三绝缘层后的显示基板的局部放大示意图。图9E为图7A中区域C1形成第三导电层后的显示基板的局部放大示意图。图9F为图7A中区域C1形成第四绝缘层后的显示基板的局部放大示意图。图9G为图7A中区域C1形成第四导电层后的显示基板的局部放大示意图。图9H为图7A中区域C1的第三导电层和第四导电层的局部放大示意图。图9I为图9G中沿Q-Q’的剖面示意图。图9A至图9H中以区域C1中两个单元 行(例如第M-1行和第M行)和四个单元列(例如，第N-1列至第N+2列)的电路单元为例进行示意。图10A为图7A中区域C2形成第三导电层后的显示基板的局部放大示意图。图10B为图7A中区域C2形成第四绝缘层后的显示基板的局部放大示意图。图10C为图7A中区域C2形成第四导电层后的显示基板的局部放大示意图。图10A至图10C中以区域C2中两个单元行和两个单元列(例如，第1列至第4列)的电路单元为例进行示意。
本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)、形成半导体层图案。在一些示例性实施方式中，在衬底基板上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成设置在衬底基板上的半导体层，如图9A所示。在一些示例中，显示区域100中每个电路单元的半导体层可以至少包括：第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17。第一有源层11至第七有源层17可以为相互连接的一体结构。第一有源层11、第二有源层12、第四有源层14可以位于本电路单元的第三有源层13的第二方向Y的一侧，第五有源层15、第六有源层 16和第七有源层17可以位于本电路单元的第三有源层13的第二方向Y的另一侧。
在一些示例中，如图9A所示，第一有源层11的形状可以呈“n”字形，第二有源层12和第五有源层15的形状可以呈“L”字形，第三有源层13的形状可以呈“Ω”字形，第四有源层14、第六有源层16和第七有源层17的形状可以呈“I”字形。然而，本实施例对此并不限定。
在一些示例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在一些示例中，第一有源层11的第一区11-1、第四有源层14的第一区14-1、第五有源层15的第一区15-1和第七有源层17的第一区17-1可以单独设置，第一有源层11的第二区11-2可以作为第二有源层12的第一区12-1，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2可以同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2可以作为第七有源层17的第二区17-2。
在一些示例中，绑定区域的引线区可以没有设置半导体层。
(2)、形成第一导电层。在一些示例性实施方式中，在形成前述图案的衬底基板上，依次沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层的第一绝缘层111，以及设置在第一绝缘层111上的第一导电层，如图9B所示。在一些示例中，第一导电层可以称为第一栅金属(GATE1)层。
在一些示例中，如图9B所示，显示区域中每个电路单元的第一导电层至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线24和存储电容的第一极板25。其中，一个单元行的像素驱动电路电连接的第三扫描信号线23即为下一个单元行的像素驱动电路电连接的第二扫描信号线22。
在一些示例中，存储电容的第一极板25的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板25在衬底基板上的正投影与第三晶体管T3的第三有源层13在衬底基板上的正投影存在重叠区域。在本示例中，第一极板25可以同时作为存储电容的一个极板和第三晶体管T3的栅极。
在一些示例中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23和发光控制线24的形状可以为主体部分沿着第一方向X延伸的线形状。第一扫描信号线21和第二扫描信号线22可以位于本电路单元的第一极板25在第二方向Y的反方向的一侧，第二扫描信号线22可以位于本电路单元的第一扫描信号线21远离第一极板25的一侧，第三扫描信号线23和发光控制线24可以位于本电路单元的第一极板25第二方向Y的一侧，第三扫描信号线23可以位于本电路单元的发光控制线24远离第一极板25的一侧。
在一些示例中，第一扫描信号线21可以设置有向第二扫描信号线22一侧凸起的栅极块21-1，第一扫描信号线21和栅极块21-1与第二有源层12相重叠的区域可以作为第二晶体管T2的栅极，形成双栅结构的第二晶体管T2。第一扫描信号线21与第四有源层14相重叠的区域可以作为第四晶体管T4的栅极。第二扫描信号线22与第一有源层11相重叠的区域可以作为双栅结构的第一晶体管T1的栅极。第三扫描信号线23与第七有源层17相重叠的区域可以作为第七晶体管T7的栅极。发光控制线24与第五有源层15相重叠的区域可以作为第五晶体管T5的栅极，发光控制线24与第六有源层16相重叠的区域可以作为第六晶体管T6的栅极。
在一些示例中，第一扫描信号线21和第三扫描信号线23可以连接相同的信号源，即第一扫描信号线21和第三扫描信号线23的输出信号相同。
在一些示例中，形成第一导电层后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层11至第七有源层17的第一区和第二区均被导体化。
(3)、形成第二导电层。在一些示例性实施方式中，在形成前述图案的衬底基板上，依次沉积第二绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第二绝缘层112，以及设置在第二绝缘层上的第二导电层，如图9C所示。在一些示例中，第二导电层可以称为第二栅金属(GATE2)层。
在一些示例中，如图9C所示，显示区域中每个电路单元的第二导电层至少包括：第一初始信号线31、第二初始信号线32、存储电容Cst的第二极 板33、极板连接线34和屏蔽电极35。
在一些示例中，第一初始信号线31和第二初始信号线32的形状可以为主体部分可以沿第一方向X延伸的线形状。第一初始信号线31可以位于本电路单元的第一扫描信号线21和第二扫描信号线22之间，第二初始信号线32可以位于本电路单元的第三扫描信号线23靠近发光控制线24的一侧。
在一些示例中，第二极板33的轮廓形状可以为矩形状，矩形状的角部可以设置倒角，第二极板33在衬底基板上的正投影与第一极板25在衬底基板上的正投影存在重叠区域，第二极板33作为存储电容的另一个极板，位于本电路单元的第一扫描信号线21和发光控制线24之间，第一极板25和第二极板33构成像素驱动电路的存储电容。
在一些示例中，极板连接线34可以设置在第二极板33第一方向X或第一方向X的反方向的一侧，极板连接线34的第一端与本电路单元的第二极板33连接，极板连接线34的第二端沿着第一方向X或者第一方向X的反方向延伸后，与相邻电路单元的第二极板33连接，使一个单元行上相邻电路单元的第二极板33相互连接。在一些示例中，通过极板连接线可以使一个单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号连接线，保证一个单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在一些示例中，第二极板33上设置有开口36，开口36可以位于第二极板33的中部，开口36可以为矩形，使第二极板33形成环形结构。开口36暴露出覆盖第一极板25的第二绝缘层112，且第一极板25在衬底基板上的正投影包含开口36在衬底基板上的正投影。在一些示例中，开口36被配置为容置后续形成的第七过孔，第七过孔可以位于开口36内并暴露出第一极板25，使后续形成的第一晶体管T1的第二极与第一极板25连接。
在一些示例中，屏蔽电极35可以位于第一初始信号线31靠近第一扫描信号线21的一侧，且与第一初始信号线31连接。屏蔽电极35与第一初始信号线31可以为一体结构。屏蔽电极35在衬底基板上的正投影与第二有源层12的第一区12-1在衬底基板上的正投影至少部分交叠。屏蔽电极35可以被 配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
(4)、形成第三绝缘层。在一些示例性实施方式中，在形成前述图案的衬底基板上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层113，如图9D所示。在一些示例中，单个电路单元中可以设置有多个过孔。例如，显示区域中每个电路单元的多个过孔可以至少包括：第一过孔V1至第十过孔V10。其中，第一过孔V1至第六过孔V6内的第三绝缘层113、第二绝缘层112和第一绝缘层111被去掉，暴露出半导体层的表面。第七过孔V7内的第三绝缘层113和第二绝缘层112被去掉，暴露出位于第一导电层的存储电容的第一极板25的表面。第八过孔V8至第十过孔V10内的第三绝缘层113被去掉，暴露出第二导电层的表面。
(5)、形成第三导电层。在一些示例性实施方式中，在形成前述图案的衬底基板上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层113上的第三导电层，如图9E和图10A所示。在一些示例中，第三导电层可以称为第一源漏金属(SD1)层。
在一些示例中，如图9E所示，显示区域中多个电路单元的第三导电层均可以包括：第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45和第六连接电极46。
在一些示例中，第一连接电极41的一端可以通过第一过孔V1与第一有源层11的第一区11-1连接，第一连接电极41的另一端可以通过第八过孔V8与第一初始信号线31连接。第二连接电极42的一端可以通过第二过孔V2与第一有源层11的第二区11-2连接，另一端可以通过第七过孔V7与第一极板25连接。第三连接电极43可以通过第三过孔V3与第四有源层14的第一区14-1连接。第四连接电极44的一端可以通过第四过孔V4与第五有源层15的第一区15-1连接，另一端可以通过第九过孔V9与第二极板33连接。第五连接电极45可以通过第五过孔V5与第六有源层16的第二区16-2连接。第六连接电极46的一端可以通过第六过孔V6与第七有源层17的第一区17-1连接，另一端可以通过第十过孔V10与第二初始信号线32连接。
在一些示例中，如图9E所示，显示区域的第一区域的第三导电层还可以包括：多条第一连接线71和多个第一数据连接电极81。如图9E和图10A所示，显示区域的第三区域的第三导电层还可以包括：多条第一补偿走线91和多个第一补偿连接电极82。如图10A所示，边框区域的第三导电层可以包括：多个第一补偿连接线83。
在一些示例中，如图9E所示，第一连接线71的形状可以为主体部分沿着第一方向X延伸的线形状。在第一区域的至少一个电路单元中，第一连接线71在第二方向Y的一侧可以设置至少一个第一数据连接电极81。例如，在第一区域的一个电路单元中，两个第一数据连接电极81在第二方向Y上可以位于第一连接线71的同一侧。第一连接线71与多个第一数据连接电极81电连接，例如可以为一体结构。在一些示例中，第一连接线71在衬底基板的正投影可以位于所在单元行电连接的发光控制线24和第二初始信号线32在衬底基板的正投影之间。第一连接线71和多个第一数据连接电极81在衬底基板的正投影可以与发光控制线24和第二初始信号线32在衬底基板的正投影没有交叠。
在一些示例中，如图9E和图10A所示，第一补偿走线91的形状可以为主体部分沿着第一方向X延伸的线形状。在第三区域的至少一个电路单元中，第一补偿走线91在第二方向Y的一侧可以设置至少一个第一补偿连接电极82。例如，在第三区域的一个电路单元中，两个第一补偿连接电极82在第二方向Y上可以位于第一补偿走线91的同一侧。第一补偿走线91与多个第一补偿连接电极82电连接，例如可以为一体结构。在一些示例中，第一补偿走线91在衬底基板的正投影可以位于所在单元行电连接的发光控制线24和第二初始信号线32在衬底基板的正投影之间。第一补偿走线91和多个第一补偿连接电极82在衬底基板的正投影可以与发光控制线24和第二初始信号线32在衬底基板的正投影没有交叠。位于同一单元行的多个数据连接电极81和多个第一补偿连接电极82可以沿第一方向X依次排布。在一些示例中，多个第一补偿连接电极82和多个数据连接电极81的形状和大小可以相同。
在一些示例中，如图9E所示，位于同一个单元行且在第一方向X上对齐的第一补偿走线91和第一连接线71之间设置有第一断口DF1。第一断口 DF1将同一个单元行中的第一连接线71和第一补偿走线91截断。例如，第一连接线71在第一方向X上的相对两侧均与第一断口DF1相邻，其中一个第一断口DF1在第一方向X的一侧为第一连接线71，在第一方向X的反方向的一侧为第一补偿走线91，另一个第一断口DF1在第一方向X的一侧为第一补偿走线91，在第一方向X的反方向的一侧为第一补偿走线91。
在一些示例中，如图10A所示，至少一条第一补偿走线91的一端可以延伸至边框区域，并与边框区域内的第一补偿连接线83电连接。例如，第一补偿走线91与第一补偿连接线83可以为一体结构。例如，第一补偿连接线8381可以先沿第二方向Y的反方向延伸，再沿第一方向X或第一方向X的反方向延伸。
(6)、形成第四绝缘层。在一些示例性实施方式中，在形成前述图案的衬底基板上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成第四绝缘层114，如图9F和图10B所示。在本示例中，第四绝缘层114还可以被称为第一平坦层。第四绝缘层114上设置有多个过孔。在一些示例中，如图9F所示，显示区域中每个电路单元的多个过孔均可以包括：第十一过孔V11至第十三过孔V13。第十一过孔V11至第十三过孔V13内的第四绝缘层114被去掉，暴露出第三导电层的表面。如图9F所示，第一区域中多个电路单元和第二区域中多个电路单元还可以包括：第十四过孔V14至第十六过孔V16。第十四过孔V14至第十六过孔V16内的第四绝缘层114可以被去掉，暴露出第三导电层的第一数据连接电极81的表面。如图9F和图10B所示，第三区域中多个电路单元还可以包括：第十七过孔V17和第十八过孔V18。第十七过孔V17和第十八过孔V18内的第四绝缘层114被去掉，暴露出第三导电层的第一补偿连接电极82的表面。如图10B所示，边框区域还可以包括：第十九过孔V19。第十九过孔V19内的第四绝缘层114被去掉，暴露出第一补偿连接线83的表面。
(7)、形成第四导电层。在一些示例性实施方式中，在形成前述图案的衬底基板上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层114上的第四导电层，如图9G和图10C所示。在一些示例中，第四导电层可以称为第二源漏金属(SD2)层。
在一些示例中，如图9G所示，显示区域中多个电路单元的第四导电层均可以包括：第一电源线51、阳极连接电极52以及数据信号线60。
在一些示例中，如图9G所示，第一电源线51的形状可以为主体部分沿着第二方向Y延伸的折线状。第一电源线51可以通过显示区域的第十二过孔V12与第四连接电极44电连接，由于第四连接电极44可以通过过孔分别与存储电容的第二极板33和第五有源层15的第一区15-1连接，因而实现了第一电源线51将电源信号写入第五晶体管T5的第一极，且存储电容的第二极板33与第一电源线51具有相同的电位。第一电源线51还可以延伸至引线区，并与引线区的高压引线电连接，以实现持续接收高电平信号。
在一些示例中，如图9G和图10C所示，第一电源线51在衬底基板上的正投影与第二连接电极42在衬底基板上的正投影可以至少部分交叠，第一电源线51可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在一些示例中，如图9G和图10C所示第一电源线51可以为非等宽度设计，采用非等宽度设计的第一电源线51不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在一些示例中，如图9G和图10C所示，阳极连接电极52的形状可以为矩形状。阳极连接电极52可以通过第十一过孔V11与第五连接电极45电连接。在一些示例中，阳极连接电极52可以被配置为与后续形成的阳极连接，由于第五连接电极45可以通过过孔与第六有源层16的第二区16-2连接，因而实现了阳极通过阳极连接电极52和第五连接电极45与第六晶体管T6的第二极电连接。
在一些示例中，如图9G和图10C所示，数据信号线60的形状可以为主体部分沿着第二方向Y延伸的直线状。数据信号线60可以通过第十三过孔V13与第三连接电极43电连接。由于第三连接电极43可以通过过孔与第四有源层14的第一区14-1连接，因而实现了数据信号线60将数据信号写入第四晶体管T4的第一极。一条数据信号线60可以配置为给一个单元列的多个像素驱动电路提供数据信号。
在一些示例中，如图9G所示，第一区域的多个电路单元的第四导电层 还可以包括：第二数据连接电极86和多个虚设电极85。第二区域的多个电路单元的第四导电层还可以包括：第二连接线72、第二数据连接电极86以及多个虚设电极85。如图9G和图10C所示，第三区域的多个电路单元的第四导电层还可以包括：第二补偿走线92、多个第二补偿连接电极87和多个虚设电极85。
在一些示例中，如图9G所示，第二连接线72的形状可以为主体部分沿着第二方向Y延伸的直线状。在第二区域的至少一个单元列中，第一电源线51、第二连接线72和数据信号线60沿第一方向X依次排布。第二连接线72可以位于第一电源线51和数据信号线60之间。在第一电源线51和第二连接线72之间可以设置一个第二数据连接电极86或者一个虚设电极85。第二连接线72可以与相邻的第二数据连接电极86电连接，例如可以为一体结构。数据信号线60沿第一方向X的一侧可以设置一个第二数据连接电极86或者一个虚设电极85。数据信号线60可以与相邻的第二数据连接电极86电连接，例如可以为一体结构。
在一些示例中，如图9G所示，位于第N列第M行的第二数据连接电极86可以通过第十五过孔V15与第一数据连接电极81电连接，从而实现位于第N列的数据信号线60与位于第M行的第一连接线71电连接。位于第N+1列第M行的第二数据连接电极86可以通过第十六过孔V16与第一数据连接电极81电连接，从而实现位于第N+1列的第二连接线72与位于第M行的第一连接线71电连接。如此一来，可以通过位于第M行的第一连接线71电连接位于第N列的数据信号线60和位于第N+1列的第二连接线72。在本示例中，第十五过孔V15可以称为第一连接孔，第十六过孔V16可以称为第二连接孔。在本示例中，第一区域和第二区域的虚设电极85可以通过第十四过孔V14与第一数据连接电极81电连接。
在一些示例中，如图10C所示，第二补偿走线92的形状可以为主体部分沿着第二方向Y延伸的直线状。在第三区域的至少一个单元列中，第一电源线51、第二补偿走线92和数据信号线60可以沿第一方向X依次排布。第二补偿走线92可以位于第一电源线51和数据信号线60之间。在第一电源线51和第二补偿走线92之间可以设置一个第二补偿连接电极87或一个虚设电 极85。第二补偿走线92可以与相邻的第二补偿连接电极87电连接，例如可以为一体结构。数据信号线60沿第一方向X的一侧可以设置一个虚设电极85。
在一些示例中，如图10C所示，至少一个第二补偿连接电极87可以通过第十八过孔V18与第一补偿连接电极82电连接，从而实现第一补偿走线91和第二补偿走线92的电连接。在本示例中，第十八过孔V18可以称为第三连接孔。在一些示例中，多条第二补偿走线92和多条第一补偿走线91可以相互连接，从而构成网状连通结构。在本示例中，第三区域的虚设电极85可以通过第十七过孔V17与第一补偿连接电极82电连接。
在一些示例中，如图9G和图10C所示，虚设电极85在衬底基板的正投影可以与第一数据连接电极81或第一补偿连接电极82在衬底基板的正投影存在交叠。虚设电极85呈现出的形貌和结构与第二补偿连接电极87和第二数据连接电极86可以相同，不仅可以提高制备工艺的均一性，而且使得不同区域具有基本上相同的转接连接结构，不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
在一些示例中，如图9E和9H所示，第四导电层在衬底基板的正投影可以覆盖第一断口DF1。例如，第四导电层的第一电源线51在衬底基板的正投影可以覆盖第一断口DF1。如图9G所示，第一导电层(例如，发光控制线24)在衬底基板的正投影可以覆盖第二断口DF2。在本示例中，通过上侧或下侧的导电层覆盖第一断口DF1和第二断口DF2，可以使得不同区域在透射光及反射光下均能达到基本上相同的显示效果，保证显示基板的外观一致性。
在一些示例中，如图10C所示，边框区域的第四导电层可以包括：多条第二补偿连接线84和边框电源引线510。第二补偿连接线84可以沿第一方向X延伸，且一端可以与边框电源引线510电连接，另一端可以通过第十九过孔V19与第一补偿连接线83电连接。在一些示例中，第二补偿连接线84与边缘电源引线510可以为一体结构。然而，本实施例对此并不限定。在另一些示例中，边框电源引线510可以位于第三导电层，第二补偿连接线84 可以通过第四绝缘层开设的过孔与边框电源引线510电连接。
本示例中，通过第一补偿连接线83和第二补偿连接线84可以实现第一补偿走线91与边框电源引线510之间的电连接。关于第二补偿走线92与边框电源引线510或绑定电源引线410的连接结构类似，故于此不再赘述。
至此，在衬底基板上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、发光控制线、第一电源线、第一初始信号线和第二初始信号线。在垂直于显示基板的平面内，驱动电路层可以至少包括在基底上依次叠设的半导体层、第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层、第三导电层、第四绝缘层、第四导电层。
在一些示例性实施例中，衬底基板101可以是柔性基底，或者可以是刚性基底。刚性基底可以为但不限于玻璃、石英中的一种或多种，柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层111、第二绝缘层112和第三绝缘层113可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层111和第二绝缘层112称为栅绝缘(GI)层，第三绝缘层113称为层间绝缘(ILD)层。第四绝缘层114可以采用有机材料， 如树脂等。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在一些示例性实施例中，制备完成驱动电路层后，可以在驱动电路层上依次制备发光结构层和封装结构层，在此不再赘述。
从以上描述的显示基板的结构以及制备过程可以看出，本示例性实施例通过在显示区域内设置数据连接线，使得绑定区域的引出线通过数据连接线与数据信号线连接，使得引线区中不需要设置扇形状的斜线，有效减小了引线区的长度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。本示例将数据连接线的第一连接线和第二连接线设置在不同的导电层，可以方便数据连接线的布局，避免大量走线聚集排布，使得不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。本示例通过设置补偿走线和虚设电极，可以进一步均衡显示区域的走线排布，有效消除了消影情况，有效避免了显示基板的外观不良。本示例通过将补偿走线设置成网状连通结构，不仅可以有效降低电源走线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可以有效提升显示基板中电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施例中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。例如，半导体层和衬底基板之间可以设置缓冲层。
图11A为图7A中区域C1形成第四导电层后的显示基板的另一局部放大示意图。图11B为图7A中区域C1形成第五绝缘层后的显示基板的另一局部放大示意图。图11C为图7A中区域C1形成第五导电层后的显示基板的另一局部放大示意图。图11D为图7A中区域C1的第四导电层和第五导电层的局部放大示意图。图11E为图11C中沿U-U’方向的剖面示意图。
在一些示例性实施方式中，如图11A至图11E所示，在垂直于显示基板的方向上，驱动电路层可以包括：依次设置在衬底基板101上的第一导电层、第二导电层、第三导电层、第四导电层和第五导电层。第四导电层可以包括：数据信号线60、第二连接线72和第二补偿走线92，第五导电层可以包括：第一连接线71和第一补偿走线91。第一绝缘层111可以设置在半导体层和第一导电层之间，第二绝缘层112可以设置在第一导电层与第二导电层之间，第三绝缘层113可以设置在第二导电层与第三导电层之间，第四绝缘层114可以设置在第三导电层与第四导电层之间。第五绝缘层115可以设置在第四导电层和第五导电层之间。本示例的驱动电路层可以包括三个源漏金属层。
在一些示例中，如图11A所示，显示区域中多个电路单元的第四导电层均可以包括：第一电源线51、阳极连接电极52、数据信号线60。显示区域的第四导电层还可以包括：第二连接线72、第二数据连接电极86、第二补偿走线92、第二补偿连接电极、以及多个虚设电极85。
在一些示例中，如图11B所示，显示区域的第五绝缘层115可以开设有多个过孔。例如，第一区域中多个电路单元和第二区域中多个电路单元可以包括：第二十一过孔V21至第二十三过孔V23。第三区域中多个电路单元可以至少包括第二十四过孔V24。第二十一过孔V21至第二十四过孔V24内的第五绝缘层115被去掉，暴露出第四导电层的表面。
在一些示例中，如图11C所示，显示区域的第五导电层可以包括：第一连接线71、第一补偿走线91、第一数据连接电极81和第一补偿连接电极82。第一连接线71和多个第一数据连接电极81可以为一体结构。第一补偿走线91和多个第一补偿连接电极82可以为一体结构。
在一些示例中，位于第N列第M行的第一数据连接电极81可以通过第二十一过孔V21与第二数据连接电极86电连接，从而实现位于第M行的第一连接线71与位于第N列的数据信号线60与电连接。位于第N+1列第M行的第一数据连接电极81可以通过第二十二过孔V22与第二数据连接电极86电连接，从而实现位于第M列的第一连接线71与位于第N+1列的第二连接线72电连接。在本示例中，第二十一过孔V21可以称为第一连接孔，第二十二过孔V22可以称为第二连接孔。在一些示例中，第一数据连接电极81 可以通过第二十三过孔V23与虚设电极85电连接。第一补偿连接电极82可以通过第二十四过孔V24与虚设电极85电连接。第一补偿连接电极还可以与第二补偿连接电极电连接，以实现第一补偿走线和第二补偿走线的电连接。
在一些示例中，如图11D所示，第一补偿走线91与第一连接线71之间设置的第一断口DF1在衬底基板的正投影可以位于第四导电层的正投影范围内，例如可以被第一电源线51的正投影覆盖。如图11C所示，第二补偿走线92和第二连接线72之间设置的第二断口DF2在衬底基板的正投影可以位于第一导电层的正投影范围内，例如可以被发光控制线的正投影覆盖。然而，本实施例对此并不限定。
关于本示例的驱动电路层的其余结构可以参照前述实施例的说明，故于此不再赘述。
在一些示例中，在显示基板的制备过程中，在形成第四导电层之后，可以涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成第五绝缘层115，随后，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第五绝缘层115上的第五导电层。在一些示例中，第五导电层可以称为第三源漏金属(SD3)层。第五绝缘层可以称为第二平坦层。在一些示例中，第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第五绝缘层可以采用有机材料，如树脂等。关于本实施例的显示基板的其余制备过程可以参照前述实施例的说明，故于此不再赘述。
本示例提供的显示基板，通过将第一连接线设置在第五导电层，可以降低第一连接线的负载，适用于较高刷新率的显示基板。
图12A为图7A中区域C1形成第二导电层后的显示基板的另一局部放大示意图。图12B为图7A中区域C1形成第三绝缘层后的显示基板的另一局部放大示意图。图12C为图7A中区域C1形成第三导电层后的显示基板的另一局部放大示意图。图12D为图7A中区域C1的第二导电层和第三导电层的局部放大示意图。图12E为图12C中沿R-R’方向的剖面示意图。
在一些示例性实施方式中，如图12A至图12E所示，在垂直于显示基板 的方向上，驱动电路层可以包括：依次设置在衬底基板101上的第一导电层、第二导电层和第三导电层。第一绝缘层111可以设置在半导体层和第一导电层之间，第二绝缘层112可以设置在第一导电层与第二导电层之间，第三绝缘层113可以设置在第二导电层与第三导电层之间。
在一些示例中，如图12A所示，显示区域中每个电路单元的第二导电层可以包括：第一初始信号线31、第二初始信号线32、存储电容的第二极板33、极板连接线34和屏蔽电极35。显示区域的第一区域的多个电路单元可以包括：第一连接线71、多个第一数据连接电极81。显示区域的第三区域的多个电路单元可以包括：第一补偿走线91、多个第一补偿连接电极82。
在一些示例中，如图12B所示，第三绝缘层可以开设有多个过孔。例如，第一区域中多个电路单元和第二区域中多个电路单元还可以包括：第二十六过孔V26至第二十八过孔V28。第三区域中多个电路单元还可以包括：第二十九过孔V29。第二十六过孔V26至第二十九过孔V29内的第三绝缘层113被去掉，暴露出第二导电层的表面。
在一些示例中，如图12C所示，第一区域和第二区域中多个电路单元的第三导电层还可以包括：第二连接线72、第二数据连接电极86以及多个虚设电极85。第三区域中多个电路单元的第三导电层还可以包括：第二补偿走线92、第二补偿连接电极以及多个虚设电极85。在一些示例中，第一电源线51可以位于第三导电层，且第一电源线51的形状可以为主体部分沿着第二方向Y延伸的直线段。在一个单元列中，第二补偿走线92和第二连接线72可以位于数据信号线60远离第一电源线51的一侧。
在一些示例中，位于第N列第M行的第二数据连接电极86可以通过第二十六过孔V26与第一数据连接电极81电连接，从而实现位于第M行的第一连接线71与位于第N列的数据信号线60与电连接。位于第N+1列第M行的第二数据连接电极87可以通过第二十七过孔V27与第一数据连接电极81电连接，从而实现位于第M列的第一连接线71与位于第N+1列的第二连接线72电连接。在本示例中，第二十六过孔V26可以称为第一连接孔，第二十七过孔V27可以称为第二连接孔。在一些示例中，虚设电极85可以通过第二十八过孔V28与第一数据连接电极81电连接。虚设电极85可以通过 第二十九过孔V29与第一补偿连接电极82电连接。第一补偿连接电极还可以与第二补偿连接电极电连接，以实现第一补偿走线和第二补偿走线的电连接。
在一些示例中，如图12D所示，第一补偿走线91与第一连接线71之间设置的第一断口DF1在衬底基板的正投影可以位于第三导电层的正投影范围内，例如可以被第一电源线51的正投影覆盖。如图12C所示，第二补偿走线92和第二连接线72之间设置的第二断口DF2在衬底基板的正投影可以位于第一导电层的正投影范围内，例如可以被发光控制线的正投影覆盖。然而，本实施例对此并不限定。
本示例提供的显示基板，驱动电路层仅包括三个导电层，可以减少工艺流程，减少掩模版的使用量和制作材料的使用量，从而可以降低成本。
关于本示例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图13为本公开至少一实施例的显示基板的另一平面结构示意图。在一些示例中，如图13所示，至少一个单元行中可以仅设置第一补偿走线91，至少一个单元行中可以仅设置至少一条第一连接线71。第一连接线71可以从靠近左侧或右侧的边框区域的一侧向中心线O延伸。第一连接线71的一端可以延伸至左侧或右侧的边框区域与显示区域的边界，另一端可以延伸至中心线O。至少一个单元行中的至少两条第一连接线71可以在第一方向上对齐，且相邻第一连接线71之间可以设置断口，以实现不同数据信号线60和数据连接线70之间的连接。至少一个单元列中可以仅设置第二补偿走线92，至少一个单元列中可以仅设置第二连接线72。在本示例中，第二连接线72可以沿第二方向D2贯通显示区域100。第二连接线72的一端可以延伸至上侧的边框区域与显示区域的边界，另一端可以延伸绑定区域与显示区域的边界B。
图14为图13中区域C3的驱动电路层的局部放大示意图。在本示例中，以驱动电路层包括三层源漏金属层为例进行示意。如图14所示，第一连接线71、第一补偿走线91、第一数据连接电极81和第一补偿连接电极82可以位于第五导电层，第二连接线72、第二补偿走线92、数据信号线60、第一电 源线51、第二数据连接电极、第二补偿连接电极以及虚设电极可以位于第四导电层。在本示例中，通过将第一连接线设置在第五导电层，可以减小第一连接线的负载，从而可以增加第一连接线的长度，简化走线排布。关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图15为本公开至少一实施例的显示基板的另一平面结构示意图。在一些示例中，如图15所示，第一连接线71可以沿第一方向X贯通显示区域100。第一连接线71的一端可以延伸至左侧边框区域与显示区域的边界，另一端可以延伸至右侧边框区域与显示区域的边界。至少一个单元行可以仅设置一条第一连接线71。第一连接线71可以与数据信号线60和第二连接线72电连接。第一补偿走线91可以与第一连接线71平行且同层设置，第一补偿走线91可以从左侧边框区域延伸至右侧边框区域。
在一些示例中，如图15所示，第二连接线72可以沿第二方向Y贯通显示区域。第二连接线72的一端可以延伸至上侧边框区域与显示区域的边界，另一端可以延伸至绑定区域与显示区域的边界。第二补偿走线92可以与第二连接线72平行且同层设置。第二补偿走线92可以从上侧边框区域延伸至绑定区域。
在一些示例中，第一连接线71和第一补偿走线91可以位于第五导电层，第二连接线72、第二补偿走线92和数据信号线60可以位于第四导电层。然而，本实施例对此并不限定。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在一些示例性实施方式中，显示区域的至少一个电路单元可以包括多个无效像素电路。至少一条第二连接线在衬底基板的正投影可以与至少一个单元列的无效像素驱动电路在衬底基板的正投影存在交叠。在一些示例中，显示基板的显示区域可以包括屏下摄像头(UDC，Under Display Camera)区域和正常显示区域，感光传感器(如，摄像头等硬件)在显示基板上的正投影可以位于屏下摄像头区域。通过对显示区域的像素驱动电路进行压缩可以排布位于屏下摄像头区域的发光元件所连接的像素驱动电路，同时也会产生无效像素驱动电路。
图16为本公开至少一实施例的电路单元的排布示意图。在一些示例中，显示区域的多个单元列可以包括：多个第一单元列75和多个第二单元列76。第一单元列75可以包括多个有效像素驱动电路。第二单元列76可以包括多个无效像素驱动电路。第一单元列75和第二单元列76可以沿第一方向X间隔排布。例如，相邻两个第二单元列76之间可以设置四个第一单元列75。然而，本实施例对此并不限定。例如，相邻两个第二单元列之间可以设置一个或者多个第一单元列。
图17为本公开至少一实施例的显示基板的另一平面结构示意图。图18A为图17中区域C4形成第三导电层后的显示基板的局部放大示意图。图18B为图17中区域C4形成第四导电层后的显示基板的局部放大示意图。图18C为图18B中第三导电层和第四导电层的示意图。
在一些示例中，如图17所示，第二连接线72可以排布在包括无效像素驱动电路的单元列(即前述的第二单元列)。至少一个第二单元列可以包括至少一条第二连接线72和至少一条第二补偿走线92。例如，至少一个第二单元列可以包括一条第二连接线72和一条第二补偿走线92。然而，本实施例对此并不限定。
在一些示例中，如图18A至图18C所示，显示基板的驱动电路层可以包括：依次设置在衬底基板的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。半导体层和第一导电层之间设置第一绝缘层。第一导电层和第二导电层之间设置第二绝缘层。第二导电层和第三导电层之间设置第三绝缘层。第三导电层和第四导电层之间设置第四绝缘层。本示例的驱动电路层可以包括两个源漏金属层。
在一些示例中，如图18A所示，显示区域的第三导电层可以至少包括：第一连接线71、第一补偿走线91、第一数据连接电极81、第一补偿连接电极82。在一些示例中，第一连接线71的形状可以为主体部分沿着第二方向Y延伸的折线状。例如，第一连接线71可以为曲线或者S型线。第一连接线71与多个第一数据连接电极81可以为一体结构。第一补偿走线91的形状可以为主体部分沿着第二方向Y延伸的折线状。例如，第一补偿走线91可以为曲线或者S型线。第一补偿走线91与多个第一补偿连接电极82可以为 一体结构。
在一些示例中，如图18B所示，显示区域的第四导电层可以至少包括：第二连接线72、第二补偿走线92、数据信号线60、第一电源线51、第二数据连接电极86、虚设电极85以及第二补偿连接电极。第二连接线72可以与其相邻的一个第二数据连接电极86为一体结构。数据信号线60可以与其相邻的一个第二数据连接电极86为一体结构。在一些示例中，第二单元列(即包括无效像素电路的单元列)可以不设置数据信号线，而将空间留出用于排布第二连接线和第二补偿走线。例如，第二单元列可以排布至少一条第二连接线和第二补偿走线。在一些示例中，第二单元列的第四导电层的阳极连接电极和第一电源线可以与第三导电层没有电性连接。然而，本实施例对此并不限定。
在一些示例中，如图18A至图18C所示，第N列和第N+5列可以为第二单元列。第N-4列至第N-1列以及第N+1列至第N+4列可以为第一单元列。第N列和第N+5列的第四导电层可以包括：第一电源线51、第二连接线72、第二补偿走线92、第二数据连接电极86和虚设电极85。第二单元列的第四导电层的第一电源线可以与第三导电层没有电性连接。在第二单元列中，第一电源线51可以与第二连接线72和第二补偿走线92相邻。第N-4列至第N-1列以及第N+1列至第N+4列的第四导电层可以包括：第一电源线51和数据信号线60、虚设电极85、第二数据连接电极86。
在一些示例中，如图18A至图18C所示，位于第N列的第二连接线72可以通过位于第M+1行的第一连接线71与位于第N-1列的数据信号线60电连接。位于第N+5列的第二连接线72可以通过位于第M行的第一连接线71与位于第N-2列的数据信号线60电连接。其中，第一连接线71的一端可以与第一数据连接电极81为一体结构，第一数据连接电极81可以通过第四绝缘层的过孔与第二数据连接电极86电连接，由于第二数据连接电极86可以与数据信号线60为一体结构，从而实现第一连接线71与数据信号线60的电连接。第一连接线71的另一端可以与另一个第一数据连接电极81为一体结构，该第一数据连接电极81可以通过第四绝缘层的过孔与另一个第二数据连接电极86电连接，由于该第二数据连接电极86可以与第二连接线72 为一体结构，从而实现第一连接线71与第二连接线72的电连接。
在一些示例中，虚设电极85呈现出的形貌和结构与第二补偿连接电极和第二数据连接电极86可以相同，不仅可以提高制备工艺的均一性，而且使得不同区域具有基本上相同的转接连接结构，不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
在本示例中，通过将第二连接线和第二补偿走线设置在第二单元列，可以避免大量走线聚集排布，使得不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图19为本公开至少一实施例的显示基板的另一平面结构示意图。在一些示例性实施方式中，如图19所示，显示区域100的多条数据信号线60可以沿着第二方向Y延伸，并按照编号递增的方式沿着第一方向X以设定的间隔顺序设置。显示区域的多条数据信号线60均可以与数据连接线70对应连接。引线区201的多条引出线80均可以与数据连接线70对应连接。在本示例中，全部引出线80可以不与数据信号线60直接连接，而是通过数据连接线70实现连接。本示例中，通过将全部数据信号线60通过数据连接线70与引出线80连接。
在一些示例中，如图19所示，数据连接线70可以包括沿第一方向X延伸的第一连接线71和沿第二方向Y延伸的第二连接线72。显示区域在第一方向X具有中心线O。位于中心线O一侧的区域内，靠近中心线O的数据信号线60所电连接的第一连接线71，可以位于远离中心线O的数据信号线60所电连接的第一连接线71远离绑定区域200的一侧。靠近中心线O的数据信号线60所电连接的第二连接线72，可以位于远离中心线O的数据信号线60所电连接的第二连接线72靠近中心线O的一侧。在本示例中，位于中心线O一侧的区域内，多条第一连接线71沿第一方向X的长度可以沿着第二方向逐渐增加。多条第二连接线72沿着第二方向Y的长度可以沿着第一 方向X逐渐增加。然而，本实施例对此并不限定。
图20为本公开至少一实施例的显示基板的另一平面结构示意图。在一些示例中，如图20所示，多条第二连接线72可以沿第二方向Y贯通显示区域100。第二连接线72的一端可以延伸至上侧边框区域和显示区域100的边界，另一端可以延伸至显示区域100和绑定区域200的边界。关于本实施例的显示基板的其余结构可以参照图19所示实施例的说明，故于此不再赘述。
图21为本公开至少一实施例的显示基板的另一平面结构示意图。图22为本公开至少一实施例的补偿走线的平面结构视图。在一些示例中，如图21和图22所示，显示区域100的驱动电路层可以包括：组成电路单元阵列的多个电路单元、多条数据信号线60、多条数据连接线70和补偿走线90。多个电路单元、多条数据信号线60和多条数据连接线70的布局和结构与前述图20所示布局和结构大致相同。补偿走线90可以包括多条沿第一方向X延伸的第一补偿走线91和多条沿第二方向Y延伸的第二补偿走线92。多条第一补偿走线91可以沿着第二方向Y依次设置，多条第二补偿走线92可以沿着第一方向X依次设置。第一补偿走线91和第二补偿走线92可以设置在不同的导电层中。例如，第一补偿走线91和第一连接线71可以同层设置，第二补偿走线92和第二连接线72可以同层设置。
图23A为图21中区域C5形成第三导电层后的显示基板的局部放大示意图。图23B为图21中区域C5形成第四导电层后的显示基板的局部放大示意图。图23C为图21中区域C5形成第五绝缘层后的显示基板的局部放大示意图。图23D为图21中区域C5形成第五导电层后的显示基板的局部放大示意图。图23E为图21中区域C5的第三导电层、第四导电层和第五导电层的局部放大示意图。图23A至图23E中仅示意了区域C5中若干单元行(例如包括第M-1行和第M行)和若干单元列(例如包括第N-1列至第N+3列)的结构。
在一些示例性实施方式中，显示基板的驱动电路层可以包括：依次设置在衬底基板上的半导体层、第一导电层、第二导电层、第三导电层、第四导电层和第五导电层。半导体层和第一导电层之间设置有第一绝缘层。第一导电层和第二导电层之间设置有第二绝缘层。第二导电层和第三导电层之间设 置有第三绝缘层。第三导电层和第四导电层之间设置有第四绝缘层。第四导电层和第五导电层之间设置有第五绝缘层。本示例的驱动电路层可以包括三个源漏金属层。
在一些示例中，如图23A所示，显示区域的第三导电层可以包括：多个连接电极和第一电源线51。第一电源线51可以通过第三绝缘层开设的过孔与存储电容的第二极板33以及第五有源层的第一区连接。关于第三导电层的多个连接电极、第三绝缘层、第二导电层、第二绝缘层、第一导电层、第一绝缘层和半导体层的描述可以参照前述实施例的相关说明，故于此不再赘述。
在一些示例中，如图23B所示，显示区域的第四导电层可以至少包括：阳极连接电极52、遮挡电极53、数据信号线60、第二连接线72和第二补偿走线。遮挡电极53可以通过第四绝缘层开设的过孔与第一电源线51电连接。在一些示例中，像素驱动电路的第三晶体管T3的栅极、第一晶体管T1的第二极、第二晶体管T2的第一极以及存储电容的第一极板与第一节点N1电连接。遮挡电极53在衬底基板的正投影可以覆盖第一节点N1在衬底基板的正投影，从而可以有效屏蔽数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。至少一个单元列可以设置一条数据信号线60和至少两条第二连接线72。两条第二连接线72可以与数据信号线60相邻。例如，数据信号线60在衬底基板的正投影可以位于第一电源线51和第二连接线72在衬底基板的正投影之间。然而，本实施例对此并不限定。例如，至少一个单元列可以包括多条第二连接线。又如，相邻两个单元列可以包括三条第二连接线。
在一些示例中，如图23C所示，显示区域的第五绝缘层可以开设有多个过孔。例如，第五绝缘层开设的多个过孔可以包括：第三十一过孔V31至第三十三过孔V33。第三十一过孔V31至第三十三过孔V33内的第五绝缘层可以被去掉，暴露出第四导电层的表面。例如，第五绝缘层开设的多个过孔可以沿第一方向X依次排布。例如，在一个单元行内的多个过孔在衬底基板的正投影可以与本单元行的第二扫描线22在衬底基板的正投影存在交叠。在本示例中，通过设置多个规则排布的过孔，有助于提高制备工艺的均一性。
在一些示例中，如图23D所示，显示区域的第五导电层可以包括：沿第 一方向X延伸的第一连接线71和第一补偿走线91、第一数据连接电极81以及虚设电极85。第一连接线71和第一补偿走线91可以为沿第一方向X延伸的直线状。第一连接线71的两端可以分别与第一数据连接电极81电连接，例如可以为一体结构。例如，位于第M-1行的第一连接线71的第一端可以通过第一数据连接电极81经由第三十一过孔V31与位于第N+2列的数据信号线60电连接，第二端可以通过另一个第一数据连接电极81经由第三十二过孔V32与位于第N+3列的一条第二连接线72电连接。位于第M行的第一连接线71的第一端可以通过一个第一数据连接电极81经由第三十一过孔V31与位于第N+1列的数据信号线60电连接，第二端可以通过另一个第一数据连接电极81经由第三十二过孔V32与位于第N+3列的另一条第二连接线72电连接。同理，位于第N+3列的数据信号线60可以通过位于第M-1行的另一条第一连接线71与该数据信号线60右侧的一条第二连接线72电连接。在本示例中，第一数据连接电极可以直接与数据信号线或第二连接线电连接，无需通过其他连接电极转接实现，可以节省排布空间。然而，本实施例对此并不限定。在另一些示例中，第四导电层还可以包括：第二数据连接电极和第二补偿连接电极。第二数据连接电极可以与数据信号线或第二连接线为一体结构，第二补偿连接电极可以与第二补偿走线为一体结构。第一数据连接电极可以与第二数据连接电极电连接，第二补偿连接电极可以与第一补偿连接电极电连接。
在一些示例中，如图23D和图23E所示，多个第一数据连接电极81和多个虚设电极85可以在第二方向Y上位于第一连接线71的相同侧。在一个单元行中，多个第一数据连接电极81和多个虚设电极85可以沿第一方向X对齐排布。虚设电极85可以通过第三十三过孔V33与数据信号线60或第二连接线72电连接。虚设电极85在衬底基板的正投影可以与数据信号线60或第二连接线72在衬底基板的正投影至少部分交叠。虚设电极85呈现出的形貌和结构与第一数据连接电极81可以相同，不仅可以提高制备工艺的均一性，而且使得不同区域具有基本上相同的转接连接结构，不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
在一些示例中，显示区域的第五导电层还可以包括多个第一补偿连接电极。第一补偿走线91可以与多个第一补偿连接电极为一体结构。第一补偿走线91可以通过第一补偿连接电极与第二补偿走线92电连接。第一补偿连接电极的形貌和结构可以与第一数据连接电极81相同，从而可以提高制备工艺的均一性。
在一些示例中，如图23E所示，第一连接线71和第一补偿走线91之间设置第一断口DF1。第一断口DF1在衬底基板的正投影可以位于第三导电层或第四导电层覆盖的区域内。例如，第一断口DF1在衬底基板的正投影可以被第四导电层的第二连接线在衬底基板的正投影覆盖。又如，第一断口DF1在衬底基板的正投影可以被第三导电层的第一电源线51在衬底基板的正投影覆盖。
关于本实施例的显示基板的其余结构和制备过程可以参照前述实施例的说明，故于此不再赘述。
图24为本公开至少一实施例的显示基板的外观效果的示意图。在一些示例中，如图24所示，本实施例的显示基板通过将第一连接线和第二连接线排布在不同的导电层，而且在显示区域设置第一补偿走线和第二补偿走线，除了数据连接线和补偿走线的断口处存在少量差异，可以使得显示区域的不同区域的走线达到一致，从而使得不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
图25A为图21中区域C5形成第三导电层后的显示基板的另一局部放大示意图。图25B为图21中区域C5形成第四导电层后的显示基板的另一局部放大示意图。图25C为图21中区域C5的第三导电层和第四导电层的局部放大示意图。图25A至图25C中仅示意了区域C5中若干单元行(例如包括第M-1行和第M行)和若干单元列(例如包括第N-1列至第N+3列)的结构。
在一些示例性实施方式中，显示基板的驱动电路层可以包括：依次设置在衬底基板上的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。半导体层和第一导电层之间设置有第一绝缘层。第一导电层和第二导电层之间设置有第二绝缘层。第二导电层和第三导电层之间设置有第三绝缘 层。第三导电层和第四导电层之间设置有第四绝缘层。本示例的驱动电路层可以包括两个源漏金属层。
在一些示例中，如图25A所示，显示区域的第三导电层可以包括：多个连接电极、第一连接线71、第一补偿走线91、第一数据连接电极81和多个虚设电极85。在一个单元行内，第一连接线71和第一补偿走线91在衬底基板的正投影可以位于本单元行的发光控制线24和第二初始信号线32在衬底基板的正投影之间。至少一个电路单元中可以设置多个虚设电极85，或者可以设置虚设电极85和第一数据连接电极81。在一个单元行内，多个虚设电极85和多个第一数据连接电极81沿第一方向X排布。多个虚设电极85和多个第一数据连接电极81可以在第二方向Y上位于本单元行的第一连接线71的同一侧。第一连接线71可以与多个第一数据连接电极81为一体结构。在一些示例中，第三导电层还可以包括：多个第一补偿连接电极。多个第一补偿连接电极可以与第一补偿走线为一体结构。第一补偿连接电极的形貌和结构可以与第一数据连接电极81和虚设电极85相同，从而可以提高制备工艺的均一性。
在一些示例中，如图25B所示，显示区域的第四导电层可以包括：阳极连接电极、数据信号线60、第二连接线72、第一电源线51和第二补偿走线。至少一个单元列可以设置一条数据信号线60和至少两条第二连接线72。两条第二连接线72可以与数据信号线60相邻。例如，数据信号线60在衬底基板的正投影可以位于第一电源线51和第二连接线72在衬底基板的正投影之间。然而，本实施例对此并不限定。在另一些示例中，第一电源线51可以设置在第三导电层。
在一些示例中，如图25A和图25C所示，第一连接线71和第一补偿走线91之间设置第一断口DF1。第一断口DF1在衬底基板的正投影可以位于第四导电层覆盖的区域内。例如，第一断口DF1在衬底基板的正投影可以被第四导电层的第二连接线、数据信号线或第一电源线在衬底基板的正投影覆盖。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图26A为图21中区域C5形成第二导电层后的显示基板的另一局部放大示意图。图26B为图21中区域C5形成第三导电层后的显示基板的另一局部放大示意图。图26C为图21中区域C5的第二导电层和第三导电层的局部放大示意图。图26A至图26C中仅示意了区域C5中若干单元行(例如包括第M-1行和第M行)和若干单元列(例如包括第N-1列至第N+3列)的结构。
在一些示例性实施方式中，显示基板的驱动电路层可以包括：依次设置在衬底基板上的半导体层、第一导电层、第二导电层和第三导电层。半导体层和第一导电层之间设置有第一绝缘层。第一导电层和第二导电层之间设置有第二绝缘层。第二导电层和第三导电层之间设置有第三绝缘层。本示例的驱动电路层可以包括单个源漏金属层。
在一些示例中，如图26A所示，显示区域的第二导电层可以包括：第一初始信号线31、第二初始信号线32、存储电容的第二极板33、极板连接电极、屏蔽电极、第一连接线72、第一补偿走线91、第一数据连接电极81、以及多个虚设电极85。在一个单元行内，第一连接线71和第一补偿走线91在衬底基板的正投影可以位于本单元行的发光控制线24和第二初始信号线32在衬底基板的正投影之间。至少一个电路单元中可以设置多个虚设电极85，或者可以设置虚设电极85和第一数据连接电极81。在一个单元行内，多个虚设电极85和多个第一数据连接电极81沿第一方向X排布。多个虚设电极85和多个第一数据连接电极81可以在第二方向Y上位于本单元行的第一连接线71的同一侧。第一连接线71可以与多个第一数据连接电极81为一体结构。在一些示例中，第二导电层还可以包括：多个第一补偿连接电极。多个第一补偿连接电极可以与第一补偿走线为一体结构。第一补偿连接电极的形貌和结构可以与第一数据连接电极81和虚设电极85相同，从而可以提高制备工艺的均一性。
在一些示例中，如图26B所示，显示区域的第三导电层可以包括：多个连接电极、数据信号线60、第一连接线72、第一电源线51以及第二补偿走线。在至少一个单元列中，两条第二连接线72、第一电源线51和数据信号线60可以沿第一方向X依次排布。两条第二连接线72可以与数据信号线60相邻。例如，数据信号线60在衬底基板的正投影可以位于第一电源线51和 第二连接线72在衬底基板的正投影之间。
在一些示例中，如图26A和图26C所示，第一连接线71和第一补偿走线91之间设置第一断口DF1。第一断口DF1在衬底基板的正投影可以位于第三导电层覆盖的区域内。例如，第一断口DF1在衬底基板的正投影可以被第三导电层的第二连接线、数据信号线或第一电源线在衬底基板的正投影覆盖。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
在另一些示例性实施方式中，第一连接线和第一补偿走线可以位于第四导电层，第一电源线、第二连接线、数据信号线和第二补偿走线可以位于第三导电层。又如，第一连接线和第一补偿走线可以位于第四导电层，第二连接线和第二补偿走线可以位于第五导电层。数据信号线和第一电源线可以均位于第三导电层，或者可以均位于第五导电层；或者，数据信号线可以位于第三导电层，第一电源线可以位于第五导电层；或者，数据信号线可以位于第五导电层，第一电源线可以位于第三导电层。
本实施例通过在显示区域内设置数据连接线，使得绑定区域的引出线部分或全部通过数据连接线与数据信号线连接，使得引线区中不需要设置扇形状的斜线，有效减小了引线区的长度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。本示例将数据连接线的第一连接线和第二连接线设置在不同的导电层，可以方便数据连接线的布局，避免大量走线聚集排布，使得不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效消除了消影情况，有效避免了显示基板的外观不良，提高了显示品质和显示质量。本示例通过设置补偿走线和虚设电极，可以进一步均衡显示区域的走线排布，有效消除了消影情况，有效避免了显示基板的外观不良。本示例通过将补偿走线设置成网状连通结构，不仅可以有效降低电源走线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可以有效提升显示基板中电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在一些示例性实施例中，本公开实施例的显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开实施例还提供一种显示装置，显示装置可以包括前述的显示基板。在一些示例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (22)

  1. 一种显示基板，包括：显示区域和位于所述显示区域一侧的绑定区域；
    所述显示区域包括：衬底基板以及设置在所述衬底基板上的驱动电路层；
    所述驱动电路层包括：构成多个单元行和多个单元列的多个电路单元、多条数据信号线和多条数据连接线；所述多条数据信号线中的至少一条数据信号线与一个单元列电连接；
    所述多条数据连接线中的至少一条数据连接线包括：沿第一方向延伸的第一连接线和沿第二方向延伸的第二连接线，所述第二连接线向所述绑定区域延伸，所述第一方向和所述第二方向交叉；
    所述第一连接线分别与所述第二连接线和所述数据信号线电连接；所述第一连接线和所述第二连接线位于不同的导电层。
  2. 根据权利要求1所述的显示基板，其中，至少一条第一连接线的第一端与所述数据信号线电连接，第二端与所述第二连接线电连接。
  3. 根据权利要求1所述的显示基板，其中，至少一条第一连接线沿所述第一方向贯通所述显示区域。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，至少一条第二连接线沿所述第二方向贯通所述显示区域。
  5. 根据权利要求3或4所述的显示基板，其中，在垂直于显示基板的方向上，所述第一连接线位于所述第二连接线远离所述衬底基板的一侧。
  6. 根据权利要求1至5中任一项所述的显示基板，其中，所述显示区域还包括：沿所述第一方向延伸的多条第一补偿走线、沿所述第二方向延伸的多条第二补偿走线；所述多条第二补偿走线中的至少一条第二补偿走线与所述多条第一补偿走线中的至少一条第一补偿走线电连接。
  7. 根据权利要求6所述的显示基板，还包括：位于所述显示区域其它侧的边框区域，所述边框区域设置有边框电源引线，所述边框电源引线与所述显示区域的多条第一补偿走线和多条第二补偿走线电连接。
  8. 根据权利要求6或7所述的显示基板，其中，所述第一补偿走线和所 述第一连接线同层设置，至少一个电路单元包括第一断口，所述第一断口设置在所述第一补偿走线和所述第一连接线之间。
  9. 根据权利要求8所述的显示基板，其中，所述第一断口在所述衬底基板的正投影被所述第一连接线所在膜层以外的导电膜层在衬底基板的正投影覆盖。
  10. 根据权利要求6至9中任一项所述的显示基板，其中，所述第二补偿走线和所述第二连接线同层设置，至少一个电路单元包括第二断口，所述第二断口设置在所述第二补偿走线和所述第二连接线之间。
  11. 根据权利要求10所述的显示基板，其中，所述第二断口在所述衬底基板的正投影被所述第二连接线所在膜层以外的导电膜层在衬底基板的正投影覆盖。
  12. 根据权利要求1至11中任一项所述的显示基板，其中，至少一个电路单元包括：虚设电极；所述虚设电极通过过孔与数据信号线或第二连接线电连接，所述虚设电极在所述衬底基板的正投影与所述数据信号线或第二连接线在所述衬底基板的正投影至少部分交叠。
  13. 根据权利要求1至11中任一项所述的显示基板，其中，至少一个电路单元包括：虚设电极和第一数据连接电极；所述第一数据连接电极与所述第一连接线电连接，所述虚设电极通过过孔与所述第一数据连接电极电连接，所述虚设电极在所述衬底基板的正投影与所述第一数据连接电极在所述衬底基板的正投影至少部分交叠。
  14. 根据权利要求1至13中任一项所述的显示基板，其中，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个晶体管；
    在垂直于显示基板的方向上，所述驱动电路层包括：在所述衬底基板上设置的半导体层、第一导电层、第二导电层和第三导电层；所述半导体层至少包括所述多个晶体管的有源层，所述第一导电层至少包括所述多个晶体管的栅极和所述存储电容的第一极板，所述第二导电层至少包括所述存储电容的第二极板，所述第三导电层至少包括多个连接电极。
  15. 根据权利要求14所述的显示基板，其中，所述第二导电层还包括： 所述第一连接线，所述第三导电层还包括：所述第二连接线和所述数据信号线。
  16. 根据权利要求14所述的显示基板，其中，所述驱动电路层还包括：位于所述第三导电层远离所述衬底基板一侧的第四导电层；
    所述第四导电层包括：所述数据信号线和所述第二连接线；
    所述第三导电层还包括：所述第一连接线。
  17. 根据权利要求14所述的显示基板，其中，所述驱动电路层还包括：位于所述第三导电层远离所述衬底基板一侧的第四导电层、以及位于所述第四导电层远离所述衬底基板一侧的第五导电层；
    所述第四导电层包括：所述数据信号线和所述第二连接线；
    所述第五导电层包括：所述第一连接线。
  18. 根据权利要求1至17中任一项所述的显示基板，其中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述数据信号线包括第一数据信号线组和第二数据信号线组，所述第一数据信号线组中的数据信号线通过所述数据连接线与所述引出线电连接，所述第二数据信号线组中的数据信号线直接与所述引出线电连接。
  19. 根据权利要求1至17中任一项所述的显示基板，其中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述多条数据信号线通过所述多条数据连接线与所述多条引出线电连接。
  20. 根据权利要求19所述的显示基板，其中，相邻两条数据信号线之间设置有至少两条第二连接线。
  21. 根据权利要求1至20中任一项所述的显示基板，其中，至少一个单元列包括多个无效像素驱动电路，至少一条第二连接线在所述衬底基板的正投影与所述单元列的无效像素驱动电路在所述衬底基板的正投影存在交叠。
  22. 一种显示装置，包括如权利要求1至21中任一项所述的显示基板。
PCT/CN2022/090203 2022-04-29 2022-04-29 显示基板及显示装置 WO2023206339A1 (zh)

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