WO2024092434A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024092434A1
WO2024092434A1 PCT/CN2022/128721 CN2022128721W WO2024092434A1 WO 2024092434 A1 WO2024092434 A1 WO 2024092434A1 CN 2022128721 W CN2022128721 W CN 2022128721W WO 2024092434 A1 WO2024092434 A1 WO 2024092434A1
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Prior art keywords
line
layer
transistor
electrode
exemplary embodiment
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PCT/CN2022/128721
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English (en)
French (fr)
Inventor
尚庭华
张毅
周洋
龙祎璇
张元其
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/128721 priority Critical patent/WO2024092434A1/zh
Publication of WO2024092434A1 publication Critical patent/WO2024092434A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area, wherein the display area includes a driving structure layer arranged on a substrate, the driving structure layer at least includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along a second direction, wherein the first direction and the second direction intersect;
  • the circuit unit includes a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of a plurality of first connecting lines are correspondingly connected to the plurality of data signal lines, and the second ends of the plurality of first connecting lines are correspondingly connected to the plurality of second connecting lines;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are arranged at gaps between pixel driving circuits of adjacent unit columns.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, the first connecting line and the second connecting line are arranged in different conductive layers, and the data signal line and the second connecting line are arranged in the same conductive layer.
  • the multiple conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are arranged in sequence along a direction away from the substrate, the first connecting line is arranged in the second source-drain metal layer, the data signal line and the second connecting line are arranged in the third source-drain metal layer, the data signal line is connected to the first end of the first connecting line through a via, and the second connecting line is connected to the second end of the first connecting line through a via.
  • the pixel driving circuit includes at least a first transistor, a second transistor and a storage capacitor
  • the first transistor includes at least a first active layer
  • the second transistor includes at least a second active layer
  • the second region of the first active layer and the first region of the second active layer are an integrated structure connected to each other, and are connected to the first electrode plate of the storage capacitor through a first connecting electrode
  • the second source-drain metal layer also includes a shielding electrode, the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer and the first region of the second active layer on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode on the substrate.
  • the third source-drain metal layer further includes a first power line, and the first power line is connected to the shielding electrode through a via.
  • the display substrate further comprises a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the light-emitting structure layer comprising a plurality of light-emitting units, the light-emitting units comprising at least an anode; in at least one light-emitting unit, an orthographic projection of the anode on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate, and an orthographic projection of the anode on the substrate at least partially overlaps with an orthographic projection of the shielding electrode on the substrate.
  • the orthographic projection of the anode on the substrate and the orthographic projection of the first power line on the substrate have a first overlapping area
  • the orthographic projection of the anode on the substrate and the orthographic projection of the shielding electrode on the substrate have a second overlapping area, and the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the pixel driving circuit includes at least a fourth transistor, a first electrode of the fourth transistor is connected to the data signal line through a data connection electrode, and in at least one circuit unit, the first connection line is connected to the data connection electrode.
  • At least one circuit unit further includes a data connection block, a first end of the data connection block is connected to the first connection line, and a second end of the data connection block is connected to the data connection electrode.
  • the first connection line, the data connection electrode, and the data connection block are disposed in the same layer and are an integrated structure connected to each other.
  • At least one circuit unit further includes a second initial signal line extending along the first direction and a second initial connecting line extending along the second direction, the second initial connecting line being arranged between two adjacent second initial signal lines in the second direction and being respectively connected to the two second initial signal lines, forming a second initial signal line of a network connection structure in the display area.
  • the second initial connection line is disposed in an odd-numbered cell column, or the second initial connection line is disposed in an even-numbered cell column.
  • the cell column where the second initial connection line is located in one cell row is different from the cell column where the second initial connection line is located in the other cell row.
  • the second initial signal line and the second initial connection line are disposed in the same layer and are an integrated structure connected to each other.
  • the pixel driving circuit includes at least a storage capacitor and a plurality of transistors
  • the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer, which are sequentially arranged along a direction away from the substrate;
  • the shielding layer includes at least a shielding electrode
  • the first semiconductor layer includes at least an active layer of a plurality of low-temperature polysilicon transistors
  • the first gate metal layer includes at least a first scanning signal line, a light-emitting signal line and a first electrode plate of the storage capacitor
  • the second gate metal layer includes at least a second electrode plate of the storage capacitor
  • the second semiconductor layer includes at least an active layer of a plurality of oxide transistors
  • the third gate metal layer includes at least a second scanning signal line and a third scanning signal line
  • the plurality of transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon transistors.
  • the present disclosure further provides a display device, comprising the aforementioned display substrate.
  • the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a display area, and the preparation method includes:
  • a driving structure layer is formed on the substrate of the display area, the driving structure layer at least comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction and a plurality of second connecting lines extending along a second direction, wherein the first direction intersects with the second direction;
  • the circuit unit comprises a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, first ends of a plurality of first connecting lines are connected to a plurality of data signal lines correspondingly, and second ends of a plurality of first connecting lines are connected to a plurality of second connecting lines correspondingly;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and extending along the second direction, and the second connecting lines are arranged at gaps
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic structural diagram of a display substrate
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an arrangement of data connection lines according to an exemplary embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG9 is a schematic diagram of an embodiment of the present disclosure after forming a shielding layer pattern
  • FIGS. 10 and 11 are schematic diagrams of the embodiment of the present disclosure after forming a first semiconductor layer pattern
  • FIGS. 12 and 13 are schematic diagrams of the embodiment of the present disclosure after forming the first conductive layer pattern
  • 16 and 17 are schematic diagrams of the second semiconductor layer pattern formed in the embodiment of the present disclosure.
  • FIGS. 18 and 19 are schematic diagrams of the embodiment of the present disclosure after forming a third conductive layer pattern
  • FIG20 is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern
  • 21 and 22 are schematic diagrams of the fourth conductive layer pattern formed in the embodiment of the present disclosure.
  • FIG23 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern
  • 24 and 25 are schematic diagrams of the fifth conductive layer pattern formed in the embodiment of the present disclosure.
  • FIG26 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern
  • 27 to 28 are schematic diagrams of the sixth conductive layer pattern formed in the embodiment of the present disclosure.
  • FIG29 is a schematic diagram of an embodiment of the present disclosure after forming a third planar layer pattern
  • FIG30 is a schematic diagram of an embodiment of the present disclosure after forming an anode conductive layer pattern
  • FIG31 is a schematic diagram of an embodiment of the present disclosure after forming a pixel definition layer pattern
  • FIG. 32 is a schematic diagram of the planar structure of another display substrate according to an embodiment of the present disclosure.
  • 65 anode connection electrode
  • 70 first connection line
  • 71 first bonding block
  • 90 power supply wiring
  • 91 first shielding connection line
  • 92 second shielding connection line
  • 93 third shielding connection line
  • 94 shielding electrode
  • 100 display area
  • 101 substrate
  • 102 driving structure layer
  • 103 light-emitting structure layer
  • 104 Packaging structure layer; 200—Binding area; 300—Border area.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit connected to the circuit unit, the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • FIG2 is a schematic diagram of a structure of a display substrate.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, wherein the plurality of sub-pixels Pxij are configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.
  • the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area.
  • the fan-out area may be connected to the display area and include a plurality of data fan-out lines, and the data fan-out lines are configured to connect the data signal lines (Data Line) of the display area in a fan-out (Fanout) routing manner.
  • the bending area may be connected to the fan-out area and may include a composite insulating layer provided with a groove, and may be configured to bend the driver chip area and the binding pin area to the back of the display area.
  • the driver chip area may be connected to the bending area and may include an integrated circuit (IC), which is configured to be connected to the plurality of data fan-out lines.
  • the binding pin area may be connected to the driver chip area and may include a bonding pad, which is configured to be bonded and connected to an external flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the border area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence in a direction away from the display area.
  • the circuit area may be connected to the display area, and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area.
  • the power line area may be connected to the circuit area, and may include at least a power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area.
  • the crack dam area may be connected to the power line area, and may include at least a plurality of cracks set on the composite insulating layer.
  • the cutting area may be connected to the crack dam area, and may include at least a cutting groove set on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.
  • the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with at least one isolation dam, at least one of which may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area, and the edge of the display area is the edge of one side of the display area binding area or the border area.
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, a third sub-pixel P3 emitting a third color light, and a fourth sub-pixel P4.
  • Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit.
  • the light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal
  • the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement or a square arrangement, etc., which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangle arrangement, etc., which is not limited in the present disclosure.
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor.
  • the light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, a pixel definition layer, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, forming an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a light emitting signal line E, a data signal line D, a first initial signal line INIT1, a second initial signal line INIT1 and a first power line VDD).
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively;
  • the second node N2 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively;
  • the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively;
  • the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively; and the fourth node N4 is also connected to the anode of the light emitting device EL.
  • a first end of the storage capacitor C is connected to the second node N2 , and a second end of the storage capacitor C is connected to the first power line VDD, that is, the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3 .
  • a gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and a second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits the first initialization voltage to the first end of the storage capacitor C, thereby initializing the storage capacitor C.
  • a gate electrode of the second transistor T2 is connected to the third scan signal line S3, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the gate electrode (second node N2) of the third transistor T3 to the second electrode (third node N3) of the third transistor T3.
  • the gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the first end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the light emitting device EL according to the potential difference between its gate electrode and the first electrode.
  • a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1
  • a first electrode of the fourth transistor T4 is connected to the data signal line D
  • a second electrode of the fourth transistor T4 is connected to the first node N1.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting signal line E
  • the first electrode of the fifth transistor T5 is connected to the first power line VDD
  • the second electrode of the fifth transistor T5 is connected to the first node N1
  • the signal of the first power line VDD is a high level signal that is continuously provided.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line E
  • the first electrode of the sixth transistor T6 is connected to the third node N3
  • the second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and a driving current path is formed between the first power line VDD and the light emitting device EL to make the light emitting device EL emit light.
  • a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1
  • a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2
  • a second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the seventh transistor T7 transmits the second initial voltage to the fourth node N4 to initialize or release the charge amount accumulated in the anode of the light emitting device EL.
  • the light emitting device EL may be an OLED including a stacked anode (first pole), an organic light emitting layer and a cathode (second pole), or may be a QLED including a stacked anode (first pole), a quantum dot light emitting layer and a cathode (second pole).
  • a first electrode of the light emitting device EL is connected to the fourth node N4, a second electrode of the light emitting device EL is connected to the second power line VSS, and a signal of the second power line VSS is a continuously provided low level signal.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and a metal oxide transistor.
  • the active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is metal oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide metal oxide semiconductor
  • Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the first transistor T1 and the second transistor T2 may be implemented as metal oxide transistors, and the third to seventh transistors T3 to T7 may be implemented as low temperature polysilicon transistors.
  • the operation process of the pixel driving circuit may include:
  • the signal of the second scan signal line S2 is a turn-on signal (high level), and the signals of the first scan signal line S1, the third scan signal line S3 and the light-emitting signal line E are turn-off signals.
  • the turn-on signal of the second scan signal line S2 turns on the first transistor T1
  • the signal of the first initial signal line INIT1 is provided to the second node N2 through the first transistor T1
  • the storage capacitor C is initialized (reset), and the original charge in the storage capacitor is cleared. Since the first end of the storage capacitor C is at a low level, the third transistor T3 is turned on.
  • the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light.
  • the signals of the first scanning signal line S1 and the third scanning signal line S3 are on signals
  • the signals of the second scanning signal line S2 and the light emitting signal line E are off signals
  • the data signal line D outputs a data voltage.
  • the on signals of the first scanning signal line S1 and the third scanning signal line S3 turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage of the first end (the second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on to provide the signal of the second initial signal line INIT2 to the first electrode of the OLED, initialize (reset) the first electrode of the OLED, clear the pre-stored voltage inside it, complete the initialization, and ensure that the OLED does not emit light.
  • the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the signal of the light-emitting signal line E is a conduction signal
  • the signals of the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 are disconnection signals.
  • the conduction signal of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the binding area usually includes a fan-out area, a bending area, a driver chip area and a binding pin area arranged in sequence along the direction away from the display area. Since the width of the binding area is smaller than the width of the display area, the signal lines of the driver chip and the binding pad in the binding area need to be introduced into the wider display area through the fan-out area in a fan-out routing manner.
  • a frame power lead is usually set in the frame area, and the frame power lead is configured to continuously provide a low-voltage power signal for transmission. In order to reduce the voltage drop of the low-voltage power signal, the width of the frame power lead is large, resulting in a large width of the left and right frames of the display device.
  • FIG6 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure.
  • the display substrate may include a driving structure layer disposed on a substrate, a light emitting structure layer disposed on a side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate.
  • the display substrate may include at least a display area 100, a binding area 200 located on one side of the second direction Y of the display area 100, and a frame area 300 located on the other side of the display area 100.
  • the driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light emitting device.
  • the light emitting structure layer of the display area 100 may include a plurality of light emitting units, at least one light emitting unit may include a light emitting device, the light emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit
  • the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device.
  • the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.
  • a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row
  • a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column
  • a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array
  • the first direction X intersects the second direction Y.
  • the driving structure layer of the display area 100 may further include a plurality of data signal lines 60, a plurality of first connection lines 70, and a plurality of second connection lines 80.
  • the data signal lines 60 are respectively connected to a plurality of pixel driving circuits in a unit column, and the data signal lines 60 are configured to provide data signals to the connected pixel driving circuits.
  • the first ends of the plurality of first connection lines 70 are connected to the plurality of data signal lines 60, and the second ends of the plurality of first connection lines 70 are connected to the plurality of second connection lines 80.
  • the first connection lines 70 and the second connection lines 80 constitute data connection lines, forming a data connection line located in the display area (Fanout in AA, referred to as FIAA) structure.
  • a portion of the data signal lines 60 is connected to the lead-out lines 210 in the binding area 200 through the data connection lines, and another portion of the data signal lines 60 is directly connected to the lead-out lines 210 in the binding area 200.
  • the binding area 200 may include a lead area 201, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area, the lead area 201 is connected to the display area 100, and the bending area is connected to the lead area 201.
  • the lead area 201 may be provided with a plurality of lead lines 210, and the plurality of lead lines 210 may extend in a direction away from the display area, the first ends of a portion of the lead lines 210 are correspondingly connected to the data connection line 60 in the display area 100, and the first ends of another portion of the lead lines are correspondingly connected to the second connection line 80 in the display area 100, and the second ends of the plurality of lead lines 210 extend along the second direction Y and cross the bending area, and then are connected to the driver chip in the driver chip area, so that the driver chip applies the data signal provided by the driver chip to the data signal line 60 through the lead lines 210.
  • the length of the lead area in the second direction Y can be effectively reduced, the width of the lower frame can be greatly reduced, the screen ratio is improved, and it is conducive to achieving full-screen display.
  • the lead-out line 210 and the data signal line 60 and the second connection line 80 may be directly connected, or may be connected through a via hole, which is not limited in the present disclosure.
  • the first connection line 70 may be in a line shape extending along the first direction X
  • the second connection line 80 may be in a line shape extending along the second direction Y
  • the data signal line 60 may be in a line shape extending along the second direction Y.
  • the first connection line 70 may be disposed perpendicular to the data signal line 60
  • the second connection line 80 may be disposed parallel to the data signal line 60 .
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • “A extends along direction B” means "the main part of A extends along direction B".
  • the second direction Y may be a direction pointing from the display area to the binding area, and the opposite direction of the second direction Y may be a direction pointing from the binding area to the display area.
  • the driving structure layer of the display area 100 may further include a plurality of power lines 90.
  • the power lines 90 may be in the shape of a line extending along the second direction Y, and the plurality of power lines 90 may be sequentially arranged along the first direction X.
  • the power trace 90 may be disposed between two adjacent data signal lines 60 in the first direction X.
  • the power supply line 90 and the second connection line 80 may be arranged in the same layer and formed simultaneously by the same patterning process. At least one circuit column may be provided with only the power supply line 90, and the second connection line 80 is not provided in the circuit column. At least one circuit column may be provided with the power supply line 90 and the second connection line 80, and a break DF is provided between the power supply line 90 and the second connection line 80, and the break DF is configured to achieve insulation between the power supply line 90 and the second connection line 80.
  • the plurality of power lines 90 may be lines that continuously provide low voltage signals.
  • the power line may be a second power line VSS.
  • the plurality of power lines 90 may be connected to power leads provided in a binding area or a frame area.
  • the present disclosure realizes a structure in which a low voltage power line is provided in a sub-pixel (VSS in pixel) by providing a power line in the display area, which can not only effectively reduce the resistance of the power signal line, effectively reduce the voltage drop of the low voltage power signal, and achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the low voltage power line provided in the sub-pixel structure can greatly reduce the width of the power lead in the frame area and the binding area, which is conducive to achieving a narrow frame.
  • the display substrate may have a center line O, and multiple data signal lines 60, multiple first connection lines 70, multiple second connection lines 80, multiple power lines 90 and multiple lead lines 210 on the display substrate may be symmetrically arranged relative to the center line O.
  • the center line O may be a straight line that bisects the multiple unit columns of the display area 100 and extends along the second direction Y.
  • the driving structure layer may include multiple conductive layers, the first connecting line 70 and the second connecting line 80 may be set in different conductive layers, the data signal line 60 and the second connecting line 80 may be set in the same conductive layer, the first connecting line 70 may be connected to the data signal line 60 through a first connecting hole, and the second connecting line 80 may be connected to the first connecting line 70 through a second connecting hole.
  • FIG7 is a schematic diagram of the arrangement of a data connection line in an exemplary embodiment of the present disclosure, illustrating the structure of 6 data signal lines, 2 data connection lines and 6 lead lines in the left area of the display substrate.
  • the plurality of data signal lines in the left area may include data signal lines 60-1 to 60-6
  • the plurality of first connection lines may include first connection lines 70-1 and first connection lines 70-2
  • the plurality of second connection lines 80 may include second connection lines 80-1 and second connection lines 80-2
  • the plurality of lead lines may include lead lines 210-1 to 210-6.
  • the data signal lines 60-1 to 60-6 may be in the shape of lines extending along the second direction Y, and may be arranged in ascending order of numbers along the first direction X.
  • the first connection lines 70-1 and 70-2 may be in the shape of lines extending along the first direction X, and may be arranged in ascending order of numbers along the second direction Y.
  • the second connection lines 80-1 and 80-2 may be in the shape of lines extending along the second direction Y, and may be arranged in descending order of numbers along the first direction X.
  • the first end of the first connection line 70-1 is connected to the data signal line 60-1 through the first connection hole K1, and the second end of the first connection line 70-1 is extended along the first direction X, and is connected to the first end of the second connection line 80-1 through the second connection hole K2, and the second end of the second connection line 80-1 is extended along the second direction Y to the binding area, and is connected to the first end of the lead line 210-1, and the second end of the lead line 210-1 is extended along the second direction Y and crosses the bending area, and is connected to the driving chip in the driving chip area, thereby realizing the connection of the lead line 210-1 to the data signal line 60-1 through the second connection line 80-1 and the first connection line 70-1.
  • the first end of the first connection line 70-2 is connected to the data signal line 60-2 through the first connection hole K1, and the second end of the first connection line 70-2 is extended along the first direction X, and is connected to the first end of the second connection line 80-2 through the second connection hole K2, and the second end of the second connection line 80-2 is extended along the second direction Y to the binding area, and is connected to the first end of the lead line 210-2, and the second end of the lead line 210-2 is extended along the second direction Y and crosses the bending area, and is connected to the driving chip in the driving chip area, thereby realizing the connection of the lead line 210-2 to the data signal line 60-2 through the second connection line 80-2 and the first connection line 70-2.
  • the data signal lines 60-3 to 60-6 extend along the second direction Y to the binding area, they are correspondingly connected to the first ends of the lead lines 210-3 to 210-6, and after the second ends of the lead lines 210-3 to 210-6 extend along the second direction Y and cross the bending area, they are connected to the driving chip in the driving chip area.
  • the pins connected to the lead wires in the driver chip are arranged in an insertion sequence, and the second pin (the pin connected to the lead wire 210-2) is inserted between the third pin (the pin connected to the lead wire 210-3) and the fourth pin (the pin connected to the lead wire 210-4), and the first pin (the pin connected to the lead wire 210-1) is inserted between the fourth pin and the fifth pin (the pin connected to the lead wire 210-5).
  • the driver chip can use the insertion sequence design to achieve load-free data signal output without sudden changes, thereby improving display quality.
  • the insertion sequence design is only one implementation method, and the implementation method of the positive sequence design can be adopted in the actual design.
  • the order of the pin output signals of the driver chip can be consistent with the arrangement order of the data signal lines in the display area through the cross-line design.
  • the intervals between adjacent first connection lines 70 in the second direction Y may be the same or different, and the intervals between adjacent second connection lines 80 in the first direction X may be the same or different, which is not limited in the present disclosure.
  • At least one second connection line 80 may be disposed between two data signal lines 60 adjacent to each other in the first direction X.
  • the present invention provides a data connection line including a first connection line and a second connection line in the display area, so that the lead line of the binding area is connected to the data signal line through the data connection line, so that there is no need to provide a fan-shaped oblique line in the lead area, thereby effectively reducing the length of the lead area, greatly reducing the width of the lower frame, and improving the screen-to-body ratio, which is conducive to achieving full-screen display.
  • the display substrate includes a display area
  • the display area includes a driving structure layer arranged on a substrate
  • the driving structure layer includes at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connection lines extending along a first direction, and a plurality of second connection lines extending along a second direction, wherein the first direction and the second direction intersect
  • the circuit unit includes a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of the plurality of first connection lines are connected to the plurality of data signal lines correspondingly, and the second ends of the plurality of first connection lines are connected to the plurality of second connection lines correspondingly;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the second connecting line, and a minimum distance between the second connecting line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are arranged at gaps between pixel driving circuits of adjacent unit columns.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is greater than a minimum distance between two data signal lines in adjacent unit columns in the first direction.
  • two data signal lines in at least one adjacent unit column are mirror-symmetric with respect to the power line, and a minimum distance between the power line and the adjacent data signal line in the first direction is 1/2 of a minimum distance between two data signal lines in the adjacent unit columns in the first direction.
  • the driving structure layer includes a plurality of conductive layers sequentially arranged on a base, the first connecting line and the second connecting line are arranged in different conductive layers, and the data signal line and the second connecting line are arranged in the same conductive layer.
  • the multiple conductive layers include at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, which are arranged in sequence along a direction away from the substrate, the first connecting line is arranged in the second source-drain metal layer, the data signal line and the second connecting line are arranged in the third source-drain metal layer, the data signal line is connected to the first end of the first connecting line through a via, and the second connecting line is connected to the second end of the first connecting line through a via.
  • the third source-drain metal layer further includes a plurality of power supply wirings extending along the second direction, and the power supply wirings are arranged at gaps between pixel driving circuits of adjacent unit columns.
  • the pixel driving circuit includes at least a storage capacitor and a plurality of transistors
  • the plurality of conductive layers include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer, which are sequentially arranged along a direction away from the substrate;
  • the shielding layer includes at least a shielding electrode
  • the first semiconductor layer includes at least an active layer of a plurality of low-temperature polysilicon transistors
  • the first gate metal layer includes at least a first scanning signal line, a light-emitting signal line and a first electrode plate of the storage capacitor
  • the second gate metal layer includes at least a second electrode plate of the storage capacitor
  • the second semiconductor layer includes at least an active layer of a plurality of oxide transistors
  • the third gate metal layer includes at least a second scanning signal line and a third scanning signal line
  • the plurality of transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the first transistor and the second transistor are oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon transistors.
  • FIG8 is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating a pixel driving circuit structure of eight circuit units (2 unit rows and 4 unit columns) in a display area.
  • the display substrate may include a display area, and the display area may include at least a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate.
  • the driving structure layer may include at least a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of circuit units in each unit row are sequentially arranged along a first direction X, a plurality of unit rows are sequentially arranged along a second direction Y, a plurality of circuit units in each unit column are sequentially arranged along a second direction Y, a plurality of unit columns are sequentially arranged along a first direction X, and the first direction X and the second direction Y intersect.
  • the driving structure layer may also include a plurality of data signal lines 60 extending along the second direction Y, a plurality of first connecting lines 70 extending along the first direction X, and a plurality of second connecting lines 80 extending along the second direction Y
  • the circuit unit may include a pixel driving circuit
  • at least one data signal line 60 is electrically connected to a plurality of pixel driving circuits of a unit column
  • the data signal line 60 is configured to provide a data signal to the connected pixel driving circuit.
  • first ends of the plurality of first connection lines 70 are connected to the plurality of data signal lines 60
  • second ends of the plurality of first connection lines 70 are connected to the plurality of second connection lines 80
  • first connection lines 70 and the second connection lines 80 are configured to provide data signals to the connected data signal lines 60 .
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means “the main part of A extends along direction B".
  • the pixel driving circuits in adjacent unit columns may be mirror-symmetrical with respect to a center line, and the center line may be a straight line located between two adjacent unit columns and extending along the second direction Y.
  • the symmetrical structure forms gaps between the pixel driving circuits of adjacent unit columns, and a plurality of second connecting lines 80 may be respectively disposed in the gaps between the pixel driving circuits of adjacent unit columns.
  • At least one second connection line 80 may be disposed between two data signal lines 60 of adjacent cell columns, and the two data signal lines 60 may be mirror-symmetrical with respect to the second connection line 80 .
  • a minimum distance L1 between at least one second connection line 80 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the driving structure layer may include a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged on the substrate
  • the second source-drain metal layer may include at least a first connecting line 70
  • the third source-drain metal layer may include at least a data signal line 60 and a second connecting line 80, that is, the first connecting line 70 and the second connecting line 80 are arranged in different conductive layers, and the data signal line 60 and the second connecting line 80 are arranged in the same conductive layer.
  • the data signal line 60 can be connected to the first end of the first connection line 70 through the first overlapping via K1
  • the second connection line 80 can be connected to the second end of the first connection line 70 through the second overlapping via K2
  • the second connection line 80 extending along the second direction Y and located in the third source and drain metal layer is connected to the first connection line 70 extending along the first direction X and located in the second source and drain metal layer through the first overlapping via K1
  • the first connection line 70 extending along the first direction X and located in the second source and drain metal layer is connected to the data signal line 60 extending along the second direction Y and located in the third source and drain metal layer through the second overlapping via K2.
  • the driving structure layer may further include a plurality of power supply lines 90 extending along the second direction Y.
  • the plurality of power supply lines 90 may be respectively disposed at gaps between pixel driving circuits of adjacent unit columns.
  • At least one power trace 90 may be disposed between two data signal lines 60 of adjacent cell columns, and the two data signal lines 60 may be mirror-symmetrical with respect to the power trace 90 .
  • a minimum distance L2 between at least one power trace 90 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the power trace 90 may be disposed in the third source-drain metal layer.
  • the pixel driving circuit may include at least a first transistor, a second transistor and a storage capacitor, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, the second region of the first active layer and the first region of the second active layer are interconnected as an integral structure, and are connected to the first electrode plate of the storage capacitor through a first connecting electrode.
  • At least one circuit unit may also include a shielding electrode 63, the orthographic projection of the shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer and the first region of the second active layer on the substrate, and the orthographic projection of the shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode on the substrate.
  • At least one circuit unit may further include a first power line 64 , and the first power line 64 may be connected to the shielding electrode 63 .
  • the shielding electrode 63 may be disposed in the second source-drain metal layer, the first power line 64 may be disposed in the third source-drain metal layer, and the first power line 64 may be connected to the shielding electrode 63 through a via.
  • the pixel driving circuit may include at least a fourth transistor, and the data signal line 60 may be connected to a first electrode of the fourth transistor in the pixel driving circuit through a data connection electrode 61.
  • the first connection line 70 is connected to the data connection electrode 61.
  • At least one circuit unit may further include a data connection block 72 having a first end connected to the first connection line 70 and a second end connected to the data connection electrode 61 .
  • the first connection line 70 , the data connection block 72 and the data connection electrode 61 are disposed in the same layer and are an integrated structure connected to each other.
  • the plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the first transistor and the second transistor being oxide transistors, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor being low-temperature polysilicon transistors.
  • the pixel driving circuit includes at least a storage capacitor and a plurality of transistors
  • the plurality of conductive layers may include a shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer sequentially arranged in a direction away from the substrate.
  • the shielding layer may include at least a shielding electrode
  • the first semiconductor layer may include at least an active layer of a plurality of low-temperature polysilicon transistors
  • the first gate metal layer may include at least a first scanning signal line, a light-emitting signal line, and a first electrode plate of the storage capacitor
  • the second gate metal layer may include at least a second electrode plate of the storage capacitor
  • the second semiconductor layer may include at least an active layer of a plurality of oxide transistors
  • the third gate metal layer may include at least a second scanning signal line and a third scanning signal line
  • the first source-drain metal layer may include at least a second initial signal line of a network connection structure
  • the second source-drain metal layer may include at least a shielding electrode and a first connection line
  • the third source-drain metal layer may include at least a first power supply line, a data signal line, and a second connection line.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the driving structure layer may include the following operations.
  • Forming a blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG. 9 .
  • the shielding layer pattern of each circuit unit may include at least a first shielding connection line 91 , a second shielding connection line 92 , a third shielding connection line 93 , and a shielding electrode 94 .
  • the shape of the shielding electrode 94 may be a rectangle, and the corners of the rectangle may be chamfered.
  • the first shielding connection line 91 may be a straight line extending along the first direction X, and the first shielding connection line 91 may be arranged on one side of the shielding electrode 94 in the first direction X, and connected to the shielding electrode 94.
  • the shape of the second shielding connection line 92 may be a folded line extending along the second direction Y, and the second shielding connection line 92 may be arranged on one side of the shielding electrode 94 in the second direction Y, and connected to the shielding electrode 94.
  • the shape of the third shielding connection line 93 may be a folded line extending along the second direction Y, and the third shielding connection line 93 may be arranged on one side of the shielding electrode 94 in the opposite direction of the second direction Y, and connected to the shielding electrode 94.
  • the first shielding connection line 91 of each circuit unit is connected to the shielding electrode 94 of the circuit unit adjacent in the first direction X, so that the shielding layers in one unit row are connected as one, forming an interconnected integrated structure.
  • the second shielding connection line 92 of each circuit unit is connected to the third shielding connection line 93 of the adjacent circuit unit in the second direction Y, so that the shielding layers in one unit column are connected as a whole to form an interconnected integrated structure.
  • the shielding layers in the unit rows and unit columns are connected as one, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the shielding layers of adjacent unit columns may be mirror-symmetrical with respect to a center line
  • the center line may be a straight line located between adjacent unit columns and extending along the second direction Y.
  • the shielding layer of the Nth column and the shielding layer of the N+1th column may be mirror-symmetrical with respect to the center line
  • the shielding layer of the N+1th column and the shielding layer of the N+2th column may be mirror-symmetrical with respect to the center line
  • the shielding layer of the N+2th column and the shielding layer of the N+3th column may be mirror-symmetrical with respect to the center line.
  • the shapes of the shielding layers in the plurality of cell rows may be substantially the same.
  • forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 10 and 11 , where FIG. 11 is a plan view schematic diagram of the first semiconductor layer in FIG. 10 .
  • the first semiconductor layer pattern of each circuit unit may include at least the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7 , and the third active layer 13 to the seventh active layer 17 are interconnected as an integral structure.
  • the orthographic projection of the third active layer 13 on the substrate at least partially overlaps the orthographic projection of the shielding electrode 94 on the substrate.
  • the sixth active layer 16 may be located on one side of the third active layer 13 in the present circuit unit in the first direction X, and the fourth active layer 14 and the fifth active layer 15 may be located on one side of the third active layer 13 in the present circuit unit in the opposite direction of the first direction X.
  • the fourth active layer 14 in the Mth row of circuit units may be located on the side of the third active layer 13 in the present circuit unit close to the M+1th row of circuit units, and the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 in the Mth row of circuit units may be located on the side of the third active layer 13 in the present circuit unit away from the M+1th row of circuit units, and M may be a positive integer greater than or equal to 1.
  • the third active layer 13 may have an inverted “ ⁇ ” shape
  • the fourth and fifth active layers 14 and 15 may have an “I” shape
  • the sixth and seventh active layers 16 and 17 may have an “L” shape.
  • the third to seventh active layers 13 to 17 may each include a first region, a second region, and a channel region between the first and second regions.
  • the first region 13-1 of the third active layer may simultaneously serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer
  • the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer
  • the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer
  • the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.
  • the first region 17 - 1 of the seventh active layer in the M+1th row circuit unit may be disposed in the Mth row circuit unit.
  • the first regions 15-1 of the fifth active layer in some adjacent two circuit units may be connected to each other.
  • the first region 15-1 of the fifth active layer in the N+1th column and the first region 15-1 of the fifth active layer in the N+2th column are connected to each other. Since the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the first regions of the fifth active layers of adjacent circuit units into an integrated structure connected to each other, it is possible to ensure that the first electrodes of the fifth transistors T5 of the adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the first semiconductor layer of the Nth column and the first semiconductor layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the first semiconductor layer of the N+1th column and the first semiconductor layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the first semiconductor layer of the N+2th column and the first semiconductor layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the first semiconductor layers in the plurality of cell rows may be substantially the same.
  • the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor to the seventh transistor are LTPS transistors.
  • patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, forming a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 12 and 13 , where FIG. 13 is a plan view schematically showing the first conductive layer in FIG. 12 .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit includes at least: a first scanning signal line 21 , a light emitting signal line 22 , and a first electrode plate 23 of a storage capacitor.
  • the shape of the first electrode plate 23 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 23 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode plate 23 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scan signal line 21 can be a line shape in which the main part extends along the first direction X, the first scan signal line 21 in the Mth row circuit unit can be located on the side of the first electrode 23 of the circuit unit close to the M+1th row circuit unit, the area where the first scan signal line 21 in the Mth row circuit unit overlaps with the fourth active layer of the circuit unit serves as the gate electrode of the fourth transistor T4, and the area where the first scan signal line 21 in the Mth row circuit unit overlaps with the seventh active layer in the M+1th row circuit unit serves as the gate electrode of the seventh transistor T7.
  • the shape of the light-emitting signal line 22 can be a line shape in which the main part extends along the first direction X.
  • the light-emitting signal line 22 in the Mth row circuit unit can be located on the side of the first electrode 23 of the circuit unit away from the M+1th row circuit unit.
  • the area where the light-emitting signal line 22 overlaps with the fifth active layer of the circuit unit serves as the gate electrode of the fifth transistor T5
  • the area where the light-emitting signal line 22 overlaps with the sixth active layer of the circuit unit serves as the gate electrode of the sixth transistor T6.
  • the first scanning signal line 21 and the light-emitting signal line 22 can be designed with unequal widths, and the widths of the first scanning signal line 21 and the light-emitting signal line 22 are the dimensions in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.
  • the present disclosure is not limited here.
  • the first scan signal line 21 may include an area overlapping with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the first scan signal line 21 in the area overlapping with the first semiconductor layer may be smaller than the width of the first scan signal line 21 in the area not overlapping with the first semiconductor layer.
  • the light emitting signal line 22 may include an overlapping area with the first semiconductor layer and an non-overlapping area with the first semiconductor layer, and the width of the first scanning signal line 21 in the overlapping area with the first semiconductor layer may be greater than the width of the first scanning signal line 21 in the non-overlapping area with the first semiconductor layer.
  • the first conductive layers of adjacent unit columns may be mirror-symmetric with respect to the center line.
  • the first conductive layer of the Nth column and the first conductive layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the first conductive layer of the N+1th column and the first conductive layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the first conductive layer of the N+2th column and the first conductive layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the first conductive layers in a plurality of unit rows may be substantially the same.
  • the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer.
  • the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the third transistor T3 to the seventh active layer are both conductorized.
  • forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 14 and 15 , where FIG. 15 is a plan view schematic diagram of the second conductive layer in FIG. 14 .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit includes at least a first initial signal line 31 , a second shielding line 32 , a third shielding line 33 , and a second electrode plate 34 of a storage capacitor.
  • the outline of the second electrode plate 34 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second electrode plate 34 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 23 on the substrate.
  • the second electrode plate 34 can serve as another electrode plate of the storage capacitor, and the first electrode plate 23 and the second electrode plate 34 constitute the storage capacitor of the pixel driving circuit.
  • an opening 35 is provided on the second electrode plate 34.
  • the opening 35 may be rectangular and may be located in the middle of the second electrode plate 34, so that the second electrode plate 34 forms a ring structure.
  • the opening 35 exposes the third insulating layer covering the first electrode plate 23, and the orthographic projection of the first electrode plate 23 on the substrate includes the orthographic projection of the opening 35 on the substrate.
  • the opening 35 is configured to accommodate a first via hole formed subsequently.
  • the first via hole is located in the opening 35 and exposes the first electrode plate 23, so that the second electrode of the first transistor T1 formed subsequently is connected to the first electrode plate 23.
  • part of the second plates 34 in two adjacent circuit units in a unit row can be connected to each other.
  • the second plates 34 in the N+1th column and the second plates 34 in the N+2th column are interconnected as an integrated structure.
  • the second plates 34 in each circuit unit are connected to the first power line formed subsequently, by forming the second plates 34 of adjacent circuit units into an integrated structure that is interconnected, the second plates of the integrated structure can be reused as power signal lines, which can ensure that multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the shape of the first initial signal line 31 can be a line shape with the main part extending along the first direction X, and the first initial signal line 31 in the Mth row circuit unit can be located on the side of the second electrode plate 34 of the circuit unit close to the M+1th row circuit unit.
  • the shape of the second shielding line 32 and the third shielding line 33 can be a line shape in which the main part extends along the first direction X, the second shielding line 32 and the third shielding line 33 in the Mth row circuit unit can be located between the first initial signal line 31 and the second electrode plate 34 of the circuit unit, and the second shielding line 32 can be located on the side of the third shielding line 33 away from the second electrode plate 34, that is, the third shielding line 33 can be located between the second shielding line 32 and the second electrode plate 34.
  • the second shielding line 32 is configured to shield the first active layer of the first transistor
  • the third shielding line 33 is configured to shield the second active layer of the second transistor.
  • the second shielding line 32 and the third shielding line 33 can be designed with unequal widths, and the widths of the second shielding line 32 and the third shielding line 33 are the dimensions in the second direction Y, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.
  • the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the second conductive layer of the Nth column and the second conductive layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the second conductive layer of the N+1th column and the second conductive layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the second conductive layer of the N+2th column and the second conductive layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the second conductive layers in a plurality of cell rows may be substantially the same.
  • Forming a second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIGS. 16 and 17 , where FIG. 17 is a plan view schematic diagram of the second semiconductor layer in FIG. 16 .
  • the second semiconductor layer pattern of each circuit unit includes at least a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2 .
  • the first active layer 11 and the second active layer 12 may be shaped like an "I", and the first active layer 11 in the Mth row of circuit units may be located on a side of the second active layer 12 of the circuit unit close to the M+1th row of circuit units.
  • the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 32 on the substrate, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the third shielding line 33 on the substrate.
  • the first active layer 11 and the second active layer 12 may each include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer may be located on a side of the second shielding line 32 away from the second active layer 12, and the second region 11-2 of the first active layer may be located on a side of the second shielding line 32 close to the second active layer 12.
  • the first region 12-1 of the second active layer may be located on a side of the third shielding line 33 away from the first active layer 11, and the second region 12-2 of the second active layer may be located on a side of the third shielding line 33 close to the first active layer 11.
  • the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer, that is, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer are an interconnected integral structure and can be located between the second shielding line 32 and the third shielding line 33.
  • the orthographic projections of the second region 11 - 2 of the first active layer and the first region 12 - 1 of the second active layer of the integrated structure on the substrate at least partially overlap with the orthographic projection of the first scan signal line 21 in the present circuit unit on the substrate.
  • the second semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the second semiconductor layer of the Nth column and the second semiconductor layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the second semiconductor layer of the N+1th column and the second semiconductor layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the second semiconductor layer of the N+2th column and the second semiconductor layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the second semiconductor layers in a plurality of cell rows may be substantially the same.
  • the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors.
  • the second semiconductor film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.
  • forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 18 and 19 , where FIG. 19 is a plan view schematically showing the third conductive layer in FIG. 18 .
  • the second conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer pattern of each circuit unit includes at least a second scan signal line 41 and a third scan signal line 42 .
  • the shape of the second scan signal line 41 and the third scan signal line 42 can be a line shape in which the main part extends along the first direction X, the second scan signal line 41 and the third scan signal line 42 in the Mth row circuit unit can be located between the first initial signal line 31 and the second electrode plate 34 of the circuit unit, and the second scan signal line 41 can be located on the side of the third scan signal line 42 away from the second electrode plate 34, that is, the third scan signal line 42 can be located between the second scan signal line 41 and the second electrode plate 34.
  • the region where the second scan signal line 41 overlaps the first active layer serves as the gate electrode of the first transistor T1
  • the region where the third scan signal line 42 overlaps the second active layer serves as the gate electrode of the second transistor T2 .
  • the orthographic projection of the second scanning signal line 41 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 32 on the substrate, and the second shielding line 32 and the second scanning signal line 41 can be connected to the same signal source, so that the second shielding line 32 can serve as the bottom gate electrode of the first transistor T1, and the second scanning signal line 41 can serve as the top gate electrode of the first transistor T1, forming a first transistor T1 with a dual-gate structure.
  • the orthographic projection of the third scanning signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third shielding line 33 on the substrate, and the third shielding line 33 and the third scanning signal line 42 can be connected to the same signal source, so that the third shielding line 33 can serve as the bottom gate electrode of the second transistor T2, and the third scanning signal line 42 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a dual-gate structure.
  • the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to the center line.
  • the third conductive layer of the Nth column and the third conductive layer of the N+1th column may be mirror-symmetric with respect to the center line
  • the third conductive layer of the N+1th column and the third conductive layer of the N+2th column may be mirror-symmetric with respect to the center line
  • the third conductive layer of the N+2th column and the third conductive layer of the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the third conductive layers in a plurality of cell rows may be substantially the same.
  • Forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of vias are disposed on the sixth insulating layer, as shown in FIG. 20 .
  • the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10 and an eleventh via V11.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 35 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 23, and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 23 through the via hole.
  • the second via hole V2 is located within the range of the positive projection of the second electrode plate 34 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second electrode plate 34, and the second via hole V2 is configured to connect the subsequently formed fourth connecting electrode to the second electrode plate 34 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the fifth active layer, and the third via hole V3 is configured to connect a subsequently formed fourth connecting electrode to the first area of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the fourth via hole V4 is configured to connect a subsequently formed sixth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of the third active layer (also the first area of the sixth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of the third active layer (also the first area of the sixth active layer), and the sixth via hole V6 is configured to connect a subsequently formed fifth connecting electrode to the second area of the third active layer (also the first area of the sixth active layer) through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of the seventh active layer, and the seventh via hole V7 is configured to connect a subsequently formed second initial signal line to the first area of the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the first active layer, and the eighth via hole V8 is configured to connect a subsequently formed second connecting electrode to the first region of the first active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the ninth via hole V9 are etched away to expose the surface of the second region of the second active layer, and the ninth via hole V9 is configured to connect a subsequently formed fifth connecting electrode to the second region of the second active layer through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the tenth via hole V10 are etched away to expose the surface of the second area of the first active layer (also the first area of the second active layer), and the tenth via hole V10 is configured to connect a subsequently formed first connecting electrode to the second area of the first active layer (also the first area of the second active layer) through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first initial signal line 31, and the eleventh via hole V11 is configured to connect a subsequently formed second connecting electrode to the first initial signal line 31 through the via hole.
  • the plurality of vias in adjacent unit columns may be mirror-symmetric with respect to the center line.
  • the plurality of vias in the Nth column and the plurality of vias in the N+1th column may be mirror-symmetric with respect to the center line
  • the plurality of vias in the N+1th column and the plurality of vias in the N+2th column may be mirror-symmetric with respect to the center line
  • the plurality of vias in the N+2th column and the plurality of vias in the N+3th column may be mirror-symmetric with respect to the center line.
  • the shapes of the plurality of vias in the plurality of unit rows may be substantially the same.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 21 and 22 , where FIG. 22 is a plan view of the fourth conductive layer in FIG. 21 .
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a second initial signal line 57 and a second initial connection line 58.
  • the shape of the first connection electrode 51 may be a zigzag shape in which the main part extends along the second direction Y.
  • the first end of the first connection electrode 51 is connected to the first electrode plate 23 through the first via hole V1.
  • the second region of the first active layer also the first region of the second active layer
  • the first connection electrode 51 may simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2 (the second node N2 of the pixel driving circuit).
  • the second connection electrode 52 may be in the shape of a strip extending along the first direction X, a first end of the second connection electrode 52 is connected to the first region of the first active layer through an eighth via hole V8, and a second end of the second connection electrode 52 is connected to the first initial signal line 31 through an eleventh via hole V11, so that the first initial voltage transmitted by the first initial signal line 31 is written into the first electrode of the first transistor T1.
  • the second connection electrode 52 may serve as the first electrode of the first transistor T1.
  • the second connection electrode 52 of the Nth column and the second connection electrode 52 of the N+1th column may be an interconnected integral structure
  • the second connection electrode 52 of the N+2th column and the second connection electrode 52 of the N+3th column may be an interconnected integral structure
  • the shape of the third connection electrode 53 may be rectangular, and the third connection electrode 53 is connected to the first region of the fourth active layer through the fifth via hole V5.
  • the third connection electrode 53 may serve as a first electrode of the fourth transistor T4, and the third connection electrode 53 is configured to be connected to an eleventh connection electrode formed subsequently.
  • the fourth connection electrode 54 may be in a "Y" shape, the first end of the fourth connection electrode 54 is connected to the second electrode plate 34 through the second via hole V2, and the second end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the third via hole V3, thereby achieving the same potential for the first electrode of the fifth transistor T5 and the second electrode plate 34 of the storage capacitor in the circuit unit.
  • the fourth connection electrode 54 may serve as the first electrode of the fifth transistor T5, and the fourth connection electrode 54 is configured to be connected to a shielding electrode formed subsequently.
  • the fourth connection electrode 54 in the N+1th column and the fourth connection electrode 54 in the N+2th column may be an integrated structure connected to each other.
  • the fourth connection electrode 54 in each circuit unit is connected to the first power line formed subsequently, by forming the fourth connection electrodes 54 of adjacent circuit units into an integrated structure connected to each other, it is possible to ensure that the fourth connection electrodes 54 of adjacent circuit units have the same potential, thereby making the first electrodes of the fifth transistors T5 in the adjacent circuit units have the same potential, and the second electrodes 34 of the storage capacitors in the adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the orthographic projection of the fourth connection electrode 54 on the substrate at least partially overlaps with the orthographic projection of the second region of the seventh active layer on the substrate, and the fourth connection electrode 54 with a constant potential can play a shielding role to ensure the potential stability of key nodes in the pixel driving circuit.
  • the shape of the fifth connection electrode 55 may be rectangular, a first end of the fifth connection electrode 55 is connected to the second region of the third active layer (also the first region of the sixth active layer) through a sixth via hole V6, and a second end of the fifth connection electrode 55 is connected to the second region of the second active layer through a ninth via hole V9.
  • the fifth connection electrode 55 may simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 (the third node N3 of the pixel driving circuit).
  • the shape of the sixth connection electrode 56 may be polygonal, and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4.
  • the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to a twelfth connection electrode formed subsequently.
  • the second initial signal line 57 may be in the shape of a zigzag line with a main portion extending along the first direction X.
  • the second initial signal line 57 in the Mth row of circuit units may be disposed on a side of the storage capacitor close to the M+1th row of circuit units.
  • the second initial signal line 57 in the Mth row of circuit units is connected to the first region of the seventh active layer in the M+1th row of circuit units through the seventh via hole V7, so that the second initial voltage transmitted by the second initial signal line 57 is written into the first electrode of the seventh transistor T7.
  • the second initial signal line 57 is connected to the first region of all the seventh active layers in a unit row, it can be ensured that the first electrodes of all the seventh transistors T7 in a unit row have the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second initial connection line 58 may be in the shape of a zigzag line with the main part extending along the second direction Y.
  • the second initial connection line 58 may be disposed between two second initial signal lines 57 adjacent to each other in the second direction Y, and respectively connected to the two second initial signal lines 57.
  • the second initial signal lines 57 extending along the first direction X and the second initial connection lines 58 extending along the second direction Y form initial signal lines of a network connection structure in the display area, which not only can minimize the resistance of the initial signal lines, reduce the voltage drop of the initial voltage, effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the uniformity within the signal plane, and effectively improve the display uniformity, but also make the potential of the fourth node (anode) of the pixel driving circuit more uniform in the reset stage, and the light-emitting device lighting speed is easier to keep consistent, thereby improving the display quality and display quality.
  • the second initial connection line 58 may be disposed in odd-numbered cell columns, or may be disposed in even-numbered cell columns, that is, one second initial connection line 58 may be disposed in two cell columns.
  • the cell column where the second initial connection line 58 in one cell row is located is different from the cell column where the second initial connection line 58 in the other cell row is located.
  • the second initial connection line 58 respectively connecting the second initial signal line 57 in the M-1th row and the second initial signal line 57 in the Mth row may be located in the circuit unit of the Nth column
  • the second initial connection line 58 respectively connecting the second initial signal line 57 in the Mth row and the second initial signal line 57 in the M+1th row may be located in the circuit unit of the N+2th column.
  • the second preliminary signal line 57 and the second preliminary connection line 58 are simultaneously formed through the same patterning process and are an integral structure connected to each other.
  • first to sixth connection electrodes 51 to 56 and the second initial signal line 57 of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the shapes of the first to sixth connection electrodes 51 to 56 and the second initial signal line 57 in a plurality of cell rows may be substantially the same.
  • Forming a first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are disposed on the first planar layer, as shown in FIG. 23 .
  • the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connecting electrode 53, and the twenty-first via hole V21 is configured to connect the subsequently formed eleventh connecting electrode to the third connecting electrode 53 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-second via hole V22 is configured to connect the subsequently formed twelfth connecting electrode to the sixth connecting electrode 56 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the fourth connecting electrode 54, and the twenty-third via hole V232 is configured to connect a subsequently formed shielding electrode to the fourth connecting electrode 54 through the via hole.
  • the plurality of vias on the first planar layer of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the plurality of vias on the first planar layer in the plurality of cell rows may have substantially the same shape.
  • forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first flat layer, as shown in FIGS. 24 and 25 , where FIG. 25 is a plan view of the fifth conductive layer in FIG. 24 .
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the fifth conductive layer of each circuit unit includes at least an eleventh connecting electrode 61 , a twelfth connecting electrode 62 , and a shielding electrode 63 .
  • the shape of the eleventh connection electrode 61 can be a strip shape with the main part extending along the second direction Y.
  • the eleventh connection electrode 61 is connected to the third connection electrode 53 through the twenty-first via hole V21.
  • the eleventh connection electrode 61 is configured to be connected to a subsequently formed data signal line.
  • the eleventh connection electrode 61 can be called a data connection electrode.
  • the shape of the twelfth connection electrode 62 may be polygonal, the twelfth connection electrode 62 is connected to the sixth connection electrode 56 through the twelfth via hole V22, and the twelfth connection electrode 62 is configured to be connected to the subsequently formed anode connection electrode.
  • the shielding electrode 63 may be in a block shape with a main portion extending along the second direction Y.
  • the shielding electrode 63 is connected to the fourth connection electrode 54 through the twenty-third via hole V23 and is configured to be connected to a first power line formed subsequently.
  • the shielding electrode 63 may include a shielding main body portion 63-1 and a shielding connection portion 63-2.
  • the shielding main body portion 63-1 may be rectangular in shape, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the shielding main body portion 63-1 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate, and the orthographic projection of the shielding main body portion 63-1 on the substrate at least partially overlaps with the orthographic projection of the second area of the first active layer and the first area of the second active layer on the substrate.
  • the shielding connection portion 63-2 may be in the shape of a strip extending along the second direction Y, the first end of the shielding connection portion 63-2 is connected to the shielding main body portion 63-1, and the second end of the shielding connection portion 63-2 is extended in a direction away from the shielding main body portion 63-1, and is connected to the fourth connection electrode 54 through the twenty-third via hole V23, and the orthographic projection of the shielding connection portion 63-2 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate.
  • the shielding electrode 63 since the shielding electrode 63 completely blocks the second region of the first active layer and the first region of the second active layer, the shielding electrode 63 can block the light emission of the light emitting device and the reflected light of the film layer from irradiating the oxide transistor, and can prevent the characteristic drift of the oxide transistor due to light, thereby improving the electrical characteristics of the oxide transistor.
  • the shielding electrode 63 Since the shielding electrode 63 is connected to the first power line formed later, the shielding electrode 63 with a constant potential can not only effectively shield the influence of the data voltage jump and other signals on the second node N2 in the pixel driving circuit, avoid the influence of the data voltage jump and other signals on the potential of the second node N2, effectively avoid the deterioration of crosstalk, but also avoid the display difference caused by the fact that some circuit units are provided with the second connection line while some circuit units are not provided with the second connection line, thereby improving the display effect.
  • the fourth conductive layer may further include a first connection line 70 , a first bonding block 71 , and a data connection block 72 .
  • the shape of the first connection line 70 can be a zigzag line with the main part extending along the first direction X.
  • the first connection line 70 of the Mth row circuit unit can be arranged on the side of the shielding electrode 63 close to the M+1th row circuit unit, and the first connection line 70 is configured as a horizontal line in the data connection line.
  • a break may be provided on the first connection line 70, and the first connection line 70 on one side of the break serves as a lateral line in the data connection line, and the first connection line 70 on the other side of the break serves as a dummy line to ensure etching uniformity of the display substrate.
  • the first bridge block 71 may be in a polygonal shape, located between adjacent unit columns, and connected to the first connection line 70.
  • the first bridge block 71 may be disposed between the Nth column and the N+1th column, and the first bridge block 71 may be disposed between the N+2th column and the N+3th column.
  • a portion of the first bridge block 71 is configured to be connected to a second connection line formed subsequently, and another portion of the first bridge block 71 is used as a dummy bridge structure to ensure etching uniformity of the display substrate.
  • the data connection block 72 may be in a bar shape extending along the second direction Y, a first end of the data connection block 72 is connected to the first connection line 70 , and a second end of the data connection block 72 is connected to the third connection electrode 53 .
  • the first connection line 70 , the first bonding block 71 , and the data connection block 72 may be simultaneously formed by a same patterning process and are an integrated structure connected to each other.
  • the eleventh connection electrode 61, the twelfth connection electrode 62 and the shielding electrode 63 of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the shapes of the eleventh connection electrode 61, the twelfth connection electrode 62 and the shielding electrode 63 in a plurality of cell rows may be substantially the same.
  • Forming a second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are disposed on the second planar layer, as shown in FIG. 26 .
  • the plurality of vias in each circuit unit includes at least a thirty-first via V31 , a thirty-second via V32 , and a thirty-third via V33 .
  • the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the eleventh connection electrode 61 on the substrate, the second flat layer in the thirty-first via hole V31 is etched away, exposing the surface of the eleventh connection electrode 61, and the thirty-first via hole V31 is configured to allow a subsequently formed data signal line to be connected to the eleventh connection electrode 61 through the via hole.
  • the thirty-first via hole V31 on the eleventh connection electrode 61 (data connection electrode) connected to the first connection line 70 can be referred to as a first lap via hole.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 62 on the substrate, the second flat layer in the thirty-second via hole V32 is etched away to expose the surface of the twelfth connecting electrode 62, and the thirty-second via hole V32 is configured to connect a subsequently formed anode connecting electrode to the twelfth connecting electrode 62 through the via hole.
  • the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the shielding connection portion 63-2 in the shielding electrode 63 on the substrate, the second flat layer in the thirty-third via V33 is etched away to expose the surface of the shielding connection portion 63-2, and the thirty-third via V33 is configured to connect a subsequently formed first power line to the shielding electrode 63 through the via.
  • the plurality of vias on the second flat layer may further include a thirty-fourth via V34.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the first lap block 71 on the substrate, the second flat layer in the thirty-fourth via V34 is etched away, exposing the surface of the first lap block 71, and the thirty-fourth via V34 is configured to allow a second connecting line formed subsequently to be connected to the first connecting line 70 through the via.
  • the thirty-fourth via V34 is provided on part of the first lap block 71, and the thirty-fourth via V34 may be referred to as a second lap via.
  • the thirty-first via V31, the thirty-second via V32, and the thirty-third via V33 of adjacent unit columns may be mirror-symmetric with respect to the center line.
  • the shapes of the thirty-first via V31, the thirty-second via V32, and the thirty-third via V33 in multiple unit rows may be substantially the same.
  • forming the sixth conductive layer may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the sixth conductive film using a patterning process, and forming a sixth conductive layer disposed on the second flat layer, as shown in FIGS. 27 and 28 , where FIG. 28 is a plan view of the sixth conductive layer in FIG. 27 .
  • the sixth conductive layer may be referred to as a third source-drain metal (SD3) layer.
  • the sixth conductive layer of each circuit unit includes at least a data signal line 60 , a first power line 64 , and an anode connection electrode 65 .
  • the data signal line 60 may be in the shape of a line whose main body portion extends along the second direction Y, and the data signal line 60 is connected to the eleventh connection electrode 61 through the thirty-first via hole V31. Since the eleventh connection electrode 61 is connected to the third connection electrode 53 through the via hole, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 60 is connected to the first electrode of the fourth transistor T4, and the data signal line 60 can write the data signal to the first electrode of the fourth transistor T4.
  • the data signal line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first and second planar layers, the distance between the data signal line and the corresponding signal line is increased, and the parasitic capacitance between the data signal line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the data signal line.
  • SD3 source-drain metal
  • the first power line 64 may be in the shape of a zigzag line with a main body extending along the second direction Y, and the first power line 64 is connected to the shielding connection portion 63-2 of the shielding electrode 63 through the thirty-third via hole V33.
  • the shielding electrode 63 is connected to the fourth connection electrode 54 through the via hole, and the fourth connection electrode 54 is connected to the first region and the second electrode plate 34 of the fifth active layer through the via hole, the connection between the first power line 64 and the first electrode and the second electrode plate 34 of the fifth transistor T5 is realized, and the first power line 64 can write a power signal to the first electrode of the fifth transistor T5, and the first electrode of the fifth transistor T5 and the second electrode plate 34 of the storage capacitor have the same potential.
  • the first power line 64 may be a zigzag line of unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.
  • the shape of the anode connection electrode 65 may be polygonal, and the anode connection electrode 65 is connected to the twelfth connection electrode 62 through the thirty-second via hole V32, and the anode connection electrode 65 is configured to be connected to the subsequently formed anode. Since the twelfth connection electrode 62 is connected to the sixth connection electrode 56 through the via hole, and the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.
  • the sixth conductive layer may further include a second connection line 80 , a second strapping block 81 , and a power trace 90 .
  • the second connection line 80 may be in the shape of a line whose main part extends along the second direction Y, and may be located at the gap between the pixel driving circuits of adjacent unit columns, and the second connection line 80 is connected to the first bridge block 71 through the thirty-fourth via hole V34. Since the first bridge block 71 is connected to the first connection line 70, the connection between the second connection line 80 and the first connection line 70 is achieved. Since the first connection line 70 is connected to the eleventh connection electrode 61 through the data connection block 72, and the eleventh connection electrode 61 is connected to the data signal line 60 through the via hole, the data signal line 60, the first connection line 70, and the second connection line 80 are sequentially connected.
  • the second overlap block 81 may be in a polygonal shape, located between adjacent unit columns, and aligned with the second connection line 80.
  • the second overlap block 81 may be disposed between the Nth column and the N+1th column, and the second overlap block 81 may be disposed between the N+2th column and the N+3th column.
  • the orthographic projection of the second overlap block 81 on the substrate at least partially overlaps the orthographic projection of the first overlap block 71 on the substrate, a portion of the second overlap block 81 is connected to the first overlap block 71 through the thirty-fourth via hole V34, and another portion of the second overlap block 81 serves as a dummy overlap structure to ensure etching uniformity of the display substrate.
  • the pixel driving circuit of the display area adopts a mirror-symmetrical structure
  • the pixel driving circuits of adjacent unit columns are mirror-symmetrical. Therefore, when the size of the circuit unit remains unchanged, a gap can be formed between the pixel driving circuits of adjacent unit columns through central compression, so that the second connecting line extending longitudinally in the display area can be set at the gap between the adjacent pixel driving circuits, thereby maximizing the distance between the second connecting line and the data signal line and minimizing the interference caused by capacitive coupling between the second connecting line and the data signal line.
  • At least one second connection line 80 may be disposed between two data signal lines 60 of adjacent cell columns, the two data signal lines 60 may be mirror-symmetrical with respect to the center line, and the two data signal lines 60 may be mirror-symmetrical with respect to the second connection line 80 .
  • a minimum distance L1 between at least one second connection line 80 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the second connecting line is arranged in the third source-drain metal (SD3) layer and is separated from the corresponding signal line by the thicker first flat layer and the second flat layer, the distance between the second connecting line and the corresponding signal line is increased, and the parasitic capacitance between the second connecting line and the corresponding signal line is reduced, thereby effectively reducing the capacitive load of the second connecting line.
  • SD3 third source-drain metal
  • the first connecting line is arranged in the second source-drain metal (SD2) layer and the second connecting line is arranged in the third source-drain metal (SD3) layer, the first connecting line and the second connecting line only need one flat layer via to be connected, thereby minimizing the occupied space and facilitating the realization of high-resolution display.
  • SD2 second source-drain metal
  • SD3 third source-drain metal
  • the power supply line 90 may be in the shape of a line whose main part extends along the second direction Y, and is located between some adjacent unit columns. Between at least one unit column, only the power supply line 90 may be provided, and no second connection line 80 may be provided. Between at least one unit column, the second connection line 80 and the power supply line 90 may be provided, respectively, and the power supply line 90 and the second connection line 80 may be located on the same straight line extending along the second direction Y, and a break is provided between the power supply line 90 and the second connection line 80, and the break is configured to achieve insulation between the power supply line 90 and the second connection line 80.
  • At least one power trace 90 may be disposed between two data signal lines 60 of adjacent cell columns, and the two data signal lines 60 may be mirror-symmetrical with respect to the power trace 90 .
  • a minimum distance L2 between at least one power trace 90 and an adjacent data signal line 60 in the first direction X may be greater than a minimum distance L3 between two data signal lines 60 in adjacent cell columns in the first direction X.
  • the plurality of power lines 90 may be lines that continuously provide low voltage signals.
  • the power line may be a second power line VSS.
  • the plurality of power lines 90 may be connected to power leads provided in a binding area or a frame area.
  • the present disclosure realizes a structure in which a low voltage power line is provided in a sub-pixel (VSS in pixel) by providing a power line in the display area, which can not only effectively reduce the resistance of the power signal line, effectively reduce the voltage drop of the low voltage power signal, and achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the low voltage power line provided in the sub-pixel structure can greatly reduce the width of the power lead in the frame area and the binding area, which is conducive to achieving a narrow frame.
  • the data signal lines 60, first power lines 64 and anode connection electrodes 65 of adjacent cell columns may be mirror-symmetrical with respect to the center line.
  • the shapes of the data signal lines 60, first power lines 64 and anode connection electrodes 65 in a plurality of cell rows may be substantially the same.
  • forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of vias are disposed on the third planar layer, as shown in FIG. 29 .
  • the vias of each circuit unit include at least an anode via V40.
  • the orthographic projection of the anode via V40 on the substrate is within the range of the orthographic projection of the anode connection electrode 65 on the substrate, the third flat layer in the anode via V40 is removed, exposing the surface of the anode connection electrode 65, and the anode via V40 is configured to connect a subsequently formed anode to the anode connection electrode 65 through the via.
  • the drive structure layer is prepared on the substrate.
  • the drive structure layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel drive circuit.
  • the drive structure layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer sequentially arranged on the substrate.
  • the blocking layer may include at least a blocking electrode
  • the first semiconductor layer may include at least an active layer of a third transistor to a seventh transistor
  • the first conductive layer may include at least a first scanning signal line, a light-emitting signal line and a first electrode plate of a storage capacitor
  • the second conductive layer may include at least a first initial signal line and a second electrode plate of a storage capacitor
  • the second semiconductor layer may include at least an active layer of a first transistor to a second transistor
  • the third conductive layer may include at least a second scanning signal line and a third scanning signal line
  • the fourth conductive layer may include at least a second initial signal line, a second initial connecting line and a plurality of connecting electrodes
  • the fifth conductive layer may include at least a shielding electrode and a first connecting line
  • the sixth conductive layer may include at least a data signal line, a first power line, a second power line and a second connecting line.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called a gate insulating (GI) layer
  • the sixth insulating layer may be called an interlayer insulating (ILD) layer.
  • the first planar layer, the second planar layer and the third planar layer may be made of organic materials, such as resin, etc.
  • the pixel driving circuits in two adjacent circuit units in one unit row may be substantially mirror-symmetrical with respect to a center line, where the center line is a straight line located between the two adjacent circuit units and extending along the second direction Y.
  • the pixel driving circuits in the Nth column and the pixel driving circuits in the N+1th column may be mirror-symmetrical with respect to the center line.
  • the pixel driving circuits in the N+1th column and the pixel driving circuits in the N+2th column may be mirror-symmetrical with respect to the center line.
  • the pixel driving circuits in two adjacent circuit units may be substantially mirror-symmetrical with respect to a center line and may include any one or more of the following: the first semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, the first conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, the second conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, the second semiconductor layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line, and the third conductive layer in two adjacent circuit units in a unit row may be mirror-symmetrical with respect to the center line.
  • a light-emitting structure layer is prepared on the driving structure layer, and the preparation process of the light-emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the third flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, as shown in FIG. 30 .
  • the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the plurality of anode patterns may include a first anode 90A located at a red light emitting unit emitting red light, a second anode 90B located at a blue light emitting unit emitting blue light, a third anode 90C located at a first green light emitting unit emitting green light, and a fourth anode 90D located at a second green light emitting unit emitting green light.
  • the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be connected to the anode connection electrode 65 of the circuit unit through the anode via hole V40 , respectively.
  • At least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting part that are connected to each other.
  • the shape of the anode main body may be rectangular, and the corners of the rectangle may be provided with arc-shaped chamfers.
  • the shape of the anode connecting part may be strip-shaped, and the first end of the anode connecting part is connected to the anode main body, and the second end of the anode connecting part extends in a direction away from the anode main body and is connected to the anode connecting electrode 65 through the anode via V40.
  • the orthographic projections of the first anode, the second anode, the third anode and the fourth anode on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projections of the first anode and the second anode on the substrate at least partially overlap with the orthographic projection of the shielding electrode on the substrate.
  • the orthographic projection of the first anode on the substrate and the orthographic projection of the first power line on the substrate have a first overlapping area
  • the orthographic projection of the first anode on the substrate and the orthographic projection of the shielding electrode on the substrate have a second overlapping area
  • the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the orthographic projection of the second anode on the substrate and the orthographic projection of the first power line on the substrate have a first overlapping area
  • the orthographic projection of the second anode on the substrate and the orthographic projection of the shielding electrode on the substrate have a second overlapping area
  • the area of the first overlapping area is smaller than the area of the second overlapping area.
  • the present disclosure effectively reduces the overlapping area of the first anode and the second anode with the first power line by setting the shielding electrode on the second source-drain metal layer SD2 and the first power line on the third source-drain metal layer SD3, effectively reduces the parasitic capacitance of the fourth node N4 of the pixel driving circuit, and improves the lighting speed of the light-emitting device.
  • forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, patterning the pixel definition film using a patterning process to form a pixel definition layer covering the anode conductive layer pattern, wherein a plurality of pixel openings 90E are provided on the pixel definition layer, and the pixel definition film in the pixel openings 90E is removed to expose the surfaces of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D, respectively, as shown in FIG. 31 .
  • the subsequent preparation process may include: first forming an organic light-emitting layer by evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a packaging structure layer
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of organic materials
  • the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • the display substrate provided by the exemplary embodiment of the present disclosure, by setting the data connection line in the display area, the lead line of the binding area is connected to the data signal line through the data connection line, so that the fan-shaped oblique line does not need to be set in the lead area, effectively reducing the length of the lead area, greatly reducing the width of the lower frame, and improving the screen ratio, which is conducive to the realization of full-screen display.
  • the present disclosure sets the first connection line in the second source and drain metal layer, and the second connection line is set in the third source and drain metal layer, so that the first connection line and the second connection line only need a flat layer via to achieve connection, which minimizes the occupied space, is conducive to the realization of high-resolution display, and can increase the resolution (PPI) of the LTPO display substrate to 480 while realizing a narrow frame.
  • the present disclosure sets the data signal line and the second connection line in the third source and drain metal layer, increases the distance between the data signal line and the second connection line and the corresponding signal line, reduces the parasitic capacitance between the data signal line and the second connection line and the corresponding signal line, and thus effectively reduces the capacitive load of the data signal line and the second connection line.
  • the present disclosure adopts the mirror symmetry and center compression of the pixel driving circuit, sets the second connection line at the gap between the adjacent unit columns, maximizes the distance between the second connection line and the data signal line, and minimizes the interference caused by capacitive coupling between the second connection line and the data signal line.
  • the present disclosure sets a shielding electrode in the second source-drain metal layer.
  • the shielding electrode can block the light emission of the light-emitting device and the reflected light of the film layer from irradiating the oxide transistor, which can prevent the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.
  • the shielding electrode can effectively shield the influence of data voltage jump and other signals on the second node N2 in the pixel driving circuit, thereby avoiding the influence of data voltage jump and other signals on the potential of the second node N2, effectively avoiding the deterioration of crosstalk, and avoiding the display difference caused by the fact that some circuit units are set with the second connection line while some circuit units are not set with the second connection line, thereby improving the display effect.
  • the present disclosure forms a second initial signal line with a network connection structure in the display area, which can not only minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the uniformity in the signal surface, and effectively improve the display uniformity, but also make the potential of the fourth node (anode) of the pixel driving circuit in the reset stage more uniform, and the light-emitting device lighting speed is easier to keep consistent, thereby improving the display quality and display quality.
  • the present disclosure effectively reduces the overlapping area of the anode and the first power line by setting the shielding electrode in the second source and drain metal layer and the first power line in the third source and drain metal layer, effectively reduces the parasitic capacitance of the fourth node N4 of the pixel driving circuit, and improves the lighting speed of the light-emitting device.
  • the present disclosure realizes the structure of VSS in pixel by setting the power line in the display area, which can greatly reduce the width of the frame power lead, greatly reduce the width of the left and right frame, improve the screen ratio, and facilitate the realization of full-screen display.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.
  • FIG32 is a schematic diagram of a planar structure of another display substrate of the embodiment of the present disclosure.
  • the main structure of the display substrate of the present exemplary embodiment is substantially similar to the main structure of the display substrate of the aforementioned embodiment, except that the minimum distance L1 between at least one second connection line 80 and an adjacent data signal line 60 in the first direction X can be approximately 1/2 of the minimum distance L3 between two data signal lines 60 in adjacent unit columns in the first direction X, and the minimum distance L2 between at least one power supply line 90 and an adjacent data signal line 60 in the first direction X can be approximately 1/2 of the minimum distance L3 between two data signal lines 60 in adjacent unit columns in the first direction X.
  • the second connection line 80 in the display substrate shown in FIG8 is arranged between two data signal lines 60 with a larger spacing in adjacent unit columns
  • the second connection line 80 in the display substrate shown in FIG32 is arranged between two data signal lines 60 with a smaller spacing in adjacent unit columns.
  • the structure and preparation process shown above in the present disclosure are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.
  • the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.
  • the present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment.
  • the display substrate includes a display area
  • the preparation method includes:
  • a driving structure layer is formed on the substrate of the display area, the driving structure layer at least comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction and a plurality of second connecting lines extending along a second direction, wherein the first direction intersects with the second direction;
  • the circuit unit comprises a pixel driving circuit, at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, first ends of a plurality of first connecting lines are connected to a plurality of data signal lines correspondingly, and second ends of a plurality of first connecting lines are connected to a plurality of second connecting lines correspondingly;
  • the pixel driving circuits in adjacent unit columns are mirror-symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and extending along the second direction, and the second connecting lines are arranged at gaps

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线（60）、多条沿着第一方向延伸的第一连接线（70）和多条沿着第二方向延伸的第二连接线（80）；电路单元包括像素驱动电路，至少一条数据信号线（60）与一个单元列的多个像素驱动电路连接，多条第一连接线（70）的第一端与多条数据信号线（60）对应连接，多条第一连接线（70）的第二端与多条第二连接线（80）对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，第二连接线（80）设置在相邻单元列的像素驱动电路之间的间隙处。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域，所述显示区域包括设置在基底上的驱动结构层，所述驱动结构层至少包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、多条沿着第一方向延伸的第一连接线和多条沿着第二方向延伸的第二连接线，所述第一方向和所述第二方向交叉；所述电路单元包括像素驱动电路，至少一条数据信号线与一个单元列的多个像素驱动电路连接，多条第一连接线的第一端与多条数据信号线对应连接，多条第一连接线的第二端与多条第二连接线对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，所述中心线是位于相邻单元列之间且沿着所述第二方向延伸的直线，所述第二连接线设置在相邻单元列的像素驱动电路之间的间隙处。
在示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于 所述第二连接线镜像对称，所述第二连接线与相邻的数据信号线在所述第一方向上的最小距离，大于相邻单元列中两条数据信号线在所述第一方向上的最小距离。
在示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述第二连接线镜像对称，所述第二连接线与相邻的数据信号线在所述第一方向上的最小距离，为相邻单元列中两条数据信号线在所述第一方向上的最小距离的1/2。
在示例性实施方式中，所述驱动结构层还包括多条沿着所述第二方向延伸的电源走线，所述电源走线设置在相邻单元列的像素驱动电路之间的间隙处。
在示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述电源走线镜像对称，所述电源走线与相邻的数据信号线在所述第一方向上的最小距离，大于相邻单元列中两条数据信号线在所述第一方向上的最小距离。
在示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述电源走线镜像对称，所述电源走线与相邻的数据信号线在所述第一方向上的最小距离，为相邻单元列中两条数据信号线在所述第一方向上的最小距离的1/2。
在示例性实施方式中，在垂直于显示基板的平面上，所述驱动结构层包括在基底上依次设置的多个导电层，所述第一连接线和第二连接线设置在不同的导电层中，所述数据信号线和所述第二连接线设置在相同的导电层中。
在示例性实施方式中，所述多个导电层至少包括沿着远离所述基底的方向依次设置的第一源漏金属层、第二源漏金属层和第三源漏金属层，所述第一连接线设置在所述第二源漏金属层中，所述数据信号线和所述第二连接线设置在所述第三源漏金属层中，所述数据信号线通过过孔与所述第一连接线的第一端连接，所述第二连接线通过过孔与所述第一连接线的第二端连接。
在示例性实施方式中，所述像素驱动电路至少包括第一晶体管、第二晶体管和存储电容，所述第一晶体管至少包括第一有源层，所述第二晶体管至 少包括第二有源层，所述第一有源层的第二区和所述第二有源层的第一区为相互连接的一体结构，且通过第一连接电极与所述存储电容的第一极板连接；所述第二源漏金属层还包括屏蔽电极，所述屏蔽电极在所述基底上的正投影与所述第一有源层的第二区和所述第二有源层的第一区在所述基底上的正投影至少部分交叠，所述屏蔽电极在所述基底上的正投影与所述第一连接电极在所述基底上的正投影至少部分交叠。
在示例性实施方式中，所述第三源漏金属层还包括第一电源线，所述第一电源线通过过孔与所述屏蔽电极连接。
在示例性实施方式中，在垂直于显示基板的平面上，所述显示基板还包括设置在所述驱动结构层远离所述基底一侧的发光结构层，所述发光结构层包括多个发光单元，所述发光单元至少包括阳极；至少一个发光单元中，所述阳极在所述基底上的正投影与所述第一电源线在所述基底上的正投影至少部分交叠，所述阳极在所述基底上的正投影与所述屏蔽电极在所述基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个发光单元中，所述阳极在所述基底上的正投影与所述第一电源线在所述基底上的正投影具有第一交叠区域，所述阳极在所述基底上的正投影与所述屏蔽电极在所述基底上的正投影具有第二交叠区域，所述第一交叠区域的面积小于所述第二交叠区域的面积。
在示例性实施方式中，所述像素驱动电路至少包括第四晶体管，所述第四晶体管的第一极通过数据连接电极与所述数据信号线连接，至少一个电路单元中，所述第一连接线与所述数据连接电极连接。
在示例性实施方式中，至少一个电路单元还包括数据连接块，所述数据连接块的第一端与所述第一连接线连接，所述数据连接块的第二端与所述数据连接电极连接。
在示例性实施方式中，至少一个电路单元中，所述第一连接线、所述数据连接电极和所述数据连接块同层设置，且为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元还包括沿着所述第一方向延伸的第二初始信号线和沿着所述第二方向延伸的第二初始连接线，所述第二初 始连接线设置在所述第二方向相邻的两条第二初始信号线之间，且分别与两条第二初始信号线连接，在所述显示区域构成网络连通结构的第二初始信号线。
在示例性实施方式中，所述第二初始连接线设置在奇数单元列中，或者，所述第二初始连接线设置在偶数单元列中。
在示例性实施方式中，相邻的两个单元行中，一个单元行中所述第二初始连接线所在的单元列与另一个单元行中所述第二初始连接线所在的单元列不同。
在示例性实施方式中，所述第二初始信号线和所述第二初始连接线同层设置，且为相互连接的一体结构。
在示例性实施方式中，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个导电层包括沿着远离基底方向依次设置的遮挡层、第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层、第二源漏金属层和第三源漏金属层；所述遮挡层至少包括遮挡电极，所述第一半导体层至少包括多个低温多晶硅晶体管的有源层，所述第一栅金属层至少包括第一扫描信号线、发光信号线和存储电容的第一极板，所述第二栅金属层至少包括存储电容的第二极板，所述第二半导体层至少包括多个氧化物晶体管的有源层，所述第三栅金属层至少包括第二扫描信号线和第三扫描信号线，所述第一源漏金属层至少包括网络连通结构的第二初始信号线，所述第二源漏金属层至少包括屏蔽电极和所述第一连接线，所述第三源漏金属层至少包括第一电源线、所述数据信号线和所述第二连接线。
在示例性实施方式中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管，所述第一晶体管和第二晶体管为氧化物晶体管，所述第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管为低温多晶硅晶体管。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括显示区域，所述制备方法包括：
在所述显示区域的基底上形成驱动结构层，所述驱动结构层至少包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、多条沿着第一方向延伸的第一连接线和多条沿着第二方向延伸的第二连接线，所述第一方向和所述第二方向交叉；所述电路单元包括像素驱动电路，至少一条数据信号线与一个单元列的多个像素驱动电路连接，多条第一连接线的第一端与多条数据信号线对应连接，多条第一连接线的第二端与多条第二连接线对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，所述中心线是位于相邻单元列之间且沿着所述第二方向延伸的直线，所述第二连接线设置在相邻单元列的像素驱动电路之间的间隙处。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为本公开示例性实施例一种显示基板的平面结构示意图；
图7为本公开示例性实施例一种数据连接线的排布示意图；
图8为本公开示例性实施例一种显示基板的平面结构示意图；
图9为本公开实施例形成遮挡层图案后的示意图；
图10和11为本公开实施例形成第一半导体层图案后的示意图；
图12和图13为本公开实施例形成第一导电层图案后的示意图；
图14和图15为本公开实施例形成第二导电层图案后的示意图；
图16和图17为本公开实施例形成第二半导体层图案后的示意图；
图18和图19为本公开实施例形成第三导电层图案后的示意图；
图20为本公开实施例形成第六绝缘层图案后的示意图；
图21和图22为本公开实施例形成第四导电层图案后的示意图；
图23为本公开实施例形成第一平坦层图案后的示意图；
图24和图25为本公开实施例形成第五导电层图案后的示意图；
图26为本公开实施例形成第二平坦层图案后的示意图；
图27至图28为本公开实施例形成第六导电层图案后的示意图；
图29为本公开实施例形成第三平坦层图案后的示意图；
图30为本公开实施例形成阳极导电层图案后的示意图；
图31为本公开实施例形成像素定义层图案后的示意图；
图32为本公开实施例另一种显示基板的平面结构示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；       13—第三有源层；
14—第四有源层；       15—第五有源层；       16—第六有源层；
17—第七有源层；       21—第一扫描信号线；   22—发光信号线；
23—第一极板；         31—第一初始信号线；   32—第二遮挡线；
33—第三遮挡线；       34—第二极板；         35—开口；
41—第二扫描信号线；   42—第三扫描信号线；   51—第一连接电极；
52—第二连接电极；     53—第三连接电极；     54—第四连接电极；
55—第五连接电极；     56—第六连接电极；     57—第二初始信号线；
58—第二初始连接线；   60—数据信号线；       61—第十一连接电极；
62—第十二连接电极；   63—屏蔽电极；         64—第一电源线；
65—阳极连接电极；     70—第一连接线；       71—第一搭接块；
72—数据连接块；       80—第二连接线；       81—第二搭接块；
90—电源走线；         91—第一遮挡连接线；   92—第二遮挡连接线；
93—第三遮挡连接线；    94—遮挡电极；          100—显示区域；
101—基底；             102—驱动结构层；       103—发光结构层；
104—封装结构层；       200—绑定区域；         300—边框区域。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或 两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的 区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区，扇出区可以连接到显示区域，包括多条数据扇出线，数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线(Data Line)。弯折区可以连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使驱动芯片区和绑定引脚区弯折到显示区域的背面。驱动芯片区可以连接到弯折区，可以包括集成电路(Integrated Circuit，简称IC)，集成电路被配置为与多条数据扇出线连接。绑定引脚区可以连接到驱动芯片区，可以包括绑定焊盘(Bonding Pad)，绑定焊盘被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区可以连接到显示区域，可以至少包括栅极驱动电路，栅极驱动电路与显示区域中的扫描信号线和发光信号线连接。电源线区可以连接到电路区，可以至少包括电源引线，电源引线沿着平行于显示区域边缘的方向延伸，与显示区域中的阴极连接。裂缝坝区可以连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区可以连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有至少一个隔离坝，至少一个可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以 包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2、出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光单元输出相应的电流。每个子像素中的发光单元分别与所在子像素的像素驱动电路连接，发光单元被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动结构层102、设置在驱动结构层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动结构层102可以包括多个电路单元，每个电路单元可以至少包括由多个晶体管和存储电容构成的像素驱动电路。发光结构层103可以包括多个发光单元，每个发光单元可以至少包括阳极、像素定义层、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以 包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1至第七晶体管T7)和1个存储电容C，像素驱动电路分别与8条信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、发光信号线E、数据信号线D、第一初始信号线INIT1、第二初始信号线INIT1和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3和第四节点N4。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容C的第一端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接，第四节点N4分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接，第四节点N4还与发光器件EL的阳极连接。
在示例性实施方式中，存储电容C的第一端与第二节点N2连接，存储电容C的第二端与第一电源线VDD连接，即存储电容C的第一端与第三晶体管T3的栅电极连接。
在示例性实施方式中，第一晶体管T1的栅电极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1的第二极与第二节点N2连接。当导通的扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始化电压传输到存储电容C的第一端，实现存储电容C的初始化。
在示例性实施方式中，第二晶体管T2的栅电极与第三扫描信号线S3连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极 与第三节点N3连接。当导通的扫描信号施加到第三扫描信号线S3时，第二晶体管T2使第三晶体管T3的栅电极(第二节点N2)与第三晶体管T3的第二极(第三节点N3)连接。
在示例性实施方式中，第三晶体管T3的栅电极与第二节点N2连接，即第三晶体管T3的栅电极与存储电容C的第一端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定在第一电源线VDD与发光器件EL之间流动的驱动电流的大小。
在示例性实施方式中，第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。当导通的扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到第一节点N1。
在示例性实施方式中，第五晶体管T5的栅电极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接，第一电源线VDD的信号为持续提供的高电平信号。第六晶体管T6的栅电极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。当导通的发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6导通，在第一电源线VDD与发光器件EL之间形成驱动电流路径而使发光器件EL发光。
在示例性实施方式中，第七晶体管T7的栅电极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。当导通的扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到第四节点N4，以使发光器件EL的阳极中累积的电荷量初始化或释放发光器件EL的阳极中累积的电荷量。
在示例性实施方式中，发光器件EL可以是OLED，包括叠设的阳极(第一极)、有机发光层和阴极(第二极)，或者可以是QLED，包括叠设的阳极(第一极)、量子点发光层和阴极(第二极)。
在示例性实施方式中，发光器件EL的第一极与第四节点N4连接，发光器件EL的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第七晶体管T7可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一晶体管T1和第二晶体管T2可以采用金属氧化物晶体管，第三晶体管T3至第七晶体管T7可以采用低温多晶硅晶体管。
在示例性实施方式中，以图5所示的像素驱动电路中第一晶体管T1和第二晶体管T2为N型的氧化物晶体管、第三晶体管T3至第七晶体管T7为P型的低温多晶硅晶体管为例，像素驱动电路的工作过程可以包括：
第一阶段(可以称为复位阶段)，第二扫描信号线S2的信号为导通信号(高电平)，第一扫描信号线S1、第三扫描信号线S3和发光信号线E的信号为断开信号。第二扫描信号线S2的导通信号使第一晶体管T1导通，第一初始信号线INIT1的信号通过第一晶体管T1提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷，由于存储电容C的第一端为低电平，因此第三晶体管T3导通。本阶段中，第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，OLED 不发光。
第二阶段(可以称为数据写入阶段或者阈值补偿阶段)，第一扫描信号线S1和第三扫描信号线S3的信号为导通信号，第二扫描信号线S2和发光信号线E的信号为断开信号，数据信号线D输出数据电压。第一扫描信号线S1和第三扫描信号线S3的导通信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第一端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使第二初始信号线INIT2的信号提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。本阶段中，第一晶体管T1、第五晶体管T5和第六晶体管T6断开。
第三阶段(可以称为发光阶段)，发光信号线E的信号为导通信号，第一扫描信号线S1、第二扫描信号线S2和第三扫描信号线S3的信号为断开信号。发光信号线E的导通信号使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越 高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，绑定区域通常包括沿着远离显示区域的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。由于绑定区域的宽度小于显示区域的宽度，绑定区域中驱动芯片和绑定焊盘的信号线需要通过扇出区以扇出(Fanout)走线方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，因而扇形区占用空间较大，导致下边框的窄化设计难度较大，下边框一直维持在2.0mm左右。另一种显示基板中，边框区域通常设置边框电源引线，边框电源引线被配置为持续提供传输低电压电源信号，为了减小低电压电源信号的压降，边框电源引线的宽度较大，导致显示装置左右边框的宽度较大。
图6为本公开示例性实施例一种显示基板的平面结构示意图。在垂直于显示基板的平面上，显示基板可以包括设置在基底上的驱动结构层、设置在驱动结构层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。如图6所示，在平行于显示基板的平面上，显示基板可以至少包括显示区域100、位于显示区域100第二方向Y一侧的绑定区域200和位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100的驱动结构层可以包括构成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路被配置为向所连接的发光器件输出相应的电流。显示区域100的发光结构层可以包括多个发光单元，至少一个发光单元可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，本公开中所说的电路单元，是指按照像素驱动电路划分的区域，本公开中所说的发光单元，是指按照发光器件划分的区域。在示例性实施方式中，发光单元在基底上正投影的位置和形状与电路单元在基底上正投影的位置和形状可以是对应的，或者，发光单元在基底上正投影的位置和形状与电路单元在基底上正投影的位置和形状可以是不对应的。
在示例性实施方式中，沿着第一方向X依次设置的多个电路单元可以称 为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
在示例性实施方式中，显示区域100的驱动结构层还可以包括多条数据信号线60、多条第一连接线70和多条第二连接线80。数据信号线60分别与一个单元列中的多个像素驱动电路连接，数据信号线60被配置为向所连接的像素驱动电路提供数据信号。多条第一连接线70的第一端与多条数据信号线60对应连接，多条第一连接线70的第二端与多条第二连接线80对应连接，第一连接线70和第二连接线80构成数据连接线数据连接线，形成数据连接线位于显示区域(Fanout in AA，简称FIAA)结构，一部分数据信号线60通过数据连接线与绑定区域200中的引出线210连接，而另一部分数据信号线60与绑定区域200中的引出线210直接连接。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的引线区201、弯折区、驱动芯片区和绑定引脚区，引线区201连接到显示区域100，弯折区连接到引线区201。引线区201可以设置多条引出线210，多条引出线210可以沿着远离显示区域的方向延伸，一部分引出线210的第一端与显示区域100中的数据连接线60对应连接，另一部分引出线的第一端与显示区域100中的第二连接线80对应连接，多条引出线210的第二端沿着第二方向Y延伸并跨过弯折区后，与驱动芯片区的驱动芯片连接，使得驱动芯片通过引出线210将驱动芯片提供的数据信号施加到数据信号线60。由于第一连接线70和第二连接线80设置在显示区域，因而可以有效减小引线区第二方向Y的长度，大大缩减下边框宽度，提高了屏占比，有利于实现全面屏显示。
在示例性实施方式中，引出线210与数据信号线60和第二连接线80可以直接连接，或者可以通过过孔连接，本公开在此不做限定。
在示例性实施方式中，第一连接线70的形状可以为沿着第一方向X延伸的线形状，第二连接线80的形状可以为沿着第二方向Y延伸的线形状，数据信号线60的形状可以为沿着第二方向Y延伸的线形状。在示例性实施方式中，第一连接线70可以设置成与数据信号线60垂直，第二连接线80 可以设置成与数据信号线60平行。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
如图6所示，显示区域100的驱动结构层还可以包括多条电源走线90。在示例性实施方式中，电源走线90的形状可以为沿着第二方向Y延伸的线形状，多条电源走线90可以沿着第一方向X依次设置。
在示例性实施方式中，电源走线90可以设置在第一方向X上相邻的两条数据信号线60之间。
在示例性实施方式中，电源走线90和第二连接线80可以同层设置，且通过同一次图案化工艺同步形成。至少一个电路列中可以仅设置有电源走线90该电路列中没有设置第二连接线80。至少一个电路列中可以设置有电源走线90和第二连接线80，电源走线90和第二连接线80之间设置有断口DF，断口DF被配置为实现电源走线90和第二连接线80之间的绝缘。
在示例性实施方式中，多条电源走线90可以为持续提供低电压信号的走线。例如，电源走线可以为第二电源线VSS。多条电源走线90可以与绑定区域或者边框区域设置的电源引线连接。本公开通过在显示区域内设置电源走线，实现了低压电源线设置在子像素(VSS in pixel)的结构，不仅可以有效降低电源信号线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可以有效提升显示基板中电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。此外，低压电源线设置在子像素结构可以大幅度减小边框区域和绑定区域中电源引线的宽度，有利于实现窄边框。
在示例性实施方式中，显示基板可以具有中心线O，显示基板上的多条数据信号线60、多条第一连接线70、多条第二连接线80、多条电源走线90和多条引出线210可以相对于中心线O对称设置，中心线O可以为平分显示区域100的多个单元列并沿着第二方向Y延伸的直线。
在示例性实施方式中，驱动结构层可以包括多个导电层，第一连接线70和第二连接线80可以设置在不同的导电层中，数据信号线60和第二连接线80可以设置相同的导电层中，第一连接线70可以通过第一连接孔与数据信号线60连接，第二连接线80可以通过第二连接孔与第一连接线70连接。
图7为本公开示例性实施例一种数据连接线的排布示意图，示意了显示基板左侧区域中6条数据信号线、2条数据连接线和6条引出线的结构。如图7所示，在示例性实施方式中，左侧区域的多条数据信号线可以包括数据信号线60-1至数据信号线60-6，多条第一连接线可以包括第一连接线70-1和第一连接线70-2，多条第二连接线80可以包括第二连接线80-1和第二连接线80-2，多条引出线可以包括引出线210-1至引出线210-6。
在示例性实施方式中，数据信号线60-1至数据信号线60-6的形状可以为沿着第二方向Y延伸的线形状，可以沿着第一方向X按照编号从小到大顺序设置。第一连接线70-1和第一连接线70-2的形状为沿着第一方向X延伸的线形状，可以沿着第二方向Y按照编号从小到大顺序设置。第二连接线80-1和第二连接线80-2的形状为沿着第二方向Y延伸的线形状，可以沿着第一方向X按照编号从大到小顺序设置。
在示例性实施方式中，第一连接线70-1的第一端通过第一连接孔K1与数据信号线60-1连接，第一连接线70-1的第二端沿着第一方向X延伸后，通过第二连接孔K2与第二连接线80-1的第一端连接，第二连接线80-1的第二端沿着第二方向Y延伸到绑定区域后，与引出线210-1的第一端连接，引出线210-1的第二端沿着第二方向Y延伸并跨过弯折区后，与驱动芯片区的驱动芯片连接，因而实现了引出线210-1通过第二连接线80-1和第一连接线70-1与数据信号线60-1连接。
在示例性实施方式中，第一连接线70-2的第一端通过第一连接孔K1与数据信号线60-2连接，第一连接线70-2的第二端沿着第一方向X延伸后，通过第二连接孔K2与第二连接线80-2的第一端连接，第二连接线80-2的第二端沿着第二方向Y延伸到绑定区域后，与引出线210-2的第一端连接，引出线210-2的第二端沿着第二方向Y延伸并跨过弯折区后，与驱动芯片区的驱动芯片连接，因而实现了引出线210-2通过第二连接线80-2和第一连接线 70-2与数据信号线60-2连接。
在示例性实施方式中，数据信号线60-3至数据信号线60-6沿着第二方向Y延伸到绑定区域后，与引出线210-3至引出线210-6的第一端对应连接，引出线210-3至引出线210-6的第二端沿着第二方向Y延伸并跨过弯折区后，与驱动芯片区的驱动芯片连接。
在示例性实施方式中，驱动芯片中与引出线连接的引脚的排序为插序，第三引脚(与引出线210-3连接的引脚)和第四引脚(与引出线210-4连接的引脚)之间穿插第二引脚(与引出线210-2连接的引脚)，第四引脚和第五引脚(与引出线210-5连接的引脚)之间穿插第一引脚(与引出线210-1连接的引脚)，驱动芯片可以利用插序设计实现负载无突变的数据信号输出，提高显示品质。在示例性实施方式中，插序设计仅为一种实现方式，实际设计中可以采用正序设计的实现方式。例如，可以通过跨线设计使得驱动芯片的引脚输出信号的顺序与显示区域中数据信号线排布顺序一致。
在示例性实施方式中，在第二方向Y上相邻第一连接线70之间的间距可以相同或者可以不同，在第一方向X上相邻第二连接线80之间的间距可以相同或者可以不同，本公开在此不做限定。
在示例性实施方式中，至少一条第二连接线80可以设置在第一方向X上相邻的两条数据信号线60之间。
本公开通过在显示区域内设置包括第一连接线和第二连接线的数据连接线，使得绑定区域的引出线通过数据连接线与数据信号线连接，使得引线区中不需要设置扇形状的斜线，有效减小了引线区的长度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。
本公开示例性实施例提供了一种显示基板。在示例性实施方式中，显示基板包括显示区域，所述显示区域包括设置在基底上的驱动结构层，所述驱动结构层至少包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、多条沿着第一方向延伸的第一连接线和多条沿着第二方向延伸的第二连接线，所述第一方向和所述第二方向交叉；所述电路单元包括像素驱动电路，至少一条数据信号线与一个单元列的多个像素驱动电路连接，多条第一连接线的第一端与多条数据信号线对应连接，多条第 一连接线的第二端与多条第二连接线对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，所述中心线是位于相邻单元列之间且沿着所述第二方向延伸的直线，所述第二连接线设置在相邻单元列的像素驱动电路之间的间隙处。
在一种示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述第二连接线镜像对称，所述第二连接线与相邻的数据信号线在所述第一方向上的最小距离，大于相邻单元列中两条数据信号线在所述第一方向上的最小距离。
在另一种示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述第二连接线镜像对称，所述第二连接线与相邻的数据信号线在所述第一方向上的最小距离，为相邻单元列中两条数据信号线在所述第一方向上的最小距离的1/2。
在示例性实施方式中，所述驱动结构层还包括多条沿着所述第二方向延伸的电源走线，所述电源走线设置在相邻单元列的像素驱动电路之间的间隙处。
在一种示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述电源走线镜像对称，所述电源走线与相邻的数据信号线在所述第一方向上的最小距离，大于相邻单元列中两条数据信号线在所述第一方向上的最小距离。
在另一种示例性实施方式中，至少一个相邻单元列中的两条数据信号线相对于所述电源走线镜像对称，所述电源走线与相邻的数据信号线在所述第一方向上的最小距离，为相邻单元列中两条数据信号线在所述第一方向上的最小距离的1/2。
在示例性实施方式中，在垂直于显示基板的平面上，所述驱动结构层包括在基底上依次设置的多个导电层，所述第一连接线和第二连接线设置在不同的导电层中，所述数据信号线和所述第二连接线设置在相同的导电层中。
在示例性实施方式中，所述多个导电层至少包括沿着远离所述基底的方向依次设置的第一源漏金属层、第二源漏金属层和第三源漏金属层，所述第一连接线设置在所述第二源漏金属层中，所述数据信号线和所述第二连接线 设置在所述第三源漏金属层中，所述数据信号线通过过孔与所述第一连接线的第一端连接，所述第二连接线通过过孔与所述第一连接线的第二端连接。
在示例性实施方式中，所述第三源漏金属层还包括多条沿着所述第二方向延伸的电源走线，所述电源走线设置在相邻单元列的像素驱动电路之间的间隙处。
在示例性实施方式中，所述像素驱动电路至少包括存储电容和多个晶体管，所述多个导电层包括沿着远离基底方向依次设置的遮挡层、第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层、第二源漏金属层和第三源漏金属层；所述遮挡层至少包括遮挡电极，所述第一半导体层至少包括多个低温多晶硅晶体管的有源层，所述第一栅金属层至少包括第一扫描信号线、发光信号线和存储电容的第一极板，所述第二栅金属层至少包括存储电容的第二极板，所述第二半导体层至少包括多个氧化物晶体管的有源层，所述第三栅金属层至少包括第二扫描信号线和第三扫描信号线，所述第一源漏金属层至少包括网络连通结构的第二初始信号线，所述第二源漏金属层至少包括屏蔽电极和所述第一连接线，所述第三源漏金属层至少包括第一电源线、所述数据信号线和所述第二连接线。
在示例性实施方式中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管，所述第一晶体管和第二晶体管为氧化物晶体管，所述第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管为低温多晶硅晶体管。
图8为本公开示例性实施例一种显示基板的平面结构示意图，示意了显示区域中八个电路单元(2个单元行4个单元列)的像素驱动电路结构。在示例性实施方式中，显示基板可以包括显示区域，显示区域可以至少包括设置在基底上的驱动结构层以及设置在驱动结构层远离基底一侧的发光结构层。在平行于显示基板的平面上，驱动结构层可以至少包括构成多个单元行和多个单元列的多个电路单元，每个单元行中的多个电路单元沿着第一方向X依次设置，多个单元行沿着第二方向Y依次设置，每个单元列中的多个电路单元沿着第二方向Y依次设置，多个单元列沿着第一方向X依次设置，第一方向X和第二方向Y交叉。在示例性实施方式中，驱动结构层还可以包括 多条沿着第二方向Y延伸的数据信号线60、多条沿着第一方向X延伸的第一连接线70和多条沿着第二方向Y延伸的第二连接线80，电路单元可以包括像素驱动电路，至少一条数据信号线60与一个单元列的多个像素驱动电路电连接，数据信号线60被配置为向所连接的像素驱动电路提供数据信号。在示例性实施方式中，多条第一连接线70的第一端与多条数据信号线60对应连接，多条第一连接线70的第二端与多条第二连接线80对应连接，第一连接线70和第二连接线80被配置为向所连接的数据信号线60提供数据信号。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
在示例性实施方式中，相邻单元列中的像素驱动电路可以相对于中心线镜像对称，中心线可以是位于相邻的两个单元列之间且沿着第二方向Y延伸的直线，对称结构使得相邻单元列的像素驱动电路之间形成有间隙，多条第二连接线80可以分别设置在相邻单元列的像素驱动电路之间的间隙处。
在示例性实施方式中，至少一条第二连接线80可以设置在相邻单元列的两条数据信号线60之间，两条数据信号线60可以相对于第二连接线80镜像对称。
在示例性实施方式中，至少一条第二连接线80与相邻的数据信号线60在第一方向X上的最小距离L1，可以大于相邻单元列中两条数据信号线60在第一方向X上的最小距离L3。
在示例性实施方式中，在垂直于显示基板的平面上，驱动结构层可以包括在基底上依次设置的第一源漏金属层、第二源漏金属层和第三源漏金属层，第二源漏金属层可以至少包括第一连接线70，第三源漏金属层可以至少包括数据信号线60和第二连接线80，即第一连接线70和第二连接线80设置在不同的导电层中，数据信号线60和第二连接线80设置在相同的导电层中。
在示例性实施方式中，数据信号线60可以通过第一搭接过孔K1与第一连接线70的第一端连接，第二连接线80可以通过第二搭接过孔K2与第一 连接线70的第二端连接，即沿着第二方向Y延伸且位于第三源漏金属层中的第二连接线80通过第一搭接过孔K1与沿着第一方向X延伸且位于第二源漏金属层中的第一连接线70连接，沿着第一方向X延伸且位于第二源漏金属层中的第一连接线70通过第二搭接过孔K2与沿着第二方向Y延伸且位于第三源漏金属层中的数据信号线60连接。
在示例性实施方式中，驱动结构层还可以包括多条沿着第二方向Y延伸的电源走线90，多条电源走线90可以分别设置在相邻单元列的像素驱动电路之间的间隙处。
在示例性实施方式中，至少一条电源走线90可以设置在相邻单元列的两条数据信号线60之间，两条数据信号线60可以相对于电源走线90镜像对称。
在示例性实施方式中，至少一条电源走线90与相邻的数据信号线60在第一方向X上的最小距离L2，可以大于相邻单元列中两条数据信号线60在第一方向X上的最小距离L3。
在示例性实施方式中，电源走线90可以设置在第三源漏金属层中。
在示例性实施方式中，像素驱动电路可以至少包括第一晶体管、第二晶体管和存储电容，第一晶体管至少包括第一有源层，第二晶体管至少包括第二有源层，第一有源层的第二区和第二有源层的第一区为相互连接的一体结构，且通过第一连接电极与存储电容的第一极板连接。至少一个电路单元还可以包括屏蔽电极63，屏蔽电极63在基底上的正投影与第一有源层的第二区和第二有源层的第一区在基底上的正投影至少部分交叠，屏蔽电极63在基底上的正投影与第一连接电极在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个电路单元还可以包括第一电源线64，第一电源线64可以与屏蔽电极63连接。
在示例性实施方式中，屏蔽电极63可以设置在第二源漏金属层中，第一电源线64可以设置在第三源漏金属层中，第一电源线64可以通过过孔与屏蔽电极63连接。
在示例性实施方式中，像素驱动电路可以至少包括第四晶体管，数据信号线60可以通过数据连接电极61与像素驱动电路中第四晶体管的第一极连 接。至少一个电路单元中，第一连接线70与数据连接电极61连接。
在示例性实施方式中，至少一个电路单元还可以包括数据连接块72，数据连接块72的第一端与第一连接线70连接，数据连接块72的第二端与数据连接电极61连接。
在示例性实施方式中，第一连接线70、数据连接块72和数据连接电极61同层设置，且为相互连接的一体结构。
在示例性实施方式中，多个晶体管可以包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管，第一晶体管和第二晶体管为氧化物晶体管，第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管为低温多晶硅晶体管。
在示例性实施方式中，像素驱动电路至少包括存储电容和多个晶体管，多个导电层可以包括沿着远离基底方向依次设置的遮挡层、第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层、第二源漏金属层和第三源漏金属层。遮挡层可以至少包括遮挡电极，第一半导体层可以至少包括多个低温多晶硅晶体管的有源层，第一栅金属层可以至少包括第一扫描信号线、发光信号线和存储电容的第一极板，第二栅金属层可以至少包括存储电容的第二极板，第二半导体层可以至少包括多个氧化物晶体管的有源层，第三栅金属层可以至少包括第二扫描信号线和第三扫描信号线，第一源漏金属层可以至少包括网络连通结构的第二初始信号线，第二源漏金属层可以至少包括屏蔽电极和第一连接线，第三源漏金属层可以至少包括第一电源线、数据信号线和第二连接线。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在 整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以八个电路单元(2个单元行4个单元列)为例，驱动结构层的制备过程可以包括如下操作。
(1)形成遮挡层图案。在示例性实施方式中，形成遮挡层图案可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在基底上形成遮挡层图案，如图9所示。
在示例性实施方式中，每个电路单元的遮挡层图案可以至少包括第一遮挡连接线91、第二遮挡连接线92、第三遮挡连接线93和遮挡电极94。
在示例性实施方式中，遮挡电极94的形状可以为矩形，矩形状的角部可以设置倒角。第一遮挡连接线91可以为沿着第一方向X延伸的直线状，第一遮挡连接线91可以设置在遮挡电极94第一方向X的一侧，且与遮挡电极94连接。第二遮挡连接线92的形状可以为沿着第二方向Y延伸的折线状，第二遮挡连接线92可以设置在遮挡电极94第二方向Y的一侧，且与遮挡电极94连接。第三遮挡连接线93的形状可以为沿着第二方向Y延伸的折线状，第三遮挡连接线93可以设置在遮挡电极94第二方向Y的反方向的一侧，且与遮挡电极94连接。
在示例性实施方式中，每个电路单元的第一遮挡连接线91与第一方向X上相邻的电路单元的遮挡电极94连接，使得一个单元行中的遮挡层连接成一体，形成相互连接的一体结构。
在示例性实施方式中，每个电路单元的第二遮挡连接线92与第二方向Y上相邻的电路单元的第三遮挡连接线93连接，使得一个单元列中的遮挡层连接成一体，形成相互连接的一体结构。
在示例性实施方式中，单元行和单元列中的遮挡层连接成一体，可以保证显示基板中的遮挡层具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，相邻单元列的遮挡层可以相对于中心线镜像对称，中心线可以是位于相邻单元列之间且沿着第二方向Y延伸的直线。例如，第N列的遮挡层和第N+1列的遮挡层可以相对于中心线镜像对称，第N+1列的遮挡层和第N+2列的遮挡层可以相对于中心线镜像对称，第N+2列的遮挡层和第N+3列的遮挡层可以相对于中心线镜像对称。
在示例性实施方式中，多个单元行中遮挡层的形状可以基本上相同。
(2)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖遮挡层的第一绝缘层，以及设置在第一绝缘层上的第一半导体层图案，如图10和图11所示，图11为图10中第一半导体层的平面示意图。
在示例性实施方式中，每个电路单元的第一半导体层图案可以至少包括第三晶体管T3的第三有源层13至第七晶体管T7的第七有源层17，且第三有源层13至第七有源层17为相互连接的一体结构。
在示例性实施方式中，第三有源层13在基底上的正投影与遮挡电极94在基底上的正投影至少部分交叠。在第一方向X上，第六有源层16可以位于本电路单元中第三有源层13第一方向X的一侧，第四有源层14和第五有源层15可以位于本电路单元中第三有源层13第一方向X的反方向的一侧。在第二方向Y上，第M行电路单元中第四有源层14可以位于本电路单元中第三有源层13靠近第M+1行电路单元的一侧，第M行电路单元中的第五有源层15、第六有源层16和第七有源层17可以位于本电路单元中第三有源层13远离第M+1行电路单元的一侧，M可以为大于或等于1的正整数。
在示例性实施方式中，第三有源层13的形状可以呈倒“Ω”形，第四有源层14和第五有源层15的形状可以呈“I”字形，第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施方式中，第三有源层13至第七有源层17可以均包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第三有源层的第一区13-1可以同时作为第四有源层的第二区14-2和第五有源层的第二区15-2，第三有源层的第二区13-2可以作为第六有源层的第一区16-1，第六有源层的第二区16-2可以作为第七有源层的第二区17-2，第四有源层的第一区14-1、第五有源层的第一区15-1和第七有源层的第一区17-1可以单独设置。
在示例性实施方式中，第M+1行电路单元中的第七有源层的第一区17-1可以设置在第M行电路单元中。
在示例性实施方式中，一个单元行中，部分相邻两个电路单元中的第五有源层的第一区15-1可以相互连接。例如，第N+1列的第五有源层的第一区15-1和第N+2列的第五有源层的第一区15-1相互连接。由于每个电路单元中的第五有源层的第一区被配置为与后续形成的第一电源线连接，通过将相邻电路单元的第五有源层的第一区形成相互连接的一体结构，可以保证相邻电路单元的第五晶体管T5的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，相邻单元列的第一半导体层可以相对于中心线镜像对称。例如，第N列的第一半导体层和第N+1列的第一半导体层可以相对于中心线镜像对称，第N+1列的第一半导体层和第N+2列的第一半导体层可以相对于中心线镜像对称，第N+2列的第一半导体层和第N+3列的第一半导体层可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第一半导体层的形状可以基本上相同。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第三晶体管至第七晶体管为LTPS晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案 可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图12和图13所示，图13为图12中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个电路单元的第一导电层图案至少包括：第一扫描信号线21、发光信号线22和存储电容的第一极板23。
在示例性实施方式中，第一极板23的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板23在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板23可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第一扫描信号线21可以位于本电路单元的第一极板23靠近第M+1行电路单元的一侧，第M行电路单元中的第一扫描信号线21与本电路单元的第四有源层相重叠的区域作为第四晶体管T4的栅电极，第M行电路单元中的第一扫描信号线21与第M+1行电路单元中的第七有源层相重叠的区域作为第七晶体管T7的栅电极。
在示例性实施方式中，发光信号线22的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的发光信号线22可以位于本电路单元的第一极板23远离第M+1行电路单元的一侧，发光信号线22与本电路单元的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光信号线22与本电路单元的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，第一扫描信号线21和发光信号线22可以为非等宽度设计，第一扫描信号线21和发光信号线22的宽度为第二方向Y的尺寸，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，第一扫描信号线21可以包括与第一半导体层相重叠区域和与第一半导体层不相重叠区域，与第一半导体层相重叠区域的第一扫描信号线21的宽度可以小于与第一半导体层不相重叠区域的第一扫描信 号线21的宽度。
在示例性实施方式中，发光信号线22可以包括与第一半导体层相重叠区域和与第一半导体层不相重叠区域，与第一半导体层相重叠区域的第一扫描信号线21的宽度可以大于与第一半导体层不相重叠区域的第一扫描信号线21的宽度。
在示例性实施方式中，相邻单元列的第一导电层可以相对于中心线镜像对称。例如，第N列的第一导电层和第N+1列的第一导电层可以相对于中心线镜像对称，第N+1列的第一导电层和第N+2列的第一导电层可以相对于中心线镜像对称，第N+2列的第一导电层和第N+3列的第一导电层可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第一导电层的形状可以基本上相同。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第三晶体管T3至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即第三晶体管T3至第七有源层的第一区和第二区均被导体化。
(4)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图14和图15所示，图15为图14中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：第一初始信号线31、第二遮挡线32、第三遮挡线33和存储电容的第二极板34。
在示例性实施方式中，第二极板34的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板34在基底上的正投影与第一极板23在基底上的正投影至少部分交叠，第二极板34可以作为存储电容的另一个极板，第一极板23和第二极板34构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板34上设置有开口35，开口35的形状可以为矩形状，可以位于第二极板34的中部，使第二极板34形成环形结构。开口35暴露出覆盖第一极板23的第三绝缘层，且第一极板23在基底上的正投影包含开口35在基底上的正投影。在示例性实施方式中，开口35被配置为容置后续形成的第一过孔，第一过孔位于开口35内并暴露出第一极板23，使后续形成的第一晶体管T1的第二极与第一极板23连接。
在示例性实施方式中，一个单元行中相邻两个电路单元中的部分第二极板34可以相互连接。例如，第N+1列的第二极板34和第N+2列的第二极板34为相互连接的一体结构。在示例性实施方式中，由于每个电路单元中的第二极板34与后续形成的第一电源线连接，通过将相邻电路单元的第二极板34形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，可以保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一初始信号线31的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第一初始信号线31可以位于本电路单元的第二极板34靠近第M+1行电路单元的一侧。
在示例性实施方式中，第二遮挡线32和第三遮挡线33的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第二遮挡线32和第三遮挡线33可以位于本电路单元的第一初始信号线31和第二极板34之间，第二遮挡线32可以位于第三遮挡线33远离第二极板34的一侧，即第三遮挡线33可以位于第二遮挡线32和第二极板34之间。
在示例性实施方式中，第二遮挡线32被配置为遮挡第一晶体管的第一有源层，第三遮挡线33被配置为遮挡第二晶体管的第二有源层。第二遮挡线32和第三遮挡线33可以为非等宽度设计，第二遮挡线32和第三遮挡线33的宽度为第二方向Y的尺寸，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，相邻单元列的第二导电层可以相对于中心线镜像对称。例如，第N列的第二导电层和第N+1列的第二导电层可以相对于中心线镜像对称，第N+1列的第二导电层和第N+2列的第二导电层可以相对 于中心线镜像对称，第N+2列的第二导电层和第N+3列的第二导电层可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第二导电层的形状可以基本上相同。
(5)形成第二半导体层图案。在示例性实施方式中，形成第二半导体层图案可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖基底的第四绝缘层，以及设置在第四绝缘层上的第二半导体层图案，如图16和图17所示，图17为图16中第二半导体层的平面示意图。
在示例性实施方式中，每个电路单元的第二半导体层图案至少包括：第一晶体管T1的第一有源层11和第二晶体管T2的第二有源层12。
在示例性实施方式中，第一有源层11和第二有源层12的形状可以呈“I”字形，第M行电路单元中的第一有源层11可以位于本电路单元的第二有源层12靠近第M+1行电路单元的一侧。
在示例性实施方式中，第一有源层11在基底上的正投影与第二遮挡线32在基底上的正投影至少部分交叠，第二有源层12在基底上的正投影与第三遮挡线33在基底上的正投影至少部分交叠。
在示例性实施方式中，第一有源层11和第二有源层12可以均包括第一区、第二区以及位于第一区和第二区之间的沟道区。第一有源层的第一区11-1可以位于第二遮挡线32远离第二有源层12的一侧，第一有源层的第二区11-2可以位于第二遮挡线32靠近第二有源层12的一侧。第二有源层的第一区12-1可以位于第三遮挡线33远离第一有源层11的一侧，第二有源层的第二区12-2可以位于第三遮挡线33靠近第一有源层11的一侧。
在示例性实施方式中，第一有源层的第二区11-2可以作为第二有源层的第一区12-1，即第一有源层的第二区11-2和第二有源层的第一区12-1为相互连接的一体结构，可以位于第二遮挡线32和第三遮挡线33之间。
在示例性实施方式中，一体结构的第一有源层的第二区11-2和第二有源层的第一区12-1在基底上的正投影与本电路单元中第一扫描信号线21在基底上的正投影至少部分交叠。
在示例性实施方式中，相邻单元列的第二半导体层可以相对于中心线镜像对称。例如，第N列的第二半导体层和第N+1列的第二半导体层可以相对于中心线镜像对称，第N+1列的第二半导体层和第N+2列的第二半导体层可以相对于中心线镜像对称，第N+2列的第二半导体层和第N+3列的第二半导体层可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第二半导体层的形状可以基本上相同。
在示例性实施方式中，第二半导体层可以采用氧化物，即第一晶体管T1和第二晶体管T2为氧化物晶体管。在示例性实施方式中，第二半导体薄膜可以采用氧化铟镓锌(IGZO)，氧化铟镓锌(IGZO)的电子迁移率高于非晶硅。
(6)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成覆盖第二半导体层的第五绝缘层，以及设置在第五绝缘层上的第三导电层图案，如图18和图19所示，图19为图18中第三导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，每个电路单元的第三导电层图案至少包括：第二扫描信号线41和第三扫描信号线42。
在示例性实施方式中，第二扫描信号线41和第三扫描信号线42的形状可以为主体部分沿着第一方向X延伸的线形状，第M行电路单元中的第二扫描信号线41和第三扫描信号线42可以位于本电路单元的第一初始信号线31和第二极板34之间，第二扫描信号线41可以位于第三扫描信号线42远离第二极板34的一侧，即第三扫描信号线42可以位于第二扫描信号线41和第二极板34之间。
在示例性实施例中，第二扫描信号线41与第一有源层相重叠的区域作为第一晶体管T1的栅电极，第三扫描信号线42与第二有源层相重叠的区域作为第二晶体管T2的栅电极。
在示例性实施例中，第二扫描信号线41在基底上的正投影与第二遮挡线32在基底上的正投影至少部分交叠，第二遮挡线32和第二扫描信号线41可 以连接相同的信号源，使得第二遮挡线32可以作为第一晶体管T1的底栅电极，第二扫描信号线41可以作为第一晶体管T1的顶栅电极，形成双栅结构的第一晶体管T1。
在示例性实施例中，第三扫描信号线42在基底上的正投影与第三遮挡线33在基底上的正投影至少部分交叠，第三遮挡线33和第三扫描信号线42可以连接相同的信号源，使得第三遮挡线33可以作为第二晶体管T2的底栅电极，第三扫描信号线42可以作为第二晶体管T2的顶栅电极，形成双栅结构的第二晶体管T2。
在示例性实施方式中，相邻单元列的第三导电层可以相对于中心线镜像对称。例如，第N列的第三导电层和第N+1列的第三导电层可以相对于中心线镜像对称，第N+1列的第三导电层和第N+2列的第三导电层可以相对于中心线镜像对称，第N+2列的第三导电层和第N+3列的第三导电层可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第三导电层的形状可以基本上相同。
(7)形成第六绝缘层图案。在示例性实施方式中，形成第六绝缘层图案可以包括：在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第六绝缘层，第六绝缘层上设置有多个过孔，如图20所示。
在示例性实施方式中，每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10和第十一过孔V11。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口35在基底上的正投影的范围之内，第一过孔V1内的第六绝缘层、第五绝缘层、第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板23的表面，第一过孔V1配置为使后续形成的第一连接电极通过该过孔与第一极板23连接。
在示例性实施方式中，第二过孔V2位于第二极板34在基底上的正投影的范围之内，第二过孔V2内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板34的表面，第二过孔V2被配置为使后续形成的第四连接电极通过该过孔与第二极板34连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第四连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面，第四过孔V4被配置为使后续形成的第六连接电极通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的第三连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第三有源层的第二区(也是第六有源层的第一区)在基底上的正投影的范围之内，第六过孔V6内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区(也是第六有源层的第一区)的表面，第六过孔V6被配置为使后续形成的第五连接电极通过该过孔与第三有源层的第二区(也是第六有源层的第一区)连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第七过孔V7被配置为使后续形成的第二初始信号线通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第六绝缘层和第 五绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第八过孔V8被配置为使后续形成的第二连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第二有源层的第二区在基底上的正投影的范围之内，第九过孔V9内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第九过孔V9被配置为使后续形成的第五连接电极通过该过孔与第二有源层的第二区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第十过孔V10内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面，第十过孔V10被配置为使后续形成的第一连接电极通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第十一过孔V11内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面，第十一过孔V11被配置为使后续形成的第二连接电极通过该过孔与第一初始信号线31连接。
在示例性实施方式中，相邻单元列的多个过孔可以相对于中心线镜像对称。例如，第N列的多个过孔和第N+1列的多个过孔可以相对于中心线镜像对称，第N+1列的多个过孔和第N+2列的多个过孔可以相对于中心线镜像对称，第N+2列的多个过孔和第N+3列的多个过孔可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中多个过孔的形状可以基本上相同。
(8)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第六绝缘层上的第四导电层，如图21和图22所示，图22为图21中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个电路单元的第四导电层至少包括：第一连接 电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第二初始信号线57和第二初始连接线58。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的折线形，第一连接电极51的第一端通过第一过孔V1与第一极板23连接，第一连接电极51的第二端沿着第二方向Y延伸后，通过第十过孔V10与第一有源层的第二区(也是第二有源层的第一区)连接，使第一极板23、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施方式中，第一连接电极51可以同时作为第一晶体管T1的第二极和第二晶体管T2的第一极(像素驱动电路的第二节点N2)。
在示例性实施方式中，第二连接电极52的形状可以为沿着第一方向X延伸的条形状，第二连接电极52的第一端通过第八过孔V8与第一有源层的第一区连接，第二连接电极52的第二端通过第十一过孔V11与第一初始信号线31连接，使第一初始信号线31传输的第一初始电压写入第一晶体管T1的第一极。在示例性实施方式中，第二连接电极52可以作为第一晶体管T1的第一极。
在示例性实施方式中，每个单元行中，第N列的第二连接电极52和第N+1列的第二连接电极52可以为相互连接的一体结构，第N+2列的第二连接电极52和第N+3列的第二连接电极52可以为相互连接的一体结构。
在示例性实施方式中，第三连接电极53的形状可以为矩形状，第三连接电极53通过第五过孔V5与第四有源层的第一区连接。在示例性实施方式中，第三连接电极53可以作为第四晶体管T4的第一极，第三连接电极53被配置为与后续形成的第十一连接电极连接。
在示例性实施方式中，第四连接电极54的形状可以为“Y”形状，第四连接电极54的第一端通过第二过孔V2与第二极板34连接，第四连接电极54的第二端通过第三过孔V3与第五有源层的第一区连接，因而实现了电路单元中第五晶体管T5的第一极和存储电容的第二极板34具有相同的电位。在示例性实施方式中，第四连接电极54可以作为第五晶体管T5的第一极，第四连接电极54被配置为与后续形成的屏蔽电极连接。
在示例性实施方式中，至少一个单元行中，第N+1列中的第四连接电极 54和第N+2列的第四连接电极54可以为相互连接的一体结构。在示例性实施方式中，由于每个电路单元中的第四连接电极54与后续形成的第一电源线连接，通过将相邻电路单元的第四连接电极54形成相互连接的一体结构，可以保证相邻电路单元的第四连接电极54具有相同的电位，因而使得相邻电路单元中第五晶体管T5的第一极具有相同的电位，相邻电路单元中存储电容的第二极板34具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第四连接电极54在基底上的正投影与第七有源层的第二区在基底上的正投影至少部分交叠，具有恒定电位的第四连接电极54可以起到屏蔽作用，保证像素驱动电路中关键节点的电位稳定性。
在示例性实施方式中，第五连接电极55的形状可以为矩形状，第五连接电极55的第一端通过第六过孔V6与第三有源层的第二区(也是第六有源层的第一区)连接，第五连接电极55的第二端通过第九过孔V9与第二有源层的第二区连接。在示例性实施方式中，第五连接电极55可以同时作为第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极(像素驱动电路的第三节点N3)。
在示例性实施方式中，第六连接电极56的形状可以为多边形状，第六连接电极56通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第六连接电极56可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第六连接电极56被配置为与后续形成的第十二连接电极连接。
在示例性实施方式中，第二初始信号线57的形状可以为主体部分沿着第一方向X延伸的折线状，第M行电路单元中的第二初始信号线57可以设置在存储电容靠近第M+1行电路单元的一侧，第M行电路单元中的第二初始信号线57通过第七过孔V7与第M+1行电路单元中第七有源层的第一区连接，使第二初始信号线57传输的第二初始电压写入第七晶体管T7的第一极。由于第二初始信号线57与一个单元行中所有的第七有源层的第一区连接，可以保证一个单元行中所有的第七晶体管T7的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第二初始连接线58的形状可以为主体部分沿着第二方向Y延伸的折线状，第二初始连接线58可以设置在第二方向Y相邻的两条第二初始信号线57之间，且分别与两条第二初始信号线57连接。这样，沿着第一方向X延伸的第二初始信号线57和沿着第二方向Y延伸的第二初始连接线58在显示区域构成网络连通结构的初始信号线，不仅可以最大限度地降低了初始信号线的电阻，减小了初始电压的压降，有效提升了显示基板中初始电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，而且使得复位阶段中像素驱动电路的第四节点(阳极)的电位更均匀，发光器件起亮速度更容易保持一致，提高了显示品质和显示质量。
在示例性实施方式中，第二初始连接线58可以设置在奇数单元列中，或者可以设置在偶数单元列，即两个单元列中设置一条第二初始连接线58。
在示例性实施方式中，相邻的两个单元行中，一个单元行中第二初始连接线58所在的单元列与另一个单元行中第二初始连接线58所在的单元列不同。例如，分别连接第M-1行中第二初始信号线57和第M行中第二初始信号线57的第二初始连接线58可以位于第N列的电路单元中，而分别连接第M行中第二初始信号线57和第M+1行中第二初始信号线57的第二初始连接线58可以位于第N+2列的电路单元中。
在示例性实施方式中，第二初始信号线57和第二初始连接线58通过同一次图案化工艺同步形成，且为相互连接的一体结构。
在示例性实施方式中，相邻单元列的第一连接电极51至第六连接电极56和第二初始信号线57可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第一连接电极51至第六连接电极56和第二初始信号线57的形状可以基本上相同。
(9)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第四导电层图案的第一平坦层，第一平坦层上设置有多个过孔，如图23所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第三连接电极53在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层被刻蚀掉，暴露出第三连接电极53的表面，第二十一过孔V21被配置为使后续形成的第十一连接电极通过该过孔与第三连接电极53连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层被刻蚀掉，暴露出第六连接电极56的表面，第二十二过孔V22被配置为使后续形成的第十二连接电极通过该过孔与第六连接电极56连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第四连接电极54在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层被刻蚀掉，暴露出第四连接电极54的表面，第二十三过孔V232被配置为使后续形成的屏蔽电极通过该过孔与第四连接电极54连接。
在示例性实施方式中，相邻单元列的第一平坦层上的多个过孔可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第一平坦层上的多个过孔的形状可以基本上相同。
(10)形成第五导电层图案。在示例性实施方式中，形成第五导电层可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第一平坦层上的第五导电层，如图24和图25所示，图25为图24中第五导电层的平面示意图。在示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，每个电路单元的第五导电层至少包括：第十一连接电极61、第十二连接电极62和屏蔽电极63。
在示例性实施方式中，第十一连接电极61的形状可以为主体部分沿着第二方向Y延伸的条形状，第十一连接电极61通过第二十一过孔V21与第三连接电极53连接，第十一连接电极61被配置为与后续形成的数据信号线连接，第十一连接电极61可以称为数据连接电极。
在示例性实施方式中，第十二连接电极62的形状可以为多边形状，第十二连接电极62通过第二十二过孔V22与第六连接电极56连接，第十二连接 电极62被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，屏蔽电极63的形状可以为主体部分沿着第二方向Y延伸的块形状，屏蔽电极63通过第二十三过孔V23与第四连接电极54连接，屏蔽电极63被配置为与后续形成的第一电源线连接。
在示例性实施方式中，屏蔽电极63可以包括屏蔽主体部63-1和屏蔽连接部63-2。屏蔽主体部63-1的形状可以为矩形状，矩形状的角部可以设置倒角，屏蔽主体部63-1在基底上的正投影与第一连接电极51在基底上的正投影至少部分交叠，屏蔽主体部63-1在基底上的正投影与第一有源层的第二区和第二有源层的第一区在基底上的正投影至少部分交叠。屏蔽连接部63-2的形状可以为沿着第二方向Y延伸的条形状，屏蔽连接部63-2的第一端与屏蔽主体部63-1连接，屏蔽连接部63-2的第二端向着远离屏蔽主体部63-1的方向延伸后，通过第二十三过孔V23与第四连接电极54连接，屏蔽连接部63-2在基底上的正投影与第一连接电极51在基底上的正投影至少部分交叠。
在示例性实施方式中，由于屏蔽电极63完全遮挡住第一有源层的第二区和第二有源层的第一区，因而屏蔽电极63可以阻挡发光器件的发光和膜层反射光照射到氧化物晶体管，可以防止氧化物晶体管因光照发生特性漂移，提高了氧化物晶体管的电学特性。由于屏蔽电极63与后续形成的第一电源线连接，因而具有恒定电位的屏蔽电极63不仅可以有效屏蔽数据电压跳变和其它信号对像素驱动电路中第二节点N2的影响，避免了数据电压跳变和其它信号影响第二节点N2的电位，有效避免了串扰(Cross Talk)恶化，而且可以避免因部分电路单元设置第二连接线而部分电路单元没有设置第二连接线产生的显示差异，提高了显示效果。
在示例性实施方式中，第四导电层还可以包括：第一连接线70、第一搭接块71和数据连接块72。
在示例性实施方式中，第一连接线70的形状可以为主体部分沿着第一方向X延伸的折线状，第M行电路单元的第一连接线70可以设置在屏蔽电极63靠近第M+1行电路单元的一侧，第一连接线70被配置作为数据连接线中的横向走线。
在示例性实施方式中，至少一个单元行中，第一连接线70上可以设置有 断口，断口一侧的第一连接线70作为数据连接线中的横向走线，断口另一侧的第一连接线70作为虚设走线，以保证显示基板的刻蚀均一性。
在示例性实施方式中，第一搭接块71的形状可以为多边形状，位于相邻的单元列之间，且与第一连接线70连接。例如，第一搭接块71可以设置在第N列和第N+1列之间，第一搭接块71可以设置在第N+2列和第N+3列之间。在示例性实施方式中，一部分第一搭接块71被配置为与后续形成的第二连接线连接，另一部分第一搭接块71作为虚设搭接结构，以保证显示基板的刻蚀均一性。
在示例性实施方式中，数据连接块72的形状可以为沿着第二方向Y延伸的条形状，数据连接块72的第一端与第一连接线70连接，数据连接块72的第二端与第三连接电极53连接。
在示例性实施方式中，至少一个电路单元中，第一连接线70、第一搭接块71和数据连接块72可以通过同一次图案化工艺同步形成，且为相互连接的一体结构。
在示例性实施方式中，相邻单元列的第十一连接电极61、第十二连接电极62和屏蔽电极63可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第十一连接电极61、第十二连接电极62和屏蔽电极63的形状可以基本上相同。
(11)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第五导电层图案的第二平坦层，第二平坦层上设置有多个过孔，如图26所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第三十一过孔V31、第三十二过孔V32和第三十三过孔V33。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于第十一连接电极61在基底上的正投影的范围之内，第三十一过孔V31内的第二平坦层被刻蚀掉，暴露出第十一连接电极61的表面，第三十一过孔V31被配置为使后续形成的数据信号线通过该过孔与第十一连接电极61连接。在示例 性实施方式中，与第一连接线70连接的第十一连接电极61(数据连接电极)上的第三十一过孔V31可以称为第一搭接过孔。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第十二连接电极62在基底上的正投影的范围之内，第三十二过孔V32内的第二平坦层被刻蚀掉，暴露出第十二连接电极62的表面，第三十二过孔V32被配置为使后续形成的阳极连接电极通过该过孔与第十二连接电极62连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于屏蔽电极63中屏蔽连接部63-2在基底上的正投影的范围之内，第三十三过孔V33内的第二平坦层被刻蚀掉，暴露出屏蔽连接部63-2的表面，第三十三过孔V33被配置为使后续形成的第一电源线通过该过孔与屏蔽电极63连接。
在示例性实施方式中，第二平坦层上的多个过孔还可以包括第三十四过孔V34。第三十四过孔V34在基底上的正投影位于第一搭接块71在基底上的正投影的范围之内，第三十四过孔V34内的第二平坦层被刻蚀掉，暴露出第一搭接块71的表面，第三十四过孔V34被配置为使后续形成的第二连接线通过该过孔与第一连接线70连接。在示例性实施方式中，部分第一搭接块71上设置有第三十四过孔V34，第三十四过孔V34可以称为第二搭接过孔。
在示例性实施方式中，相邻单元列的第三十一过孔V31、第三十二过孔V32和第三十三过孔V33可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中第三十一过孔V31、第三十二过孔V32和第三十三过孔V33的形状可以基本上相同。
(12)形成第六导电层图案。在示例性实施方式中，形成第六导电层可以包括：在形成前述图案的基底上，沉积第六导电薄膜，采用图案化工艺对第六导电薄膜进行图案化，形成设置在第二平坦层上的第六导电层，如图27和图28所示，图28为图27中第六导电层的平面示意图。在示例性实施方式中，第六导电层可以称为第三源漏金属(SD3)层。
在示例性实施方式中，每个电路单元的第六导电层至少包括：数据信号线60、第一电源线64和阳极连接电极65。
在示例性实施方式中，数据信号线60的形状可以为主体部分沿着第二 方向Y延伸的线形状，数据信号线60通过第三十一过孔V31与第十一连接电极61连接。由于第十一连接电极61通过过孔与第三连接电极53连接，第三连接电极53通过过孔与第四有源层的第一区连接，因而实现了数据信号线60与第四晶体管T4的第一极的连接，数据信号线60可以将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，由于数据信号线设置在第三源漏金属(SD3)层，与相应信号线之间间隔有较厚的第一平坦层和第二平坦层，增加了数据信号线与相应信号线之间的距离，减小了数据信号线与相应信号线之间的寄生电容，因而有效减小了数据信号线的电容负载。
在示例性实施方式中，第一电源线64的形状可以为主体部分沿着第二方向Y延伸的折线状，第一电源线64通过第三十三过孔V33与屏蔽电极63的屏蔽连接部63-2连接。由于屏蔽电极63通过过孔与第四连接电极54连接，第四连接电极54通过过孔与第五有源层的第一区和第二极板34连接，因而实现了第一电源线64与第五晶体管T5的第一极和第二极板34的连接，第一电源线64可以将电源信号写入第五晶体管T5的第一极，且第五晶体管T5的第一极和存储电容的第二极板34具有相同的电位。
在示例性实施方式中，第一电源线64可以为非等宽度的折线，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，阳极连接电极65的形状可以为多边形状，阳极连接电极65通过第三十二过孔V32与第十二连接电极62连接，阳极连接电极65被配置为与后续形成的阳极连接。由于第十二连接电极62通过过孔与第六连接电极56连接，第六连接电极56通过过孔与第六有源层的第二区和第七有源层的第二区连接，因而可以实现后续形成的阳极与第六晶体管T6的第二极和第七晶体管T7的第二极的连接，像素驱动电路可以驱动发光器件发光。
在示例性实施方式中，第六导电层还可以包括第二连接线80、第二搭接块81和电源走线90。
在示例性实施方式中，第二连接线80的形状可以为主体部分沿着第二方 向Y延伸的线形状，可以位于相邻单元列的像素驱动电路之间的间隙处，第二连接线80通过第三十四过孔V34与第一搭接块71连接。由于第一搭接块71与第一连接线70连接，因而实现了第二连接线80与第一连接线70之间的连接。由于第一连接线70通过数据连接块72与第十一连接电极61连接，第十一连接电极61通过过孔与数据信号线60连接，因而实现了数据信号线60、第一连接线70和第二连接线80之间的依次连接。
在示例性实施方式中，第二搭接块81的形状可以为多边形状，位于相邻的单元列之间，且与第二连接线80。例如，第二搭接块81可以设置在第N列和第N+1列之间，第二搭接块81可以设置在第N+2列和第N+3列之间。在示例性实施方式中，第二搭接块81在基底上的正投影与第一搭接块71在基底上的正投影至少部分交叠，一部分第二搭接块81通过第三十四过孔V34与第一搭接块71连接，另一部分第二搭接块81作为虚设搭接结构，以保证显示基板的刻蚀均一性。
在示例性实施方式中，由于显示区域的像素驱动电路采用镜像对称结构，相邻单元列的像素驱动电路镜像对称，因而可以在电路单元尺寸不变的情况下，可以通过中心压缩在相邻单元列的像素驱动电路之间形成间隙，使得在显示区域纵向延伸的第二连接线可以设置在相邻像素驱动电路之间的间隙处，最大限度地增加了第二连接线与数据信号线之间的距离，最大限度地减小了第二连接线与数据信号线之间因电容耦合产生的干扰。
在示例性实施方式中，至少一条第二连接线80可以设置在相邻单元列的两条数据信号线60之间，两条数据信号线60可以相对于中心线镜像对称，两条数据信号线60可以相对于第二连接线80镜像对称。
在示例性实施方式中，至少一条第二连接线80与相邻的数据信号线60在第一方向X上的最小距离L1，可以大于相邻单元列中两条数据信号线60在第一方向X上的最小距离L3。
在示例性实施方式中，由于第二连接线设置在第三源漏金属(SD3)层，与相应信号线之间间隔有较厚的第一平坦层和第二平坦层，增加了第二连接线与相应信号线之间的距离，减小了第二连接线与相应信号线之间的寄生电容，因而有效减小了第二连接线的电容负载。
在示例性实施方式中，由于第一连接线设置在第二源漏金属(SD2)层，第二连接线设置在第三源漏金属(SD3)层，因而第一连接线和第二连接线只需要一个平坦层过孔即可实现连接，最大限度地减小了占用空间，有利于实现高分辨率显示。
在示例性实施方式中，电源走线90的形状可以为主体部分沿着第二方向Y延伸的线形状，位于部分相邻的单元列之间。至少一个单元列之间，可以仅设置有电源走线90，而没有设置第二连接线80。至少一个单元列之间，可以分别设置有第二连接线80和电源走线90，电源走线90和第二连接线80可以位于同一条沿着第二方向Y延伸的直线上，且电源走线90和第二连接线80之间设置有断口断口，断口被配置为实现电源走线90和第二连接线80之间的绝缘。
在示例性实施方式中，至少一条电源走线90可以设置在相邻单元列的两条数据信号线60之间，两条数据信号线60可以相对于电源走线90镜像对称。
在示例性实施方式中，至少一条电源走线90与相邻的数据信号线60在第一方向X上的最小距离L2，可以大于相邻单元列中两条数据信号线60在第一方向X上的最小距离L3。
在示例性实施方式中，多条电源走线90可以为持续提供低电压信号的走线。例如，电源走线可以为第二电源线VSS。多条电源走线90可以与绑定区域或者边框区域设置的电源引线连接。本公开通过在显示区域内设置电源走线，实现了低压电源线设置在子像素(VSS in pixel)的结构，不仅可以有效降低电源信号线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可以有效提升显示基板中电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。此外，低压电源线设置在子像素结构可以大幅度减小边框区域和绑定区域中电源引线的宽度，有利于实现窄边框。
在示例性实施方式中，相邻单元列的数据信号线60、第一电源线64和阳极连接电极65可以相对于中心线镜像对称。在示例性实施方式中，多个单元行中数据信号线60、第一电源线64和阳极连接电极65的形状可以基本上相同。
(13)形成第三平坦层图案。在示例性实施方式中，形成第三平坦层图 案可以包括：在形成前述图案的基底上，涂覆第三平坦薄膜，采用图案化工艺对第三平坦薄膜进行图案化，形成覆盖第六导电层图案的第三平坦层，第三平坦层上设置有多个过孔，如图29所示。
在示例性实施方式中，每个电路单元的过孔至少包括阳极过孔V40。阳极过孔V40在基底上的正投影位于阳极连接电极65在基底上的正投影的范围之内，阳极过孔V40内的第三平坦层被去掉，暴露出阳极连接电极65的表面，阳极过孔V40被配置为使后续形成的阳极通过该过孔与阳极连接电极65连接。
至此，在基底上制备完成驱动结构层。在平行于显示基板的平面内，驱动结构层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。在垂直于显示基板的平面内，驱动结构层可以包括在基底上依次设置的遮挡层、第一绝缘层、第一半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第二半导体层、第五绝缘层、第三导电层、第六绝缘层、第四导电层、第一平坦层、第五导电层、第二平坦层、第六导电层和第三平坦层。遮挡层可以至少包括遮挡电极，第一半导体层可以至少包括第三晶体管至第七晶体管的有源层，第一导电层可以至少包括第一扫描信号线、发光信号线和存储电容的第一极板，第二导电层可以至少包括第一初始信号线和存储电容的第二极板，第二半导体层可以至少包括第一晶体管至第二晶体管的有源层，第三导电层可以至少包括第二扫描信号线和第三扫描信号线，第四导电层可以至少包括第二初始信号线、第二初始连接线和多个连接电极，第五导电层可以至少包括屏蔽电极和第一连接线，第六导电层可以至少包括数据信号线、第一电源线、第二电源线和第二连接线。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性 材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层、第五导电层和第六导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以称为栅绝缘(GI)层，第六绝缘层可以称为层间绝缘(ILD)层。第一平坦层、第二平坦层和第三平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，一个单元行中相邻两个电路单元中的像素驱动电路可以相对于中心线基本上镜像对称，中心线是位于相邻两个电路单元之间且沿着第二方向Y延伸的直线。例如，第N列的像素驱动电路和第N+1列的像素驱动电路可以相对于中心线镜像对称。又如，第N+1列的像素驱动电路和第N+2列的像素驱动电路可以相对于中心线镜像对称。
在示例性实施方式中，相邻两个电路单元中的像素驱动电路可以相对于中心线基本上镜像对称可以包括如下任意一种或多种：一个单元行中相邻两个电路单元中的第一半导体层可以相对于中心线镜像对称，一个单元行中相邻两个电路单元中的第一导电层可以相对于中心线镜像对称，一个单元行中相邻两个电路单元中的第二导电层可以相对于中心线镜像对称，一个单元行中相邻两个电路单元中的第二半导体层可以相对于中心线镜像对称，一个单元行中相邻两个电路单元中的第三导电层可以相对于中心线镜像对称。
在示例性实施方式中，制备完成驱动结构层后，在驱动结构层上制备发 光结构层，发光结构层的制备过程可以包括如下操作。
(14)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第三平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案，如图30所示。
在示例性实施方式中，阳极导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，多个阳极图案可以包括位于出射红色光线的红色发光单元的第一阳极90A、位于出射蓝色光线的蓝色发光单元的第二阳极90B、位于出射绿色光线的第一绿色发光单元的第三阳极90C和位于出射绿色光线的第二绿色发光单元的第四阳极90D。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D可以分别通过阳极过孔V40与所在电路单元的阳极连接电极65连接。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D中的至少一个可以包括相互连接的阳极主体部和阳极连接部，阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，阳极连接部的形状可以为条形状，阳极连接部的第一端与阳极主体部连接，阳极连接部的第二端向着远离阳极主体部的方向延伸后，通过阳极过孔V40与阳极连接电极65连接。
在示例性实施方式中，第一阳极、第二阳极、第三阳极和第四阳极在基底上的正投影与第一电源线在基底上的正投影至少部分交叠，第一阳极和第二阳极在基底上的正投影与屏蔽电极在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个发光单元中，第一阳极在基底上的正投影与第一电源线在基底上的正投影具有第一交叠区域，第一阳极在基底上的正投影与屏蔽电极在基底上的正投影具有第二交叠区域，第一交叠区域的面积小于第二交叠区域的面积。至少一个发光单元中，第二阳极在基底上的正投影与第一电源线在基底上的正投影具有第一交叠区域，第二阳极在基底上的正投影与屏蔽电极在基底上的正投影具有第二交叠区域，第一交叠区域的 面积小于第二交叠区域的面积。本公开通过将屏蔽电极设置在第二源漏金属层SD2，第一电源线设置在第三源漏金属层SD3，有效减小了第一阳极和第二阳极与第一电源线的交叠面积，有效减小了像素驱动电路第四节点N4的寄生电容，提高了发光器件的起亮速度。
(15)形成像素定义层图案。在示例性实施方式中，形成像素定义层图案可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成覆盖阳极导电层图案的像素定义层，像素定义层上设置有多个像素开口90E，像素开口90E内的像素定义薄膜被去掉，分别暴露出第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D的表面，如图31所示。
在示例性实施方式中，后续制备流程可以包括：先采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，随后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
从以上描述的显示基板的结构以及制备过程可以看出，本公开示例性实施例所提供的显示基板，通过在显示区域内设置数据连接线，使得绑定区域的引出线通过数据连接线与数据信号线连接，使得引线区中不需要设置扇形状的斜线，有效减小了引线区的长度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。本公开通过将第一连接线设置在第二源漏金属层，第二连接线设置在第三源漏金属层，因而第一连接线和第二连接线只需要一个平坦层过孔即可实现连接，最大限度地减小了占用空间，有利于实现高分辨率显示，在实现窄边框的同时，可以将LTPO显示基板的分辨率(PPI)提升至480。本公开通过将数据信号线和第二连接线设置在第三源漏金属层，增加了数据信号线和第二连接线与相应信号线之间的距离，减小了数据信号线和第二连接线与相应信号线之间的寄生电容，因而有效减小了数据信号线和第二连接线的电容负载。本公开通过采用像素驱动电路镜像对称和中心压缩，将第二连接线设置在相邻单元列的间隙处，最大限度地增加了第二连接 线与数据信号线之间的距离，最大限度地减小了第二连接线与数据信号线之间因电容耦合产生的干扰。本公开通过在第二源漏金属层中设置屏蔽电极，屏蔽电极一方面可以阻挡发光器件的发光和膜层反射光照射到氧化物晶体管，可以防止氧化物晶体管因光照发生特性漂移，提高了氧化物晶体管的电学特性，屏蔽电极另一方面可以有效屏蔽数据电压跳变和其它信号对像素驱动电路中第二节点N2的影响，避免了数据电压跳变和其它信号影响第二节点N2的电位，有效避免了串扰恶化，而且可以避免因部分电路单元设置第二连接线而部分电路单元没有设置第二连接线产生的显示差异，提高了显示效果。本公开通过在显示区域形成网络连通结构的第二初始信号线，不仅可以最大限度地降低了初始信号线的电阻，减小了初始电压的压降，有效提升了显示基板中初始电压的均一性，有效提升了信号面内的均一性，有效提升了显示均一性，而且使得复位阶段中像素驱动电路的第四节点(阳极)的电位更均匀，发光器件起亮速度更容易保持一致，提高了显示品质和显示质量。本公开通过将屏蔽电极设置在第二源漏金属层，第一电源线设置在第三源漏金属层，有效减小了阳极与第一电源线的交叠面积，有效减小了像素驱动电路第四节点N4的寄生电容，提高了发光器件的起亮速度。本公开通过在显示区域内设置电源走线，实现了VSS in pixel的结构，可以大幅度减小边框电源引线的宽度，大大缩减了左右边框宽度，提高了屏占比，有利于实现全面屏显示。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图32为本公开实施例另一种显示基板的平面结构示意图。如图12所示，本示例性实施例显示基板的主体结构与前述实施例显示基板的主体结构基本上相近，所不同的是，至少一条第二连接线80与相邻的数据信号线60在第一方向X上的最小距离L1，可以约为相邻单元列中两条数据信号线60在第一方向X上的最小距离L3的1/2，至少一条电源走线90与相邻的数据信号线60在第一方向X上的最小距离L2，可以约为相邻单元列中两条数据信号线60在第一方向X上的最小距离L3的1/2。
在示例性实施方式中，图8所示显示基板中第二连接线80设置在相邻单元列中间距较远的两条数据信号线60之间，图32所示显示基板中第二连接 线80设置在相邻单元列中间距较近的两条数据信号线60之间。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括显示区域，所述制备方法包括：
在所述显示区域的基底上形成驱动结构层，所述驱动结构层至少包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、多条沿着第一方向延伸的第一连接线和多条沿着第二方向延伸的第二连接线，所述第一方向和所述第二方向交叉；所述电路单元包括像素驱动电路，至少一条数据信号线与一个单元列的多个像素驱动电路连接，多条第一连接线的第一端与多条数据信号线对应连接，多条第一连接线的第二端与多条第二连接线对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，所述中心线是位于相邻单元列之间且沿着所述第二方向延伸的直线，所述第二连接线设置在相邻单元列的像素驱动电路之间的间隙处。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种显示基板，包括显示区域，所述显示区域包括设置在基底上的驱动结构层，所述驱动结构层至少包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、多条沿着第一方向延伸的第一连接线和多条沿着第二方向延伸的第二连接线，所述第一方向和所述第二方向交叉；所述电路单元包括像素驱动电路，至少一条数据信号线与一个单元列的多个像素驱动电路连接，多条第一连接线的第一端与多条数据信号线对应连接，多条第一连接线的第二端与多条第二连接线对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，所述中心线是位于相邻单元列之间且沿着所述第二方向延伸的直线，所述第二连接线设置在相邻单元列的像素驱动电路之间的间隙处。
  2. 根据权利要求1所述的显示基板，其中，至少一个相邻单元列中的两条数据信号线相对于所述第二连接线镜像对称，所述第二连接线与相邻的数据信号线在所述第一方向上的最小距离，大于相邻单元列中两条数据信号线在所述第一方向上的最小距离。
  3. 根据权利要求1所述的显示基板，其中，至少一个相邻单元列中的两条数据信号线相对于所述第二连接线镜像对称，所述第二连接线与相邻的数据信号线在所述第一方向上的最小距离，为相邻单元列中两条数据信号线在所述第一方向上的最小距离的1/2。
  4. 根据权利要求1所述的显示基板，其中，所述驱动结构层还包括多条沿着所述第二方向延伸的电源走线，所述电源走线设置在相邻单元列的像素驱动电路之间的间隙处。
  5. 根据权利要求4所述的显示基板，其中，至少一个相邻单元列中的两条数据信号线相对于所述电源走线镜像对称，所述电源走线与相邻的数据信号线在所述第一方向上的最小距离，大于相邻单元列中两条数据信号线在所述第一方向上的最小距离。
  6. 根据权利要求4所述的显示基板，其中，至少一个相邻单元列中的两条数据信号线相对于所述电源走线镜像对称，所述电源走线与相邻的数据信 号线在所述第一方向上的最小距离，为相邻单元列中两条数据信号线在所述第一方向上的最小距离的1/2。
  7. 根据权利要求1至6任一项所述的显示基板，其中，在垂直于显示基板的平面上，所述驱动结构层包括在基底上依次设置的多个导电层，所述第一连接线和第二连接线设置在不同的导电层中，所述数据信号线和所述第二连接线设置在相同的导电层中。
  8. 根据权利要求7所述的显示基板，其中，所述多个导电层至少包括沿着远离所述基底的方向依次设置的第一源漏金属层、第二源漏金属层和第三源漏金属层，所述第一连接线设置在所述第二源漏金属层中，所述数据信号线和所述第二连接线设置在所述第三源漏金属层中，所述数据信号线通过过孔与所述第一连接线的第一端连接，所述第二连接线通过过孔与所述第一连接线的第二端连接。
  9. 根据权利要求8所述的显示基板，其中，所述像素驱动电路至少包括第一晶体管、第二晶体管和存储电容，所述第一晶体管至少包括第一有源层，所述第二晶体管至少包括第二有源层，所述第一有源层的第二区和所述第二有源层的第一区为相互连接的一体结构，且通过第一连接电极与所述存储电容的第一极板连接；所述第二源漏金属层还包括屏蔽电极，所述屏蔽电极在所述基底上的正投影与所述第一有源层的第二区和所述第二有源层的第一区在所述基底上的正投影至少部分交叠，所述屏蔽电极在所述基底上的正投影与所述第一连接电极在所述基底上的正投影至少部分交叠。
  10. 根据权利要求9所述的显示基板，其中，所述第三源漏金属层还包括第一电源线，所述第一电源线通过过孔与所述屏蔽电极连接。
  11. 根据权利要求10所述的显示基板，其中，在垂直于显示基板的平面上，所述显示基板还包括设置在所述驱动结构层远离所述基底一侧的发光结构层，所述发光结构层包括多个发光单元，所述发光单元至少包括阳极；至少一个发光单元中，所述阳极在所述基底上的正投影与所述第一电源线在所述基底上的正投影至少部分交叠，所述阳极在所述基底上的正投影与所述屏蔽电极在所述基底上的正投影至少部分交叠。
  12. 根据权利要求11所述的显示基板，其中，至少一个发光单元中，所述阳极在所述基底上的正投影与所述第一电源线在所述基底上的正投影具有第一交叠区域，所述阳极在所述基底上的正投影与所述屏蔽电极在所述基底上的正投影具有第二交叠区域，所述第一交叠区域的面积小于所述第二交叠区域的面积。
  13. 根据权利要求1至6任一项所述的显示基板，其中，所述像素驱动电路至少包括第四晶体管，所述第四晶体管的第一极通过数据连接电极与所述数据信号线连接，至少一个电路单元中，所述第一连接线与所述数据连接电极连接。
  14. 根据权利要求13所述的显示基板，其中，至少一个电路单元还包括数据连接块，所述数据连接块的第一端与所述第一连接线连接，所述数据连接块的第二端与所述数据连接电极连接。
  15. 根据权利要求14所述的显示基板，其中，至少一个电路单元中，所述第一连接线、所述数据连接电极和所述数据连接块同层设置，且为相互连接的一体结构。
  16. 根据权利要求1至6任一项所述的显示基板，其中，至少一个电路单元还可以包括沿着所述第一方向延伸的第二初始信号线和沿着所述第二方向延伸的第二初始连接线，所述第二初始连接线设置在所述第二方向相邻的两条第二初始信号线之间，且分别与两条第二初始信号线连接，在所述显示区域构成网络连通结构的第二初始信号线。
  17. 根据权利要求16所述的显示基板，其中，所述第二初始连接线设置在奇数单元列中，或者，所述第二初始连接线设置在偶数单元列中。
  18. 根据权利要求16所述的显示基板，其中，相邻的两个单元行中，一个单元行中所述第二初始连接线所在的单元列与另一个单元行中所述第二初始连接线所在的单元列不同。
  19. 根据权利要求16所述的显示基板，其中，所述第二初始信号线和所述第二初始连接线同层设置，且为相互连接的一体结构。
  20. 根据权利要求1至6任一项所述的显示基板，其中，所述像素驱动 电路至少包括存储电容和多个晶体管，所述多个导电层包括沿着远离基底方向依次设置的遮挡层、第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层、第二源漏金属层和第三源漏金属层；所述遮挡层至少包括遮挡电极，所述第一半导体层至少包括多个低温多晶硅晶体管的有源层，所述第一栅金属层至少包括第一扫描信号线、发光信号线和存储电容的第一极板，所述第二栅金属层至少包括存储电容的第二极板，所述第二半导体层至少包括多个氧化物晶体管的有源层，所述第三栅金属层至少包括第二扫描信号线和第三扫描信号线，所述第一源漏金属层至少包括网络连通结构的第二初始信号线，所述第二源漏金属层至少包括屏蔽电极和所述第一连接线，所述第三源漏金属层至少包括第一电源线、所述数据信号线和所述第二连接线。
  21. 根据权利要求20所述的显示基板，其中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管，所述第一晶体管和第二晶体管为氧化物晶体管，所述第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管为低温多晶硅晶体管。
  22. 一种显示装置，包括如权利要求1至21任一项所述的显示基板。
  23. 一种显示基板的制备方法，所述显示基板包括显示区域，所述制备方法包括：
    在所述显示区域的基底上形成驱动结构层，所述驱动结构层至少包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸的数据信号线、多条沿着第一方向延伸的第一连接线和多条沿着第二方向延伸的第二连接线，所述第一方向和所述第二方向交叉；所述电路单元包括像素驱动电路，至少一条数据信号线与一个单元列的多个像素驱动电路连接，多条第一连接线的第一端与多条数据信号线对应连接，多条第一连接线的第二端与多条第二连接线对应连接；相邻单元列中的像素驱动电路相对于中心线镜像对称，所述中心线是位于相邻单元列之间且沿着所述第二方向延伸的直线，所述第二连接线设置在相邻单元列的像素驱动电路之间的间隙处。
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Publication number Priority date Publication date Assignee Title
CN109791745A (zh) * 2016-09-27 2019-05-21 夏普株式会社 显示面板
CN114784082A (zh) * 2022-06-15 2022-07-22 京东方科技集团股份有限公司 显示基板和显示装置
CN114937686A (zh) * 2022-05-19 2022-08-23 京东方科技集团股份有限公司 显示基板及其驱动方法、显示装置
CN115004376A (zh) * 2022-04-29 2022-09-02 京东方科技集团股份有限公司 显示基板及显示装置
CN115398641A (zh) * 2022-04-28 2022-11-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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CN109791745A (zh) * 2016-09-27 2019-05-21 夏普株式会社 显示面板
CN115398641A (zh) * 2022-04-28 2022-11-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115004376A (zh) * 2022-04-29 2022-09-02 京东方科技集团股份有限公司 显示基板及显示装置
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