WO2023000125A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023000125A1
WO2023000125A1 PCT/CN2021/106995 CN2021106995W WO2023000125A1 WO 2023000125 A1 WO2023000125 A1 WO 2023000125A1 CN 2021106995 W CN2021106995 W CN 2021106995W WO 2023000125 A1 WO2023000125 A1 WO 2023000125A1
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WIPO (PCT)
Prior art keywords
line
data
layer
signal line
display substrate
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Application number
PCT/CN2021/106995
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English (en)
French (fr)
Inventor
王世龙
青海刚
于子阳
肖云升
宋江
蒋志亮
胡明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001917.1A priority Critical patent/CN114730538B/zh
Priority to PCT/CN2021/106995 priority patent/WO2023000125A1/zh
Publication of WO2023000125A1 publication Critical patent/WO2023000125A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • This article relates to but not limited to the field of display technology, and specifically relates to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • the present disclosure provides a display substrate, including a driving circuit layer disposed on a substrate, the driving circuit layer including a plurality of circuit units, at least one circuit unit of the plurality of circuit units includes a pixel driving circuit, A first power line that provides power signals to the pixel drive circuit, a data signal line that provides data signals to the pixel drive circuit, and a data fan-out line connected to the data signal line; the first power line, the At least part of the data signal line and the data fan-out line extend along the second direction and are arranged at intervals along the first direction, at least part of the data fan-out line is arranged between the first power supply line and the data signal line , the first direction intersects with the second direction.
  • the data fan-out line is connected to the data signal line through a via hole.
  • the orthographic projection of the portion of the data fan-out line extending along the second direction in the plane of the display substrate does not overlap with the orthographic projection of the first power line in the plane of the display substrate In the region, the orthographic projection of the portion of the data fan-out line extending along the second direction in the plane of the display substrate does not overlap with the orthographic projection of the main part of the data signal line in the plane of the display substrate.
  • the data fan-out lines include at least first data fan-out lines, the first data fan-out lines extend along the second direction, at least part of the first data fan-out lines are arranged on the Between the first power line and the data signal line.
  • At least one circuit unit further includes an initial signal line that supplies an initial signal to the pixel driving circuit, and the initial signal line includes a first initial signal line whose main body part extends along the first direction and a main body An initial signal connection line partially extending along the second direction, the initial signal connection line is connected to the first initial signal line; the orthographic projection of at least one data fan-out line in the plane of the display substrate is connected to the initial signal line The orthographic projections of the connection lines in the plane of the display substrate at least partially overlap.
  • the initial signal connection line is connected to the first initial signal line through a via hole.
  • the data fan-out lines include at least second data fan-out lines, the second data fan-out lines extend along the second direction, and the second data fan-out lines in the plane of the display substrate
  • the orthographic projection at least partially overlaps the orthographic projection of the initial signal connection line in the plane of the display substrate.
  • the data fan-out line includes at least a third data fan-out line, the third data fan-out line extends along the first direction, the third data fan-out line is identical to the first data fan-out line or the second data fan-out line connection.
  • the display substrate includes a display area and a binding area located on one side of the display area, and the first power line, the data signal line, and the data fan-out line are arranged on the display area.
  • the bonding area includes at least one lead-out line; the first end of the data fan-out line is connected to the data signal line, and the second end of the data fan-out line is connected to the lead-out line.
  • the driving circuit layer in a plane perpendicular to the display substrate, includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged on the substrate, between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer are all provided with An insulating layer; the data signal line and the data fan-out line are arranged in different conductive layers.
  • the first power supply line and the data signal line are disposed in the third conductive layer, and the data fan-out lines are disposed in the fourth conductive layer.
  • the driving circuit layer further includes a first initial signal line whose main body extends along the first direction and an initial signal connection line whose main body extends along the second direction, the first initial The signal line and the initial signal connection line are disposed in different conductive layers, and the initial signal connection line is connected to the first initial signal line through a via hole.
  • the first initial signal line is disposed in the second conductive layer, and the initial signal connection line is disposed in the third conductive layer.
  • the initial signal connection line is connected to the first region of the active layer of the first transistor in the pixel driving circuit through a via hole.
  • the initial signal connection line includes a first line segment and a second line segment connected to each other, the first line segment is a straight line segment extending along the second direction, and the second line segment is a broken line segment, and the orthographic projection of the first line segment in the plane of the display substrate at least partially overlaps the orthographic projection of the second data fan-out line in the plane of the display substrate.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate. Described preparation method comprises:
  • a driving circuit layer is formed on the substrate; the driving circuit layer includes a plurality of circuit units, at least one circuit unit in the plurality of circuit units includes a pixel driving circuit, and a first power line that provides a power signal to the pixel driving circuit , a data signal line that provides data signals to the pixel driving circuit, and a data fan-out line connected to the data signal line; at least part of the first power line, the data signal line, and the data fan-out line are along The second direction extends and is arranged at intervals along the first direction, at least part of the data fan-out lines are arranged between the first power supply line and the data signal line, and the first direction crosses the second direction .
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 5 is a working timing diagram of a pixel driving circuit
  • FIG. 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a data signal line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of data fan-out lines in a driving circuit layer according to an exemplary embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a driving circuit layer according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the present disclosure showing a semiconductor layer pattern formed on a substrate
  • FIG. 11a is a schematic diagram of the present disclosure showing that the substrate is patterned with a first conductive layer
  • Figure 11b is a schematic plan view of the first conductive layer in Figure 11a;
  • FIG. 12a is a schematic diagram of the present disclosure showing that the second conductive layer pattern is formed on the substrate
  • Figure 12b is a schematic plan view of the second conductive layer in Figure 12a;
  • FIG. 13a is a schematic diagram of the present disclosure showing a substrate after forming a pattern of a fourth insulating layer
  • Fig. 13b is a schematic plan view of a plurality of via holes in Fig. 13a;
  • FIG. 14a is a schematic diagram of the present disclosure showing that a third conductive layer pattern is formed on a substrate
  • Figure 14b is a schematic plan view of the third conductive layer in Figure 14a;
  • FIG. 15a is a schematic diagram of the present disclosure showing a fifth insulating layer pattern formed on a substrate
  • Fig. 15b is a schematic plan view of a plurality of via holes in Fig. 15a;
  • FIG. 16a is a schematic diagram of the present disclosure showing that the fourth conductive layer pattern is formed on the substrate
  • Figure 16b is a schematic plan view of the fourth conductive layer in Figure 16a;
  • FIG. 17a is a schematic diagram of the present disclosure showing that the sixth insulating layer pattern is formed on the substrate;
  • Fig. 17b is a schematic plan view of a plurality of via holes in Fig. 17a;
  • FIG. 18a is a schematic diagram of the present disclosure showing that the fifth conductive layer pattern is formed on the substrate
  • Figure 18b is a schematic plan view of the fifth conductive layer in Figure 18a;
  • FIG. 19a is a schematic diagram of the present disclosure showing that the substrate is formed with a first planar layer pattern
  • Fig. 19b is a schematic plan view of a plurality of via holes in Fig. 19a;
  • Fig. 20a is a schematic diagram of the present disclosure showing that the substrate is formed with an anode pattern
  • Fig. 20b is a schematic plan view of the anode in Fig. 20a.
  • 100 display area
  • 101 substrate
  • 102 drive circuit layer
  • 103 light emitting structure layer
  • 104 encapsulation layer
  • 200 binding area
  • 201 lead area
  • 202 bending area
  • 210 transistor
  • 211 storage capacitor
  • 300 frame area
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 the first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged, and “source terminal” and “drain terminal” can be interchanged.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array, the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively, and the data driver is connected to a plurality of data signal lines respectively.
  • the scanning drivers are respectively connected to a plurality of scanning signal lines (S1 to Sm)
  • the light emitting drivers are respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light emitting signal line and a pixel driving circuit.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver.
  • the driver can supply a clock signal, an emission stop signal, etc.
  • the data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light emitting driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting driver can be configured in the form of a shift register, and can generate emission signals in a manner of sequentially transmitting emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits light of the first color, and a first sub-pixel P1 that emits light of the second color.
  • each of the four sub-pixels may include circuit units and light emitting devices, and the circuit units may include scanning signal lines, data signal lines and The light emitting signal line and the pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to receive the signal transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line The data voltage is used to output a corresponding current to the light emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • four sub-pixels may be arranged in a square (Square) manner to form a GGRB pixel arrangement.
  • the four sub-pixels may be arranged horizontally, vertically, or in a diamond shape, which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal arrangement, a vertical arrangement, or a pattern, which is not limited in the present disclosure.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction is called a pixel row
  • a plurality of sub-pixels arranged in sequence in the vertical direction are called a pixel column
  • a plurality of pixel rows and a plurality of pixel columns constitute a pixel array arranged in an array .
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base, and a light-emitting structure layer 103 disposed on the base 102.
  • Layer 103 is away from the encapsulation layer 104 on the side of the substrate.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and storage capacitors. In FIG. 3 , only one driving transistor 210 and one storage capacitor 211 are taken as examples for illustration.
  • the light-emitting structure layer 103 of each sub-pixel may include multiple film layers that constitute a light-emitting device, and the multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 communicates with the drive transistor 210 through a via hole.
  • the drain electrode is connected, the organic light emitting layer 303 is connected to the anode 301 , the cathode 304 is connected to the organic light emitting layer 303 , and the organic light emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of a corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short), and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together
  • all The hole blocking layer of the sub-pixels can be a common layer connected together, and the light-emitting layer and the electron blocking layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected with 8 signal lines (data signal line D, first scan The signal line S1, the second scanning signal line S2, the light emitting signal line E, the first initial signal line INIT1, the second initial signal line INIT2, the first power line VDD and the second power line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor
  • the first pole of the second transistor T2, the control pole of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3 and the second terminal of the storage capacitor C.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the first initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the second initial voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or The amount of charges accumulated in the first pole of the light emitting device is released.
  • the light emitting device may be an OLED comprising a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode), or may be a QLED comprising a stacked first pole (anode) , a quantum dot light-emitting layer and a second pole (cathode).
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first transistor T1 to the seventh transistor T7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to realize low-frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 5 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 4.
  • the pixel driving circuit in FIG. signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD and second power line VSS), and the seven transistors are all P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, so that the first transistor T1 is turned on, and the first initial voltage of the first initial signal line INIT1 is supplied to the second node N2 to initialize the storage capacitor C and clear the storage capacitor Central original data voltage.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is supplied to the second node N2, and charge the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the second initial voltage of the second initial signal line INIT2 is supplied to the first pole of the OLED, the first pole of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure OLED Does not shine.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • a display substrate generally includes a display area and a binding area located on one side of the display area.
  • the binding area may at least include a first fan-out area, a bending area, and a driver chip area arranged in sequence along a direction away from the display area. and binding pin area.
  • the first fan-out area at least includes data fan-out lines, and a plurality of data fan-out lines are configured to connect data signal lines (Data Lines) of the display area in a fan-out (Fanout) routing manner.
  • the bending region may include a composite insulating layer provided with grooves configured to bend the binding region to the rear of the display region.
  • the driver chip area may include an integrated circuit (Integrated Circuit, IC for short), which is configured to be connected to a plurality of data fan-out lines.
  • the bonding pin area may include a bonding pad (Bonding Pad), which is configured to be bonded and connected to an external flexible circuit board (Flexible Printed Circuit, FPC for short).
  • the width of the binding area is smaller than the width of the display area, and the signal lines of the integrated circuit and the bonding pad in the binding area need to pass through the first fan-out area in a fan-out manner to be introduced into the wider display area.
  • the larger the width difference of the binding area the more oblique fan-out lines in the fan-shaped area, and the greater the distance between the driver chip area and the display area, so the fan-shaped area occupies a larger space, making the narrowing design of the lower frame more difficult. Large, the lower border has been maintained at around 2.0mm.
  • FIG. 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate 10 may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on the other side of the display area 100 .
  • the display area 100 may be a planarized area, including a plurality of sub-pixels Pxij constituting a pixel array, a plurality of data signal lines and a plurality of data fan-out lines, and the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images , the multiple data signal lines are configured to provide data signals to multiple sub-pixels Pxij, the multiple data fan-out lines are correspondingly connected to the multiple data signal lines, and are configured to make the multiple data signal lines pass through the multiple data fan-out lines and the bonding area 200
  • the multiple pinout lines in correspond to connections.
  • the display substrate may employ a flexible substrate, and thus the display substrate may be deformable, such as rolled, bent, folded, or rolled.
  • the display area 100 may include a plurality of pixel units arranged in a matrix, and at least one pixel unit may include a red sub-pixel R that emits red light, a blue sub-pixel B that emits blue light, and a sub-pixel that emits blue light.
  • the red sub-pixel R may include a red light-emitting device that emits red light and a red circuit unit connected to the red light-emitting device
  • the blue sub-pixel B may include a blue light-emitting device that emits blue light and a circuit unit connected to the blue light.
  • the blue circuit unit connected to the color light-emitting device, the first green sub-pixel G1 may include a first green light-emitting device that emits green light and a first green circuit unit connected to the first green light-emitting device, and the second green sub-pixel G2 may include The second green light-emitting device that emits green light and the second green circuit unit connected to the second green light-emitting device, the red circuit unit, the blue circuit unit, the first green circuit unit and the second green circuit unit form a circuit unit group, Four circuit units in at least one circuit unit group may be arranged in a square manner.
  • a plurality of sub-pixels may form a plurality of pixel rows and a plurality of pixel columns
  • a plurality of circuit units may form a plurality of circuit unit rows and a plurality of circuit unit columns.
  • the sub-pixels mentioned in the present disclosure refer to the regions divided according to the light emitting devices
  • the circuit units mentioned in the present disclosure refer to the regions divided according to the pixel driving circuits.
  • the positions of both the sub-pixel and the circuit unit may correspond, or the positions of the sub-pixel and the circuit unit may not correspond.
  • the binding area 200 may include a wiring area 201, a bending area 202, a driver chip area and a binding pin area arranged in sequence along a direction away from the display area, the wiring area 201 is connected to the display area 100, The bending area 202 is connected to the lead area 201 .
  • the wiring area 201 may be provided with a plurality of lead-out lines parallel to each other, the plurality of lead-out lines extend along a direction away from the display area, and one end of the plurality of lead-out lines is connected to the plurality of data fan-out lines in the display area 100 Corresponding to the connection, the other ends of the plurality of lead-out lines are connected to the integrated circuit in the driving chip area across the bending area 202, so that the integrated circuit applies data signals to the data signal lines through the lead-out lines and the data fan-out lines.
  • the length in the vertical direction of the lead area is effectively reduced, and the width of the lower frame is greatly reduced, so that the widths of the upper frame, lower frame, left frame and right frame of the display device are similar , are all below 1.0mm, which increases the screen-to-body ratio and is conducive to the realization of a full-screen display.
  • Fig. 7 is a schematic structural diagram of a data signal line and a data fan-out line according to an exemplary embodiment of the present disclosure.
  • the display area 100 may include multiple data signal lines 42 and multiple data fan-out lines 50
  • the lead area 201 of the bonding area may include multiple lead-out lines 60 .
  • a plurality of data signal lines 42 may extend along the direction of the circuit unit column, and be arranged sequentially at set intervals along the direction of the circuit unit row.
  • the pixel driving circuits of all the circuit units in one circuit unit column are connected.
  • the first ends of the plurality of data fan-out lines 50 are correspondingly connected to the plurality of data signal lines 42, and the second ends of the plurality of data fan-out lines 50 are correspondingly connected to the plurality of lead-out lines 60 in the lead area 201, so that the display area 100 has multiple
  • the data signal lines 42 are correspondingly connected to the multiple lead-out lines 60 in the bonding area 200 through the multiple data fan-out lines 50 in the display area 100 .
  • the number of data fan-out lines and the number of data signal lines in the display area may be the same, and each data signal line is correspondingly connected to one lead-out line through a data fan-out line.
  • the number of data fan-out lines in the display area may be smaller than the number of data signal lines, a part of the data signal lines in the display area are connected to the lead-out lines through data fan-out lines, and the other part of the data signal lines are directly connected to the lead-out lines. It is not limited here.
  • the present disclosure provides a display substrate, including a driving circuit layer disposed on a substrate, the driving circuit layer including a plurality of circuit units, at least one circuit unit including a pixel driving circuit, a first circuit that provides a power signal to the pixel driving circuit A power line, a data signal line providing data signals to the pixel driving circuit, and a data fan-out line connected to the data signal line; at least one first power line, data signal line, and data fan-out line extend along a first direction, And arranged at intervals along the second direction, at least one data fan-out line is arranged between the first power supply line and the data signal line, and the first direction crosses the second direction.
  • the data fan-out line is connected to the data signal line through a via hole.
  • the orthographic projection of the data fan-out line in the plane of the display substrate has no overlapping area with the orthographic projection of the first power line in the plane of the display substrate, and the orthographic projection of the data fan-out line in the plane of the display substrate There is no overlapping area between the orthographic projection and the orthographic projection of the data signal line in the plane of the display substrate.
  • the data fan-out lines include at least a first data fan-out line, and the first data fan-out lines are disposed between the first power supply line and the data signal line.
  • At least one circuit unit further includes an initial signal line that supplies an initial signal to the pixel driving circuit, and the initial signal line includes a first initial signal line whose main body part extends along the first direction and a main body Part of the initial signal connection line extending along the second direction, the initial signal connection line is connected to the first initial signal line through a via hole; the orthographic projection of the data fan-out line in the display substrate plane is the same as the initial The orthographic projections of the signal connection lines in the plane of the display substrate overlap at least partially.
  • the initial signal connection line is connected to the first initial signal line through a via hole.
  • the data fan-out line includes at least a second data fan-out line, the orthographic projection of the second data fan-out line in the display substrate plane and the orthographic projection of the initial signal connection line in the display substrate plane overlap at least partially.
  • FIG. 8 is a schematic diagram of a data fan-out line in a driving circuit layer according to an exemplary embodiment of the present disclosure.
  • the driving circuit layer may include a plurality of circuit units, and the plurality of circuit units sequentially arranged along the first direction X are called circuit unit rows.
  • a plurality of circuit units sequentially arranged in the second direction Y is called a circuit unit column, a plurality of circuit unit rows and a plurality of circuit unit columns constitute a circuit unit array arranged in an array, and the first direction X crosses the second direction Y.
  • the first direction X may be the extending direction (horizontal direction) of the scanning signal lines
  • the second direction Y may be the extending direction (vertical direction) of the data signal lines
  • the first direction X and the second direction Y can be perpendicular to each other.
  • At least one circuit unit row is provided with a first initial signal line 31 , and the first initial signal line 31 may extend along the first direction X.
  • At least one circuit unit column is provided with a first power line 41, a data signal line 42 and a data fan-out line 50, and the first power line 41, the data signal line 42 and the data fan-out line 50 may all extend along the second direction Y, and arranged at X intervals along the first direction.
  • the data fan-out line 50 in the second direction Y, can be arranged between the first power line 41 and the data signal line 42, and the orthographic projection of the data fan-out line 50 in the plane of the display substrate is the same as that of the first power line.
  • the orthographic projection of 41 in the plane of the display substrate has no overlapping area
  • the orthographic projection of the data fan-out line 50 in the plane of the display substrate has no overlapping area with the orthographic projection of the data signal line 42 in the plane of the display substrate.
  • FIG. 9 is a schematic structural diagram of a driving circuit layer according to an exemplary embodiment of the present disclosure, illustrating the planar structure of eight circuit units (two circuit unit rows and four circuit unit columns), which is an enlarged view of area A in FIG. 7 . As shown in FIG.
  • At least one circuit unit may include: a first scanning signal line 21, a second scanning signal line 22, a light emitting signal line 23, a first initial signal line 31, a second The initial signal line 32, the first power line 41, the data signal line 42, the initial signal connection line 43, the first data fan-out line 52, the second data fan-out line 53 and the pixel driving circuit, the pixel driving circuit may include a storage capacitor and 7
  • the seven transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and the third transistor may be a driving transistor.
  • the body portions of the first scanning signal line 21 , the second scanning signal line 22 , the light emitting signal line 23 , the first initial signal line 31 and the second initial signal line 32 may extend along the first direction X.
  • the main parts of the first power line 41 , the data signal line 42 , the initial signal connection line 43 , the first data fan-out line 52 and the second data fan-out line 53 may extend along the second direction Y.
  • the driving circuit layer may at least include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate.
  • the semiconductor layer may include an active layer of a plurality of transistors
  • the first conductive layer may include a first scan signal line 21, a second scan signal line 22, gate electrodes of the plurality of transistors, and a first electrode of a storage capacitor.
  • the second conductive layer can include the first initial signal line 31, the second initial signal line 32 and the second polar plate of the storage capacitor, and the third conductive layer can include the first power line 41, the data signal line 42, the initial The signal connection line 43 and the first pole and the second pole of the plurality of transistors, and the fourth conductive layer may include a first data fan-out line 52 and a second data fan-out line 53 .
  • the initial signal connection line 43 located in the third conductive layer may be connected to the first initial signal line 31 located in the second conductive layer through a via hole, so that the main body portion extends along the first direction X for the second
  • An initial signal line 31 and initial signal connection lines 43 extending along the second direction Y form a grid.
  • the first initial signal lines 31 in multiple circuit unit rows and multiple circuit unit columns have the same potential.
  • the driving circuit layer may include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, and the first insulating layer is disposed between the substrate and the semiconductor layer.
  • the second insulating layer is arranged between the semiconductor layer and the first conductive layer
  • the third insulating layer is arranged between the first conductive layer and the second conductive layer
  • the fourth insulating layer is arranged between the second conductive layer and the third conductive layer
  • the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.
  • the orthographic projection of the first data fan-out line 52 in the plane of the display substrate is consistent with the first power supply line.
  • the orthographic projection of the line 41 in the plane of the display substrate has no overlapping area
  • the orthographic projection of the first data fan-out line 52 in the plane of the display substrate has no overlapping area with the orthographic projection of the main part of the data signal line 42 in the plane of the display substrate.
  • the main part of the line 42 refers to the part of the data signal line 42 extending along the second direction Y.
  • the orthographic projection of the second data fan-out line 53 in the plane of the display substrate at least partially overlaps the orthographic projection of the original signal connection line 43 in the plane of the display substrate.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A , or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the preparation process of the driving circuit layer may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate.
  • the semiconductor layer on the first insulating layer is shown in FIG. 10 .
  • the semiconductor layer of each circuit unit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17
  • the active layer 17 is an integral structure connected to each other, and the sixth active layer 16 of the circuit unit in the M row in each circuit unit column is connected to the seventh active layer 17 of the circuit unit in the M+1 row, that is, each The semiconductor layers of adjacent circuit units in the circuit unit column are connected to each other as an integral structure.
  • the first active layer 11, the second active layer 12, the fourth active layer 14, and the seventh active layer 17 in the Mth row of circuit units are located in the third active layer of the current circuit unit.
  • Layer 13 is away from the side of the circuit unit in the M+1th row, and the first active layer 11 and the seventh active layer 17 are located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13
  • the fifth active layer 15 and the sixth active layer 16 in the Mth row of circuit units are located on the side of the third active layer 13 close to the M+1th row of circuit units.
  • the shape of the first active layer 11 may be "n"
  • the shape of the second active layer 12 may be "7”
  • the shape of the third active layer 13 may be "several”.
  • the shapes of the fourth active layer 14 and the seventh active layer 17 may be "1”
  • the shapes of the fifth active layer 15 and the sixth active layer 16 may be "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the second The first region 17-1 of the seven active layers 17 can be set independently, the second region 11-2 of the first active layer 11 is also used as the first region 12-1 of the second active layer 12, and the third active layer
  • the first region 13-1 of 13 serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15 at the same time, and the second region 13-2 of the third active layer 13 2 simultaneously serving as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 simultaneously serving as the seventh active
  • the second zone 17-2 of the layer 17 the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, and patterning the first conductive film through a patterning process to form The second insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scanning signal line 21, a second scanning signal line 22, and a light emission control line 23 and the first pole plate 24, as shown in Figure 11a and Figure 11b, Figure 11b is a schematic plan view of the first conductive layer in Figure 11a.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the main parts of the first scanning signal line 21 , the second scanning signal line 22 and the light emission control line 23 may extend along the first direction X.
  • the first scanning signal line 21 and the second scanning signal line 22 in the Mth row of circuit units can be located on the side of the first plate 24 of this circuit unit away from the M+1th row of circuit units, and the second scanning signal line 22 is located on the The first scanning signal line 21 of this circuit unit is away from the side of the first pole plate 24, and the light emission control line 23 may be located on the side of the first pole plate 24 of this circuit unit close to the circuit unit in the M+1th row.
  • the first plate 24 may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the first plate 24 on the substrate is consistent with the third active layer 13 of the third transistor T3 Orthographic projections on the substrate have overlapping regions.
  • the first plate 24 may serve as a plate of the storage capacitor and a gate electrode of the third transistor T3 at the same time.
  • the overlapping area of the first scanning signal line 21 and the second active layer 12 serves as the gate electrode of the second transistor T2, and the first scanning signal line 21 is provided with The raised gate block 21 - 1 , the orthographic projection of the gate block 21 - 1 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate, forming a second transistor T2 with a double gate structure.
  • the overlapping area of the first scanning signal line 21 and the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps with the first active layer 11 is used as the gate electrode of the first transistor T1 of the double gate structure, and the area where the second scanning signal line 22 overlaps with the seventh active layer 17 is used as the seventh
  • the semiconductor layer may be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the area blocked by the first conductive layer forms the first transistors T1 to the seventh In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are all conductorized.
  • forming the pattern of the second conductive layer may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, and forming A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least includes: a first initial signal line 31, a second initial signal line 32, a second initial signal line
  • the pole plate 33 and the shielding electrode 34 are shown in Fig. 12a and Fig. 12b, and Fig. 12b is a schematic plan view of the second conductive layer in Fig. 12a.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the main parts of the first initial signal line 31 and the second initial signal line 32 can extend along the first direction X, and the first initial signal line 31 in the Mth row of circuit units can be located in this circuit
  • the second initial signal line 32 may be located on the side of the second scanning signal line 22 of the circuit unit away from the first scanning signal line 21 .
  • the second plate 33 serves as another plate of the storage capacitor and is located between the first scanning signal line 21 and the light emission control line 23 of this circuit unit.
  • the shielding electrode 34 is located between the first scanning signal line 21 (not including the main part of the gate block 21-1) and the second initial signal line 32 of this circuit unit, and the shielding electrode 34 is configured to shield the critical node from the data voltage jump. The impact of the data voltage jump is avoided to affect the potential of the key node of the pixel driving circuit, and the display effect is improved.
  • the outline of the second pole plate 33 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second pole plate 33 on the base is the same as that of the first pole plate 24 on the base. There is an overlapping area in the orthographic projection, and the first pole plate 24 and the second pole plate 33 constitute the storage capacitor of the pixel driving circuit.
  • An opening 35 is disposed on the second pole plate 33 , and the opening 35 may be located in the middle of the second pole plate 33 .
  • the opening 35 may be rectangular, so that the second pole plate 33 forms a ring structure.
  • the opening 35 exposes the third insulating layer covering the first pole plate 24, and the orthographic projection of the first pole plate 24 on the base includes the orthographic projection of the opening 35 on the base.
  • the opening 35 is configured to accommodate the subsequently formed first via hole, the first via hole is located in the opening 35 and exposes the first electrode plate 24, so that the second electrode of the subsequently formed first transistor T1 Connect with the first pole plate 24.
  • the second pole plates 33 of adjacent circuit units in the first direction X or the opposite direction of the first direction X can be connected by a plate connection line, and the first end of the plate connection line is connected to the circuit.
  • the second pole plate 33 of the unit is connected, and the second end of the pole plate connection line extends along the first direction X or the opposite direction of the first direction X, and is connected with the second pole plate 33 of the adjacent circuit unit, that is, the pole plate
  • the connecting wires are configured to connect the second plates 33 of adjacent circuit units in a row of circuit units to each other.
  • the second pole plates of multiple circuit units in a circuit unit row can form an integrated structure connected to each other through the plate connection lines, and the second plate of the integrated structure can be reused as a power signal connection line to ensure that multiple second plates in one circuit unit row have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • each circuit unit is provided with a plurality of via holes, and the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole Via V5, sixth via V6, seventh via V7, eleventh via V11, ninth via V9, tenth via V10 and eleventh via V11, as shown in Figure 13a and Figure 13b ,
  • FIG. 13b is a schematic plan view of a plurality of via holes in FIG. 13a.
  • the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening 35 of the second plate 33 on the substrate, and the fourth insulation in the first via hole V1 layer and the third insulating layer are etched away, exposing the surface of the first plate 24 .
  • the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second plate 33 on the substrate, and the fourth insulating layer in the second via hole V2 is etched away. , exposing the surface of the second pole plate 33 .
  • the second via hole V2 is configured to connect the subsequently formed first power line to the second plate 33 through the via hole.
  • the second via hole V2 serving as a power supply via hole may include a plurality of second via holes V2 arranged in sequence along the second direction Y, so as to increase the number of connections between the first power line and the second plate. 33% connection reliability.
  • the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer in the third via hole V3 layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer.
  • the third via hole V3 is configured to connect the subsequently formed first power line to the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is within the range of the orthographic projection of the sixth active layer on the substrate, and the fourth insulating layer and the third insulating layer in the fourth via hole V4 layer and the second insulating layer are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer).
  • the fourth via hole V4 is configured such that the second pole of the subsequently formed sixth transistor T6 is connected to the sixth active layer through the via hole, and the second pole of the subsequently formed seventh transistor T7 is connected to the sixth active layer through the via hole. Seven active layer connections.
  • the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the fourth active layer on the substrate, and the fourth insulating layer and the third insulating layer in the fifth via hole V5 layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer.
  • the fifth via hole V5 is configured to connect the subsequently formed data signal line to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second active layer on the substrate, and the fourth insulating layer and the third insulating layer in the sixth via hole V6 layer and the second insulating layer are etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer).
  • the sixth via hole V6 is configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through the via hole, and connect the first pole of the subsequently formed second transistor T2 to the first active layer through the via hole. Two active layer connections.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate, and the fourth insulating layer and the third insulating layer in the seventh via hole V7 layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer.
  • the seventh via hole V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the first active layer on the substrate, and the fourth insulating layer and the third insulating layer in the eighth via hole V8 layer and the second insulating layer are etched away, exposing the surface of the first region of the first active layer.
  • the eighth via hole V8 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first active layer through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer in the ninth via hole V9 is etched. drop, exposing the surface of the first initial signal line 31.
  • the ninth via hole V9 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 31 through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the second initial signal line 32 on the substrate, and the fourth insulating layer inside the tenth via hole V10 is etched. The surface of the second initial signal line 32 is exposed. The tenth via hole V10 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the second initial signal line 32 through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the shielding electrode 34 on the substrate, and the fourth insulating layer in the eleventh via hole V11 is etched away. , exposing the surface of the shielding electrode 34 .
  • the eleventh via hole V11 is configured to connect the subsequently formed first power line to the shielding electrode 34 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film by a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer, the third conductive layer at least includes: a first power line 41, a data signal line 42, an initial signal connection line 43, a first connection electrode 44, a second connection electrode 45 and a third connection electrode 46, as shown in the figure 14a and 14b, FIG. 14b is a schematic plan view of the third conductive layer in FIG. 14a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the main part of the first power line 41 can extend along the second direction Y.
  • the first power line 41 is connected to the second plate 33 through the second via hole V2, and on the other hand Connect to the fifth active layer through the third via hole V3, and connect to the shielding electrode 34 through the eleventh via hole V11 on the other hand, so that the shielding electrode 34 and the second electrode plate 33 have the same potential as the first power line 41 .
  • the shielding electrode 34 is connected to the first power line 41, and at least a partial area of the shielding electrode 34 (such as the vertical portion on the right side of the shielding electrode 34) is located on the first connection electrode 44 (as the second pole of the first transistor T1 and the second pole of the first transistor T1).
  • the influence of the data voltage jump on the key nodes in the pixel driving circuit can be effectively shielded, and the influence of the data voltage jump on the pixel driving circuit is avoided.
  • the potential of the key nodes improves the display effect.
  • the main part of the data signal line 42 may extend along the second direction Y, and the data signal line 42 is connected to the first region of the fourth active layer through the fifth via hole V5, thereby realizing the data signal Line 42 writes the data signal into the fourth transistor T4.
  • the initial signal connection line 43 may be in the shape of a zigzag line whose main body extends along the second direction Y. In each circuit unit, the initial signal connection line 43 connects with the first through the ninth via hole V9 on the one hand. The initial signal line 31 is connected, and on the other hand, it is connected to the first region of the first active layer through the eighth via hole V8. The initial signal connection line 43 can be used as the first pole of the first transistor T1, thus realizing the first initial signal Line 31 writes the first initial signal into the first transistor T1.
  • the initial signal connection line 43 may include a first line segment 43-1 and a second line segment 43-2 connected to each other, and the first line segment 43-1 may be a straight line extending along the second direction Y segment, the second line segment 43-2 may be a polyline segment.
  • the second line segment 43-2 may include a first sub-line segment 43-2A and a third sub-line segment 43-2C whose main body portion extends along the first direction X, and a main body portion extending along the second direction Y. Extended second sub-segment 43-2B.
  • the first end of the first sub-line segment 43-2A of the Mth circuit unit is connected to the first line segment 43-1 of the M-1th circuit unit, and the second end extends along the first direction X After that, it is connected with the first end of the second sub-line segment 43-2B, and after the second end of the second sub-line segment 43-2B extends along the second direction Y, it is connected with the first end of the third sub-line segment 43-2C.
  • the second ends of the three sub-line segments 43-2C extend along the direction opposite to the first direction X and are connected to the first line segment 43-1 of the current circuit unit.
  • the initial signal connection lines 43 of the circuit units in the Mth row in each circuit unit column are connected to the initial signal connection lines 43 of the circuit units in the M+1th row, that is, adjacent in each circuit unit column
  • the initial signal connection line 43 of the circuit unit is an integral structure connected to each other. Since the initial signal connection line 43 is connected to the first initial signal line 31 through the ninth via hole V9, the initial signal connection line 43 of the integrated structure can be multiplexed as a vertical initial signal line, and the first signal line extending along the first direction X An initial signal line 31 and an initial signal connection line 43 extending along the second direction Y form a grid.
  • the first initial signal line is connected to the first initial signal line by setting the initial signal connection line, so that the first initial signal line forms a network structure, and the multiple first initial signal lines 31 in multiple circuit unit rows and multiple circuit unit columns have the same potential, which not only effectively reduces the resistance of the first initial signal line, reduces the voltage drop of the first initial voltage, but also effectively improves the uniformity of the first initial voltage in the display substrate, effectively improves the display uniformity, and improves the Display Quality and Display Quality.
  • the first connection electrode 44 may be in the shape of a straight line extending along the second direction Y, and its first end is connected to the second region of the first active layer (which is also the second active layer) through the sixth via hole V6.
  • the first region of the source layer) is connected, and its second end is connected to the first plate 24 through the first via hole V1, so that the first plate 24, the second pole of the first transistor T1 and the first electrode of the second transistor T2 poles have the same potential.
  • the first connection electrode 44 may function as a second pole of the first transistor T1 and a first pole of the second transistor T2.
  • the second connection electrode 45 may be in the shape of a straight line extending along the second direction Y, its first end is connected to the second initial signal line 32 through the tenth via hole V10 , and its second end is connected through the first
  • the seven vias V7 are connected to the first region of the seventh active layer, and the second connection electrode 45 can be used as the first electrode of the seventh transistor T7, thus realizing the writing of the second initial signal into the seventh transistor T7 by the second initial signal line 32 Transistor T7.
  • the third connection electrode 46 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second region of the sixth transistor T6 The pole and the second pole of the seventh transistor T7 have the same potential.
  • the third connection electrode 46 may function as a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7.
  • the third connection electrode 46 is configured to be connected to a subsequently formed first anode connection electrode.
  • the first power line 41 of each circuit unit can be designed with a non-uniform width, and the first power line 41 with a non-equal width design can not only facilitate the layout of the pixel structure, but also reduce the size of the first power line. and the parasitic capacitance between the data signal lines.
  • the shapes of the first power line 41, the data signal line 42, the initial signal connection line 43, the first connection electrode 44, the second connection electrode 45, and the third connection electrode 46 of each circuit unit may be the same, Or it may be different, and the disclosure is not limited here.
  • Forming a fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film by a patterning process to form a pattern covering the third conductive layer.
  • the fifth insulating layer, the fifth insulating layer is provided with a plurality of via holes, and the plurality of via holes include at least the twelfth via hole V12, as shown in Figure 15a and Figure 15b, Figure 15b is a diagram of the plurality of via holes in Figure 15a Schematic plan view.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the third connection electrode 46 on the substrate, and the fifth insulating layer in the twelfth via hole V12 is removed, exposing the surface of the third connection electrode 46 , and the twelfth via hole V12 is configured so that the subsequently formed first anode connection electrode is connected to the third connection electrode 46 through the via hole.
  • the positions of the twelfth via holes V12 in each circuit unit may be the same or different, which is not limited in the present disclosure.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film by a patterning process, and forming a layer disposed on the fifth insulating layer.
  • the fourth conductive layer on the top, the fourth conductive layer at least includes: the first anode connection electrode 51, the first data fan-out line 52 and the second data fan-out line 53, as shown in Figure 16a and Figure 16b, Figure 16b is the A schematic plan view of the fourth conductive layer.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • a first anode connection electrode 51 may be provided in each circuit unit.
  • the first anode connection electrode 51 is connected to the third connection electrode 46 through the twelfth via hole V12 . Since the third connection electrode 46 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, the first anode connection electrode 51 is connected to the second region of the seventh active layer through the third connection electrode. 46 is connected to the second region of the sixth active layer (also the second region of the seventh active layer).
  • the first anode connection electrode 51 is configured to be connected to a subsequently formed second anode connection electrode.
  • the shape of the first anode connection electrode in the Nth column of circuit units may be the same as the shape of the first anode connection electrode in the N+2th column of circuit units, and the shape of the first anode connection electrode in the N+1th column of circuit units
  • the shape of the first anode connection electrode may be the same as that of the first anode connection electrode in the N+3th row of circuit units, and the shape of the first anode connection electrode may be rectangular.
  • the first data fan-out line 52 and the second data fan-out line 53 may be in the shape of a straight line whose main body extends along the second direction Y.
  • the first data fan-out line 52 is arranged at Between the first power supply line 41 and the data signal line 42, the orthographic projection of the first data fan-out line 52 on the substrate has no overlapping area with the orthographic projection of the first power supply line 41 on the substrate, and the first data fan-out line 52 is on the substrate. There is no overlapping area between the orthographic projection of the data signal line 42 and the orthographic projection of the main part of the data signal line 42 on the substrate.
  • the first data fan-out line is arranged above the first power line, that is, the orthographic projection of the first data fan-out line on the substrate is within the range of the orthographic projection of the first power supply line on the substrate.
  • the exemplary embodiment of the present disclosure arranges the first data fan-out line between the first power supply line and the data signal line, and the first data fan-out line does not overlap with the first power supply line and the data signal line, so that the first data fan-out line By avoiding the first power line, the parasitic capacitance between the first data fan-out line and the first power line is effectively reduced, and the crosstalk is effectively reduced.
  • the simulation structure shows that in the substrate structure of the exemplary embodiment of the present disclosure, the parasitic capacitance value between the first data fan-out line and the first power line can be reduced to below 6fF, and the degree of crosstalk is reduced by 30%.
  • the second data fan-out line 53 is arranged on the side of the first power supply line 41 away from the data signal line 42, and the orthographic projection of the second data fan-out line 53 on the substrate is consistent with the first signal connection line 43 in the initial signal connection line 43.
  • the orthographic projections of the line segment on the base at least partially overlap.
  • the exemplary embodiment of the present disclosure arranges the second data fan-out line in the area where the original signal connection line is located, and the orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the initial signal connection line on the substrate, so that the normal
  • the initial signal connection line of the pressure signal can shield the impact of the data voltage jump on the second data fan-out line on the pixel drive circuit, effectively reducing the impact of the data fan-out line on the potential of key nodes in the pixel drive circuit, and improving the display effect.
  • the circuit unit may only include the first data fan-out line 52, or the circuit unit may only include the second data fan-out line 53, or the circuit unit may include the first data fan-out line 52 and the second data fan-out line at the same time.
  • the fan-out line 53 is not limited in this disclosure.
  • the data fan-out lines in the display substrate may include third data fan-out lines extending along the first direction X, the third data fan-out lines may be connected to the first data fan-out lines, or the third data fan-out lines
  • the outgoing line can be connected to the second data fan-out line, or one third data fan-out line is connected to the first data fan-out line, another third data fan-out line is connected to the second data fan-out line, the first data fan-out line, the second data
  • the fan-out line or the third data fan-out line may be connected to the data signal line through a via hole, which is not limited in this disclosure.
  • Forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film by a patterning process to form a pattern covering the fourth conductive layer.
  • the sixth insulating layer is provided with a thirteenth via hole V13, as shown in FIG. 17a and FIG. 17b, and FIG. 17b is a schematic plan view of a plurality of via holes in FIG. 17a.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the first anode connection electrode 51 on the substrate, and the sixth insulation in the thirteenth via hole V13
  • the layer is removed to expose the surface of the first anode connection electrode 51 , and the thirteenth via hole V13 is configured so that the subsequently formed second anode connection electrode is connected to the first anode connection electrode 51 through the via hole.
  • the positions of the thirteenth vias V13 in each circuit unit may be the same or different, which is not limited by the present disclosure.
  • Forming a fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film by a patterning process, and forming a layer disposed on the sixth insulating layer.
  • the fifth conductive layer on the top, the fifth conductive layer at least includes: a second anode connection electrode 61, as shown in Figure 18a and Figure 18b, Figure 18b is a schematic plan view of the fifth conductive layer in Figure 18a.
  • the second anode connection electrode 61 may be provided in each circuit unit.
  • the second anode connection electrode 61 is connected to the first anode connection electrode 51 through the thirteenth via hole V13 . Since the first anode connection electrode 51 is connected to the third connection electrode 46 through the twelfth via hole V12, the third connection electrode 46 is connected to the second region of the sixth active layer (also the seventh active layer) through the fourth via hole V4.
  • the second region of the second region is connected, thereby realizing the connection between the second anode connection electrode 61 and the second region of the sixth active layer (also the second region of the seventh active layer) through the first anode connection electrode 51 and the third connection electrode 46 )connect.
  • the second anode connection electrode 61 is configured to be connected to a subsequently formed anode.
  • the shape of the anode connection electrode in the circuit unit of row M and column N may be the same as the shape of the second anode connection electrode in the circuit unit of row M+1 and column N+2.
  • the shape of the second anode connection electrode in the circuit unit in the Nth column of the 1st row can be the same as the shape of the second anode connection electrode in the N+2th column circuit unit in the Mth row, and the second anode connection electrode in the N+1th column circuit unit
  • the shape of the anode connection electrode may be the same as that of the second anode connection electrode in the N+3th row of circuit units, and the shape of the second anode connection electrode may be rectangular.
  • forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, and patterning the first planar film by a patterning process to form a fifth conductive layer covering
  • the first planar layer, the first planar layer is provided with a plurality of via holes, the plurality of via holes include at least the fourteenth via hole V14, as shown in Figure 19a and Figure 19b, Figure 19b is a plurality of via holes in Figure 19a floor plan.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is within the range of the orthographic projection of the second anode connection electrode 61 on the substrate, and the first flat surface in the fourteenth via hole V14
  • the layer is removed to expose the surface of the second anode connection electrode 61
  • the fourteenth via hole V14 is configured so that the subsequently formed anode is connected to the second anode connection electrode 61 through the via hole.
  • the driving circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a light emission control circuit connected to the pixel driving circuit. line, data signal line, first power line, first initial signal line and second initial signal line.
  • at least one circuit unit may include a first data fan-out line and/or a second data fan-out line, the first data fan-out line is disposed between the first power supply line and the data signal line, and the second data fan-out line
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the original signal connection line on the substrate.
  • the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a The four insulating layers, the third conducting layer, the fifth insulating layer, the fourth conducting layer, the sixth insulating layer, the fifth conducting layer and the first planar layer, the first data fan-out line and/or the second data fan-out line may be arranged on fourth conductive layer.
  • a light emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode pattern may include: depositing a sixth conductive film on the substrate on which the foregoing pattern is formed, and patterning the sixth conductive film by a patterning process to form an anode disposed on the first planar layer pattern, the anodes are arranged in a square manner to form a GGRB pixel arrangement, as shown in Figure 20a and Figure 20b, and Figure 20b is a schematic plan view of the anode in Figure 20a.
  • the anode pattern may include a red anode 301R of a red light-emitting device, a blue anode 301B of a blue light-emitting device, a first green anode 301G1 of a first green light-emitting device, and a first green anode 301G1 of a second green light-emitting device.
  • the area where the red anode 301R is located can form a red sub-pixel R that emits red light
  • the area where the blue anode 301B is located can form a blue sub-pixel B that emits blue light
  • the area where the first green anode 301G1 is located can form an outgoing sub-pixel
  • the first green sub-pixel G1 for green light, and the area where the second green anode 301G2 is located can form the second green sub-pixel G2 for emitting green light
  • the red sub-pixel R and blue sub-pixel B are arranged in sequence along the second direction Y.
  • a green sub-pixel G1 and a second green sub-pixel G2 are arranged in sequence along the second direction Y, and the first green sub-pixel G1 and the second green sub-pixel G2 are respectively arranged in the first direction of the red sub-pixel R and the blue sub-pixel B
  • the red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 form a pixel unit arranged in a square.
  • the red anode 301R is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via hole V14 in the Mth row and Nth column circuit unit, and the blue anode 301B Connect the second anode connection electrode 61 in the circuit unit through the fourteenth via hole V14 in the circuit unit in the Nth column of the M+1th row, and the first green anode 301G1 passes through the circuit unit in the N+1th column of the Mth row
  • the fourteenth via hole V14 in the circuit unit is connected to the second anode connection electrode 61 in the circuit unit, and the second green anode 301G2 is connected to the circuit unit through the fourteenth via hole V14 in the circuit unit in the M+1th row and the N+1th column.
  • the second anode connection electrode 61 in the cell is connected.
  • the red anode 301R is connected to the second anode connection electrode 61 in the circuit unit through the fourteenth via hole V14 in the circuit unit in the M+1th row and the N+2th column
  • the blue anode 301B is connected to the second anode connection electrode 61 in the circuit unit through the fourth
  • the fourteenth via hole V14 in the circuit unit in the N+2th column of the row M is connected to the second anode connection electrode 61 in the circuit unit, and the first green anode 301G1 passes through the circuit unit in the N+3th column of the M+1th row
  • the fourteenth via hole V14 in the circuit unit is connected to the second anode connection electrode 61 in the circuit unit
  • the second green anode 301G2 is connected to the circuit unit through the fourteenth via hole V14 in the circuit unit in the Mth row and the N+3 column.
  • the second anode connection electrode 61 is connected.
  • the anode of each is connected to the second region of the sixth active layer (which is also the seventh active layer) through the second anode connection electrode, the first anode connection electrode and the third connection electrode 46 in one circuit unit
  • the second region of the source layer is connected, so the four anodes in one pixel unit are respectively connected to the pixel driving circuits of the four circuit units in one circuit unit group, so that the pixel driving circuit can drive the light emitting device to emit light.
  • the shape and position of the two red anodes 301R connected to the pixel driving circuit in the circuit unit in the Nth column of the M row and the N+2th column circuit unit in the M+1 row are the same in shape and position, respectively.
  • the shape and position of the two blue anodes 301B connected to the pixel driving circuit in the N+1 row circuit unit and the M row N+2 column circuit unit are the same as those of the M row N+1 column circuit unit respectively.
  • the shape and position of the two first green anodes 301G1 connected to the pixel driving circuit in the N+3th row of the M+1th row and the N+3th row are the same as those of the M+1th row N+1th column circuit unit and the Mth row
  • the shapes and positions of the two second green anodes 301G2 connected to the pixel driving circuit in the N+3th column of circuit units are the same.
  • the shapes and areas of the red anode 301R, the blue anode 301B, the first green anode 301G1 and the second green anode 301G2 are different in one pixel unit.
  • the anode shapes and areas of the four sub-pixels in a pixel unit may be the same or different, and the positional relationship between the four sub-pixels in a pixel unit and the four circuit units in a circuit unit group may be the same, Or they may be different.
  • the shapes and positions of the red anode 301R, the blue anode 301B, the first green anode 301G1 and the second green anode 301G2 in different pixel units may be the same or different, which is not limited in this disclosure.
  • the subsequent manufacturing process may include: firstly forming a pixel definition layer pattern, the pixel definition layer pattern may include a red pixel opening exposing a red anode, a blue pixel opening exposing a blue anode, and a first pixel opening exposing a blue anode.
  • an organic light-emitting layer is formed by vapor deposition or inkjet printing process, the organic light-emitting layer is connected to the anode through the corresponding pixel opening, a cathode is formed on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al ) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be single-layer structure, or multi-layer composite structure, such as Mo/Cu/Mo etc.
  • the sixth conductive layer can adopt a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO/Ag/ITO and the like.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can use silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) ) in any one or more, can be a single layer, multi-layer or composite layer.
  • the first insulating layer is called the buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer and the third insulating layer are called the gate insulating (GI) layer, and the fourth insulating layer is called the interlayer insulation ( ILD) layer, fifth insulating layer and sixth insulating layer are called passivation (PVX) layer.
  • Buffer buffer
  • GI gate insulating
  • ILD interlayer insulation
  • PVX passivation
  • the first flat layer can be made of organic materials, such as resin.
  • the active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), Materials such as hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polysilicon
  • the present disclosure sets the data fan-out lines in the display area so that the lead-out lines in the binding area are connected to the data signal lines through the data fan-out lines, so that there is no need in the lead area
  • Setting fan-shaped oblique lines effectively reduces the length of the lead area in the vertical direction and greatly reduces the width of the lower frame, making the width of the upper frame, lower frame, left frame, and right frame of the display device similar, all of which are less than 1.0mm , which increases the screen-to-body ratio and facilitates the realization of a full-screen display.
  • the first data fan-out line avoids the first power line, effectively reducing the distance between the first data fan-out line and the first power line.
  • the parasitic capacitance between them effectively reduces crosstalk.
  • the orthographic projection of the second data fan-out line on the substrate at least partially overlaps with the orthographic projection of the initial signal connection line on the substrate, effectively reducing the number of data fan-out lines. It can affect the potential of key nodes in the pixel driving circuit and improve the display effect.
  • the initial signal connection line is connected to the first initial signal line through a via hole, so that the initial signal connection line and the first initial signal line form a network structure, which is not only effective
  • the resistance of the first initial signal line is reduced, the voltage drop of the first initial voltage is reduced, and the uniformity of the first initial voltage in the display substrate is effectively improved, the display uniformity is effectively improved, and the display quality and display quality are improved .
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the display substrate of the present disclosure can be applied in a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc., the disclosure is not limited here.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc.
  • first data fan-out line and the second data fan-out line may be disposed in different film layers.
  • first power line and the data signal line may be disposed in different film layers, which is not limited in this disclosure.
  • the present disclosure also provides a method for preparing a display substrate, so as to manufacture the display substrate provided by the above-mentioned embodiments.
  • the preparation method may include:
  • a driving circuit layer is formed on the substrate; the driving circuit layer includes a plurality of circuit units, at least one circuit unit in the plurality of circuit units includes a pixel driving circuit, and a first power line that provides a power signal to the pixel driving circuit , a data signal line that provides data signals to the pixel driving circuit, and a data fan-out line connected to the data signal line; at least part of the first power line, the data signal line, and the data fan-out line are along The second direction extends and is arranged at intervals along the first direction, at least part of the data fan-out lines are arranged between the first power supply line and the data signal line, and the first direction crosses the second direction .
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiment of the present invention is not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。所述显示基板包括设置在基底上的驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元中的至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信号的数据信号线以及与所述数据信号线连接的数据扇出线；所述第一电源线、所述数据信号线和所述数据扇出线中的至少部分沿第二方向延伸，并沿着第一方向间隔设置，至少部分所述数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括设置在基底上的驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元中的至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信号的数据信号线以及与所述数据信号线连接的数据扇出线；所述第一电源线、所述数据信号线和所述数据扇出线中的至少部分沿第二方向延伸，并沿着第一方向间隔设置，至少部分所述数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述数据扇出线通过过孔与所述数据信号线连接。
在示例性实施方式中，所述数据扇出线沿所述第二方向延伸的部分在所述显示基板平面内的正投影与所述第一电源线在所述显示基板平面内的正投 影没有重叠区域，所述数据扇出线沿所述第二方向延伸的部分在所述显示基板平面内的正投影与所述数据信号线的主体部分在所述显示基板平面内的正投影没有重叠区域。
在示例性实施方式中，所述数据扇出线至少包括第一数据扇出线，所述第一数据扇出线沿所述第二方向延伸，所述第一数据扇出线中的至少部分设置在所述第一电源线和所述数据信号线之间。
在示例性实施方式中，至少一个电路单元还包括向所述像素驱动电路提供初始信号的初始信号线，所述初始信号线包括主体部分沿所述第一方向延伸的第一初始信号线和主体部分沿所述第二方向延伸的初始信号连接线，所述初始信号连接线与所述第一初始信号线连接；至少一条数据扇出线在所述显示基板平面内的正投影与所述初始信号连接线在所述显示基板平面内的正投影至少部分交叠。
在示例性实施方式中，所述初始信号连接线通过过孔与所述第一初始信号线连接。
在示例性实施方式中，所述数据扇出线至少包括第二数据扇出线，所述第二数据扇出线沿所述第二方向延伸，所述第二数据扇出线在所述显示基板平面内的正投影与所述初始信号连接线在所述显示基板平面内的正投影至少部分交叠。
在示例性实施方式中，所述数据扇出线至少包括第三数据扇出线，所述第三数据扇出线沿所述第一方向延伸，所述第三数据扇出线与所述第一数据扇出线或所述第二数据扇出线连接。
在示例性实施方式中，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述第一电源线、所述数据信号线和所述数据扇出线设置在所述显示区域，所述绑定区域包括至少一个引出线；所述数据扇出线的第一端与所述数据信号线连接，所述数据扇出线的第二端与所述引出线连接。
在示例性实施方式中，在垂直于所述显示基板的平面内，所述驱动电路层包括在基底上依次设置的第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三 导电层之间以及所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据信号线和所述数据扇出线设置在不同的导电层中。
在示例性实施方式中，所述第一电源线和所述数据信号线设置在所述第三导电层中，所述数据扇出线设置在所述第四导电层中。
在示例性实施方式中，所述驱动电路层还包括主体部分沿所述第一方向延伸的第一初始信号线和主体部分沿所述第二方向延伸的初始信号连接线，所述第一初始信号线和所述初始信号连接线设置在不同的导电层中，所述初始信号连接线通过过孔与所述第一初始信号线连接。
在示例性实施方式中，所述第一初始信号线设置在所述第二导电层中，所述初始信号连接线设置在第三导电层中。
在示例性实施方式中，所述初始信号连接线通过过孔与所述像素驱动电路中第一晶体管的有源层第一区连接。
在示例性实施方式中，所述初始信号连接线包括相互连接的第一线段和第二线段，所述第一线段为沿着所述第二方向延伸的直线段，所述第二线段为折线段，所述第一线段在所述显示基板平面内的正投影与第二数据扇出线在所述显示基板平面内的正投影至少部分交叠。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法。所述制备方法包括：
在基底上形成驱动电路层；所述驱动电路层包括多个电路单元，所述多个电路单元中的至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信号的数据信号线以及与所述数据信号线连接的数据扇出线；所述第一电源线、所述数据信号线和所述数据扇出线中的至少部分沿第二方向延伸，并沿着第一方向间隔设置，至少部分所述数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为本公开示例性实施例一种显示基板的平面结构示意图；
图7为本公开示例性实施例数据信号线和数据扇出线的结构示意图；
图8为本公开示例性实施例驱动电路层中数据扇出线的示意图；
图9为本公开示例性实施例一种驱动电路层的结构示意图；
图10为本公开显示基板形成半导体层图案后的示意图；
图11a为本公开显示基板形成第一导电层图案后的示意图；
图11b为图11a中第一导电层的平面示意图；
图12a为本公开显示基板形成第二导电层图案后的示意图；
图12b为图12a中第二导电层的平面示意图；
图13a为本公开显示基板形成第四绝缘层图案后的示意图；
图13b为图13a中多个过孔的平面示意图；
图14a为本公开显示基板形成第三导电层图案后的示意图；
图14b为图14a中第三导电层的平面示意图；
图15a为本公开显示基板形成第五绝缘层图案后的示意图；
图15b为图15a中多个过孔的平面示意图；
图16a为本公开显示基板形成第四导电层图案后的示意图；
图16b为图16a中第四导电层的平面示意图；
图17a为本公开显示基板形成第六绝缘层图案后的示意图；
图17b为图17a中多个过孔的平面示意图；
图18a为本公开显示基板形成第五导电层图案后的示意图；
图18b为图18a中第五导电层的平面示意图；
图19a为本公开显示基板形成第一平坦层图案后的示意图；
图19b为图19a中多个过孔的平面示意图；
图20a为本公开显示基板形成阳极图案后的示意图；
图20b为图20a中阳极的平面示意图。
附图标记说明:
11—第一有源层；        12—第二有源层；        13—第三有源层；
14—第四有源层；        15—第五有源层；        16—第六有源层；
17—第七有源层；        21—第一扫描信号线；    22—第二扫描信号线；
23—发光控制线；        24—第一极板；          31—第一初始信号线；
32—第二初始信号线；    33—第二极板；          34—屏蔽电极；
35—开口；              41—第一电源线；        42—数据信号线；
43—初始信号连接线；    44—第一连接电极；      45—第二连接电极；
46—第三连接电极；      50—数据扇出线；        51—第一阳极连接电极；
52—第一数据扇出线；    53—第二数据扇出线；    61—第二阳极连接电极；
100—显示区域；         101—基底；             102—驱动电路层；
103—发光结构层；       104—封装层；           200—绑定区域；
201—引线区；           202—弯折区；           210—晶体管；
211—存储电容；         300—边框区域；         301—阳极；
302—像素定义层；       303—有机发光层；       304—阴极；
401—第一封装层；       402—第二封装层；       403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个 端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个 数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和二个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和发光信号线和像素驱动电路，像素驱动电路分别与扫描信号线、数 据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一种示例性实施方式中，四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布。在其它示例性实施方式中，四个子像素可以采用水平并列、竖直并列或钻石形等方式排列，本公开在此不做限定。在其它示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括多个信号线和像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，图3中仅以一个驱动晶体管210和一个存储电容211为例进行示意。每个子像素的发光结构层103可以包括构成发光器件的多个膜层，多个膜层可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接， 有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与8个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用 两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和8个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，以OLED为例，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，第一初始信号线INIT1的第一初始电压提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得第二初始信号线INIT2的第二初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号， 使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，通常包括显示区域和位于显示区域一侧的绑定区域，绑定区域可以至少包括沿着远离显示区域的方向依次设置的第一扇出区、弯折区、驱动芯片区和绑定引脚区。第一扇出区至少包括数据扇出线，多条数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线(Data Line)。弯折区可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。通常，绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过第一扇出区以扇出方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之 间的距离就越大，因而扇形区占用空间较大，导致下边框的窄化设计难度较大，下边框一直维持在2.0mm左右。
图6为本公开示例性实施例一种显示基板的平面结构示意图。如图6所示，显示基板10可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦化区域，包括组成像素阵列的多个子像素Pxij、多条数据信号线和多条数据扇出线，多个子像素Pxij配置为显示动态图片或静止图像，多条数据信号线配置为向多个子像素Pxij提供数据信号，多条数据扇出线与多条数据信号线对应连接，配置为使多条数据信号线通过多条数据扇出线与绑定区域200中的多条引出线对应连接。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，显示区域100可以包括以矩阵方式排布的多个像素单元，至少一个像素单元可以包括出射红色光线的红色子像素R、出射蓝色光线的蓝色子像素B、出射绿色光线的第一绿色子像素G1和出射绿色光线的第二绿色子像素G2。在示例性实施方式中，红色子像素R可以包括出射红色光线的红色发光器件和与红色发光器件连接的红色电路单元，蓝色子像素B可以包括出射蓝色光线的蓝色发光器件和与蓝色发光器件连接的蓝色电路单元，第一绿色子像素G1可以包括出射绿色光线的第一绿色发光器件和与第一绿色发光器件连接的第一绿色电路单元，第二绿色子像素G2可以包括出射绿色光线的第二绿色发光器件和与第二绿色发光器件连接的第二绿色电路单元，红色电路单元、蓝色电路单元、第一绿色电路单元和第二绿色电路单元构成一个电路单元组，至少一个电路单元组中的四个电路单元可以采用正方形方式排列。在示例性实施方式中，多个子像素可以形成多个像素行和多个像素列，多个电路单元可以形成多个电路单元行和多个电路单元列。本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素驱动电路划分的区域。在示例性实施方式中，子像素与电路单元两者的位置可以是对应的，或者，子像素与电路单元两者的位置可以是不对应的。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的引线区201、弯折区202、驱动芯片区和绑定引脚区，引线区201连接到显示区域100，弯折区202连接到引线区201。
在示例性实施方式中，引线区201可以设置相互平行的多条引出线，多条引出线沿着远离显示区域的方向延伸，多条引出线的一端与显示区域100中的多条数据扇出线对应连接，多条引出线的另一端跨过弯折区202连接驱动芯片区的集成电路，使得集成电路通过引出线和数据扇出线将数据信号施加到数据信号线。由于引线区中不需要设置扇形状的斜线，有效减小了引线区竖直方向的长度，大大缩减了下边框宽度，使得显示装置的上边框、下边框、左边框和右边框的宽度相近，均为1.0mm以下，提高了屏占比，有利于实现全面屏显示。
图7为本公开示例性实施例一种数据信号线和数据扇出线的结构示意图。如图7所示，显示区域100可以包括多条数据信号线42和多条数据扇出线50，绑定区域的引线区201可以包括多条引出线60。在示例性实施方式中，多条数据信号线42可以沿着电路单元列的方向延伸，并沿着电路单元行的方向以设定的间隔顺序设置，每条数据信号线42与显示区域100中一个电路单元列中所有电路单元的像素驱动电路连接。多条数据扇出线50的第一端与多条数据信号线42对应连接，多条数据扇出线50的第二端与引线区201的多条引出线60对应连接，使得显示区域100中的多条数据信号线42通过显示区域100中的多条数据扇出线50与绑定区域200中的多条引出线60对应连接。
在示例性实施方式中，显示区域中的数据扇出线的数量与数据信号线的数量可以相同，每条数据信号线通过一条数据扇出线与一条引出线对应连接。或者，显示区域中的数据扇出线的数量可以小于数据信号线的数量，显示区域中的一部分数据信号线通过数据扇出线与引出线对应连接，另一部分数据信号线与引出线直接连接，本公开在此不做限定。
本公开提供了一种显示基板，包括设置在基底上的驱动电路层，所述驱动电路层包括多个电路单元，至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信 号的数据信号线以及与所述数据信号线连接的数据扇出线；至少一个第一电源线、数据信号线和数据扇出线沿第一方向延伸，并沿着第二方向间隔设置，至少一个数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。
在示例性实施方式中，所述数据扇出线通过过孔与所述数据信号线连接。
在示例性实施方式中，所述数据扇出线在显示基板平面内的正投影与所述第一电源线在显示基板平面内的正投影没有重叠区域，所述数据扇出线在显示基板平面内的正投影与所述数据信号线在显示基板平面内的正投影没有重叠区域。
在示例性实施方式中，所述数据扇出线至少包括第一数据扇出线，所述第一数据扇出线设置在所述第一电源线和所述数据信号线之间。
在示例性实施方式中，至少一个电路单元还包括向所述像素驱动电路提供初始信号的初始信号线，所述初始信号线包括主体部分沿所述第一方向延伸的第一初始信号线和主体部分沿所述第二方向延伸的初始信号连接线，所述初始信号连接线通过过孔与所述第一初始信号线连接；所述数据扇出线在显示基板平面内的正投影与所述初始信号连接线在显示基板平面内的正投影至少部分交叠。
在示例性实施方式中，所述初始信号连接线通过过孔与所述第一初始信号线连接。
在示例性实施方式中，所述数据扇出线至少包括第二数据扇出线，所述第二数据扇出线在显示基板平面内的正投影与所述初始信号连接线在显示基板平面内的正投影至少部分交叠。
图8为本公开示例性实施例一种驱动电路层中数据扇出线的示意图。如图8所示并结合图2，在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，沿着第一方向X依次设置的多个电路单元称为电路单元行，沿着第二方向Y依次设置的多个电路单元称为电路单元列，多个电路单元行和多个电路单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。在示例性实施方式中，第一方向X可以是扫描信号线的延伸方向(水平方向)，第二方向Y可以是数据信号线的延伸方向(竖直方向)，第一方向 X和第二方向Y可以相互垂直。
在示例性实施方式中，至少一个电路单元行中设置有第一初始信号线31，第一初始信号线31可以沿着第一方向X延伸。至少一个电路单元列中设置有第一电源线41、数据信号线42和数据扇出线50，第一电源线41、数据信号线42和数据扇出线50可以均沿着第二方向Y延伸，且沿着第一方向X间隔设置。在示例性实施方式中，在第二方向Y，数据扇出线50可以设置在第一电源线41和数据信号线42之间，数据扇出线50在显示基板平面内的正投影与第一电源线41在显示基板平面内的正投影没有重叠区域，数据扇出线50在显示基板平面内的正投影与数据信号线42在显示基板平面内的正投影没有重叠区域。
图9为本公开示例性实施例一种驱动电路层的结构示意图，示意了八个电路单元(2个电路单元行4个电路单元列)的平面结构，为图7中A区域的放大图。如图9所示，在平行于显示基板的平面内，至少一个电路单元可以包括：第一扫描信号线21、第二扫描信号线22、发光信号线23、第一初始信号线31、第二初始信号线32、第一电源线41、数据信号线42、初始信号连接线43、第一数据扇出线52、第二数据扇出线53和像素驱动电路，像素驱动电路可以包括存储电容和7个晶体管，7个晶体管包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7，第三晶体管可以为驱动晶体管。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、发光信号线23、第一初始信号线31和第二初始信号线32的主体部分可以沿着第一方向X延伸，第一电源线41、数据信号线42、初始信号连接线43、第一数据扇出线52和第二数据扇出线53的主体部分可以沿着第二方向Y延伸。
在示例性实施方式中，在垂直于显示基板的平面内，驱动电路层可以至少包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层。在示例性实施方式中，半导体层可以包括多个晶体管的有源层，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、多个晶体管的栅电极和存储电容的第一极板，第二导电层可以包括第一初始信号线31、第二初始信号线32和存储电容的第二极板，第三导电层可以包括第一电 源线41、数据信号线42、初始信号连接线43和多个晶体管的第一极和第二极，第四导电层可以包括第一数据扇出线52和第二数据扇出线53。
在示例性实施方式中，位于第三导电层中的初始信号连接线43可以通过过孔与位于第二导电层中的第一初始信号线31连接，使得主体部分沿着第一方向X延伸第一初始信号线31和主体部分沿着第二方向Y延伸的初始信号连接线43构成网格状，多个电路单元行和多个电路单元列中的第一初始信号线31具有相同的电位。
在示例性实施方式中，驱动电路层可以至少包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
在示例性实施方式中，第一数据扇出线52中的至少部分设置在第一电源线41和数据信号线42之间，第一数据扇出线52在显示基板平面内的正投影与第一电源线41在显示基板平面内的正投影没有重叠区域，第一数据扇出线52在显示基板平面内的正投影与数据信号线42的主体部分在显示基板平面内的正投影没有重叠区域，数据信号线42的主体部分是指数据信号线42中沿着第二方向Y延伸的部分。
在示例性实施方式中，第二数据扇出线53在显示基板平面内的正投影与初始信号连接线43在显示基板平面内的正投影至少部分重叠。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”， 图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以八个电路单元(2个电路单元行4个电路单元列)为例，驱动电路层的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图10所示。
在示例性实施例中，每个电路单元的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构，每个电路单元列中第M行电路单元的第六有源层16与第M+1行电路单元的第七有源层17相互连接，即每个电路单元列中相邻电路单元的半导体层为相互连接的一体结构。
在示例性实施例中，第M行电路单元中的第一有源层11、第二有源层12、第四有源层14和第七有源层17位于本电路单元的第三有源层13远离第M+1行电路单元的一侧，第一有源层11和第七有源层17位于第二有源层12和第四有源层14远离第三有源层13的一侧，第M行电路单元中的第五有源层15和第六有源层16位于第三有源层13靠近第M+1行电路单元的一侧。
在示例性实施例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14和第七有源层17的形状可以呈“1”字形，第五有源层15和第六有源层16的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一区11-1、第四有源层14的第一区14-1、第五有源层15的第一区15-1和第 七有源层17的第一区17-1可以单独设置，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和第一极板24，如图11a和图11b所示，图11b为图11a中第一导电层的平面示意图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
结合图10至图11b所示，第一扫描信号线21、第二扫描信号线22和发光控制线23的主体部分可以沿第一方向X延伸。第M行电路单元中的第一扫描信号线21和第二扫描信号线22可以位于本电路单元的第一极板24远离第M+1行电路单元的一侧，第二扫描信号线22位于本电路单元的第一扫描信号线21远离第一极板24的一侧，发光控制线23可以位于本电路单元的第一极板24靠近第M+1行电路单元的一侧。
在示例性实施例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层13在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施例中，第一扫描信号线21与第二有源层12相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二有源层12在基底上的正投影存在重叠区域，形成双栅结构的第二晶体管T2。第一扫描信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极。第二扫描信号线22与第一有源层11相重叠的区域作为双栅结构的第一晶体管 T1的栅电极，第二扫描信号线22与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，发光控制线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六有源层16相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：第一初始信号线31、第二初始信号线32、第二极板33和屏蔽电极34，如图12a和图12b所示，图12b为图12a中第二导电层的平面示意图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
结合图10至图12b所示，第一初始信号线31和第二初始信号线32的主体部分可以沿第一方向X延伸，第M行电路单元中的第一初始信号线31可以位于本电路单元的第一扫描信号线21和第二扫描信号线22之间，第二初始信号线32可以位于本电路单元的第二扫描信号线22远离第一扫描信号线21的一侧。第二极板33作为存储电容的另一个极板，位于本电路单元的第一扫描信号线21和发光控制线23之间。屏蔽电极34位于本电路单元的第一扫描信号线21(不包含栅极块21-1的主体部分)与第二初始信号线32之间，屏蔽电极34配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，第二极板33的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板33在基底上的正投影与第一极板24在基底上的正投影存在重叠区域，第一极板24和第二极板33构成像素驱动电路的存储电容。第二极板33上设置有开口35，开口35可以位于第二极板33的中部。开口35可以为矩形，使第二极板33形成环形结构。开口35暴露出覆盖第一极板 24的第三绝缘层，且第一极板24在基底上的正投影包含开口35在基底上的正投影。在示例性实施例中，开口35配置为容置后续形成的第一过孔，第一过孔位于开口35内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，第一方向X或第一方向X的反方向上相邻电路单元的第二极板33之间可以通过极板连接线连接，极板连接线的第一端与本电路单元的第二极板33连接，极板连接线的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻电路单元的第二极板33连接，即极板连接线配置为使一电路单元行上相邻电路单元的第二极板33相互连接。在示例性实施例中，通过极板连接线可以使一电路单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号连接线，保证一电路单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第十一过孔V11、第九过孔V9、第十过孔V10和第十一过孔V11，如图13a和图13b所示，图13b为图13a中多个过孔的平面示意图。
结合图10至图13b所示，第一过孔V1在基底上的正投影位于第二极板33的开口35在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在示例性实施例中，第二过孔V2在基底上的正投影位于第二极板33在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板33的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板33连接。在示例性实施例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，以增加第 一电源线与第二极板33的连接可靠性。
在示例性实施例中，第三过孔V3在基底上的正投影位于第五有源层在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在示例性实施例中，第四过孔V4在基底上的正投影位于第六有源层在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在示例性实施例中，第五过孔V5在基底上的正投影位于第四有源层在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在示例性实施例中，第六过孔V6在基底上的正投影位于第二有源层在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在示例性实施例中，第七过孔V7在基底上的正投影位于第七有源层在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接。
在示例性实施例中，第八过孔V8在基底上的正投影位于第一有源层在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面。第八过孔V8配 置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在示例性实施例中，第九过孔V9在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面。第九过孔V9配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一初始信号线31连接。
在示例性实施例中，第十过孔V10在基底上的正投影位于第二初始信号线32在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层被刻蚀掉，暴露出第二初始信号线32的表面。第十过孔V10配置为使后续形成的第七晶体管T7的第一极通过该过孔与第二初始信号线32连接。
在示例性实施例中，第十一过孔V11在基底上的正投影位于屏蔽电极34在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出屏蔽电极34的表面。第十一过孔V11配置为使后续形成的第一电源线通过该过孔与屏蔽电极34连接。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据信号线42、初始信号连接线43、第一连接电极44、第二连接电极45和第三连接电极46，如图14a和图14b所示，图14b为图14a中第三导电层的平面示意图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
结合图10至图14b所示，第一电源线41的主体部分可以沿着第二方向Y延伸，第一电源线41一方面通过第二过孔V2与第二极板33连接，另一方面通过第三过孔V3与第五有源层连接，又一方面通过第十一过孔V11与屏蔽电极34连接，使屏蔽电极34和第二极板33具有与第一电源线41相同的电位。由于屏蔽电极34与第一电源线41连接，且屏蔽电极34的至少部分区域(如屏蔽电极34右侧的竖直部)位于第一连接电极44(作为第一晶体管T1的第二极和第二晶体管T2的第一极，即第二节点N2)与数据信号线42之间，可以有效屏蔽了数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，数据信号线42的主体部分可以沿着第二方向Y延伸，数据信号线42通过第五过孔V5与第四有源层的第一区连接，因而实现了数据信号线42将数据信号写入第四晶体管T4。
在示例性实施例中，初始信号连接线43可以为主体部分沿着第二方向Y延伸的折线形，在每个电路单元中，初始信号连接线43一方面通过第九过孔V9与第一初始信号线31连接，另一方面通过第八过孔V8与第一有源层的第一区连接，初始信号连接线43可以作为第一晶体管T1的第一极，因而实现了第一初始信号线31将第一初始信号写入第一晶体管T1。
在示例性实施例中，初始信号连接线43可以包括相互连接的第一线段43-1和第二线段43-2，第一线段43-1可以为沿着第二方向Y延伸的直线段，第二线段43-2可以为折线段。
在示例性实施例中，第二线段43-2可以包括主体部分沿着第一方向X延伸的第一子线段43-2A和第三子线段43-2C，以及主体部分沿着第二方向Y延伸的第二子线段43-2B。在一个电路单元列中，第M电路单元的第一子线段43-2A的第一端与第M-1电路单元的第一线段43-1连接，第二端沿着第一方向X延伸后与第二子线段43-2B的第一端连接，第二子线段43-2B的第二端沿着第二方向Y延伸后，与第三子线段43-2C的第一端连接，第三子线段43-2C的第二端沿着第一方向X的反方向延伸后与本电路单元的第一线段43-1连接。
在示例性实施例中，每个电路单元列中第M行电路单元的初始信号连接线43与第M+1行电路单元的初始信号连接线43相互连接，即每个电路单元列中相邻电路单元的初始信号连接线43为相互连接的一体结构。由于初始信号连接线43通过第九过孔V9与第一初始信号线31连接，因而一体结构的初始信号连接线43可以复用为竖向的初始信号线，沿着第一方向X延伸的第一初始信号线31和主体部分沿着第二方向Y延伸的初始信号连接线43形成网格状。本公开通过设置初始信号连接线与第一初始信号线连接，使得第一初始信号线形成网状结构，多个电路单元行和多个电路单元列中的多个第一初始信号线31具有相同的电位，不仅有效降低了第一初始信号线的电阻，减小了第一初始电压的压降，而且有效提升了显示基板中第一初始电压的均 一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施例中，初始信号连接线43在基底上的正投影与屏蔽电极34在基底上的正投影存在重叠区域。
在示例性实施例中，第一连接电极44可以为沿着第二方向Y延伸的直线形，其第一端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极44可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施例中，第二连接电极45可以为沿着第二方向Y延伸的直线形，其第一端通过第十过孔V10与第二初始信号线32连接，其第二端通过第七过孔V7与第七有源层的第一区连接，第二连接电极45可以作为第七晶体管T7的第一极，因而实现了第二初始信号线32将第二初始信号写入第七晶体管T7。
在示例性实施例中，第三连接电极46通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极46可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第三连接电极46配置为与后续形成的第一阳极连接电极连接。
在示例性实施例中，每个电路单元的第一电源线41可以为非等宽度设计，采用非等宽度设计的第一电源线41不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施例中，各个电路单元的第一电源线41、数据信号线42、初始信号连接线43、第一连接电极44、第二连接电极45和第三连接电极46的形状可以相同，或者可以不同，本公开在此不做限定。
(6)形成第五绝缘层图案。在示例性实施例中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，沉积第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，第五绝缘层上设置有多个过孔，多个过孔至少包括第十二过孔V12，如图15a和图15b 所示，图15b为图15a中多个过孔的平面示意图。
结合图10至图15b所示，第十二过孔V12在基底上的正投影位于第三连接电极46在基底上的正投影的范围之内，第十二过孔V12内的第五绝缘层被去掉，暴露出第三连接电极46的表面，第十二过孔V12配置为使后续形成的第一阳极连接电极通过该过孔与第三连接电极46连接。
在示例性实施例中，各个电路单元中的第十二过孔V12的位置可以相同，或者可以不同，本公开在此不做限定。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第五绝缘层上的第四导电层，第四导电层至少包括：第一阳极连接电极51、第一数据扇出线52和第二数据扇出线53，如图16a和图16b所示，图16b为图16a中第四导电层的平面示意图。在示例性实施例中，第四导电层可以称为第二源漏金属(SD2)层。
结合图10至图16b所示，在示例性实施例中，第一阳极连接电极51可以设置每个电路单元中。第一阳极连接电极51通过第十二过孔V12与第三连接电极46连接。由于第三连接电极46通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了第一阳极连接电极51通过第三连接电极46与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施例中，第一阳极连接电极51配置为与后续形成的第二阳极连接电极连接。
在示例性实施例中，第N列电路单元中的第一阳极连接电极的形状与第N+2列电路单元中的第一阳极连接电极的形状可以相同，第N+1列电路单元中的第一阳极连接电极的形状与第N+3列电路单元中的第一阳极连接电极的形状可以相同，第一阳极连接电极的形状可以为矩形状。
在示例性实施例中，第一数据扇出线52和第二数据扇出线53可以为主体部分沿着第二方向Y延伸的直线形，在每个电路单元中，第一数据扇出线52设置在第一电源线41与数据信号线42之间，第一数据扇出线52在基底上的正投影与第一电源线41在基底上的正投影没有重叠区域，第一数据扇出线52在基底上的正投影与数据信号线42的主体部分在基底上的正投影没有 重叠区域。
一种显示基板中，将第一数据扇出线设置在第一电源线的上方，即第一数据扇出线在基底上的正投影位于第一电源线在基底上的正投影的范围之内。研究表明，该结构造成第一数据扇出线与第一电源线产生较大的寄生电容，寄生电容值达到9fF以上，导致较大的串扰。本公开示例性实施例通过将第一数据扇出线设置在第一电源线与数据信号线之间，第一数据扇出线与第一电源线和数据信号线没有交叠，使得第一数据扇出线避开了第一电源线，有效降低了第一数据扇出线与第一电源线之间的寄生电容，有效降低了串扰。仿真结构表明，本公开示例性实施例显示基板结构中，第一数据扇出线与第一电源线之间的寄生电容值可降低到6fF以下，串扰程度减小了30％。
在示例性实施例中，第二数据扇出线53设置在第一电源线41远离数据信号线42的一侧，第二数据扇出线53在基底上的正投影与初始信号连接线43中的第一线段在基底上的正投影至少部分重叠。
本公开示例性实施例通过将第二数据扇出线设置在初始信号连接线所在区域，第二数据扇出线在基底上的正投影与初始信号连接线在基底上的正投影至少部分重叠，使得常压信号的初始信号连接线可以屏蔽第二数据扇出线上数据电压跳变对像素驱动电路的影响，有效降低了数据扇出线对像素驱动电路中关键节点电位影响，提高显示效果。
在示例性实施例中，电路单元可以只包括第一数据扇出线52，或者，电路单元可以只包括第二数据扇出线53，或者，电路单元可以同时包括第一数据扇出线52和第二数据扇出线53，本公开在此不做限定。
在示例性实施例中，显示基板中的数据扇出线可以包括沿着第一方向X延伸的第三数据扇出线，第三数据扇出线可以与第一数据扇出线连接，或者，第三数据扇出线可以与第二数据扇出线连接，或者，一个第三数据扇出线与第一数据扇出线连接，另一个第三数据扇出线与第二数据扇出线连接，第一数据扇出线、第二数据扇出线或第三数据扇出线可以通过过孔与数据信号线连接，本公开在此不做限定。
(8)形成第六绝缘层图案。在示例性实施例中，形成第六绝缘层图案可以包括：在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对 第六绝缘薄膜进行图案化，形成覆盖第四导电层的第六绝缘层，第六绝缘层上设置有第十三过孔V13，如图17a和图17b所示，图17b为图17a中多个过孔的平面示意图。
结合图10至图17b所示，第十三过孔V13在基底上的正投影位于第一阳极连接电极51在基底上的正投影的范围之内，第十三过孔V13内的第六绝缘层被去掉，暴露出第一阳极连接电极51的表面，第十三过孔V13配置为使后续形成的第二阳极连接电极通过该过孔与第一阳极连接电极51连接。
在示例性实施例中，各个电路单元中的第十三过孔V13的位置可以相同，或者可以不同，本公开在此不做限定。
(9)形成第五导电层图案。在示例性实施例中，形成第五导电层图案可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第六绝缘层上的第五导电层，第五导电层至少包括：第二阳极连接电极61，如图18a和图18b所示，图18b为图18a中第五导电层的平面示意图。
结合图10至图18b所示，在示例性实施例中，第二阳极连接电极61可以设置每个电路单元中。第二阳极连接电极61通过第十三过孔V13与第一阳极连接电极51连接。由于第一阳极连接电极51通过第十二过孔V12与第三连接电极46连接，第三连接电极46通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了第二阳极连接电极61通过第一阳极连接电极51和第三连接电极46与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施例中，第二阳极连接电极61配置为与后续形成的阳极连接。
在示例性实施例中，第M行第N列电路单元中的阳极连接电极的形状与第M+1行第N+2列电路单元中的第二阳极连接电极的形状可以相同，第M+1行第N列电路单元中的第二阳极连接电极的形状与第M行第N+2列电路单元中的第二阳极连接电极的形状可以相同，第N+1列电路单元中的第二阳极连接电极的形状与第N+3列电路单元中的第二阳极连接电极的形状可以相同，第二阳极连接电极的形状可以为矩形状。
(10)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案 可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第五导电层的第一平坦层，第一平坦层上设置有多个过孔，多个过孔至少包括第十四过孔V14，如图19a和图19b所示，图19b为图19a中多个过孔的平面示意图。
结合图10至图19b所示，第十四过孔V14在基底上的正投影位于第二阳极连接电极61在基底上的正投影的范围之内，第十四过孔V14内的第一平坦层被去掉，暴露出第二阳极连接电极61的表面，第十四过孔V14配置为使后续形成的阳极通过该过孔与第二阳极连接电极61连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。在示例性实施例中，至少一个电路单元可以包括第一数据扇出线和/或第二数据扇出线，第一数据扇出线设置在第一电源线与数据信号线之间，第二数据扇出线在基底上的正投影与初始信号连接线在基底上的正投影至少部分重叠。在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层、第四导电层、第六绝缘层、第五导电层和第一平坦层，第一数据扇出线和/或第二数据扇出线可以设置在第四导电层。
在示例性实施例中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(11)形成阳极图案。在示例性实施例中，形成阳极图案可以包括：在形成前述图案的基底上，沉积第六导电薄膜，采用图案化工艺对第六导电薄膜进行图案化，形成设置在第一平坦层上的阳极图案，阳极采用正方形方式排列，形成GGRB像素排布，如图20a和图20b所示，图20b为图20a中阳极的平面示意图。
结合图10至图20b所示，阳极图案可以包括红色发光器件的红色阳极301R、蓝色发光器件的蓝色阳极301B、第一绿色发光器件的第一绿色阳极301G1和第二绿色发光器件的第二绿色阳极301G2，红色阳极301R所在区 域可以形成出射红色光线的红色子像素R，蓝色阳极301B所在区域可以形成出射蓝色光线的蓝色子像素B，第一绿色阳极301G1所在区域可以形成出射绿色光线的第一绿色子像素G1，第二绿色阳极301G2所在区域可以形成出射绿色光线的第二绿色子像素G2，红色子像素R和蓝色子像素B沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2分别设置在红色子像素R和蓝色子像素B第一方向X的一侧，红色子像素R、蓝色子像素B、第一绿色子像素G1和第二绿色子像素G2组成一个正方形排布的像素单元。
在示例性实施例中，一个像素单元中，红色阳极301R通过第M行第N列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接，蓝色阳极301B通过第M+1行第N列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接，第一绿色阳极301G1通过第M行第N+1列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接，第二绿色阳极301G2通过第M+1行第N+1列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接。另一个像素单元中，红色阳极301R通过第M+1行第N+2列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接，蓝色阳极301B通过第M行第N+2列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接，第一绿色阳极301G1通过第M+1行第N+3列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接，第二绿色阳极301G2通过第M行第N+3列电路单元中的第十四过孔V14与该电路单元中的第二阳极连接电极61连接。
在示例性实施例中，由于每个的阳极通过一个电路单元中的第二阳极连接电极、第一阳极连接电极和第三连接电极46与第六有源层的第二区(也是第七有源层的第二区)连接，因而一个像素单元中的四个阳极分别与一个电路单元组中的四个电路单元的像素驱动电路对应连接，实现了像素驱动电路可以驱动发光器件发光。
在示例性实施例中，分别与第M行第N列电路单元和第M+1行第N+2列电路单元中像素驱动电路连接的两个红色阳极301R的形状和位置相同， 分别与第M+1行第N列电路单元和第M行第N+2列电路单元中像素驱动电路连接的两个蓝色阳极301B的形状和位置相同，分别与第M行第N+1列电路单元和第M+1行第N+3列电路单元中像素驱动电路连接的两个第一绿色阳极301G1的形状和位置相同，分别与第M+1行第N+1列电路单元和第M行第N+3列电路单元中像素驱动电路连接的两个第二绿色阳极301G2的形状和位置相同。在示例性实施例中，一个像素单元中红色阳极301R、蓝色阳极301B、第一绿色阳极301G1和第二绿色阳极301G2的形状和面积均不同。
在示例性实施例中，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同，一个像素单元的四个子像素与一个电路单元组中的四个电路单元的位置关系可以相同，或者可以不同，不同像素单元中的红色阳极301R、蓝色阳极301B、第一绿色阳极301G1和第二绿色阳极301G2的形状和位置可以相同，或者可以不同，本公开在此不做限定。
在示例性实施例中，后续制备流程可以包括：先形成像素定义层图案，像素定义层图案可以包括暴露出红色阳极的红色像素开口、暴露出蓝色阳极的蓝色像素开口、暴露出第一绿色阳极的第一绿色开口和暴露出第二绿色阳极的第二绿色开口。然后，采用蒸镀或喷墨打印工艺形成有机发光层，有机发光层通过相应的像素开口与阳极连接，在有机发光层上形成阴极，阴极与有机发光层连接。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和 第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第六导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层，第五绝缘层和第六绝缘层称为钝化(PVX)层。第一平坦层可以采用有机材料，如树脂等。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
从以上描述的显示基板的结构以及制备过程可以看出，本公开通过在显示区域内设置数据扇出线，使得绑定区域的引出线通过数据扇出线与数据信号线连接，使得引线区中不需要设置扇形状的斜线，有效减小了引线区竖直方向的长度，大大缩减了下边框宽度，使得显示装置的上边框、下边框、左边框和右边框的宽度相近，均为1.0mm以下，提高了屏占比，有利于实现全面屏显示。本公开通过将第一数据扇出线设置在第一电源线与数据信号线之间，使得第一数据扇出线避开了第一电源线，有效降低了第一数据扇出线与第一电源线之间的寄生电容，有效降低了串扰。本公开通过将第二数据扇出线设置在初始信号连接线所在区域，第二数据扇出线在基底上的正投影与初始信号连接线在基底上的正投影至少部分重叠，有效降低了数据扇出线对像素驱动电路中关键节点电位影响，提高显示效果。本公开通过设置主体部分沿第二方向延伸的初始信号连接线，初始信号连接线通过过孔与第一初始 信号线连接，使得初始信号连接线和第一初始信号线形成网状结构，不仅有效降低了第一初始信号线的电阻，减小了第一初始电压的压降，而且有效提升了显示基板中第一初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，第一数据扇出线和第二数据扇出线可以设置在不同的膜层中。又如，第一电源线和数据信号线可以设置在不同的膜层中等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施例中，所述制备方法可以包括：
在基底上形成驱动电路层；所述驱动电路层包括多个电路单元，所述多个电路单元中的至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信号的数据信号线以及与所述数据信号线连接的数据扇出线；所述第一电源线、所述数据信号线和所述数据扇出线中的至少部分沿第二方向延伸，并沿着第一方向间隔设置，至少部分所述数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进 行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种显示基板，包括设置在基底上的驱动电路层，所述驱动电路层包括多个电路单元，所述多个电路单元中的至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信号的数据信号线以及与所述数据信号线连接的数据扇出线；所述第一电源线、所述数据信号线和所述数据扇出线中的至少部分沿第二方向延伸，并沿着第一方向间隔设置，至少部分所述数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。
  2. 根据权利要求1所述的显示基板，其中，所述数据扇出线通过过孔与所述数据信号线连接。
  3. 根据权利要求1所述的显示基板，其中，所述数据扇出线沿所述第二方向延伸的部分在所述显示基板平面内的正投影与所述第一电源线在所述显示基板平面内的正投影没有重叠区域，所述数据扇出线沿所述第二方向延伸的部分在所述显示基板平面内的正投影与所述数据信号线的主体部分在所述显示基板平面内的正投影没有重叠区域。
  4. 根据权利要求1所述的显示基板，其中，所述数据扇出线至少包括第一数据扇出线，所述第一数据扇出线沿所述第二方向延伸，所述第一数据扇出线中的至少部分设置在所述第一电源线和所述数据信号线之间。
  5. 根据权利要求1所述的显示基板，其中，至少一个电路单元还包括向所述像素驱动电路提供初始信号的初始信号线，所述初始信号线包括主体部分沿所述第一方向延伸的第一初始信号线和主体部分沿所述第二方向延伸的初始信号连接线，所述初始信号连接线与所述第一初始信号线连接；至少一条数据扇出线在所述显示基板平面内的正投影与所述初始信号连接线在所述显示基板平面内的正投影至少部分交叠。
  6. 根据权利要求5所述的显示基板，其中，所述初始信号连接线通过过孔与所述第一初始信号线连接。
  7. 根据权利要求5所述的显示基板，其中，所述数据扇出线至少包括第二数据扇出线，所述第二数据扇出线沿所述第二方向延伸，所述第二数据 扇出线在所述显示基板平面内的正投影与所述初始信号连接线在所述显示基板平面内的正投影至少部分交叠。
  8. 根据权利要求7所述的显示基板，其中，所述数据扇出线至少包括第三数据扇出线，所述第三数据扇出线沿所述第一方向延伸，所述第三数据扇出线与所述第一数据扇出线或所述第二数据扇出线连接。
  9. 根据权利要求1至8任一项所述的显示基板，其中，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述第一电源线、所述数据信号线和所述数据扇出线设置在所述显示区域，所述绑定区域包括至少一个引出线；所述数据扇出线的第一端与所述数据信号线连接，所述数据扇出线的第二端与所述引出线连接。
  10. 根据权利要求1至8任一项所述的显示基板，其中，在垂直于所述显示基板的平面内，所述驱动电路层包括在基底上依次设置的第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层之间以及所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据信号线和所述数据扇出线设置在不同的导电层中。
  11. 根据权利要求10所述的显示基板，其中，所述第一电源线和所述数据信号线设置在所述第三导电层中，所述数据扇出线设置在所述第四导电层中。
  12. 根据权利要求10所述的显示基板，其中，所述驱动电路层还包括主体部分沿所述第一方向延伸的第一初始信号线和主体部分沿所述第二方向延伸的初始信号连接线，所述第一初始信号线和所述初始信号连接线设置在不同的导电层中，所述初始信号连接线通过过孔与所述第一初始信号线连接。
  13. 根据权利要求12所述的显示基板，其中，所述第一初始信号线设置在所述第二导电层中，所述初始信号连接线设置在第三导电层中。
  14. 根据权利要求12所述的显示基板，其中，所述初始信号连接线通过过孔与所述像素驱动电路中第一晶体管的有源层第一区连接。
  15. 根据权利要求12所述的显示基板，其中，所述初始信号连接线包 括相互连接的第一线段和第二线段，所述第一线段为沿着所述第二方向延伸的直线段，所述第二线段为折线段，所述第一线段在所述显示基板平面内的正投影与第二数据扇出线在所述显示基板平面内的正投影至少部分交叠。
  16. 一种显示装置，包括如权利要求1至15任一项所述的显示基板。
  17. 一种显示基板的制备方法，包括：
    在基底上形成驱动电路层；所述驱动电路层包括多个电路单元，所述多个电路单元中的至少一个电路单元包括像素驱动电路、向所述像素驱动电路提供电源信号的第一电源线、向所述像素驱动电路提供数据信号的数据信号线以及与所述数据信号线连接的数据扇出线；所述第一电源线、所述数据信号线和所述数据扇出线中的至少部分沿第二方向延伸，并沿着第一方向间隔设置，至少部分所述数据扇出线设置在所述第一电源线和所述数据信号线之间，所述第一方向与所述第二方向交叉。
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