WO2022267016A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2022267016A1
WO2022267016A1 PCT/CN2021/102423 CN2021102423W WO2022267016A1 WO 2022267016 A1 WO2022267016 A1 WO 2022267016A1 CN 2021102423 W CN2021102423 W CN 2021102423W WO 2022267016 A1 WO2022267016 A1 WO 2022267016A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
anode
initial signal
layer
pixel
Prior art date
Application number
PCT/CN2021/102423
Other languages
English (en)
French (fr)
Inventor
尚庭华
张毅
刘庭良
周洋
杨慧娟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21946510.1A priority Critical patent/EP4216200A4/en
Priority to CN202180001632.8A priority patent/CN115868261A/zh
Priority to PCT/CN2021/102423 priority patent/WO2022267016A1/zh
Priority to US17/780,533 priority patent/US20240169908A1/en
Publication of WO2022267016A1 publication Critical patent/WO2022267016A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but not limited to the field of display technology, and specifically relates to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • LCD Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • the present disclosure provides a display substrate, comprising a driving circuit layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer comprising a plurality of circuit units , the light emitting structure layer includes a plurality of light emitting devices; at least one circuit unit includes a first power supply line, an initial signal line and a pixel driving circuit, and the initial signal line includes a first initial signal line extending along a first direction and a first initial signal line extending along a second direction. A second initial signal line extending in two directions, the first direction intersects the second direction; the orthographic projection of the second initial signal line on the substrate at least partially overlaps the orthographic projection of the first power supply line on the substrate .
  • the second initial signal line in at least one circuit unit includes an extension portion and a connection portion connected to each other, the extension portion extends along the second direction, and the connection portion extends along the second direction. Extending in one direction, the connection part is connected to the first initial signal line through a via hole.
  • the orthographic projection of the extending portion on the base at least partially overlaps the orthographic projection of the first power line on the base, and the orthographic projection of the connecting portion on the base overlaps with the first initial The orthographic projections of the signal lines on the substrate at least partially overlap.
  • At least one circuit unit includes a second connection electrode, the connection part is connected to the second connection electrode through a via hole, and the second connection electrode is connected to the first initial signal line through a via hole connect.
  • the second connection electrode is connected to the first region of the active layer of the first transistor and the first region of the active layer of the seventh transistor in the pixel driving circuit through via holes.
  • the driving circuit layer includes a plurality of unit rows and a plurality of unit columns, the unit rows include a plurality of circuit units arranged along the first direction, and the unit columns include a plurality of circuit units arranged along the first direction.
  • the plurality of circuit units include a first circuit unit connected to a red light emitting device emitting red light, a second circuit unit connected to a blue light emitting device emitting blue light, and a second circuit unit connected to a blue light emitting device emitting green light.
  • the third circuit unit connected to the first green light-emitting device and the fourth circuit unit connected to the second green light-emitting device emitting green light;
  • the plurality of unit columns include a first unit column and a second unit column, and the first The first circuit unit and the second circuit unit in a unit column are arranged alternately along the second direction, and the third circuit unit and the fourth circuit unit in the second unit column are arranged alternately along the second direction ; At least part of the second initial signal lines are arranged in the first cell column.
  • the light emitting device includes an anode and a pixel definition layer;
  • the anode includes a first anode of the red light emitting device, a second anode of the blue light emitting device, the first green light emitting device The third anode of the second green light-emitting device and the fourth anode of the second green light-emitting device;
  • the pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode , the third pixel opening exposing the third anode and the fourth pixel opening exposing the fourth anode;
  • the second centerlines of the line's orthographic projections on the substrate at least partially overlap.
  • the driving circuit layer further includes a data signal line, a third central line of the second pixel opening on the substrate orthographic projection and a fourth central line of the data signal line on the substrate orthographic projection overlap at least partially.
  • the light emitting device includes an anode and a pixel definition layer;
  • the anode includes a first anode of the red light emitting device, a second anode of the blue light emitting device, the first green light emitting device The third anode of the second green light-emitting device and the fourth anode of the second green light-emitting device;
  • the pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode , the third pixel opening exposing the third anode and the fourth pixel opening exposing the fourth anode;
  • the driving circuit layer also includes a data signal line;
  • the extension of the second initial signal line is on the substrate
  • the second centerline of the upper orthographic projection and the fourth centerline of the data signal line on the base are located on both sides of the first centerline of the first pixel opening's orthographic projection on the substrate.
  • the second centerline of the extension portion of the second initial signal line on the substrate orthographically projects and the fourth centerline of the data signal line on the substrate orthographically projects relative to the first pixel
  • the openings are arranged symmetrically on the first central line of the orthographic projection on the base.
  • the second centerline of the extension of the second initial signal line on the base orthographically projects and the fourth centerline of the data signal line on the base orthographic projection is located at the second pixel opening. On either side of the third centerline orthographically projected onto the base.
  • the second centerline of the extension part of the second initial signal line on the substrate orthographically projects and the fourth centerline of the data signal line on the substrate orthographically projects relative to the second pixel
  • the openings are arranged symmetrically on the third central line of the orthographic projection on the base.
  • the plurality of circuit units include a first circuit unit connected to a red light emitting device emitting red light, a second circuit unit connected to a blue light emitting device emitting blue light, and a second circuit unit connected to a blue light emitting device emitting green light.
  • the plurality of unit columns include a first unit column and a second unit column, and the first The first circuit unit and the second circuit unit in a unit column are arranged alternately along the second direction, and the third circuit unit and the fourth circuit unit in the second unit column are arranged alternately along the second direction ; At least part of the second initial signal lines are arranged in the second cell column. .
  • the light emitting device includes an anode and a pixel definition layer;
  • the anode includes a first anode of the red light emitting device, a second anode of the blue light emitting device, the first green light emitting device The third anode of the second green light-emitting device and the fourth anode of the second green light-emitting device;
  • the pixel definition layer is provided with a first pixel opening exposing the first anode, a second pixel opening exposing the second anode , the third pixel opening that exposes the third anode and the fourth pixel opening that exposes the fourth anode;
  • the connection of the lines at least partially overlaps the seventh centerline of the orthographic projection on the base.
  • a sixth centerline of the fourth pixel opening on the base orthographically projects at least partially overlaps with a seventh centerline of the connecting portion of the second initial signal line on the base orthographic projection.
  • the plurality of circuit units include a first circuit unit connected to a red light emitting device emitting red light, a second circuit unit connected to a blue light emitting device emitting blue light, and a second circuit unit connected to a blue light emitting device emitting green light.
  • the plurality of unit columns include a first unit column and a second unit column, and the first The first circuit unit and the second circuit unit in a unit column are arranged alternately along the second direction, and the third circuit unit and the fourth circuit unit in the second unit column are arranged alternately along the second direction ;
  • the second initial signal line is arranged in the first cell column and the second cell column.
  • the driving circuit layer in a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate.
  • the semiconductor layer includes active layers of multiple transistors in the pixel drive circuit, the first conductive layer includes scan signal lines and gate electrodes of multiple transistors, and the second conductive layer includes the first initial Signal lines, the third conductive layer includes first power lines, and the fourth conductive layer includes data signal lines and the second initial signal lines.
  • the third conductive layer further includes a second connection electrode, the second connection electrode is connected to the first initial signal line through a via hole, and the second initial signal line is connected to the first initial signal line through a via hole.
  • the second connection electrode is connected.
  • the second conductive layer further includes a shielding electrode, and the first power line is connected to the shielding electrode through a via hole.
  • the orthographic projection of at least a partial area of the shielding electrode on the substrate is located between the orthographic projection of the data signal line on the substrate and the second of the first transistor in the pixel driving circuit. Pole between orthographic projections on the substrate.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a driving circuit layer arranged on a base and a light emitting structure layer arranged on a side of the driving circuit layer away from the base, the driving circuit layer includes a plurality of circuit units, and the light emitting structure layer includes a plurality of a light emitting device; at least one circuit unit includes a first power supply line, an initial signal line and a pixel driving circuit, and the initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction line, the first direction crosses the second direction; the preparation method includes:
  • a second initial signal line extending along the second direction is formed, and the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the first power supply line on the substrate.
  • 1 is a schematic structural view of a display device
  • Figure 2a and Figure 2b are a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 5 is a working timing diagram of a pixel driving circuit
  • Fig. 6a is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • Fig. 6b is a schematic diagram showing an initial signal line in a substrate according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of the present disclosure showing a semiconductor layer pattern formed on a substrate
  • FIG. 8a is a schematic diagram of the present disclosure showing that a first conductive layer pattern is formed on a substrate
  • Figure 8b is a schematic plan view of the first conductive layer in Figure 8a;
  • FIG. 9a is a schematic diagram of the present disclosure showing that a second conductive layer pattern is formed on a substrate
  • Figure 9b is a schematic plan view of the second conductive layer in Figure 9a;
  • FIG. 10a is a schematic diagram of the present disclosure showing a fourth insulating layer pattern formed on a substrate
  • Fig. 10b is a schematic plan view of a plurality of via holes in Fig. 10a;
  • FIG. 11a is a schematic diagram of the present disclosure showing that a third conductive layer pattern is formed on a substrate
  • Figure 11b is a schematic plan view of the third conductive layer in Figure 11a;
  • FIG. 12a is a schematic diagram of the present disclosure showing that the substrate is patterned with a first flat layer
  • Figure 12b is a schematic plan view of a plurality of vias in Figure 12a;
  • Fig. 13a is a schematic diagram of the present disclosure showing that a fourth conductive layer pattern is formed on a substrate;
  • Fig. 13b is a schematic plan view of the fourth conductive layer in Fig. 13a;
  • FIG. 14a is a schematic diagram of the present disclosure showing that the second planar layer pattern is formed on the substrate
  • Fig. 14b is a schematic plan view of a plurality of via holes in Fig. 14a;
  • Fig. 15a is a schematic diagram of the present disclosure showing that the substrate is formed with an anode pattern
  • Figure 15b is a schematic plan view of the anode in Figure 15a;
  • FIG. 16a is a schematic diagram of the present disclosure showing that a pixel definition layer pattern is formed on a substrate
  • Figure 16b is a schematic plan view of the pixel definition layer in Figure 16a;
  • Fig. 17a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure.
  • Figure 17b is a schematic plan view of the fourth conductive layer in Figure 17a;
  • Fig. 18a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure.
  • Figure 18b is a schematic plan view of the fourth conductive layer in Figure 18a;
  • Fig. 19a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure.
  • Figure 19b is a schematic plan view of the fourth conductive layer in Figure 19a;
  • Fig. 20a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure.
  • Figure 20b is a schematic plan view of the fourth conductive layer in Figure 20a;
  • Fig. 21a is another schematic diagram after forming an anode pattern according to an exemplary embodiment of the present disclosure.
  • Figure 21b is a schematic plan view of the anode in Figure 21a;
  • Fig. 22a is another schematic diagram after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure
  • Fig. 22b is a schematic plan view of the pixel definition layer in Fig. 22a.
  • 51 data signal line
  • 52 second initial signal line
  • 53 anode connection electrode
  • 71 anode
  • 72 pixel definition layer
  • 73 pixel opening
  • 101 substrate
  • 102 drive circuit layer
  • 103 light emitting structure layer
  • 104 encapsulation layer
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged, and “source terminal” and “drain terminal” can be interchanged.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array, the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively, and the data driver is connected to a plurality of data signal lines respectively.
  • the scanning drivers are respectively connected to a plurality of scanning signal lines (S1 to Sm)
  • the light emitting drivers are respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data signal line, At least one light emitting signal line and a pixel driving circuit.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver.
  • the driver can supply a clock signal, an emission stop signal, etc.
  • the data driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light emitting driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting driver can be configured in the form of a shift register, and can generate emission signals in a manner of sequentially transmitting emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2a and FIG. 2b are schematic diagrams of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 that emits light of the first color, and a first sub-pixel P1 that emits light of the second color.
  • each of the four sub-pixels may include circuit units and light emitting devices, and the circuit units may include scanning signal lines, data signal lines and The light emitting signal line and the pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line and the light emitting signal line, and the pixel driving circuit is configured to receive the signal transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line The data voltage is used to output a corresponding current to the light emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel to emit light with a corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • four sub-pixels may be arranged in a square (Square) manner to form a GGRB pixel arrangement, as shown in FIG. 2a.
  • four sub-pixels may be arranged in a diamond shape (Diamond) to form an RGBG pixel arrangement, as shown in FIG. 2b.
  • the four sub-pixels may be arranged horizontally or vertically.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in the present disclosure.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction is called a pixel row
  • a plurality of sub-pixels arranged in sequence in the vertical direction are called a pixel column
  • a plurality of pixel rows and a plurality of pixel columns constitute a pixel array arranged in an array .
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the base, and a light-emitting structure layer 103 disposed on the base 102.
  • Layer 103 is away from the encapsulation layer 104 on the side of the substrate.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and storage capacitors. In FIG. 3 , only one driving transistor 210 and one storage capacitor 211 are taken as examples for illustration.
  • the light-emitting structure layer 103 of each sub-pixel may include multiple film layers that constitute a light-emitting device, and the multiple film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 communicates with the drive transistor 210 through a via hole.
  • the drain electrode is connected, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. material, the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 , which can ensure that external water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL for short), Emitting Layer (EML for short), Hole Block Layer (HBL for short), Electron Transport Layer (ETL for short), and Electron Injection Layer (EIL for short) .
  • HIL Hole Injection Layer
  • HTL hole transport layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all sub-pixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all sub-pixels may be a common layer connected together
  • all The hole blocking layer of the sub-pixels can be a common layer connected together, and the light-emitting layer and the electron blocking layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected with 7 signal lines (data signal line D, first scan The signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line INIT, the first power line VDD and the second power line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor
  • the first pole of the second transistor T2, the control pole of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3 and the second terminal of the storage capacitor C.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the initial voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or released to emit light The amount of charge accumulated in the first pole of a device.
  • the light emitting device may be an OLED comprising a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode), or may be a QLED comprising a stacked first pole (anode) , a quantum dot light-emitting layer and a second pole (cathode).
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first transistor T1 to the seventh transistor T7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to realize low-frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 5 is a working timing diagram of a pixel driving circuit.
  • the following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 4.
  • the pixel driving circuit in FIG. signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS), 7 transistors are is a P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals.
  • the signal line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is supplied to the second node N2, and charge the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power line VDD.
  • Fig. 6a is a schematic structural diagram of a driving circuit layer according to an exemplary embodiment of the present disclosure, illustrating a planar structure of eight circuit units (two unit rows and four unit columns).
  • the driving circuit layer may include a plurality of circuit units, and the plurality of circuit units arranged in sequence along the first direction X are called unit rows, and along the second direction Y
  • a plurality of circuit units arranged in sequence is called a unit column, and a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X crosses the second direction Y.
  • At least one circuit unit may include a first power line, an initial signal line, and a pixel driving circuit connected to the first power line and the initial signal line, and the pixel driving circuit may include a plurality of transistors and a storage capacitor.
  • the first power line may be configured as a signal line receiving a power signal
  • the initial signal line may be configured to initialize (reset) the storage capacitor.
  • the initial signal line of at least one circuit unit may include a first initial signal line 31 whose main body portion extends along the first direction X and a second initial signal line 52 whose main body portion extends along the second direction Y, and The first initial signal line 31 and the second initial signal line 52 are connected through via holes.
  • a extending along the B direction means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a bar-shaped body, the main part extends along the B direction, and the main part extends along the B The length extending in one direction is greater than the length extending in the other direction of the minor portion.
  • the second initial signal line 52 may include an extension part 521 and a connection part 522 connected to each other, the main part of the extension part 521 extends along the second direction Y, and the connection part 522 The main body portion extends along the first direction X.
  • the end of the connection portion 522 on a side away from the extension portion 521 may be connected to the first initial signal line 31 through a via hole.
  • the orthographic projection of at least part of the connecting portion 522 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate.
  • the orthographic projection of at least part of the extension portion 521 on the base is within the range of the orthographic projection of the first power line 41 on the base.
  • Fig. 6b is a schematic diagram of an initial signal line in a driving circuit layer according to an exemplary embodiment of the present disclosure.
  • the driving circuit layer may include a plurality of unit rows and a plurality of unit columns, the first initial signal line 31 may be arranged in each unit row, and the second initial signal line 52 may be arranged in alternate unit columns , that is, there is at least one cell column between two adjacent second initial signal lines 52 in the first direction X.
  • the direction of the cell row may be a first direction X
  • the direction of the cell column may be a second direction Y.
  • the plurality of sub-pixels in the display substrate may include a red sub-pixel R emitting red light, a blue sub-pixel B emitting blue light, a first green sub-pixel G1 emitting green light, and a first green sub-pixel G1 emitting green light.
  • the red sub-pixel R may include a red light-emitting device emitting red light and a first circuit unit Q1 connected to the red light-emitting device
  • the blue sub-pixel B may include a blue light-emitting device emitting blue light and a first circuit unit Q1 connected to the blue light-emitting device.
  • the second circuit unit Q2, the first green sub-pixel G1 may include a first green light-emitting device emitting green light and a third circuit unit Q3 connected to the first green light-emitting device, the second green sub-pixel G2 may include a green light-emitting device
  • the second green light emitting device and the fourth circuit unit Q4 connected to the second green light emitting device, the first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3 and the fourth circuit unit Q4 form a circuit unit group, at least
  • the four circuit units in one circuit unit group can be arranged in a square manner, that is, the four circuit units are arranged in two unit rows and two unit columns.
  • the sub-pixels mentioned in the present disclosure refer to the regions divided according to the light emitting devices, and the circuit units mentioned in the present disclosure refer to the regions divided according to the pixel driving circuits.
  • the positions of both the sub-pixel and the circuit unit may correspond, or the positions of the sub-pixel and the circuit unit may not correspond.
  • the plurality of unit columns may include a first unit column and a second unit column, the first unit column refers to a column formed by a plurality of first circuit units Q1 and second circuit units Q2, and the second unit column refers to a column formed by a plurality of third circuit units Q3 and fourth circuit units Q4.
  • the first circuit unit Q1 and the second circuit unit Q2 in the first unit column are arranged alternately along the second direction Y, and the third circuit unit Q3 and the fourth circuit unit Q4 in the second unit column are alternately arranged along the second direction Y set up.
  • the second initial signal line 52 may be disposed in the first cell column.
  • the Nth unit column and the N+2th unit column are the first unit column
  • the N+1th unit column and the N+3th unit column can be the second unit column
  • the second initial signal line 52 can be set at the In the N unit column, the N+2th unit column, the N+4th unit column, . . .
  • the second initial signal line 52 repeats every other second unit column.
  • the second initial signal line 52 may be disposed in the second cell column.
  • the Nth unit column and the N+2th unit column are the first unit column
  • the N+1th unit column and the N+3th unit column can be the second unit column
  • the second initial signal line 52 can be set at the In the N+1 unit row, the N+3th unit row, the N+5th unit row, . . .
  • the second initial signal line 52 repeats every other first unit row.
  • the second initial signal line 52 may be disposed in the first cell column and the second cell column.
  • the N-th cell column and the N+2-th cell column may be the first cell column
  • the N+1-th cell column and the N+3-th cell column may be the second cell column.
  • the circuit unit in the Mth row is the first circuit unit
  • the circuit unit in the M+1th row is the second circuit unit, so the first circuit unit and the second circuit unit in the Nth unit column are along the The second direction Y is arranged alternately.
  • the circuit unit in the Mth row is the second circuit unit
  • the circuit unit in the M+1th row is the first circuit unit, so the second circuit unit in the N+2th unit column and the first circuit unit
  • the circuit units are arranged alternately along the second direction Y.
  • the second initial circuit unit in the Mth row, Nth column circuit unit since the circuit unit in the Mth row, Nth column and the M+1th row, N+2th column circuit unit are both first circuit units, the second initial circuit unit in the Mth row, Nth column circuit unit
  • the shape of the signal line may be the same as that of the second initial signal line in the circuit unit in the M+1th row and the N+2th column. Since the circuit unit in the Nth column of the M+1th row and the N+2th column of the Mth row are both second circuit units, the shape of the second initial signal line in the M+1th row of the Nth column circuit unit is the same as The shapes of the second initial signal lines in the circuit units in the Mth row and the N+2th column may be the same.
  • the extension part 521 may include a first initial part, a second initial part, and a third initial part connected in sequence.
  • the initial portion, the first initial portion and the third initial portion may be parallel to the second direction Y, and the second initial portion may have a first angle with the second direction Y, and the first angle may be greater than 0° and less than 90°.
  • an end portion of the first initial portion and/or the third initial portion may be connected to the connection portion 522 .
  • the extension part 521 may include a fourth initial part, a fifth initial part, a sixth initial part, and a sixth initial part connected in sequence.
  • the initial part, the seventh initial part and the eighth initial part, the fourth initial part, the sixth initial part and the eighth initial part may be parallel to the second direction Y, and the fifth initial part may have a first angle with the second direction Y , the seventh initial portion may have a second angle with the second direction Y, the first angle may be greater than 0° and less than 90°, and the second angle may be greater than 0° and less than 90°.
  • the extending direction of the fifth initial portion and the extending direction of the seventh initial portion may be mirror-symmetrical with respect to the first direction X.
  • the second initial signal line 52 may be arranged in an alternate first unit column or second unit column, that is, between two second initial signal lines 52 adjacent in the first direction X interval with three cell columns.
  • the second initial signal line 52 can be arranged in the Nth unit column, the N+4th unit column, the N+8th unit column, ..., the second initial signal line 52 every other first unit column and the second unit column Two-unit row one repeat.
  • the second initial signal line 52 may be arranged in the N+1th unit column, the N+5th unit column, the N+9th unit column, ..., the second initial signal line 52 every second first unit column and A second cell column repeats.
  • there is no special requirement on the number of unit columns between adjacent second initial signal lines 52 which can be set according to needs, which is not limited in the present disclosure.
  • the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate;
  • the semiconductor layer may include active layers of a plurality of transistors, the first conductive layer may include scanning signal lines and gate electrodes of a plurality of transistors, the second conductive layer may include the first initial signal line 31, and the third conductive layer may include The first power line and the first pole and the second pole of the plurality of transistors, the fourth conductive layer may include a data signal line and a second initial signal line 52 .
  • the third conductive layer may further include a second connection electrode 44 .
  • the second connection electrode 44 on the third conductive layer can be connected to the first initial signal line 31 on the second conductive layer through a via hole, and the second initial signal line 52 on the fourth conductive layer can be connected to the first initial signal line 52 on the third conductive layer through a via hole.
  • the second connection electrode 44 of the conductive layer is connected.
  • the second connection electrode may be referred to as an initial connection electrode.
  • the second connection electrode 44 may be connected to the first region of the active layer of the first transistor and the first region of the active layer of the seventh transistor in the pixel driving circuit through via holes.
  • the second conductive layer may further include a shielding electrode, and the first power line is connected to the shielding electrode through a via hole.
  • the orthographic projection of at least a partial area of the shielding electrode on the substrate is located between the orthographic projection of the data signal line on the substrate and the orthographic projection of the second electrode of the first transistor in the pixel driving circuit on the substrate.
  • the driving circuit layer may further include a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, and a storage capacitor, and the storage capacitor may include a first plate and a second plate, and more
  • the transistors may include first to seventh transistors, and the third transistor is a driving transistor.
  • the first conductive layer may include a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, a first plate of a storage capacitor, and gate electrodes of a plurality of transistors
  • the second conductive layer can include the first initial signal line 31, the second plate of the storage capacitor, the shielding electrode and the plate connection line
  • the third conductive layer can include the first power line 41, the data connection electrode, the first connection electrode, the second connection
  • the electrode 44 , the third connection electrode and the fourth connection electrode, the fourth conductive layer may include a data signal line 51 , a second initial signal line 52 and an anode connection electrode.
  • the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer
  • the first insulating layer is disposed between the substrate and the semiconductor layer
  • the second insulating layer is arranged between the semiconductor layer and the first conductive layer
  • the third insulating layer is arranged between the first conductive layer and the second conductive layer
  • the fourth insulating layer is arranged between the second conductive layer and the third conductive layer
  • the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.
  • the following is an exemplary description by showing the preparation process of the substrate.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the orthographic projection of A , or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the preparation process of the driving circuit layer may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate.
  • the semiconductor layer on the first insulating layer is shown in FIG. 7 .
  • the semiconductor layer of each circuit unit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17
  • the active layer 17 is an integral structure connected to each other, and the sixth active layer 16 of the M row of circuit units in each cell column is connected to the seventh active layer 17 of the M+1th row of circuit cells, that is, each unit
  • the semiconductor layers of adjacent circuit units in a column are connected to each other as a unitary structure.
  • the first active layer 11, the second active layer 12, the fourth active layer 14, and the seventh active layer 17 in the Mth row of circuit units are located in the third active layer of the current circuit unit.
  • Layer 13 is away from the side of the circuit unit in the M+1th row, and the first active layer 11 and the seventh active layer 17 are located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13
  • the fifth active layer 15 and the sixth active layer 16 in the Mth row of circuit units are located on the side of the third active layer 13 close to the M+1th row of circuit units.
  • the shape of the first active layer 11 may be "n"
  • the shape of the second active layer 12 may be "7”
  • the shape of the third active layer 13 may be "several”.
  • the shape of the fourth active layer 14 may be "1”
  • the shape of the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 11-1 of the first active layer 11 simultaneously functions as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 simultaneously
  • the first region 12-1 of the second active layer 12 the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the fifth active layer 15
  • the second region 15-2 of the third active layer 13, the second region 13-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16
  • the second region 16 - 2 of the sixth active layer 16 serves as the second region 17 - 2 of the seventh active layer 17 at the same time.
  • the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are separately disposed.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, and patterning the first conductive film through a patterning process to form The second insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scanning signal line 21, a second scanning signal line 22, and a light emission control line 23 and the first pole plate 24, as shown in Figure 8a and Figure 8b, Figure 8b is a schematic plan view of the first conductive layer in Figure 8a.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first scanning signal line 21 , the second scanning signal line 22 and the light emission control line 23 can extend along the first direction X along the main part.
  • the first scanning signal line 21 and the second scanning signal line 22 in the circuit unit of the M row are located on the side of the first plate 24 of the circuit unit away from the circuit unit in the M+1 row, and the second scanning signal line 22 is located in this circuit unit.
  • the first scanning signal line 21 of the circuit unit is away from the side of the first pole plate 24, and the light emission control line 23 may be located on the side of the first pole plate 24 of the circuit unit close to the circuit unit in the M+1th row.
  • the first plate 24 may be rectangular, and the corners of the rectangle may be chamfered. Orthographic projections on the base have overlapping regions. In an exemplary embodiment, the first plate 24 may serve as a plate of the storage capacitor and a gate electrode of the third transistor T3 at the same time.
  • the overlapping area of the first scanning signal line 21 and the second active layer 12 serves as the gate electrode of the second transistor T2, and the first scanning signal line 21 is provided with The raised gate block 21 - 1 , the orthographic projection of the gate block 21 - 1 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate, forming a second transistor T2 with a double gate structure.
  • the overlapping area of the first scanning signal line 21 and the fourth active layer 14 serves as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps with the first active layer 11 is used as the gate electrode of the first transistor T1 of the double gate structure, and the area where the second scanning signal line 22 overlaps with the seventh active layer 17 is used as the seventh
  • the semiconductor layer may be subjected to conductorization treatment by using the first conductive layer as a shield, and the semiconductor layer in the area blocked by the first conductive layer forms the first transistors T1 to the seventh In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are all conductorized.
  • forming the pattern of the second conductive layer may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, and forming A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least includes: a first initial signal line 31, a second pole plate 32, and a shielding electrode 33 9a and 9b, and FIG. 9b is a schematic plan view of the second conductive layer in FIG. 9a.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the first initial signal line 31 can extend along the first direction X along the main body part, and the first initial signal line 31 in the Mth row of circuit units is located far away from the second scanning signal line 22 of this circuit unit.
  • the second plate 32 is used as the other plate of the storage capacitor, and is located between the first scanning signal line 21 and the light-emitting control line 23 of this circuit unit, and the shielding electrode 33 is located in this circuit.
  • the shielding electrode 33 is configured to shield the influence of the data voltage jump on key nodes and avoid the data voltage The jump affects the potential of key nodes of the pixel driving circuit, improving the display effect.
  • the outline of the second pole plate 32 can be rectangular, the corners of the rectangle can be chamfered, and the orthographic projection of the second pole plate 32 on the base is the same as that of the first pole plate 24 on the base There is an overlapping area in the orthographic projection, and the first pole plate 24 and the second pole plate 32 form a storage capacitor of the pixel driving circuit.
  • An opening 34 is disposed on the second pole plate 32 , and the opening 34 may be located in the middle of the second pole plate 32 .
  • the opening 34 may be rectangular, so that the second pole plate 32 forms a ring structure.
  • the opening 34 exposes the third insulating layer covering the first pole plate 24, and the orthographic projection of the first pole plate 24 on the base includes the orthographic projection of the opening 34 on the base.
  • the opening 34 is configured to accommodate the subsequently formed first via hole, the first via hole is located in the opening 34 and exposes the first electrode plate 24, so that the second electrode of the subsequently formed first transistor T1 Connect with the first pole plate 24.
  • the plate connection line 35 is arranged between the second plate 32 of the adjacent circuit unit in the first direction X or in the opposite direction of the first direction X, and the first end of the plate connection line 35 is connected to The second pole plate 32 of this circuit unit is connected, and the second end of the pole plate connection line 35 extends along the first direction X or the opposite direction of the first direction X, and is connected with the second pole plate 32 of the adjacent circuit unit, That is, the plate connecting wires 35 are configured to connect the second plates of adjacent circuit units in a unit row to each other.
  • the second pole plates of a plurality of circuit units in a unit row can form an interconnected integrated structure through the plate connection line 35, and the second plate of the integrated structure can be multiplexed as a power signal line, Ensuring that multiple second pole plates in a unit row have the same potential is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • each circuit unit is provided with a plurality of via holes, and the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole Vias V5, sixth vias V6, seventh vias V7, eighth vias V8, and ninth vias V9, as shown in Figure 10a and Figure 10b, Figure 10b is a schematic plan view of multiple vias in Figure 10a .
  • the first via hole V1 is located in the opening 34 of the second plate 32, and the orthographic projection of the first via hole V1 on the substrate is within the range of the orthographic projection of the opening 34 on the substrate.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via hole.
  • the second via hole V2 is located within the range of the orthographic projection of the second polar plate 32 on the substrate, and the orthographic projection of the second via hole V2 on the substrate is located at the range of the second polar plate 32 on the substrate.
  • the fourth insulating layer in the second via hole V2 is etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured to connect the subsequently formed first power line to the second pole plate 32 through the via hole.
  • the second via hole V2 serving as a power supply via hole may include a plurality of second via holes V2 arranged in sequence along the second direction Y, so as to increase the number of connections between the first power line and the second plate. 32 connection reliability.
  • the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer in the third via hole V3 layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer.
  • the third via hole V3 is configured to connect the subsequently formed first power line to the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is within the range of the orthographic projection of the sixth active layer on the substrate, and the fourth insulating layer and the third insulating layer in the fourth via hole V4 layer and the second insulating layer are etched away, exposing the surface of the second region of the sixth active layer (also the second region of the seventh active layer).
  • the fourth via hole V4 is configured such that the second pole of the subsequently formed sixth transistor T6 is connected to the sixth active layer through the via hole, and the second pole of the subsequently formed seventh transistor T7 is connected to the sixth active layer through the via hole. Seven active layer connections.
  • the orthographic projection of the fifth via hole V5 on the substrate is within the range of the orthographic projection of the fourth active layer on the substrate, and the fourth insulating layer and the third insulating layer in the fifth via hole V5 layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer.
  • the fifth via hole V5 is configured to connect the subsequently formed data signal line to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the second active layer on the substrate, and the fourth insulating layer and the third insulating layer in the sixth via hole V6 layer and the second insulating layer are etched away, exposing the surface of the first region of the second active layer (which is also the second region of the first active layer).
  • the sixth via hole V6 is configured to connect the second pole of the subsequently formed first transistor T1 to the first active layer through the via hole, and connect the first pole of the subsequently formed second transistor T2 to the first active layer through the via hole. Two active layer connections.
  • the orthographic projection of the seventh via hole V7 on the substrate is within the range of the orthographic projection of the seventh active layer on the substrate, and the fourth insulating layer and the third insulating layer in the seventh via hole V7 layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer (which is also the first region of the first active layer).
  • the seventh via hole V7 is configured such that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • An active layer connection is configured such that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the shielding electrode 33 on the substrate, and the fourth insulating layer in the eighth via hole V8 is etched away, exposing out of the surface of the shielding electrode 33.
  • the eighth via hole V8 is configured to connect the subsequently formed first power line to the shielding electrode 33 through the via hole.
  • the orthographic projection of the ninth via hole V9 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer in the ninth via hole V9 is etched. drop, exposing the surface of the first initial signal line 31.
  • the ninth via hole V9 is configured such that the first pole of the subsequently formed seventh transistor T7 (also the first pole of the first transistor T1 ) is connected to the first initial signal line 31 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film by a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer, the third conductive layer at least includes: a first power line 41, a data connection electrode 42, a first connection electrode 43, a second connection electrode 44 and a third connection electrode 45, as shown in Figure 11a and Figure 11b , FIG. 11b is a schematic plan view of the third conductive layer in FIG. 11a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the main part of the first power line 41 extends along the second direction Y.
  • the third via V3 is connected to the fifth active layer, and on the other hand is connected to the shielding electrode 33 through the eighth via V8, so that the shielding electrode 33 and the second plate 32 have the same potential as the first power line 41 .
  • the shielding electrode 33 is connected to the first power line 41, and the orthographic projection of at least a part of the shielding electrode 33 (such as the protrusion on the right side of the shielding electrode 33) on the substrate is located at the first connection electrode 43 (as the first transistor T1 Between the orthographic projection of the second pole and the first pole of the second transistor T2 (that is, the second node N2) on the substrate and the orthographic projection of the subsequently formed data signal line on the substrate, the impact of the data voltage jump can be effectively shielded.
  • the influence of the key nodes in the pixel driving circuit avoids the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit, and improves the display effect.
  • the orthographic projection of at least a partial area of the shielding electrode 33 on the substrate may at least partially overlap with the orthographic projection of the subsequently formed data signal line on the substrate.
  • shielding electrodes 33 in adjacent circuit units in the first direction X may be connected to each other to reduce resistance.
  • the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, and the data connection electrode 42 is configured to be connected to a subsequently formed data signal line.
  • the first connection electrode 43 extends along the second direction Y, and its first end connects with the second region of the first active layer (which is also the first region of the second active layer) through the sixth via hole V6. region), the second end of which is connected to the first pole plate 24 through the first via hole V1, so that the first pole plate 24, the second pole of the first transistor T1 and the first pole of the second transistor T2 have the same potential .
  • the first connection electrode 43 may function as a second pole of the first transistor T1 and a first pole of the second transistor T2.
  • the first end of the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, and the second end thereof is connected to the first primary signal line 31 through the seventh via hole V7.
  • region also the first region of the first active layer
  • the second connection electrode 44 may serve as a first electrode of the seventh transistor T7 and a first electrode of the first transistor T1
  • the second connection electrode is configured to be connected to a second initial signal line formed subsequently.
  • the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second region of the sixth transistor T6 The pole and the second pole of the seventh transistor T7 have the same potential.
  • the third connection electrode 45 may function as a second pole of the sixth transistor T6 and a second pole of the seventh transistor T7.
  • the third connection electrode 45 is configured to be connected to a subsequently formed anode connection electrode.
  • the first power line 41 of at least one circuit unit may be a folded line of unequal width.
  • the first power supply line 41 of each circuit unit may include a first power supply part d1, a second power supply part d2, a third power supply part d3, a fourth power supply part d4 and a fifth power supply part connected in sequence d5, the first power supply part d1, the third power supply part d3 and the fifth power supply part d5 can be parallel to the second direction Y, the second power supply part d2 can be bent towards the first direction X, and the fourth power supply part d4 can be bent towards the first direction X. Bending in the opposite direction of direction X.
  • the angle between the second power supply part d2 and the first power supply part d1 can be greater than 0° and less than 90°, and the angle between the fourth power supply part d4 and the third power supply part d3 can be greater than 0° and less than 90°.
  • the fifth power supply part d5 is provided with a connection part d6 extending in a direction opposite to the first direction X, and the connection part d6 is configured to be connected to the fifth active layer through the third via hole.
  • the first power line 41 is arranged in a zigzag line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.
  • the shapes of the first power lines of the respective circuit units may be the same, or may be different.
  • the shape of the first power line in the circuit unit in the Mth row and the Nth column may be the same as the shape of the first power line in the M+1th row and the N+2th column circuit unit.
  • the shape of the first power line in the circuit unit in the Nth column of the 1st row can be the same as the shape of the first power line in the N+2th column circuit unit in the Mth row, and the shape of the first power line in the N+1th column circuit unit in the Mth row
  • the shape of a power supply line can be the same as the shape of the first power supply line in the circuit unit in the N+3th row of the M+1th row, and the shape of the first power supply line in the N+1th column circuit unit in the M+1th row is the same as
  • the shapes of the first power lines in the circuit units in the Mth row and the N+3th column may be the same.
  • the shape of the second connection electrode in each circuit unit of the Nth column may be the same as that of the second connection electrode in each circuit unit of the N+2th column, and the shape of the second connection electrode in each circuit unit of the N+1th column
  • the shape of the second connecting electrode in the N+3 column may be the same as that of the second connecting electrode in each circuit unit in the N+3th column.
  • the shape of the second connecting electrodes in the circuit units in the N+1th column and the N+3th column can be a strip shape extending along the second direction Y, and the second connecting electrodes are configured to pass through the ninth via hole and the seventh via hole respectively connected to the first initial signal line and the first region of the seventh active layer.
  • the shape of the second connection electrode 44 in the Nth column and the N+2th column circuit unit may include a first part 44-1 and a second part 44-2 connected to each other, the first part 44-1 is along the second In the shape of a strip extending in the direction Y, the second part 44-2 can be rectangular, and the second part 44-2 is arranged on the side of the first part 44-1 opposite to the first direction X, and the first part 44-1 is configured In order to connect to the first initial signal line and the first region of the seventh active layer through the ninth via hole and the seventh via hole respectively, the second part 44-2 is configured to connect with the subsequently formed second via hole through the subsequently formed via hole.
  • the initial signal lines are connected, so as to realize the connection between the first initial signal line and the second initial signal line.
  • the shapes of the third connection electrodes of the respective circuit units may be the same, or may be different.
  • the shape of the third connection electrode in the circuit unit of row M and column N may be the same as the shape of the third connection electrode in the circuit unit of row M+1 and column N+2.
  • the shape of the third connection electrode in the circuit unit in the Nth column of the 1st row can be the same as the shape of the third connection electrode in the N+2th column circuit unit in the Mth row, and the shape of the third connection electrode in the N+1th column circuit unit in the Mth row
  • the shape of the three connection electrodes may be the same as that of the third connection electrode in the circuit unit in the M+1th row and the N+3th column, and the shape of the third connection electrode in the M+1th row and the N+1th column circuit unit is the same as
  • the shapes of the third connection electrodes in the circuit units in the Mth row and the N+3th column may be the same.
  • the shapes of the data connection electrodes and the first connection electrodes of the respective circuit units may be the same, or may be different.
  • Forming a first flat layer pattern may include: coating the first planar film on the substrate on which the foregoing pattern is formed, and patterning the first planar film by a patterning process to form a covering third conductive layer.
  • the first flat layer, the first flat layer is provided with the eleventh via hole V11, the twelfth via hole V12 and the thirteenth via hole V13, as shown in FIG. 12a and FIG. A plan view of a via.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the data connection electrode 42 on the substrate, and the first flat layer in the eleventh via hole V11 is covered by It is removed to expose the surface of the data connection electrode 42 , and the eleventh via hole V11 is configured so that the subsequently formed data signal line is connected to the data connection electrode 42 through the via hole.
  • the eleventh via hole V11 may be in a bar shape, and an extension length in the second direction Y of the eleventh via hole V11 is greater than an extension length in the first direction X.
  • the eleventh via hole V11 in a strip shape extending along the second direction Y, the width of the eleventh via hole V11 in the first direction X can be reduced, and the degree of inclination of the subsequently formed anode can be reduced.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the second connection electrode 44 on the substrate, and the first flat layer in the twelfth via hole V12 is removed, exposing the second connection electrode 44 , the twelfth via hole V12 is configured so that the subsequently formed second initial signal line is connected to the second connection electrode 44 through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the third connection electrode 45 on the substrate, and the first flat layer in the thirteenth via hole V13 is removed, exposing the third connection electrode 45 , the thirteenth via hole V13 is configured to connect the subsequently formed anode connection electrode to the third connection electrode 45 through the via hole.
  • all circuit units are provided with an eleventh via hole V11 and a thirteenth via hole V13, and each circuit unit in the Nth column and the N+2th column is provided with a twelfth via V12 , the twelfth via hole V12 is not provided in each circuit unit in the N+1th column and the N+3th column.
  • the positions of the eleventh via hole V11 and the thirteenth via hole V13 in each circuit unit may be the same, or may be different.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film by a patterning process, and forming a layer disposed on the first planar layer.
  • the fourth conductive layer on the top, the fourth conductive layer at least includes: data signal line 51, second initial signal line 52 and anode connection electrode 53, as shown in Figure 13a and Figure 13b, Figure 13b is the fourth conductive layer in Figure 13a floor plan.
  • data signal lines 51 are arranged in each cell column.
  • the data signal line 51 may extend along the second direction Y, and the data signal line 51 is connected to the data connection electrode 42 through the eleventh via hole V11 . Since the data connection electrode 42 is connected to the first region of the fourth active layer through the fifth via hole V5, the data signal line 51 is connected to the first region of the fourth active layer through the data connection electrode 42, and the data signal is connected to the first region of the fourth active layer.
  • the second initial signal line 52 is disposed in the Nth unit column and the N+2th unit column, and the second initial signal lines 52 of each circuit unit in the unit column are connected to each other.
  • the main part of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second connection electrode 44 through the twelfth via hole V12 . Since the second connection electrode 44 is connected to the first initial signal line 31 through the ninth via hole V9, the second initial signal line 52 is connected to the first initial signal line 31 through the second connection electrode 44, so that the first initial signal The line 31 and the second initial signal line 52 have the same potential.
  • the initial signal line forms a mesh structure, which not only effectively reduces the initial signal
  • the resistance of the line reduces the voltage drop of the initial voltage, and effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.
  • the anode connection electrode 53 is disposed in at least part of the circuit unit.
  • the anode connection electrode 53 is connected to the third connection electrode 45 through the thirteenth via hole V13 . Since the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, the anode connection electrode 53 is connected to the second region of the seventh active layer through the third connection electrode 45.
  • the second region of the sixth active layer (also the second region of the seventh active layer) is connected.
  • the second initial signal line 52 in one circuit unit may include an extension part 521 and a connection part 522 .
  • the extension portion 521 may be a fold line extending along the second direction Y of the main body, and the connecting portion 522 may be a straight line extending along the first direction X of the main body.
  • an end portion of the connection portion 522 on a side away from the extension portion 521 may be connected to the second connection electrode 44 through the twelfth via hole V12 .
  • the orthographic projection of at least part of the extension 521 on the substrate is within the range of the orthographic projection of the first power line 41 on the substrate, which not only enables the first power line 41 to effectively shield the second initial signal line 52 influences on the key nodes in the pixel drive circuit, avoiding the initial signal from affecting the potential of the key nodes in the pixel drive circuit, and making full use of the layout space, avoiding the influence of light transmittance due to the setting of the second initial signal line, and improving the display effect.
  • the orthographic projection of at least part of the connecting portion 522 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can make full use of the layout space and avoid the need for setting the second initial signal line. It affects the light transmittance and improves the display effect.
  • the shape of the second initial signal line 52 in the circuit unit of the Mth row and the Nth column may be the same as that of the second initial signal line 52 in the circuit unit of the M+1th row and the N+2th column.
  • the shape of the second initial signal line 52 in the circuit unit at row M+1 and column N may be the same as the shape of the second initial signal line 52 in the circuit unit at row M and column N+2.
  • the extension part 521 may include the first initial part c1 sequentially connected along the second direction Y , the second initial part c2 and the third initial part c3, the first initial part c1 and the third initial part c3 can be parallel to the second direction Y, the second initial part c2 can deflect toward the opposite direction of the first direction X, the second The initial part c2 has a first included angle ⁇ 1 with the second direction Y, and the first included angle ⁇ 1 may be greater than 0° and less than 90°.
  • the extension part 521 may include a fourth initial part c4 sequentially connected along the second direction Y , the fifth initial part c5, the sixth initial part c6, the seventh initial part c7 and the eighth initial part c8, the fourth initial part c4, the sixth initial part c6 and the eighth initial part c8 may be parallel to the second direction Y,
  • the fifth initial portion c5 may have a first included angle ⁇ 1 with the second direction Y
  • the seventh initial portion c7 may have a second included angle ⁇ 2 with the second direction Y
  • the first included angle ⁇ 1 may be greater than 0° and less than 90°
  • the second included angle ⁇ 2 may be greater than 0° and less than 90°.
  • the extending direction of the fifth initial portion c5 and the extending direction of the seventh initial portion c7 may be mirror-symmetrical with respect to the first direction X.
  • At least some of the circuit units are provided with data signal lines 51 and anode connection electrodes 53, each circuit unit in the Nth column and the N+2th column is provided with a second initial signal line 52, and the N+th column is provided with a second initial signal line 52.
  • the second initial signal line 52 is not provided in each circuit unit in the 1st column and the N+3th column.
  • the shape of the anode connection electrode in the M row and N column circuit unit may be the same as the shape of the anode connection electrode in the M+1 row N+2 column circuit unit, and the shape of the anode connection electrode Can be rectangular.
  • the shape of the anode connection electrode in the circuit unit of row M+1 and column N can be the same as the shape of the anode connection electrode in the circuit unit of row M and column N+2, and the shape of the anode connection electrode can be a dumbbell shape.
  • the shape of the anode connection electrode in the circuit unit of row M and column N+1 can be the same as the shape of the anode connection electrode in the circuit unit of row M+1 and column N+3, and the shape of the anode connection electrode can be rectangular.
  • the shape of the anode connection electrode in the circuit unit of row M+1 and column N+1 can be the same as the shape of the anode connection electrode in the circuit unit of row M and column N+3, and the shape of the anode connection electrode can be rectangular.
  • forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, and patterning the second planar film by a patterning process to form a covering fourth conductive layer.
  • the second planar layer, the second planar layer is provided with a fourteenth via hole V14, as shown in Figure 14a and Figure 14b, Figure 14b is a schematic plan view of a plurality of via holes in Figure 14a.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is within the range of the orthographic projection of the anode connection electrode 53 on the substrate, and the second flat layer in the fourteenth via hole V14 is covered by Removed to expose the surface of the anode connection electrode 53 , the fourteenth via hole V14 is configured so that the subsequently formed anode is connected to the anode connection electrode 53 through the via hole.
  • the driving circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a light emission control circuit connected to the pixel driving circuit. line, data signal line, first power line, first initial signal line and second initial signal line.
  • the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a Four insulating layers, a third conductive layer, a first flat layer, a fourth conductive layer and a second flat layer.
  • a light emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode pattern may include: depositing a fifth conductive film on the substrate on which the foregoing pattern is formed, patterning the fifth conductive film by a patterning process, and forming an anode disposed on the second planar layer pattern, the anode forms the GGRB pixel arrangement, as shown in Figure 15a and Figure 15b, and Figure 15b is a schematic plan view of the anode in Figure 15a.
  • the anode pattern may include a first anode 71A of a red light-emitting device, a second anode 71B of a blue light-emitting device, a third anode 71C of a first green light-emitting device, and a first anode 71C of a second green light-emitting device.
  • the area where the first anode 71A is located can form a red sub-pixel R that emits red light
  • the area where the second anode 71B is located can form a blue sub-pixel B that emits blue light
  • the area where the third anode 71C is located can form a green sub-pixel that emits green light.
  • the first green sub-pixel G1 of the light, the area where the fourth anode 71D is located can form the second green sub-pixel G2 emitting green light
  • the red sub-pixel R and the blue sub-pixel B are arranged in sequence along the second direction Y
  • the first green The sub-pixel G1 and the second green sub-pixel G2 are arranged in sequence along the second direction Y
  • the first green sub-pixel G1 and the second green sub-pixel G2 are respectively arranged in the first direction X of the red sub-pixel R and the blue sub-pixel B.
  • the red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 form a pixel unit.
  • the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via hole V14 in the circuit unit in the Mth row and the Nth column
  • the second anode 71B is connected to the anode connection electrode 53 in the circuit unit through
  • the fourteenth via hole V14 in the circuit unit in the Nth column of the M+1 row is connected to the anode connection electrode 53 in the circuit unit
  • the third anode 71C passes through the fourteenth via hole V14 in the N+1 column circuit unit in the M row.
  • the via hole V14 is connected to the anode connection electrode 53 in the circuit unit, and the fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via hole V14 in the circuit unit in the M+1th row and the N+1th column connect.
  • the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via hole V14 in the circuit unit of the M+1th row and the N+2th column
  • the second anode 71B is connected to the anode connection electrode 53 in the circuit unit through the Mth
  • the fourteenth via hole V14 in the circuit unit in the N+2 column of the row is connected to the anode connection electrode 53 in the circuit unit
  • the third anode 71C passes through the fourteenth via hole V14 in the circuit unit in the N+3 column of the M+1 row.
  • the via hole V14 is connected to the anode connection electrode 53 in the circuit unit, and the fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via V14 in the circuit unit in the Mth row and the N+3th column.
  • the anode connection electrode 53 in at least one circuit unit is connected to the third connection electrode 45 through the thirteenth via hole V13, and the third connection electrode 45 is connected to the sixth active electrode 45 through the fourth via hole V4.
  • the second region of the layer also the second region of the seventh active layer
  • the third connection electrode 45 is used as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, so that the anode can connect the electrode through the anode 53 and the third connection electrode 45 are connected to the sixth transistor T6 and the seventh transistor T7, and the four anodes in at least one pixel unit are respectively connected to the pixel driving circuits of the four circuit units in one circuit unit group, realizing The pixel driving circuit can drive the light emitting device to emit light.
  • the positional relationship between the four sub-pixels of one pixel unit and the four circuit units in one circuit unit group may be the same, or may be different.
  • the main part of the first anode 71A is located on the opposite side of the first direction X of the corresponding connected circuit unit, and the orthographic projection of the first anode 71A on the substrate can be compared with that of the second initial signal line. Orthographic projections of the extensions on the base at least partially overlap.
  • the main part of the second anode 71B is located on one side of the corresponding connected circuit unit in the first direction X, and the orthographic projection of the second anode 71B on the substrate can at least partially overlap with the orthographic projection of the data signal line on the substrate.
  • the main part of the third anode 71C is located on one side of the corresponding connected circuit unit in the second direction Y, and the main part of the fourth anode 71D is located in the next row of circuit units corresponding to the connected circuit unit.
  • the main body of the first anode 71A can be located on one side of the corresponding connected circuit unit in the first direction X, and the orthographic projection of the first anode 71A on the substrate can be aligned with the data signal line on the substrate.
  • the orthographic projections on are at least partially overlapping.
  • the main part of the second anode 71B can be located on the opposite side of the first direction X of the corresponding connected circuit unit, and the orthographic projection of the second anode 71B on the substrate can be the same as the orthographic projection of the extension of the second initial signal line on the substrate. overlap at least partially.
  • the shapes and positions of the first anodes 71A in different pixel units may be the same, or may be different.
  • the shapes and positions of the second anodes 71B in different pixel units may be the same or different.
  • the shapes and positions of the third anodes 71C in different pixel units may be the same or different.
  • the shapes and positions of the fourth anodes 71D in different pixel units may be the same or different.
  • the shapes and positions of the two first anodes 71A respectively connected to the pixel driving circuit in the circuit unit in the Mth row and the Nth column and the M+1th row and the N+2th column circuit unit are the same, respectively.
  • the shapes and positions of the two second anodes 71B connected to the pixel drive circuit in the M+1th row N+2 column circuit unit and the Mth row N+2th column circuit unit are the same in shape and position, and are respectively connected to the Mth row N+1 column
  • the shape and position of the circuit unit and the two third anodes 71C connected to the pixel drive circuit in the M+1th row N+3th column circuit unit are the same, and are respectively the same as the M+1th row N+1th column circuit unit and the Mth
  • the shapes and positions of the two fourth anodes 71D connected to the pixel driving circuit in the circuit unit in the N+3th column of the row are the same.
  • anode shapes and areas of four sub-pixels in one pixel unit may be the same, or may be different.
  • the shapes and areas of the first anode 71A, the second anode 71B, the third anode 71C, and the fourth anode 71D in one pixel unit are different.
  • the first anode 71A in the red sub-pixel may include a first anode body part, and the shape of the first anode body part may be hexagon-like.
  • the first anode 71A may further include a first protrusion 71-1 and a second protrusion 71-2, and both the first protrusion 71-1 and the second protrusion 71-2 are connected to the first anode
  • the main body part is connected, the first protrusion 71-1 can be a rectangle protruding towards the gate electrode of the third transistor T3 in the connected pixel driving circuit, and the second protrusion 71-2 can be close to the connected pixel driving circuit.
  • the sixth transistor T6 in the circuit protrudes into a rectangle, the first protrusion 71-1 and the second protrusion 71-2 are configured to adjust the parasitic capacitance of the N3 node in the connected pixel drive circuit, and reduce the N3 in the adjacent circuit unit
  • the difference between the parasitic capacitances of the nodes can reduce the brightness difference and improve the display effect.
  • the second anode 71B in the blue sub-pixel may include a second anode body part, and the shape of the second anode body part may be hexagon-like.
  • the second anode 71B may further include a third protrusion 71-3, a fourth protrusion 71-4, and a fifth protrusion 71-5, the third protrusion 71-3, the fourth protrusion 71-4 and the fifth protrusion 71-5 are both connected to the second anode main body, the third protrusion 71-3 can be a rectangle protruding toward the first power line in the connected pixel drive circuit, and the fourth protrusion
  • the protrusion 71-4 may be a rectangle protruding away from the first power line in the connected pixel driving circuit, and the fifth protrusion 71-5 may be a polygon protruding toward the sixth transistor T6 in the connected pixel driving circuit.
  • the third protrusion 71-3, the fourth protrusion 71-4 and the fifth protrusion 71-5 are configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, and reduce the parasitic capacitance of the N3 node in the adjacent circuit unit
  • the difference between the capacitors can reduce the brightness difference and improve the display effect.
  • the third anode 71C may include a third anode body part, and the shape of the third anode body part may be pentagon-like.
  • the third anode 71C may further include a sixth protrusion 71-6, the sixth protrusion 71-6 is connected to the third anode body part, and the sixth protrusion 71-6 may be toward the connected
  • the sixth transistor T6 protrudes in the pixel driving circuit, and the sixth protrusion 71-6 is configured to adjust the parasitic capacitance of the N3 node in the pixel driving circuit connected to this place, and reduce the parasitic capacitance of the N3 node in adjacent circuit units. to reduce the brightness difference, especially to reduce the brightness difference between this sub-pixel and the second green sub-pixel, and improve the display effect.
  • the fourth anode 71D may include a fourth anode body part, and the shape of the fourth anode body part may be pentagon-like.
  • the fourth anode 71D may further include a seventh protrusion 71-7 connected to the main body of the fourth anode, the seventh protrusion 71-7 may be toward the connected
  • the gate electrode of the third transistor T3 in the pixel driving circuit protrudes in a strip shape, and the seventh protrusion 71-7 is configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, and reduce the N3 node in the adjacent circuit unit
  • the difference between the parasitic capacitances is used to reduce the difference in brightness, especially to reduce the difference in brightness between the sub-pixel and the first green sub-pixel, so as to improve the display effect.
  • Forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the foregoing pattern is formed, and patterning the pixel definition film through a patterning process to form a pattern of the pixel definition layer 72, as shown in FIG. 16a and 16b, FIG. 16b is a schematic plan view of the pixel definition layer in FIG. 16a.
  • the pattern of the pixel definition layer 72 may include a first pixel opening 73A exposing the first anode 71A, a second pixel opening 73B exposing the second anode 71B, and a third pixel opening 73B exposing the third anode 71C. Three pixel openings 73C and a fourth pixel opening 73D exposing the fourth anode 71D.
  • the orthographic projection of the first pixel opening 73A on the substrate has a first centerline Z1
  • the orthographic projection of the extension of the second initial signal line 52 on the substrate has a second centerline
  • the first centerline Z1 is a line extending along the second direction Y and bisecting the orthographic projection of the first pixel opening 73A on the substrate in the first direction X
  • the second central line is extending along the second direction Y and bisecting the first direction X
  • the second centerline is a line extending along the second direction Y and bisecting in the first direction X the orthographic projection of the first initial portion c1 in the extended portion on the base.
  • the first centerline at least partially overlaps the second centerline.
  • the orthographic projection of the second pixel opening 73B on the substrate has a third centerline Z3
  • the orthographic projection of the data signal line 51 on the substrate has a fourth centerline
  • the third centerline Z3 is along the The line extending along the second direction Y and bisecting the orthographic projection of the second pixel opening 73B on the substrate in the first direction X
  • the fourth center line is extending along the second direction Y and bisecting the data signal line on the substrate in the first direction X
  • the third centerline at least partially overlaps the fourth centerline.
  • the data signal line in the second pixel opening 73B can be left and right symmetrical, ensuring the flatness of the second anode. Sexuality can avoid biased roles.
  • the “half A” mentioned in this disclosure may mean that the centerline makes the distances between the two sides of the orthographic projection of A on the base and the centerline substantially equal, and the distances between the two sides and the centerline may be substantially equal due to process or tolerances. deviations within the range.
  • the ratio of the minimum distance between the two side edges of the orthographic projection of A on the base and the center line may be about 0.8 to 1.2.
  • the “overlapping of A and B” mentioned in the present disclosure does not require that A and B are completely overlapped, and there may be deviations within the allowable range caused by processes or tolerances.
  • the signal line can be widened and substantially consistent with the shape of the anode.
  • the signal line can be divided into left and right sections, and the two sections are located on both sides of the center line and symmetrically placed under the two sides of the anode.
  • the signal line may be located on both sides of the center line and divided into two lines, respectively placed on the left and right sides of the anode, etc., which is not limited in this disclosure.
  • the subsequent preparation process may include: forming an organic light-emitting layer by evaporation or inkjet printing process, the organic light-emitting layer is connected to the anode through the pixel opening, and a cathode is formed on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer .
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, one or more of textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can adopt materials such as polyimide (PI), polyethylene terephthalate (PET) or through the polymer soft film of surface treatment, the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may use metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo Wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo )
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), Can be single layer, multilayer or composite layer.
  • the first insulating layer is called the buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), Materials such as hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • the first flat layer and the second flat layer can be made of organic materials, such as resin and the like.
  • the fifth conductive layer can adopt a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO/Ag/ITO and the like.
  • the pixel definition layer can be polyimide, acrylic or polyethylene terephthalate.
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy.
  • the display substrate provided by the present disclosure, by setting the first initial signal line whose main part extends along the first direction and the second initial signal line whose main part extends along the second direction, line, the first initial signal line and the second initial signal line are connected through via holes, so that the initial signal line forms a mesh structure, which not only effectively reduces the resistance of the initial signal line, reduces the voltage drop of the initial voltage, but also effectively improves the
  • the uniformity of the initial voltage in the display substrate effectively improves the display uniformity, improves the display quality and display quality.
  • the first initial signal line and the second initial signal line are arranged on different conductive layers, and the extension part of the second initial signal line overlaps with the first power line at least partially, and the connection part of the second initial signal line and the first power line
  • An initial signal line is at least partially overlapped, not only can the first power line effectively shield the influence of the second initial signal line on key nodes in the pixel driving circuit, and prevent the initial signal from affecting the potential of the key node of the pixel driving circuit, but also can make full use of the layout Space, to avoid the light transmittance being affected by the setting of the second initial signal line.
  • the second initial signal line in the first unit column by arranging the second initial signal line in the first unit column, the brightness difference between two green sub-pixels in the same pixel unit can be avoided, and the display quality can be improved.
  • the second initial signal line in the first pixel opening by setting the first center line of the first pixel opening to at least partially overlap with the second center line of the extension part of the second initial signal line, the second initial signal line in the first pixel opening can maintain left-right symmetry, ensuring The flatness of the first anode can avoid large viewing angle deviation and improve display quality.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high in production efficiency, low in production cost and high in yield.
  • Fig. 17a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure
  • Fig. 17b is a schematic plan view of the fourth conductive layer in Fig. 17a, showing eight circuit units (two unit rows and four unit columns) planar structure.
  • this exemplary embodiment drives the data signal line 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the circuit layer.
  • the structure is basically similar to the previous embodiment, the difference is that the second initial signal lines 52 in the fourth conductive layer are arranged in some circuit units in a unit column, and two adjacent second initial signal lines in a unit column 52 may be mutually isolated.
  • the main part of the second initial signal line 52 is respectively arranged in the circuit unit of the Mth row, the Nth column, and the M+1th row, the N+2th column circuit unit , the second initial signal line 52 is not only connected to the second connection electrode 44 of the current circuit unit through the twelfth via hole V12 of the current circuit unit, but also connected to the second connection electrode 44 of the next row of circuit units through the twelfth via hole V12 of the next row of circuit units.
  • the second connection electrode 44 is connected.
  • the second initial signal line 52 is connected to the second connection electrode 44 of the circuit unit in row M and column N through the twelfth via hole V12 of the circuit unit in row M and column N , through the twelfth via hole V12 of the circuit unit in the M+1th row and the Nth column to be connected to the second connection electrode 44 of the circuit unit in the M+1th row and the Nth column.
  • the second initial signal line 52 passes through the twelfth via hole V12 of the circuit unit in row M+1 and column N and the second via hole V12 of the circuit unit in row M+1 and column N.
  • the connecting electrode 44 is connected to the second connecting electrode 44 of the circuit unit in the M+2th row and Nth column through the twelfth via hole V12 of the M+2th row and Nth column circuit unit.
  • At least one second initial signal line 52 may include an extension part 521 , a first connection part 523 and a second connection part 524 .
  • the extension part 521 can be a fold line extending along the second direction Y of the main body part
  • the first connecting part 523 and the second connecting part 524 can be straight lines extending along the first direction X of the main part
  • the first connecting part 523 can be arranged on In this circuit unit, the second connection portion 524 may be disposed in the next row of circuit units.
  • the end of the first connection part 523 away from the extension part 521 can be connected to the second connection electrode 44 of the circuit unit through the twelfth via hole V12 of the circuit unit, and the second connection part 524 The end of the side away from the extension portion 521 is connected to the second connection electrode 44 of the next row of circuit units through the twelfth via hole V12 of the next row of circuit units.
  • one second initial signal line 52 can be connected to the first initial signal lines of two cell rows, so that the first initial signal line and the second initial signal line form a network structure.
  • the orthographic projection of the extension part 521 on the base is at least partially within the range of the orthographic projection of the first power line 41 on the base, and the first connection part 523 and the second connection part 524 on the base
  • the orthographic projection is at least partly within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can make full use of the layout space, avoid affecting the light transmittance due to the arrangement of the second initial signal line, and improve the display effect.
  • the subsequent process of forming the light emitting structure layer is basically similar to that of the foregoing embodiments.
  • the orthographic projection of the first anode on the substrate may at least partially overlap with the orthographic projection of the extension of the second initial signal line on the substrate, the first center line of the first pixel opening and the second initial signal line
  • the second centerline of the extended part of the extended part at least partially overlaps, so that the flatness of the first anode can be ensured, and large viewing angle deviation can be avoided.
  • Fig. 18a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure
  • Fig. 18b is a schematic plan view of the fourth conductive layer in Fig. 18a, showing eight circuit units (two unit rows and four unit columns) planar structure.
  • this exemplary embodiment drives the data signal line 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the circuit layer.
  • the structure is basically similar to the previous embodiment, the difference is that the second initial signal lines 52 in the fourth conductive layer are arranged in some circuit units in a unit column, and two adjacent second initial signal lines in a unit column 52 may be mutually isolated.
  • the main part of the second initial signal line 52 is respectively arranged in the circuit unit of the M+1th row of the Nth column and the Mth row of the N+2th column circuit unit , the second initial signal line 52 is not only connected to the second connection electrode 44 of the current circuit unit through the twelfth via hole V12 of the current circuit unit, but also connected to the second connection electrode 44 of the next row of circuit units through the twelfth via hole V12 of the next row of circuit units.
  • the second connection electrode 44 is connected.
  • the main body structure of at least one second initial signal line 52 may include an extension part 521, a first connection part 523 and a second connection part 524, and the extension part 521, the first connection part 523 and the second connection part 524 may be similar to the structure described in FIG. 17b, and one second initial signal line 52 may be connected to the first initial signal lines of two cell rows, so that the first initial signal line and the second initial signal line form a network structure.
  • the orthographic projection of the extension portion 521 on the base is at least partially within the range of the orthographic projection of the first power line 41 on the base, and the orthographic projections of the first connecting portion 523 and the second connecting portion 524 on the base are at least partially within the first
  • the original signal line 31 is within the range of the orthographic projection on the substrate, which can make full use of the layout space, avoid the light transmittance being affected by the second initial signal line, and improve the display effect.
  • the subsequent process of forming the light emitting structure layer is basically similar to that of the foregoing embodiments.
  • the orthographic projections of the first anode and the second anode on the substrate may have no overlapping area with the orthographic projection of the second initial signal line on the substrate, and the extension of the second initial signal line does not pass through any pixel
  • the opening can further ensure the flatness of the first anode and the second anode, and can avoid large viewing angle deviation.
  • Fig. 19a is a schematic structural diagram of yet another driving circuit layer according to an exemplary embodiment of the present disclosure
  • Fig. 19b is a schematic plan view of the fourth conductive layer in Fig. 19a, illustrating eight circuit units (two unit rows and four unit columns) planar structure.
  • this exemplary embodiment drives the data signal line 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the circuit layer.
  • the structure is basically similar to the previous embodiment, the difference is that the second initial signal line 52 in the fourth conductive layer is arranged in the N+1th unit column and the N+3th unit column, and each circuit unit in the unit column The second initial signal lines 52 are connected to each other.
  • the second connection electrodes 44 in the N+1th column and the N+3th column of circuit units include a first portion and a second portion connected to each other.
  • the main part of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second part of the second connection electrode 44 through the twelfth via hole V12 in each circuit unit, so that the first The initial signal line and the second initial signal line form a mesh structure.
  • the shape of the second initial signal line 52 in the circuit unit of the N+1th column in the Mth row is the same as the shape of the second initial signal line 52 in the N+3th column circuit unit in the M+1th row It may be the same, the shape of the second initial signal line 52 in the circuit unit of row M+1 and column N+1 may be the same as the shape of the second initial signal line 52 in the circuit unit of row M and column N+3.
  • the second initial signal line 52 in one circuit unit may include an extension part 525 and a connection part 526 .
  • the extension portion 525 may be a fold line extending along the second direction Y of the main body, and the connecting portion 526 may be a straight line extending along the first direction X of the main body.
  • an end portion of the connection portion 526 on a side away from the extension portion 525 may be connected to the second connection electrode 44 through the twelfth via hole V12 .
  • the orthographic projection of the extension part 525 on the base is at least partially within the range of the orthographic projection of the first power line 41 on the base, which not only enables the first power line 41 to effectively shield the second initial signal line 52 influences on the key nodes in the pixel drive circuit, avoiding the initial signal from affecting the potential of the key nodes in the pixel drive circuit, and making full use of the layout space, avoiding the influence of light transmittance due to the setting of the second initial signal line, and improving the display effect.
  • the orthographic projection of the connecting portion 526 on the substrate is at least partially within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can make full use of the layout space and avoid the need for setting the second initial signal line. It affects the light transmittance and improves the display effect.
  • the subsequent process of forming the light emitting structure layer is basically similar to that of the foregoing embodiments.
  • the orthographic projections of the third anode and the fourth anode on the substrate may at least partially overlap with the orthographic projection of the connecting portion of the second initial signal line on the substrate, while the first anode and the second anode are on the substrate.
  • the orthographic projection of is not overlapped with the orthographic projection of the second initial signal line on the substrate, and the orthographic projections of the first pixel opening and the second pixel opening on the substrate are not overlapped with the orthographic projection of the second initial signal line on the substrate, that is,
  • the two initial signal lines do not pass through the first pixel opening and the second pixel opening, so that the flatness of the first anode and the second anode can be ensured, and large viewing angle deviation can be avoided.
  • the area where the first green pixel opening and/or the second green pixel opening are located can be thickened.
  • the planarity of the third anode and/or the fourth anode can be improved by means such as the thickness of the planar layer.
  • the second initial signal line 52 can be set in some circuit units in the N+1th unit column and the N+3th unit column, and two adjacent second initial signal lines in a unit column Lines 52 may be isolated from each other.
  • the main part of the second initial signal line 52 can be respectively arranged in the circuit unit in the Mth row, column N+1 and the circuit unit in the M+1th row, N+3 column, so that the subsequently formed third anode is on the substrate.
  • the orthographic projection of and the orthographic projection of the extension of the second initial signal line on the substrate at least partially overlap, while the orthographic projection of the fourth anode on the substrate has no overlapping area with the orthographic projection of the extension of the second initial signal line on the substrate .
  • the main part of the second initial signal line 52 can be respectively arranged in the circuit unit in the M+1th row, the N+1th column and the Mth row, the N+3th column circuit unit, so that the fourth anode formed subsequently is on the substrate.
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the extension of the second initial signal line on the substrate, while the orthographic projection of the third anode on the substrate does not overlap the orthographic projection of the extension of the second initial signal line on the substrate.
  • the region is not limited in this disclosure.
  • Fig. 20a is a schematic structural diagram of yet another driving circuit layer according to an exemplary embodiment of the present disclosure
  • Fig. 20b is a schematic plan view of the fourth conductive layer in Fig. 20a, illustrating eight circuit units (two unit rows and four unit columns) planar structure.
  • this exemplary embodiment drives the data signal line 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the circuit layer.
  • the structure is basically similar to that of the previous embodiment, except that the second initial signal lines 52 in the fourth conductive layer are respectively arranged in the N-th unit column, the N+1-th unit column, the N+2-th unit column and the N-th unit column. In +3 unit columns, the second initial signal lines 52 of each circuit unit in at least one unit column are connected to each other.
  • the second connection electrode 44 in at least one column of circuit units includes a first portion and a second portion connected to each other.
  • the main part of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second part of the second connection electrode 44 through the twelfth via hole V12 in each circuit unit, so that the first The initial signal line and the second initial signal line form a mesh structure, which minimizes the resistance of the initial signal line, reduces the voltage drop of the initial voltage, and effectively improves the uniformity of the initial voltage in the display substrate, effectively improving the Display uniformity, improved display quality and display quality.
  • the second initial signal line 52 of one circuit cell may include an extension part 521 and a connection part 522 .
  • the extension portion 521 may be a fold line extending along the second direction Y of the main body, and the connecting portion 522 may be a straight line extending along the first direction X of the main body.
  • an end portion of the connection portion 522 on a side away from the extension portion 521 may be connected to the second connection electrode 44 through the twelfth via hole V12 .
  • the second initial signal line 52 of one circuit cell may include an extension part 525 and a connection part 526 .
  • the extension portion 525 may be a fold line extending along the second direction Y of the main body, and the connecting portion 526 may be a straight line extending along the first direction X of the main body.
  • an end portion of the connection portion 526 on a side away from the extension portion 525 may be connected to the second connection electrode 44 through the twelfth via hole V12 .
  • the orthographic projections of the extension portion 521 and the extension portion 525 on the base are at least partially within the range of the orthographic projection of the first power line 41 on the base, which not only enables the first power line 41 to effectively shield the second
  • the impact of the second initial signal line 52 on the key nodes in the pixel drive circuit can prevent the initial signal from affecting the potential of the key nodes of the pixel drive circuit, and can make full use of the layout space, avoiding the influence of light transmittance due to the setting of the second initial signal line, and improving display effect.
  • the orthographic projections of the connecting portion 522 and the connecting portion 526 on the substrate are at least partially within the range of the orthographic projection of the first initial signal line 31 on the substrate, which can make full use of the layout space and avoid the The second initial signal line affects the light transmittance and improves the display effect.
  • the subsequent process of forming the light emitting structure layer is basically similar to that of the foregoing embodiments.
  • the orthographic projections of the first anode, the second anode, the third anode and the fourth anode on the substrate may at least partially overlap with the orthographic projection of the second initial signal line on the substrate, and the first pixel opening A centerline at least partially overlaps with a second centerline of the extension of the second initial signal line, and a third centerline of the second pixel opening at least partially overlaps with a fourth centerline of the data signal line, which helps to eliminate the flatness of each anode Differences between genders can avoid overestimating role bias.
  • the area where the first green pixel opening and/or the second green pixel opening are located can be improved by means such as increasing the thickness of the flat layer.
  • the flatness of the third anode and/or the fourth anode can be improved by means such as increasing the thickness of the flat layer.
  • the second initial signal line 52 may be arranged in some circuit units in the Nth unit column, the N+1th unit column, the N+2th unit column, and the N+3th unit column, Two adjacent second initial signal lines 52 in a cell column may be isolated from each other.
  • the second initial signal lines 52 of adjacent circuit units can be connected to each other, and in the N+1th unit column and the N+3th unit column, the second The initial signal line 52 may only be provided in the circuit unit in the N+1th column of the Mth row and the N+3th column circuit unit in the M+1th row, or the second initial signal line 52 may only be provided in the Nth row of the Mth row +3 column circuit units and M+1th row N+1th column circuit units.
  • the second initial signal lines 52 of adjacent circuit units may be connected to each other, and in the Nth unit column and the N+2th unit column, the The second initial signal line 52 may only be provided in the circuit unit at the Nth column of the Mth row and the N+2th column circuit unit in the M+1th row, or the second initial signal line 52 may only be provided in the N+th row of the Mth row.
  • the circuit units in the 2 columns and in the circuit units in the M+1th row and the Nth column may be connected to each other, and in the Nth unit column and the N+2th unit column.
  • the second initial signal line 52 may only be provided in the circuit unit in the Nth column of the Mth row and the N+2th column circuit unit in the M+1th row, or the second initial signal line 52 may only be provided in the Mth row In the N+2th column circuit unit in the row and the M+1th row Nth column circuit unit, the second initial signal line 52 can only be provided with the Mth row N+1th column circuit unit and the M+1th row N+1th circuit unit In 3 columns of circuit units, alternatively, the second initial signal line 52 may only be provided in the circuit units in the Mth row, N+3th column and the M+1th row, N+1th column circuit unit, which is not limited in this disclosure .
  • Fig. 21a is another schematic diagram of an anode pattern formed in an exemplary embodiment of the present disclosure
  • Fig. 21b is a schematic plan view of the anode in Fig. 21a, illustrating the planar structure of eight circuit units (2 unit rows and 4 unit columns).
  • the structure of the driving circuit layer in this exemplary embodiment is basically similar to that of the previous embodiment, and the second initial signal line 52 in the fourth conductive layer is arranged in the Nth unit column and the N+1th unit column 1.
  • the second initial signal line 52 of each circuit unit in the unit row is connected to each other, the difference is that the anodes of the light emitting structure layer are arranged in a diamond shape, forming RGBG pixel arrangement.
  • the anode pattern may include a first anode 71A of a red light emitting device, a second anode 71B of a blue light emitting device, a third anode 71C of a first green light emitting device, and a first anode 71C of a second green light emitting device.
  • the area where the first anode 71A is located can form a red sub-pixel R that emits red light
  • the area where the second anode 71B is located can form a blue sub-pixel B that emits blue light
  • the area where the third anode 71C is located can form a green sub-pixel that emits green light.
  • the first green sub-pixel G1 of the light, the area where the fourth anode 71D is located can form the second green sub-pixel G2 emitting green light
  • the red sub-pixel R and the blue sub-pixel B are arranged in sequence along the second direction Y
  • the first green The sub-pixel G1 and the second green sub-pixel G2 are arranged in sequence along the first direction X
  • the first green sub-pixel G1 is arranged on the opposite side of the first direction X of the red sub-pixel R and the blue sub-pixel B
  • the sub-pixel G2 is arranged on one side of the red sub-pixel R and the blue sub-pixel B in the first direction X
  • the red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 form a pixel unit.
  • the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via hole V14 in the circuit unit in the Mth row and the Nth column
  • the second anode 71B is connected to the anode connection electrode 53 in the circuit unit through
  • the fourteenth via hole V14 in the circuit unit in the Nth column of the M+1 row is connected to the anode connection electrode 53 in the circuit unit
  • the third anode 71C passes through the fourteenth via hole V14 in the N+1 column circuit unit in the M row.
  • the via hole V14 is connected to the anode connection electrode 53 in the circuit unit, and the fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via V14 in the circuit unit in the Mth row and the N ⁇ 1 column.
  • the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via hole V14 in the circuit unit of the M+1th row and the N+2th column
  • the second anode 71B is connected to the anode connection electrode 53 in the circuit unit through the Mth
  • the fourteenth via hole V14 in the circuit unit in the N+2 column of the row is connected to the anode connection electrode 53 in the circuit unit
  • the third anode 71C passes through the fourteenth via hole in the circuit unit in the N+1 column of the M row V14 is connected to the anode connection electrode 53 in the circuit unit
  • the fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the fourteenth via V14 in the circuit unit in row M, column N+3.
  • the orthographic projections of the first anode 71A and the second anode 71B on the substrate may at least partially overlap with the orthographic projection of the extension of the second initial signal line on the substrate, and the third anode 71C and the fourth anode
  • the orthographic projection of 71D on the substrate may at least partially overlap with the orthographic projection of the connection portion of the second initial signal line on the substrate.
  • the shapes and positions of the anodes in different pixel units may be the same or different, and the shapes and areas of the anodes of four sub-pixels in one pixel unit may be the same or different, which is not limited by the present disclosure. .
  • Fig. 22a is a schematic diagram of another patterned pixel definition layer according to an exemplary embodiment of the present disclosure.
  • Fig. 22b is a schematic plan view of the pixel definition layer in Fig. 22a, showing eight circuit units (2 unit rows and 4 unit columns) plane structure.
  • the structures of the driving circuit layer and the anode in this exemplary embodiment are basically similar to those of the foregoing embodiments, except that the openings of the pixel definition layer 72 in the light emitting structure layer are arranged in a diamond shape.
  • the pattern of the pixel definition layer 72 may include a first pixel opening 73A exposing the first anode 71A, a second pixel opening 73B exposing the second anode 71B, and a first pixel opening 73B exposing the third anode 71C. Three pixel openings 73C and a fourth pixel opening 73D exposing the fourth anode 71D.
  • the orthographic projection of the first pixel opening 73A on the substrate has a first centerline Z1
  • the orthographic projection of the extension of the second initial signal line 52 on the substrate has a second centerline
  • the second pixel opening The orthographic projection of 73B on the substrate has a third centerline Z3
  • the orthographic projection of the data signal line 51 on the substrate has a fourth centerline
  • the first centerline Z1 extends along the second direction Y and in the first direction X
  • the line that bisects the orthographic projection of the first pixel opening 73A on the substrate, the second central line is the line that extends along the second direction Y and bisects the extension of the second initial signal line in the first direction X and that is the line that is orthographic projection on the substrate
  • the third central line Z3 is a line extending along the second direction Y and bisecting the second pixel opening 73B on the substrate in the first direction X
  • the fourth central line is extending along the second direction Y and in
  • the "half A” mentioned in this disclosure may mean that the center line makes the two sides of the orthographic projection of A on the substrate have substantially equal areas, and the areas on both sides may be substantially equal due to process or tolerance deviations within the allowable range.
  • the area ratio of the two sides is about 0.8 to 1.2.
  • the “overlapping of A and B” mentioned in the present disclosure does not require that A and B are completely overlapped, and there may be deviations within the allowable range caused by processes or tolerances.
  • the first centerline Z1 may at least partially overlap with the third centerline Z3, the second centerline and the fourth centerline may be located on both sides of the first centerline Z1, the second centerline and the fourth centerline The centerline may be located on either side of the third centerline.
  • the second central line of the second initial signal line and the fourth central line of the data signal line may be arranged symmetrically with respect to the first central line Z1 of the first pixel opening, and the second central line of the second initial signal line
  • the center line and the fourth center line of the data signal line may be symmetrically arranged with respect to the third center line Z3 of the second pixel opening.
  • centerline A and centerline B are arranged symmetrically with respect to centerline C in this disclosure means that the ratio of the distance between centerline A and centerline C to the distance between centerline B and centerline C is approximately 0.8 to 1.2.
  • the position of the anode in the circuit unit can be adjusted so that the second centerline of the second initial signal line is aligned with the first centerline of the first pixel opening and the third centerline of the second pixel opening. overlap, or make the fourth centerline of the data signal line overlap with the first centerline of the first pixel opening and the third centerline of the second pixel opening, which is not limited in this disclosure.
  • the orthographic projection of the third pixel opening 73C on the substrate has a fifth centerline Z5
  • the orthographic projection of the fourth pixel opening 73D on the substrate has a sixth centerline Z6, and the second initial signal line 52
  • the orthographic projection of the connection portion on the substrate has a seventh centerline
  • the fifth centerline Z5 is a line extending along the first direction X and bisects the third pixel opening 73C on the substrate in the second direction Y
  • the sixth The central line Z6 is a line extending along the first direction X and bisecting the orthographic projection of the fourth pixel opening 73D on the substrate in the second direction Y
  • the seventh central line is extending along the first direction X and in the second direction Y A line that bisects the connecting portion of the second initial signal line 52 on the substrate orthographically projected.
  • the fifth centerline Z5 may at least partially overlap the seventh centerline
  • the sixth centerline Z6 may at least partially overlap the seventh centerline.
  • the fifth centerline of the third pixel opening 73C at least partially overlapping the seventh centerline of the connection part of the second initial signal line
  • the connection of the sixth centerline of the fourth pixel opening 73D and the second initial signal line The seventh center line of the first part overlaps at least partially, which can ensure the flatness of the third anode and the fourth anode, and can avoid large viewing angle deviation.
  • the structure and its preparation process shown above in the present disclosure are only exemplary illustrations. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the first initial signal line may be disposed in the first conductive layer (GATE 1).
  • the second initial signal line may be disposed in the third conductive layer ( SD1 ), and the first power line may be disposed in the fourth conductive layer ( SD2 ), which is not limited in this disclosure.
  • the display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, and the present disclosure is not limited here.
  • the present disclosure also provides a method for preparing a display substrate, so as to manufacture the display substrate provided by the above-mentioned embodiments.
  • the display substrate includes a driving circuit layer disposed on a base and a light emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer includes a plurality of circuit units, The light emitting structure layer includes a plurality of light emitting devices; at least one circuit unit includes a first power supply line, an initial signal line and a pixel driving circuit, and the initial signal line includes a first initial signal line extending along a first direction and a first initial signal line extending along a second direction. A second initial signal line extending in a direction where the first direction crosses the second direction; the preparation method includes:
  • a second initial signal line extending along the second direction is formed, and an orthographic projection of the second initial signal line on the substrate at least partially overlaps with an orthographic projection of the first power supply line on the substrate.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator, and the embodiment of the present invention is not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其制备方法、显示装置。所述显示基板包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括多个电路单元，所述发光结构层包括多个发光器件；至少一个电路单元包括第一电源线、初始信号线和像素驱动电路，所述初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，所述第一方向与第二方向交叉；所述第二初始信号线在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括多个电路单元，所述发光结构层包括多个发光器件；至少一个电路单元包括第一电源线、初始信号线和像素驱动电路，所述初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，所述第一方向与第二方向交叉；所述第二初始信号线在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠。
在示例性实施方式中，至少一个电路单元中的所述第二初始信号线包括相互连接的延伸部和连接部，所述延伸部沿所述第二方向延伸，所述连接部沿所述第一方向延伸，所述连接部通过过孔与所述第一初始信号线连接。
在示例性实施方式中，所述延伸部在基底上的正投影与所述第一电源线 在基底上的正投影至少部分重叠，所述连接部在基底上的正投影与所述第一初始信号线在基底上的正投影至少部分重叠。
在示例性实施方式中，至少一个电路单元包括第二连接电极，所述连接部通过过孔与所述第二连接电极连接，所述第二连接电极通过过孔与所述第一初始信号线连接。
在示例性实施方式中，所述第二连接电极通过过孔与所述像素驱动电路中第一晶体管的有源层第一区和第七晶体管的有源层第一区连接。
在示例性实施方式中，所述驱动电路层包括多个单元行和多个单元列，所述单元行包括沿所述第一方向排布的多个电路单元，所述单元列包括沿所述第二方向排布的多个电路单元；至少一个单元列中，相邻电路单元中的第二初始信号线相互连接，或者，相邻电路单元中的第二初始信号线间隔设置。
在示例性实施方式中，所述多个电路单元包括与出射红色光线的红色发光器件连接的第一电路单元、与出射蓝色光线的蓝色发光器件连接的第二电路单元、与出射绿色光线的第一绿色发光器件连接的第三电路单元和与出射绿色光线的第二绿色发光器件连接的第四电路单元；所述多个单元列包括第一单元列和第二单元列，所述第一单元列中的第一电路单元和第二电路单元沿着所述第二方向交替设置，所述第二单元列中的第三电路单元和第四电路单元沿着所述第二方向交替设置；至少部分所述第二初始信号线设置在所述第一单元列中。
在示例性实施方式中，所述发光器件包括阳极和像素定义层；所述阳极包括所述红色发光器件的第一阳极、所述蓝色发光器件的第二阳极、所述第一绿色发光器件的第三阳极和所述第二绿色发光器件的第四阳极；所述像素定义层上设置有暴露出所述第一阳极的第一像素开口、暴露出所述第二阳极的第二像素开口、暴露出所述第三阳极的第三像素开口和暴露出所述第四阳极的第四像素开口；所述第一像素开口在基底上正投影的第一中心线与所述第二初始信号线在基底上正投影的第二中心线至少部分重叠。
在示例性实施方式中，所述驱动电路层还包括数据信号线，所述第二像素开口在基底上正投影的第三中心线与所述数据信号线在基底上正投影的第 四中心线至少部分重叠。
在示例性实施方式中，所述发光器件包括阳极和像素定义层；所述阳极包括所述红色发光器件的第一阳极、所述蓝色发光器件的第二阳极、所述第一绿色发光器件的第三阳极和所述第二绿色发光器件的第四阳极；所述像素定义层上设置有暴露出所述第一阳极的第一像素开口、暴露出所述第二阳极的第二像素开口、暴露出所述第三阳极的第三像素开口和暴露出所述第四阳极的第四像素开口；所述驱动电路层还包括数据信号线；所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线位于所述第一像素开口在基底上正投影的第一中心线的两侧。
在示例性实施方式中，所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线相对于所述第一像素开口在基底上正投影的第一中心线对称设置。
在示例性实施方式中，所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线位于所述第二像素开口在基底上正投影的第三中心线的两侧。
在示例性实施方式中，所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线相对于所述第二像素开口在基底上正投影的第三中心线对称设置。
在示例性实施方式中，所述多个电路单元包括与出射红色光线的红色发光器件连接的第一电路单元、与出射蓝色光线的蓝色发光器件连接的第二电路单元、与出射绿色光线的第一绿色发光器件连接的第三电路单元和与出射绿色光线的第二绿色发光器件连接的第四电路单元；所述多个单元列包括第一单元列和第二单元列，所述第一单元列中的第一电路单元和第二电路单元沿着所述第二方向交替设置，所述第二单元列中的第三电路单元和第四电路单元沿着所述第二方向交替设置；至少部分所述第二初始信号线设置在所述第二单元列中。。
在示例性实施方式中，所述发光器件包括阳极和像素定义层；所述阳极包括所述红色发光器件的第一阳极、所述蓝色发光器件的第二阳极、所述第 一绿色发光器件的第三阳极和所述第二绿色发光器件的第四阳极；所述像素定义层上设置有暴露出所述第一阳极的第一像素开口、暴露出所述第二阳极的第二像素开口、暴露出所述第三阳极的第三像素开口和暴露出所述第四阳极的第四像素开口；所述第三像素开口在基底上正投影的第五中心线与所述第二初始信号线的连接部在基底上正投影的第七中心线至少部分重叠。
在示例性实施方式中，所述第四像素开口在基底上正投影的第六中心线与所述第二初始信号线的连接部在基底上正投影的第七中心线至少部分重叠。
在示例性实施方式中，所述多个电路单元包括与出射红色光线的红色发光器件连接的第一电路单元、与出射蓝色光线的蓝色发光器件连接的第二电路单元、与出射绿色光线的第一绿色发光器件连接的第三电路单元和与出射绿色光线的第二绿色发光器件连接的第四电路单元；所述多个单元列包括第一单元列和第二单元列，所述第一单元列中的第一电路单元和第二电路单元沿着所述第二方向交替设置，所述第二单元列中的第三电路单元和第四电路单元沿着所述第二方向交替设置；所述第二初始信号线设置在所述第一单元列和所述第二单元列中。
在示例性实施方式中，在垂直于显示基板的平面内，所述驱动电路层包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述半导体层包括所述像素驱动电路中多个晶体管的有源层，所述第一导电层包括扫描信号线和多个晶体管的栅电极，所述第二导电层包括所述第一初始信号线，所述第三导电层包括第一电源线，所述第四导电层包括数据信号线和所述第二初始信号线。
在示例性实施方式中，所述第三导电层还包括第二连接电极，所述第二连接电极通过过孔与所述第一初始信号线连接，所述第二初始信号线通过过孔与所述第二连接电极连接。
在示例性实施方式中，所述第二导电层还包括屏蔽电极，所述第一电源线通过过孔与所述屏蔽电极连接。
在示例性实施方式中，所述屏蔽电极的至少部分区域在所述基底上的正 投影位于所述数据信号线在所述基底上的正投影与所述像素驱动电路中第一晶体管的第二极在所述基底上的正投影之间。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法。所述显示基板包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括多个电路单元，所述发光结构层包括多个发光器件；至少一个电路单元包括第一电源线、初始信号线和像素驱动电路，所述初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，所述第一方向与第二方向交叉；所述制备方法包括：
在基底上形成沿所述第一方向延伸的第一初始信号线；
形成沿所述第二方向延伸的第二初始信号线，所述第二初始信号线在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2a和图2b为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6a为本公开示例性实施例一种显示基板的结构示意图；
图6b为本公开示例性实施例一种显示基板中初始信号线的示意图；
图7为本公开显示基板形成半导体层图案后的示意图；
图8a为本公开显示基板形成第一导电层图案后的示意图；
图8b为图8a中第一导电层的平面示意图；
图9a为本公开显示基板形成第二导电层图案后的示意图；
图9b为图9a中第二导电层的平面示意图；
图10a为本公开显示基板形成第四绝缘层图案后的示意图；
图10b为图10a中多个过孔的平面示意图；
图11a为本公开显示基板形成第三导电层图案后的示意图；
图11b为图11a中第三导电层的平面示意图；
图12a为本公开显示基板形成第一平坦层图案后的示意图；
图12b为图12a中多个过孔的平面示意图；
图13a为本公开显示基板形成一种第四导电层图案后的示意图；图13b为图13a中第四导电层的平面示意图；
图14a为本公开显示基板形成第二平坦层图案后的示意图；
图14b为图14a中多个过孔的平面示意图；
图15a为本公开显示基板形成阳极图案后的示意图；
图15b为图15a中阳极的平面示意图；
图16a为本公开显示基板形成像素定义层图案后的示意图；
图16b为图16a中像素定义层的平面示意图；
图17a为本公开示例性实施例另一种驱动电路层的结构示意图；
图17b为图17a中第四导电层的平面示意图；
图18a为本公开示例性实施例又一种驱动电路层的结构示意图；
图18b为图18a中第四导电层的平面示意图；
图19a为本公开示例性实施例又一种驱动电路层的结构示意图；
图19b为图19a中第四导电层的平面示意图；
图20a为本公开示例性实施例又一种驱动电路层的结构示意图；
图20b为图20a中第四导电层的平面示意图；
图21a为本公开示例性实施例另一种形成阳极图案后的示意图；
图21b为图21a中阳极的平面示意图；
图22a为本公开示例性实施例另一种形成像素定义层图案后的示意图；
图22b为图22a中像素定义层的平面示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；        13—第三有源层；
14—第四有源层；       15—第五有源层；        16—第六有源层；
17—第七有源层；       21—第一扫描信号线；    22—第二扫描信号线；
23—发光控制线；       24—第一极板；          31—第一初始信号线；
32—第二极板；         33—屏蔽电极；          34—开口；
35—极板连接线；       41—第一电源线；        42—数据连接电极；
43—第一连接电极；     44—第二连接电极；      45—第三连接电极；
51—数据信号线；       52—第二初始信号线；    53—阳极连接电极；
71—阳极；             72—像素定义层；        73—像素开口；
101—基底；            102—驱动电路层；       103—发光结构层；
104—封装层；          301—阳极；             302—像素定义层；
303—有机发光层；      304—阴极；             401—第一封装层；
402—第二封装层；      403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和 Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2a和图2b为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和二个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括扫描信号线、数据信号线和发光信号线和像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一 种示例性实施方式中，四个子像素可以采用正方形(Square)方式排列，形成GGRB像素排布，如图2a所示。在另一种示例性实施方式中，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布，如图2b所示。在其它示例性实施方式中，四个子像素可以采用水平并列或竖直并列等方式排列。在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括多个信号线和像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，图3中仅以一个驱动晶体管210和一个存储电容211为例进行示意。每个子像素的发光结构层103可以包括构成发光器件的多个膜层，多个膜层可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简 称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。图4为一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的 第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二 电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和7个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、初始信号线INIT、第一电源线VDD和第二电源线VSS)，7个晶体管均为P型晶体管。
在示例性实施方式中，以OLED为例，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为 Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图6a为本公开示例性实施例一种驱动电路层的结构示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。如图6a所示，在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，沿着第一方向X依次排布的多个电路单元称为单元行，沿着第二方向Y依次排布的多个电路单元称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
在示例性实施方式中，至少一个电路单元可以包括第一电源线、初始信号线以及与第一电源线和初始信号线连接的像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容。在示例性实施方式中，第一电源线可以被配置为接收电源信号的信号线，初始信号线可以被配置为对存储电容进行初始化(复位)。
在示例性实施方式中，至少一个电路单元的初始信号线可以包括主体部分沿第一方向X延伸的第一初始信号线31和主体部分沿第二方向Y延伸的第二初始信号线52，且第一初始信号线31和第二初始信号线52通过过孔连接。本公开中，A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其它方向伸展的长度。
在示例性实施方式中，在至少一个电路单元中，第二初始信号线52可以包括相互连接的延伸部521和连接部522，延伸部521的主体部分沿第二方向Y延伸，连接部522的主体部分沿第一方向X延伸。在示例性实施方式中，连接部522远离延伸部521一侧的端部可以通过过孔与第一初始信号线31连接。
在示例性实施方式中，至少部分连接部522在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内。
在示例性实施方式中，至少部分延伸部521在基底上的正投影位于第一电源线41在基底上的正投影的范围之内。
图6b为本公开示例性实施例一种驱动电路层中初始信号线的示意图。如图6b所示，驱动电路层可以包括多个单元行和多个单元列，第一初始信号线31可以设置在每个单元行中，第二初始信号线52可以设置在间隔的单元列中，即在第一方向X相邻的两条第二初始信号线52之间，间隔有至少一个单元列。在示例性实施方式中，单元行的方向可以是第一方向X，单元列的方向可以是第二方向Y。
在示例性实施方式中，显示基板中的多个子像素可以包括出射红色光线的红色子像素R、出射蓝色光线的蓝色子像素B、出射绿色光线的第一绿色子像素G1和出射绿色光线的第二绿色子像素G2。红色子像素R可以包括出射红色光线的红色发光器件和与红色发光器件连接的第一电路单元Q1，蓝色子像素B可以包括出射蓝色光线的蓝色发光器件和与蓝色发光器件连接的第二电路单元Q2，第一绿色子像素G1可以包括出射绿色光线的第一绿色发光器件和与第一绿色发光器件连接的第三电路单元Q3，第二绿色子像素G2可以包括出射绿色光线的第二绿色发光器件和与第二绿色发光器件连接的第四电路单元Q4，第一电路单元Q1、第二电路单元Q2、第三电路单元Q3和第四电路单元Q4构成一个电路单元组，至少一个电路单元组中的四个电路单元可以采用正方形(Square)方式排列，即四个电路单元排布在两个单元行和两个单元列中。本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素驱动电路划分的区域。在示例性实施方式中，子像素与电路单元两者的位置可以是对应的，或者，子像素与电路单元两者的位置可以是不对应的。
在示例性实施方式中，多个单元列可以包括第一单元列和第二单元列，第一单元列是指多个第一电路单元Q1和第二电路单元Q2形成的列，第二单元列是指多个第三电路单元Q3和第四电路单元Q4形成的列。第一单元列中的第一电路单元Q1和第二电路单元Q2沿着第二方向Y交替设置，第二单 元列中的第三电路单元Q3和第四电路单元Q4沿着第二方向Y交替设置。
在一种示例性实施方式中，第二初始信号线52可以设置在第一单元列中。例如，第N单元列和第N+2单元列为第一单元列，第N+1单元列和第N+3单元列可以为第二单元列，则第二初始信号线52可以设置在第N单元列、第N+2单元列、第N+4单元列、……，第二初始信号线52每隔一第二单元列一重复。
在另一种示例性实施方式中，第二初始信号线52可以设置在第二单元列中。例如，第N单元列和第N+2单元列为第一单元列，第N+1单元列和第N+3单元列可以为第二单元列，则第二初始信号线52可以设置在第N+1单元列、第N+3单元列、第N+5单元列、……，第二初始信号线52每隔一第一单元列一重复。
在又一种示例性实施方式中，第二初始信号线52可以设置在第一单元列和第二单元列中。
在示例性实施方式中，第N单元列和第N+2单元列可以为第一单元列，第N+1单元列和第N+3单元列可以为第二单元列。第N单元列中，第M行的电路单元为第一电路单元，第M+1行的电路单元为第二电路单元，因而第N单元列中的第一电路单元和第二电路单元沿着第二方向Y交替设置。第N+2单元列中，第M行的电路单元为第二电路单元，第M+1行的电路单元为第一电路单元，因而第N+2单元列中的第二电路单元和第一电路单元沿着第二方向Y交替设置。
在示例性实施方式中，由于第M行第N列电路单元和第M+1行第N+2列电路单元均为第一电路单元，因而第M行第N列电路单元中的第二初始信号线的形状与第M+1行第N+2列电路单元中的第二初始信号线的形状可以相同。由于第M+1行第N列电路单元和第M行第N+2列电路单元均为第二电路单元，因而第M+1行第N列电路单元中的第二初始信号线的形状与第M行第N+2列电路单元中的第二初始信号线的形状可以相同。
在示例性实施方式中，第M行第N列电路单元和第M+1行第N+2列电路单元中，延伸部521可以包括依次连接的第一初始部、第二初始部和第三初始部，第一初始部和第三初始部可以与第二方向Y平行，第二初始部可以 与第二方向Y具有第一夹角，第一夹角可以大于0°，小于90°。在示例性实施方式中，第一初始部和/或第三初始部的端部可以连接连接部522。
在示例性实施方式中，第M行第N+2列电路单元和第M+1行第N列电路单元中，延伸部521可以包括依次连接的第四初始部、第五初始部、第六初始部、第七初始部和第八初始部，第四初始部、第六初始部和第八初始部可以与第二方向Y平行，第五初始部可以与第二方向Y具有第一夹角，第七初始部可以与第二方向Y具有第二夹角，第一夹角可以大于0°，小于90°，第二夹角可以大于0°，小于90°。在示例性实施方式中，第五初始部的延伸方向与第七初始部的延伸方向可以相对于第一方向X镜像对称。
在一些可能的示例性实施方式中，第二初始信号线52可以设置在间隔的第一单元列或第二单元列中，即在第一方向X相邻的两条第二初始信号线52之间，间隔有三个单元列。例如，第二初始信号线52可以设置在第N单元列、第N+4单元列、第N+8单元列、……，第二初始信号线52每隔一个第一单元列和二个第二单元列一重复。或者，第二初始信号线52可以设置在第N+1单元列、第N+5单元列、第N+9单元列、……，第二初始信号线52每隔二个第一单元列和一个第二单元列一重复。在示例性实施方式中，相邻的第二初始信号线52之间间隔的单元列数没有特殊要求，可以根据需要来设置，本公开在此不做限定。
在示例性实施方式中，在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；半导体层可以包括多个晶体管的有源层，第一导电层可以包括扫描信号线和多个晶体管的栅电极，第二导电层可以包括所述第一初始信号线31，第三导电层可以包括第一电源线和多个晶体管的第一极和第二极，第四导电层可以包括数据信号线和第二初始信号线52。
在示例性实施方式中，第三导电层还可以包括第二连接电极44。位于第三导电层的第二连接电极44可以通过过孔与位于第二导电层的第一初始信号线31连接，位于第四导电层的第二初始信号线52可以通过过孔与位于第三导电层的第二连接电极44连接。本公开中，第二连接电极可以称为初始连接电极。
在示例性实施方式中，第二连接电极44可以通过过孔与像素驱动电路中第一晶体管的有源层第一区和第七晶体管的有源层第一区连接。
在示例性实施方式中，第二导电层还可以包括屏蔽电极，第一电源线通过过孔与屏蔽电极连接。屏蔽电极的至少部分区域在基底上的正投影位于数据信号线在基底上的正投影与像素驱动电路中第一晶体管的第二极在基底上的正投影之间。
在示例性实施方式中，驱动电路层还可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容，存储电容可以包括第一极板和第二极板，多个晶体管可以包括第一晶体管至第七晶体管，第三晶体管为驱动晶体管。
在示例性实施方式中，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23、存储电容的第一极板和多个晶体管的栅电极，第二导电层可以包括第一初始信号线31、存储电容的第二极板、屏蔽电极和极板连接线，第三导电层可以包括第一电源线41、数据连接电极、第一连接电极、第二连接电极44、第三连接电极和第四连接电极，第四导电层可以包括数据信号线51、第二初始信号线52和阳极连接电极。
在示例性实施方式中，驱动电路层可以包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在 整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以八个电路单元(2个单元行4个单元列)为例，驱动电路层的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图7所示。
在示例性实施例中，每个电路单元的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构，每个单元列中第M行电路单元的第六有源层16与第M+1行电路单元的第七有源层17相互连接，即每个单元列中相邻电路单元的半导体层为相互连接的一体结构。
在示例性实施例中，第M行电路单元中的第一有源层11、第二有源层12、第四有源层14和第七有源层17位于本电路单元的第三有源层13远离第M+1行电路单元的一侧，第一有源层11和第七有源层17位于第二有源层12和第四有源层14远离第三有源层13的一侧，第M行电路单元中的第五有源层15和第六有源层16位于第三有源层13靠近第M+1行电路单元的一侧。
在示例性实施例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第 一区11-1同时作为第七有源层17的第一区17-1，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2。在示例性实施例中，第四有源层14的第一区14-1和第五有源层15的第一区15-1单独设置。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和第一极板24，如图8a和图8b所示，图8b为图8a中第一导电层的平面示意图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
结合图7至图8b所示，第一扫描信号线21、第二扫描信号线22和发光控制线23可以主体部分沿第一方向X延伸。第M行电路单元中的第一扫描信号线21和第二扫描信号线22位于本电路单元的第一极板24远离第M+1行电路单元的一侧，第二扫描信号线22位于本电路单元的第一扫描信号线21远离第一极板24的一侧，发光控制线23可以位于本电路单元的第一极板24靠近第M+1行电路单元的一侧。
在示例性实施例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施例中，第一扫描信号线21与第二有源层12相重叠的区域作为第二晶体管T2的栅电极，第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二有源层12在基底上的正投影存在重叠区域，形成双栅结构的第二晶体管T2。第一扫描信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极。第 二扫描信号线22与第一有源层11相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，发光控制线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六有源层16相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：第一初始信号线31、第二极板32、屏蔽电极33和极板连接线35，如图9a和图9b所述，图9b为图9a中第二导电层的平面示意图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
结合图7至图9b所示，第一初始信号线31可以主体部分沿第一方向X延伸，第M行电路单元中的第一初始信号线31位于本电路单元的第二扫描信号线22远离第M+1行电路单元的一侧，第二极板32作为存储电容的另一个极板，位于本电路单元的第一扫描信号线21和发光控制线23之间，屏蔽电极33位于本电路单元的第二扫描信号线22与第一扫描信号线21(不包含栅极块21-1的主体部分)之间，屏蔽电极33配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域，第一极板24和第二极板32构成像素驱动电路的存储电容。第二极板32上设置有开口34，开口34可以位于第二极板32的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极板 24的第三绝缘层，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第一方向X上或第一方向X的反方向上相邻电路单元的第二极板32之间，极板连接线35的第一端与本电路单元的第二极板32连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸，并与相邻电路单元的第二极板32连接，即极板连接线35配置为使一单元行上相邻电路单元的第二极板相互连接。在示例性实施例中，通过极板连接线35可以使一单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如图10a和图10b所示，图10b为图10a中多个过孔的平面示意图。
结合图7至图10b所示，第一过孔V1位于第二极板32的开口34内，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在示例性实施例中，第二过孔V2位于第二极板32在基底上的正投影的范围之内，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极 板32连接。在示例性实施例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，以增加第一电源线与第二极板32的连接可靠性。
在示例性实施例中，第三过孔V3在基底上的正投影位于第五有源层在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在示例性实施例中，第四过孔V4在基底上的正投影位于第六有源层在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在示例性实施例中，第五过孔V5在基底上的正投影位于第四有源层在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据信号线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在示例性实施例中，第六过孔V6在基底上的正投影位于第二有源层在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区(也是第一有源层的第二区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在示例性实施例中，第七过孔V7在基底上的正投影位于第七有源层在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接，以及使后续形成的第一晶体管T1的第一极通过 该过孔与第一有源层连接。
在示例性实施例中，第八过孔V8在基底上的正投影位于屏蔽电极33在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。
在示例性实施例中，第九过孔V9在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面。第九过孔V9配置为使后续形成的第七晶体管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与第一初始信号线31连接。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据连接电极42、第一连接电极43、第二连接电极44和第三连接电极45，如图11a和图11b所示，图11b为图11a中第三导电层的平面示意图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
结合图7至图11b所示，第一电源线41主体部分沿着第二方向Y延伸，第一电源线41一方面通过第二过孔V2与第二极板32连接，另一方面通过第三过孔V3与第五有源层连接，又一方面通过第八过孔V8与屏蔽电极33连接，使屏蔽电极33和第二极板32具有与第一电源线41相同的电位。由于屏蔽电极33与第一电源线41连接，且屏蔽电极33的至少部分区域(如屏蔽电极33右侧的突出部)在基底上的正投影位于第一连接电极43(作为第一晶体管T1的第二极和第二晶体管T2的第一极，即第二节点N2)在基底上的正投影与后续形成的数据信号线在基底上的正投影之间，可以有效屏蔽了数据电压跳变对像素驱动电路中关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，屏蔽电极33的至少部分区域在基底上的正投影可以与后续形成的数据信号线在基底上的正投影至少部分重叠。在示例性实施例 中，第一方向X上相邻电路单元中的屏蔽电极33可以相互连接，以降低电阻。
在示例性实施例中，数据连接电极42通过第五过孔V5与第四有源层的第一区连接，数据连接电极42配置为与后续形成的数据信号线连接。
在示例性实施例中，第一连接电极43沿着第二方向Y延伸，其第一端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极43可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施例中，第二连接电极44的第一端通过第九过孔V9与第一初始信号线31连接，其第二端通过第七过孔V7与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与第一初始信号线31相同的电位。在示例性实施例中，第二连接电极44可以作为第七晶体管T7的第一极和第一晶体管T1的第一极，第二连接电极配置为连接后续形成的第二初始信号线。本公开通过设置第二连接电极同时连接第七有源层、第一初始信号线和第二初始信号线，可以减小过孔的数量和转接电极的数量，节约布线空间。
在示例性实施例中，第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极45可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第三连接电极45配置为与后续形成的阳极连接电极连接。
在示例性实施例中，至少一个电路单元的第一电源线41可以为非等宽度的折线。沿着第二方向Y，每个电路单元的第一电源线41可以包括依次连接的第一电源部d1、第二电源部d2、第三电源部d3、第四电源部d4和第五电源部d5，第一电源部d1、第三电源部d3和第五电源部d5可以与第二方向Y平行，第二电源部d2可以向着第一方向X弯折，第四电源部d4可以向着第一方向X的反方向弯折。第二电源部d2与第一电源部d1之间的夹角可以大 于0°且小于90°，第四电源部d4与第三电源部d3之间的夹角可以大于0°且小于90°。第五电源部d5设置有向着第一方向X的反方向延伸的连接部d6，连接部d6配置为通过通过第三过孔与第五有源层连接。第一电源线41采用折线设置，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施例中，各个电路单元的第一电源线的形状可以相同，或者可以不同。在示例性实施例中，第M行第N列电路单元中的第一电源线的形状与第M+1行第N+2列电路单元中的第一电源线的形状可以相同，第M+1行第N列电路单元中的第一电源线的形状与第M行第N+2列电路单元中的第一电源线的形状可以相同，第M行第N+1列电路单元中的第一电源线的形状与第M+1行第N+3列电路单元中的第一电源线的形状可以相同，第M+1行第N+1列电路单元中的第一电源线的形状与第M行第N+3列电路单元中的第一电源线的形状可以相同。
在示例性实施例中，第N列各个电路单元中的第二连接电极的形状与第N+2列各个电路单元中的第二连接电极的形状可以相同，第N+1列各个电路单元中的第二连接电极的形状与第N+3列各个电路单元中的第二连接电极的形状可以相同。第N+1列和第N+3列电路单元中的第二连接电极的形状可以为沿着第二方向Y延伸的条形状，第二连接电极配置为通过第九过孔和第七过孔分别与第一初始信号线和第七有源层的第一区连接。第N列和第N+2列电路单元中的第二连接电极44的形状可以包括相互连接的第一部44-1和第二部44-2，第一部44-1为沿着第二方向Y延伸的条形状，第二部44-2可以为矩形状，第二部44-2设置在第一部44-1第一方向X的反方向的一侧，第一部44-1配置为通过第九过孔和第七过孔分别与第一初始信号线和第七有源层的第一区连接，第二部44-2配置为通过后续形成的过孔与后续形成的第二初始信号线连接，从而实现第一初始信号线与第二初始信号线的连接。
在示例性实施例中，各个电路单元的第三连接电极的形状可以相同，或者可以不同。在示例性实施例中，第M行第N列电路单元中的第三连接电极的形状与第M+1行第N+2列电路单元中的第三连接电极的形状可以相同， 第M+1行第N列电路单元中的第三连接电极的形状与第M行第N+2列电路单元中的第三连接电极的形状可以相同，第M行第N+1列电路单元中的第三连接电极的形状与第M+1行第N+3列电路单元中的第三连接电极的形状可以相同，第M+1行第N+1列电路单元中的第三连接电极的形状与第M行第N+3列电路单元中的第三连接电极的形状可以相同。
在示例性实施例中，各个电路单元的数据连接电极和第一连接电极的形状可以相同，或者可以不同。
(6)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦层上设置有第十一过孔V11、第十二过孔V12和第十三过孔V13，如图12a和图12b所示，图12b为图12a中多个过孔的平面示意图。
结合图7至图12b所示，第十一过孔V11在基底上的正投影位于数据连接电极42在基底上的正投影的范围之内，第十一过孔V11内的第一平坦层被去掉，暴露出数据连接电极42的表面，第十一过孔V11配置为使后续形成的数据信号线通过该过孔与数据连接电极42连接。
在示例性实施例中，第十一过孔V11可以是条形状，第十一过孔V11中第二方向Y的延伸长度大于第一方向X的延伸长度。本公开通过将第十一过孔V11设置沿着第二方向Y延伸的条形状，可以减小第十一过孔V11第一方向X上的宽度，可以减少后续形成的阳极的倾斜程度。
第十二过孔V12在基底上的正投影位于第二连接电极44在基底上的正投影的范围之内，第十二过孔V12内的第一平坦层被去掉，暴露出第二连接电极44的表面，第十二过孔V12配置为使后续形成的第二初始信号线通过该过孔与第二连接电极44连接。
第十三过孔V13在基底上的正投影位于第三连接电极45在基底上的正投影的范围之内，第十三过孔V13内的第一平坦层被去掉，暴露出第三连接电极45的表面，第十三过孔V13配置为使后续形成的阳极连接电极通过该过孔与第三连接电极45连接。
在示例性实施例中，所有电路单元均设置有第十一过孔V11和第十三过 孔V13，第N列和第N+2列中的各个电路单元中设置有第十二过孔V12，第N+1列和第N+3列中的各个电路单元中没有设置第十二过孔V12。
在示例性实施例中，各个电路单元中的第十一过孔V11和第十三过孔V13的位置可以相同，或者可以不同。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，第四导电层至少包括：数据信号线51、第二初始信号线52和阳极连接电极53，如图13a和图13b所示，图13b为图13a中第四导电层的平面示意图。
结合图7至图13b所示，数据信号线51设置在每个单元列中。数据信号线51可以沿着第二方向Y延伸，数据信号线51通过第十一过孔V11与数据连接电极42连接。由于数据连接电极42通过第五过孔V5与第四有源层的第一区连接，因而实现了数据信号线51通过数据连接电极42与第四有源层的第一区连接，将数据信号写入第四晶体管T4。
在示例性实施例中，第二初始信号线52设置在第N单元列和第N+2单元列中，单元列中每个电路单元的第二初始信号线52相互连接。第二初始信号线52主体部分沿着第二方向Y延伸，第二初始信号线52通过第十二过孔V12与第二连接电极44连接。由于第二连接电极44通过第九过孔V9与第一初始信号线31连接，因而实现了第二初始信号线52通过第二连接电极44与第一初始信号线31连接，使得第一初始信号线31和第二初始信号线52具有相同的电位。本公开通过设置主体部分沿第一方向X延伸的第一初始信号线31和沿着第二方向Y延伸的第二初始信号线52，使得初始信号线形成网状结构，不仅有效降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施例中，阳极连接电极53设置在至少部分电路单元中。阳极连接电极53通过第十三过孔V13与第三连接电极45连接。由于第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了阳极连接电极53通过第三连接电极45与第六有源层的第 二区(也是第七有源层的第二区)连接。
在示例性实施例中，一个电路单元中的第二初始信号线52可以包括延伸部521和连接部522。延伸部521可以为主体部分沿着第二方向Y延伸的折线，连接部522可以为主体部分沿着第一方向X延伸的直线。在示例性实施例中，连接部522远离延伸部521一侧的端部可以通过第十二过孔V12与第二连接电极44连接。
在示例性实施例中，至少部分延伸部521在基底上的正投影位于第一电源线41在基底上的正投影的范围之内，不仅可以使得第一电源线41有效屏蔽第二初始信号线52对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在示例性实施例中，至少部分连接部522在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在示例性实施例中，第M行第N列电路单元中的第二初始信号线52的形状与第M+1行第N+2列电路单元中的第二初始信号线52的形状可以相同，第M+1行第N列电路单元中的第二初始信号线52的形状与第M行第N+2列电路单元中的第二初始信号线52的形状可以相同。
在示例性实施例中，在第M行第N列电路单元和第M+1行第N+2列电路单元中，延伸部521可以包括沿着第二方向Y依次连接的第一初始部c1、第二初始部c2和第三初始部c3，第一初始部c1和第三初始部c3可以与第二方向Y平行，第二初始部c2可以向着第一方向X的反方向偏转，第二初始部c2与第二方向Y具有第一夹角θ1，第一夹角θ1可以大于0°，小于90°。
在示例性实施例中，在第M行第N+2列电路单元和第M+1行第N列电路单元中，延伸部521可以包括沿着第二方向Y依次连接的第四初始部c4、第五初始部c5、第六初始部c6、第七初始部c7和第八初始部c8，第四初始部c4、第六初始部c6和第八初始部c8可以与第二方向Y平行，第五初始部c5可以与第二方向Y具有第一夹角θ1，第七初始部c7可以与第二方向Y具有第二夹角θ2，第一夹角θ1可以大于0°，小于90°，第二夹角θ2可以大 于0°，小于90°。
在示例性实施例中，第五初始部c5的延伸方向与第七初始部c7的延伸方向可以相对于第一方向X镜像对称。
在示例性实施例中，至少部分电路单元设置有数据信号线51和阳极连接电极53，第N列和第N+2列中的各个电路单元中设置有第二初始信号线52，第N+1列和第N+3列中的各个电路单元中没有设置第二初始信号线52。
在示例性实施例中，第M行第N列电路单元中的阳极连接电极的形状与第M+1行第N+2列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为矩形状。第M+1行第N列电路单元中的阳极连接电极的形状与第M行第N+2列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为哑铃形状。第M行第N+1列电路单元中的阳极连接电极的形状与第M+1行第N+3列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为矩形状。第M+1行第N+1列电路单元中的阳极连接电极的形状与第M行第N+3列电路单元中的阳极连接电极的形状可以相同，阳极连接电极的形状可以为矩形状。
(8)形成第二平坦层图案。在示例性实施例中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有第十四过孔V14，如图14a和图14b所示，图14b为图14a中多个过孔的平面示意图。
结合图7至图14b所示，第十四过孔V14在基底上的正投影位于阳极连接电极53在基底上的正投影的范围之内，第十四过孔V14内的第二平坦层被去掉，暴露出阳极连接电极53的表面，第十四过孔V14配置为使后续形成的阳极通过该过孔与阳极连接电极53连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次叠设的第一绝缘层、半 导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施例中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(9)形成阳极图案。在示例性实施例中，形成阳极图案可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第二平坦层上的阳极图案，阳极形成GGRB像素排布，如图15a和图15b所示，图15b为图15a中阳极的平面示意图。
结合图7至图15b所示，阳极图案可以包括红色发光器件的第一阳极71A、蓝色发光器件的第二阳极71B、第一绿色发光器件的第三阳极71C和第二绿色发光器件的第四阳极71D，第一阳极71A所在区域可以形成出射红色光线的红色子像素R，第二阳极71B所在区域可以形成出射蓝色光线的蓝色子像素B，第三阳极71C所在区域可以形成出射绿色光线的第一绿色子像素G1，第四阳极71D所在区域可以形成出射绿色光线的第二绿色子像素G2，红色子像素R和蓝色子像素B沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2分别设置在红色子像素R和蓝色子像素B第一方向X的一侧，红色子像素R、蓝色子像素B、第一绿色子像素G1和第二绿色子像素G2组成一个像素单元。
在示例性实施例中，一个像素单元中，第一阳极71A通过第M行第N列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第二阳极71B通过第M+1行第N列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第三阳极71C通过第M行第N+1列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第四阳极71D通过第M+1行第N+1列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接。另一个像素单元中，第一阳极71A通过第M+1行第N+2列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第二阳极71B通过第M行第N+2列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第三阳极71C通过第M+1行第N+3 列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第四阳极71D通过第M行第N+3列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接。
在示例性实施例中，由于至少一个电路单元中的阳极连接电极53通过第十三过孔V13与第三连接电极45连接，而第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，第三连接电极45作为第六晶体管T6的第二极和第七晶体管T7的第二极，因而阳极可以通过阳极连接电极53和第三连接电极45与第六晶体管T6和第七晶体管T7的连接，至少一个像素单元中的四个阳极分别与一个电路单元组中的四个电路单元的像素驱动电路对应连接，实现了像素驱动电路可以驱动发光器件发光。
在示例性实施例中，一个像素单元的四个子像素与一个电路单元组中的四个电路单元的位置关系可以相同，或者可以不同。本公开示例性实施例中，第一阳极71A的主体部分位于对应连接的电路单元第一方向X的反方向的一侧，第一阳极71A在基底上的正投影可以与第二初始信号线的延伸部在基底上的正投影至少部分重叠。第二阳极71B主体部分位于对应连接的电路单元第一方向X的一侧，第二阳极71B在基底上的正投影可以与数据信号线在基底上的正投影至少部分重叠。第三阳极71C主体部分位于对应连接的电路单元第二方向Y的一侧，第四阳极71D主体部分位于对应连接的电路单元的下一行电路单元中。
在一种可能的示例性实施例中，第一阳极71A的主体部分可以位于对应连接的电路单元第一方向X的一侧，第一阳极71A在基底上的正投影可以与数据信号线在基底上的正投影至少部分重叠。第二阳极71B主体部分可以位于对应连接的电路单元第一方向X的反方向的一侧，第二阳极71B在基底上的正投影可以与第二初始信号线的延伸部在基底上的正投影至少部分重叠。
在示例性实施例中，不同像素单元中的第一阳极71A的形状和位置可以相同，或者可以不同。不同像素单元中的第二阳极71B的形状和位置可以相同，或者可以不同。不同像素单元中的第三阳极71C的形状和位置可以相同，或者可以不同。不同像素单元中的第四阳极71D的形状和位置可以相同，或者可以不同。本公开示例性实施例中，分别与第M行第N列电路单元和第 M+1行第N+2列电路单元中像素驱动电路连接的两个第一阳极71A的形状和位置相同，分别与第M+1行第N列电路单元和第M行第N+2列电路单元中像素驱动电路连接的两个第二阳极71B的形状和位置相同，分别与第M行第N+1列电路单元和第M+1行第N+3列电路单元中像素驱动电路连接的两个第三阳极71C的形状和位置相同，分别与第M+1行第N+1列电路单元和第M行第N+3列电路单元中像素驱动电路连接的两个第四阳极71D的形状和位置相同。
在示例性实施例中，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同。本公开示例性实施例中，一个像素单元中第一阳极71A、第二阳极71B、第三阳极71C和第四阳极71D的形状和面积均不同。
在示例性实施例中，红色子像素中的第一阳极71A可以包括第一阳极主体部，第一阳极主体部的形状可以为类六边形。在示例性实施例中，第一阳极71A还可以包括第一凸起71-1和第二凸起71-2，第一凸起71-1和第二凸起71-2均与第一阳极主体部连接，第一凸起71-1可以是向着靠近所连接的像素驱动电路中第三晶体管T3的栅电极凸出的矩形，第二凸起71-2可以是向着靠近所连接的像素驱动电路中第六晶体管T6凸出的矩形，第一凸起71-1和第二凸起71-2配置为调整所连接的像素驱动电路中N3节点的寄生电容，减小相邻电路单元中N3节点寄生电容之间的差异，以减小亮度差异，提升显示效果。
在示例性实施例中，蓝色子像素中的第二阳极71B可以包括第二阳极主体部，第二阳极主体部的形状可以为类六边形。在示例性实施例中，第二阳极71B还可以包括第三凸起71-3、第四凸起71-4和第五凸起71-5，第三凸起71-3、第四凸起71-4和第五凸起71-5均与第二阳极主体部连接，第三凸起71-3可以是向着靠近所连接的像素驱动电路中第一电源线凸出的矩形，第四凸起71-4可以是向着远离所连接的像素驱动电路中第一电源线凸出的矩形，第五凸起71-5可以是向着靠近所连接的像素驱动电路中第六晶体管T6凸出的多边形，第三凸起71-3、第四凸起71-4和第五凸起71-5配置为调整所连接的像素驱动电路中N3节点的寄生电容，减小相邻电路单元中N3节点寄生电容之间的差异，以减小亮度差异，提升显示效果。
在示例性实施例中，第三阳极71C可以包括第三阳极主体部，第三阳极主体部的形状可以为类五边形。在示例性实施例中，第三阳极71C还可以包括第六凸起71-6，第六凸起71-6与第三阳极主体部连接，第六凸起71-6可以是向着靠近所连接的像素驱动电路中第六晶体管T6凸出的矩形，第六凸起71-6配置为调整本所连接的像素驱动电路中N3节点的寄生电容，减小相邻电路单元中N3节点寄生电容之间的差异，以减小亮度差异，特别是减小本子像素与第二绿色子像素的亮度差异，提升显示效果。
在示例性实施例中，第四阳极71D可以包括第四阳极主体部，第四阳极主体部的形状可以为类五边形。在示例性实施例中，第四阳极71D还可以包括第七凸起71-7，第七凸起71-7与第四阳极主体部连接，第七凸起71-7可以是向着靠近所连接的像素驱动电路中第三晶体管T3的栅电极凸出的条形，第七凸起71-7配置为调整所连接的像素驱动电路中N3节点的寄生电容，减小相邻电路单元中N3节点寄生电容之间的差异，以减小亮度差异，特别是减小本子像素与第一绿色子像素的亮度差异，提升显示效果。
(10)形成像素定义层图案。在示例性实施例中，形成像素定义层图案可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层72图案，如图16a和图16b所示，图16b为图16a中像素定义层的平面示意图。
结合图7至图16b所示，像素定义层72图案可以包括暴露出第一阳极71A的第一像素开口73A、暴露出第二阳极71B的第二像素开口73B、暴露出第三阳极71C的第三像素开口73C和暴露出第四阳极71D的第四像素开口73D。
在示例性实施例中，第一像素开口73A在基底上的正投影具有第一中心线Z1，第二初始信号线52的延伸部在基底上的正投影具有第二中心线，第一中心线Z1是沿着第二方向Y延伸且在第一方向X上平分第一像素开口73A在基底上正投影的线，第二中心线是沿着第二方向Y延伸且在第一方向X上平分第二初始信号线的延伸部在基底上正投影的线。在示例性实施例中，第二中心线是沿着第二方向Y延伸且在第一方向X上平分延伸部中的第一初始部c1在基底上的正投影的线。在示例性实施例中，第一中心线与第二中心 线至少部分重叠。本公开通过设置第一像素开口73A的第一中心线与第二初始信号线的延伸部的第二中心线至少部分重叠，可以使得第一像素开口73A中的第二初始信号线保持左右对称，保证了第一阳极的平坦性，可以避免大视角色偏。
在示例性实施例中，第二像素开口73B在基底上的正投影具有第三中心线Z3，数据信号线51在基底上的正投影具有第四中心线，第三中心线Z3是沿着第二方向Y延伸且在第一方向X上平分第二像素开口73B在基底上正投影的线，第四中心线是沿着第二方向Y延伸且在第一方向X上平分数据信号线在基底上正投影的线。在示例性实施例中，第三中心线与第四中心线至少部分重叠。本公开通过设置第二像素开口73B的第三中心线与数据信号线的第四中心线至少部分重叠，可以使得第二像素开口73B内的数据信号线保持左右对称，保证了第二阳极的平坦性，可以避免大视角色偏。
本公开所说的“平分A”可以是中心线使A在基底上正投影的两侧与中心线的距离基本上相等，两侧与中心线的距离基本上相等可以存在工艺或公差导致的允许范围内的偏差。例如，A在基底上正投影的两侧边缘距离中心线最小距离的比值可以约为0.8至1.2。本公开所说的“A与B重叠”并不要求A与B完全重叠，可以存在工艺或公差导致的允许范围内的偏差。
在示例性实施例中，可以采用其它方式保证阳极的平坦性。例如，可以采用增加第二平坦层厚度等方式。又如，可以使信号线加宽且与阳极形状基本一致。再如，可以将信号线分成左右两段，两段位于中心线两侧对称垫在阳极两侧下方。再如，可以使信号线位于中心线两侧分成两根线分别垫在阳极左右两侧等，本公开在此不做限定。
在示例性实施例中，后续制备流程可以包括：采用蒸镀或喷墨打印工艺形成有机发光层，有机发光层通过像素开口与阳极连接，在有机发光层上形成阴极，阴极与有机发光层连接。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚 性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。第一平坦层和第二平坦层可以采用有机材料，如树脂等。第五导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或多种，或采用上述金属中任意一种或多种制成的合金。
从以上描述的显示基板的结构以及制备过程可以看出，本公开提供的显示基板，通过设置主体部分沿第一方向延伸的第一初始信号线和主体部分沿第二方向延伸的第二初始信号线，第一初始信号线和第二初始信号线通过过 孔连接，使得初始信号线形成网状结构，不仅有效降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开通过将第一初始信号线和第二初始信号线设置在不同的导电层，且第二初始信号线的延伸部与第一电源线至少部分重叠，第二初始信号线的连接部与第一初始信号线至少部分重叠，不仅可以使得第一电源线有效屏蔽第二初始信号线对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率。本公开通过在第一单元列设置第二初始信号线，可以避免同一个像素单元中两个绿色子像素的亮度差异，提高显示质量。本公开通过设置第一像素开口的第一中心线与第二初始信号线的延伸部的第二中心线至少部分重叠，可以使得第一像素开口内的第二初始信号线保持左右对称，保证了第一阳极的平坦性，可以避免大视角色偏，提高显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图17a为本公开示例性实施例另一种驱动电路层的结构示意图，图17b为图17a中第四导电层的平面示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，本示例性实施例驱动电路层中半导体层、第一导电层、第二导电层、第三导电层以及第四导电层中的数据信号线51和阳极连接电极53的结构与前述实施例基本上相近，所不同的是，第四导电层中的第二初始信号线52设置在一单元列中部分电路单元中，一单元列中相邻两个第二初始信号线52可以是相互隔离的。
如图17a和图17b所示，在示例性实施例中，第二初始信号线52的主体部分分别设置在第M行第N列电路单元和第M+1行第N+2列电路单元中，第二初始信号线52不仅通过本电路单元的第十二过孔V12与本电路单元的第二连接电极44连接，而且通过下一行电路单元的第十二过孔V12与下一行电路单元的第二连接电极44连接。例如，对于第M行第N列电路单元，第二初始信号线52通过第M行第N列电路单元的第十二过孔V12与第M行第N列电路单元的第二连接电极44连接，通过第M+1行第N列电路单元 的第十二过孔V12与第M+1行第N列电路单元的第二连接电极44连接。对于第M+1行第N列电路单元，第二初始信号线52通过第M+1行第N列电路单元的第十二过孔V12与第M+1行第N列电路单元的第二连接电极44连接，通过第M+2行第N列电路单元的第十二过孔V12与第M+2行第N列电路单元的第二连接电极44连接。
在示例性实施例中，至少一个第二初始信号线52可以包括延伸部521、第一连接部523和第二连接部524。延伸部521可以为主体部分沿着第二方向Y延伸的折线，第一连接部523和第二连接部524可以为主体部分沿着第一方向X延伸的直线，第一连接部523可以设置在本电路单元，第二连接部524可以设置在下一行电路单元。在示例性实施例中，第一连接部523远离延伸部521一侧的端部可以通过本电路单元的第十二过孔V12与本电路单元的第二连接电极44连接，第二连接部524远离延伸部521一侧的端部通过下一行电路单元的第十二过孔V12与下一行电路单元的第二连接电极44连接。这样，一个第二初始信号线52可以与两个单元行的第一初始信号线连接，使得第一初始信号线和第二初始信号线形成网状结构。
在示例性实施例中，延伸部521在基底上的正投影至少部分位于第一电源线41在基底上的正投影的范围之内，第一连接部523和第二连接部524在基底上的正投影至少部分位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
本示例性实施例中，后续形成发光结构层的过程与前述实施例基本上相近。在形成阳极图案后，第一阳极在基底上的正投影可以与第二初始信号线的延伸部在基底上的正投影至少部分重叠，第一像素开口的第一中心线与第二初始信号线的延伸部的第二中心线至少部分重叠，因而可以保证第一阳极的平坦性，可以避免大视角色偏。
图18a为本公开示例性实施例又一种驱动电路层的结构示意图，图18b为图18a中第四导电层的平面示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，本示例性实施例驱动电路层中半导体层、第一导电层、第二导电层、第三导电层以及第四导电层中的数 据信号线51和阳极连接电极53的结构与前述实施例基本上相近，所不同的是，第四导电层中的第二初始信号线52设置在一单元列中部分电路单元中，一单元列中相邻两个第二初始信号线52可以是相互隔离的。
如图18a和图18b所示，在示例性实施例中，第二初始信号线52的主体部分分别设置在第M+1行第N列电路单元和第M行第N+2列电路单元中，第二初始信号线52不仅通过本电路单元的第十二过孔V12与本电路单元的第二连接电极44连接，而且通过下一行电路单元的第十二过孔V12与下一行电路单元的第二连接电极44连接。
在示例性实施例中，至少一个第二初始信号线52的主体结构可以包括延伸部521、第一连接部523和第二连接部524，延伸部521、第一连接部523和第二连接部524可以与图17b所述的结构相近，一个第二初始信号线52可以与两个单元行的第一初始信号线连接，使得第一初始信号线和第二初始信号线形成网状结构。延伸部521在基底上的正投影至少部分位于第一电源线41在基底上的正投影的范围之内，第一连接部523和第二连接部524在基底上的正投影至少部分位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
本示例性实施例中，后续形成发光结构层的过程与前述实施例基本上相近。在形成阳极图案后，第一阳极和第二阳极在基底上的正投影可以均与第二初始信号线在基底上的正投影没有重叠区域，第二初始信号线的延伸部未穿过任何像素开口，可以进一步保证第一阳极和第二阳极的平坦性，可以避免大视角色偏。
图19a为本公开示例性实施例又一种驱动电路层的结构示意图，图19b为图19a中第四导电层的平面示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，本示例性实施例驱动电路层中半导体层、第一导电层、第二导电层、第三导电层以及第四导电层中的数据信号线51和阳极连接电极53的结构与前述实施例基本上相近，所不同的是，第四导电层中的第二初始信号线52设置在第N+1单元列和第N+3单元列中，单元列中每个电路单元的第二初始信号线52相互连接。
如图19a和图19b所示，在示例性实施例中，第N+1列和第N+3列电路单元中的第二连接电极44包括相互连接的第一部和第二部。第二初始信号线52主体部分沿着第二方向Y延伸，第二初始信号线52通过每个电路单元中的第十二过孔V12与第二连接电极44的第二部连接，使得第一初始信号线和第二初始信号线形成网状结构。
在示例性实施例中，第M行第N+1列电路单元中的第二初始信号线52的形状与第M+1行第N+3列电路单元中的第二初始信号线52的形状可以相同，第M+1行第N+1列电路单元中的第二初始信号线52的形状与第M行第N+3列电路单元中的第二初始信号线52的形状可以相同。
在示例性实施例中，一个电路单元中的第二初始信号线52可以包括延伸部525和连接部526。延伸部525可以为主体部分沿着第二方向Y延伸的折线，连接部526可以为主体部分沿着第一方向X延伸的直线。在示例性实施例中，连接部526远离延伸部525一侧的端部可以通过第十二过孔V12与第二连接电极44连接。
在示例性实施例中，延伸部525在基底上的正投影至少部分位于第一电源线41在基底上的正投影的范围之内，不仅可以使得第一电源线41有效屏蔽第二初始信号线52对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在示例性实施例中，连接部526在基底上的正投影至少部分位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在示例性实施方式中，相邻的第二初始信号线52之间间隔的单元列数没有特殊要求，可以根据需要来设置，本公开在此不做限定。
本示例性实施例中，后续形成发光结构层的过程与前述实施例基本上相近。在形成阳极图案后，第三阳极和第四阳极在基底上的正投影可以与第二初始信号线的连接部在基底上的正投影至少部分重叠，而第一阳极和第二阳极在基底上的正投影与第二初始信号线在基底上的正投影没有重叠，第一像素开口和第二像素开口在基底上的正投影与第二初始信号线在基底上的正投 影没有重叠，即第二初始信号线未穿过第一像素开口和第二像素开口，因而可以保证第一阳极和第二阳极的平坦性，可以避免大视角色偏。
本示例性实施例中，由于第二初始信号线会穿过第一绿色像素开口和/或第二绿色像素开口，因而第一绿色像素开口和/或第二绿色像素开口所在区域可以采用增厚平坦层厚度等手段来改善第三阳极和/或第四阳极的平坦性。
在一种示例性实施例中，第二初始信号线52可以设置在第N+1单元列和第N+3单元列中的部分电路单元中，一单元列中相邻两个第二初始信号线52可以是相互隔离的。例如，第二初始信号线52的主体部分可以分别设置在第M行第N+1列电路单元和第M+1行第N+3列电路单元中，使得后续形成的第三阳极在基底上的正投影与第二初始信号线的延伸部在基底上的正投影至少部分重叠，而第四阳极在基底上的正投影与第二初始信号线的延伸部在基底上的正投影没有重叠区域。又如，第二初始信号线52的主体部分可以分别设置在第M+1行第N+1列电路单元和第M行第N+3列电路单元中，使得后续形成的第四阳极在基底上的正投影与第二初始信号线的延伸部在基底上的正投影至少部分重叠，而第三阳极在基底上的正投影与第二初始信号线的延伸部在基底上的正投影没有重叠区域，本公开在此不做限定。
图20a为本公开示例性实施例又一种驱动电路层的结构示意图，图20b为图20a中第四导电层的平面示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，本示例性实施例驱动电路层中半导体层、第一导电层、第二导电层、第三导电层以及第四导电层中的数据信号线51和阳极连接电极53的结构与前述实施例基本上相近，所不同的是，第四导电层中的第二初始信号线52分别设置在第N单元列、第N+1单元列、第N+2单元列和第N+3单元列中，至少一个单元列中每个电路单元的第二初始信号线52相互连接。
如图20a和图20b所示，在示例性实施例中，至少一列电路单元中的第二连接电极44包括相互连接的第一部和第二部。第二初始信号线52主体部分沿着第二方向Y延伸，第二初始信号线52通过每个电路单元中的第十二过孔V12与第二连接电极44的第二部连接，使得第一初始信号线和第二初始信号线形成网状结构，最大限度地降低了初始信号线的电阻，减小了初始 电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施例中，第N单元列和第N+2单元列中，一个电路单元的第二初始信号线52可以包括延伸部521和连接部522。延伸部521可以为主体部分沿着第二方向Y延伸的折线，连接部522可以为主体部分沿着第一方向X延伸的直线。在示例性实施例中，连接部522远离延伸部521一侧的端部可以通过第十二过孔V12与第二连接电极44连接。
在示例性实施例中，第N+1单元列和第N+3单元列中，一个电路单元的第二初始信号线52可以包括延伸部525和连接部526。延伸部525可以为主体部分沿着第二方向Y延伸的折线，连接部526可以为主体部分沿着第一方向X延伸的直线。在示例性实施例中，连接部526远离延伸部525一侧的端部可以通过第十二过孔V12与第二连接电极44连接。
在示例性实施例中，延伸部521和延伸部525在基底上的正投影至少部分位于第一电源线41在基底上的正投影的范围之内，不仅可以使得第一电源线41有效屏蔽第二初始信号线52对像素驱动电路中关键节点的影响，避免初始信号影响像素驱动电路的关键节点的电位，而且可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
在示例性实施例中，连接部522和连接部526在基底上的正投影至少部分位于第一初始信号线31在基底上的正投影的范围之内，可以充分利用布局空间，避免因设置第二初始信号线影响光透过率，提高了显示效果。
本示例性实施例中，后续形成发光结构层的过程与前述实施例基本上相近。在形成阳极图案后，第一阳极、第二阳极、第三阳极和第四阳极在基底上的正投影可以与第二初始信号线在基底上的正投影至少部分重叠，第一像素开口的第一中心线与第二初始信号线的延伸部的第二中心线至少部分重叠，第二像素开口的第三中心线与数据信号线的第四中心线至少部分重叠，有助于消除各个阳极平坦性之间的差异，可以避免大视角色偏。由于第二初始信号线会穿过第一绿色像素开口和/或第二绿色像素开口，因而第一绿色像素开口和/或第二绿色像素开口所在区域可以采用增厚平坦层厚度等手段来改善第三阳极和/或第四阳极的平坦性。
在一种示例性实施例中，第二初始信号线52可以设置在第N单元列、第N+1单元列、第N+2单元列和第N+3单元列中的部分电路单元中，一单元列中相邻两个第二初始信号线52可以是相互隔离的。例如，在第N单元列和第N+2单元列，相邻电路单元的第二初始信号线52可以是相互连接的，而在第N+1单元列和第N+3单元列，第二初始信号线52可以仅设置在第M行第N+1列电路单元和第M+1行第N+3列电路单元中，或者，第二初始信号线52可以仅设置在第M行第N+3列电路单元和第M+1行第N+1列电路单元中。又如，在第N+1单元列和第N+3单元列，相邻电路单元的第二初始信号线52可以是相互连接的，而在第N单元列和第N+2单元列，第二初始信号线52可以仅设置在第M行第N列电路单元和第M+1行第N+2列电路单元中，或者，第二初始信号线52可以仅设置在第M行第N+2列电路单元和第M+1行第N列电路单元中。再如，第二初始信号线52可以仅设置在第M行第N列电路单元和第M+1行第N+2列电路单元中，或者，第二初始信号线52可以仅设置在第M行第N+2列电路单元和第M+1行第N列电路单元中，第二初始信号线52可以仅设置在第M行第N+1列电路单元和第M+1行第N+3列电路单元中，或者，第二初始信号线52可以仅设置在第M行第N+3列电路单元和第M+1行第N+1列电路单元中，本公开在此不做限定。
图21a为本公开示例性实施例另一种形成阳极图案后的示意图，图21b为图21a中阳极的平面示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，本示例性实施例驱动电路层的结构与前述实施例基本上相近，第四导电层中的第二初始信号线52设置在第N单元列、第N+1单元列、第N+2单元列和第N+3单元列中，单元列中每个电路单元的第二初始信号线52相互连接，所不同的是，发光结构层的阳极采用钻石形方式排列，形成RGBG像素排布。
如图21a和图21b所示，阳极图案可以包括红色发光器件的第一阳极71A、蓝色发光器件的第二阳极71B、第一绿色发光器件的第三阳极71C和第二绿色发光器件的第四阳极71D，第一阳极71A所在区域可以形成出射红色光线的红色子像素R，第二阳极71B所在区域可以形成出射蓝色光线的蓝 色子像素B，第三阳极71C所在区域可以形成出射绿色光线的第一绿色子像素G1，第四阳极71D所在区域可以形成出射绿色光线的第二绿色子像素G2，红色子像素R和蓝色子像素B沿着第二方向Y依次设置，第一绿色子像素G1和第二绿色子像素G2沿着第一方向X依次设置，第一绿色子像素G1设置在红色子像素R和蓝色子像素B第一方向X的反方向一侧，第二绿色子像素G2设置在红色子像素R和蓝色子像素B第一方向X的一侧，红色子像素R、蓝色子像素B、第一绿色子像素G1和第二绿色子像素G2组成一个像素单元。
在示例性实施例中，一个像素单元中，第一阳极71A通过第M行第N列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第二阳极71B通过第M+1行第N列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第三阳极71C通过第M行第N+1列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第四阳极71D通过第M行第N-1列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接。另一个像素单元中，第一阳极71A通过第M+1行第N+2列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第二阳极71B通过第M行第N+2列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第三阳极71C通过第M行第N+1列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接，第四阳极71D通过第M行第N+3列电路单元中的第十四过孔V14与该电路单元中的阳极连接电极53连接。
在示例性实施例中，第一阳极71A和第二阳极71B在基底上的正投影可以与第二初始信号线的延伸部在基底上的正投影至少部分重叠，第三阳极71C和第四阳极71D在基底上的正投影可以与第二初始信号线的连接部在基底上的正投影至少部分重叠。
在示例性实施例中，不同像素单元中的阳极的形状和位置可以相同，或者可以不同，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同，本公开在此不做限定。
图22a为本公开示例性实施例另一种形成像素定义层图案后的示意图， 图22b为图22a中像素定义层的平面示意图，示意了八个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，本示例性实施例驱动电路层和阳极的结构与前述实施例基本上相近，所不同的是，发光结构层中像素定义层72的开口采用钻石形方式排列。
如图22a和图22b所示，像素定义层72图案可以包括暴露出第一阳极71A的第一像素开口73A、暴露出第二阳极71B的第二像素开口73B、暴露出第三阳极71C的第三像素开口73C和暴露出第四阳极71D的第四像素开口73D。
在示例性实施例中，第一像素开口73A在基底上的正投影具有第一中心线Z1，第二初始信号线52的延伸部在基底上的正投影具有第二中心线，第二像素开口73B在基底上的正投影具有第三中心线Z3，数据信号线51在基底上的正投影具有第四中心线，第一中心线Z1是沿着第二方向Y延伸且在第一方向X上平分第一像素开口73A在基底上正投影的线，第二中心线是沿着第二方向Y延伸且在第一方向X上平分第二初始信号线的延伸部在基底上正投影的线，第三中心线Z3是沿着第二方向Y延伸且在第一方向X上平分第二像素开口73B在基底上正投影的线，第四中心线是沿着第二方向Y延伸且在第一方向X上平分数据信号线在基底上正投影的线。
本公开所说的“平分A”可以是中心线使A在基底上正投影的两侧面积基本上相等，两侧面积基本上相等可以存在工艺或公差导致的允许范围内的偏差。例如，两侧面积比值在约为0.8至1.2。本公开所说的“A与B重叠”并不要求A与B完全重叠，可以存在工艺或公差导致的允许范围内的偏差。
在示例性实施例中，第一中心线Z1可以与第三中心线Z3至少部分重叠，第二中心线和第四中心线可以位于第一中心线Z1的两侧，第二中心线和第四中心线可以位于第三中心线的两侧。
在示例性实施例中，第二初始信号线的第二中心线和数据信号线的第四中心线可以相对于第一像素开口的第一中心线Z1对称设置，第二初始信号线的第二中心线和数据信号线的第四中心线可以相对于第二像素开口的第三中心线Z3对称设置。本公开通过设置第二初始信号线的延伸部和数据信号线分别位于第一像素开口73A的第一中心线或第二像素开口73B的第三中心 线的两侧，可以保证了第一阳极和第二阳极的平坦性，可以避免大视角色偏。
本公开所说的“中心线A和中心线B相对于中心线C对称设置”是指，中心线A和中心线C之间的距离与中心线B和中心线C之间的距离的比值约为0.8至1.2。
在示例性实施例中，可以通过调整阳极在电路单元中的位置，使得第二初始信号线的第二中心线均与第一像素开口的第一中心线和第二像素开口的第三中心线重叠，或者，使得数据信号线的第四中心线均与第一像素开口的第一中心线和第二像素开口的第三中心线重叠，本公开在此不做限定。
在示例性实施例中，第三像素开口73C在基底上的正投影具有第五中心线Z5，第四像素开口73D在基底上的正投影具有第六中心线Z6，第二初始信号线52的连接部在基底上的正投影具有第七中心线，第五中心线Z5是沿着第一方向X延伸且在第二方向Y上平分第三像素开口73C在基底上正投影的线，第六中心线Z6是沿着第一方向X延伸且在第二方向Y上平分第四像素开口73D在基底上正投影的线，第七中心线是沿着第一方向X延伸且在第二方向Y上平分第二初始信号线52的连接部在基底上正投影的线。
在示例性实施例中，第五中心线Z5可以与第七中心线至少部分重叠，第六中心线Z6与第七中心线至少部分重叠。本公开通过设置第三像素开口73C的第五中心线与第二初始信号线的连接部的第七中心线至少部分重叠，第四像素开口73D的第六中心线与第二初始信号线的连接部的第七中心线至少部分重叠，可以保证了第三阳极和第四阳极的平坦性，可以避免大视角色偏。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，第一初始信号线可以设置在第一导电层(GATE 1)中。又如，第二初始信号线可以设置在第三导电层(SD1)中，第一电源线可以设置在第四导电层(SD2)中，本公开在此不做限定。本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施例中，所述显示基板包括设置在基底上的驱动电路层和 设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括多个电路单元，所述发光结构层包括多个发光器件；至少一个电路单元包括第一电源线、初始信号线和像素驱动电路，所述初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，所述第一方向与第二方向交叉；所述制备方法包括：
在基底上形成沿所述第一方向延伸的第一初始信号线；
形成沿所述第二方向延伸的第二初始信号线，所述第二初始信号线在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠。
本公开提供的显示基板的制备方法所制作的显示基板，其实现原理和实现效果类似，在此不再赘述。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (23)

  1. 一种显示基板，包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括多个电路单元，所述发光结构层包括多个发光器件；至少一个电路单元包括第一电源线、初始信号线和像素驱动电路，所述初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，所述第一方向与第二方向交叉；所述第二初始信号线在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，至少一个电路单元中的所述第二初始信号线包括相互连接的延伸部和连接部，所述延伸部沿所述第二方向延伸，所述连接部沿所述第一方向延伸，所述连接部通过过孔与所述第一初始信号线连接。
  3. 根据权利要求2所述的显示基板，其中，所述延伸部在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠，所述连接部在基底上的正投影与所述第一初始信号线在基底上的正投影至少部分重叠。
  4. 根据权利要求2所述的显示基板，其中，至少一个电路单元包括第二连接电极，所述连接部通过过孔与所述第二连接电极连接，所述第二连接电极通过过孔与所述第一初始信号线连接。
  5. 根据权利要求4所述的显示基板，其中，所述第二连接电极通过过孔与所述像素驱动电路中第一晶体管的有源层第一区和第七晶体管的有源层第一区连接。
  6. 根据权利要求1所述的显示基板，其中，所述驱动电路层包括多个单元行和多个单元列，所述单元行包括沿所述第一方向排布的多个电路单元，所述单元列包括沿所述第二方向排布的多个电路单元；至少一个单元列中，相邻电路单元中的第二初始信号线相互连接，或者，相邻电路单元中的第二初始信号线间隔设置。
  7. 根据权利要求6所述的显示基板，其中，所述多个电路单元包括与出射红色光线的红色发光器件连接的第一电路单元、与出射蓝色光线的蓝色 发光器件连接的第二电路单元、与出射绿色光线的第一绿色发光器件连接的第三电路单元和与出射绿色光线的第二绿色发光器件连接的第四电路单元；所述多个单元列包括第一单元列和第二单元列，所述第一单元列中的第一电路单元和第二电路单元沿着所述第二方向交替设置，所述第二单元列中的第三电路单元和第四电路单元沿着所述第二方向交替设置；至少部分所述第二初始信号线设置在所述第一单元列中。
  8. 根据权利要求7所述的显示基板，其中，所述发光器件包括阳极和像素定义层；所述阳极包括所述红色发光器件的第一阳极、所述蓝色发光器件的第二阳极、所述第一绿色发光器件的第三阳极和所述第二绿色发光器件的第四阳极；所述像素定义层上设置有暴露出所述第一阳极的第一像素开口、暴露出所述第二阳极的第二像素开口、暴露出所述第三阳极的第三像素开口和暴露出所述第四阳极的第四像素开口；所述第一像素开口在基底上正投影的第一中心线与所述第二初始信号线在基底上正投影的第二中心线至少部分重叠。
  9. 根据权利要求8所述的显示基板，其中，所述驱动电路层还包括数据信号线，所述第二像素开口在基底上正投影的第三中心线与所述数据信号线在基底上正投影的第四中心线至少部分重叠。
  10. 根据权利要求7所述的显示基板，其中，所述发光器件包括阳极和像素定义层；所述阳极包括所述红色发光器件的第一阳极、所述蓝色发光器件的第二阳极、所述第一绿色发光器件的第三阳极和所述第二绿色发光器件的第四阳极；所述像素定义层上设置有暴露出所述第一阳极的第一像素开口、暴露出所述第二阳极的第二像素开口、暴露出所述第三阳极的第三像素开口和暴露出所述第四阳极的第四像素开口；所述驱动电路层还包括数据信号线；所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线位于所述第一像素开口在基底上正投影的第一中心线的两侧。
  11. 根据权利要求10所述的显示基板，其中，所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线相对于所述第一像素开口在基底上正投影的第一中心线对称设置。
  12. 根据权利要求10所述的显示基板，其中，所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线位于所述第二像素开口在基底上正投影的第三中心线的两侧。
  13. 根据权利要求12所述的显示基板，其中，所述第二初始信号线的延伸部在基底上正投影的第二中心线和所述数据信号线在基底上正投影的第四中心线相对于所述第二像素开口在基底上正投影的第三中心线对称设置。
  14. 根据权利要求6所述的显示基板，其中，所述多个电路单元包括与出射红色光线的红色发光器件连接的第一电路单元、与出射蓝色光线的蓝色发光器件连接的第二电路单元、与出射绿色光线的第一绿色发光器件连接的第三电路单元和与出射绿色光线的第二绿色发光器件连接的第四电路单元；所述多个单元列包括第一单元列和第二单元列，所述第一单元列中的第一电路单元和第二电路单元沿着所述第二方向交替设置，所述第二单元列中的第三电路单元和第四电路单元沿着所述第二方向交替设置；至少部分所述第二初始信号线设置在所述第二单元列中。
  15. 根据权利要求14所述的显示基板，其中，所述发光器件包括阳极和像素定义层；所述阳极包括所述红色发光器件的第一阳极、所述蓝色发光器件的第二阳极、所述第一绿色发光器件的第三阳极和所述第二绿色发光器件的第四阳极；所述像素定义层上设置有暴露出所述第一阳极的第一像素开口、暴露出所述第二阳极的第二像素开口、暴露出所述第三阳极的第三像素开口和暴露出所述第四阳极的第四像素开口；所述第三像素开口在基底上正投影的第五中心线与所述第二初始信号线的连接部在基底上正投影的第七中心线至少部分重叠。
  16. 根据权利要求15所述的显示基板，其中，所述第四像素开口在基底上正投影的第六中心线与所述第二初始信号线的连接部在基底上正投影的第七中心线至少部分重叠。
  17. 根据权利要求6所述的显示基板，其中，所述多个电路单元包括与出射红色光线的红色发光器件连接的第一电路单元、与出射蓝色光线的蓝色发光器件连接的第二电路单元、与出射绿色光线的第一绿色发光器件连接的第三电路单元和与出射绿色光线的第二绿色发光器件连接的第四电路单元； 所述多个单元列包括第一单元列和第二单元列，所述第一单元列中的第一电路单元和第二电路单元沿着所述第二方向交替设置，所述第二单元列中的第三电路单元和第四电路单元沿着所述第二方向交替设置；所述第二初始信号线设置在所述第一单元列和所述第二单元列中。
  18. 根据权利要求1至17任一项所述的显示基板，其中，在垂直于显示基板的平面内，所述驱动电路层包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述半导体层包括所述像素驱动电路中多个晶体管的有源层，所述第一导电层包括扫描信号线和多个晶体管的栅电极，所述第二导电层包括所述第一初始信号线，所述第三导电层包括第一电源线，所述第四导电层包括数据信号线和所述第二初始信号线。
  19. 根据权利要求18所述的显示基板，其中，所述第三导电层还包括第二连接电极，所述第二连接电极通过过孔与所述第一初始信号线连接，所述第二初始信号线通过过孔与所述第二连接电极连接。
  20. 根据权利要求18所述的显示基板，其中，所述第二导电层还包括屏蔽电极，所述第一电源线通过过孔与所述屏蔽电极连接。
  21. 根据权利要求20所述的显示基板，其中，所述屏蔽电极的至少部分区域在所述基底上的正投影位于所述数据信号线在所述基底上的正投影与所述像素驱动电路中第一晶体管的第二极在所述基底上的正投影之间。
  22. 一种显示装置，包括如权利要求1至21任一项所述的显示基板。
  23. 一种显示基板的制备方法，所述显示基板包括设置在基底上的驱动电路层和设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括多个电路单元，所述发光结构层包括多个发光器件；至少一个电路单元包括第一电源线、初始信号线和像素驱动电路，所述初始信号线包括沿第一方向延伸的第一初始信号线和沿第二方向延伸的第二初始信号线，所述第一方向与第二方向交叉；所述制备方法包括：
    在基底上形成沿所述第一方向延伸的第一初始信号线；
    形成沿所述第二方向延伸的第二初始信号线，所述第二初始信号线在基底上的正投影与所述第一电源线在基底上的正投影至少部分重叠。
PCT/CN2021/102423 2021-06-25 2021-06-25 显示基板及其制备方法、显示装置 WO2022267016A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP21946510.1A EP4216200A4 (en) 2021-06-25 2021-06-25 DISPLAY BASE PLATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS
CN202180001632.8A CN115868261A (zh) 2021-06-25 2021-06-25 显示基板及其制备方法、显示装置
PCT/CN2021/102423 WO2022267016A1 (zh) 2021-06-25 2021-06-25 显示基板及其制备方法、显示装置
US17/780,533 US20240169908A1 (en) 2021-06-25 2021-06-25 Display Substrate, Preparation Method Therefor, and Display Apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/102423 WO2022267016A1 (zh) 2021-06-25 2021-06-25 显示基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2022267016A1 true WO2022267016A1 (zh) 2022-12-29

Family

ID=84545057

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/102423 WO2022267016A1 (zh) 2021-06-25 2021-06-25 显示基板及其制备方法、显示装置

Country Status (4)

Country Link
US (1) US20240169908A1 (zh)
EP (1) EP4216200A4 (zh)
CN (1) CN115868261A (zh)
WO (1) WO2022267016A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120026144A1 (en) * 2010-07-27 2012-02-02 Ki-Nyeng Kang Organic light emitting display device
CN106098726A (zh) * 2015-04-30 2016-11-09 三星显示有限公司 有机发光显示设备和制造有机发光显示设备的方法
CN109585499A (zh) * 2017-09-29 2019-04-05 三星显示有限公司 显示基板以及包括显示基板的有机发光显示设备
CN210722408U (zh) * 2019-09-25 2020-06-09 昆山工研院新型平板显示技术中心有限公司 一种显示面板和显示装置
JP2020166178A (ja) * 2019-03-29 2020-10-08 株式会社ジャパンディスプレイ 表示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102551789B1 (ko) * 2016-06-15 2023-07-07 삼성디스플레이 주식회사 디스플레이 장치
KR20200051108A (ko) * 2018-11-02 2020-05-13 삼성디스플레이 주식회사 표시 패널

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120026144A1 (en) * 2010-07-27 2012-02-02 Ki-Nyeng Kang Organic light emitting display device
CN106098726A (zh) * 2015-04-30 2016-11-09 三星显示有限公司 有机发光显示设备和制造有机发光显示设备的方法
CN109585499A (zh) * 2017-09-29 2019-04-05 三星显示有限公司 显示基板以及包括显示基板的有机发光显示设备
JP2020166178A (ja) * 2019-03-29 2020-10-08 株式会社ジャパンディスプレイ 表示装置
CN210722408U (zh) * 2019-09-25 2020-06-09 昆山工研院新型平板显示技术中心有限公司 一种显示面板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4216200A4 *

Also Published As

Publication number Publication date
EP4216200A4 (en) 2024-03-20
EP4216200A1 (en) 2023-07-26
CN115868261A (zh) 2023-03-28
US20240169908A1 (en) 2024-05-23

Similar Documents

Publication Publication Date Title
WO2022062465A1 (zh) 显示基板及其制备方法、显示装置
WO2023241490A1 (zh) 显示基板和显示装置
WO2023000125A1 (zh) 显示基板及其制备方法、显示装置
WO2024027669A1 (zh) 显示基板及其制备方法、显示装置
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2022227005A1 (zh) 显示基板及其制备方法、显示装置
WO2022241747A1 (zh) 显示基板及其制备方法、显示装置
WO2022104576A1 (zh) 显示基板及其制作方法、显示装置
WO2022267016A1 (zh) 显示基板及其制备方法、显示装置
WO2024031315A1 (zh) 显示基板及其制备方法、显示装置
WO2023016341A1 (zh) 显示基板及其制备方法、显示装置
WO2023159511A1 (zh) 显示基板及其制备方法、显示装置
WO2023226050A1 (zh) 显示基板及其制备方法、显示装置
WO2023279333A1 (zh) 显示基板及显示装置
WO2024031240A1 (zh) 显示基板及其制备方法、显示装置
WO2023230912A1 (zh) 显示基板及其制备方法、显示装置
WO2023205997A1 (zh) 显示基板及其制备方法、显示装置
WO2023115457A1 (zh) 显示基板及其驱动方法、显示装置
WO2023184352A1 (zh) 显示基板及显示装置
WO2024060082A1 (zh) 显示基板及其制备方法、显示装置
WO2023178612A1 (zh) 显示基板及其制备方法、显示装置
WO2023051103A1 (zh) 显示基板及其制备方法、显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2023201536A1 (zh) 显示基板及其制备方法、显示装置
WO2023201591A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 17780533

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21946510

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2023524807

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2021946510

Country of ref document: EP

Effective date: 20230418

NENP Non-entry into the national phase

Ref country code: DE