WO2022227005A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022227005A1
WO2022227005A1 PCT/CN2021/091499 CN2021091499W WO2022227005A1 WO 2022227005 A1 WO2022227005 A1 WO 2022227005A1 CN 2021091499 W CN2021091499 W CN 2021091499W WO 2022227005 A1 WO2022227005 A1 WO 2022227005A1
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WIPO (PCT)
Prior art keywords
line
segment
sub
lead
data
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PCT/CN2021/091499
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English (en)
French (fr)
Inventor
张振华
徐映嵩
王本莲
张玉欣
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/091499 priority Critical patent/WO2022227005A1/zh
Priority to US17/636,369 priority patent/US20230354655A1/en
Priority to EP21938479.9A priority patent/EP4203053A4/en
Priority to CN202180001059.0A priority patent/CN115552627A/zh
Publication of WO2022227005A1 publication Critical patent/WO2022227005A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a display substrate, a method for manufacturing the same, and a display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • An embodiment of the present disclosure provides a display substrate, including a display area and a binding area on one side of the display area, the binding area at least includes a lead area; the display area includes a plurality of data lines and a plurality of data lines a fan-out line, the lead area includes a plurality of lead-out lines; at least one lead-out line is connected to the data line through the data fan-out line;
  • the display substrate In a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, and between the first conductive layer and the second conductive layer, An insulating layer is provided between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are provided in different conductive layers .
  • the at least one data fan-out line includes a first line segment and a second line segment; a first end of the first line segment is connected to the lead-out line, and a second line segment of the first line segment is connected to the outgoing line. After the end extends away from the lead area, it is connected to the first end of the second line segment; after the second end of the second line segment extends toward the direction close to the lead area, it is connected to the data line through a via hole.
  • the first line segment is parallel to the first direction
  • the second line segment and the first direction have a first included angle
  • the first included angle is 20° to 70° .
  • the second line segment includes a protruding segment and a connecting segment; the first end of the protruding segment is located in the display area and is connected with the second end of the first line segment, so After the second end of the protruding section extends to the edge of the display area in the direction close to the lead area, it is connected with the first end of the connection section, and after the second end of the connection section extends in the direction away from the display area, the The via hole is connected with the data line extending to the lead area; the edge of the display area is the edge of the side of the display area close to the lead area.
  • the display area further includes a first power line and a plate connecting line, the first power line extending along a first direction, and the plate connecting line extending along a second direction; The second direction intersects the first direction;
  • the protruding segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segment and the second sub-line segment are alternately connected, and are located in the protruding segment.
  • the first sub-line segment on one side of the segment is connected with the first line segment
  • the second sub-line segment on the other side of the protruding segment is connected with the connecting segment
  • the first line segment and the second sub-line segment are connected with the connecting segment.
  • the orthographic projection of the line segment on the display substrate plane overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane and the plate connecting line are displayed on the display substrate.
  • the orthographic projections on the substrate plane overlap.
  • the display area further includes a first power line and a plate connecting line, the first power line extending along a first direction, and there is a space between the plate connecting line and the first direction a second included angle, the second included angle is 20° to 70°;
  • the protruding segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segment and the second sub-line segment are alternately connected, and are located in the protruding segment.
  • the first sub-line segment on one side of the segment is connected with the first line segment
  • the second sub-line segment on the other side of the protruding segment is connected with the connecting segment
  • the first line segment and the second sub-line segment are connected with the connecting segment.
  • the orthographic projection of the line segment on the display substrate plane overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane and the plate connecting line are displayed on the display substrate.
  • the orthographic projections on the substrate plane overlap.
  • the plate connection line is located in the second conductive layer
  • the first power supply line is located in the third conductive layer
  • the data fan-out line is located in the fourth conductive layer .
  • the display area further includes a first power line, an initial signal line, and a pad connection line, the first power line extends in a first direction, and the initial signal line and the pad connection line are both extending in a second direction; the second direction intersects the first direction;
  • the protruding segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segment and the second sub-line segment are alternately connected, and are located in the protruding segment.
  • the first sub-line segment on one side of the segment is connected with the first line segment
  • the second sub-line segment on the other side of the protruding segment is connected with the connecting segment
  • the first line segment and the second sub-line segment are connected with the connecting segment.
  • the orthographic projection of the line segment on the display substrate plane overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane is any one of the following: the initial signal The orthographic projection of the line and the plate connecting line on the plane of the display substrate overlaps.
  • the display area further includes a first power line, an initial signal line, and a pad connection line, the first power line extends in a first direction, and the initial signal line and the pad connection line are both There is a second included angle with the first direction, and the second included angle is 20° to 70°;
  • the protruding segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segment and the second sub-line segment are alternately connected, and are located in the protruding segment.
  • the first sub-line segment on one side of the segment is connected with the first line segment
  • the second sub-line segment on the other side of the protruding segment is connected with the connecting segment
  • the first line segment and the second sub-line segment are connected with the connecting segment.
  • the orthographic projection of the line segment on the display substrate plane overlaps with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane is any one of the following: the initial signal The orthographic projection of the line and the plate connecting line on the plane of the display substrate overlaps.
  • the initial signal line and the pad connection line are located in the second conductive layer
  • the first power supply line is located in the third conductive layer
  • the data fan-out line is located in the in the fourth conductive layer.
  • the plurality of lead lines in the lead region have the same width along the second direction, and the distances between adjacent lead lines along the second direction are the same.
  • the plurality of lead lines of the lead region include a first lead group and a second lead group, the lead lines of the first lead group and the lead lines of the second lead group are in a second direction alternate setting;
  • the plurality of lead lines in the first lead group are correspondingly connected to the data lines through a plurality of the data fan-out lines, and the plurality of lead lines in the second lead group are directly connected to the data lines correspondingly.
  • Embodiments of the present disclosure also provide a display device, including the display substrate described in any preceding item.
  • An embodiment of the present disclosure further provides a method for manufacturing a display substrate, the display substrate includes a display area and a binding area on one side of the display area, the binding area at least includes a lead area; the manufacturing method includes: :
  • a plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead area; at least one lead-out line is connected to the data line through the data fan-out line; In the plane of the An insulating layer is provided between the layer and the third conductive layer, the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are provided in different conductive layers.
  • 1 is a schematic structural diagram of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic plan view of a display area in a display substrate
  • FIG. 4 is a schematic cross-sectional structure diagram of a display region in a display substrate
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a working timing diagram of a pixel driving circuit
  • FIG. 7 is a schematic plan view of a binding area in a display substrate
  • FIG. 8 is a schematic diagram of a data fanout line in a binding area
  • FIG. 9 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a side view of the substrate shown in FIG. 9;
  • FIG. 11 is a schematic structural diagram of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • Figure 12 is an enlarged view of the C1 region in Figure 11;
  • Figure 13 is an enlarged view of the C2 region in Figure 12;
  • Figure 14 is a sectional view taken along the A-A direction in Figure 13;
  • 15 is a schematic structural diagram of another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • Figure 16 is an enlarged view of the C3 region in Figure 15;
  • 17 is a schematic structural diagram of still another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • Figure 18 is an enlarged view of the C4 region in Figure 17;
  • FIG. 19 is a schematic structural diagram of still another lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure
  • Figure 20 is an enlarged view of the C5 region in Figure 19;
  • 21a is a schematic diagram of a display substrate of the present disclosure after a semiconductor layer pattern is formed
  • Figure 21b is a cross-sectional view taken along the direction A-A in Figure 21a;
  • 22a is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the disclosure
  • Figure 22b is a cross-sectional view taken along the direction A-A in Figure 22a;
  • 23a is a schematic diagram of a display substrate after forming a second conductive layer pattern according to the disclosure.
  • Figure 23b is a cross-sectional view taken along the direction A-A in Figure 23a;
  • 24a is a schematic diagram of a display substrate of the present disclosure after a fourth insulating layer pattern is formed;
  • Figure 24b is a cross-sectional view taken along the direction A-A in Figure 24a;
  • FIG. 25a is a schematic diagram of a display substrate of the present disclosure after a third conductive layer pattern is formed
  • Figure 25b is a cross-sectional view taken along the direction A-A in Figure 25a;
  • 26a is a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to the disclosure.
  • Figure 26b is a cross-sectional view taken along the direction A-A in Figure 26a;
  • FIG. 27a is a schematic diagram of a display substrate of the present disclosure after a flat layer pattern is formed
  • Figure 27b is a cross-sectional view taken along the direction A-A in Figure 27a;
  • 28a is a schematic diagram of a display substrate of the present disclosure after an anode pattern is formed
  • Figure 28b is a cross-sectional view taken along the direction A-A in Figure 28a;
  • FIG. 29 is a schematic plan view of a display area in a display substrate.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light-emitting signal driver, and a pixel array
  • the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data lines ( D1 to Dn), a plurality of light-emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij.
  • the timing controller may supply a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may supply a clock signal, a scan start signal, etc., suitable for the specification of the scan signal driver When supplied to the scan signal driver, a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting signal driver can be supplied to the light-emitting signal driver.
  • the data signal driver may generate data voltages to be supplied to the data lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller.
  • the data signal driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be constructed in the form of a shift register, and may generate scans in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal signal, m can be a natural number.
  • the emission signal driver may generate emission signals to be supplied to the emission signal lines E1 , E2 , E3 , . . . and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the emission signal driver may sequentially supply emission signals having off-level pulses to the emission signal lines E1 to Eo.
  • the light-emitting signal driver may be constructed in the form of a shift register, and may generate the light-emitting signal in such a manner that the light-emitting stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o can be a natural number.
  • the pixel array may include a plurality of sub-pixels Pxij, each sub-pixel Pxij may be connected to a corresponding data line, a corresponding scanning signal line and a corresponding light-emitting signal line, and i and j may be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 on one side of the display area 100 , and a frame area 300 on the other side of the display area 100 .
  • the display area 100 may include a plurality of sub-pixels configured to display moving pictures or still images
  • the binding area 200 may include connecting lines and circuits connecting a plurality of data lines to an integrated circuit
  • the bezel area 300 may include power lines that transmit voltage signals
  • the binding area 200 and the frame area 300 may include isolation dams in a ring structure
  • at least one side of the frame area 300 may be a curled area formed by bending, or both the display area 100 and the frame area 300 may be bent or curved region, which is not limited in this disclosure.
  • the display area may include a plurality of pixel units arranged in a matrix.
  • FIG. 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a first sub-pixel P1 that emits light of a second color.
  • the two sub-pixels P2 and the third sub-pixel P3 that emits light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data line and the light-emitting signal line, and the pixel driving circuit is configured to connect between the scanning signal line and the light-emitting signal line.
  • the data voltage transmitted by the data line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, and blue sub-pixels and white sub-pixels, which are not limited in this disclosure.
  • the shape of the sub-pixels in the pixel unit may be a rectangle, a diamond, a pentagon or a hexagon.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. The arrangement is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display area in a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the substrate 101 , a light emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101 , and a light emitting structure layer 103 disposed on the light emitting
  • the structure layer 103 is away from the encapsulation layer 104 on the side of the substrate 101 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or it may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and only one transistor 102A and one storage capacitor 102B are taken as an example in FIG. 4 .
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304.
  • the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting
  • the layers 303 are connected, and the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light of the corresponding color.
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting structure layer 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL) .
  • HIL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layers of all subpixels may be a common layer connected together
  • the electron injection layers of all subpixels may be a common layer connected together
  • the hole transport layers of all subpixels may be A common layer connected together
  • the electron transport layer of all subpixels can be a common layer connected together
  • the hole blocking layer of all subpixels can be a common layer connected together
  • the light emitting layers of adjacent subpixels can have a small amount of The electron blocking layers of adjacent sub-pixels may overlap slightly, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may include seven switching transistors (the first transistor T1 to the seventh transistor T7 ), one storage capacitor C1 and seven signal lines (the data line DATA, the first scan signal line S1, the Two scan signal lines S2, an initial signal line INIT, a first power supply line VDD, a second power supply line VSS and a light-emitting signal line EM).
  • the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2 connect.
  • the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the gate electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data line DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the first end of the storage capacitor C1 is connected to the first power line VDD, and the second end of the storage capacitor C1 is connected to the second node N2.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the second pole of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuous high-level signal.
  • the first scan signal line S1 is the scan signal line in the pixel driving circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row, that is, for the nth display row
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line and the first scanning signal line S1 in the pixel driving circuit of the previous display line can be
  • the same signal line is used to reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first scan signal line S1, the second scan signal line S2, the light emission signal line EM and the initial signal line INIT extend in the horizontal direction
  • the second power supply line VSS, the first power supply line VDD and the data line DATA Extend vertically.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 6 is a working timing diagram of a pixel driving circuit.
  • the pixel driving circuit in FIG. 5 includes seven transistors (the first transistor T1 to the sixth transistor T7 ) and one storage capacitor C1 and 7 signal lines (data line DATA, first scan signal line S1, second scan signal line S2, initial signal line INIT, first power line VDD, second power line VSS, and light-emitting signal line EM), and the seven transistors are P-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called a reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are a high-level signal.
  • the signal of the second scanning signal line S2 is a low level signal, which turns on the first transistor T1
  • the signal of the initial signal line INIT is supplied to the second node N2 to initialize the storage capacitor C1 and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage, the signal of the first scanning signal line S1 is a low-level signal, the signals of the second scanning signal line S2 and the light-emitting signal line EM are a high-level signal, and the data Line DATA outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data line DATA is supplied to the second node through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 N2, and the difference between the data voltage output by the data line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1, and the voltage of the second end (second node N2) of the storage capacitor C1 is Vdata-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, initializes (resets) the first electrode of the OLED, clears the internal pre-stored voltage, completes the initialization, and ensures that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high-level signal, so that the first transistor T1 is turned off.
  • the signal of the light-emitting signal line EM is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are a high-level signal.
  • the signal of the light-emitting signal line EM is a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD passes through the fifth transistor T5, the third transistor T3 and the sixth transistor T5, which are turned on.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor.
  • Vdata is the data voltage output by the data line DATA
  • Vdd is the power supply voltage output by the first power line VDD.
  • FIG. 7 is a schematic plan view of a binding area in a display substrate
  • FIG. 8 is a schematic diagram of a data fan-out line in the binding area.
  • the binding area 200 in a plane parallel to the display substrate, is located on one side of the display area 100 , and the binding area 200 may include first fan-out areas 201 arranged in sequence along a direction away from the display area 100 . , a bending area 202 , a second fan-out area 203 , an anti-static area 204 , a driving chip area 205 and a bonding pin area 206 .
  • the first fan-out area 201 includes at least data fan-out lines, and a plurality of data fan-out lines are configured to connect data lines (Data Lines) of the display area in a fan-out (Fanout) routing manner, as shown in FIG. 8 .
  • the bending area 202 includes a composite insulating layer provided with grooves, and is configured to bend the binding area 200 to the back of the display area 100 .
  • the second fan-out area 203 includes a plurality of data fan-out lines drawn out in a fan-out routing manner.
  • the anti-static area 204 includes an anti-static circuit configured to prevent electrostatic damage to the display substrate by eliminating static electricity.
  • the driver chip area 205 includes an integrated circuit (Integrated Circuit, IC for short), and is configured to be connected to a plurality of data fan-out lines.
  • the bonding pin area 206 includes a bonding pad (Bonding Pad), which is configured to be bonded and connected to an external flexible printed circuit (Flexible Printed Circuit, FPC for short).
  • the left frame, right frame and upper frame of the display device can be controlled within 1.0mm, but the narrowing design of the lower frame (the frame on the side of the binding area) is relatively difficult and has been maintained at about 2.0mm. This is because the data fan-out line is usually set in the fan-out area of the binding area, and the fan-shaped area occupies a large space. Usually, the width of the binding area is smaller than the width of the display area.
  • the signal lines of the integrated circuits and the binding pads in the binding area need to be fan-out through the fan-out area to be introduced into the wider display area.
  • the display substrate may include a display area and a binding area on one side of the display area, the binding area includes at least a lead area; the display area includes a plurality of data lines and a plurality of data fan-out lines, and the lead area includes a plurality of lead lines; at least one lead line is connected to the data line through the data fan-out line; in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, and a third conductive layer and a fourth conductive layer, between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer An insulating layer is arranged between them; the data lines and the data fan-out lines are arranged in different conductive layers.
  • FIG. 9 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG. 10 is a side view of the display substrate in FIG. 9
  • the display substrate 10 may include a display area 100 , a binding area 500 on one side of the display area 100 , and a frame area 300 on the other side of the display area 100 .
  • the display area 100 may be a flattened area including a plurality of sub-pixels Pxij constituting a pixel array, a plurality of data lines and a plurality of data fan-out lines, and the plurality of sub-pixels Pxij are configured to display moving pictures or still images,
  • the plurality of data lines are configured to provide data signals to the plurality of sub-pixels Pxij
  • the plurality of data fanout lines are correspondingly connected to the plurality of data lines
  • the display substrate may adopt a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded or rolled.
  • the bonding area 500 may include a lead area 501, a bending area 502, and a composite circuit area 503 sequentially disposed along a reverse direction of the first direction D1 (a direction away from the display area), and the lead area 501 is connected to In the display area 100 , the bending area 502 is connected to the lead area 501 , and the composite circuit area 503 is connected to the bending area 502 .
  • the lead area 501 may be provided with a plurality of lead lines, one end of a part of the lead lines is correspondingly connected to the plurality of data fan-out lines in the display area 100 , and one end of the other part of the lead lines is connected to the display area 100
  • a plurality of data lines in are connected correspondingly, and the other ends of the plurality of lead lines are connected to the integrated circuits in the composite circuit region 503 across the bending region 502, so that the integrated circuits apply data signals to the data lines through the lead lines and the data fan-out lines.
  • the bending region 502 can be bent with a curvature in the third direction D3, and the surface of the composite circuit region 503 can be reversed, that is, the surface of the composite circuit region 503 facing upward can pass through the bending region 502.
  • the bending is converted to face downward, and the third direction D3 intersects the first direction D1.
  • the composite circuit region 503 may overlap the display region 100 in the third direction D3 (thickness direction).
  • the composite circuit area 503 may include an anti-static area, a driving chip area and a binding pin area, and the integrated circuit (Integrate Circuit, IC for short) 20 may be bound and connected to the driving chip area, and the flexible circuit board ( Flexible Printed Circuit (FPC for short) 30 can be bound and connected in the binding pin area.
  • the integrated circuit 20 may generate driving signals required for driving the sub-pixels, and may provide the driving signals to the sub-pixels in the display area 100 .
  • the driving signal may be a data signal for driving the luminance of the sub-pixels.
  • the integrated circuit 20 may be bonded and connected to the driving chip area through an anisotropic conductive film or other means, and the width of the integrated circuit 20 in the second direction D2 may be smaller than that of the composite circuit area 503 in the second direction D2 The width of the second direction D2 intersects the first direction D1.
  • the bonding pin area may be provided with pads including a plurality of pins (PINs), and the flexible circuit board 30 may be bonded and connected to the pads.
  • the first direction D1 may be the extension direction (column direction) of the data lines in the display area
  • the second direction D2 may be the extension direction (row direction) of the scan signal lines in the display area
  • the third direction D3 It may be a direction perpendicular to the plane of the display substrate, the first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.
  • FIG. 11 is a schematic structural diagram of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure.
  • the display area 100 may include multiple sub-pixels, multiple data lines DA and multiple data fan-out lines 700 arranged in a matrix, and the lead area 501 of the binding area may include multiple lead-out lines 600 .
  • a plurality of sub-pixels in the display area 100 form a plurality of pixel rows and a plurality of pixel columns, and the plurality of data lines DA extend along the opposite direction of the first direction D1 and extend along the second direction D2 to The set intervals are arranged in sequence, each data line DA is connected to all sub-pixels of a pixel column in the display area 100, and the end of each data line DA extends to the lead area 501 of the binding area.
  • each data fan-out line 700 is correspondingly connected to a part of the lead lines 600 of the lead area 501
  • the second end of each data fan-out line 700 is correspondingly connected to a part of the data line DA extending to the lead area 501
  • a part of the lead lines 600 in the lead area 501 is connected to the data fan-out line 700
  • another part of the lead lines 600 is correspondingly connected to another part of the data lines DA extending to the lead area 501 .
  • the display substrate has a center line O, the center line O extends along the first direction D1 and bisects a plurality of pixel columns of the display area 100 , a plurality of data lines DA, a plurality of data sectors in the display area 100
  • the outgoing wires 700 and the plurality of outgoing wires 600 in the lead area 501 of the bonding area may be symmetrically arranged with respect to the center line O.
  • the plurality of data lines DA, the plurality of data fan-out lines 700 in the display area 100, and the plurality of lead lines 600 in the lead area 501 of the binding area may also be different on both sides of the center line O.
  • Symmetrical arrangement for example, a plurality of data lines DA, a plurality of data fan-out lines 700 in the display area 100, and a plurality of lead lines 600 in the lead area 501 of the binding area may have similar designs on both sides of the center line O .
  • the left side of the display substrate includes N data lines, M data fan-out lines and N lead-out lines as an example, where N is a positive integer greater than 2, and M is a positive integer greater than 2 and less than N.
  • the N data lines on the left side of the display area may be divided into a first data line group and a second data line group according to the size of the numbers.
  • the first data line group may include a first data line DA1, a second data line DA2, ..., an Mth data line
  • the second data line group may include (M+1)th data line, (M+2)th data line line, ..., the Nth data line.
  • M may be the number of data lines that need to be drawn out in a fan-out manner.
  • M may be N/2
  • N when N is an odd number, M may be (N+1)/2, or M may be (N-1)/2.
  • M can be set according to the actual situation, which is not limited in this disclosure.
  • the plurality of data lines of the first data line group are sequentially arranged along the second direction D2 in a manner of increasing numbers
  • the plurality of data lines of the second data line group are arranged along the second direction D2 in a manner of increasing numbers.
  • the directions D2 are arranged in sequence, and the second data line group is arranged on one side of the second direction D2 of the first data line group. That is to say, the N data lines include the first data line DA1 , the second data line DA2 , .
  • the direction D2 increases sequentially.
  • the i-th data line may be a data line located in the i-th pixel column, and the i-th data line is connected to the sub-pixels in the i-th pixel column.
  • the N lead lines on the left side of the lead area 501 may be divided into a first lead group and a second lead group according to the size of the numbers.
  • the first lead group may include a first lead wire 601, a second lead wire 602, ..., the Mth lead wire
  • the second lead group may include the (M+1)th lead wire, the (M+2)th lead wire, ..., the Nth lead wire.
  • the plurality of lead lines of the first lead group are sequentially arranged along the opposite direction of the second direction D2 in a manner of increasing numbers, and the plurality of lead lines of the second lead group are arranged along the first line in a manner of increasing numbers.
  • the two directions D2 are arranged in sequence, and the lead wires of the first lead group and the lead wires of the second lead group are alternately arranged.
  • the first lead line is adjacent to the Nth lead line
  • the second lead line is adjacent to the N-1th lead line
  • the Mth lead line is adjacent to the (M+1)th lead line.
  • a plurality of lead lines in the first lead group may be correspondingly connected to a plurality of data lines in the first data line group through a plurality of data fan-out lines, and a plurality of lead lines in the second lead group may be connected It is directly connected to a plurality of data lines in the second data line group, and the lead lines can provide data signals to the data lines directly or through data fan-out lines.
  • the edge B of the display area is the edge of the side of the display area 100 close to the lead area 501 .
  • the i-th data fan-out line may include a first line segment and a second line segment connected in sequence. After the second end of the line segment extends in a direction away from the lead area, it is connected to the first end of the second line segment. After the second end of the second line segment extends from the display area 100 to the lead area 501 in the direction of the lead area, it is connected to the i-th data line extending to the lead area 501 .
  • the second line segment may include a protruding segment and a connecting segment, a first end of the protruding segment is located in the display area 100 and is connected with a second end of the second line segment, and the second end of the protruding segment faces toward After the direction close to the lead area extends to the edge B of the display area, it is connected to the first end of the connection segment, and the second end of the connection segment extends in the direction away from the display area, and is connected to the i-th data line extending to the lead area through the via hole. connect.
  • connection segment may be a polyline segment, including a vertical line segment parallel to the first direction D1 and a horizontal line segment parallel to the second direction D2.
  • the plurality of data lines in the first data line group and the second data line group may be arranged to be parallel to the first direction D1, and the plurality of lead lines in the first lead group and the second lead group It can be arranged to be parallel to the first direction D1, that is, the lead lines are parallel to the data lines.
  • the extension lines of the plurality of data lines in the first direction D1 in the second data line group may correspondingly overlap with the plurality of lead lines in the second lead line group.
  • the first line segments of the plurality of data fan-out lines may be arranged to be parallel to the first direction D1, and the second line segments of the plurality of data fan-out lines may be arranged to have a first clip with the first direction D1.
  • the angle ⁇ 1 and the first included angle ⁇ 1 may be greater than 0° and less than 90°.
  • the first included angle ⁇ 1 may be about 20° to 70°, and the first included angle ⁇ 1 and the second included angle ⁇ 2 may be the same, or may be different.
  • At least one first line segment is disposed between adjacent data lines.
  • a plurality of line segments of the kth data fan-out line may form a triangular line, and the triangle line formed by the kth data fan-out line is nested within the triangle line formed by the k-1th data fan-out line to form a triangular line formed by the k-th data fan-out line.
  • the distance between the first end of the second line segment of the k-1th data fan-out line and the edge B of the display area is greater than the distance between the first end of the second line segment of the kth data fan-out line and the edge B of the display area
  • the plurality of data lines may include a first data line DA1, a second data line DA2, a third data line DA3, a fourth data line DA4, a fifth data line DA5,
  • the sixth data line DA6, the seventh data line DA7 and the eighth data line DA8, the plurality of lead lines in the lead area 501 of the binding area may include the first lead lines 601, Eighth lead-out line 608 , second lead-out line 602 , seventh lead-out line 607 , third lead-out line 603 , sixth lead-out line 606 , fourth lead-out line 604 , and fifth lead-out line 605 .
  • the first end of the first data fan-out line 701 is connected with the first lead-out line 601 near the edge B of the display area, the second end extends to the vicinity of the first data line DA1 of the display area 100, and then from the display area
  • the area 100 extends to the lead area 501 and is connected to the first data line DA1.
  • the first end of the second data fan-out line 702 is connected to the second lead line 602 near the edge B of the display area, the second end extends to the vicinity of the second data line DA2 of the display area 100 , and then extends from the display area 100 to the lead area 501 connected to the second data line DA2.
  • the first end of the third data fan-out line 703 is connected to the third lead-out line 603 near the edge B of the display area, the second end extends to the vicinity of the third data line DA3 of the display area 100 , and then extends from the display area 100 to the lead area 501 connected with the third data line DA3.
  • the first end of the fourth data fan-out line 704 is connected to the fourth lead line 604 near the edge B of the display area, and the second end extends to the vicinity of the fourth data line DA4 of the display area 100, and then extends from the display area 100 to the lead area 501 connected to the fourth data line DA4.
  • the fifth data line DA5 extending to the lead area 501 is directly connected to the fifth lead line 605
  • the sixth data line DA6 extending to the lead area 501 is directly connected to the sixth lead line 606, extending to the lead line
  • the seventh data line DA7 in the area 501 is directly connected with the seventh lead line 607
  • the eighth data line DA8 extending to the lead area 501 is directly connected with the eighth lead line 608 .
  • the second line segment of the data fan-out line may be located on the left side of the corresponding data line , or a part of the second line segment is located on the right side of the data line, and another part of the second line segment is located on the left side of the data line, which is not limited in the present disclosure.
  • FIG. 13 is an enlarged view of the C2 region in FIG. 12 .
  • the third data line DA3 , the fourth data line DA4 , the fifth data line DA5 and the sixth data line DA6 respectively extend to the lead area 501 of the bonding area along the first direction D1 .
  • the third data fan-out line 703 first extends to the vicinity of the third data line DA3 of the display area 100, then extends from the display area 100 to the lead area 501, and passes through the first via K1 and the third data line DA3. end connections.
  • the fourth data fan-out line 704 first extends to the vicinity of the fourth data line DA4 in the display area 100, then extends from the display area 100 to the lead area 501, and is connected to the end of the fourth data line DA4 through the second via hole K2.
  • the fifth lead line 605 is connected to the end of the fifth data line DA5 through the third via K3, and the sixth connection signal line 606 is connected to the end of the sixth data line DA6 through the fourth via K4.
  • the data line and the data fan-out line may be disposed in different film layers, and an insulating layer is disposed between the data line and the data fan-out line.
  • the lead-out line and the data fan-out line may be disposed in the same film layer and formed simultaneously by the same patterning process, and the lead-out line and the data fan-out line may be an integral structure connected to each other.
  • the lead-out line and the data fan-out line may be disposed in different film layers, an insulating layer is disposed therebetween, and the two are connected through via holes.
  • FIG. 14 is a cross-sectional view taken along the line A-A in FIG. 13 .
  • the display substrate in a plane perpendicular to the display substrate, the display substrate may include a plurality of conductive layers disposed on the substrate, and the plurality of conductive layers may include a first conductive layer, a second conductive layer and a second conductive layer disposed in sequence along the direction away from the substrate layer, a third conductive layer and a fourth conductive layer
  • the first conductive layer (not shown in the figure) may include scan signal lines, gate electrodes of a plurality of transistors, light-emitting control lines and first plates of storage capacitors
  • the second The conductive layer (not shown in the figure) can include the initial signal line, the plate connecting line and the second plate of the storage capacitor
  • the third conductive layer can include: the first power line (not shown in the figure), the data line,
  • the source electrodes and drain electrodes (not shown in the figure) of the plurality of transistors, and the fourth conductive layer may
  • the display substrate in a plane perpendicular to the display substrate, may include a semiconductor layer and a plurality of insulating layers, the semiconductor layer may include active layers of a plurality of transistors, and the plurality of insulating layers may include a plurality of insulating layers along a distance away from the substrate
  • the first insulating layer 91 , the second insulating layer 92 , the third insulating layer 93 , the fourth insulating layer 94 and the fifth insulating layer 95 are arranged in sequence.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the side of the first insulating layer 91 away from the substrate
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed on the second
  • the insulating layer 92 is on the side away from the substrate
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is arranged on the side of the third insulating layer 93 away from the substrate
  • the fourth insulating layer 94 covers the second conductive layer
  • the third insulating layer 94 covers the second conductive layer.
  • the conductive layer is disposed on the side of the fourth insulating layer 94 away from the substrate
  • the fifth insulating layer 95 covers the third conductive layer
  • the fourth conductive layer is disposed on the side of the fifth insulating layer 95 away from the substrate.
  • the orthographic projection of any one of the lead lines on the substrate has no overlapping area with the orthographic projections of other lead lines on the substrate, and the orthographic projection of any one of the data fan-out lines on the substrate and other data fan-out lines on the substrate
  • the orthographic projections have no overlapping areas.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride Any one or more of (SiON), which may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer, and is configured to prevent impurity diffusion of ions, prevent moisture penetration, and perform a surface planarization function.
  • the third insulating layer between the first conductive layer and the second conductive layer may be referred to as a gate insulating (GI) layer, and the fourth insulating layer disposed between the second conductive layer and the third conductive layer may be referred to as a layer inter-insulation (ILD) layer.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • any one or more of the above metals, or alloy materials of the above metals can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • the active layer based on oxide technology can employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin , oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • the fifth insulating layer 95 may be provided with a plurality of openings (K1 to K4 in the figure), the plurality of openings are located at the ends of the data lines, and the fifth insulating layer 95 in the openings is Etched away to expose the surface of the data lines.
  • the openings are configured so that the data fan-out lines or lead-out lines formed later are correspondingly connected to the data lines through the openings.
  • the width M of each lead-out line is the same, the distance L between adjacent lead-out lines is the same, and both the width M and the distance L are in the second direction D2 size.
  • the width of each data fanout line may be the same.
  • FIG. 15 is a schematic structural diagram of another lead-out line and data fan-out line according to an embodiment of the disclosure
  • FIG. 16 is an enlarged view of the C3 area in FIG. 15 .
  • the display area also includes a first power line VDD and a plate connecting line 35, the first power line VDD extends along the first direction D1, and the plate connecting line 35 extends along the second direction D2;
  • the protruding segment 700b includes M1 first sub-line segments 700b1 and M1 second sub-line segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-line segment 700b1 and the second sub-line segment 700b2 are alternately connected, and are located on the first line of the protruding segment 700b.
  • the first sub-line segment 700b1 on the side is connected to the first line segment 700a
  • the second sub-line segment 700b2 located on the other side of the protruding segment 700b is connected to the connecting segment 700c
  • the first line segment 700a and the second sub-line segment 700b2 are on the display substrate plane.
  • the orthographic projections of the first power line VDD overlap with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-line segment 700b1 on the display substrate plane overlaps with the orthographic projection of the plate connecting line 35 on the display substrate plane.
  • FIG. 17 is a schematic structural diagram of another lead-out line and data fan-out line according to an embodiment of the disclosure
  • FIG. 18 is an enlarged view of the C4 area in FIG. 17
  • the display area It also includes a first power line VDD and a plate connecting line 35, the first power line VDD extends along the first direction D1, and the plate connecting line 35 and the first direction D1 have a second included angle ⁇ 2, and the second included angle ⁇ 2 20° to 70°;
  • the protruding segment 700b includes M1 first sub-line segments 700b1 and M1 second sub-line segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-line segment 700b1 and the second sub-line segment 700b2 are alternately connected, and are located on the first line of the protruding segment 700b.
  • the first sub-line segment 700b1 on the side is connected to the first line segment 700a
  • the second sub-line segment 700b2 located on the other side of the protruding segment 700b is connected to the connecting segment 700c
  • the first line segment 700a and the second sub-line segment 700b2 are on the display substrate plane.
  • the orthographic projections of the first power line VDD overlap with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-line segment 700b1 on the display substrate plane overlaps with the orthographic projection of the plate connecting line 35 on the display substrate plane.
  • the pad connection line 35 is located in the second conductive layer
  • the first power supply line VDD is located in the third conductive layer
  • the data fan-out line 700 is located in the fourth conductive layer.
  • FIG. 19 is a schematic structural diagram of another lead-out line and data fan-out line according to an embodiment of the disclosure
  • FIG. 20 is an enlarged view of the C5 area in FIG. 19
  • the display area also includes a first power line VDD, an initial signal line 31 and a plate connecting line 35, the first power line VDD extends along the first direction D1, and the initial signal line 31 and the plate connecting line 35 both extend along the second direction D2;
  • the protruding segment 700b includes M1 first sub-line segments 700b1 and M1 second sub-line segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-line segment 700b1 and the second sub-line segment 700b2 are alternately connected, located in the protruding segment
  • M1 is a natural number greater than or equal to 1
  • the first sub-line segment 700b1 and the second sub-line segment 700b2 are alternately connected, located in the protruding segment
  • the first sub-line segment 700b1 on one side of 700b is connected with the first line segment 700a
  • the second sub-line segment 700b2 on the other side of the protruding segment 700b is connected with the connecting segment 700c.
  • the first line segment 700a and the second sub-line segment 700b2 are shown in the display
  • the orthographic projection on the substrate plane overlaps with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-line segment 700b1 on the display substrate plane is any one of the following: the initial signal line 31 and the plate connecting line 35.
  • the orthographic projections on the plane of the display substrate overlap.
  • the display area further includes a first power line VDD, an initial signal line and a pad connection line 35, the first power line VDD extends along the first direction D1, and the initial signal line 31 and the pad connection line 35 are both There is a second included angle with the first direction D1, and the second included angle is 20° to 70°;
  • the protruding segment 700b includes M1 first sub-line segments 700b1 and M1 second sub-line segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-line segment 700b1 and the second sub-line segment 700b2 are alternately connected, and are located on the first line of the protruding segment 700b.
  • the first sub-line segment 700b1 on the side is connected to the first line segment 700a
  • the second sub-line segment 700b2 located on the other side of the protruding segment 700b is connected to the connecting segment 700c
  • the first line segment 700a and the second sub-line segment 700b2 are on the display substrate plane.
  • the orthographic projection of the first power line VDD on the display substrate plane overlaps, and the orthographic projection of the first sub-line segment 700b1 on the display substrate plane is any one of the following: the initial signal line 31 and the plate connecting line 35, The orthographic projections on the display substrate plane overlap.
  • the initial signal line 31 and the pad connection line 35 are located in the second conductive layer
  • the first power supply line VDD is located in the third conductive layer
  • the data fan-out line 700 is located in the fourth conductive layer.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • A's orthographic projection includes B's orthographic projection means that the boundary of B's orthographic projection falls within the boundary of A's orthographic projection, or the boundary of A's orthographic projection overlaps with the boundary of B's orthographic projection.
  • the manufacturing process of the display substrate may include the following operations.
  • a semiconductor layer pattern is formed.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate.
  • the semiconductor layer on the first insulating layer is shown in FIG. 21a and FIG. 21b, and FIG. 21b is a cross-sectional view taken along the line A-A in FIG. 21a.
  • the semiconductor layer of each sub-pixel may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 11
  • the source layer 17 is an interconnected integral structure.
  • the first region R1 may include at least part of the first active layer 11 of the first transistor T1 , the second active layer 12 of the second transistor T2 , and the fourth active layer of the fourth transistor T4 14 and the seventh active layer 17 of the seventh transistor T7
  • the second region R2 may include at least part of the third active layer 13 of the third transistor T3
  • the third region R3 may include at least part of the third active layer 13 of the fifth transistor T5.
  • the first active layer 11 and the seventh active layer 17 are disposed on the side of the first region R1 away from the second region R2, and the second active layer 12 and the fourth active layer 14 are disposed adjacent to the first region R1 One side of the second region R2.
  • the shape of the first active layer 11 may be in the shape of "n"
  • the shape of the second active layer 12 may be in the shape of "7”
  • the shape of the third active layer 13 may be in the shape of "six”
  • the shape of the fourth active layer 14 may be in the shape of "1”
  • the shape of the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be in the shape of "L”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 11-1 of the first active layer 11 simultaneously serves as the first region 17-1 of the seventh active layer 17, and the second region 11-2 of the first active layer 11 simultaneously serves as the first region 11-1 of the seventh active layer 17.
  • the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the fifth active layer 15
  • the second region 15-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16
  • the second region 16 - 2 of the sixth active layer 16 simultaneously serves as the second region 17 - 2 of the seventh active layer 17 .
  • the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are provided separately.
  • the third active layer 13 of the third transistor includes a first region 13-1, a second region 13-2 and a channel region, and the channel region of the third active layer 13 is disposed on the first region 13-1. Between the region 13-1 and the second region 13-2, and both ends of the channel region are connected to the first region 13-1 and the second region 13-2, respectively.
  • the first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, namely the third active layer 13
  • the first region 13-1 of the fourth active layer 14, the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15 are connected to each other.
  • the second region 13-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, that is, the third active layer 13
  • the second region 13-2 of the second active layer 12, the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16 are connected to each other.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10 and a semiconductor layer disposed on the first insulating layer 91, and the semiconductor layer may include the first active layer 11 and the first active layer 11 Three active layers 13 .
  • a first conductive layer pattern is formed.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, and patterning the first metal film through a patterning process to form A second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22, and a light-emitting control line 23 and the first plate 24 of the storage capacitor, as shown in FIG. 22a and FIG. 22b, and FIG. 22b is a cross-sectional view taken along the direction A-A in FIG. 22a.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first scan signal line 21, the second scan signal line 22, and the light emission control line 23 extend in the second direction D2.
  • the first scan signal line 21 and the second scan signal line 22 are arranged in the first region R1, the second scan signal line 22 is located on the side of the first scan signal line 21 away from the second region R2, and the light emission control line 23 is arranged in the first region R1.
  • the first plate 24 of the storage capacitor is arranged in the second region R2 , between the first scanning signal line 21 and the light-emitting control line 23 .
  • the first electrode plate 24 may be rectangular, the corners of the rectangle may be provided with chamfers, and the orthographic projection of the first electrode plate 24 on the substrate and the third active layer of the third transistor T3 are at The orthographic projections on the substrate have overlapping regions.
  • the first electrode plate 24 simultaneously serves as the gate electrode of the third transistor T3.
  • a region where the first scan signal line 21 overlaps with the fourth active layer of the fourth transistor T4 serves as a gate electrode of the fourth transistor T4.
  • the first scanning signal line 21 is provided with a gate block 21-1 protruding toward the side of the second scanning signal line 22, the orthographic projection of the gate block 21-1 on the substrate and the second active layer of the second transistor T2
  • the orthographic projection on the substrate has an overlapping area, and the overlapping area of the first scanning signal line 21 and the gate block 21-1 with the second active layer of the second transistor T2 serves as the gate electrode of the double gate structure of the second transistor T2.
  • the region where the second scan signal line 22 and the first active layer of the first transistor T1 overlap serves as the gate electrode of the double gate structure of the first transistor T1, and the second scan signal line 22 and the seventh active layer of the seventh transistor T7
  • the overlapping area serves as the gate electrode of the seventh transistor T7
  • the area where the light emission control line 23 and the fifth active layer of the fifth transistor T5 overlap serve as the gate electrode of the fifth transistor T5
  • the light emission control line 23 and the sixth transistor T6 The overlapping region of the sixth active layers serves as the gate electrode of the sixth transistor T6.
  • the first conductive layer can be used as a shield to conduct conductorization processing on the semiconductor layer, and the semiconductor layers in the region shielded by the first conductive layer form the first transistors T1 to T7 In the channel region of the transistor T7, the semiconductor layer in the region not shielded by the first conductive layer is conductive, that is, the first region and the second region from the first active layer to the seventh active layer are all conductive.
  • the display substrate includes a first insulating layer 91 disposed on the substrate 10, a semiconductor layer disposed on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a second insulating layer 92 disposed on the substrate 10.
  • the first conductive layer on the second insulating layer 92, the semiconductor layer may include the first active layer 11 and the third active layer 13, the first conductive layer may include the first scan signal line 21, the second scan signal line 22, The light emission control line 23 and the first plate 24 of the storage capacitor.
  • a second conductive layer pattern is formed.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film using a patterning process to form A third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93, the second conductive layer pattern at least includes: the initial signal line 31, the second electrode plate 32 of the storage capacitor, The shielding electrode 33 and the electrode plate connecting line 35 are as described in Fig. 23a and Fig. 23b, and Fig. 23b is a cross-sectional view taken along the line A-A in Fig. 23a.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the initial signal line 31 extends along the second direction D2, is disposed in the first region R1, and is located on the side of the second scan signal line 22 away from the second region R2.
  • the second electrode plate 32 of the storage capacitor is disposed in the second region R2 between the first scan signal line 21 and the light emission control line 23 .
  • the shielding electrode 33 is disposed in the first region R1, and is configured to shield the influence of the data voltage jump on the key nodes, so as to prevent the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit and improve the display effect.
  • the initial signal lines 31 may be provided with unequal widths, and the width of the initial signal lines 31 is the size of the first direction D1 of the initial signal lines 31 .
  • the initial signal line 31 includes a region overlapping with the semiconductor layer and a region not overlapping with the semiconductor layer.
  • the width of the initial signal line 31 in the region not overlapping with the semiconductor layer may be smaller than the width of the initial signal line 31 in the region overlapping with the semiconductor layer. width.
  • the outline of the second electrode plate 32 may be rectangular, the corners of the rectangular shape may be chamfered, and the orthographic projection of the second electrode plate 32 on the substrate is the same as that of the first electrode plate 24 on the substrate. Orthographic projections have overlapping areas.
  • the second pole plate 32 is provided with an opening 34, and the opening 34 may be located in the middle of the second region R2.
  • the opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure.
  • the opening 34 exposes the third insulating layer 93 covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate.
  • the opening 34 is configured to accommodate a subsequently formed first via hole, and the first via hole is located in the opening 34 and exposes the first electrode plate 24 so that the second electrode of the subsequently formed first transistor T1 connected to the first pole plate 24 .
  • the electrode plate connecting line 35 is disposed between the second electrode plates 32 of adjacent sub-pixels in the second direction D2, and the first end of the electrode plate connecting line 35 is connected to the second electrode plate 32 of this sub-pixel. connection, the second end of the plate connecting line 35 extends along the second direction D2 or the opposite direction of the second direction D2, and is connected with the second plate 32 of the adjacent sub-pixel, that is, the plate connecting line 35 is configured to make The second electrode plates of adjacent sub-pixels in the second direction D2 are connected to each other.
  • the second electrode plates in a sub-pixel row are formed into an integral structure connected to each other through the electrode plate connecting lines 35, and the second electrode plates of the integral structure can be reused as power supply signal lines to ensure that one sub-pixel
  • the plurality of second electrode plates in the pixel row have the same potential, which is beneficial to improve the uniformity of the panel, avoid poor display of the display substrate, and ensure the display effect of the display substrate.
  • the orthographic projection of the edge of the second electrode plate 32 adjacent to the first region R1 on the substrate overlaps with the orthographic projection of the boundary line of the first region R1 and the second region R2 on the substrate, and the second electrode plate
  • the orthographic projection of the edge of 32 adjacent to the third region R3 on the substrate overlaps with the orthographic projection of the boundary line of the second region R2 and the third region R3 on the substrate, that is, the length of the second polar plate 32 is equal to the length of the second region R2
  • the length of the second pole plate 32 refers to the dimension of the second pole plate 32 in the second direction D2.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the second conductive layer at least includes the initial signal line 31 and the second plate of the storage capacitor 32
  • the second pole plate 32 of the storage capacitor is provided with an opening 34
  • the opening 34 exposes the third insulating layer 93 covering the first pole plate 24, the orthographic projection of the second pole plate 32 on the substrate and the first pole plate 24
  • the orthographic projections on the substrate have overlapping regions.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • the fourth insulating layer, the fourth insulating layer is provided with a plurality of vias, and the plurality of vias at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via
  • the via hole V5 , the sixth via hole V6 , the seventh via hole V7 , the eighth via hole V8 and the ninth via hole V9 are shown in FIGS. 24 a and 24 b
  • FIG. 24 b is a cross-sectional view taken along the line A-A in FIG. 24 a .
  • the first via hole V1 is located in the opening 34 of the second electrode plate 32, and the orthographic projection of the first via hole V1 on the substrate is located at the position of the orthographic projection of the opening 34 on the substrate.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 24 .
  • the first via hole V1 is configured so that the second electrode of the first transistor T1 formed subsequently is connected to the first electrode plate 24 through the via hole.
  • the second via hole V2 is located in the region where the second electrode plate 32 is located, and the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second electrode plate 32 on the substrate.
  • the fourth insulating layer in the two via holes V2 is etched away, exposing the surface of the second electrode plate 32 .
  • the second via hole V2 is configured so that the subsequently formed first power line is connected to the second electrode plate 32 through the via hole.
  • a plurality of second vias V2 serving as power vias may be included, and the plurality of second vias V2 may be arranged in sequence along the first direction D1, adding a first power line and a second electrode plate 32 connection reliability.
  • the third via hole V3 is located in the third region R3, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the fifth active the surface of the first region of the layer.
  • the third via hole V3 is configured so that the first power supply line formed later is connected to the fifth active layer through the via hole.
  • the fourth via V4 is located in the third region R3, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched away, exposing the sixth active The surface of the second region of the layer (which is also the second region of the seventh active layer).
  • the fourth via hole V4 is configured so that the second electrode of the sixth transistor T6 formed subsequently is connected to the sixth active layer through the via hole, and the second electrode of the seventh transistor T7 formed subsequently is connected to the sixth active layer through the via hole. Seven active layer connections.
  • the fifth via V5 is located in the first region R1, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via V5 are etched away, exposing the fourth active the surface of the first region of the layer.
  • the fifth via hole V5 is configured to connect the data line formed subsequently to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.
  • the sixth via hole V6 is located in the first region R1, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the first active The surface of the second region of the layer (which is also the first region of the second active layer).
  • the sixth via hole V6 is configured so that the second electrode of the first transistor T1 formed subsequently is connected to the first active layer through the via hole, and the first electrode of the second transistor T2 formed subsequently is connected to the first active layer through the via hole. Two active layers are connected.
  • the seventh via hole V7 is located in the first region R1, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away, exposing the seventh active The surface of the first region of the layer (which is also the first region of the first active layer).
  • the seventh via hole V7 is configured so that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • An active layer connection is configured so that the first electrode of the subsequently formed seventh transistor T7 is connected to the seventh active layer through the via hole, and the first electrode of the subsequently formed first transistor T1 is connected to the seventh active layer through the via hole.
  • the eighth via hole V8 is located in the first region R1 , and the fourth insulating layer in the eighth via hole V8 is etched away to expose the surface of the shield electrode 33 .
  • the eighth via hole V8 is configured so that the first power supply line formed later is connected to the shield electrode 33 through the via hole.
  • the ninth via hole V9 is located in the first region R1 , and the fourth insulating layer in the ninth via hole V9 is etched away to expose the surface of the initial signal line 31 .
  • the ninth via hole V9 is configured so that the first electrode of the seventh transistor T7 (which is also the first electrode of the first transistor T1 ) to be formed subsequently is connected to the initial signal line 31 through the via hole.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is provided on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the fourth insulating layer 94 is provided
  • the plurality of via holes include at least a first via hole V1 and a sixth via hole V6.
  • the fourth insulating layer 94 and the third insulating layer 93 in the first via hole V1 are etched away, exposing the surface of the second electrode plate 32 .
  • the fourth insulating layer 94 , the third insulating layer 93 and the second insulating layer 92 in the sixth via hole V6 are etched away, exposing the surface of the first active layer 11 .
  • a third conductive layer pattern is formed.
  • forming the third conductive layer may include: depositing a third metal thin film on the substrate on which the aforementioned patterns are formed, patterning the third metal thin film by a patterning process, and forming a third metal thin film disposed on the fourth insulating layer
  • the third conductive layer, the third conductive layer at least includes: a first power line 41, a data line 42, a first connection electrode 43, a second connection electrode 44 and a third connection electrode 45, as shown in Figure 25a and Figure 25b, Figure 25b is a cross-sectional view taken along the line A-A in Figure 25a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the first power line 41 extends along the first direction D1.
  • the first power line 41 is connected to the second electrode plate 32 through the second via V2
  • the shield electrode 33 is connected to the shield electrode 33 through the eighth via hole V8 , and is connected to the fifth active layer through the third via hole V3 , so that the shield electrode 33 and the second electrode plate 32 have the same potential as the first power line 41 .
  • the shielding electrode 33 on the substrate and the orthographic projection of the subsequently formed data line on the substrate have an overlapping area, and the shielding electrode 33 is connected to the first power line 41 , the influence of the data voltage jump on key nodes is effectively shielded , avoiding the data voltage jump to affect the potential of the key node of the pixel driving circuit, and improving the display effect.
  • the data line 42 extends along the first direction D1, and the data line 42 is connected to the first region of the fourth active layer through the fifth via hole V5, so that the data signal transmitted by the data line 42 is written into the first region of the fourth active layer.
  • Four transistors T4 are transistors T4.
  • the first connection electrode 43 extends along the first direction D1, and the first end of the first connection electrode 43 passes through the sixth via hole V6 and the second region of the first active layer (which is also the second region of the second active layer). One area) connection, and its second end is connected to the first electrode plate 24 through the first via V1, so that the first electrode plate 24, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 43 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • the second connection electrode 44 extends along the first direction D1, the first end thereof is connected to the initial signal line 31 through the ninth via hole V9, and the second end thereof is connected to the seventh via hole V7 through the seventh via hole V9.
  • the first region of the active layer (which is also the first region of the first active layer) is connected so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the initial signal line 31 .
  • the second connection electrode 44 may serve as the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1.
  • the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second region of the sixth transistor T6 The pole and the second pole of the seventh transistor T7 have the same potential.
  • the third connection electrode 45 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the third connection electrode 45 is configured to be connected to a subsequently formed anode.
  • the first power line 41 and the data line 42 may be straight lines of equal width, or straight lines of unequal width.
  • the first insulating layer 91 is provided on the substrate 10
  • the semiconductor layer is provided on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is provided On the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the third conductive layer is disposed on the third insulating layer 93.
  • the third conductive layer includes at least a first connection electrode 43 and a third connection electrode 45, and the first connection electrode 43 is connected to the first electrode plate 24 and the first electrode plate 24 and the first electrode plate 43 through the first via hole V1 and the sixth via hole V6 respectively.
  • the first active layer 11 of a transistor T1 is connected.
  • a fourth conductive layer pattern is formed.
  • forming the fourth conductive layer pattern may include: sequentially depositing a fifth insulating film and a fourth metal film on the substrate on which the foregoing pattern is formed, and patterning the fourth metal film using a patterning process to form A fifth insulating layer 95 covering the third conductive layer, and a fourth conductive layer pattern disposed on the fifth insulating layer 95, the fourth conductive layer pattern at least includes: a data fan-out line 700 and a fourth connection electrode 52, as shown in FIG. 26a As described in Figure 16b, Figure 26b is a cross-sectional view taken along the line A-A in Figure 26a.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fifth insulating layer 95 is provided with a tenth via hole (not shown in the figure), the tenth via hole exposes the surface of the third connection electrode 45 , and the fourth connection electrode 52 passes through the tenth via hole. The hole is connected to the third connection electrode 45 .
  • the orthographic projection of the data fan-out line 700 on the substrate is located in any one or more of the following: the first power line 41 , the pad connection line 35 and the initial signal line 31 , the range of the orthographic projection on the substrate within.
  • the data fan-out line 700 overlap with some fixed-potential signal lines (the first power supply line 41, the plate connecting line 35, the initial signal line 31, etc.), the data fan-out line can be avoided when the data signal is written.
  • the potential change on 700 causes potential jumps of other signal lines in the pixel circuit, so that the display quality can be improved.
  • the orthographic projection of the data fan-out line 700 on the substrate is within the range of the orthographic projection of the first power line 41 and/or the plate connecting line 35 on the substrate.
  • the plate connecting line 35 is connected to the first power line 41 , the voltage in the first power line 41 is a constant positive voltage, and the range of the data voltage is also generally a positive voltage. Therefore, the data fanout line 700 is connected to the first power line 41 The potential difference of (or the plate connecting line 35 ) is relatively small, and the load is relatively small when the data signal is written, thereby further reducing the signal crosstalk between the data fan-out line and other signal lines.
  • a flat layer pattern is formed.
  • forming the flattening layer pattern may include: coating a flattening film on the substrate on which the aforementioned pattern is formed, patterning the flattening film by a patterning process, forming a flattening layer covering the third conductive layer, and the flattening layer
  • An eleventh via hole V11 is provided on the top, as shown in FIG. 27a and FIG. 27b
  • FIG. 27b is a cross-sectional view taken along A-A in FIG. 27a .
  • the tenth via hole V10 is located in the area where the fourth connection electrode 52 is located, the flat layer in the eleventh via hole V11 is removed, and the surface of the fourth connection electrode 52 is exposed, and the eleventh via hole V11 is configured In order to connect the anode to be formed subsequently to the fourth connection electrode 52 through the via hole.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed On the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the third conductive layer is disposed on the third insulating layer 93.
  • the fifth insulating layer 95 covers the third conductive layer
  • the fourth conductive layer is disposed on the fifth insulating layer 95
  • the flat layer 96 covers the fourth conductive layer
  • the eleventh via V11 is disposed on the flat layer
  • the flat layer 95 in the eleventh via V11 is removed, exposing the surface of the fourth connection electrode 52 .
  • An anode pattern is formed.
  • forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, and patterning the transparent conductive film by a patterning process to form an anode 71 disposed on the flat layer, as shown in FIG. 28a and 28b, and Fig. 28b is a cross-sectional view taken along the line A-A in Fig. 28a.
  • the anode 71 may be in a hexagonal shape, and the anode 71 is connected to the fourth connection electrode 52 through the eleventh via V11. Since the fourth connection electrode 52 and the third connection electrode 45 are connected through the tenth via hole, the third connection electrode 45 serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, so the anode 71 is connected to the sixth transistor T7. T6 is connected to the seventh transistor T7, so that the pixel driving circuit can drive the light-emitting device to emit light.
  • the first insulating layer 91 is disposed on the substrate 10
  • the semiconductor layer is disposed on the first insulating layer 91
  • the second insulating layer 92 covers the semiconductor layer
  • the first conductive layer is disposed On the second insulating layer 92
  • the third insulating layer 93 covers the first conductive layer
  • the second conductive layer is disposed on the third insulating layer 93
  • the fourth insulating layer 94 covers the second conductive layer
  • the third conductive layer is disposed on the third insulating layer 93.
  • the fifth insulating layer 95 covers the third conductive layer
  • the fourth conductive layer is disposed on the fifth insulating layer 95
  • the flat layer 96 covers the fourth conductive layer
  • the anode 71 is disposed on the flat layer 96
  • the anode 71 It is connected to the fourth connection electrode 52 through the eleventh via hole.
  • the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening is The anode is exposed.
  • the organic light-emitting layer is formed by vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of organic materials, and the third encapsulation layer can be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light emitting structure layer.
  • the substrate may be a flexible substrate, or it may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, the first flexible material layer and the second flexible material layer
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, etc.
  • the material of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo Wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) One or more, it can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer.
  • the flat layer can be made of organic materials, and the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO.
  • the active layer may use polysilicon (p-Si), that is, the present disclosure is applicable to LTPS thin film transistors.
  • the exemplary embodiment shown in FIG. 28b is described by taking the data line disposed in the third conductive layer and the data fan-out line disposed in the fourth conductive layer as an example, in the present disclosure, the data fan-out line and the data line may be disposed in any layer , as long as it is ensured that the data line and the data fan-out line are located in different conductive layers, which is not limited in the present disclosure.
  • the structure of the display substrate and the preparation process thereof shown in the present disclosure are merely exemplary descriptions.
  • corresponding structures may be changed and patterning processes may be added or decreased according to actual needs, which are not limited in the present disclosure.
  • the binding area is provided with a fan-out area, and the data lines of the display area are drawn out through the data fan-out lines of the fan-out area. Since there are many oblique lines in the fan-shaped area, the lower frame is wider, which is not conducive to the realization of Narrow borders.
  • lead lines are set in the lead area of the binding area, and data fan-out lines are set in the display area, and the lead lines are connected to the corresponding data lines through the data fan-out lines, which not only realizes that multiple lead lines and
  • the corresponding connection of multiple data lines makes it unnecessary to set a fan-shaped oblique line in the lead area, and the multiple lead lines are vertical lines parallel to each other, which can be directly introduced into the composite circuit area of the binding area, effectively reducing the need for
  • the vertical length of the lead area greatly reduces the width of the lower frame, so that the widths of the upper frame, lower frame, left frame and right frame of the display device are similar, all of which are less than 1.0mm, which increases the screen ratio and facilitates the realization of a comprehensive screen is displayed.
  • the data fan-out line 700 overlap with some fixed-potential signal lines (the first power line 41 , the plate connecting line 35 and the initial signal line 31 , etc.)
  • the potential change on the fan-out line 700 causes the potential jump of other signal lines in the pixel circuit, thereby further improving the display quality.
  • FIG. 29 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • the display area 100 includes a plurality of plate connecting lines 35 and initial signal lines 31 , and the plurality of plate connecting lines 35 and the initial signal lines 31 have a second angle ⁇ 2 with the first direction D1, and the second clamping
  • the angle ⁇ 2 may be approximately greater than 0° and less than 90°.
  • the second included angle ⁇ 2 may be about 20° to 70°.
  • the length of the data fan-out line located above the pad connection line 35 and the initial signal line 31 can be reduced by slanting the pad connection line 35 and the initial signal line 31 .
  • the plate connecting line 35 and the initial signal line 31 are arranged in the same layer as the second gate metal layer, the plate connecting line 35 and the initial signal line 31 are arranged obliquely and do not affect other film layer signal lines. (For example, the arrangement of scan signal lines, light-emitting control lines, reset signal lines, first power lines, data lines, etc.).
  • the exemplary embodiments of the present disclosure can achieve the technical effects of the foregoing embodiments, including effectively reducing the width of the lower frame, and effectively improving the display uniformity and display quality.
  • the present disclosure effectively reduces the length of the data fan-out lines above the plate connecting line 35 and the initial signal line 31 by slanting the plate connecting line 35 and the initial signal line 31 , which is beneficial to reduce the difficulty of wiring design.
  • the film layer structures of the data lines, the data fan-out lines, and the lead-out lines may be similar to those in the foregoing exemplary embodiment, and will not be repeated here.
  • Exemplary embodiments of the present disclosure also provide a method of fabricating a display substrate.
  • the display substrate includes a display area and a binding area on one side of the display area, and the binding area at least includes a lead area; the preparation method may include:
  • a plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead area; at least one lead-out line is connected to the data line through the data fan-out line; In the plane of the An insulating layer is provided between the layer and the third conductive layer, the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are provided in different conductive layers.
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments.
  • the display device can be: mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, advertising panel, watch phone, e-book portable multimedia player or display screen of various products of the Internet of Things, etc. products or parts.
  • the display device may be a wearable display device, which can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。

Description

显示基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；
在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
在示例性实施例中，所述至少一条数据扇出线包括第一线段和第二线段；所述第一线段的第一端与所述引出线连接，所述第一线段的第二端向着远离引线区的方向延伸后，与所述第二线段的第一端连接；所述第二线段的第二端向着靠近引线区的方向延伸后，通过过孔与所述数据线连接。
在示例性实施例中，所述第一线段与第一方向平行，所述第二线段与所述第一方向之间具有第一夹角，所述第一夹角为20°至70°。
在示例性实施例中，所述第二线段包括伸出段和连接段；所述伸出段的第一端位于所述显示区域内，与所述第一线段的第二端连接，所述伸出段的第二端向着靠近引线区的方向延伸到显示区域边缘后，与所述连接段的第一端连接，所述连接段的第二端向着远离显示区域的方向延伸后，通过过孔与延伸到引线区的数据线连接；所述显示区域边缘是显示区域靠近引线区一侧的边缘。
在示例性实施例中，所述显示区域还包括第一电源线和极板连接线，所述第一电源线沿第一方向延伸，所述极板连接线沿第二方向延伸；所述第二方向与所述第一方向交叉；
所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与所述极板连接线在显示基板平面上的正投影重叠。
在示例性实施例中，所述显示区域还包括第一电源线和极板连接线，所述第一电源线沿第一方向延伸，所述极板连接线与所述第一方向之间具有第二夹角，所述第二夹角为20°至70°；
所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与所述极板连接线在显示基板平面上的正投影重叠。
在示例性实施例中，所述极板连接线位于所述第二导电层中，所述第一 电源线位于所述第三导电层中，所述数据扇出线位于所述第四导电层中。
在示例性实施例中，所述显示区域还包括第一电源线、初始信号线和极板连接线，所述第一电源线沿第一方向延伸，所述初始信号线和极板连接线均沿第二方向延伸；所述第二方向与所述第一方向交叉；
所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与以下任意一个：所述初始信号线和所述极板连接线，在显示基板平面上的正投影重叠。
在示例性实施例中，所述显示区域还包括第一电源线、初始信号线和极板连接线，所述第一电源线沿第一方向延伸，所述初始信号线和极板连接线均与第一方向之间具有第二夹角，所述第二夹角为20°至70°；
所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与以下任意一个：所述初始信号线和所述极板连接线，在显示基板平面上的正投影重叠。
在示例性实施例中，所述初始信号线和极板连接线均位于所述第二导电层中，所述第一电源线位于所述第三导电层中，所述数据扇出线位于所述第四导电层中。
在示例性实施例中，所述引线区中的多条引出线沿第二方向的宽度相同，相邻引出线之间沿第二方向的间距相同。
在示例性实施例中，所述引线区的多条引出线包括第一引线组和第二引线组，所述第一引线组的引出线与所述第二引线组的引出线沿第二方向交替 设置；
所述第一引线组中的多条引出线通过多条所述数据扇出线与所述数据线对应连接，所述第二引线组中的多条引出线直接与所述数据线对应连接。
本公开实施例还提供了一种显示装置，包括如前任一项所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述制备方法包括：
在所述显示区域形成多条数据线和多条数据扇出线，在所述引线区形成多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7为一种显示基板中绑定区域的平面结构示意图；
图8为一种绑定区域中数据扇出线的示意图；
图9为本公开示例性实施例一种显示基板的平面结构示意图；
图10为图9中显示基板的侧视图；
图11为本公开示例性实施例一种引出线和数据扇出线的结构示意图；
图12为图11中C1区域的放大图；
图13为图12中C2区域的放大图；
图14为图13中A-A向的剖视图；
图15为本公开示例性实施例另一种引出线和数据扇出线的结构示意图；
图16为图15中C3区域的放大图；
图17为本公开示例性实施例又一种引出线和数据扇出线的结构示意图；
图18为图17中C4区域的放大图；
图19为本公开示例性实施例又一种引出线和数据扇出线的结构示意图；
图20为图19中C5区域的放大图；
图21a为本公开一种显示基板形成半导体层图案后的示意图；
图21b为图21a中A-A向的剖视图；
图22a为本公开一种显示基板形成第一导电层图案后的示意图；
图22b为图22a中A-A向的剖视图；
图23a为本公开一种显示基板形成第二导电层图案后的示意图；
图23b为图23a中A-A向的剖视图；
图24a为本公开一种显示基板形成第四绝缘层图案后的示意图；
图24b为图24a中A-A向的剖视图；
图25a为本公开一种显示基板形成第三导电层图案后的示意图；
图25b为图25a中A-A向的剖视图；
图26a为本公开一种显示基板形成第四导电层图案后的示意图；
图26b为图26a中A-A向的剖视图；
图27a为本公开一种显示基板形成平坦层图案后的示意图；
图27b为图27a中A-A向的剖视图；
图28a为本公开一种显示基板形成阳极图案后的示意图；
图28b为图28a中A-A向的剖视图；
图29为一种显示基板中显示区域的平面结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述， 而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层” 换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器、发光信号驱动器和像素阵列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据线(D1到Dn)、多个发光信号线(E1到Eo)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器，可以将适合于发光信号驱动器的规格的时钟信号、发射停止信号等提供到发光信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光信号驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光信号驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号，o可以是自然数。像素阵列可以包括多个子像素Pxij，每个子像素Pxij可以连接到对应的数据线、对应的扫描信号线和对应的发光信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据线的子像素。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。显示区域100可以包括配置为显示动态图片或静止图像的多个子像素，绑定区域200可以包括将多个数据线连接至集成电路的连接线和电路，边框区域300可以包括传输电压信号的电源线，绑定区域200和边框区域300可以包括环形结构的隔离坝，边框区域300的至少一侧可以是通过弯折形成的卷曲区域，或者，显示区域100和边框区域300均是弯折或弯曲的区域，本公开在此不做限定。
在示例性实施方式中，显示区域可以包括以矩阵方式排布的多个像素单元。图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的形状可以是矩形、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基 板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图4中仅以一个晶体管102A和一个存储电容102B作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。图5为一种像素驱动电路的等效电路示意图。如图5所示，像素驱动电路可以包括7个开关晶体管(第一晶体管T1到第七晶体管 T7)、1个存储电容C1和7个信号线(数据线DATA、第一扫描信号线S1、第二扫描信号线S2、初始信号线INIT、第一电源线VDD、第二电源线VSS和发光信号线EM)。
在示例性实施方式中，第一晶体管T1的栅电极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的栅电极与第二节点N2连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据线DATA连接，第四晶体管T4的第二极与第一节点N1连接。第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第七晶体管T7的栅电极与第二扫描信号线S2连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。存储电容C1的第一端与第一电源线VDD连接，存储电容C1的第二端与第二节点N2连接。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)， 本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1可以为同一信号线，以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM和初始信号线INIT沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据线DATA沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C1和7个信号线(数据线DATA、第一扫描信号线S1、第二扫描信号线S2、初始信号线INIT、第一电源线VDD、第二电源线VSS和发光信号线EM)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线EM的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C1进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线EM的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线EM的信号为高电平信号，数据线DATA输出数据电压。此阶段由于存储电容C1的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据线DATA输出的数据电压经过第一节点N1、 导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据线DATA输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C1，存储电容C1的第二端(第二节点N2)的电压为Vdata-|Vth|，Vdata为数据线DATA输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线EM的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vdata+|Vth|)-Vth] 2＝K*[(Vdd-Vdata] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据线DATA输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图7为一种显示基板中绑定区域的平面结构示意图，图8为一种绑定区域中数据扇出线的示意图。如图7所示，在平行于显示基板的平面内，绑定区域200位于显示区域100的一侧，绑定区域200可以包括沿着远离显示区域100的方向依次设置的第一扇出区201、弯折区202、第二扇出区203、防静电区204、驱动芯片区205和绑定引脚区206。第一扇出区201至少包括数据扇出线，多条数据扇出线被配置为以扇出(Fanout)走线方式连接显示区 域的数据线(Data Line)，如图8所示。弯折区202包括设置有凹槽的复合绝缘层，被配置为使绑定区域200弯折到显示区域100的背面。第二扇出区203包括以扇出走线方式引出的多条数据扇出线。防静电区204包括防静电电路，被配置为通过消除静电防止显示基板的静电损伤。驱动芯片区205包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区206包括绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。目前，显示装置的左边框、右边框和上边框可以控制在1.0mm以内，但下边框(绑定区域一侧的边框)的窄化设计难度较大，一直维持在2.0mm左右。这是因为数据扇出线通常设置在绑定区域的扇出区，而扇形区占用空间较大。通常，绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，则下边框就越宽，导致下边框比左边框和右边框大很多。
本公开示例性实施例提供了一种显示基板。显示基板可以包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
图9为本公开示例性实施例一种显示基板的平面结构示意图，图10为图9中显示基板的侧视图。如图9和图10所示，显示基板10可以包括显示区域100、位于显示区域100一侧的绑定区域500以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦化区域， 包括组成像素阵列的多个子像素Pxij、多条数据线和多条数据扇出线，多个子像素Pxij配置为显示动态图片或静止图像，多条数据线配置为向多个子像素Pxij提供数据信号，多条数据扇出线与多条数据线对应连接，配置为使多条数据线与绑定区域500中的多条引出线对应连接。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域500可以包括沿着第一方向D1的反方向(远离显示区域方向)依次设置的引线区501、弯折区502和复合电路区503，引线区501连接到显示区域100，弯折区502连接到引线区501，复合电路区503连接到弯折区502。
在示例性实施方式中，引线区501可以设置多条引出线，一部分多条引出线的一端与显示区域100中的多条数据扇出线对应连接，另一部分多条引出线的一端与显示区域100中的多条数据线对应连接，多条引出线的另一端跨过弯折区502连接复合电路区503的集成电路，使得集成电路通过引出线和数据扇出线将数据信号施加到数据线。
在示例性实施方式中，弯折区502可以在第三方向D3上以一曲率弯曲，可以将复合电路区503的表面反转，即复合电路区503朝向上方的表面可以通过弯折区502的弯曲转换成面朝向下方，第三方向D3与第一方向D1交叉。在示例性实施方式中，当弯折区502被弯曲时，复合电路区503可以在第三方向D3(厚度方向)上与显示区域100重叠。
在示例性实施方式中，复合电路区503可以包括防静电区、驱动芯片区和绑定引脚区，集成电路(Integrate Circuit，简称IC)20可以绑定连接在驱动芯片区，柔性电路板(Flexible Printed Circuit，简称FPC)30可以绑定连接在绑定引脚区。在示例性实施方式中，集成电路20可以产生用于驱动子像素所需的驱动信号，并且可以将驱动信号提供给在显示区域100中的子像素。例如，驱动信号可以是驱动子像素发光亮度的数据信号。在示例性实施方式中，集成电路20可以通过各向异性导电膜或者其它方式绑定连接在驱动芯片区，集成电路20在第二方向D2上的宽度可以小于复合电路区503在第二方向D2上的宽度，第二方向D2与第一方向D1交叉。在示例性实施方式中， 绑定引脚区可以设置包括多个引脚(PIN)的焊盘，柔性电路板30可以绑定连接到焊盘上。
在示例性实施方式中，第一方向D1可以是显示区域中数据线的延伸方向(列方向)，第二方向D2可以是显示区域中扫描信号线的延伸方向(行方向)，第三方向D3可以是垂直于显示基板平面的方向，第一方向D1和第二方向D2可以相互垂直，第一方向D1和第三方向D3可以相互垂直。
图11为本公开示例性实施例一种引出线和数据扇出线的结构示意图。如图11所示，显示区域100可以包括以矩阵方式排布的多个子像素、多条数据线DA和多条数据扇出线700，绑定区域的引线区501可以包括多条引出线600。在示例性实施方式中，显示区域100中的多个子像素形成多个像素行和多个像素列，多条数据线DA沿着第一方向D1的反方向延伸，并沿着第二方向D2以设定的间隔顺序设置，每条数据线DA与显示区域100中一个像素列的所有子像素连接，每条数据线DA的端部延伸到绑定区域的引线区501。每条数据扇出线700的第一端与引线区501的一部分引出线600对应连接，每条数据扇出线700的第二端与延伸到引线区501的一部分数据线DA对应连接。引线区501中的一部分引出线600与数据扇出线700连接，另一部分引出线600与延伸到引线区501的另一部分数据线DA对应连接。
在示例性实施方式中，显示基板具有中心线O，中心线O沿着第一方向D1延伸并平分显示区域100的多个像素列，显示区域100中的多条数据线DA、多条数据扇出线700和绑定区域的引线区501中的多条引出线600可以相对于中心线O对称设置。在另一些示例性实施方式中，显示区域100中的多条数据线DA、多条数据扇出线700和绑定区域的引线区501中的多条引出线600也可以在中心线O两侧不对称设置，示例性的，显示区域100中的多条数据线DA、多条数据扇出线700和绑定区域的引线区501中的多条引出线600可以在中心线O两侧具有类似的设计。下面以显示基板左侧包括N条数据线、M条数据扇出线和N条引出线为例进行说明，N为大于2的正整数，M为大于2且小于N的正整数。
在示例性实施方式中，显示区域左侧的N条数据线可以包括按照编号大小划分为第一数据线组和第二数据线组。第一数据线组可以包括第一数据线 DA1、第二数据线DA2、……、第M数据线，第二数据线组可以包括第(M+1)数据线、第(M+2)数据线、……、第N数据线。
在示例性实施方式中，M可以为需要采用扇出方式引出的数据线的数量。例如，N为偶数时，M可以为N/2，N为奇数时，M可以为(N+1)/2，或者M可以为(N-1)/2。M可以根据实际情况设置，本公开在此不做限定。
在示例性实施方式中，第一数据线组的多条数据线按照编号递增的方式沿着第二方向D2依次设置，第二数据线组的多条数据线按照编号递增的方式沿着第二方向D2依次设置，且第二数据线组设置在第一数据线组第二方向D2的一侧。也就是说，N条数据线包括沿着第二方向D2依次设置的第一数据线DA1、第二数据线DA2、……、第N数据线DAN，即N条数据线的编号沿着第二方向D2依次递增。在示例性实施方式中，第i数据线可以是位于第i像素列的数据线，第i数据线与第i像素列中的子像素连接。
在示例性实施方式中，引线区501左侧的N条引出线可以包括按照编号大小划分为第一引线组和第二引线组。第一引线组可以包括第一引出线601、第二引出线602、……、第M引出线，第二引线组可以包括第(M+1)引出线、第(M+2)引出线、……、第N引出线。
在示例性实施方式中，第一引线组的多条引出线按照编号递增的方式沿着第二方向D2的反方向依次设置，第二引线组的多条引出线按照编号递增的方式沿着第二方向D2依次设置，且第一引线组的引出线与第二引线组的引出线交替设置。例如，第一引出线与第N引出线相邻，第二引出线与第N-1引出线相邻，……，第M引出线与第(M+1)引出线相邻。
在示例性实施方式中，第一引线组中的多条引出线可以通过多条数据扇出线与第一数据线组中的多条数据线对应连接，第二引线组中的多条引出线可以直接与第二数据线组中的多条数据线对应连接，引出线可以直接或通过数据扇出线将数据信号提供给数据线。
在示例性实施方式中，第i数据扇出线的第一端在显示区域边缘B附近位置与第一引线组中的第i引出线连接，第i数据扇出线的第二端先向着远离引线区501的方向延伸，然后返回到引线区501后，与延伸到引线区501 的第一数据线组中的第i数据线连接，i＝1，2，…….，M。在示例性实施方式中，显示区域边缘B是显示区域100靠近引线区501一侧的边缘。
在示例性实施方式中，第i数据扇出线可以包括依次连接的第一线段和第二线段，第一线段的第一端位于显示区域边缘B附近，与第i引出线连接，第一线段的第二端向着远离引线区的方向延伸后，与第二线段的第一端连接。第二线段的第二端向着引线区的方向从显示区域100延伸到引线区501后，与延伸到引线区501的第i数据线连接。
在示例性实施方式中，第二线段可以包括伸出段和连接段，伸出段的第一端位于显示区域100内，与第二线段的第二端连接，伸出段的第二端向着靠近引线区的方向延伸到显示区域边缘B后，与连接段的第一端连接，连接段的第二端向着远离显示区域的方向延伸后，通过过孔与延伸到引线区的第i数据线连接。
在示例性实施方式中，连接段可以是折线段，包括与第一方向D1平行的竖线段和与第二方向D2平行的横线段。
在示例性实施方式中，第一数据线组和第二数据线组中的多条数据线可以设置成均与第一方向D1平行，第一引线组和第二引线组中的多条引出线可以设置成均与第一方向D1平行，即引出线与数据线平行。
在示例性实施方式中，第二数据线组中的多条数据线第一方向D1的延长线可以与第二引线组中的多条引出线对应重叠。
在示例性实施方式中，多条数据扇出线的第一线段可以设置成均与第一方向D1平行，多条数据扇出线的第二线段可以设置成均与第一方向D1具有第一夹角θ1，第一夹角θ1可以约为大于0°，小于90°。
在示例性实施方式中，第一夹角θ1可以约为20°至70°，第一夹角θ1和第二夹角θ2可以相同，或者可以不同。
在示例性实施方式中，至少一条第一线段设置在相邻的数据线之间。
在示例性实施方式中，第k数据扇出线的多个线段可以形成三角形走线，第k数据扇出线形成的三角形走线套设在第k-1数据扇出线形成的三角形走 线内，形成三角形嵌套结构，第k-1数据扇出线的第二线段的第一端与显示区域边缘B的距离大于第k数据扇出线的第二线段的第一端与显示区域边缘B的距离，第k-1数据扇出线中第一线段与第二线段的第二端之间的距离大于第k数据扇出线中第一线段与第二线段的第二端之间的距离，k＝2，…….，M。
图12为图11中C1区域的放大图，示意了N＝8时引出线和数据扇出线的结构。图12所示，多条数据线可以包括沿着第二方向D2依次设置的第一数据线DA1、第二数据线DA2、第三数据线DA3、第四数据线DA4、第五数据线DA5、第六数据线DA6、第七数据线DA7和第八数据线DA8，绑定区域的引线区501的多条引出线可以包括沿着第二方向D2的反方向依次设置的第一引出线601、第八引出线608、第二引出线602、第七引出线607、第三引出线603、第六引出线606、第四引出线604和第五引出线605。
在示例性实施方式中，第一数据扇出线701的第一端在显示区域边缘B附近与第一引出线601连接，第二端延伸到显示区域100的第一数据线DA1附近，然后从显示区域100延伸到引线区501与第一数据线DA1连接。第二数据扇出线702的第一端在显示区域边缘B附近与第二引出线602连接，第二端延伸到显示区域100的第二数据线DA2附近，然后从显示区域100延伸到引线区501与第二数据线DA2连接。第三数据扇出线703的第一端在显示区域边缘B附近与第三引出线603连接，第二端延伸到显示区域100的第三数据线DA3附近，然后从显示区域100延伸到引线区501与第三数据线DA3连接。第四数据扇出线704的第一端在显示区域边缘B附近与第四引出线604连接，第二端延伸到显示区域100的第四数据线DA4附近，然后从显示区域100延伸到引线区501与第四数据线DA4连接。
在示例性实施方式中，延伸到引线区501的第五数据线DA5与第五引出线605直接连接，延伸到引线区501的第六数据线DA6与第六引出线606直接连接，延伸到引线区501的第七数据线DA7与第七引出线607直接连接，延伸到引线区501的第八数据线DA8与第八引出线608直接连接。
虽然图12所示示例性实施例以数据扇出线的第二线段位于对应数据线的右侧为例进行了说明，但本公开中，数据扇出线的第二线段可以位于对应 数据线的左侧，或者一部分第二线段位于数据线的右侧，另一部分第二线段位于数据线的左侧，本公开在此不做限定。
图13为图12中C2区域的放大图。图13所示，第三数据线DA3、第四数据线DA4、第五数据线DA5和第六数据线DA6分别沿着第一方向D1延伸到绑定区域的引线区501。在引线区501，第三数据扇出线703先延伸到显示区域100的第三数据线DA3附近，然后从显示区域100延伸到引线区501，并通过第一过孔K1与第三数据线DA3的端部连接。第四数据扇出线704先延伸到显示区域100的第四数据线DA4附近，然后从显示区域100延伸到引线区501，通过第二过孔K2与第四数据线DA4的端部连接。第五引出线605通过第三过孔K3与第五数据线DA5的端部连接，第六连接信号线606通过第四过孔K4与第六数据线DA6的端部连接。
在示例性实施方式中，数据线和数据扇出线可以设置在不同的膜层中，且数据线与数据扇出线之间设置有绝缘层。
在示例性实施方式中，引出线和数据扇出线可以设置在相同的膜层中，且通过同一次图案化工艺同时形成，引出线和数据扇出线可以是相互连接的一体结构。
在示例性实施方式中，引出线和数据扇出线可以设置在不同的膜层中，两者之间设置有绝缘层，两者通过过孔实现连接。
图14为图13中A-A向的剖视图。图14所示，在垂直于显示基板的平面内，显示基板可以包括设置在基底上的多个导电层，多个导电层可以包括沿着远离基底方向依次设置的第一导电层、第二导电层、第三导电层和第四导电层，第一导电层(图中未示出)可以包括扫描信号线、多个晶体管的栅电极、发光控制线和存储电容的第一极板，第二导电层(图中未示出)可以包括初始信号线、极板连接线和存储电容的第二极板，第三导电层可以包括：第一电源线(图中未示出)、数据线、多个晶体管的源电极和漏电极(图中未示出)，第四导电层可以包括：数据扇出线。
在示例性实施方式中，在垂直于显示基板的平面内，显示基板可以包括半导体层和多个绝缘层，半导体层可以包括多个晶体管的有源层，多个绝缘 层可以包括沿着远离基底方向依次设置的第一绝缘层91、第二绝缘层92、第三绝缘层93、第四绝缘层94和第五绝缘层95。在示例性实施方式中，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91远离基底的一侧，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92远离基底的一侧，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93远离基底的一侧，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94远离基底的一侧，第五绝缘层95覆盖第三导电层，第四导电层设置在第五绝缘层95远离基底的一侧。
在示例性实施方式中，任意一条引出线在基底上的正投影与其它引出线在基底上的正投影没有重叠区域，任意一条数据扇出线在基底上的正投影与其它数据扇出线在基底上的正投影没有重叠区域。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，配置为防止离子的杂质扩散，防止水分渗透，并且执行表面平坦化功能，设置在半导体层和第一导电层之间的第二绝缘层、设置在第一导电层和第二导电层之间的第三绝缘层可以称为栅绝缘(GI)层，设置在第二导电层和第三导电层之间的第四绝缘层可称之为层间绝缘(ILD)层。第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或者上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。基于氧化物技术的有源层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。
在示例性实施方式中，第五绝缘层95上可以开设有多个开孔(图中的 K1至K4)，多个开孔位于数据线的端部，开孔内的第五绝缘层95被刻蚀掉，暴露出数据线的表面。开孔配置为使后续形成的数据扇出线或引出线通过该开孔与数据线对应连接。
在示例性实施方式中，如图13和图14所示，每条引出线的宽度M均相同，相邻引出线之间的间距L均相同，宽度M和间距L均是第二方向D2的尺寸。在示例性实施方式中，每条数据扇出线的宽度可以相同。
在示例性实施方式中，图15为本公开实施例另一种引出线和数据扇出线的结构示意图，图16为图15中C3区域的放大图，如图15和图16所示，显示区域还包括第一电源线VDD和极板连接线35，第一电源线VDD沿第一方向D1延伸，极板连接线35沿第二方向D2延伸；
伸出段700b包括M1个第一子线段700b1和M1个第二子线段700b2，M1为大于或等于1的自然数，第一子线段700b1和第二子线段700b2交替连接，位于伸出段700b一侧的第一子线段700b1与第一线段700a连接，位于伸出段700b另一侧的第二子线段700b2与连接段700c连接，第一线段700a和第二子线段700b2在显示基板平面上的正投影均与第一电源线VDD在显示基板平面上的正投影重叠，第一子线段700b1在显示基板平面上的正投影与极板连接线35在显示基板平面上的正投影重叠。
在示例性实施方式中，图17为本公开实施例又一种引出线和数据扇出线的结构示意图，图18为图17中C4区域的放大图，如图17和图18所示，显示区域还包括第一电源线VDD和极板连接线35，第一电源线VDD沿第一方向D1延伸，极板连接线35与第一方向D1之间具有第二夹角θ2，第二夹角θ2为20°至70°；
伸出段700b包括M1个第一子线段700b1和M1个第二子线段700b2，M1为大于或等于1的自然数，第一子线段700b1和第二子线段700b2交替连接，位于伸出段700b一侧的第一子线段700b1与第一线段700a连接，位于伸出段700b另一侧的第二子线段700b2与连接段700c连接，第一线段700a和第二子线段700b2在显示基板平面上的正投影均与第一电源线VDD在显示基板平面上的正投影重叠，第一子线段700b1在显示基板平面上的正投影 与极板连接线35在显示基板平面上的正投影重叠。
在示例性实施方式中，极板连接线35位于第二导电层中，第一电源线VDD位于第三导电层中，数据扇出线700位于第四导电层中。
在示例性实施方式中，图19为本公开实施例又一种引出线和数据扇出线的结构示意图，图20为图19中C5区域的放大图，如图19和图20所示，显示区域还包括第一电源线VDD、初始信号线31和极板连接线35，第一电源线VDD沿第一方向D1延伸，初始信号线31和极板连接线35均沿第二方向D2延伸；
伸出段700b包括M1个第一子线段700b1和M1个第二子线段700b2，M1为大于或等于1的自然数，第一子线段700b1和所述第二子线段700b2交替连接，位于伸出段700b一侧的第一子线段700b1与第一线段700a连接，位于伸出段700b另一侧的第二子线段700b2与连接段700c连接，第一线段700a和第二子线段700b2在显示基板平面上的正投影均与第一电源线VDD在显示基板平面上的正投影重叠，第一子线段700b1在显示基板平面上的正投影与以下任意一个：初始信号线31和极板连接线35，在显示基板平面上的正投影重叠。
在示例性实施方式中，显示区域还包括第一电源线VDD、初始信号线和极板连接线35，第一电源线VDD沿第一方向D1延伸，初始信号线31和极板连接线35均与第一方向D1之间具有第二夹角，所述第二夹角为20°至70°；
伸出段700b包括M1个第一子线段700b1和M1个第二子线段700b2，M1为大于或等于1的自然数，第一子线段700b1和第二子线段700b2交替连接，位于伸出段700b一侧的第一子线段700b1与第一线段700a连接，位于伸出段700b另一侧的第二子线段700b2与连接段700c连接，第一线段700a和第二子线段700b2在显示基板平面上的正投影均与第一电源线VDD在显示基板平面上的正投影重叠，第一子线段700b1在显示基板平面上的正投影与以下任意一个：初始信号线31和极板连接线35，在显示基板平面上的正投影重叠。
在示例性实施方式中，初始信号线31和极板连接线35均位于第二导电层中，第一电源线VDD位于第三导电层中，数据扇出线700位于第四导电层中。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板的制备过程可以包括如下操作。
(11)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图21a和图21b所示，图21b为图21a中A-A向的剖视图。
在示例性实施例中，每个子像素的半导体层可以包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第七有源层17为相互连接的一体结构。
在示例性实施例中，第一区域R1可以包括至少部分的第一晶体管T1的第一有源层11、第二晶体管T2的第二有源层12、第四晶体管T4的第四有 源层14和第七晶体管T7的第七有源层17，第二区域R2可以包括至少部分的第三晶体管T3的第三有源层13，第三区域R3可以包括至少部分的第五晶体管T5的第五有源层15和第六晶体管T6的第六有源层16。第一有源层11和第七有源层17设置在第一区域R1内远离第二区域R2的一侧，第二有源层12和第四有源层14设置在第一区域R1内邻近第二区域R2的一侧。
在示例性实施例中，第一有源层11的形状可以呈“n”字形，第二有源层12的形状可以呈“7”字形，第三有源层13的形状可以呈“几”字形，第四有源层14的形状可以呈“1”字形，第五有源层15、第六有源层16和第七有源层17的形状可以呈“L”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一区11-1同时作为第七有源层17的第一区17-1，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2。在示例性实施例中，第四有源层14的第一区14-1和第五有源层15的第一区15-1单独设置。
在示例性实施例中，第三晶体管的第三有源层13包括第一区13-1、第二区13-2和沟道区，第三有源层13的沟道区设置在第一区13-1和第二区13-2之间，且沟道区的两端分别与第一区13-1和第二区13-2连接。第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，即第三有源层13的第一区13-1、第四有源层14的第二区14-2和第五有源层15的第二区15-2之间相互连接。第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，即第三有源层13的第二区13-2、第二有源层12的第二区12-2和第六有源层16的第一区16-1之间相互连接。
如图21b所示，本次工艺后，显示基板包括设置在基底10上的第一绝缘层91和设置在第一绝缘层91上的半导体层，半导体层可以包括第一有源层 11和第三有源层13。
(12)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24，如图22a和图22b所示，图22b为图22a中A-A向的剖视图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE 1)层。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22和发光控制线23沿第二方向D2延伸。第一扫描信号线21和第二扫描信号线22设置在第一区域R1内，第二扫描信号线22位于第一扫描信号线21远离第二区域R2的一侧，发光控制线23设置在第三区域R3内，存储电容的第一极板24设置在第二区域R2内，位于第一扫描信号线21和发光控制线23之间。
在示例性实施例中，第一极板24可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域。在示例性实施例中，第一极板24同时作为第三晶体管T3的栅电极。
在示例性实施例中，第一扫描信号线21与第四晶体管T4的第四有源层相重叠的区域作为第四晶体管T4的栅电极。第一扫描信号线21设置有向第二扫描信号线22一侧凸起的栅极块21-1，栅极块21-1在基底上的正投影与第二晶体管T2的第二有源层在基底上的正投影存在重叠区域，第一扫描信号线21和栅极块21-1与第二晶体管T2的第二有源层相重叠的区域作为第二晶体管T2双栅结构的栅电极。第二扫描信号线22与第一晶体管T1的第一有源层相重叠的区域作为第一晶体管T1双栅结构的栅电极，第二扫描信号线22与第七晶体管T7的第七有源层相重叠的区域作为第七晶体管T7的栅电极，发光控制线23与第五晶体管T5的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六晶体管T6的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为 遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
如图22b所示，本次工艺后，显示基板包括设置在基底10上的第一绝缘层91、设置在第一绝缘层91上的半导体层、覆盖半导体层的第二绝缘层92和设置在第二绝缘层92上的第一导电层，半导体层可以包括第一有源层11和第三有源层13，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24。
(13)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层93，以及设置在第三绝缘层93上的第二导电层图案，第二导电层图案至少包括：初始信号线31、存储电容的第二极板32、屏蔽电极33和极板连接线35，如图23a和图23b所述，图23b为图23a中A-A向的剖视图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE 2)层。
如图23a所示，在示例性实施例中，初始信号线31沿第二方向D2延伸，设置在第一区域R1内，位于第二扫描信号线22远离第二区域R2的一侧。存储电容的第二极板32设置在第二区域R2内，位于第一扫描信号线21和发光控制线23之间。屏蔽电极33设置在第一区域R1内，屏蔽电极33配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，初始信号线31可以为非等宽度设置，初始信号线31的宽度为初始信号线31第一方向D1的尺寸。初始信号线31包括与半导体层相重叠的区域和与半导体层不相重叠的区域，与半导体层不相重叠的区域初始信号线31的宽度可以小于与半导体层相重叠的区域初始信号线31的宽度。
在示例性实施例中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域。第二极板32上设置有开口34，开口34可以位于第二区域 R2的中部。开口34可以为矩形，使第二极板32形成环形结构。开口34暴露出覆盖第一极板24的第三绝缘层93，且第一极板24在基底上的正投影包含开口34在基底上的正投影。在示例性实施例中，开口34配置为容置后续形成的第一过孔，第一过孔位于开口34内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施例中，极板连接线35设置在第二方向D2上相邻子像素的第二极板32之间，极板连接线35的第一端与本子像素的第二极板32连接，极板连接线35的第二端沿着第二方向D2或者第二方向D2的反方向延伸，并与相邻子像素的第二极板32连接，即极板连接线35配置为使第二方向D2上相邻子像素的第二极板相互连接。在示例性实施例中，通过极板连接线35，使一子像素行中的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，保证一子像素行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第二极板32邻近第一区域R1的边缘在基底上的正投影与第一区域R1与第二区域R2的交界线在基底上的正投影重叠，第二极板32邻近第三区域R3的边缘在基底上的正投影与第二区域R2与第三区域R3的交界线在基底上的正投影重叠，即第二极板32的长度等于第二区域R2的长度，第二极板32的长度是指第二极板32第二方向D2上的尺寸。
如图23b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第二导电层至少包括初始信号线31和存储电容的第二极板32，存储电容的第二极板32上设置有开口34，开口34暴露出覆盖第一极板24的第三绝缘层93，第二极板32在基底上的正投影与第一极板24在基底上的正投影存在重叠区域。
(14)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘 层上设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8和第九过孔V9，如图24a和图24b所示，图24b为图24a中A-A向的剖视图。
如图24a所示，在示例性实施例中，第一过孔V1位于第二极板32的开口34内，第一过孔V1在基底上的正投影位于开口34在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面。第一过孔V1配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一极板24连接。
在示例性实施例中，第二过孔V2位于第二极板32所在区域，第二过孔V2在基底上的正投影位于第二极板32在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板32的表面。第二过孔V2配置为使后续形成的第一电源线通过该过孔与第二极板32连接。在示例性实施例中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第一方向D1依次排列，增加第一电源线与第二极板32的连接可靠性。
在示例性实施例中，第三过孔V3位于第三区域R3，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面。第三过孔V3配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在示例性实施例中，第四过孔V4位于第三区域R3，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面。第四过孔V4配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层连接，以及使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层连接。
在示例性实施例中，第五过孔V5位于第一区域R1，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面。第五过孔V5配置为使后续形成的数据线通过该过孔与第四有源层连接，第五过孔V5称为数据写入孔。
在示例性实施例中，第六过孔V6位于第一区域R1，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面。第六过孔V6配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一有源层连接，以及使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层连接。
在示例性实施例中，第七过孔V7位于第一区域R1，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区(也是第一有源层的第一区)的表面。第七过孔V7配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层连接，以及使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层连接。
在示例性实施例中，第八过孔V8位于第一区域R1，第八过孔V8内的第四绝缘层被刻蚀掉，暴露出屏蔽电极33的表面。第八过孔V8配置为使后续形成的第一电源线通过该过孔与屏蔽电极33连接。
在示例性实施例中，第九过孔V9位于第一区域R1，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面。第九过孔V9配置为使后续形成的第七晶体管T7的第一极(也是第一晶体管T1的第一极)通过该过孔与初始信号线31连接。
如图24b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第四绝缘层94上设置有多个过孔，多个过孔至少包括第一过孔V1和第六过孔V6。第一过孔V1内的第四绝缘层94和第三绝缘层93被刻蚀掉，暴露出第二极板32的表面。第六过孔V6内的第四绝缘层94、第三绝缘层93和第二绝缘层92被刻蚀掉，暴露出第一有源层11的表面。
(15)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一电源线41、数据线42、第一连接电极43、第二连接电极 44和第三连接电极45，如图25a和图25b所示，图25b为图25a中A-A向的剖视图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
如图25a所示，在示例性实施例中，第一电源线41沿着第一方向D1延伸，第一电源线41一方面通过第二过孔V2与第二极板32连接，另一方面通过第八过孔V8与屏蔽电极33连接，又一方面通过第三过孔V3与第五有源层连接，使屏蔽电极33和第二极板32具有与第一电源线41相同的电位。由于屏蔽电极33在基底上的正投影与后续形成的数据线在基底上的正投影存在重叠区域，且屏蔽电极33与第一电源线41连接，有效屏蔽了数据电压跳变对关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，数据线42沿着第一方向D1延伸，数据线42通过第五过孔V5与第四有源层的第一区连接，使数据线42传输的数据信号写入第四晶体管T4。
在示例性实施例中，第一连接电极43沿着第一方向D1延伸，其第一端通过通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接，其第二端通过第一过孔V1与第一极板24连接，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位。在示例性实施例中，第一连接电极43可以作为第一晶体管T1的第二极和第二晶体管T2的第一极。
在示例性实施例中，第二连接电极44沿着第一方向D1延伸，其第一端通过第九过孔V9与初始信号线31连接，其第二端通过第七过孔V7与第七有源层的第一区(也是第一有源层的第一区)连接，使第七晶体管T7的第一极和第一晶体管T1的第一极具有与初始信号线31相同的电位。在示例性实施例中，第二连接电极44可以作为第七晶体管T7的第一极和第一晶体管T1的第一极。
在示例性实施例中，第三连接电极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接，使第六晶体管T6的第二极和第七晶体管T7的第二极具有相同的电位。在示例性实施例中，第三连接电极 45可以作为第六晶体管T6的第二极和第七晶体管T7的第二极。在示例性实施例中，第三连接电极45配置为与后续形成的阳极连接。
在示例性实施例中，第一电源线41和数据线42可以为等宽度直线，或者为非等宽度的直线。
如图25b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94上，第三导电层至少包括第一连接电极43和第三连接电极45，第一连接电极43分别通过第一过孔V1和第六过孔V6与第一极板24和第一晶体管T1的第一有源层11连接。
(16)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成覆盖第三导电层的第五绝缘层95，以及设置在第五绝缘层95上的第四导电层图案，第四导电层图案至少包括：数据扇出线700和第四连接电极52，如图26a和图16b所述，图26b为图26a中A-A向的剖视图。在示例性实施例中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施例中，第五绝缘层95上设有第十过孔(图中未示出)，第十过孔暴露出第三连接电极45的表面，第四连接电极52通过第十过孔与第三连接电极45连接。
在示例性实施例中，数据扇出线700在基底上的正投影位于以下任意一个或多个：第一电源线41、极板连接线35和初始信号线31，在基底上的正投影的范围之内。
本公开实施例中，通过使得数据扇出线700与一些固定电位信号线(第一电源线41、极板连接线35和初始信号线31等)重叠，可以避免数据信号写入时，数据扇出线700上的电位变化引起像素电路中其他信号线的电位跳变，从而可以提高显示品质。
在示例性实施例中，如图26a所示，数据扇出线700在基底上的正投影位于第一电源线41和/或极板连接线35在基底上的正投影的范围之内。
由于极板连接线35和第一电源线41连接，第一电源线41中的电压为恒定的正电压，数据电压的范围通常也为正电压，因此，数据扇出线700与第一电源线41(或极板连接线35)的电位相差较小，数据信号写入时，负载相对较小，从而进一步减轻了数据扇出线对其他信号线的信号串扰。
(17)形成平坦层图案。在示例性实施例中，形成平坦层图案可以包括：在形成前述图案的基底上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第三导电层的平坦层，平坦层上设置有第十一过孔V11，如图27a和图27b所示，图27b为图27a中A-A向的剖视图。
如图27a所示，第十过孔V10位于第四连接电极52所在区域，第十一过孔V11内的平坦层被去掉，暴露出第四连接电极52的表面，第十一过孔V11配置为使后续形成的阳极通过该过孔与第四连接电极52连接。
如图27b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94上，第五绝缘层95覆盖第三导电层，第四导电层设置在第五绝缘层95上，平坦层96覆盖第四导电层，平坦层上设置有第十一过孔V11，第十一过孔V11内的平坦层95被去掉，暴露出第四连接电极52的表面。
(18)形成阳极图案。在示例性实施例中，形成阳极图案可以包括：在形成前述图案的基底上，沉积透明导电薄膜，采用图案化工艺对透明导电薄膜进行图案化，形成设置在平坦层上的阳极71，如图28a和图28b所示，图28b为图28a中A-A向的剖视图所示。
如图28a所示，阳极71可以为六边形状，阳极71通过第十一过孔V11与第四连接电极52连接。由于第四连接电极52与第三连接电极45通过第十过孔连接，第三连接电极45作为第六晶体管T6的第二极和第七晶体管T7的第二极，因而阳极71与第六晶体管T6和第七晶体管T7连接，实现了像 素驱动电路可以驱动发光器件发光。
如图28b所示，在垂直于基底的平面内，第一绝缘层91设置在基底10上，半导体层设置在第一绝缘层91上，第二绝缘层92覆盖半导体层，第一导电层设置在第二绝缘层92上，第三绝缘层93覆盖第一导电层，第二导电层设置在第三绝缘层93上，第四绝缘层94覆盖第二导电层，第三导电层设置在第四绝缘层94上，第五绝缘层95覆盖第三导电层，第四导电层设置在第五绝缘层95上，平坦层96覆盖第四导电层，阳极71设置在平坦层96上，阳极71通过第十一过孔与第四连接电极52连接。
在示例性实施例中，后续制备流程可以包括：涂覆像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。采用蒸镀或喷墨打印工艺形成有机发光层，在有机发光层上形成阴极。形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一 绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。平坦层可以采用有机材料，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。有源层可以采用多晶硅(p-Si)，即本公开适用于LTPS薄膜晶体管。
虽然图28b所示示例性实施例以数据线设置在第三导电层、数据扇出线设置在第四导电层为例进行了说明，但本公开中，数据扇出线和数据线可以设置在任意层中，只要保证数据线与数据扇出线位于不同的导电层中即可，本公开在此不做限定。
本公开所示显示基板的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
一种显示基板中，绑定区域设置有扇出区，显示区域的数据线通过扇出区的数据扇出线引出，由于扇形区中斜向线较多，因而使得下边框较宽，不利于实现窄边框。本公开示例性实施例中，在绑定区域的引线区中设置引出线，在显示区域内设置数据扇出线，引出线通过数据扇出线与对应的数据线连接，不仅实现了多条引出线与多条数据线的对应连接，而且使得引线区中不需要设置扇形状的斜线，多条引出线为相互平行的竖直线，可以直接引入到绑定区域的复合电路区，有效减小了引线区竖直方向的长度，大大缩减了下边框宽度，使得显示装置的上边框、下边框、左边框和右边框的宽度相近，均为1.0mm以下，提高了屏占比，有利于实现全面屏显示。
此外，本公开实施例中，通过使得数据扇出线700与一些固定电位信号线(第一电源线41、极板连接线35和初始信号线31等)重叠，可以避免数据信号写入时，数据扇出线700上的电位变化引起像素电路中其他信号线的电位跳变，从而进一步提高显示品质。
图29为本公开示例性实施例另一种显示基板的结构示意图。如图29所示，显示区域100包括多条极板连接线35和初始信号线31，多条极板连接 线35和初始信号线31与第一方向D1具有第二夹角θ2，第二夹角θ2可以约为大于0°，小于90°。
在示例性实施方式中，第二夹角θ2可以约为20°至70°。
本实施例中，通过将极板连接线35和初始信号线31倾斜设置，可以减小位于极板连接线35和初始信号线31上方的数据扇出线的长度。如图29所示，由于极板连接线35和初始信号线31与第二栅金属层同层设置，因此，极板连接线35和初始信号线31倾斜设置，并不影响其他膜层信号线(如扫描信号线、发光控制线、复位信号线、第一电源线、数据线等)的排布。
本公开示例性实施例可以实现前述实施例的技术效果，包括有效缩减了下边框宽度，有效提高了显示均一性和显示品质。此外，本公开通过将极板连接线35和初始信号线31倾斜设置，有效减小了位于极板连接线35和初始信号线31上方的数据扇出线的长度，有利于降低布线设计的难度。
本示例性实施例中，数据线、数据扇出线和引出线的膜层结构可以与前述示例性实施例相近，这里不再赘述。
本公开示例性实施例还提供了一种显示基板的制备方法。在示例性实施方式中，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述制备方法可以包括：
在所述显示区域形成多条数据线和多条数据扇出线，在所述引线区形成多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、广告面板、手表电话、电子书便携式多媒体播放器或物联网各种产品的显示屏等任何具有显示功能的产品或部件。在示例性实施方式中，显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智 能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (14)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述显示区域包括多条数据线和多条数据扇出线，所述引线区包括多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；
    在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
  2. 根据权利要求1所述的显示基板，其中，所述至少一条数据扇出线包括第一线段和第二线段；所述第一线段的第一端与所述引出线连接，所述第一线段的第二端向着远离引线区的方向延伸后，与所述第二线段的第一端连接；所述第二线段的第二端向着靠近引线区的方向延伸后，通过过孔与所述数据线连接。
  3. 根据权利要求2所述的显示基板，其中，所述第一线段与第一方向平行，所述第二线段与所述第一方向之间具有第一夹角，所述第一夹角为20°至70°。
  4. 根据权利要求2所述的显示基板，其中，所述第二线段包括伸出段和连接段；所述伸出段的第一端位于所述显示区域内，与所述第一线段的第二端连接，所述伸出段的第二端向着靠近引线区的方向延伸到显示区域边缘后，与所述连接段的第一端连接，所述连接段的第二端向着远离显示区域的方向延伸后，通过过孔与延伸到引线区的数据线连接；所述显示区域边缘是显示区域靠近引线区一侧的边缘。
  5. 根据权利要求4所述的显示基板，其中，所述显示区域还包括第一电源线和极板连接线，所述第一电源线沿第一方向延伸，所述极板连接线沿第二方向延伸；所述第二方向与所述第一方向交叉；
    所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与所述极板连接线在显示基板平面上的正投影重叠。
  6. 根据权利要求4所述的显示基板，其中，所述显示区域还包括第一电源线和极板连接线，所述第一电源线沿第一方向延伸，所述极板连接线与所述第一方向之间具有第二夹角，所述第二夹角为20°至70°；
    所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与所述极板连接线在显示基板平面上的正投影重叠。
  7. 根据权利要求5或6所述的显示基板，其中，所述极板连接线位于所述第二导电层中，所述第一电源线位于所述第三导电层中，所述数据扇出线位于所述第四导电层中。
  8. 根据权利要求4所述的显示基板，其中，所述显示区域还包括第一电源线、初始信号线和极板连接线，所述第一电源线沿第一方向延伸，所述初始信号线和极板连接线均沿第二方向延伸；所述第二方向与所述第一方向交叉；
    所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上 的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与以下任意一个：所述初始信号线和所述极板连接线，在显示基板平面上的正投影重叠。
  9. 根据权利要求4所述的显示基板，其中，所述显示区域还包括第一电源线、初始信号线和极板连接线，所述第一电源线沿第一方向延伸，所述初始信号线和极板连接线均与第一方向之间具有第二夹角，所述第二夹角为20°至70°；
    所述伸出段包括M1个第一子线段和M1个第二子线段，M1为大于或等于1的自然数，所述第一子线段和所述第二子线段交替连接，位于所述伸出段一侧的第一子线段与所述第一线段连接，位于所述伸出段另一侧的第二子线段与所述连接段连接，所述第一线段和所述第二子线段在显示基板平面上的正投影均与所述第一电源线在显示基板平面上的正投影重叠，所述第一子线段在显示基板平面上的正投影与以下任意一个：所述初始信号线和所述极板连接线，在显示基板平面上的正投影重叠。
  10. 根据权利要求8或9任一项所述的显示基板，其中，所述初始信号线和极板连接线均位于所述第二导电层中，所述第一电源线位于所述第三导电层中，所述数据扇出线位于所述第四导电层中。
  11. 根据权利要求1所述的显示基板，其中，所述引线区中的多条引出线沿第二方向的宽度相同，相邻引出线之间沿第二方向的间距相同。
  12. 根据权利要求11所述的显示基板，其中，所述引线区的多条引出线包括第一引线组和第二引线组，所述第一引线组的引出线与所述第二引线组的引出线沿第二方向交替设置；
    所述第一引线组中的多条引出线通过多条所述数据扇出线与所述数据线对应连接，所述第二引线组中的多条引出线直接与所述数据线对应连接。
  13. 一种显示装置，包括如权利要求1至12任一项所述的显示基板。
  14. 一种显示基板的制备方法，所述显示基板包括显示区域和位于所述 显示区域一侧的绑定区域，所述绑定区域至少包括引线区；所述制备方法包括：
    在所述显示区域形成多条数据线和多条数据扇出线，在所述引线区形成多条引出线；至少一条引出线通过所述数据扇出线与所述数据线连接；在垂直于显示基板的平面内，所述显示基板包括第一导电层、第二导电层、第三导电层和第四导电层，所述第一导电层和所述第二导电层之间、所述第二导电层和所述第三导电层、所述第三导电层和所述第四导电层之间均设置有绝缘层；所述数据线和数据扇出线设置在不同的导电层中。
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