WO2023205997A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023205997A1
WO2023205997A1 PCT/CN2022/088977 CN2022088977W WO2023205997A1 WO 2023205997 A1 WO2023205997 A1 WO 2023205997A1 CN 2022088977 W CN2022088977 W CN 2022088977W WO 2023205997 A1 WO2023205997 A1 WO 2023205997A1
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WIPO (PCT)
Prior art keywords
electrode
transistor
signal line
initial
virtual
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PCT/CN2022/088977
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English (en)
French (fr)
Inventor
张跳梅
陈文波
谷泉泳
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/088977 priority Critical patent/WO2023205997A1/zh
Priority to CN202280000870.1A priority patent/CN115004375B/zh
Publication of WO2023205997A1 publication Critical patent/WO2023205997A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area, a binding area provided on one side of the display area, and a frame area provided on other sides of the display area.
  • the display area includes: a plurality of a plurality of circuit units in a unit row and a plurality of unit columns, and a plurality of virtual units constituting at least one virtual row and/or at least one virtual column, the virtual row including a plurality of virtual units arranged sequentially along a first direction,
  • the virtual column includes a plurality of virtual cells arranged sequentially along a second direction, the first direction intersects the second direction; at least one cell column is provided with a first initial signal extending along the second direction.
  • At least one virtual row is provided with a first connection line extending along the first direction, the first initial signal line is connected to the first connection line to form a mesh structure for transmitting the first initial signal; and /Or, at least one unit row is provided with a second initial signal line extending along the first direction, and at least one virtual column is provided with a second connection line extending along the second direction.
  • the second initial signal line The wires are connected to the second connection wires to form a mesh structure for transmitting the second initial signal.
  • At least one virtual cell in the virtual row includes a first initial electrode, a first end of the first initial electrode is connected to the first initial signal line, and a first end of the first initial electrode is connected to the first initial signal line. The second end is connected to the first connection line.
  • At least one virtual unit in the virtual column includes a second initial electrode, a first end of the second initial electrode is connected to the second connection line, and a first end of the second initial electrode is connected to the second connecting line. Two ends are connected to the second initial signal line.
  • At least one virtual cell in the virtual row includes a first initial electrode, a first end of the first initial electrode is connected to the first initial signal line, and a first end of the first initial electrode is connected to the first initial signal line.
  • the second end is connected to the first connection line;
  • at least one virtual cell in the virtual column includes a second initial electrode, and the first end of the second initial electrode is connected to the second connection line. The second ends of the two initial electrodes are connected to the second initial signal line.
  • At least one circuit unit includes a pixel driving circuit, which at least includes a storage capacitor and a plurality of transistors; in a plane perpendicular to the display substrate, the display substrate includes sequentially arranged A semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer, the semiconductor layer at least includes an active layer of a plurality of transistors, the first conductive layer at least includes a first plate of the storage capacitor and Gate electrodes of a plurality of transistors, the second conductive layer at least includes the second plate of the storage capacitor and the second initial signal line, the third conductive layer at least includes the first initial signal line and a plurality of the first and second poles of a transistor.
  • the second conductive layer further includes the first connection line
  • the third conductive layer further includes a first initial electrode, a first end of the first initial electrode is connected to the first The initial signal line is connected, and the second end of the first initial electrode is connected to the first connection line through a via hole.
  • the third conductive layer further includes a second initial electrode and the second connection line, a first end of the second initial electrode is connected to the second connection line, and the second The second end of the initial electrode is connected to the second initial signal line through a via hole.
  • the second conductive layer further includes the first connection line
  • the third conductive layer further includes a first initial electrode, a second initial electrode and the second connection line
  • the third conductive layer further includes a first initial electrode, a second initial electrode and the second connection line.
  • the plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the first electrode of the first transistor
  • the first terminal of the fourth transistor is connected to the first initial signal line
  • the first terminal of the fourth transistor is connected to the data signal line
  • the first terminal of the fifth transistor is connected to the first power supply line
  • the first terminal of the seventh transistor is connected to the first initial signal line.
  • the second electrode of the first transistor is connected to the first electrode of the second transistor and the gate electrode of the third transistor
  • the second electrode of the second transistor is connected to the second initial signal line.
  • the second pole of the third transistor is connected to the first pole of the sixth transistor, and the first pole of the third transistor is connected to the second pole of the fourth transistor and the second pole of the fifth transistor. connected, the second pole of the sixth transistor is connected to the second pole of the seventh transistor.
  • the pixel driving circuit further includes an anode connection electrode, the anode connection electrode is connected to the second electrode of the sixth transistor and the second electrode of the seventh transistor respectively, and the anode connection electrode An orthographic projection of the electrode on the substrate at least partially overlaps an orthographic projection of the first initial signal line on the substrate.
  • the anode connection electrode includes a first electrode, a second electrode and a third electrode, and a first end of the first electrode is connected to the second pole of the sixth transistor through a via hole, so The second end of the first electrode extends along the opposite direction of the first direction and is connected to the first end of the second electrode. The second end of the second electrode extends along the second direction. After extending in the opposite direction, it is connected to the first end of the third electrode. After extending along the first direction, the second end of the third electrode is connected to the second electrode of the seventh transistor through a via hole.
  • the orthographic projection of the second electrode on the substrate at least partially overlaps the orthographic projection of the first initial signal line on the substrate.
  • the pixel driving circuit further includes a shield electrode connected to the first power line, and an orthographic projection of the shield electrode on the substrate is in contact with the first transistor. Orthographic projections of the two poles on the substrate at least partially overlap.
  • At least one dummy unit includes a dummy driving circuit
  • the dummy driving circuit includes at least a storage capacitor and first to seventh transistors
  • the storage capacitor includes a first plate and a second plate, so The orthographic projection of the first pole plate on the substrate at least partially overlaps the orthographic projection of the second pole plate on the substrate, and the first pole plate of the virtual drive circuit and the virtual drive circuit The second pole plates are both connected to the first power line.
  • the active layer of the first transistor in the dummy driving circuit lacks a channel region
  • the active layer of the seventh transistor in the dummy driving circuit lacks a channel region
  • the display area includes at least a first circuit area, a second circuit area and a third circuit area;
  • the first circuit area includes a plurality of unit rows, a plurality of unit columns, at least one virtual row and At least one virtual column
  • the second circuit area is provided between the first circuit area and the frame area, the second circuit area includes a gate drive circuit, a plurality of unit rows, a plurality of unit columns and at least A virtual row
  • the third circuit area is disposed between the first circuit area and the binding area
  • the third circuit area includes data fan-out lines, a plurality of unit rows, a plurality of unit columns and at least one virtual column.
  • At least one virtual unit in the virtual row includes at least a virtual drive circuit connected to a first scan signal line, a second scan signal line and a light emitting control line, and the virtual row
  • the first scanning signal line, the second scanning signal line and the light-emitting control line extend to the frame area along the first direction and are connected to the frame power supply lead in the frame area, and the frame power supply lead is configured To transmit high-voltage power signals or low-voltage power signals.
  • At least one virtual cell in the virtual column includes at least a virtual driving circuit connected to a data signal line, and the data signal line in the virtual column is along the second direction. Extending to the binding area, it is connected to a binding power lead in the binding area, and the binding power lead is configured to transmit a high voltage power signal or a low voltage power signal.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a display area, a binding area provided on one side of the display area, and a frame area provided on the other side of the display area.
  • the display area includes: a plurality of unit rows and a plurality of unit columns. a plurality of circuit units, and a plurality of virtual units constituting at least one virtual row and/or at least one virtual column.
  • the virtual row includes a plurality of virtual units arranged sequentially along a first direction
  • the virtual column includes a plurality of virtual units arranged along a first direction.
  • a plurality of virtual units arranged sequentially in two directions, the first direction intersecting the second direction; the preparation method includes:
  • a first initial signal line extending along the second direction is formed in at least one unit column, and a first connection line extending along the first direction is formed in at least one virtual row.
  • the first initial signal line is connected to the first initial signal line.
  • the first connection lines are connected to form a mesh structure for transmitting the first initial signal; and/or,
  • a second initial signal line extending along the first direction is formed in at least one unit row, and a second connection line extending along the second direction is formed in at least one virtual column.
  • the second initial signal line is connected to
  • the second connection lines are connected to form a mesh structure for transmitting the second initial signal.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic cross-sectional structural diagram of a display area in a display substrate
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit
  • Figure 5 is a schematic plan view of a light-emitting structure layer in a display substrate according to an embodiment of the present disclosure
  • Figure 6 is a schematic plan view of a driving circuit layer in a display substrate according to an embodiment of the present disclosure
  • Figure 7a is a schematic plan view of a first circuit area according to an exemplary embodiment of the present disclosure.
  • Figure 7b is a schematic plan view of a second circuit area according to an exemplary embodiment of the present disclosure.
  • Figure 7c is a schematic plan view of a third circuit area according to an exemplary embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of a first circuit area according to an exemplary embodiment of the present disclosure.
  • Figure 9 is a schematic diagram of an initial signal line of a mesh structure according to an exemplary embodiment of the present disclosure.
  • Figure 10 is a schematic diagram of the present disclosure after the semiconductor layer pattern is formed on the substrate;
  • Figures 11a and 11b are schematic diagrams of the display substrate after forming a first conductive layer pattern
  • Figures 12a and 12b are schematic diagrams of the display substrate after forming a second conductive layer pattern
  • Figure 13 is a schematic diagram of the disclosure showing that the fourth insulating layer pattern is formed on the substrate
  • Figures 14a and 14b are schematic diagrams of the display substrate after forming a third conductive layer pattern
  • Figure 15 is a schematic diagram of the display substrate after forming a first flat layer pattern according to the present disclosure.
  • Figures 16a and 16b are schematic diagrams of the display substrate after forming a fourth conductive layer pattern
  • Figure 17 is a schematic diagram of an initial signal line of another mesh structure according to an exemplary embodiment of the present disclosure.
  • Figure 18 is a schematic diagram of another display substrate according to the present disclosure after forming a third conductive layer pattern
  • Figure 19 is a schematic diagram of an initial signal line of yet another mesh structure according to an exemplary embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of another display substrate according to the present disclosure after forming a third conductive layer pattern.
  • 70 the first initial electrode
  • 80 the second connecting line
  • 90 the second initial electrode
  • 103 Light-emitting structural layer
  • 104 Encapsulation layer
  • 110 First region
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 the first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal. lines, data signal lines and light-emitting signal lines.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample a grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be called an active area (AA).
  • the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area that are sequentially arranged in a direction away from the display area 100 .
  • the fan-out area is connected to the display area and may include at least a data fan-out line, a high-voltage power supply line, and a low-voltage power supply line.
  • the plurality of data fan-out lines are configured to connect the data signal lines of the display area in a fan-out (Fanout) wiring manner.
  • the high-voltage power supply line is configured to connect to the first power supply line (VDD) of the display area 100
  • the low-voltage power supply line is configured to connect to the second power supply line (VSS) of the frame area 300 .
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area may at least include an integrated circuit (Integrated Circuit, IC for short) configured to be connected to multiple data fan-out lines.
  • the bonding pin area may include at least a plurality of bonding pads (Bonding Pads) configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning signal line, the second scanning signal line and the light emission control line of the pixel driving circuit in the display area 100 .
  • the power line area is connected to the circuit area and may at least include a power lead extending in a direction parallel to the edge of the display area and connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along Extending in a direction parallel to the edge of the display area, forming a ring-shaped structure surrounding the display area 100, the edge of the display area is an edge on one side of the display area binding area or the frame area.
  • FIG. 3 is a schematic cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 provided on a substrate 101 , a light-emitting structure layer 103 provided on a side of the driving circuit layer 102 away from the substrate, and a light-emitting structure layer 103 provided on the side of the driving circuit layer 102 away from the substrate.
  • Layer 103 is away from the packaging structure layer 104 on the side of the substrate.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and a storage capacitor.
  • the light-emitting structure layer 103 may include a plurality of sub-pixels. Each sub-pixel may include a light-emitting device and a pixel definition layer 302.
  • the light-emitting device may include an anode 301, an organic light-emitting layer 303 and a cathode 304.
  • the organic light-emitting layer 303 is disposed between the anode 301 and the cathode 304.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together Common layer, the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C.
  • the pixel driving circuit is respectively connected to 8 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the first initial signal line INIT1, the second initial signal line INIT2, the first power supply line VDD and the second power supply line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor,
  • the first electrode of the second transistor T2 and the control electrode of the third transistor T3 are connected to the second end of the storage capacitor C.
  • the third node N3 is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the first initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switching transistor, a scanning transistor, or the like.
  • the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth and sixth transistors T5 and T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the second initial voltage to the first pole of the light-emitting device to initialize the amount of charge accumulated in the first pole of the light-emitting device or The amount of charge accumulated in the first pole of the light-emitting device is released.
  • the light-emitting device may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode) , quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD continuously provides a high-level signal.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the working process of the pixel driving circuit may include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned on.
  • the first transistor T1 is turned on so that the first initial voltage of the first initial signal line INIT1 is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the seventh transistor T7 is turned on so that the second initial voltage of the second initial signal line INIT2 is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal pre-stored voltage, and completing the initialization.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 to be turned off. At this stage, the OLED does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, causing the second transistor T2 and the fourth transistor T4 to be turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • Node N2 and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 and the seventh transistor T7 to be turned off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • Exemplary embodiments of the present disclosure provide a display substrate that adopts a structure in which the data fan-out line is located in the display area (Fanout in AA, referred to as FIAA) and the gate driver circuit is located in the display area (Gate Driver In AA, referred to as GIA).
  • FIG. 5 is a schematic plan view of a light-emitting structure layer in a display substrate according to an exemplary embodiment of the present disclosure.
  • the light-emitting structure layer of the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a A first sub-pixel P1 that emits light of the first color, a second sub-pixel P2 that emits light of the second color, and two third sub-pixels P3 and P4 that emit light of the third color.
  • the four sub-pixels can be evenly spaced.
  • It includes a light-emitting device, the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels can be rectangular, rhombus, pentagon or hexagon, and the four sub-pixels can be arranged horizontally, vertically, square or diamond-shaped.
  • the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • FIG. 6 is a schematic plan view of a driving circuit layer in a display substrate according to an exemplary embodiment of the present disclosure.
  • the driving circuit layer of the display area may include a first circuit area 110 , a second circuit area 120 and a third circuit area 130 .
  • the circuit area 110 is configured to provide a plurality of circuit units and a plurality of dummy units
  • the second circuit area 120 is configured to provide a gate driving circuit
  • the third circuit area 130 is configured to provide Multiple data fan-out lines, multiple circuit units, and multiple virtual units.
  • the second circuit area 120 may be disposed on one side or both sides of the first circuit area 110 in the first direction X, and the second circuit area 120 may be in a strip shape extending along the second direction Y.
  • One direction X intersects the second direction Y.
  • the third circuit area 130 may be disposed on one side of the first circuit area 110 in the second direction Y, the third circuit area 130 may be close to the binding area, and the third circuit area 130 may be along the first direction.
  • the first direction X may be an extending direction of the scanning signal line
  • the second direction Y may be an extending direction of the data signal line
  • the first direction X and the second direction Y are perpendicular.
  • Figure 7a is a schematic plan view of a first circuit area according to an exemplary embodiment of the present disclosure.
  • the first circuit area may include multiple circuit units PA and multiple virtual units DA.
  • the multiple circuit units PA may constitute multiple unit rows and multiple unit columns.
  • the multiple virtual units DA may constitute at least one Virtual rows and at least one virtual column.
  • the unit row may include a plurality of circuit units PA and at least one dummy unit DA sequentially arranged along the first direction X
  • the unit column may include a plurality of circuit units PA sequentially arranged along the second direction Y. and at least one virtual unit DA.
  • the virtual row may include a plurality of virtual units DA arranged in sequence along the first direction X
  • the virtual column may include a plurality of virtual units DA arranged in series along the second direction Y.
  • At least one virtual row may be disposed between two unit rows, and at least one virtual column may be disposed between two unit columns.
  • the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is connected to the scanning signal line, the data signal line, and the light-emitting signal line respectively, and the pixel driving circuit is configured to control the scanning signal line and the light-emitting signal line. , receives the data voltage transmitted by the data signal line, and outputs the corresponding current to the connected light-emitting device.
  • the dummy unit may at least include a dummy driving circuit configured to assume the topography and structure of the pixel driving circuit but not output a corresponding current.
  • Figure 7b is a schematic plan view of a second circuit area according to an exemplary embodiment of the present disclosure.
  • the second circuit area may include a second pixel area 121 and a gate circuit area 122.
  • the gate circuit area 122 may be disposed on a side of the second pixel area 121 away from the first circuit area.
  • the second pixel area 121 may include a plurality of circuit units PA and a plurality of dummy units DA, and the gate circuit area 122 may include a plurality of gate circuit units GA.
  • a plurality of circuit units PA may constitute a plurality of unit rows and a plurality of unit columns, and a plurality of virtual units DA may constitute at least one virtual row.
  • the second circuit area is provided with only dummy rows and no dummy columns.
  • a plurality of circuit units PA may be arranged in the second circuit area in a close-packed and laterally compressed manner, and the compressed space serves as the installation space for the gate circuit unit GA. Since the gate driving circuit is disposed in the second circuit area in the display area, the frame width of the display device is effectively reduced, and the left and right frame widths are effectively reduced.
  • Figure 7c is a schematic plan view of a third circuit area according to an exemplary embodiment of the present disclosure.
  • the third circuit area may include a third pixel area 131 and a fan-out line area 132.
  • the fan-out line area 132 may be disposed on a side of the third pixel area 131 away from the first circuit area.
  • the third pixel area 131 may include a plurality of circuit units PA and a plurality of dummy units DA, and the fan-out line area 132 may include a plurality of data fan-out lines.
  • a plurality of circuit units PA may constitute a plurality of unit rows and a plurality of unit columns, and a plurality of virtual cells DA may constitute at least one virtual column.
  • the third circuit area is provided with only virtual columns and no virtual rows.
  • the third circuit area may be configured with a plurality of circuit units PA in a close-packed longitudinal compression manner, and the compressed space is used as a space for installing data fan-out lines.
  • one end of the plurality of data fan-out lines is correspondingly connected to the plurality of data signal lines in the third circuit area, and the other end of the plurality of data fan-out lines extends to the binding area and is correspondingly connected to the integrated circuit. Since there is no need to set fan-shaped diagonal lines in the binding area, the width of the fan-out area is reduced, effectively reducing the width of the bottom border.
  • both the second circuit area and the third circuit area use a close-packed compression method to arrange circuit units.
  • the first circuit area also adopts the same method as the second circuit area and the second circuit area.
  • circuit units are arranged in the same close-packed compression method, and at least one virtual row and at least one virtual column are arranged in the compressed space.
  • the present disclosure provides a display substrate, including a display area, a binding area provided on one side of the display area, and a frame area provided on the other side of the display area.
  • the display area includes: a plurality of unit rows and A plurality of circuit units in a plurality of unit columns, and a plurality of virtual cells constituting at least one virtual row and/or at least one virtual column, the virtual row including a plurality of virtual cells arranged sequentially along a first direction, the virtual The columns include a plurality of virtual cells arranged sequentially along a second direction, the first direction intersecting the second direction; at least one cell column is provided with a first initial signal line extending along the second direction, at least One virtual row is provided with a first connection line extending along the first direction, and the first initial signal line is connected to the first connection line to form a mesh structure for transmitting the first initial signal; and/or, At least one unit row is provided with a second initial signal line extending along the first direction, and at least one virtual column is provided with a second
  • At least one virtual unit in the virtual row includes a first initial electrode, a first end of the first initial electrode is connected to the first initial signal line, and the first initial electrode The second end of the electrode is connected to the first connection line.
  • At least one virtual cell in the virtual column includes a second initial electrode, a first end of the second initial electrode is connected to the second connection line, and the second initial electrode The second end of the electrode is connected to the second initial signal line.
  • At least one virtual cell in the virtual row includes a first initial electrode, a first end of the first initial electrode is connected to the first initial signal line, and the first initial electrode The second end of the initial electrode is connected to the first connection line; at least one virtual unit in the virtual column includes a second initial electrode, and the first end of the second initial electrode is connected to the second connection line, The second end of the second initial electrode is connected to the second initial signal line.
  • At least one circuit unit includes a pixel driving circuit, which at least includes a storage capacitor and a plurality of transistors; in a plane perpendicular to the display substrate, the display substrate includes sequentially arranged A semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer, the semiconductor layer at least includes active layers of a plurality of transistors, the first conductive layer at least includes a first plate of a storage capacitor and a plurality of The gate electrode of the transistor, the second conductive layer at least includes the second plate of the storage capacitor and the second initial signal line, the third conductive layer at least includes the first initial signal line and the first signal line of the plurality of transistors.
  • the second conductive layer further includes the first connection line
  • the third conductive layer further includes a first initial electrode
  • the first end of the first initial electrode is connected to the first connection line.
  • the first initial signal line is connected
  • the second end of the first initial electrode is connected to the first connection line through a via hole.
  • the third conductive layer further includes a second initial electrode and the second connection line, and a first end of the second initial electrode is connected to the second connection line, so The second end of the second initial electrode is connected to the second initial signal line through a via hole.
  • the second conductive layer further includes the first connection line
  • the third conductive layer further includes a first initial electrode, a second initial electrode and the second connection line
  • the first end of the first initial electrode is connected to the first initial signal line
  • the second end of the first initial electrode is connected to the first connection line through a via hole
  • the second end of the second initial electrode is connected to the first connection line through a via hole.
  • One end is connected to the second connection line
  • the second end of the second initial electrode is connected to the second initial signal line through a via hole.
  • the plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; the first electrode of the first transistor
  • the first terminal of the fourth transistor is connected to the first initial signal line
  • the first terminal of the fourth transistor is connected to the data signal line
  • the first terminal of the fifth transistor is connected to the first power supply line
  • the first terminal of the seventh transistor is connected to the first initial signal line.
  • the second electrode of the first transistor is connected to the first electrode of the second transistor and the gate electrode of the third transistor
  • the second electrode of the second transistor is connected to the second initial signal line.
  • the second pole of the third transistor is connected to the first pole of the sixth transistor, and the first pole of the third transistor is connected to the second pole of the fourth transistor and the second pole of the fifth transistor. connected, the second pole of the sixth transistor is connected to the second pole of the seventh transistor.
  • At least one dummy unit includes a dummy driving circuit
  • the dummy driving circuit includes at least a storage capacitor and first to seventh transistors
  • the storage capacitor includes a first plate and a second plate, so The orthographic projection of the first pole plate on the substrate at least partially overlaps the orthographic projection of the second pole plate on the substrate, and the first pole plate of the virtual drive circuit and the virtual drive circuit The second pole plates are both connected to the first power line.
  • the virtual driving circuit further includes an inter-electrode connection electrode, a second electrode of a first transistor among the plurality of transistors is connected to the first plate through a via hole, and a fifth electrode among the plurality of transistors
  • the first electrode of the transistor is connected to the second electrode plate through a via hole
  • the inter-electrode connection electrode is connected to the second electrode of the first transistor and the first electrode of the fifth transistor respectively.
  • the active layer of the first transistor in the dummy driving circuit lacks a channel region
  • the active layer of the seventh transistor in the dummy driving circuit lacks a channel region
  • FIG. 8 is a schematic structural diagram of a first circuit area according to an exemplary embodiment of the present disclosure, illustrating the planar structure of 8 circuit units and 7 dummy units in the first circuit area.
  • the M-1th row and the M+1th row are unit rows, including 4 circuit units and 1 virtual unit respectively.
  • the Mth row is a virtual row, including 5 virtual units.
  • the N-2nd column and the N-1th row Column, N+1th column and N+2th column are unit columns, including 2 circuit units and 1 virtual unit respectively, and Nth column is a virtual column, including 3 virtual units.
  • the unit rows may include at least a plurality of circuit units arranged in sequence along the first direction X, the plurality of unit rows may be arranged in sequence along the second direction Y, and the unit columns may at least It includes a plurality of circuit units arranged in sequence along the second direction Y, and a plurality of unit columns may be arranged in sequence along the first direction X.
  • At least one circuit unit may include a pixel driving circuit.
  • the pixel driving circuit may include a plurality of transistors and storage capacitors. The pixel driving circuit is connected to the first scanning signal line 21, the second scanning signal line 22, the light emission control line 23, and the first initial signal respectively.
  • the line 47, the second initial signal line 31, the data signal line 51 and the first power supply line 52 are connected.
  • the first scan signal line 21 and the second scan signal line 22 are configured to receive the first scan signal and the second scan signal respectively
  • the light emitting control line 23 is configured to receive the light emitting control signal
  • the data signal line 51 is configured to receive the data signal
  • the first power line 52 is configured to receive the first power signal
  • the first initial signal line 47 and the second initial signal line 31 are configured to receive the first initial signal and the second initial signal respectively
  • the first initial signal may be configured to initialize (reset) the first plate of the storage capacitor
  • the second initial signal may be configured to initialize (reset) the anode of the light-emitting device.
  • the plurality of transistors in the pixel driving circuit may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor.
  • Transistor T7 The first electrode of the first transistor T1 is connected to the first initial signal line 47, the first electrode of the fourth transistor T4 is connected to the data signal line 51, the first electrode of the fifth transistor T5 is connected to the first power line 52, and the first electrode of the fifth transistor T5 is connected to the first power line 52.
  • the first electrode of the transistor T7 is connected to the second initial signal line 31, the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 and the gate electrode of the third transistor T3, and the second electrode of the second transistor T2
  • the second electrode of the third transistor T3 is connected to the first electrode of the sixth transistor T6.
  • the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5.
  • the second electrode of the transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the pixel driving circuit may further include an anode connection electrode 54, which is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 respectively, and the anode connection electrode 54 is on the substrate.
  • the anode connection electrode 54 may include a first electrode, a second electrode, and a third electrode.
  • the first end of the first electrode is connected to the second pole of the sixth transistor T6 through a via hole.
  • the second end extends along the opposite direction of the first direction X and is connected to the first end of the second electrode.
  • the second end of the second electrode extends along the opposite direction of the second direction Y and is connected to the first end of the third electrode.
  • One end is connected, and the second end of the third electrode extends along the first direction Orthographic projections on the substrate at least partially overlap.
  • the driving circuit layer may at least include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate.
  • the semiconductor layer may at least include active layers of a plurality of transistors, the first conductive layer may at least include gate electrodes of the plurality of transistors and a first plate of a storage capacitor, and the second conductive layer may at least include a first connection line 60 and a storage capacitor.
  • the second plate of the capacitor, the third conductive layer may include at least the first initial signal line 47 and the first initial electrode 70 , and the fourth conductive layer may include at least the data signal line 51 and the first power line 52 .
  • the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a first flat layer, the first insulating layer being disposed between the substrate and the semiconductor layer, The second insulating layer is disposed between the semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, and the fourth insulating layer is disposed between the second conductive layer and the third conductive layer. , the first flat layer is disposed between the third conductive layer and the fourth conductive layer.
  • the shape of the first connection line 60 may be a line shape with the main body extending along the first direction X
  • the shape of the first initial signal line 47 may be a line shape with the main body extending along the second direction Y.
  • the first initial signal line 47 and the first connection line 60 are connected to each other through the first initial electrode 70 to form an initial signal line with a mesh structure.
  • A extends along the direction B. It means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body.
  • the main part extends along the direction B, and the main part extends along the direction B.
  • the length of extension in one direction is greater than the length of the secondary portion extending in other directions.
  • FIG. 9 is a schematic diagram of an initial signal line of a mesh structure in a first circuit area according to an exemplary embodiment of the present disclosure.
  • the arrangement of circuit units and virtual units is the same as that shown in FIG. 8 .
  • the first initial signal line 47 may be provided in each unit column and the virtual column
  • the first connection line 60 may be provided in the virtual row
  • the second initial signal line 31 may be Set in each cell row.
  • the first initial electrode 70 may be disposed in at least one virtual cell in the virtual row, and the first end of the first initial electrode 70 is directly connected to the first initial signal line 47 in the virtual cell.
  • the second end of an initial electrode 70 is connected to the first connection line 60 in the virtual unit through via holes and connection blocks, thereby realizing the first initial signal line 47 extending along the second direction Y and the first initial signal line 47 extending along the first direction X.
  • the connection of the extended first connection line 60 causes the first initial signal line 47 and the first connection line 60 to form a mesh structure in the display area for transmitting the first initial signal, which can not only effectively reduce the risk of the first initial signal line.
  • the resistance can reduce the voltage drop of the first initial signal, and can effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the first initial signal line 47 and the first initial electrode 70 may be arranged on the same layer, formed simultaneously through the same patterning process, and be an integral structure connected to each other.
  • the first initial electrode 70 may be connected to the first region of the seventh active layer, which is the active layer of the seventh transistor T7, through a via hole.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the driving circuit layer may include the following operations.
  • Form a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on The semiconductor layer on the first insulating layer is shown in Figure 10.
  • the semiconductor layer of the circuit unit may include the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7 , and the first to sixth active layers 11 to 17 of the seventh transistor T7 .
  • the layers 16 are an integral structure connected to each other, and the seventh active layer 17 can be provided separately.
  • the first active layer 11 , the second active layer 12 , the fourth active layer 14 and the seventh active layer 17 in the M-1th row circuit unit are located in the third row of the circuit unit.
  • the active layer 13 is on the side away from the circuit unit of the Mth row.
  • the first active layer 11 and the seventh active layer 17 are located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13 .
  • side, the fifth active layer 15 and the sixth active layer 16 in the circuit unit of the M-1th row are located on the side of the third active layer 13 close to the circuit unit of the M-th row.
  • the first active layer 11 may be in an "n" shape
  • the second active layer 12 , the fifth active layer 15 and the sixth active layer 16 may be in an "L” shape
  • the shape of the third active layer 13 may be in the shape of "J”
  • the shape of the fourth active layer 14 and the seventh active layer 17 may be in the shape of "I”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region 11-2 of the first active layer 11 simultaneously serves as the first region 12-1 of the second active layer 12, and the first region 13-1 of the third active layer 13 simultaneously As the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 simultaneously serves as the second active layer 12
  • the second region 12-2 and the first region 16-1 of the sixth active layer 16 the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, The first region 15-1 of the fifth active layer 15, the second region 16-2 of the sixth active layer 16, the first region 17-1 of the seventh active layer 17, and the first region 17-1 of the seventh active layer 17.
  • Zone 2 17-2 is set separately.
  • the semiconductor layer of the dummy unit and the semiconductor layer of the circuit unit may be substantially the same, except that the first region 11-1 and the first active layer of the first active layer 11 of the dummy unit A break 18 is provided between the second area 11 - 2 of the seventh active layer 17 , and a break 18 is provided between the first area 17 - 1 of the seventh active layer 17 and the second area 17 - 2 of the seventh active layer 17 .
  • the position of the break 18 may correspond to the position of the subsequently formed second scanning signal line, so that the first active layer 11 and the seventh active layer 17 have only the first area and the second area, and There is no channel area, that is, the active layer of the first transistor lacks the channel area, and the active layer of the seventh transistor lacks the channel area.
  • the first transistor and the seventh transistor of the dummy unit cannot perform signal transmission, forming a dummy first transistor. transistor and a dummy seventh transistor.
  • Flexible connection structure allows freer connection to relevant DC signals.
  • the first scanning signal line, the second scanning signal line and the light-emitting control signal line in the Mth row can be connected to the frame power leads in the frame area, thereby greatly reducing the load of transmitting power signals and helping to improve display uniformity.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming The second insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, are shown in Figures 11a and 11b.
  • Figure 11b is a schematic plan view of the first conductive layer in Figure 11a.
  • the first conductive layer may be referred to as a first gate metal (GATE 1) layer.
  • the first conductive layer pattern of the circuit unit may include at least a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23 and a first plate 24 of a storage capacitor,
  • the shape of the first plate 24 of the storage capacitor may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate 24 on the substrate is consistent with the third transistor T3 Orthographic projections of the three active layers on the substrate at least partially overlap.
  • the first plate 24 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the first scanning signal line 21 , the second scanning signal line 22 and the light emission control line 23 may be a line shape in which the main body portion extends along the first direction X.
  • the first scanning signal line 21 and the second scanning signal line 22 in the M-1th row circuit unit can be located on the side of the first plate 24 of this circuit unit away from the M-th row circuit unit, and the second scanning signal line 22 is located on the side of the first plate 24 of the circuit unit away from the M-th row circuit unit.
  • the first scanning signal line 21 of this circuit unit is on the side away from the first plate 24, and the light-emitting control line 23 can be located on the side of the first plate 24 of this circuit unit close to the M-th row circuit unit.
  • the first scanning signal line 21 of the circuit unit is provided with a gate block 21-1 protruding toward the second scanning signal line 22 side, the first scanning signal line 21 and the gate block 21-1
  • the area overlapping the second active layer serves as the gate electrode of the second transistor T2, forming the second transistor T2 with a double-gate structure.
  • a region where the first scanning signal line 21 overlaps the fourth active layer serves as the gate electrode of the fourth transistor T4.
  • the area where the second scanning signal line 22 overlaps with the first active layer serves as the gate electrode of the first transistor T1 in the double-gate structure, and the area where the second scanning signal line 22 overlaps with the seventh active layer serves as the seventh transistor T7 gate electrode.
  • the area where the light-emitting control line 23 overlaps the fifth active layer serves as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 23 overlaps the sixth active layer serves as the gate electrode of the sixth transistor T6.
  • the first conductive layer pattern of the dummy unit and the first conductive layer pattern of the circuit unit may be substantially the same, except that the second scanning signal line 22 and the gap of the first active layer and the first conductive layer pattern of the circuit unit may be substantially the same.
  • the gaps in the seven active layers overlap.
  • the first active layer and the seventh active layer are respectively the active layer of the first transistor T1 and the active layer of the seventh transistor T7.
  • the overlapping areas respectively form a dummy first transistor.
  • the first scanning signal line 21, the second scanning signal line 22, and the light emitting control line 23 in the M-1th row and the M+1th row are respectively connected with the gate drive in the third circuit area 130.
  • the gate drive circuit provides corresponding scanning signals and light-emitting control signals.
  • the first scanning signal line 21, the second scanning signal line 22 and the light emission control line 23 in the Mth row (dummy row) can be used as constant voltage signal lines, which can extend through the third circuit area 130 of the display area to the frame area.
  • the left frame and/or the right frame are connected to the frame power leads set in the left frame and/or the right frame.
  • the bezel power leads may be configured to carry a high voltage power signal (VDD) or may be configured to carry a low voltage power signal (VSS).
  • VDD high voltage power signal
  • VSS low voltage power signal
  • the first conductive layer can be used as a shield to perform a conductive process on the semiconductor layer, and the semiconductor layer in the area blocked by the first conductive layer forms the first to seventh transistors T1 to T1.
  • the semiconductor layer in the region not blocked by the first conductive layer is conductive, that is, the first and second regions of the first to seventh active layers are all conductive.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process to form The third insulating layer covering the first conductive layer and the second conductive layer pattern disposed on the third insulating layer are as described in Figures 12a and 12b.
  • Figure 12b is a schematic plan view of the second conductive layer in Figure 12a.
  • the second conductive layer may be referred to as a second gate metal (GATE 2) layer.
  • the second conductive layer pattern of the circuit unit at least includes: a second initial signal line 31, a connection block 32, a second plate 33 of the storage capacitor, and a plate connection line 34.
  • the shape of the second initial signal line 31 may be a line shape in which the main body portion extends along the first direction X.
  • the second initial signal line 31 in the circuit unit of the M-1th row may be located on the side of the second scanning signal line 22 of this circuit unit away from the circuit unit of the M-th row.
  • the second initial signal line 31 is configured to be formed by subsequent
  • the first electrode of the seventh transistor T7 is connected to the first region of the seventh active layer.
  • connection block 32 of the circuit unit may be rectangular in shape, disposed on a side of the second initial signal line 31 close to the second scanning signal line 22 , and connected to the second initial signal line 31 .
  • connection block 32 is configured to be connected to a subsequently formed sixth connection electrode to enable the second initial signal line 31 to input the second initial signal to the first electrode of the seventh transistor T7.
  • the second initial signal line 31 and the connection block 32 may be an integral structure connected to each other.
  • the outline shape of the second electrode plate 33 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 33 on the base is the same as the orthographic projection of the first electrode plate 24 on the base.
  • the orthographic projections at least partially overlap, the second plate 33 serves as the other plate of the storage capacitor, and the first plate 24 and the second plate 33 constitute the storage capacitor of the pixel driving circuit.
  • the second plate 33 is provided with an opening 35 , and the opening 35 may be located in the middle of the second plate 33 .
  • the opening 35 may be in a rectangular shape, so that the second electrode plate 33 forms an annular structure.
  • the opening 35 exposes the third insulating layer covering the first electrode plate 24 , and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 35 on the substrate.
  • the opening 35 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located within the opening 35 and exposes the first plate 24 so that the subsequently formed second transistor T1 can The pole is connected to the first pole plate 24 .
  • the plate connecting line 35 may be disposed on one side of the second plate 33 in the first direction X or in the opposite direction to the first direction
  • the second electrode plate 33 is connected, and the second end of the plate connection line 35 extends along the first direction X or the opposite direction of the first direction X, and is connected to the second electrode plate 33 of the adjacent circuit unit.
  • the plate connection line 35 is configured to interconnect the second plates of adjacent circuit units on a unit row.
  • the second plates of multiple circuit units in a unit row form an integrated structure connected to each other through the plate connection lines 35 .
  • the second plates of the integrated structure can be reused as power signal lines to ensure that Multiple second electrode plates in one unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second conductive layer pattern of the dummy unit and the second conductive layer pattern of the circuit unit may be substantially the same, except that the second conductive layer pattern of the dummy unit in the Mth row includes the first connection Line 60, the position and shape of the first connection line 60 in the virtual unit and the position and shape of the second initial signal line 31 in the circuit unit may be substantially the same.
  • connection block 32 of the virtual unit in the M-th row may be rectangular in shape, disposed on a side of the first connection line 60 close to the second scanning signal line 22 , and connected to the first connection line 60 .
  • the connection block 32 is configured to connect with the subsequently formed first initial electrode to realize the connection between the first connection line 60 and the first initial signal line.
  • the shape of the first connection line 60 of the virtual unit in the M-th row may be a line shape in which the main body part extends along the first direction X.
  • the first connection line 60 may be located on the side of the second scanning signal line 22 of the virtual unit away from the first scanning signal line 25.
  • the first connection line 60 is configured to pass through the subsequently formed first initial electrode and the first initial signal line. connect.
  • Form a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • the fourth insulating layer is provided with multiple via holes, as shown in Figure 13.
  • the plurality of vias of the circuit unit may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via Via V6, seventh via V7, eighth via V8, ninth via V9 and tenth via V10,
  • the orthographic projection of the first via hole V1 on the substrate may be located within the range of the orthogonal projection of the opening 35 of the second plate 33 on the substrate, and the fourth insulating layer in the first via hole V1 and the third insulating layer is etched away to expose the surface of the first plate 24.
  • the first via hole V1 is configured to allow the second electrode of the subsequently formed first transistor T1 to communicate with the first plate through the via hole. 24 connections.
  • the orthographic projection of the second via hole V2 on the substrate may be located within the range of the orthographic projection of the second electrode plate 33 on the substrate, and the fourth insulating layer in the second via hole V2 is etched. removed, exposing the surface of the second electrode plate 33 , and the second via hole V2 is configured so that the first electrode of the subsequently formed fifth transistor is connected to the second electrode plate 33 through the via hole.
  • the second via hole V2 serving as a power via hole may include a plurality of second via holes V2, and the plurality of second via holes V2 may be arranged sequentially along the second direction Y to increase connection reliability.
  • the orthographic projection of the third via hole V3 on the substrate may be located within the range of the orthogonal projection of the first region of the fifth active layer on the substrate, and the fourth insulation in the third via hole V3 layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fifth active layer, and the third via V3 is configured to allow the first electrode of the subsequently formed fifth transistor to pass through The via hole is connected to the first region of the fifth active layer.
  • the orthographic projection of the fourth via hole V4 on the substrate may be located within the range of the orthogonal projection of the second region of the sixth active layer on the substrate, and the fourth insulation in the fourth via hole V4 layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the second region of the sixth active layer, and the fourth via V4 is configured to enable the second electrode of the subsequently formed sixth transistor T6
  • the via hole is connected to the second region of the sixth active layer.
  • the orthographic projection of the fifth via hole V5 on the substrate may be located within the range of the orthogonal projection of the first region of the fourth active layer on the substrate, and the fourth insulation in the fifth via hole V5 layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the fourth active layer, and the fifth via V5 is configured to enable the first electrode of the subsequently formed fourth transistor T4 The via hole is connected to the first region of the fourth active layer.
  • the orthographic projection of the sixth via V6 on the substrate may be located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away, exposing the surface of the second area of the first active layer, and the sixth via hole V6 is configured as
  • the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) is connected to the first region of the first active layer through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate may be located within the range of the orthogonal projection of the first region of the seventh active layer on the substrate, and the fourth insulation in the seventh via hole V7 layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to enable the first electrode of the subsequently formed seventh transistor T7
  • the via hole is connected to the first region of the seventh active layer.
  • the orthographic projection of the eighth via hole V8 on the substrate may be located within the range of the orthogonal projection of the second region of the seventh active layer on the substrate, and the fourth insulation in the eighth via hole V8 layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the second region of the seventh active layer, and the eighth via V8 is configured to enable the second electrode of the subsequently formed seventh transistor T7
  • the via hole is connected to the second region of the seventh active layer.
  • the orthographic projection of the ninth via hole V9 on the substrate may be located within the range of the orthographic projection of the connection block 32 on the substrate, and the fourth insulating layer in the ninth via hole V9 is etched away, The surface of the connection block 32 is exposed, and the ninth via hole V9 is configured so that the first pole of the subsequently formed seventh transistor T7 is connected to the connection block 32 through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate may be located within the range of the orthogonal projection of the first region of the first active layer on the substrate, and the fourth insulation in the tenth via hole V10
  • the layer, the third insulating layer and the second insulating layer are etched away to expose the surface of the first region of the first active layer, and the tenth via hole V10 is configured to allow the subsequently formed first initial signal line to pass through the via hole V10.
  • the hole is connected to the first region of the first active layer.
  • the plurality of via hole patterns of the dummy unit and the second conductive layer pattern of the circuit unit may be substantially the same, except that the seventh via hole V7 of the dummy unit in the Mth row is configured such that The first initial electrode formed later is connected to the connection block 32 through the via hole, and the ninth via hole V9 is configured so that the first initial electrode formed subsequently is connected to the first region of the seventh active layer through the via hole, so as to The connection between the first initial signal line and the first connection line is realized.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer is as shown in Figures 14a and 14b.
  • Figure 14b is a schematic plan view of the third conductive layer in Figure 14a.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • SD1 first source-drain metal
  • the third conductive layer of the circuit unit includes at least: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode electrode 46 and first initial signal line 47.
  • the shape of the first connection electrode 41 may be a strip shape with a main body portion extending along the second direction Y.
  • the first end of the first connection electrode 41 communicates with the first plate 24 through the first via hole V1
  • the second end of the first connection electrode 41 is connected to the second area of the first active layer (also the first area of the second active layer) through the sixth via hole V6.
  • the first connection electrode 41 may simultaneously serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, so that the first electrode plate 24, the second electrode of the first transistor T1 and the first electrode of the second transistor T2
  • the first poles of the two transistors T2 ie, the second node N2 of the pixel driving circuit
  • the shape of the second connection electrode 42 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the second connection electrode 42 may be connected to the fifth active electrode through the third via hole V3.
  • the first area of the layer is connected, and the second end of the second connection electrode 42 can be connected to the second plate 33 through a plurality of second via holes V2.
  • the second connection electrode 42 may serve as the first electrode of the fifth transistor T5, so that the first electrode of the fifth transistor T5 and the second plate 33 have the same potential, and the second connection electrode 42 is configured To connect with the first power line formed later.
  • the shape of the third connection electrode 43 may be a polygonal shape, and the third connection electrode 43 may be connected to the second region of the seventh active layer through the eighth via hole V8.
  • the third connection electrode 43 may serve as the second electrode of the seventh transistor T7, and the third connection electrode 43 is configured to be connected to a subsequently formed anode connection electrode.
  • the shape of the fourth connection electrode 44 may be a polygonal shape, and the fourth connection electrode 44 may be connected to the second region of the sixth active layer through the fourth via hole V4.
  • the fourth connection electrode 44 may serve as the second electrode of the sixth transistor T6, and the fourth connection electrode 44 is configured to be connected to a subsequently formed anode connection electrode.
  • the shape of the fifth connection electrode 45 may be a strip shape with a main body portion extending along the second direction Y, and the fifth connection electrode 45 may communicate with the first portion of the fourth active layer through the fifth via hole V5 . area connection.
  • the fifth connection electrode 45 may serve as the first electrode of the fourth transistor T4, and the fifth connection electrode 45 is configured to be connected to a subsequently formed data signal line.
  • the shape of the sixth connection electrode 46 may be a strip shape with a main body portion extending along the first direction X, and the first end of the sixth connection electrode 46 is connected to the connection block 32 through the ninth via hole V9, The second end of the sixth connection electrode 46 is connected to the first area of the seventh active layer through the seventh via hole V7. Since the connection block 32 is connected to the second initial signal line 31, the second initial signal line 31 and Connections to the first area of the seventh active layer.
  • the sixth connection electrode 46 may serve as the first pole of the seventh transistor T7, so that the second initial signal line 31 and the first pole of the seventh transistor T7 have the same potential, realizing the second initial signal line 31 inputs the second initial signal to the first pole of the seventh transistor T7.
  • the shape of the first initial signal line 47 may be a line shape with the main body portion extending along the second direction Y, and the first initial signal line 47 may communicate with the first active layer through the tenth via V10
  • the first area connection enables the first initial signal line 47 to input the first initial signal to the first pole of the first transistor T1.
  • the first initial signal from the binding area can be quickly transmitted to the display area, which improves the initialization speed and is more conducive to increasing the refresh rate and meeting high-frequency requirements.
  • the third conductive layer of the dummy unit and the third conductive layer of the circuit unit may be substantially the same, except that the third conductive layer of the dummy unit further includes an inter-electrode connection electrode 48, row M
  • the third conductive layer of at least one dummy unit further includes a first initial electrode 70 .
  • the shape of the interelectrode connection electrode 48 may be a rectangular shape, a first end of the interelectrode connection electrode 48 is connected to the first connection electrode 41 , and a second end of the interelectrode connection electrode 48 is connected to the second connection electrode. 42 connections. Since the first connection electrode 41 is connected to the first plate 24 and the second connection electrode 42 is connected to the second plate 33, the first plate 24 and the second plate 33 of the dummy unit can be connected through the inter-electrode connection electrode 48. have the same potential.
  • the second connection electrode 42 is configured to be connected to the first power line formed subsequently, the first plate 24 , the second plate 33 and the first power line of the dummy unit have the same potential, that is, the first power line of the pixel driving circuit.
  • the second node N2 has the same potential as the first power line, which can eliminate the influence of the floating second node N2 of the virtual unit on the display and improve the display quality.
  • the first connection electrode 41 , the second connection electrode 42 and the inter-electrode connection electrode 48 of the dummy unit may be an integral structure connected to each other.
  • the position and shape of the first initial electrode 70 of the virtual unit in the M-th row may be substantially the same as the position and shape of the sixth connection electrode 46 of the circuit unit, except that the first initial electrode 70 is connected to the first initial signal line 47 .
  • the shape of the first initial electrode 70 may be a strip shape with a main body portion extending along the first direction X.
  • the first end of the first initial electrode 70 is connected to the first initial signal line 47 . After the second end of the electrode 70 extends along the first direction
  • the connection block in the M-th row is connected to the first connection line 60 in the M-th row on the one hand, and is connected to the first initial electrode 70 through the via hole on the other hand, the first initial electrode 70 Connected to the first initial signal line 47 , thus realizing the connection between the first initial signal line 47 extending along the second direction Y and the first connection line 60 extending along the first direction X, so that the first initial signal line 47 and the first connection line 60 form a mesh structure in the display area for transmitting the first initial signal, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the display
  • the uniformity of the first initial signal in the substrate effectively improves display uniformity and improves display quality and display quality.
  • the first initial electrode 70 and the first initial signal line 47 may be an integral structure connected to each other.
  • forming the first flat layer pattern may include: coating a first flat film on the substrate on which the foregoing pattern is formed, patterning the first flat film using a patterning process, and forming a covering third conductive layer.
  • the first flat layer is provided with multiple via holes, as shown in Figure 15.
  • the plurality of via holes of the circuit unit include at least: an eleventh via hole V11, a twelfth via hole V12, a thirteenth via hole V13, and a fourteenth via hole V14.
  • the orthographic projection of the eleventh via hole V11 on the substrate may be located within the range of the orthographic projection of the fifth connection electrode 45 on the substrate, and the first flat layer in the eleventh via hole V11 is Removed, the surface of the fifth connection electrode 45 is exposed, and the eleventh via hole V11 is configured to allow a subsequently formed data signal line to be connected to the fifth connection electrode 45 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate may be located within the range of the orthographic projection of the second connection electrode 42 on the substrate, and the first flat layer in the twelfth via hole V12 is Removed, the surface of the second connection electrode 42 is exposed, and the twelfth via hole V12 is configured so that the first power supply line formed later is connected to the second connection electrode 42 through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate may be located within the range of the orthographic projection of the fourth connection electrode 44 on the substrate, and the first flat layer in the thirteenth via hole V13 is Removed, the surface of the fourth connection electrode 44 is exposed, and the thirteenth via hole V13 is configured so that the subsequently formed anode connection electrode is connected to the fourth connection electrode 44 through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate may be located within the range of the orthographic projection of the third connection electrode 43 on the substrate, and the first flat layer in the fourteenth via hole V14 is Removed, the surface of the third connection electrode 43 is exposed, and the fourteenth via hole V14 is configured to allow the subsequently formed anode connection electrode to be connected to the third connection electrode 43 through the via hole.
  • the plurality of via hole patterns of the dummy unit and the plurality of via hole patterns of the circuit unit may be substantially the same.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a pattern on the first planar layer.
  • the fourth conductive layer on the substrate is shown in Figures 16a and 16b.
  • Figure 16b is a schematic plan view of the fourth conductive layer in Figure 16a.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer of the circuit unit includes at least: a data signal line 51 , a first power supply line 52 , a shield electrode 53 and an anode connection electrode 54 .
  • the shape of the data signal line 51 may be a line shape with the main body extending along the second direction Y, and the data signal line 51 may be connected to the fifth connection electrode 45 through the eleventh via hole V11 . Since the fifth connection electrode 45 is connected to the first region of the fourth active layer through the via hole, the data signal line 51 is realized to write the data signal into the first electrode of the fourth transistor T4 through the fifth connection electrode 45 .
  • the shape of the first power line 52 may be a line shape with the main body portion extending along the second direction Y, and the first power line 52 may be connected to the second connection electrode 42 through the twelfth via hole V12. Since the second connection electrode 42 is connected to the first area of the fifth active layer and the second plate 33 through the via hole, it is realized that the first power line 52 writes the first power signal into the fifth active layer through the second connection electrode 42 .
  • the first pole of the transistor T5, the second plate 33 and the first power line 52 have the same potential.
  • the shielding electrode 53 may be in a rectangular shape, is disposed on a side of the first power line 52 close to the first connection electrode 41 , and is connected to the first power line 52 .
  • the shielding electrode 53 is on the substrate.
  • the orthographic projection at least partially overlaps the orthographic projection of the first connection electrode 41 on the substrate.
  • the shield electrode 53 since the shield electrode 53 is connected to the first power line 52 and has the same potential as the first power line 52 , and the orthographic projection of the shield electrode 53 on the substrate is the same as the orthographic projection of the first connection electrode 41 on the substrate.
  • the orthographic projection at least partially overlaps, so it can effectively shield the key node (second node N2) on the pixel drive circuit.
  • the shape of the anode connection electrode 54 may be a "C" shape.
  • the first end of the anode connection electrode 54 may be connected to the fourth connection electrode 44 through the thirteenth via hole V13 .
  • the two ends can be connected to the third connection electrode 43 through the fourteenth via hole V14. Since the third connection electrode 43 is connected to the second area of the seventh active layer through the via hole, and the fourth connection electrode 44 is connected to the second area of the sixth active layer through the via hole, the anode connection electrode 54 is realized to be respectively By connecting the third connection electrode 43 and the fourth connection electrode 44 to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 respectively, same-pole reset is achieved.
  • anode connection electrode 54 is configured to connect with a subsequently formed anode.
  • the orthographic projection of the anode connection electrode 54 on the substrate at least partially overlaps the orthographic projection of the first initial signal line 47 on the substrate.
  • the anode connection electrode 54 may include a first electrode 54-1, a second electrode 54-2, and a third electrode 54-3 connected to each other.
  • the shape of the second electrode 54 - 2 may be a strip shape with the main body extending along the first direction X, and the shape of the second electrode 54 - 2 may be a strip shape with the main body extending along the second direction Y.
  • the first end of the first electrode 54-1 is connected to the fourth connection electrode 44 through the thirteenth via hole V13, and the second end of the first electrode 54-1 is along the opposite direction of the first direction X. After extending in the direction (towards the direction close to the first initial signal line 47 in this circuit unit), it is connected to the first end of the second electrode 54-2.
  • the second end of the second electrode 54-2 extends in the opposite direction of the second direction Y (toward the direction close to the seventh transistor T7 in this circuit unit) and is connected to the first end of the third electrode 54-3. After the second end of the third electrode 54-3 extends along the first direction .
  • the orthographic projection of the second electrode 54-2 on the substrate at least partially overlaps the orthographic projection of the first initial signal line 47 on the substrate, so that the first initial signal line 47 can play a shielding role to avoid
  • the influence of the anode connection electrode 54 on key nodes in the pixel driving circuit is beneficial to improving display uniformity, and can make full use of the layout space to avoid affecting the light transmittance due to the arrangement of the anode connection electrode 54, thereby improving the display effect.
  • the data signal lines 51 of the N-2th column, the N-1th column, the N+1th column, and the N+2th column are connected to the data fan-out lines in the second circuit area 120, and are formed by data The fanout line provides the data signal.
  • the data signal line 51 in the Nth column can be used as a constant voltage signal line, and the data signal line 51 in the Nth column can extend through the second circuit area 120 to the bonding area and be connected to the bonding power lead in the bonding area.
  • the bonded power leads may be configured to carry a high voltage power signal (VDD) or may be configured to carry a low voltage power signal (VSS).
  • the data signal line 51 of the Nth column may extend to the upper frame of the frame area and the frame power lead in the upper frame. This disclosure is not limited here.
  • the fourth conductive layer pattern of the dummy unit and the fourth conductive layer pattern of the circuit unit may be substantially the same.
  • the subsequent preparation process may include: forming a second flat layer pattern, completing the driving circuit layer, and then preparing the light-emitting structure layer and the packaging structure layer on the driving circuit layer.
  • forming the second flat layer pattern may include: coating a second flat film on the substrate on which the foregoing pattern is formed, patterning the second flat film using a patterning process, and forming a covering fourth conductive layer.
  • the second flat layer is provided with a plurality of twenty-first via holes, and the orthographic projection of the twenty-first via hole on the substrate can be located within the range of the orthographic projection of the anode connection electrode 54 on the substrate.
  • the second flat layer in the twenty-first via hole is removed, exposing the surface of the anode connection electrode 54, and the twenty-first via hole is configured so that the subsequently formed anode is connected to the anode connection electrode 54 through the via hole.
  • preparing the light-emitting structure layer may include: forming an anode pattern, and the anode is connected to the anode connection electrode through a fourteenth via hole.
  • a pixel definition layer pattern is formed, and a pixel opening exposing the anode is provided on the pixel definition layer.
  • the organic light-emitting layer is formed using an evaporation or inkjet printing process, and the organic light-emitting layer is connected to the anode through the pixel opening.
  • a cathode is formed, and the cathode is connected to the organic light-emitting layer.
  • the packaging structure layer may include a stacked first packaging layer, a second packaging layer, and a third packaging layer.
  • the first packaging layer and the third packaging layer may be made of inorganic materials
  • the second packaging layer may be made of Organic material
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the display substrate including the driving circuit layer, the light-emitting structure layer and the packaging structure layer is prepared.
  • the driving circuit layer may at least include a plurality of circuit units and a plurality of dummy units.
  • the circuit units may include pixel driving circuits.
  • the dummy units may include dummy driving circuits, and may be connected to the pixel driving circuit and the dummy driving circuit. The connected first scanning signal line, the second scanning signal line, the light emitting control line, the data signal line, the first power supply line, the first initial signal line and the second initial signal line.
  • the pixel driving circuit may include at least first to seventh transistors
  • the dummy driving circuit may include at least first to seventh transistors
  • the active layer of the first transistor of the dummy driving circuit lacks a channel region
  • the active layer of the seventh transistor lacks a channel region.
  • the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, and a third insulating layer sequentially stacked on the substrate. , a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer and a second planar layer.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, and polyether ether ketone. , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • the materials of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), Can be single layer, multi-layer or composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate.
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer, and the fourth insulating layer is called the interlayer insulation (interlayer insulation). ILD) layer.
  • the first flat layer and the second flat layer may be made of organic materials, such as resin.
  • the active layer can use amorphous indium gallium zinc oxide materials (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), Materials such as hexathiophene or polythiophene, that is, this disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide materials
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • the display substrate provided by the present disclosure sets a first connection line with the main part extending along the first direction in the virtual row, and the first connection line is connected to the main part along the first direction.
  • the first initial signal line extending in the second direction is connected, so that the initial signal line transmitting the first initial signal forms a mesh structure, which not only effectively reduces the resistance of the first initial signal line, but also reduces the voltage drop of the first initial voltage. , and effectively improves the uniformity of the first initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.
  • the present disclosure sets the first connection line in the virtual row, connects some or all of the signal lines in the virtual row with the frame power leads of the frame area, and connects the data signal lines in the virtual column with the bound power leads of the binding area.
  • the connection not only makes the signal lines in the virtual rows and virtual columns rationally utilized, avoiding the waste of display area space, but also greatly reduces the load of transmitting power signals, which is beneficial to improving display uniformity.
  • FIG. 17 is a schematic diagram of the initial signal lines of another mesh structure in the first circuit area according to an exemplary embodiment of the present disclosure.
  • the arrangement of circuit units and virtual units is the same as that shown in FIG. 8 .
  • the second initial signal line 31 may be provided in each unit row and virtual row
  • the first initial signal line 47 may be provided in each unit column
  • the second connection line 80 can be set in each virtual column.
  • the second initial electrode 90 may be disposed in at least one virtual cell in the virtual column.
  • the first end of the second initial electrode 90 is directly connected to the second connection line 80 in the virtual cell.
  • the second end of the initial electrode 90 is connected to the second initial signal line 31 in the virtual unit through via holes and connection blocks, thereby realizing the second initial signal line 31 extending along the first direction X and the second initial signal line 31 extending along the second direction Y.
  • the connection of the extended second connection line 80 causes the second initial signal line 31 and the second connection line 80 to form a mesh structure in the display area for transmitting the second initial signal, which can not only effectively reduce the risk of the second initial signal line.
  • the resistance can reduce the voltage drop of the second initial signal, and can effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the structure of the circuit unit in the present exemplary embodiment may be substantially the same as the structure of the circuit unit in the previous embodiment.
  • this exemplary embodiment shows that the preparation process of the substrate may include:
  • (21) Form the semiconductor layer pattern, the first conductive layer pattern, the second conductive layer pattern and the fourth insulating layer pattern.
  • the preparation process and the formed conductive pattern are basically the same as steps (11) to (14) of the previous embodiment, The difference is that the second conductive layer patterns of the circuit units in the unit rows and the dummy cells in the dummy rows may include second initial signal lines 31 .
  • the third conductive layer pattern is basically the same as the third conductive layer pattern formed in step (15) of the previous embodiment. The difference is that: the third conductive layer pattern of the plurality of virtual cells in the Nth column is
  • the three conductive layers may include second connection lines 80 and second initial electrodes 90, as shown in FIG. 18 .
  • the shape of the second connection line 80 in the Nth column may be a line shape with the main body extending along the second direction Y, and the shape of the second initial electrode 90 of at least one virtual unit may be a shape along the main body.
  • the first end of the second initial electrode 90 is connected to the second connection line 80 in a strip shape extending in the first direction
  • the via hole is connected to the connection block, and on the other hand, is connected to the first region of the seventh active layer through the seventh via hole.
  • connection block in the Nth column is connected to the second initial signal line 31 on the one hand and the second initial electrode 90 through the via hole on the other hand, and the second initial electrode 90 is connected to the second
  • the wires 80 are connected, thus realizing the connection between the second initial signal line 31 extending along the first direction X and the second connection line 80 extending along the second direction Y, so that the second initial signal line 31 and the second connection line 80 forms a mesh structure in the display area for transmitting the second initial signal, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the second initial signal in the display substrate.
  • the uniformity of the signal effectively improves the display uniformity and improves the display quality and display quality.
  • the second initial electrode 90 and the second connection line 80 may be an integral structure connected to each other.
  • the second connection line 80 may be connected to the first region of the first active layer through a via hole to realize inputting the second initial signal to the first pole of the first transistor T1.
  • the display substrate provided by the exemplary embodiment of the present disclosure, by arranging in the virtual column a second connection line with the main body portion extending along the second direction, the second connection line and the second initial signal extending along the first direction along the main body portion.
  • the wire connection allows the initial signal lines that transmit the second initial signal to form a mesh structure, which not only effectively reduces the resistance of the second initial signal line and reduces the voltage drop of the second initial voltage, but also effectively improves the second initial signal line in the display substrate.
  • the uniformity of the initial voltage effectively improves the display uniformity and improves the display quality and display quality.
  • FIG. 19 is a schematic diagram of another initial signal line of a mesh structure in the first circuit area according to an exemplary embodiment of the present disclosure.
  • the arrangement of circuit units and virtual units is the same as that shown in FIG. 8 .
  • the second initial signal line 31 may be provided in the unit row
  • the first connection line 60 may be provided in the dummy row
  • the first initial signal line 47 may be provided in the unit column.
  • the second connection line 80 may be disposed in the virtual column.
  • the first initial electrode 70 may be disposed in at least one virtual cell in the virtual row (except for the virtual cell at the intersection of the virtual row and the virtual column), and the first end of the first initial electrode 70 is connected to the virtual cell where the virtual row is located.
  • the first initial signal line 47 in the unit is directly connected, and the second end of the first initial electrode 70 is connected to the first connection line 60 in the virtual unit through a via hole, thereby realizing the first initial signal line 47 extending along the second direction Y.
  • the connection between the signal line 47 and the first connection line 60 extending along the first direction X causes the first initial signal line 47 and the first connection line 60 to form a mesh structure in the display area for transmitting the first initial signal.
  • the second initial electrode 90 may be disposed in at least one virtual cell in the virtual column (except for the virtual cell at the intersection of the virtual row and the virtual column), and the first end of the second initial electrode 90 is connected to the virtual cell where the virtual column is located.
  • the second connection line 80 in the unit is directly connected, and the second end of the second initial electrode 90 is connected to the second initial signal line 31 in the virtual unit through a via hole, thereby realizing the second initial signal line 31 extending along the first direction X.
  • the connection between the signal line 31 and the second connection line 80 extending along the second direction Y causes the second initial signal line 31 and the second connection line 80 to form a mesh structure in the display area for transmitting the second initial signal.
  • a sixth connection electrode 46 is provided in the virtual unit at the intersection of the virtual row and the virtual column.
  • the structure of the circuit unit in this exemplary embodiment may be substantially the same as that in the previous embodiment.
  • this exemplary embodiment shows that the preparation process of the substrate may include:
  • the third conductive layer pattern is basically the same as the third conductive layer pattern formed in step (15) of the previous embodiment, except that: in the Mth row (except for the Nth column)
  • the third conductive layer of the dummy unit may include a first initial signal line 47 and a first initial electrode 70
  • the third conductive layer of the dummy unit in the Nth column may include a second connection line 80 and a second initial electrode 70
  • the electrode 90 and the third conductive layer of the dummy unit in the Mth row and Nth column may include a second connection line 80 and a sixth connection electrode 46, as shown in FIG. 20 .
  • the first end of the first initial electrode 70 is connected to the first initial signal line 47 , and the first initial electrode 70 After the second end extends along the first direction
  • the connection between the first initial signal line 47 extending in the second direction Y and the first connection line 60 extending along the first direction X enables the first initial signal line 47 and the first connection line 60 to form a mesh transmission in the display area.
  • the mesh structure of the first initial signal is
  • the first end of the second initial electrode 90 is connected to the second connection line 80 , and the second initial electrode 90 After the second end extends along the first direction
  • the sixth connection electrode 46 in the dummy cell of the Mth row and Nth column, is connected to the connection block through the ninth via hole on the one hand, and is connected to the seventh active layer through the seventh via hole on the other hand.
  • the first area connection that is, the sixth connection electrode 46 in the dummy cell in the Mth row and Nth column is only connected to the first connection line 60 and not to the second connection line 80 .
  • the display substrate provided by exemplary embodiments of the present disclosure, on the one hand, by arranging first connection lines with the main body portion extending along the first direction in the virtual row, the first connection line and the first connection line with the main body portion extending along the second direction.
  • the initial signal line is connected so that the initial signal line transmitting the first initial signal forms a mesh structure.
  • the second connection line is connected to the main part.
  • the second initial signal lines extending along the first direction are connected, so that the initial signal lines transmitting the second initial signal form a mesh structure, and at the same time, the initial signal lines transmitting the first initial signal and the initial signal transmitting the second initial signal are realized
  • the mesh layout of the lines not only effectively reduces the resistance of the first initial signal line and the second initial signal line, reduces the voltage drop between the first initial voltage and the second initial voltage, but also effectively improves the first initial signal line in the display substrate.
  • the uniformity of the voltage and the second initial voltage effectively improves the display uniformity and improves the display quality and display quality.
  • the present disclosure can avoid the anode connection electrode from affecting the potential of key nodes of the pixel drive circuit, and is conducive to improving display uniformity. .
  • the present disclosure can at least partially overlap the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the second node N2 of the pixel driving circuit on the substrate, which can not only prevent the corresponding signal from affecting the potential of the key node of the pixel driving circuit, but also The difference in parasitic capacitance in the area where the second node N2 is located in different circuit units can be eliminated, thereby improving display uniformity and display effect.
  • the present disclosure allows the first initial signal from the binding area to be quickly transmitted to the display area, thereby improving the initialization speed and is more conducive to increasing the refresh rate and meeting high-frequency requirements.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process.
  • the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the display substrate of the present disclosure can be applied to other display devices with pixel driving circuits, and the disclosure is not limited here.
  • a first initial signal line extending along the second direction is formed in at least one unit column, and a first connection line extending along the first direction is formed in at least one virtual row.
  • the first initial signal line is connected to the first initial signal line.
  • the first connection lines are connected to form a mesh structure for transmitting the first initial signal; and/or,
  • a second initial signal line extending along the first direction is formed in at least one unit row, and a second connection line extending along the second direction is formed in at least one virtual column.
  • the second initial signal line is connected to
  • the second connection lines are connected to form a mesh structure for transmitting the second initial signal.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，虚拟行包括沿着第一方向(X)依次排列的多个虚拟单元，虚拟列包括沿着第二方向(Y)依次排列的多个虚拟单元；至少一个单元列设置有第一初始信号线(47)，至少一个虚拟行设置有第一连接线(60)，第一初始信号线(47)与第一连接线(60)连接；和/或，至少一个单元行设置有第二初始信号线(31)，至少一个虚拟列设置有第二连接线(80)，第二初始信号线(80)与第二连接线(31)连接。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域、设置在所述显示区域一侧的绑定区域和设置在所述显示区域其它侧的边框区域，所述显示区域包括：构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，所述虚拟行包括沿着第一方向依次排列的多个虚拟单元，所述虚拟列包括沿着第二方向依次排列的多个虚拟单元，所述第一方向与所述第二方向交叉；至少一个单元列设置有沿着所述第二方向延伸的第一初始信号线，至少一个虚拟行设置有沿着所述第一方向延伸的第一连接线，所述第一初始信号线与所述第一连接线连接，形成传输第一初始信号的网状结构；和/或，至少一个单元行设置有沿着所述第一方向延伸的第二初始信号线，至少一个虚拟列设置有沿着所述第二方向延伸的第二连接线，所述第二初始信号线与所述第二连接线连接，形成传输第二初 始信号的网状结构。
在示例性实施方式中，所述虚拟行中的至少一个虚拟单元包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端与所述第一连接线连接。
在示例性实施方式中，所述虚拟列中的至少一个虚拟单元包括第二初始电极，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端与所述第二初始信号线连接。
在示例性实施方式中，所述虚拟行中的至少一个虚拟单元包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端与所述第一连接线连接；所述虚拟列中的至少一个虚拟单元包括第二初始电极，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端与所述第二初始信号线连接。
在示例性实施方式中，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管；在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层，所述半导体层至少包括多个晶体管的有源层，所述第一导电层至少包括所述存储电容的第一极板和多个晶体管的栅电极，所述第二导电层至少包括所述存储电容的第二极板和所述第二初始信号线，所述第三导电层至少包括所述第一初始信号线以及多个晶体管的第一极和第二极。
在示例性实施方式中，所述第二导电层还包括所述第一连接线，所述第三导电层还包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端通过过孔与所述第一连接线连接。
在示例性实施方式中，所述第三导电层还包括第二初始电极和所述第二连接线，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端通过过孔与所述第二初始信号线连接。
在示例性实施方式中，所述第二导电层还包括所述第一连接线，所述第三导电层还包括第一初始电极、第二初始电极和所述第二连接线，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端 通过过孔与所述第一连接线连接，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端通过过孔与所述第二初始信号线连接。
在示例性实施方式中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；所述第一晶体管的第一极与所述第一初始信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第七晶体管的第一极与所述第二初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极和所述第三晶体管的栅电极连接，所述第二晶体管的第二极与所述第三晶体管的第二极和所述第六晶体管的第一极连接，所述第三晶体管的第一极与所述第四晶体管的第二极和所述第五晶体管的第二极连接，所述第六晶体管的第二极与所述第七晶体管的第二极连接。
在示例性实施方式中，所述像素驱动电路还包括阳极连接电极，所述阳极连接电极分别与所述第六晶体管的第二极与所述第七晶体管的第二极连接，所述阳极连接电极在所述基底上的正投影与所述第一初始信号线在所述基底上的正投影至少部分重叠。
在示例性实施方式中，所述阳极连接电极包括第一电极、第二电极和第三电极，所述第一电极的第一端通过过孔与所述第六晶体管的第二极连接，所述第一电极的第二端沿着所述第一方向的反方向延伸后，与所述第二电极的第一端连接，所述第二电极的第二端沿着所述第二方向的反方向延伸后，与所述第三电极的第一端连接，所述第三电极的第二端沿着所述第一方向延伸后，通过过孔与所述第七晶体管的第二极连接，所述第二电极在所述基底上的正投影与所述第一初始信号线在所述基底上的正投影至少部分重叠。
在示例性实施方式中，所述像素驱动电路还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接，所述屏蔽电极在所述基底上的正投影与所述第一晶体管的第二极在所述基底上的正投影至少部分重叠。
在示例性实施方式中，至少一个虚拟单元包括虚拟驱动电路，所述虚拟驱动电路至少包括存储电容以及第一晶体管至第七晶体管，所述存储电容包括第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极 板在所述基底上的正投影至少部分交叠，所述虚拟驱动电路的第一极板和所述虚拟驱动电路的第二极板均与所述第一电源线连接。
在示例性实施方式中，所述虚拟驱动电路中的第一晶体管的有源层缺少沟道区，所述虚拟驱动电路中的第七晶体管的有源层缺少沟道区。
在示例性实施方式中，所述显示区域至少包括第一电路区、第二电路区和第三电路区；所述第一电路区包括多个单元行、多个单元列、至少一个虚拟行和至少一个虚拟列，所述第二电路区设置在所述第一电路区与所述边框区域之间，所述第二电路区包括栅极驱动电路、多个单元行、多个单元列和至少一个虚拟行，所述第三电路区设置在所述第一电路区与所述绑定区域之间，所述第三电路区包括数据扇出线、多个单元行、多个单元列和至少一个虚拟列。
在示例性实施方式中，所述虚拟行中的至少一个虚拟单元至少包括虚拟驱动电路，所述虚拟驱动电路与第一扫描信号线、第二扫描信号线和发光控制线连接，所述虚拟行中的第一扫描信号线、第二扫描信号线和发光控制线沿着所述第一方向延伸到所述边框区域，与所述边框区域中的边框电源引线连接，所述边框电源引线被配置为传输高电压电源信号或者低电压电源信号。
在示例性实施方式中，所述虚拟列中的至少一个虚拟单元至少包括虚拟驱动电路，所述虚拟驱动电路与数据信号线连接，所述虚拟列中的数据信号线沿着所述第二方向延伸到所述绑定区域，与所述绑定区域中的绑定电源引线连接，所述绑定电源引线被配置为传输高电压电源信号或者低电压电源信号。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法。所述显示基板包括显示区域、设置在所述显示区域一侧的绑定区域和设置在所述显示区域其它侧的边框区域，所述显示区域包括：构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，所述虚拟行包括沿着第一方向依次排列的多个虚拟单元，所述虚拟列包括沿着第二方向依次排列的多个虚拟单元，所述第一方向与所述第二方向交叉； 所述制备方法包括：
在至少一个单元列形成沿着所述第二方向延伸的第一初始信号线，在至少一个虚拟行形成沿着所述第一方向延伸的第一连接线，所述第一初始信号线与所述第一连接线连接，形成传输第一初始信号的网状结构；和/或，
在至少一个单元行形成沿着所述第一方向延伸的第二初始信号线，在至少一个虚拟列形成有沿着所述第二方向延伸的第二连接线，所述第二初始信号线与所述第二连接线连接，形成传输第二初始信号的网状结构。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为本公开实施例一种显示基板中发光结构层的平面结构示意图；
图6为本公开实施例一种显示基板中驱动电路层的平面结构示意图；
图7a为本公开示例性实施例一种第一电路区的平面结构示意图；
图7b为本公开示例性实施例一种第二电路区的平面结构示意图；
图7c为本公开示例性实施例一种第三电路区的平面结构示意图；
图8为本公开示例性实施例一种第一电路区的结构示意图；
图9为本公开示例性实施例一种网状结构的初始信号线的示意图；
图10为本公开显示基板形成半导体层图案后的示意图；
图11a和图11b为本公开显示基板形成第一导电层图案后的示意图；
图12a和图12b为本公开显示基板形成第二导电层图案后的示意图；
图13为本公开显示基板形成第四绝缘层图案后的示意图；
图14a和图14b为本公开显示基板形成第三导电层图案后的示意图；
图15为本公开显示基板形成第一平坦层图案后的示意图；
图16a和图16b为本公开显示基板形成第四导电层图案后的示意图；
图17为本公开示例性实施例另一种网状结构的初始信号线的示意图；
图18为本公开显示基板另一种形成第三导电层图案后的示意图；
图19为本公开示例性实施例又一种网状结构的初始信号线的示意图；
图20为本公开显示基板又一种形成第三导电层图案后的示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；        13—第三有源层；
14—第四有源层；       15—第五有源层；        16—第六有源层；
17—第七有源层；       18—断口；              21—第一扫描信号线；
22—第二扫描信号线；   23—发光控制线；        24—第一极板；
31—第二初始信号线；   32—连接块；            33—第二极板；
34—极板连接线；       35—开口；              41—第一连接电极；
42—第二连接电极；     43—第三连接电极；      44—第四连接电极；
45—第五连接电极；     46—第六连接电极；      47—第一初始信号线；
48—极间连接电极；     51—数据信号线；        52—第一连接线；
53—屏蔽电极；         54—阳极连接电极；      60—第一连接线；
70—第一初始电极；     80—第二连接线；        90—第二初始电极；
100—显示区域；        101—基底；             102—驱动电路层；
103—发光结构层；      104—封装层；           110—第一区域；
120—第二区域；        121—第二像素区；       122—栅极电路区；
130—第三区域；        131—第三像素区；       132—扇出线区；
200—绑定区域；        300—边框区域；         301—阳极；
302—像素定义层；      303—有机发光层；       304—阴极；
401—第一封装层；      402—第二封装层；      403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情 况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时 序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij配置为显示动 态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施方式中，显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域100的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。扇出区连接到显示区域，可以至少包括数据扇出线、高电压电源线和低电压电源线，多条数据扇出线被配置为以扇出(Fanout)走线方式连接显示区域的数据信号线，高电压电源线被配置为连接显示区域100的第一电源线(VDD)，低电压电源线被配置为连接边框区域300的第二电源线(VSS)。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以至少包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据扇出线连接。绑定引脚区可以至少包括多个绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描信号线、第二扫描信号线和发光控制线连接。电源线区连接到电路区，可以至少包括电源引线，电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的剖面结构示意图，示意了显示区域四个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底 一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容。发光结构层103可以包括多个子像素，每个子像素可以包括发光器件和像素定义层302，发光器件可以包括阳极301、有机发光层303和阴极304，有机发光层303设置在阳极301和阴极304之间，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图4为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图4所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与8个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与 第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体 管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第二扫描信号线S2连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第二扫描信号线S2时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，以图4中的7个晶体管均为P型晶体管为例，像 素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号使第一晶体管T1和第七晶体管T7导通。第一晶体管T1导通使得第一初始信号线INIT1的第一初始电压提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第七晶体管T7导通使得第二初始信号线INIT2的第二初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5和第六晶体管T6断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动 电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，窄边框和全面屏成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。由于绑定区域中集成电路和绑定焊盘的信号线需要通过数据扇出线以扇出方式才能引入到较宽的显示区域，使得扇形区占用空间较大，导致下边框的宽度较大。由于边框区域需要设置栅极驱动电路和电源引线，且栅极驱动电路和电源引线占用空间较大，导致左右边框的宽度较大。
本公开示例性实施例提供了一种显示基板，采用数据扇出线位于显示区域(Fanout in AA，简称FIAA)结构和栅极驱动电路位于显示区域内(Gate Driver In AA，简称GIA)结构。
图5为本公开示例性实施例一种显示基板中发光结构层的平面结构示意图。如图5所示，在示例性实施方式中，在平行于显示基板的平面上，显示基板的发光结构层可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括一个出射第一颜色光线的第一子像素P1、一个出射第二颜色光线的第二子像素P2和两个出射第三颜色光线的第三子像素P3和第四子像素P4，四个子像素可以均包括发光器件，每个子像素中的发光器件分别与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用水平并 列、竖直并列、正方形(Square)或者钻石形(Diamond)等方式排列。
在一种可能的示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图6为本公开示例性实施例一种显示基板中驱动电路层的平面结构示意图。如图6所示，在示例性实施方式中，在平行于显示基板的平面上，显示区域的驱动电路层可以包括第一电路区110、第二电路区120和第三电路区130，第一电路区110被配置为设置多个电路单元和多个虚拟单元，第二电路区120被配置为设置栅极驱动电路、多个电路单元和多个虚拟单元，第三电路区130被配置为设置多条数据扇出线、多个电路单元和多个虚拟单元。
在示例性实施方式中，第二电路区120可以设置在第一电路区110第一方向X的一侧或者两侧，第二电路区120可以为沿着第二方向Y延伸的条形状，第一方向X与第二方向Y交叉。
在示例性实施方式中，第三电路区130可以设置在第一电路区110第二方向Y的一侧，第三电路区130靠近绑定区域，第三电路区130可以为沿着第一方向X延伸的条形状。
在示例性实施方式中，第一方向X可以是扫描信号线的延伸方向，第二方向Y可以是数据信号线的延伸方向，第一方向X和第二方向Y垂直。
图7a为本公开示例性实施例一种第一电路区的平面结构示意图。如图7a所示，第一电路区可以包括多个电路单元PA和多个虚拟单元DA，多个电路单元PA可以构成多个单元行和多个单元列，多个虚拟单元DA可以构成至少一个虚拟行和至少一个虚拟列。
在示例性实施方式中，单元行可以包括沿着第一方向X依次设置的多个电路单元PA和至少一个虚拟单元DA，单元列可以包括沿着第二方向Y依次设置的多个电路单元PA和至少一个虚拟单元DA。
在示例性实施方式中，虚拟行可以包括沿着第一方向X依次设置的多个虚拟单元DA，虚拟列可以包括沿着第二方向Y依次设置的多个虚拟单元DA。
在示例性实施方式中，至少一个虚拟行可以设置在两个单元行之间，至少一个虚拟列可以设置在两个单元列之间。
在示例性实施方式中，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所连接的发光器件输出相应的电流。
在示例性实施方式中，虚拟单元可以至少包括虚拟驱动电路，虚拟驱动电路被配置为呈现像素驱动电路的形貌和结构，但不输出相应的电流。
图7b为本公开示例性实施例一种第二电路区的平面结构示意图。如图7b所示，第二电路区可以包括第二像素区121和栅极电路区122，栅极电路区122可以设置在第二像素区121远离第一电路区的一侧。第二像素区121可以包括多个电路单元PA和多个虚拟单元DA，栅极电路区122可以包括多个栅极电路单元GA。
在示例性实施方式中，多个电路单元PA可以构成多个单元行和多个单元列，多个虚拟单元DA可以构成至少一个虚拟行。
在示例性实施方式中，第二电路区只设置有虚拟行，没有设置虚拟列。
在示例性实施方式中，第二电路区可以采用密排横向压缩的方式设置多个电路单元PA，压缩出的空间作为栅极电路单元GA的设置空间。由于栅极驱动电路设置在显示区域中的第二电路区，因而有效缩减了显示装置的边框宽度，有效减小了左右边框宽度。
图7c为本公开示例性实施例一种第三电路区的平面结构示意图。如图7c所示，第三电路区可以包括第三像素区131和扇出线区132，扇出线区132可以设置在第三像素区131远离第一电路区的一侧。第三像素区131可以包括多个电路单元PA和多个虚拟单元DA，扇出线区132可以包括多条数据扇出线。
在示例性实施方式中，多个电路单元PA可以构成多个单元行和多个单元列，多个虚拟单元DA可以构成至少一个虚拟列。
在示例性实施方式中，第三电路区只设置有虚拟列，没有设置虚拟行。
在示例性实施方式中，第三电路区可以采用密排纵向压缩的方式设置多个电路单元PA，压缩出的空间作为数据扇出线的设置空间。在示例性实施方式中，多条数据扇出线的一端在第三电路区与多条数据信号线对应连接，多条数据扇出线的另一端延伸到绑定区域后，与集成电路对应连接。由于绑定区域中不需要设置扇形状的斜线，因而缩减了扇出区的宽度，有效减小了下边框宽度。
在示例性实施方式中，第二电路区和第三电路区均采用密排压缩方式设置电路单元，为了保持显示区域中像素驱动电路的一致性，第一电路区也采用与第二电路区和第三电路区相同的密排压缩方式设置电路单元，压缩出的空间设置至少一个虚拟行和至少一个虚拟列。本公开通过在第一电路区设置至少一个虚拟行和至少一个虚拟列，不仅可以保证显示区域显示的均一性，而且可以避免出现闪烁(Flicker)现象。
本公开提供了一种显示基板，包括显示区域、设置在所述显示区域一侧的绑定区域和设置在所述显示区域其它侧的边框区域，所述显示区域包括：构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，所述虚拟行包括沿着第一方向依次排列的多个虚拟单元，所述虚拟列包括沿着第二方向依次排列的多个虚拟单元，所述第一方向与所述第二方向交叉；至少一个单元列设置有沿着所述第二方向延伸的第一初始信号线，至少一个虚拟行设置有沿着所述第一方向延伸的第一连接线，所述第一初始信号线与所述第一连接线连接，形成传输第一初始信号的网状结构；和/或，至少一个单元行设置有沿着所述第一方向延伸的第二初始信号线，至少一个虚拟列设置有沿着所述第二方向延伸的第二连接线，所述第二初始信号线与所述第二连接线连接，形成传输第二初始信号的网状结构。
在一种示例性实施方式中，所述虚拟行中的至少一个虚拟单元包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端与所述第一连接线连接。
在另一种示例性实施方式中，所述虚拟列中的至少一个虚拟单元包括第二初始电极，所述第二初始电极的第一端与所述第二连接线连接，所述第二 初始电极的第二端与所述第二初始信号线连接。
在又一种示例性实施方式中，所述虚拟行中的至少一个虚拟单元包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端与所述第一连接线连接；所述虚拟列中的至少一个虚拟单元包括第二初始电极，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端与所述第二初始信号线连接。
在示例性实施方式中，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管；在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层，所述半导体层至少包括多个晶体管的有源层，所述第一导电层至少包括存储电容的第一极板和多个晶体管的栅电极，所述第二导电层至少包括存储电容的第二极板和所述第二初始信号线，所述第三导电层至少包括所述第一初始信号线以及多个晶体管的第一极和第二极。
在一种示例性实施方式中，所述第二导电层还包括所述第一连接线，所述第三导电层还包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端通过过孔与所述第一连接线连接。
在另一种示例性实施方式中，所述第三导电层还包括第二初始电极和所述第二连接线，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端通过过孔与所述第二初始信号线连接。
在又一种示例性实施方式中，所述第二导电层还包括所述第一连接线，所述第三导电层还包括第一初始电极、第二初始电极和所述第二连接线，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端通过过孔与所述第一连接线连接，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端通过过孔与所述第二初始信号线连接。
在示例性实施方式中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；所述第一晶体管的第一极与所述第一初始信号线连接，所述第四晶体管的第一极与 数据信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第七晶体管的第一极与所述第二初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极和所述第三晶体管的栅电极连接，所述第二晶体管的第二极与所述第三晶体管的第二极和所述第六晶体管的第一极连接，所述第三晶体管的第一极与所述第四晶体管的第二极和所述第五晶体管的第二极连接，所述第六晶体管的第二极与所述第七晶体管的第二极连接。
在示例性实施方式中，至少一个虚拟单元包括虚拟驱动电路，所述虚拟驱动电路至少包括存储电容和第一晶体管至第七晶体管，所述存储电容包括第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述虚拟驱动电路的第一极板和所述虚拟驱动电路的第二极板均与所述第一电源线连接。
在示例性实施方式中，所述虚拟驱动电路还包括极间连接电极，多个晶体管中的第一晶体管的第二极通过过孔与所述第一极板连接，多个晶体管中的第五晶体管的第一极通过过孔与所述第二极板连接，所述极间连接电极分别与所述第一晶体管的第二极和所述第五晶体管的第一极连接。
在示例性实施方式中，所述虚拟驱动电路中的第一晶体管的有源层缺少沟道区，所述虚拟驱动电路中的第七晶体管的有源层缺少沟道区。
图8为本公开示例性实施例一种第一电路区的结构示意图，示意了第一电路区中8个电路单元和7个虚拟单元的平面结构。其中，第M-1行和第M+1行为单元行，分别包括4个电路单元和1个虚拟单元，第M行为虚拟行，包括5个虚拟单元，第N-2列、第N-1列、第N+1列和第N+2列为单元列，分别包括2个电路单元和1个虚拟单元，第N列为虚拟列，包括3个虚拟单元。
如图8所示，在示例性实施方式中，单元行可以至少包括沿着第一方向X依次排列的多个电路单元，多个单元行可以沿着第二方向Y依次设置，单元列可以至少包括沿着第二方向Y依次排列的多个电路单元，多个单元列可以沿着第一方向X依次设置。至少一个电路单元可以包括像素驱动电路，像素驱动电路可以包括多个晶体管和存储电容，像素驱动电路分别与第一扫描信号线21、第二扫描信号线22、发光控制线23、第一初始信号线47、第二 初始信号线31、数据信号线51和第一电源线52连接。在示例性实施方式中，第一扫描信号线21和第二扫描信号线22被配置为分别接收第一扫描信号和第二扫描信号，发光控制线23被配置为接收发光控制信号，数据信号线51被配置为接收数据信号，第一电源线52被配置为接收第一电源信号，第一初始信号线47和第二初始信号线31被配置为分别接收第一初始信号和第二初始信号，第一初始信号可以被配置为对存储电容的第一极板进行初始化(复位)，第二初始信号可以被配置为对发光器件的阳极进行初始化(复位)。
在示例性实施方式中，像素驱动电路中的多个晶体管可以至少包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。第一晶体管T1的第一极与第一初始信号线47连接，第四晶体管T4的第一极与数据信号线51连接，第五晶体管T5的第一极与第一电源线52连接，第七晶体管T7的第一极与第二初始信号线31连接，第一晶体管T1的第二极与第二晶体管T2的第一极和第三晶体管T3的栅电极连接，第二晶体管T2的第二极与第三晶体管T3的第二极和第六晶体管T6的第一极连接，第三晶体管T3的第一极与第四晶体管T4的第二极和第五晶体管T5的第二极连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。
在示例性实施方式中，像素驱动电路还可以包括阳极连接电极54，阳极连接电极54分别与第六晶体管T6的第二极与第七晶体管T7的第二极连接，阳极连接电极54在基底上的正投影与第一初始信号线47在基底上的正投影至少部分重叠。
在示例性实施方式中，阳极连接电极54可以包括第一电极、第二电极和第三电极，第一电极的第一端通过过孔与第六晶体管T6的第二极连接，第一电极的第二端沿着第一方向X的反方向延伸后，与第二电极的第一端连接，第二电极的第二端沿着第二方向Y的反方向延伸后，与第三电极的第一端连接，第三电极的第二端沿着第一方向X延伸后，通过过孔与第七晶体管T7的第二极连接，第二电极在基底上的正投影与第一初始信号线47在基底上的正投影至少部分重叠。
在示例性实施方式中，在垂直于显示基板的平面内，驱动电路层可以至 少包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；半导体层可以至少包括多个晶体管的有源层，第一导电层可以至少包括多个晶体管的栅电极和存储电容的第一极板，第二导电层可以至少包括第一连接线60和存储电容的第二极板，第三导电层可以至少包括第一初始信号线47和第一初始电极70，第四导电层可以至少包括数据信号线51和第一电源线52。
在示例性实施方式中，驱动电路层可以包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第一平坦层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第一平坦层设置在第三导电层与第四导电层之间。
在示例性实施方式中，第一连接线60的形状可以为主体部分沿着第一方向X延伸的线形状，第一初始信号线47的形状可以为主体部分沿着第二方向Y延伸的线形状，第一初始信号线47和第一连接线60通过第一初始电极70相互连接，形成网状结构的初始信号线。本公开中，A沿B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿B方向伸展，且主要部分沿B方向伸展的长度大于次要部分沿其它方向伸展的长度。
图9为本公开示例性实施例一种第一电路区中网状结构的初始信号线的示意图，电路单元和虚拟单元的排布与图8所示排布相同。如图9所示，在示例性实施方式中，第一初始信号线47可以设置在每个单元列和虚拟列中，第一连接线60可以设置在虚拟行中，第二初始信号线31可以设置在每个单元行中。
在示例性实施方式中，第一初始电极70可以设置在虚拟行中的至少一个虚拟单元中，第一初始电极70的第一端与所在虚拟单元中的第一初始信号线47直接连接，第一初始电极70的第二端通过过孔和连接块与所在虚拟单元中的第一连接线60连接，实现了沿着第二方向Y延伸的第一初始信号线47与沿着第一方向X延伸的第一连接线60的连接，使得第一初始信号线47和第一连接线60在显示区域形成网状的传输第一初始信号的网状结构，不仅可 以有效降低第一初始信号线的电阻，减小第一初始信号的压降，而且可以有效提升显示基板中第一初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第一初始信号线47和第一初始电极70可以同层设置，通过同一次图案化工艺同步形成，且为相互连接的一体结构。
在示例性实施方式中，第一初始电极70可以通过过孔与第七有源层的第一区连接，第七有源层是第七晶体管T7的有源层。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以第一电路区中8个电路单元和7个虚拟单元为例，驱动电路层的制备过程可以包括如下操作。
(11)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图10所示。
在示例性实施方式中，电路单元的半导体层可以包括第一晶体管T1的 第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第六有源层16为相互连接的一体结构，第七有源层17可以单独设置。
在示例性实施方式中，第M-1行电路单元中的第一有源层11、第二有源层12、第四有源层14和第七有源层17位于本电路单元的第三有源层13远离第M行电路单元的一侧，第一有源层11和第七有源层17位于第二有源层12和第四有源层14远离第三有源层13的一侧，第M-1行电路单元中的第五有源层15和第六有源层16位于第三有源层13靠近第M行电路单元的一侧。
在示例性实施方式中，第一有源层11的形状可以呈“n”字形，第二有源层12、第五有源层15和第六有源层16的形状可以呈“L”字形，第三有源层13的形状可以呈“几”字形，第四有源层14和第七有源层17的形状可以呈“I”字形。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层11的第二区11-2同时作为第二有源层12的第一区12-1，第三有源层13的第一区13-1同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第一有源层11的第一区11-1、第四有源层14的第一区14-1、第五有源层15的第一区15-1、第六有源层16的第二区16-2、第七有源层17的第一区17-1和第七有源层17的第二区17-2单独设置。
在示例性实施方式中，虚拟单元的半导体层与电路单元的半导体层可以基本上相同，所不同的是，虚拟单元的第一有源层11的第一区11-1和第一有源层11的第二区11-2之间设置有断口18，第七有源层17的第一区17-1和第七有源层17的第二区17-2之间设置有断口18。
在示例性实施方式中，断口18的位置可以与后续形成的第二扫描信号线的位置相对应，使得第一有源层11和第七有源层17只有第一区和第二区，而没有沟道区，即第一晶体管的有源层缺少沟道区，第七晶体管的有源层缺少沟道区，虚拟单元的第一晶体管和第七晶体管不能进行信号传递，形成虚设的第一晶体管和虚设的第七晶体管。本公开通过在虚拟单元设置断开的第一有源层和第七有源层，可以使得虚拟单元中后续形成的第一扫描信号线、 第二扫描信号线和/或发光控制信号线具有较灵活地连接结构，可以较自由地连接到相关直流信号中。例如，第M行中的第一扫描信号线、第二扫描信号线和发光控制信号线可以连接边框区域的边框电源引线，从而大大降低传输电源信号的负载，有利于改善显示均一性。
(12)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图11a和图11b所示，图11b为图11a中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE 1)层。
在示例性实施方式中，电路单元的第一导电层图案可以至少包括第一扫描信号线21、第二扫描信号线22、发光控制线23和存储电容的第一极板24，
在示例性实施方式中，存储电容的第一极板24的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板24在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分重叠。在示例性实施方式中，第一极板24可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22和发光控制线23的形状可以为主体部分沿着第一方向X延伸的线形状。第M-1行电路单元中的第一扫描信号线21和第二扫描信号线22可以位于本电路单元的第一极板24远离第M行电路单元的一侧，第二扫描信号线22位于本电路单元的第一扫描信号线21远离第一极板24的一侧，发光控制线23可以位于本电路单元的第一极板24靠近第M行电路单元的一侧。
在示例性实施方式中，电路单元的第一扫描信号线21设置有向着第二扫描信号线22一侧凸起的栅极块21-1，第一扫描信号线21和栅极块21-1与第二有源层相重叠的区域作为第二晶体管T2的栅电极，形成双栅结构的第二晶体管T2。
在示例性实施方式中，第一扫描信号线21与第四有源层相重叠的区域作为第四晶体管T4的栅电极。第二扫描信号线22与第一有源层相重叠的区域作为双栅结构的第一晶体管T1的栅电极，第二扫描信号线22与第七有源层 相重叠的区域作为第七晶体管T7的栅电极。发光控制线23与第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线23与第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，虚拟单元的第一导电层图案与电路单元的第一导电层图案可以基本上相同，所不同的是，第二扫描信号线22与第一有源层的缺口和第七有源层的缺口相重叠，第一有源层和第七有源层分别为第一晶体管T1的有源层和第七晶体管T7的有源层，相重叠的区域分别形成虚设的第一晶体管T1的栅电极和虚设的第七晶体管T7的栅电极。
在示例性实施方式中，第M-1行和第M+1行中的第一扫描信号线21、第二扫描信号线22、发光控制线23分别与第三电路区130中的栅极驱动电路连接，由栅极驱动电路提供相应的扫描信号和发光控制信号。第M行(虚设行)中的第一扫描信号线21、第二扫描信号线22和发光控制线23可以作为恒压信号线，可以穿过显示区域的第三电路区130延伸到边框区域的左边框和/或右边框，与左边框和/或右边框中设置的边框电源引线连接。在示例性实施方式中，边框电源引线可以被配置为传输高电压电源信号(VDD)或者可以被配置为传输低电压电源信号(VSS)。本公开通过将虚拟行的信号线连接边框区域的边框电源引线，可以大大降低传输高电压电源信号或者低电压电源信号的负载，有利于改善显示均一性。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(13)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图12a和图12b所述，图12b为图12a中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE 2)层。
在示例性实施方式中，电路单元的第二导电层图案至少包括：第二初始 信号线31、连接块32、存储电容的第二极板33和极板连接线34。
在示例性实施方式中，第二初始信号线31的形状可以为主体部分沿着第一方向X延伸的线形状。第M-1行电路单元中的第二初始信号线31可以位于本电路单元的第二扫描信号线22远离第M行电路单元的一侧，第二初始信号线31被配置为通过后续形成的第七晶体管T7的第一极与第七有源层的第一区连接。
在示例性实施方式中，电路单元的连接块32的形状可以为矩形状，设置在第二初始信号线31靠近第二扫描信号线22的一侧，且与第二初始信号线31连接。在示例性实施方式中，连接块32被配置为与后续形成的第六连接电极连接，以实现第二初始信号线31将第二初始信号输入到第七晶体管T7的第一极。
在示例性实施方式中，第二初始信号线31和连接块32可以为相互连接的一体结构。
在示例性实施方式中，第二极板33的轮廓形状可以为矩形状，矩形状的角部可以设置倒角，第二极板33在基底上的正投影与第一极板24在基底上的正投影至少部分重叠，第二极板33作为存储电容的另一个极板，第一极板24和第二极板33构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板33上设置有开口35，开口35可以位于第二极板33的中部。开口35可以为矩形状，使第二极板33形成环形结构。开口35暴露出覆盖第一极板24的第三绝缘层，且第一极板24在基底上的正投影包含开口35在基底上的正投影。在示例性实施方式中，开口35被配置为容置后续形成的第一过孔，第一过孔位于开口35内并暴露出第一极板24，使后续形成的第一晶体管T1的第二极与第一极板24连接。
在示例性实施方式中，极板连接线35可以设置在第二极板33第一方向X或者第一方向X的反方向的一侧，极板连接线35的第一端与本电路单元的第二极板33连接，极板连接线35的第二端沿着第一方向X或者第一方向X的反方向延伸后，与相邻电路单元的第二极板33连接，极板连接线35被配置为使一单元行上相邻电路单元的第二极板相互连接。在示例性实施方式中，通过极板连接线35使一单元行中多个电路单元的第二极板形成相互连接 的一体结构，一体结构的第二极板可以复用为电源信号线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，虚拟单元的第二导电层图案与电路单元的第二导电层图案可以基本上相同，所不同的是，第M行中虚拟单元的第二导电层图案包括第一连接线60，虚拟单元中第一连接线60的位置和形状与电路单元中第二初始信号线31的位置和形状可以基本上相同。
在示例性实施方式中，第M行中虚拟单元的连接块32的形状可以为矩形状，设置在第一连接线60靠近第二扫描信号线22的一侧，且与第一连接线60连接。在示例性实施方式中，连接块32被配置为与后续形成的第一初始电极连接，以实现第一连接线60与第一初始信号线的连接。
第M行中虚拟单元的第一连接线60的形状可以为主体部分沿着第一方向X延伸的线形状。第一连接线60可以位于本虚拟单元的第二扫描信号线22远离第一扫描信号线25的一侧，第一连接线60被配置为通过后续形成的第一初始电极与第一初始信号线连接。
(14)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图13所示。
在示例性实施方式中，电路单元的多个过孔可以至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9和第十过孔V10，
在示例性实施方式中，第一过孔V1在基底上的正投影可以位于第二极板33的开口35在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板24的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板24连接。
在示例性实施方式中，第二过孔V2在基底上的正投影可以位于第二极板33在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板33的表面，第二过孔V2被配置为使后续形成的第五晶体管 的第一极通过该过孔与第二极板33连接。在示例性实施方式中，作为电源过孔的第二过孔V2可以包括多个，多个第二过孔V2可以沿着第二方向Y依次排列，以增加连接可靠性。
在示例性实施方式中，第三过孔V3在基底上的正投影可以位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管的第一极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影可以位于第六有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极通过该过孔与第六有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影可以位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的第四晶体管T4的第一极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影可以位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第六过孔V6被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影可以位于第七有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第七过孔V7被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影可以位于第七有源层的第二区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第二区的表面，第八过孔V8被配置为使后续形成的第七晶体管T7的第二极通过该过孔与第七有源层的第二区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影可以位于连接块32在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出连接块32的表面，第九过孔V9被配置为使后续形成的第七晶体管T7的第一极通过该过孔与连接块32连接。
在示例性实施方式中，第十过孔V10在基底上的正投影可以位于第一有源层的第一区在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第十过孔V10被配置为使后续形成的第一初始信号线通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，虚拟单元的多个过孔图案与电路单元的第二导电层图案可以基本上相同，所不同的是，第M行中虚拟单元的第七过孔V7被配置为使后续形成的第一初始电极通过该过孔与连接块32连接，第九过孔V9被配置为使后续形成的第一初始电极通过该过孔与第七有源层的第一区连接，以实现第一初始信号线与第一连接线的连接。
(15)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图14a和图14b所示，图14b为图14a中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，电路单元的第三导电层至少包括：第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45、第六连接电极46和第一初始信号线47。
在示例性实施方式中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的条形状，第一连接电极41的第一端通过第一过孔V1与第一极 板24连接，第一连接电极41的第二端通过第六过孔V6与第一有源层的第二区(也是第二有源层的第一区)连接。在示例性实施方式中，第一连接电极41可以同时作为第一晶体管T1的第二极和第二晶体管T2的第一极，使第一极板24、第一晶体管T1的第二极和第二晶体管T2的第一极(即像素驱动电路的第二节点N2)具有相同的电位。
在示例性实施方式中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的条形状，第二连接电极42的第一端可以通过第三过孔V3与第五有源层的第一区连接，第二连接电极42的第二端可以通过多个第二过孔V2与第二极板33连接。在示例性实施方式中，第二连接电极42可以作为第五晶体管T5的第一极，使第五晶体管T5的第一极和第二极板33具有相同的电位，第二连接电极42被配置为与后续形成的第一电源线连接。
在示例性实施方式中，第三连接电极43的形状可以为多边形状，第三连接电极43可以通过第八过孔V8与第七有源层的第二区连接。在示例性实施方式中，第三连接电极43可以作为第七晶体管T7的第二极，第三连接电极43被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第四连接电极44的形状可以为多边形状，第四连接电极44可以通过第四过孔V4与第六有源层的第二区连接。在示例性实施方式中，第四连接电极44可以作为第六晶体管T6的第二极，第四连接电极44被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第五连接电极45的形状可以为主体部分沿着第二方向Y延伸的条形状，第五连接电极45可以通过第五过孔V5与第四有源层的第一区连接。在示例性实施方式中，第五连接电极45可以作为第四晶体管T4的第一极，第五连接电极45被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第六连接电极46的形状可以为主体部分沿着第一方向X延伸的条形状，第六连接电极46的第一端通过第九过孔V9与连接块32连接，第六连接电极46的第二端通过第七过孔V7与第七有源层的第一区连接，由于连接块32与第二初始信号线31连接，因而实现了第二初始信号线31与第七有源层的第一区的连接。在示例性实施方式中，第六连接电极46可以作为第七晶体管T7的第一极，使得第二初始信号线31和第七晶体管 T7的第一极具有相同的电位，实现第二初始信号线31将第二初始信号输入到第七晶体管T7的第一极。
在示例性实施方式中，第一初始信号线47的形状可以为主体部分沿着第二方向Y延伸的线形状，第一初始信号线47可以通过第十过孔V10与第一有源层的第一区连接，实现第一初始信号线47将第一初始信号输入到第一晶体管T1的第一极。本公开通过设置纵向贯通显示区域的第一初始信号线47，使得来自绑定区域的第一初始信号可以快速传输到显示区域，提高了初始化速度，更有利于提高刷新率，满足高频需求。
在示例性实施方式中，虚拟单元的第三导电层与电路单元的第三导电层可以基本上相同，所不同的是，虚拟单元的第三导电层还包括极间连接电极48，第M行中至少一个虚拟单元的第三导电层还包括第一初始电极70。
在示例性实施方式中，极间连接电极48的形状可以为矩形状，极间连接电极48的第一端与第一连接电极41连接，极间连接电极48的第二端与第二连接电极42连接。由于第一连接电极41与第一极板24连接，第二连接电极42与第二极板33连接，因而通过极间连接电极48可以使得虚拟单元的第一极板24和第二极板33具有相同的电位。由于第二连接电极42被配置为与后续形成的第一电源线连接，因而虚拟单元的第一极板24、第二极板33和第一电源线具有相同的电位，即像素驱动电路的第二节点N2与第一电源线具有相同的电位，可以消除因虚拟单元的第二节点N2浮设(floating)对显示的影响，提高显示品质。
在示例性实施方式中，虚拟单元的第一连接电极41、第二连接电极42和极间连接电极48可以为相互连接的一体结构。
在示例性实施方式中，第M行中虚拟单元的第一初始电极70的位置和形状可以与电路单元的第六连接电极46的位置和形状基本上相同，所不同的是，第一初始电极70与第一初始信号线47连接。
在示例性实施方式中，第一初始电极70的形状可以为主体部分沿着第一方向X延伸的条形状，第一初始电极70的第一端与第一初始信号线47连接，第一初始电极70的第二端沿着第一方向X延伸后，一方面通过第九过孔V9与连接块32连接，另一方面通过第七过孔V7与第七有源层的第一区连接。
在示例性实施方式中，由于第M行中的连接块一方面与第M行中的第一连接线60连接，另一方面通过过孔与第一初始电极70连接，而第一初始电极70与第一初始信号线47连接，因而实现了沿着第二方向Y延伸的第一初始信号线47与沿着第一方向X延伸的第一连接线60的连接，使得第一初始信号线47和第一连接线60在显示区域形成网状的传输第一初始信号的网状结构，不仅可以有效降低第一初始信号线的电阻，减小第一初始信号的压降，而且可以有效提升显示基板中第一初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第一初始电极70和第一初始信号线47可以为相互连接的一体结构。
(16)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦层上设置有多个过孔，如图15所示。
在示例性实施方式中，电路单元的多个过孔至少包括：第十一过孔V11、第十二过孔V12、第十三过孔V13和第十四过孔V14。
在示例性实施方式中，第十一过孔V11在基底上的正投影可以位于第五连接电极45在基底上的正投影的范围之内，第十一过孔V11内的第一平坦层被去掉，暴露出第五连接电极45的表面，第十一过孔V11被配置为使后续形成的数据信号线通过该过孔与第五连接电极45连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影可以位于第二连接电极42在基底上的正投影的范围之内，第十二过孔V12内的第一平坦层被去掉，暴露出第二连接电极42的表面，第十二过孔V12被配置为使后续形成的第一电源线通过该过孔与第二连接电极42连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影可以位于第四连接电极44在基底上的正投影的范围之内，第十三过孔V13内的第一平坦层被去掉，暴露出第四连接电极44的表面，第十三过孔V13被配置为使后续形成的阳极连接电极通过该过孔与第四连接电极44连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影可以位于第三 连接电极43在基底上的正投影的范围之内，第十四过孔V14内的第一平坦层被去掉，暴露出第三连接电极43的表面，第十四过孔V14被配置为使后续形成的阳极连接电极通过该过孔与第三连接电极43连接。
在示例性实施方式中，虚拟单元的多个过孔图案与电路单元的多个过孔图案可以基本上相同。
(17)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图16a和图16b所示，图16b为图16a中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，电路单元的第四导电层至少包括：数据信号线51、第一电源线52、屏蔽电极53和阳极连接电极54。
在示例性实施方式中，数据信号线51的形状可以为主体部分沿着第二方向Y延伸的线形状，数据信号线51可以通过第十一过孔V11与第五连接电极45连接。由于第五连接电极45通过过孔与第四有源层的第一区连接，因而实现了数据信号线51通过第五连接电极45将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，第一电源线52的形状可以为主体部分沿着第二方向Y延伸的线形状，第一电源线52可以通过第十二过孔V12与第二连接电极42连接。由于第二连接电极42通过过孔与第五有源层的第一区和第二极板33连接，因而实现了第一电源线52通过第二连接电极42将第一电源信号写入第五晶体管T5的第一极，且第二极板33和第一电源线52具有相同的电位。
在示例性实施方式中，屏蔽电极53的形状可以为矩形状，设置在第一电源线52靠近第一连接电极41的一侧，且与第一电源线52连接，屏蔽电极53在基底上的正投影与第一连接电极41在基底上的正投影至少部分重叠。在示例性实施方式中，由于屏蔽电极53与第一电源线52连接，具有与第一电源线52相同的电位，且屏蔽电极53在基底上的正投影与第一连接电极41在基底上的正投影至少部分重叠，因而可以有效屏蔽像素驱动电路上的关键 节点(第二节点N2)，不仅可以避免相应信号(如数据电压跳变信号)影响像素驱动电路的关键节点的电位，而且可以消除不同电路单元中第二节点N2所在区域的寄生电容的差异，提高了显示均一性，提高了显示效果。
在示例性实施方式中，阳极连接电极54的形状可以为“C”字形，阳极连接电极54的第一端可以通过第十三过孔V13与第四连接电极44连接，阳极连接电极54的第二端可以通过第十四过孔V14与第三连接电极43连接。由于第三连接电极43通过过孔与第七有源层的第二区连接，第四连接电极44通过过孔与第六有源层的第二区连接连接，因而实现了阳极连接电极54分别通过第三连接电极43和第四连接电极44分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接，实现了同极复位。在示例性实施方式中，阳极连接电极54被配置为与后续形成的阳极连接。
在示例性实施方式中，阳极连接电极54在基底上的正投影与第一初始信号线47在基底上的正投影至少部分重叠。
在示例性实施方式中，阳极连接电极54可以包括相互连接的第一电极54-1、第二电极54-2和第三电极54-3，第一电极54-1和第三电极54-3的形状可以为主体部分沿着第一方向X延伸的条形状，第二电极54-2的形状可以为主体部分沿着第二方向Y延伸的条形状。
在示例性实施方式中，第一电极54-1的第一端通过第十三过孔V13与第四连接电极44连接，第一电极54-1的第二端沿着第一方向X的反方向(向着靠近本电路单元中的第一初始信号线47的方向)延伸后，与第二电极54-2的第一端连接。第二电极54-2的第二端沿着第二方向Y的反方向(向着靠近本电路单元中第七晶体管T7的方向)延伸后，与第三电极54-3的第一端连接。第三电极54-3的第二端沿着第一方向X(向着远离本电路单元中的第一初始信号线47的方向)延伸后，通过第十四过孔V14与第三连接电极43连接。
在示例性实施方式中，第二电极54-2在基底上的正投影与第一初始信号线47在基底上的正投影至少部分重叠，使得第一初始信号线47可以起到屏蔽作用，避免阳极连接电极54对像素驱动电路中关键节点的影响，有利于改善显示均一性，而且可以充分利用布局空间，避免因设置阳极连接电极54 影响光透过率，提高了显示效果。
在示例性实施方式中，第N-2列、第N-1列、第N+1列和第N+2列的数据信号线51与第二电路区120中的数据扇出线连接，由数据扇出线提供数据信号。第N列的数据信号线51可以作为恒压信号线，第N列的数据信号线51可以穿过第二电路区120延伸到绑定区域，与绑定区域中的绑定电源引线连接。在示例性实施方式中，绑定电源引线可以被配置为传输高电压电源信号(VDD)或者可以被配置为传输低电压电源信号(VSS)。本公开通过将虚拟列的数据信号线连接绑定区域的绑定电源引线，可以大大降低传输高电压电源信号或者低电压电源信号的负载，有利于改善显示均一性。
在一些可能的示例性实施方式中，第N列的数据信号线51可以延伸到边框区域的上边框，与上边框中的边框电源引线，本公开在此不做限定。
在示例性实施方式中，虚拟单元的第四导电层图案与电路单元的第四导电层图案可以基本上相同。
后续制备过程可以包括：形成第二平坦层图案，完成驱动电路层，随后在驱动电路层上制备发光结构层和封装结构层。
在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层的第二平坦层，第二平坦层上设置有多个第二十一过孔，第二十一过孔在基底上的正投影可以位于阳极连接电极54在基底上的正投影的范围之内，第二十一过孔内的第二平坦层被去掉，暴露出阳极连接电极54的表面，第二十一过孔配置为使后续形成的阳极通过该过孔与阳极连接电极54连接。
在示例性实施方式中，制备发光结构层可以包括：形成阳极图案，阳极通过第十四过孔与阳极连接电极连接。形成像素定义层图案，像素定义层上设置有暴露出阳极的像素开口。采用蒸镀或喷墨打印工艺形成有机发光层，有机发光层通过像素开口与阳极连接。形成阴极，阴极与有机发光层连接。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可 以保证外界水汽无法进入发光结构层。
至此，制备完成包括驱动电路层、发光结构层和封装结构层的显示基板。在平行于显示基板的平面内，驱动电路层可以至少包括多个电路单元和多个虚拟单元，电路单元可以包括像素驱动电路，虚拟单元可以包括虚拟驱动电路，以及与像素驱动电路和虚拟驱动电路连接的第一扫描信号线、第二扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。
在示例性实施方式中，像素驱动电路可以至少包括第一晶体管至第七晶体管，虚拟驱动电路可以至少包括第一晶体管至第七晶体管，虚拟驱动电路第一晶体管的有源层缺少沟道区，第七晶体管的有源层缺少沟道区。
在示例性实施方式中，在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、 硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
从以上描述的显示基板的结构以及制备过程可以看出，本公开提供的显示基板，通过在虚拟行中设置主体部分沿着第一方向延伸的第一连接线，第一连接线与主体部分沿着第二方向延伸的第一初始信号线连接，使得传输第一初始信号的初始信号线形成网状结构，不仅有效降低了第一初始信号线的电阻，减小了第一初始电压的压降，而且有效提升了显示基板中第一初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开通过将第一连接线设置在虚拟行中，将虚拟行中的部分或全部信号线与边框区域的边框电源引线连接，将虚拟列中的数据信号线与绑定区域的绑定电源引线连接，不仅使得虚拟行和虚拟列中的信号线得到合理利用，避免了显示区域空间的浪费，而且可以大大降低传输电源信号的负载，有利于改善显示均一性。
图17为本公开示例性实施例第一电路区中另一种网状结构的初始信号线的示意图，电路单元和虚拟单元的排布与图8所示排布相同。如图17所示，在示例性实施方式中，第二初始信号线31可以设置在每个单元行和虚拟行中，第一初始信号线47可以设置在每个单元列中，第二连接线80可以设置在每个虚拟列中。
在示例性实施方式中，第二初始电极90可以设置在虚拟列中的至少一个虚拟单元中，第二初始电极90的第一端与所在虚拟单元中的第二连接线80直接连接，第二初始电极90的第二端通过过孔和连接块与所在虚拟单元中的第二初始信号线31连接，实现了沿着第一方向X延伸的第二初始信号线31与沿着第二方向Y延伸的第二连接线80的连接，使得第二初始信号线 31和第二连接线80在显示区域形成网状的传输第二初始信号的网状结构，不仅可以有效降低第二初始信号线的电阻，减小第二初始信号的压降，而且可以有效提升显示基板中第二初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，本示例性实施例中电路单元的结构与前述实施例中电路单元的结构可以基本上相同。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括：
(21)形成半导体层图案、第一导电层图案、第二导电层图案和第四绝缘层图案，制备过程和所形成导电图案与前述实施例步骤(11)至步骤(14)基本上相同，所不同的是，单元行中的电路单元和虚拟行中的虚拟单元的第二导电层图案均可以包括第二初始信号线31。
(22)形成第三导电层图案，第三导电层图案与前述实施例步骤(15)中形成的第三导电层图案基本上相同，所不同的是：第N列中多个虚拟单元的第三导电层可以包括第二连接线80和第二初始电极90，如图18所示。
在示例性实施方式中，第N列中第二连接线80的形状可以为主体部分沿着第二方向Y延伸的线形状，至少一个虚拟单元的第二初始电极90的形状可以为主体部分沿着第一方向X延伸的条形状，第二初始电极90的第一端与第二连接线80连接，第二初始电极90的第二端沿着第一方向X延伸后，一方面通过第九过孔与连接块连接，另一方面通过第七过孔与第七有源层的第一区连接。
在示例性实施方式中，由于第N列中的连接块一方面与第二初始信号线31连接，另一方面通过过孔与第二初始电极90连接，而第二初始电极90与第二连接线80连接，因而实现了沿着第一方向X延伸的第二初始信号线31与沿着第二方向Y延伸的第二连接线80的连接，使得第二初始信号线31和第二连接线80在显示区域形成网状的传输第二初始信号的网状结构，不仅可以有效降低第二初始信号线的电阻，减小第二初始信号的压降，而且可以有效提升显示基板中第二初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第二初始电极90和第二连接线80可以为相互连 接的一体结构。
在示例性实施方式中，第二连接线80可以通过过孔与第一有源层的第一区连接，以实现将第二初始信号输入到第一晶体管T1的第一极。
(23)形成第一平坦层图案和第四导电层图案，制备过程和所形成的图案与前述实施例步骤(16)至步骤(17)基本上相同，这里不再赘述。
本公开示例性实施例所提供的显示基板，通过在虚拟列中设置主体部分沿着第二方向延伸的第二连接线，第二连接线与主体部分沿着第一方向延伸的第二初始信号线连接，使得传输第二初始信号的初始信号线形成网状结构，不仅有效降低了第二初始信号线的电阻，减小了第二初始电压的压降，而且有效提升了显示基板中第二初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
图19为本公开示例性实施例第一电路区中又一种网状结构的初始信号线的示意图，电路单元和虚拟单元的排布与图8所示排布相同。如图19所示，在示例性实施方式中，第二初始信号线31可以设置在单元行中，第一连接线60可以设置在虚拟行中，第一初始信号线47可以设置在单元列中，第二连接线80可以设置在虚拟列中。
在示例性实施方式中，第一初始电极70可以设置在虚拟行中的至少一个虚拟单元中(除了虚拟行和虚拟列交汇处的虚拟单元)，第一初始电极70的第一端与所在虚拟单元中的第一初始信号线47直接连接，第一初始电极70的第二端通过过孔与所在虚拟单元中的第一连接线60连接，实现了沿着第二方向Y延伸的第一初始信号线47与沿着第一方向X延伸的第一连接线60的连接，使得第一初始信号线47和第一连接线60在显示区域形成网状的传输第一初始信号的网状结构。
在示例性实施方式中，第二初始电极90可以设置在虚拟列中的至少一个虚拟单元中(除了虚拟行和虚拟列交汇处的虚拟单元)，第二初始电极90的第一端与所在虚拟单元中的第二连接线80直接连接，第二初始电极90的第二端通过过孔与所在虚拟单元中的第二初始信号线31连接，实现了沿着第一方向X延伸的第二初始信号线31与沿着第二方向Y延伸的第二连接线80的连接，使得第二初始信号线31和第二连接线80在显示区域形成网状的传 输第二初始信号的网状结构。
在示例性实施方式中，虚拟行和虚拟列交汇处的虚拟单元中设置有第六连接电极46，本示例性实施例中电路单元的结构与前述实施例中电路单元的结构可以基本上相同。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括：
(31)形成半导体层图案、第一导电层图案、第二导电层图案和第四绝缘层图案，制备过程和所形成导电图案与前述实施例步骤(11)至步骤(14)基本上相同，这里不再赘述。
(32)形成第三导电层图案，第三导电层图案与前述实施例步骤(15)中形成的第三导电层图案基本上相同，所不同的是：第M行中(除了第N列)虚拟单元的第三导电层可以包括第一初始信号线47和第一初始电极70，第N列中(除了第M行)虚拟单元的第三导电层可以包括第二连接线80和第二初始电极90，第M行、第N列的虚拟单元的第三导电层可以包括第二连接线80和第六连接电极46，如图20所示。
在示例性实施方式中，第M行的至少一个虚拟单元(除了位于第N列的虚拟单元)中，第一初始电极70的第一端与第一初始信号线47连接，第一初始电极70的第二端沿着第一方向X延伸后，一方面通过第九过孔与连接块连接，另一方面通过第七过孔与第七有源层的第一区连接，因而实现了沿着第二方向Y延伸的第一初始信号线47与沿着第一方向X延伸的第一连接线60的连接，使得第一初始信号线47和第一连接线60在显示区域形成网状的传输第一初始信号的网状结构。
在示例性实施方式中，第N列的至少一个虚拟单元(除了位于第M行的虚拟单元)中，第二初始电极90的第一端与第二连接线80连接，第二初始电极90的第二端沿着第一方向X延伸后，一方面通过第九过孔与连接块连接，另一方面通过第七过孔与第七有源层的第一区连接，因而实现了沿着第一方向X延伸的第二初始信号线31与沿着第二方向Y延伸的第二连接线80的连接，使得第二初始信号线31和第二连接线80在显示区域形成网状的传输第二初始信号的网状结构。
在示例性实施方式中，第M行、第N列的虚拟单元中，第六连接电极 46一方面通过第九过孔与连接块连接，另一方面通过第七过孔与第七有源层的第一区连接，即第M行、第N列的虚拟单元中的第六连接电极46只与第一连接线60连接，而不与第二连接线80连接。
(33)形成第一平坦层图案和第四导电层图案，制备过程和所形成的图案与前述实施例步骤(16)至步骤(17)基本上相同，这里不再赘述。
本公开示例性实施例所提供的显示基板，一方面通过在虚拟行中设置主体部分沿着第一方向延伸的第一连接线，第一连接线与主体部分沿着第二方向延伸的第一初始信号线连接，使得传输第一初始信号的初始信号线形成网状结构，另一方面通过在虚拟列中设置主体部分沿着第二方向延伸的第二连接线，第二连接线与主体部分沿着第一方向延伸的第二初始信号线连接，使得传输第二初始信号的初始信号线形成网状结构，同时实现了传输第一初始信号的初始信号线和传输第二初始信号的初始信号线的网状布局，不仅有效降低了第一初始信号线和第二初始信号线的电阻，减小了第一初始电压和第二初始电压的压降，而且有效提升了显示基板中第一初始电压和第二初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
本公开通过设置阳极连接电极在基底上的正投影与第一初始信号线在基底上的正投影至少部分重叠，可以避免阳极连接电极影响像素驱动电路的关键节点的电位，有利于改善显示均一性。
本公开通过设置屏蔽电极，屏蔽电极在基底上的正投影与像素驱动电路的第二节点N2在基底上的正投影至少部分重叠，不仅可以避免相应信号影响像素驱动电路的关键节点的电位，而且可以消除不同电路单元中第二节点N2所在区域的寄生电容的差异，提高了显示均一性，提高了显示效果。
本公开通过设置纵向贯通显示区域的第一初始信号线，使得来自绑定区域的第一初始信号可以快速传输到显示区域，提高了初始化速度，更有利于提高刷新率，满足高频需求。
本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公 开在此不做限定。
本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板可以包括显示区域、设置在所述显示区域一侧的绑定区域和设置在所述显示区域其它侧的边框区域，所述显示区域可以包括：构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，所述虚拟行包括沿着第一方向依次排列的多个虚拟单元，所述虚拟列包括沿着第二方向依次排列的多个虚拟单元，所述第一方向与所述第二方向交叉；所述制备方法可以包括：
在至少一个单元列形成沿着所述第二方向延伸的第一初始信号线，在至少一个虚拟行形成沿着所述第一方向延伸的第一连接线，所述第一初始信号线与所述第一连接线连接，形成传输第一初始信号的网状结构；和/或，
在至少一个单元行形成沿着所述第一方向延伸的第二初始信号线，在至少一个虚拟列形成有沿着所述第二方向延伸的第二连接线，所述第二初始信号线与所述第二连接线连接，形成传输第二初始信号的网状结构。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (19)

  1. 一种显示基板，包括显示区域、设置在所述显示区域一侧的绑定区域和设置在所述显示区域其它侧的边框区域，所述显示区域包括：构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，所述虚拟行包括沿着第一方向依次排列的多个虚拟单元，所述虚拟列包括沿着第二方向依次排列的多个虚拟单元，所述第一方向与所述第二方向交叉；至少一个单元列设置有沿着所述第二方向延伸的第一初始信号线，至少一个虚拟行设置有沿着所述第一方向延伸的第一连接线，所述第一初始信号线与所述第一连接线连接，形成传输第一初始信号的网状结构；和/或，至少一个单元行设置有沿着所述第一方向延伸的第二初始信号线，至少一个虚拟列设置有沿着所述第二方向延伸的第二连接线，所述第二初始信号线与所述第二连接线连接，形成传输第二初始信号的网状结构。
  2. 根据权利要求1所述的显示基板，其中，所述虚拟行中的至少一个虚拟单元包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端与所述第一连接线连接。
  3. 根据权利要求1所述的显示基板，其中，所述虚拟列中的至少一个虚拟单元包括第二初始电极，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端与所述第二初始信号线连接。
  4. 根据权利要求1所述的显示基板，其中，所述虚拟行中的至少一个虚拟单元包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端与所述第一连接线连接；所述虚拟列中的至少一个虚拟单元包括第二初始电极，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端与所述第二初始信号线连接。
  5. 根据权利要求1至4任一项所述的显示基板，其中，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括存储电容和多个晶体管；在垂直于显示基板的平面内，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层，所述半导体层至少包括多个晶 体管的有源层，所述第一导电层至少包括所述存储电容的第一极板和多个晶体管的栅电极，所述第二导电层至少包括所述存储电容的第二极板和所述第二初始信号线，所述第三导电层至少包括所述第一初始信号线以及多个晶体管的第一极和第二极。
  6. 根据权利要求5所述的显示基板，其中，所述第二导电层还包括所述第一连接线，所述第三导电层还包括第一初始电极，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端通过过孔与所述第一连接线连接。
  7. 根据权利要求5所述的显示基板，其中，所述第三导电层还包括第二初始电极和所述第二连接线，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端通过过孔与所述第二初始信号线连接。
  8. 根据权利要求5所述的显示基板，其中，所述第二导电层还包括所述第一连接线，所述第三导电层还包括第一初始电极、第二初始电极和所述第二连接线，所述第一初始电极的第一端与所述第一初始信号线连接，所述第一初始电极的第二端通过过孔与所述第一连接线连接，所述第二初始电极的第一端与所述第二连接线连接，所述第二初始电极的第二端通过过孔与所述第二初始信号线连接。
  9. 根据权利要求5所述的显示基板，其中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；所述第一晶体管的第一极与所述第一初始信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第五晶体管的第一极与第一电源线连接，所述第七晶体管的第一极与所述第二初始信号线连接，所述第一晶体管的第二极与所述第二晶体管的第一极和所述第三晶体管的栅电极连接，所述第二晶体管的第二极与所述第三晶体管的第二极和所述第六晶体管的第一极连接，所述第三晶体管的第一极与所述第四晶体管的第二极和所述第五晶体管的第二极连接，所述第六晶体管的第二极与所述第七晶体管的第二极连接。
  10. 根据权利要求9所述的显示基板，其中，所述像素驱动电路还包括阳极连接电极，所述阳极连接电极分别与所述第六晶体管的第二极与所述第 七晶体管的第二极连接，所述阳极连接电极在所述基底上的正投影与所述第一初始信号线在所述基底上的正投影至少部分重叠。
  11. 根据权利要求10所述的显示基板，其中，所述阳极连接电极包括第一电极、第二电极和第三电极，所述第一电极的第一端通过过孔与所述第六晶体管的第二极连接，所述第一电极的第二端沿着所述第一方向的反方向延伸后，与所述第二电极的第一端连接，所述第二电极的第二端沿着所述第二方向的反方向延伸后，与所述第三电极的第一端连接，所述第三电极的第二端沿着所述第一方向延伸后，通过过孔与所述第七晶体管的第二极连接，所述第二电极在所述基底上的正投影与所述第一初始信号线在所述基底上的正投影至少部分重叠。
  12. 根据权利要求9所述的显示基板，其中，所述像素驱动电路还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接，所述屏蔽电极在所述基底上的正投影与所述第一晶体管的第二极在所述基底上的正投影至少部分重叠。
  13. 根据权利要求9所述的显示基板，其中，至少一个虚拟单元包括虚拟驱动电路，所述虚拟驱动电路至少包括存储电容以及第一晶体管至第七晶体管，所述存储电容包括第一极板和第二极板，所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影至少部分交叠，所述虚拟驱动电路的第一极板和所述虚拟驱动电路的第二极板均与所述第一电源线连接。
  14. 根据权利要求13所述的显示基板，其中，所述虚拟驱动电路中的第一晶体管的有源层缺少沟道区，所述虚拟驱动电路中的第七晶体管的有源层缺少沟道区。
  15. 根据权利要求1至4任一项所述的显示基板，其中，所述显示区域至少包括第一电路区、第二电路区和第三电路区；所述第一电路区包括多个单元行、多个单元列、至少一个虚拟行和至少一个虚拟列，所述第二电路区设置在所述第一电路区与所述边框区域之间，所述第二电路区包括栅极驱动电路、多个单元行、多个单元列和至少一个虚拟行，所述第三电路区设置在所述第一电路区与所述绑定区域之间，所述第三电路区包括数据扇出线、多 个单元行、多个单元列和至少一个虚拟列。
  16. 根据权利要求15所述的显示基板，其中，所述虚拟行中的至少一个虚拟单元至少包括虚拟驱动电路，所述虚拟驱动电路与第一扫描信号线、第二扫描信号线和发光控制线连接，所述虚拟行中的第一扫描信号线、第二扫描信号线和发光控制线沿着所述第一方向延伸到所述边框区域，与所述边框区域中的边框电源引线连接，所述边框电源引线被配置为传输高电压电源信号或者低电压电源信号。
  17. 根据权利要求15所述的显示基板，其中，所述虚拟列中的至少一个虚拟单元至少包括虚拟驱动电路，所述虚拟驱动电路与数据信号线连接，所述虚拟列中的数据信号线沿着所述第二方向延伸到所述绑定区域，与所述绑定区域中的绑定电源引线连接，所述绑定电源引线被配置为传输高电压电源信号或者低电压电源信号。
  18. 一种显示装置，包括如权利要求1至17任一项所述的显示基板。
  19. 一种显示基板的制备方法，所述显示基板包括显示区域、设置在所述显示区域一侧的绑定区域和设置在所述显示区域其它侧的边框区域，所述显示区域包括：构成多个单元行和多个单元列的多个电路单元，以及构成至少一个虚拟行和/或至少一个虚拟列的多个虚拟单元，所述虚拟行包括沿着第一方向依次排列的多个虚拟单元，所述虚拟列包括沿着第二方向依次排列的多个虚拟单元，所述第一方向与所述第二方向交叉；所述制备方法包括：
    在至少一个单元列形成沿着所述第二方向延伸的第一初始信号线，在至少一个虚拟行形成沿着所述第一方向延伸的第一连接线，所述第一初始信号线与所述第一连接线连接，形成传输第一初始信号的网状结构；和/或，
    在至少一个单元行形成沿着所述第一方向延伸的第二初始信号线，在至少一个虚拟列形成有沿着所述第二方向延伸的第二连接线，所述第二初始信号线与所述第二连接线连接，形成传输第二初始信号的网状结构。
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