WO2023206217A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023206217A1
WO2023206217A1 PCT/CN2022/089822 CN2022089822W WO2023206217A1 WO 2023206217 A1 WO2023206217 A1 WO 2023206217A1 CN 2022089822 W CN2022089822 W CN 2022089822W WO 2023206217 A1 WO2023206217 A1 WO 2023206217A1
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WIPO (PCT)
Prior art keywords
lead
connection
line
data signal
electrode
Prior art date
Application number
PCT/CN2022/089822
Other languages
English (en)
French (fr)
Inventor
于子阳
王梦奇
王世龙
蒋志亮
胡明
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001013.3A priority Critical patent/CN115398641B/zh
Priority to CN202311189485.9A priority patent/CN116981295A/zh
Priority to PCT/CN2022/089822 priority patent/WO2023206217A1/zh
Publication of WO2023206217A1 publication Critical patent/WO2023206217A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically relates to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a display area and a binding area located on one side of the display area.
  • the display area includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns.
  • data signal lines and a plurality of data connection lines include a first connection line extending along a first direction and a second connection line extending along a second direction, the first connection line and the The second connection line is connected, and the first direction and the second direction intersect; in at least one circuit unit, the data signal line is connected to the first connection line through a first connection hole, and in the first direction At least one data signal line is provided between two upwardly adjacent first connection holes.
  • the first connection holes are provided in circuit units of odd-numbered unit columns, and m data signal lines are provided between two adjacent first connection holes in the first direction, m is an odd number greater than or equal to 1.
  • the first connection holes are provided in circuit units of even-numbered unit columns, and m data signal lines are provided between two adjacent first connection holes in the first direction, m is an odd number greater than or equal to 1.
  • the first connection hole is provided in a circuit unit of an odd-numbered unit column, and another first connection hole adjacent to the first connection hole in the first direction is provided in an even-numbered unit.
  • the circuit unit of the column two data signal lines are provided between two adjacent first connection holes in the first direction.
  • At least one second connection line is provided between two adjacent data signal lines in the first direction.
  • the second connection line is connected to the first connection line through a second connection hole, and the first connection hole and the second connection hole connecting the same first connection line are respectively provided on the The first connection line is on both sides of the second direction.
  • the circuit unit at least includes a pixel driving circuit, and the data signal line is connected to the pixel driving circuits of a plurality of circuit units in one unit column; the plurality of unit columns include at least a first unit column and In the second unit column, the pixel driving circuits of the plurality of circuit units in the first unit column are respectively connected to red light-emitting devices that emit red light and blue light-emitting devices that emit blue light.
  • the plurality of circuit units in the second unit column are The pixel driving circuit of the circuit unit is connected to a green light-emitting device that emits green light.
  • the first connection line is connected to the data signal line of the first unit column.
  • the first connection line is connected to the data signal line of the second unit column.
  • the signal cable is not connected.
  • the display area further includes a plurality of first power supply traces extending along the first direction and a plurality of second power supply traces extending along the second direction.
  • the second power supply line is connected to the first power supply line through the third connection hole.
  • the second power supply trace is provided between two adjacent data signal lines in the first direction.
  • the binding area is provided with binding power leads, and the binding power leads are connected to a plurality of second power traces of the display area.
  • the display substrate further includes a frame area located on the other side of the display area.
  • the frame area is provided with frame power leads, and the frame power leads are connected to a plurality of first power supplies of the display area. Wire connections.
  • the first power supply line and the first connection line are arranged on the same layer, and at least one circuit unit includes a first break, and the first break is provided between the first connection line and the first connection line. Between the first power traces, the orthographic projection of the first break on the display substrate plane and the orthographic projection of the second power trace on the display substrate plane at least partially overlap.
  • the second power trace and the second connection line are arranged on the same layer, and at least one circuit unit includes a second break, and the second break is provided between the second connection line and the second connection line. Between the second power traces, the orthographic projection of the second break on the display substrate plane at least partially overlaps the orthographic projection of the first connection line on the display substrate plane.
  • the binding area at least includes a lead area
  • the lead area includes a plurality of lead lines
  • the plurality of lead lines include a first lead line group and a second lead line group
  • the first lead line The lead lines in the group are connected to the data signal lines through the data connection lines
  • the lead lines in the second lead line group are connected to the data signal lines.
  • the plurality of lead lines of the first lead line group are sequentially arranged along the first direction in an increasing number, and the plurality of lead lines of the second lead line group are arranged in an increasing number.
  • the way is arranged sequentially along the opposite direction of the first direction; or, the plurality of lead lines of the first lead line group are arranged sequentially along the opposite direction of the first direction in an increasing number manner, and the second The plurality of lead lines of the lead line group are sequentially arranged along the first direction in an increasing numbered manner.
  • the circuit unit at least includes a pixel drive circuit including a storage capacitor and a plurality of transistors; in a plane perpendicular to the display substrate, the drive circuit layer includes components sequentially arranged on the substrate. a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the semiconductor layer at least includes an active layer of a plurality of transistors, the first conductive layer at least includes an active layer of a plurality of transistors.
  • the gate electrode and the first plate of the storage capacitor, the second conductive layer at least includes the second plate of the storage capacitor, the third conductive layer at least includes the first electrode, the second electrode and the third electrode of a plurality of transistors.
  • a connection line, the fourth conductive layer at least includes the data signal line, the second connection line and a first power line, the data signal line is connected to the first connection line of the first connection line through a first connection hole.
  • the second connection line is connected to the second end of the first connection line through the second connection hole.
  • the binding area at least includes a lead area
  • the lead area at least includes a plurality of lead lines
  • the plurality of lead lines include a plurality of first lead lines disposed in the first conductive layer and A plurality of second lead-out lines are provided in the second conductive layer;
  • the first lead-out lines are connected to the data signal lines of odd-numbered unit columns in the display area, and the second lead-out lines are connected to the data signal lines in the odd-numbered unit columns in the display area.
  • the data signal lines of the even-numbered unit columns are connected; or the first lead-out line is connected to the data signal lines of the even-numbered unit columns in the display area, and the second lead-out line is connected to the data signals of the odd-numbered unit columns in the display area. wire connection.
  • the first conductive layer further includes a plurality of first lead electrodes connected to the first lead wires; the second conductive layer further includes a plurality of second lead wires.
  • the second lead electrode is connected to the second lead wire;
  • the third conductive layer also includes a plurality of third lead electrodes and a plurality of fourth lead electrodes, and the third lead electrode is connected to the second lead electrode through a via hole.
  • the first lead electrode is connected, and the fourth lead electrode is connected to the second lead electrode through a via hole; the data signal lines of the odd-numbered unit columns in the display area are connected to the third lead electrode through a via hole, and the display
  • the data signal lines of the even-numbered unit columns in the display area are connected to the fourth lead electrode through via holes; or the data signal lines of the even-numbered unit columns in the display area are connected to the third lead electrode through via holes, and the odd-numbered units in the display area
  • the data signal line of the column is connected to the fourth lead electrode through the via hole.
  • the third conductive layer further includes a plurality of first power traces extending along the first direction
  • the fourth conductive layer further includes a plurality of first power traces extending along the second direction.
  • a second power supply trace is connected to the first power supply trace through a third connection hole.
  • the binding area at least includes a lead area
  • the lead area includes at least a plurality of binding high-voltage electrodes
  • the plurality of binding high-voltage electrodes are arranged sequentially along the first direction
  • the binding area The high-voltage electrode is configured to be connected to the first power line
  • a lead electrode connected to the data signal line is provided between the adjacent bonded high-voltage electrodes in the first direction.
  • a lead electrode connected to the second connection line is further provided between some adjacent binding high-voltage electrodes.
  • the plurality of transistors include at least a driving transistor, a reset transistor and a compensation transistor
  • the storage capacitor includes a first plate and a second plate
  • the third conductive layer further includes a first connection electrode. and a second connection electrode, the first connection electrode is respectively connected to the first plate, the gate electrode of the driving transistor, the second pole of the reset transistor and the first pole of the compensation transistor, the The second connection electrodes are respectively connected to the second plate and the first power line.
  • an orthographic projection of the first connection electrode on the substrate at least partially overlaps an orthographic projection of the first power line on the substrate.
  • an orthographic projection of the second connection electrode on the substrate at least partially overlaps an orthographic projection of the first power line on the substrate.
  • the plurality of transistors at least include data writing transistors, and in at least one circuit unit, the third conductive layer pattern further includes a data connection electrode, and the data connection electrode is connected to the first connection line. Connection, the data connection electrode and the first pole of the data writing transistor have a common structure.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display substrate includes a display area and a binding area located on one side of the display area.
  • the display area includes a plurality of unit rows and a plurality of a plurality of circuit units of the unit column, a plurality of data signal lines and a plurality of data connection lines, the data connection lines including a first connection line extending along a first direction and a second connection line extending along a second direction, The first connection line and the second connection line are connected, and the first direction and the second direction intersect;
  • the preparation method includes:
  • the data signal line and the first connection line are formed in at least one circuit unit, the first connection line is connected to the data signal line through a first connection hole, and two adjacent second connection lines in the first direction At least one data signal line is provided between one connection hole.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic structural diagram of a display substrate
  • Figure 3 is a schematic plan view of a display area in a display substrate
  • Figure 4 is a schematic cross-sectional structural diagram of a display area in a display substrate
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit
  • Figure 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7a to 7e are schematic diagrams of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure.
  • FIG. 8a to 8b are schematic planar structural diagrams of another display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 9 is a schematic plan view of a power supply wiring according to an exemplary embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure.
  • FIG. 11a and 11b are schematic diagrams of the present disclosure after the semiconductor layer pattern is formed on the substrate;
  • Figures 12a and 12b are schematic diagrams of the display substrate after forming a first conductive layer pattern
  • Figures 13a and 13b are schematic diagrams of the display substrate after forming a second conductive layer pattern
  • 14a and 14b are schematic diagrams of the present disclosure after the fourth insulating layer pattern is formed on the substrate;
  • 15a to 15f are schematic diagrams of the display substrate after forming a third conductive layer pattern
  • 16a to 16f are schematic diagrams of the display substrate after forming a first flat layer pattern
  • 17a to 17f are schematic diagrams of the display substrate after forming a fourth conductive layer pattern
  • 18a to 18f are schematic structural diagrams of the lead area in the display substrate of the present disclosure.
  • 81 data connection electrode
  • 82 data connection block
  • 83 fan-out connection electrode
  • 103 Light-emitting structural layer
  • 104 Encapsulation structural layer
  • 110 First region
  • 201 lead area
  • 210 first lead electrode
  • 220 second lead electrode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 403 The third packaging layer; 410—Binding power leads; 420—Lead openings;
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively.
  • the data driver is connected to a plurality of data signal lines. (D1 to Dn) are connected, the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal. Lines, light-emitting signal lines and data signal lines are connected.
  • the timing controller may provide grayscale values and control signals suitable for specifications of the data driver to the data driver, and may provide clock signals, scan start signals, and the like suitable for specifications of the scan driver to the scan driver.
  • the driver can provide a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample a grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, or the like from the timing controller.
  • the light-emitting driver may sequentially provide emission signals with off-level pulses to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may generate the emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic structural diagram of a display substrate.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display dynamic pictures or still images, and the display area 100 may be referred to as an effective area (AA ).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curled, bent, folded, or rolled.
  • the bonding area 200 may include a fan-out area, a bending area, a driver chip area and a bonding pin area that are sequentially arranged in a direction away from the display area, and the fan-out area is connected to the display area 100, at least Including data fan-out lines, a plurality of data fan-out lines are configured to connect data signal lines of the display area in a fan-out wiring manner.
  • the bending area is connected to the fan-out area and may include a composite insulating layer provided with grooves configured to bend the binding area to the back of the display area.
  • the driver chip area may include an integrated circuit (Integrated Circuit, IC for short), and the integrated circuit is configured to be connected to multiple data fan-out lines.
  • the bonding pin area may include a bonding pad, which is configured to be bonded to an external flexible circuit board (Flexible Printed Circuit, referred to as FPC).
  • the bezel area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged in a direction away from the display area 100 .
  • the circuit area is connected to the display area 100 and may include at least a gate driving circuit connected to the first scanning line, the second scanning line and the light emission control line of the pixel driving circuit in the display area 100.
  • the power line area is connected to the circuit area and may include at least a frame power lead.
  • the frame power lead extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100 .
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulation layer.
  • the cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after all film layers of the display substrate are prepared, the cutting equipment cuts along the cutting grooves respectively.
  • the fan-out area in the binding area 200 and the power line area in the frame area 300 may be provided with first isolation dams and second isolation dams, and the first isolation dams and the second isolation dams may be provided along Extending in a direction parallel to the edge of the display area, forming a ring-shaped structure surrounding the display area 100, the edge of the display area is an edge on one side of the display area binding area or the frame area.
  • Figure 3 is a schematic plan view of a display area in a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, and a second sub-pixel that emits light of a second color.
  • the pixel P2 and the third and fourth sub-pixels P3 and P4 that emit light of the third color.
  • Each sub-pixel may include a circuit unit and a light-emitting device.
  • the circuit unit may include at least a pixel driving circuit.
  • the pixel driving circuit is connected to the scanning signal line, the data signal line and the light-emitting signal line respectively.
  • the pixel driving circuit is configured to operate between the scanning signal line and the light-emitting signal line. Under the control of the light-emitting signal line, it receives the data voltage transmitted by the data signal line and outputs the corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagon or hexagon, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement.
  • the four sub-pixels may be arranged horizontally, vertically, or in a square manner, which is not limited in this disclosure.
  • the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged horizontally, vertically, or vertically, which is not limited in this disclosure.
  • FIG. 4 is a schematic cross-sectional structural diagram of a display area in a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 .
  • the structural layer 103 is away from the packaging structural layer 104 on one side of the substrate 101.
  • the display substrate may include other film layers, such as touch structure layers, etc., which are not limited in this disclosure.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the light-emitting structure layer 103 of each sub-pixel may at least include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304.
  • the anode 301 is connected to the pixel driving circuit
  • the organic light-emitting layer 303 is connected to the anode 301
  • the cathode 304 is connected to the organic light-emitting layer.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material/organic material/inorganic material stack structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include an emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be each connected together.
  • the light-emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated from each other.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • Figure 5 is an equivalent circuit schematic diagram of a pixel driving circuit.
  • the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C.
  • the pixel driving circuit is respectively connected to 8 signal lines (data signal line D, first scanning The signal line S1, the second scanning signal line S2, the light emitting signal line E, the first initial signal line INIT1, the second initial signal line INIT2, the first power supply line VDD and the second power supply line VSS) are connected.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor,
  • the first electrode of the second transistor T2 and the control electrode of the third transistor T3 are connected to the second end of the storage capacitor C.
  • the third node N3 is respectively connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3.
  • the first pole of the sixth transistor T6 is connected.
  • the first terminal of the storage capacitor C is connected to the first power line VDD, and the second terminal of the storage capacitor C is connected to the second node N2, that is, the second terminal of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the first initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, and the first electrode of the third transistor T3 is connected to the first node N1.
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of the driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be called a switching transistor, a scan transistor, or the like. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel drive circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be called light emitting transistors.
  • the fifth and sixth transistors T5 and T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the second initial voltage to the first pole of the light-emitting device to initialize the amount of charge accumulated in the first pole of the light-emitting device or The amount of charge accumulated in the first pole of the light-emitting device is released.
  • the light-emitting device may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode) , quantum dot light-emitting layer and second electrode (cathode).
  • the second pole of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal. flat signal.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the first to seventh transistors T1 to T7 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low-temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide semiconductor (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate, that is, LTPS+Oxide (LTPO for short)
  • the display substrate can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the working process of the pixel driving circuit may include:
  • the first phase A1 is called the reset phase.
  • the signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal, turning on the first transistor T1.
  • the first initial voltage of the first initial signal line INIT1 is provided to the second node N2 to initialize the storage capacitor C and clear the storage capacitor.
  • Zhongyuan has data voltage.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, causing the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to turn off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data The signal line D outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low-level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second transistor through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. Node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the second initial voltage of the second initial signal line INIT2 is provided to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED Not glowing.
  • the signal of the second scanning signal line S2 is a high-level signal, causing the first transistor T1 to turn off.
  • the signal of the light-emitting signal line E is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned off.
  • the third stage A3 is called the light-emitting stage.
  • the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, causing the fifth transistor T5 and the sixth transistor T6 to be turned on.
  • the power supply voltage output by the first power supply line VDD passes through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6.
  • the transistor T6 provides a driving voltage to the first pole of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current that drives the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3.
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the bonding area usually includes a fan-out area, a bending area, a driver chip area and a bonding pin area that are sequentially arranged in a direction away from the display area. Since the width of the bonding area is smaller than the width of the display area, the signal lines of the integrated circuits and bonding pads in the bonding area need to be introduced into the wider display area through the fan-out area in the fanout routing method.
  • the sector area takes up a larger space, resulting in a narrower design of the lower border. It is quite difficult, as the lower border has always been maintained at around 2.0mm.
  • frame power leads are usually provided in the frame area, and the frame power leads are configured to transmit low-voltage power signals. In order to reduce the voltage drop of the low-voltage power signal, the width of the frame power leads is larger, resulting in the left and right sides of the display device. The width of the border is larger.
  • Exemplary embodiments of the present disclosure provide a display substrate, including a display area and a binding area located on one side of the display area, the display area including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, A plurality of data signal lines extending along the second direction and a plurality of data connection lines, the data connection lines include a first connection line extending along the first direction and a second connection line extending along the second direction, said The first connection line is connected to the second connection line, and the first direction and the second direction intersect; in at least one circuit unit, the first connection line is connected to the data signal line through a first connection hole. , at least one data signal line is provided between two adjacent first connection holes in the first direction.
  • a extending along direction B means that A may include a main part and a secondary part connected to the main part.
  • the main part is a line, line segment or bar-shaped body, the main part extends along direction B, and the main part
  • the length extending in direction B is greater than the length of the secondary portion extending in other directions.
  • “A extends along direction B” means "the main body part of A extends along direction B".
  • the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.
  • FIG. 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate may include a driving circuit layer disposed on the substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base.
  • the display substrate in a plane parallel to the display substrate, may at least include a display area 100 , a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on other sides of the display area 100 .
  • the driving circuit layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 60 and a plurality of data connection lines 70 , at least one circuit unit A pixel driving circuit may be included, and the pixel driving circuit is configured to output a corresponding current to the connected light emitting device.
  • the light-emitting structure layer of the display area 100 may include a plurality of sub-pixels constituting a pixel array. At least one sub-pixel may include a light-emitting device. The light-emitting device is connected to a pixel driving circuit of a corresponding circuit unit. The light-emitting device is configured to respond to the connected pixel driving circuit. The output current emits light with corresponding brightness.
  • At least one data signal line 60 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 60 is configured to provide data signals to the connected pixel driving circuits, and at least one data connection line 70 Correspondingly connected to the data signal line 60 , the data connection line 70 is configured such that the data signal line 60 is correspondingly connected to the lead-out line 80 in the binding area 200 through the data connection line 70 .
  • the sub-pixels mentioned in this disclosure refer to areas divided according to light-emitting devices, and the circuit units mentioned in this disclosure refer to areas divided according to pixel driving circuits.
  • the orthographic projection position of the sub-pixel on the substrate may correspond to the orthographic projection position of the circuit unit on the substrate, or the orthographic projection position of the sub-pixel on the substrate corresponds to the orthographic projection position of the circuit unit on the substrate. The positions may not correspond.
  • a plurality of circuit units sequentially arranged along the first direction X may be called a unit row
  • a plurality of circuit units sequentially arranged along the second direction Y may be called a unit column.
  • a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X and the second direction Y intersect.
  • the second direction Y may be an extending direction of the data signal line (vertical direction), and the first direction X may be perpendicular to the second direction Y (horizontal direction).
  • the bonding area 200 may include a lead area 201, a bending area, a driver chip area and a bonding pin area that are sequentially arranged in a direction away from the display area.
  • the lead area 201 is connected to the display area 100, and the bending area 201 is connected to the display area 100.
  • the fold area is connected to the lead area 201.
  • the lead area 201 may be provided with a plurality of lead lines 80.
  • the plurality of lead lines 80 extend in a direction away from the display area.
  • the first end of a part of the lead lines 80 is correspondingly connected to the data connection line 70 in the display area 100, and the other part of the lead lines 80 is connected to the data connection line 70 in the display area 100.
  • the first ends of the lead wires 80 are connected correspondingly to the data signal lines 60 in the display area 100, and the second ends of all the lead wires 80 are connected to the integrated circuits in the composite circuit area across the bending area, so that the integrated circuits transmit data through the lead wires and data connection lines.
  • the signal is applied to the data signal line. Since the data connection line is arranged in the display area, the length of the second direction Y in the lead area can be effectively reduced, the width of the lower frame is greatly reduced, the screen-to-body ratio is increased, and it is conducive to realizing a full-screen display.
  • the plurality of data signal lines of the display area 100 may extend along the second direction Y and be sequentially arranged at set intervals along the first direction X in an increasing numbered manner.
  • the plurality of data signal lines can be divided into a first data signal line group and a second data signal line group according to whether they are connected to the data connection lines.
  • the plurality of data signal lines in the first data signal line group are connected to the data connection lines correspondingly. Multiple data signal lines in the second data signal line group are not connected to the data connection lines.
  • the plurality of lead lines in the lead area 201 can be divided into a first lead line group and a second lead line group according to whether they are connected to data connection lines or data signal lines.
  • the plurality of lead lines in the first lead line group are connected to data.
  • the wires are connected correspondingly, and the plurality of wires in the second wire group are connected correspondingly to the data signal lines.
  • the first ends of the plurality of data connection lines 70 provided in the display area 100 are correspondingly connected to the plurality of data signal lines 60 of the first data signal line group through the first connection holes.
  • the plurality of data connection lines The second end of 70 extends toward the direction of the binding area 200 and crosses the display area boundary B, and is correspondingly connected to the plurality of lead lines 80 of the first lead line group in the lead area 201, so that the first data signal line in the display area 100
  • the plurality of data signal lines 60 of the group are indirectly connected to the lead-out lines 80 through the data connection lines 70 .
  • the plurality of data signal lines 60 of the second data signal line group extend in the direction of the binding area 200 and cross the display area boundary B, and are correspondingly connected to the plurality of lead lines 80 of the second lead line group in the lead area 201, so that the display
  • the plurality of data signal lines 60 of the second data signal line group in the area 100 are directly connected to the lead-out lines 80 .
  • the display area boundary B is the junction of the display area 100 and the binding area 200 .
  • the lead-out line 80 and the data signal line 60 and the lead-out line 80 and the data connection line 70 may be directly connected or may be connected through a via hole, which is not limited in this disclosure.
  • the data connection line 70 may include a first connection line and a second connection line, and the first connection line and the second connection line are connected to each other.
  • the first end of the first connection line is connected to the data signal line through the first connection hole.
  • After the second end of the first connection line extends along the first direction X or the opposite direction of the first direction X, it is connected with the second end of the second connection line.
  • the first end is connected, and the second end of the second connection line extends along the second direction Y toward the lead area and then is connected to the lead line.
  • At least one data signal line may be provided between two adjacent first connection holes in the first direction X.
  • At least one second connection line may be disposed between adjacent data signal lines, or at least one second connection hole may be disposed between adjacent data signal lines.
  • n data signal lines may be provided between adjacent second connection lines in the first direction X (between adjacent second connection holes in the first direction X), n Can be a positive integer greater than or equal to 1.
  • n may be 1, 2, 3, 4, 5, or 6.
  • one data signal line may be provided between adjacent second connection lines.
  • two data signal lines may be provided between adjacent second connection lines.
  • three data signal lines may be provided between adjacent second connection lines.
  • the plurality of second connection lines may be disposed parallel to the data signal line, and the plurality of first connection lines may be disposed perpendicular to the data signal line.
  • the spacing between adjacent second connection lines may be substantially the same, and the spacing between adjacent first connection lines may be substantially the same, which is not limited by the present disclosure.
  • the display area 100 may have a center line O, and the plurality of data signal lines 60 , the plurality of data connection lines 70 in the display area 100 and the plurality of lead lines 80 in the lead area 201 may be relative to the center line O.
  • O is arranged symmetrically, and the center line O may be a straight line that bisects the plurality of unit columns of the display area 100 and extends along the second direction Y.
  • NA is a positive integer greater than or equal to 2
  • NB is greater than or equal to 2 and less than or equal to NA. positive integer.
  • the first connection holes are provided in circuit units of odd-numbered unit columns, that is, the first data signal line group may include NB odd-numbered data signal lines, and the second data signal line group may include the first Data signal lines other than the data signal line group.
  • the first data signal line group may include the first data signal line, the third data signal line, ..., the 2NB-1 data signal line
  • the second data signal line group may include the second data signal line, the fourth data signal line, and the second data signal line.
  • Signal lines,..., the 2nd NB data signal line to the NAth data signal line.
  • odd-numbered data signal lines refer to data signal lines provided in odd-numbered unit columns
  • even-numbered data signal lines refer to data signal lines provided in even-numbered unit columns.
  • m data signal lines may be provided between two adjacent first connection holes in the first direction X, where m is an odd number greater than or equal to 1.
  • the first data signal line group includes the first data signal line, the third data signal line, ..., the 2NB-1 data signal line
  • One data signal line of the second data signal line group is provided (between two adjacent first connection holes).
  • the first data signal line group includes a first data signal line, a fifth data signal line, ..., a 4NB-3 data signal line, one of the two adjacent data signal lines in the first data signal line group
  • Three data signal lines of the second data signal line group are arranged between two adjacent first connection holes.
  • the first connection holes are provided in circuit units of even-numbered unit columns, that is, the first data signal line group may include NB even-numbered data signal lines, and the second data signal line group may include an A data signal line other than a data signal line group.
  • the first data signal line group may include a second data signal line, a fourth data signal line, ..., a 2nd NB data signal line
  • the second data signal line group may include a first data signal line, a third data signal line ,..., the 2nd NB-1 data signal line, the 2NB+1 data signal line to the NAth data signal line.
  • m data signal lines may be provided between two adjacent first connection holes in the first direction X, where m is an odd number greater than or equal to 1.
  • the first data signal line group includes a second data signal line, a fourth data signal line, ..., a 2Mth data signal line
  • the distance between two adjacent data signal lines in the first data signal line group (phase One data signal line of the second data signal line group is disposed between two adjacent first connection holes.
  • the first data signal line group includes the second data signal line, the sixth data signal line, ..., the 4NB-2 data signal line
  • the first data signal line group includes the second data signal line, the sixth data signal line, ..., the 4NB-2 data signal line
  • three data signal lines of the second data signal line group are arranged between two adjacent first connection holes.
  • the first connection holes may be respectively provided in the circuit units of the odd-numbered unit columns and the circuit units of the even-numbered unit columns.
  • One first connection hole may be provided in a circuit unit of an odd-numbered unit column, and another first connection hole adjacent to the first connection hole in the first direction X may be provided in a circuit unit of an even-numbered unit column.
  • one first connection hole may be provided in a circuit unit of an even-numbered unit column, and another first connection hole adjacent to the first connection hole in the first direction X may be provided in a circuit unit of an odd-numbered unit column.
  • Two data signal lines may be provided between two adjacent first connection holes in the first direction X.
  • the first data signal line group may include a first data signal line, a fourth data signal line, a seventh data signal line, ..., a 3NB-2 data signal line, the first data signal line and the fourth data signal line.
  • a second data signal line and a third data signal line are provided therebetween.
  • the multiple lead lines of the first lead line group can be sequentially arranged in an increasing number along the opposite direction of the first direction X (reverse order design),
  • the plurality of lead lines of the second lead line group may be arranged sequentially along the first direction X in an increasing numbered manner (positive sequence design).
  • the multiple lead lines of the first lead line group can be arranged sequentially along the first direction are arranged sequentially along the opposite direction of the first direction X.
  • n lead lines of the second lead line group are disposed between two adjacent lead lines in the first lead line group, and n may be 1, 2, 3, 4, 5, or 6.
  • n may be 1, 2, 3, 4, 5, or 6.
  • one lead wire of the second lead wire group may be provided between adjacent lead wires in the first lead wire group.
  • two lead lines of the second lead line group may be provided between adjacent lead lines in the first lead line group.
  • the first lead-out line group may include NB odd-numbered lead-out lines, and the NB odd-numbered lead-out lines are connected to the NB odd-numbered data signal lines of the first data signal line group through NB data connection lines. connect.
  • the second lead-out line group may include other lead-out lines other than the first lead-out line group and be connected to the plurality of data signal lines in the second data signal line group.
  • the first lead-out line group may include NB even-numbered lead-out lines, and the NB even-numbered lead-out lines are connected to the NB even-numbered data signal lines of the first data signal line group through NB data connection lines. connect.
  • the second lead-out line group may include other lead-out lines other than the first lead-out line group and be connected to the plurality of data signal lines in the second data signal line group.
  • the first lead-out line group may include odd-numbered lead-out lines and even-numbered lead-out lines.
  • One lead-out line may be an odd-numbered lead-out line
  • another lead-out line adjacent to the lead-out line in the first direction X may be an even-numbered lead-out line.
  • a plurality of lead lines of the first lead line group are connected to a plurality of data signal lines of the first data signal line group through a plurality of data connection lines
  • a plurality of lead lines of the second lead line group are connected to a plurality of data signal lines of the second data signal line group. data signal line connection.
  • some of the lead lines in the second lead line group may be straight lines parallel to the data signal lines, and another part of the lead lines may be polygonal lines.
  • Figure 7a is a schematic diagram of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 6, illustrating the structure of 16 data signal lines, 4 data connection lines and 16 lead lines.
  • the plurality of data signal lines in the display area may include first to sixteenth data signal lines 60-1 to 60-16, and the plurality of data connection lines in the display area may Including the first data connection line 70-1 to the fourth data connection line 70-4, the plurality of lead lines of the lead area 201 may include the first lead line 80-1 to the sixteenth lead line 80-16.
  • the first data signal line group includes four odd-numbered data signal lines (the first data signal line 60-1, the third data signal line 60-3, the fifth data signal line 60-5 and the third data signal line 60-1). Seven data signal lines 60-7), the second data signal line group includes the remaining 12 data signal lines, the first data signal line 60-1 to the sixteenth data signal line 60-16 can be sequentially along the first direction X set up.
  • the first lead-out line group includes 4 odd-numbered lead-out lines (the first lead-out line 80-1, the third lead-out line 80-3, the fifth lead-out line 80-5, and the seventh lead-out line 80-5). 7).
  • the second lead-out line group includes the remaining 12 lead-out lines.
  • the multiple lead-out lines of the first lead-out line group can be arranged sequentially in the opposite direction of the first direction X.
  • the multiple lead-out lines of the second lead-out line group can be arranged sequentially. They are arranged sequentially along the first direction X, and two lead lines of the second lead line group are arranged between adjacent lead lines in the first lead line group.
  • the plurality of lead-out lines may include a second lead-out line 80-2, a fourth lead-out line 80-4, a sixth lead-out line 80-6, an eighth lead-out line 80-8, and a third lead-out line 80-8, which are sequentially arranged along the first direction X.
  • a fourteenth lead wire 80-14 and a fifteenth lead wire 80-15 may be provided between the first lead wire 80-1 and the third lead wire 80-3.
  • the third lead wire 80 A twelfth lead wire 80-12 and a thirteenth lead wire 80-13 can be provided between -3 and the fifth lead wire 80-5, and between the fifth lead wire 80-5 and the seventh lead wire 80-7
  • a tenth lead wire 80-10 and an eleventh lead wire 80-11 may be provided.
  • the first connection holes are provided in circuit cells of odd-numbered cell columns.
  • the first end of the first data connection line 70-1 is connected to the first data signal line 60-1 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the first lead line 80-1.
  • the first end of the second data connection line 70-2 is connected to the third data signal line 60-3 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the third lead line 80-3.
  • the first end of the third data connection line 70-3 is connected to the fifth data signal line 60-5 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the fifth lead line 80-5.
  • the first end of the fourth data connection line 70-4 is connected to the seventh data signal line 60-7 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the seventh lead line 80-7.
  • the plurality of data signal lines of the second data signal line group extend to the lead area 201 and are connected correspondingly to the plurality of lead lines of the second lead line group.
  • the second data signal line 60-2, the fourth data signal line 60-4, the sixth data signal line 60-6, the eighth data signal line 60-8 to the sixteenth data signal line 60-16 and the corresponding The lead wires are connected accordingly.
  • the distances between the plurality of first connection holes corresponding to the data connection lines and the data signal lines and the edge B of the display area may be different.
  • the distance between the first connection hole connecting the first data connection line 70-1 and the first data signal line 60-1 and the edge B of the display area may be greater than the distance between the second data connection line 70-2 and the third data signal line 60-2. 3
  • the distance between the first connection hole and the edge B of the display area may be greater than the distance between the third data connection line 70-3 and the fifth data signal line 60
  • the distance between the first connection hole connecting the third data connection line 70-3 and the fifth data signal line 60-5 and the edge B of the display area may be greater than the distance between the fourth data connection line 70-4 and the seventh data signal line 60.
  • the distance between the first connection hole of -7 connections and the edge B of the display area may be greater than the distance between the fourth data connection line 70-4 and the seventh data signal line 60.
  • the data connection line may include a first connection line and a second connection line connected in sequence.
  • the shape of the first connecting line may be a straight line extending along the first direction X
  • the shape of the second connecting line may be a straight line extending along the second direction Y.
  • the first end of the first connection line is connected to the data signal line through the first connection hole.
  • the second end of the first connection line extends along the first direction X or the opposite direction of the first direction X and then connects with the third end of the second connection line.
  • One end is connected, and the second end of the second connection line extends along the second direction Y toward the lead area and then is connected to the lead line.
  • two data signal lines may be provided between adjacent second connection lines in the first direction
  • a structure of two data signal lines is provided between the two connecting lines.
  • a fourteenth data signal line 60-14 and a fifteenth data signal line may be provided between the second connection line of the first data connection line 70-1 and the second connection line of the second data connection line 70-2.
  • 60-15 may be provided between the second connection line of the second data connection line 70-2 and the second connection line of the third data connection line 70-3.
  • Line 60-13 may be provided between the second connection line of the third data connection line 70-3 and the second connection line of the fourth data connection line 70-4. 60-11.
  • some of the lead lines in the second lead line group are straight lines parallel to the data signal lines, and another part of the lead lines are polygonal lines.
  • the shapes of the tenth lead-out line 80-10 to the sixteenth lead-out line 80-16 may be straight lines, and the shapes of the second lead-out line 80-2, the fourth lead-out line 80-4 and the sixth lead-out line 80-6 may be is a polyline.
  • the positions of the multiple sub-pixels in the light-emitting structure layer may correspond to the positions of the multiple circuit units in the driving structure layer.
  • the odd-numbered unit columns may be called first unit columns, and the plurality of odd-numbered unit columns may be called first unit columns.
  • the circuit unit corresponds to multiple red sub-pixels and blue sub-pixels, that is, the pixel driving circuits of multiple circuit units in the odd-numbered unit columns are respectively connected to red light-emitting devices that emit red light and blue light-emitting devices that emit blue light.
  • the even-numbered units The column may be called a second unit column, and multiple circuit units in the even-numbered unit column correspond to multiple green sub-pixels. That is, the pixel driving circuits of the multiple circuit units in the even-numbered unit column are connected to green light-emitting devices that emit green light.
  • the first connection line is connected to the data signal line of the first unit column through the first connection hole, and the first connection line is not connected to the data signal line of the second unit column.
  • the first connection holes in odd-numbered unit columns, that is, the data signals of red sub-pixels and blue sub-pixels are transmitted using data connection lines, not only can the layout of the data connection lines be facilitated, but also the reverse sequence design can be used to achieve no sudden change in the load. , improve display quality.
  • Figure 7b is a schematic diagram of the arrangement of another data connection line according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 6, illustrating the structure of 16 data signal lines, 4 data connection lines and 16 lead lines. . As shown in FIG. 7b , in this exemplary embodiment, this exemplary embodiment is a structure in which data connection lines are connected to data signal lines of odd-numbered unit columns, and one data signal line is provided between adjacent second connection lines.
  • the first data signal line group includes 4 odd-numbered data signal lines, which are connected correspondingly to the first ends of the 4 data connection lines, and the first lead-out line group includes 4 odd-numbered lead lines, and 4 The second ends of the data connection lines are connected correspondingly, and the 12 data signal lines of the second data signal line group are connected correspondingly to the 12 lead lines of the second lead line group.
  • the connection structure is basically the same as that shown in Figure 7a. The difference is that one lead line to the second lead line group is provided between adjacent lead lines in the first lead line group, and one data signal line is provided between adjacent second connection lines.
  • the plurality of lead-out lines may include a second lead-out line 80-2, a fourth lead-out line 80-4, a sixth lead-out line 80-6, and an eighth lead-out line arranged sequentially along the first direction X. 80-8, seventh lead wire 80-7, ninth lead wire 80-9, fifth lead wire 80-5, tenth lead wire 80-10, third lead wire 80-3, eleventh lead wire 80 -11.
  • an eleventh lead wire 80-11, a third lead wire 80-3 and a fifth lead wire 80-3 may be provided between the first lead wire 80-1 and the third lead wire 80-3.
  • a tenth lead wire 80-10 may be provided between 5, and a ninth lead wire 80-9 may be provided between the fifth lead wire 80-5 and the seventh lead wire 80-7.
  • one data signal line may be provided between adjacent second connection lines in the first direction X.
  • an eleventh data signal line 60-11 may be provided between the second connection line of the first data connection line 70-1 and the second connection line of the second data connection line 70-2.
  • a tenth data signal line 60-10 may be provided between the second connection line of the second data connection line 70-2 and the second connection line of the third data connection line 70-3.
  • a ninth data signal line 60-9 may be provided between the second connection line of the third data connection line 70-3 and the second connection line of the fourth data connection line 70-4.
  • this exemplary embodiment not only facilitates the layout of the data connection lines without sudden changes in the load, but also enables further compression by providing a structure with one data signal line between adjacent second connection lines.
  • the space occupied by the data cable can minimize the difference in data signal load.
  • Figure 7c is a schematic diagram of the arrangement of another data connection line according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 6, illustrating the structure of 16 data signal lines, 4 data connection lines and 16 lead lines. . As shown in FIG. 7c , in this exemplary embodiment, this exemplary embodiment is a structure in which the data connection lines are connected to the data signal lines of the even-numbered unit columns, and two data signal lines are provided between adjacent second connection lines.
  • the first data signal line group includes four even-numbered data signal lines (the second data signal line 60-2, the fourth data signal line 60-4, the sixth data signal line 60-6 and the Eight data signal lines 60-8), the second data signal line group includes the remaining 12 data signal lines, the first data signal line 60-1 to the sixteenth data signal line 60-16 can be sequentially along the first direction X set up.
  • the first lead-out line group includes four even-numbered lead-out lines (the second lead-out line 80-2, the fourth lead-out line 80-4, the sixth lead-out line 80-6, and the eighth lead-out line 80-8).
  • the second lead wire group includes the remaining 12 lead wires.
  • the multiple lead wires of the first lead wire group can be arranged sequentially along the opposite direction of the first direction X, and the multiple lead wires of the second lead wire group can be They are arranged sequentially along the first direction X, and two lead lines of the second lead line group are arranged between adjacent lead lines in the first lead line group.
  • the plurality of lead-out lines may include a first lead-out line 80-1, a third lead-out line 80-3, a fifth lead-out line 80-5, a seventh lead-out line 80-7, and a third lead-out line 80-7, which are sequentially arranged along the first direction
  • a fourteenth lead wire 80-14 and a fifteenth lead wire 80-15 may be provided between the second lead wire 80-2 and the fourth lead wire 80-4.
  • the fourth lead wire 80 A twelfth lead wire 80-12 and a thirteenth lead wire 80-13 may be provided between -4 and the sixth lead wire 80-6, and between the sixth lead wire 80-6 and the eighth lead wire 80-8.
  • a tenth lead wire 80-10 and an eleventh lead wire 80-11 may be provided.
  • the first connection holes are provided in circuit cells of even-numbered cell columns.
  • the first end of the first data connection line 70-1 is connected to the second data signal line 60-2 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the second lead line 80-2.
  • the first end of the second data connection line 70-2 is connected to the fourth data signal line 60-4 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the fourth lead line 80-4.
  • the first end of the third data connection line 70-3 is connected to the sixth data signal line 60-6 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the sixth lead line 80-6.
  • the first end of the fourth data connection line 70-4 is connected to the eighth data signal line 60-8 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the eighth lead line 80-8.
  • the plurality of data signal lines of the second data signal line group extend to the lead area 201 and are connected correspondingly to the plurality of lead lines of the second lead line group.
  • the data signal lines 60-16 are connected to corresponding lead lines.
  • two data signal lines may be provided between adjacent second connection lines in the first direction
  • a structure of two data signal lines is provided between the two connecting lines.
  • a fourteenth data signal line 60-14 and a fifteenth data signal line may be provided between the second connection line of the first data connection line 70-1 and the second connection line of the second data connection line 70-2.
  • 60-15 may be provided between the second connection line of the second data connection line 70-2 and the second connection line of the third data connection line 70-3.
  • Line 60-13 may be provided between the second connection line of the third data connection line 70-3 and the second connection line of the fourth data connection line 70-4. 60-11.
  • some of the lead lines in the second lead line group are straight lines parallel to the data signal lines, and another part of the lead lines are polygonal lines.
  • the shapes of the ninth lead-out line 80-9 to the sixteenth lead-out line 80-16 may be straight lines, and the first data signal line 60-1, the third data signal line 60-3, and the fifth data signal line 60-5
  • the shape of the seventh data signal line 60-7 may be a polygonal line.
  • the positions of multiple sub-pixels in the light-emitting structure layer may correspond to the positions of multiple circuit units in the driving structure layer, and multiple circuit units in odd-numbered unit columns correspond to multiple red sub-pixels and blue sub-pixels. Sub-pixels, multiple circuit units in even-numbered unit columns correspond to multiple green sub-pixels.
  • Figure 7d is a schematic diagram of the arrangement of another data connection line according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 6, illustrating the structure of 16 data signal lines, 4 data connection lines and 16 lead lines. . As shown in FIG. 7d , in this exemplary embodiment, this exemplary embodiment is a structure in which the data connection lines are connected to the data signal lines of the even-numbered unit columns, and one data signal line is provided between adjacent second connection lines.
  • the first data signal line group includes 4 even-numbered data signal lines, which are connected correspondingly to the first ends of the 4 data connection lines, and the first lead-out line group includes 4 even-numbered lead lines, and 4 The second ends of the data connection lines are connected correspondingly, and the 12 data signal lines of the second data signal line group are connected correspondingly to the 12 lead lines of the second lead line group.
  • the connection structure is basically the same as that shown in Figure 7c. The difference is that one lead line to the second lead line group is provided between adjacent lead lines in the first lead line group, and one data signal line is provided between adjacent second connection lines.
  • the plurality of lead-out lines may include a first lead-out line 80-1, a third lead-out line 80-3, a fifth lead-out line 80-5, and a seventh lead-out line arranged sequentially along the first direction X. 80-7, ninth lead wire 80-9, eighth lead wire 80-8, tenth lead wire 80-10, sixth lead wire 80-6, eleventh lead wire 80-11, fourth lead wire 80 -4.
  • a twelfth lead wire 80-12, a fourth lead wire 80-4 and a sixth lead wire 80-4 may be provided between the second lead wire 80-2 and the fourth lead wire 80-4.
  • An eleventh lead wire 80-11 may be provided between 6, and a tenth lead wire 80-10 may be provided between the sixth lead wire 80-6 and the eighth lead wire 80-8.
  • one data signal line may be provided between adjacent second connection lines in the first direction X.
  • a twelfth data signal line 60-12 may be provided between the second connection line of the first data connection line 70-1 and the second connection line of the second data connection line 70-2.
  • an eleventh data signal line 60-11 may be provided between the second connection line of the second data connection line 70-2 and the second connection line of the third data connection line 70-3.
  • a tenth data signal line 60-10 may be provided between the second connection line of the third data connection line 70-3 and the second connection line of the fourth data connection line 70-4.
  • this exemplary embodiment not only facilitates the layout of the data connection lines without sudden changes in the load, but also enables further compression by providing a structure with one data signal line between adjacent second connection lines.
  • the space occupied by the data cable can minimize the difference in data signal load.
  • Figures 7a to 7d respectively illustrate an exemplary structure in which one data signal line of the second data signal line group is arranged between adjacent data signal lines in the first data signal line group.
  • more than three odd-numbered data signal lines of the second data signal line group may be provided between adjacent data signal lines in the first data signal line group, and the disclosure is not limited here.
  • Figures 7a and 7c respectively illustrate an exemplary structure in which two data signal lines are provided between adjacent second connection lines.
  • Figures 7b and 7d respectively illustrate an exemplary structure in which one data signal line is provided between adjacent second connection lines. Exemplary structures of data signal lines. In some other exemplary embodiments, more than three data signal lines may be provided between adjacent second connection lines. This disclosure is not limited here.
  • Figure 7e is a schematic diagram of the arrangement of another data connection line according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 6, illustrating the structure of 16 data signal lines, 4 data connection lines and 16 lead lines. .
  • the first connection holes of this exemplary embodiment are respectively provided in the circuit units of the odd-numbered unit columns and the circuit units of the even-numbered unit columns.
  • the first data signal line group includes 2 odd-numbered data signal lines (the first data signal line 60-1 and the seventh data signal line 60-7) and 2 even-numbered data signal lines (the first data signal line 60-1 and the seventh data signal line 60-7).
  • the second data signal line group includes the remaining 12 data signal lines, the first data signal line 60-1 to the sixteenth data signal line 60- 16 may be arranged sequentially along the first direction X.
  • the first lead-out line group includes 2 odd-numbered lead-out lines (the first lead-out line 80-1 and the seventh lead-out line 80-7) and 2 even-numbered lead-out lines (the fourth lead-out line 80-7). 4 and the tenth lead-out line 80-10), the second lead-out line group includes the remaining 12 lead-out lines, the multiple lead-out lines of the first lead-out line group can be arranged sequentially along the opposite direction of the first direction X, and the second lead-out line group The multiple lead wires of the wire group may be arranged sequentially along the first direction X, and one lead wire of the second lead wire group is disposed between adjacent lead wires in the first lead wire group.
  • the first connection holes are respectively provided in the circuit units of the odd-numbered unit columns and the circuit units of the even-numbered unit columns.
  • the first end of the first data connection line 70-1 is connected to the first data signal line 60-1 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the first lead line 80-1.
  • the first end of the second data connection line 70-2 is connected to the fourth data signal line 60-4 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the fourth lead line 80-4. .
  • the first end of the third data connection line 70-3 is connected to the seventh data signal line 60-7 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the seventh lead line 80-7.
  • the first end of the fourth data connection line 70-4 is connected to the tenth data signal line 60-10 through the first connection hole in the display area 100, and the second end extends to the lead area 201 and is connected to the tenth lead line 80-10. .
  • one data signal line may be provided between adjacent second connection lines in the first direction structure.
  • Figure 8a is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure
  • Figure 8b is an enlarged view of the C2 area in Figure 8a.
  • the driving circuit layer of the display area 100 may include multiple circuit units that form a circuit unit array, multiple data signal lines 60 , multiple data connection lines 70 , and power supply lines 90 in a mesh connection structure.
  • the multiple circuit units, multiple The layout and structure of the data signal line 60 and the plurality of data connection lines 70 are basically the same as those shown in FIG. 6 .
  • the data connection line 70 may include a first connection line 71 extending along the first direction X and a second connection line 72 extending along the second direction Y.
  • the first connection line 71 and the second connection line 72 may be provided in different conductive layers.
  • the first connection line 71 and the data signal line 60 may be provided in different conductive layers.
  • the first end of the first connection line 71 passes through the third conductive layer.
  • a connection hole K1 is connected to the data signal line 60.
  • the first end is connected, and the second end of the second connection line 72 extends along the second direction Y toward the lead area and is connected to the lead line 80 .
  • the second connection line 72 can be disposed between adjacent data signal lines 60 .
  • first connection hole K1 and the second connection hole K2 connecting the same first connection line 71 may be respectively provided on both sides of the first connection line 71 in the second direction Y.
  • the power traces 90 may include a plurality of first power traces 91 extending along the first direction X and a plurality of second power traces 92 extending along the second direction Y, and a plurality of first power traces 91 extending along the second direction Y.
  • One power trace 91 can be arranged in sequence along the second direction Y, and a plurality of second power traces 92 can be arranged in sequence along the first direction X.
  • the first power trace 91 and the second power trace 92 may be disposed in different conductive layers, and the second power trace 92 may be disposed between adjacent data signal lines 60 , at least one The second power trace 92 can be connected to at least one first power trace 91 through the third connection hole K3, so that the plurality of first power traces 91 and the plurality of second power traces 92 form a power trace of a mesh connection structure. Line 90.
  • the first connection holes K1 may be provided in circuit units of odd-numbered unit columns, and one data signal line may be provided between two adjacent first connection holes K1 in the first direction X. 60 and 2 second power traces 92.
  • two data signal lines 60 and one second power supply trace 92 may be provided between two adjacent second connection lines 72 in the first direction X.
  • the first power trace 91 and the first connection line 71 may be arranged on the same layer and formed simultaneously through the same patterning process, and the second power trace 92 and the second connection line 72 may be arranged on the same layer. , and are formed simultaneously through the same patterning process.
  • only one first power supply line 91 may be provided in at least one circuit row, and no first connection line 71 is provided in this circuit row.
  • At least one first power supply line 91 and at least one first connection line 71 may be provided in at least one circuit row, and a first power supply line 91 and at least one first connection line 71 may be provided between the first power supply line 91 and the first connection line 71 .
  • the first break DF1 is configured to achieve insulation between the first power trace 91 and the first connection line 71 .
  • only one second power trace 92 may be provided in at least one circuit column, and no second connection line 72 is provided in this circuit column.
  • At least one circuit column may be provided with at least one second power supply line 92 and at least one second connection line 72 , and a second break is provided between the second power supply line 92 and the second connection line 72 DF2, the second break DF2 is configured to achieve insulation between the second power trace 92 and the second connection line 72 .
  • power trace 90 may be a continuously provided low level signal.
  • the power trace 90 may be the second power line VSS.
  • FIG. 9 is a schematic plan view of a power supply wiring according to an exemplary embodiment of the present disclosure.
  • the display substrate may include a display area 100 , a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on other sides of the display area 100 .
  • the display area 100 is provided with a grid-shaped
  • the power trace 90 is provided with a binding power lead 410 in the binding area 200, and a frame power lead 510 is provided in the frame area 300.
  • the power trace 90 is connected to the binding power lead 410 and the frame power lead 510 respectively.
  • the binding power lead 410 of the binding area 200 and the frame power lead 510 of the frame area 300 may be an integral structure connected to each other.
  • the power supply traces 90 of the display area 100 may include a plurality of first power traces 91 extending along the first direction X and a plurality of second power traces 92 extending along the second direction Y.
  • a plurality of first power traces 91 can be arranged sequentially along the second direction Y, and one or both ends of the first direction X are connected to the frame power lead 510
  • a plurality of second power traces 92 can be arranged along the first direction X is set in sequence, and one end of the second direction Y is connected to the binding power lead 410 .
  • one end of the second power trace 92 in the opposite direction of the second direction Y may be connected to the frame power lead 510 .
  • the first power trace 91 and the second power trace 92 may be disposed in different conductive layers, and at least one second power trace 92 may be connected to at least one first power trace through a third connection hole.
  • the lines 91 are connected so that the plurality of first power supply traces 91 and the plurality of second power supply traces 92 have the same potential.
  • This disclosure realizes a structure in which low-voltage lines are set in sub-pixels (VSS in pixel) by arranging power supply lines in the display area, which can greatly reduce the width of the frame power supply leads and is conducive to the realization of narrow borders.
  • the present disclosure can not only effectively reduce the resistance of the power wiring, effectively reduce the voltage drop of the low-voltage power signal, achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate. , effectively improving display uniformity, improving display quality and display quality.
  • Figure 10 is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure.
  • the data connection lines are provided in a partial area of the display area, and the data connection lines include a first connection line extending along the first direction X and a second connection line extending along the second direction Y, Therefore, the display area can be divided into the first area 110, the second area 120 and the third area 130 according to the presence or absence of the data connection line and the extension direction of the data connection line.
  • the first area 110 can be provided with the first connection
  • the area of line 71 (the fan-out line transverse routing area)
  • the second area 120 may be an area where the second connection line 72 is provided (the fan-out line vertical routing area)
  • the third area 130 may be where the first connection line 71 is not provided. and the area of the second connection line 72 (normal area).
  • the first region 110 may include a plurality of circuit units, and the orthographic projection of the first connection line 71 on the display substrate plane is consistent with the pixel driving circuit in the plurality of circuit units of the first region 110 on the display substrate plane.
  • the orthographic projections of the plurality of circuit units in the first region 110 overlap at least partially, and the orthographic projection of the pixel driving circuits on the display substrate plane in the plurality of circuit units in the first region 110 does not overlap with the orthographic projection of the second connection line 72 on the display substrate plane.
  • the second region 120 may include a plurality of circuit units, and the orthographic projection of the second connection line 72 on the display substrate plane is consistent with the pixel driving circuit in the plurality of circuit units of the second region 120 on the display substrate plane.
  • the orthographic projections of the plurality of circuit units in the second region 120 overlap at least partially, and the orthographic projection of the pixel driving circuits on the display substrate plane in the plurality of circuit units of the second region 120 does not overlap with the orthographic projection of the first connection line 71 on the display substrate plane.
  • the third region 130 may include a plurality of circuit units, and the orthographic projection of the pixel driving circuit on the display substrate plane in the plurality of circuit units of the third region 130 is connected with the first connection line 71 and the second connection line. 72 There is no overlap in the orthographic projections on the display substrate plane.
  • the division of various areas shown in FIG. 10 is only an exemplary illustration. Since the first area 110, the second area 120 and the third area 130 are divided according to the presence or absence of data connection lines and the extension direction of the data connection lines, the shapes of the three areas may be regular polygons or irregular. Polygonally, the display area may be divided into one or more first areas 110, one or more second areas 120, and one or more third areas 130, which is not limited in this disclosure.
  • the driving circuit layer in a plane perpendicular to the display substrate, includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the substrate, the The third conductive layer at least includes the first connection line.
  • the fourth conductive layer at least includes the data signal line and the second connection line.
  • the data signal line is connected to the first connection line through a first connection hole.
  • the first end of the wire is connected, and the second connection wire is connected to the second end of the first connection wire through the second connection hole.
  • the third conductive layer further includes a plurality of first power traces extending along the first direction
  • the fourth conductive layer further includes a plurality of first power traces extending along the second direction.
  • a second power supply trace is connected to the first power supply trace through a third connection hole.
  • the binding area at least includes a lead area, the lead area includes a plurality of lead lines, the plurality of lead lines include a plurality of first lead lines disposed in the first conductive layer and A plurality of second lead-out lines in the second conductive layer; the first lead-out lines are connected to the data signal lines of the odd-numbered unit columns in the display area, and the second lead-out lines are connected to the even-numbered unit columns in the display area.
  • the data signal lines of the unit columns are connected; or the first lead-out line is connected to the data signal lines of the even-numbered unit columns in the display area, and the second lead-out line is connected to the data signal lines of the odd-numbered unit columns in the display area. connect.
  • the first conductive layer further includes a plurality of first lead electrodes connected to the first lead wires; the second conductive layer further includes a plurality of second lead wires.
  • the second lead electrode is connected to the second lead wire;
  • the third conductive layer also includes a plurality of third lead electrodes and a plurality of fourth lead electrodes, and the third lead electrode is connected to the second lead electrode through a via hole.
  • the first lead electrode is connected, and the fourth lead electrode is connected to the second lead electrode through a via hole; the data signal lines of the odd-numbered unit columns in the display area are connected to the third lead electrode through a via hole, and the display
  • the data signal lines of the even-numbered unit columns in the display area are connected to the fourth lead electrode through via holes; or the data signal lines of the even-numbered unit columns in the display area are connected to the third lead electrode through via holes, and the odd-numbered units in the display area
  • the data signal line of the column is connected to the fourth lead electrode through the via hole.
  • the driving circuit layer may further include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a first flat layer, the first insulating layer being disposed between the substrate and the semiconductor layer
  • the second insulating layer is disposed between the semiconductor layer and the first conductive layer
  • the third insulating layer is disposed between the first conductive layer and the second conductive layer
  • the fourth insulating layer is disposed between the second conductive layer and the third conductive layer.
  • the first flat layer is disposed between the third conductive layer and the fourth conductive layer.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on The semiconductor layer on the first insulating layer is shown in Figures 11a and 11b.
  • Figure 11a is an enlarged view of the E0 region in Figure 10
  • Figure 11b is an enlarged view of the F region in Figure 10.
  • the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the third active layer 13 and the fifth active layer 15 to the seventh active layer 17 may be an integral structure connected to each other, and the fourth active layer 14 may be provided separately.
  • the first active layer 11 and the second active layer 12 may be located on a side opposite to the second direction Y of the third active layer 13 of this circuit unit, and the fourth active layer 14, The fifth active layer 15 , the sixth active layer 16 and the seventh active layer 17 may be located on one side of the third active layer 13 of the circuit unit in the second direction Y.
  • the first active layer 11 may be in an "n" shape
  • the second active layer 12 and the fifth active layer 15 may be in an "L” shape
  • the third active layer 13 may be in an "L” shape.
  • the shapes of the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 can be in the shape of "I”.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the second region 14-2 of the fourth active layer 14, the The first area 15-1 of the fifth active layer 15 and the first area 17-1 of the seventh active layer 17 can be provided separately, and the second area 11-2 of the first active layer 11 can be used as the second active layer.
  • the first region 12-1 of 12 and the first region 13-1 of the third active layer 13 can simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15 of the fifth active layer 15. -2.
  • the second area 13-2 of the third active layer 13 can simultaneously serve as the second area 12-2 of the second active layer 12 and the first area 16-1 of the sixth active layer 16.
  • the sixth area has The second region 16 - 2 of the source layer 16 may serve as the second region 17 - 2 of the seventh active layer 17 .
  • the first region of the third active layer may serve as a first electrode of a third transistor (driving transistor), and the second region of the fourth active layer may serve as a fourth transistor (data writing transistor).
  • the second electrode of the fifth active layer can be used as the second electrode of the fifth transistor, and the first electrode of the third transistor, the second electrode of the fourth transistor and the second electrode of the fifth transistor are connected to each other, The connection point is the first node N1 of the pixel driving circuit.
  • the semiconductor patterns in the E1 region, E2 region, E3 region and E4 region in FIG. 10 are substantially the same as the semiconductor patterns in the E0 region, and no semiconductor pattern is provided in the lead region in the bonding region.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming The second insulating layer covering the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, are shown in Figures 12a and 12b.
  • Figure 12a is an enlarged view of the E0 area in Figure 10
  • Figure 12b is Magnified view of area F in 10.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit in the display area includes at least: a first scanning signal line 21, a second scanning signal line 22, a third scanning signal line 23, a light emitting control line 24 and a storage The first plate 25 of the capacitor.
  • the shape of the first plate 25 of the storage capacitor may be a rectangle, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the first plate 25 on the substrate is consistent with the third transistor T3 There are overlapping areas in the orthographic projections of the three active layers on the substrate.
  • the first plate 25 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shapes of the first scanning signal line 21 , the second scanning signal line 22 , the third scanning signal line 23 and the light emission control line 24 may be a line shape in which the main body portion extends along the first direction X.
  • the first scanning signal line 21 and the second scanning signal line 22 may be located on the opposite side of the second direction Y of the first plate 25 of the circuit unit, and the second scanning signal line 22 may be located on the first scanning side of the circuit unit.
  • the signal line 21 is on the side away from the first plate 25.
  • the third scanning signal line 23 and the light-emitting control line 24 can be located on the side of the first plate 25 in the second direction Y of this circuit unit.
  • the third scanning signal line 23 can be The light-emitting control line 24 of this circuit unit is located on the side away from the first plate 25 .
  • the first scanning signal line 21 may be provided with a gate block 21-1 protruding toward the second scanning signal line 22 side, and the first scanning signal line 21 and the gate block 21-1 are connected to the first scanning signal line 21 and the gate block 21-1.
  • the overlapping area of the two active layers can be used as the gate electrode of the second transistor T2 to form the second transistor T2 with a double-gate structure.
  • a region where the second scanning signal line 22 overlaps the first active layer may serve as a gate electrode of the first transistor T1 of the double-gate structure.
  • the area where the third scanning signal line 23 overlaps with the fourth active layer can be used as the gate electrode of the fourth transistor T4, and the area where the third scanning signal line 23 overlaps with the seventh active layer can be used as the gate electrode of the seventh transistor T7. electrode.
  • the area where the light-emitting control line 24 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting control line 24 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.
  • the first scanning signal line 21 and the third scanning signal line 23 may be connected to the same signal source, that is, the output signals of the first scanning signal line 21 and the third scanning signal line 23 are the same.
  • the first conductive layer patterns of the E1 region, the E2 region, the E3 region, and the E4 region in FIG. 10 are substantially the same as the first conductive layer patterns of the E0 region.
  • the first conductive layer pattern of the lead area in the bonding area may include at least a plurality of first lead electrodes 210 .
  • the shape of the first lead electrode 210 may be a strip shape extending along the second direction Y, and the first lead electrode 210 is configured to be connected to the data signal lines of subsequently formed odd-numbered cell columns.
  • the first conductive layer can be used as a shield to perform a conductive process on the semiconductor layer.
  • the semiconductor layer in the area blocked by the first conductive layer forms the first to seventh transistors T1 to T1.
  • the semiconductor layer in the region not blocked by the first conductive layer is conductive, that is, the first and second regions of the first to seventh active layers are all conductive.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, and patterning the second conductive film using a patterning process to form A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer.
  • the second conductive layer pattern at least includes: as shown in Figures 13a and 13b, Figure 13a is E0 in Figure 10 An enlarged view of the area, Figure 13b is an enlarged view of the F area in Figure 10.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit in the display area at least includes: a first initial signal line 31, a second initial signal line 32, a second plate 33 of the storage capacitor, and plate connection lines. 34 and shield electrode 35.
  • the shape of the first initial signal line 31 and the second initial signal line 32 may be a line shape in which the main body portion may extend along the first direction X.
  • the first initial signal line 31 may be located between the first scanning signal line 21 and the second scanning signal line 22 of this circuit unit, and the second initial signal line 32 may be located away from the third scanning signal line 23 of this circuit unit away from the light-emitting control line. 24 on one side.
  • the outline shape of the second electrode plate 33 may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the orthographic projection of the second electrode plate 33 on the base is the same as the orthographic projection of the first electrode plate 25 on the base. There is an overlapping area in the orthographic projection of 33 constitutes the storage capacitor of the pixel drive circuit.
  • the plate connecting line 34 may be disposed on one side of the second plate 33 in the first direction X or the opposite direction to the first direction
  • the second plate 33 is connected.
  • the second end of the plate connection line 34 extends along the first direction X or the opposite direction of the first direction
  • the second plates 33 of upper adjacent circuit units are connected to each other.
  • the second electrode plates of multiple circuit units in a unit row can form an integrated structure connected to each other through the plate connection lines, and the second electrode plates of the integrated structure can be reused as power signal connection lines, Ensuring that multiple second electrode plates in a unit row have the same potential is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the second pole plate 33 is provided with an opening 36 , the opening 36 may be located in the middle of the second pole plate 33 , and the opening 36 may be rectangular, so that the second pole plate 33 forms an annular structure.
  • the opening 36 exposes the third insulating layer covering the first electrode plate 25 , and the orthographic projection of the first electrode plate 25 on the substrate includes the orthographic projection of the opening 36 on the substrate.
  • the opening 36 is configured to accommodate a subsequently formed first via hole.
  • the first via hole is located within the opening 36 and exposes the first plate 25 so that the subsequently formed second transistor T1 can The pole is connected to the first pole plate 25.
  • the orthographic projection of the second plate 33 on the substrate at least partially overlaps with the orthographic projection of the first node N1 on the substrate. Since the second plate 33 is connected to the subsequently formed first signal line, Therefore, the second plate 33 can effectively shield the first node N1, preventing the potential of the first node N1 from being affected by the outside world, and improving the display effect.
  • the shielding electrode 35 may be located on a side of the first initial signal line 31 close to the first scanning signal line 21 and connected to the first initial signal line 31 , and the orthographic projection of the shielding electrode 35 on the substrate is consistent with the first scanning signal line 21 .
  • the orthographic projections of the first regions of the two active layers on the substrate at least partially overlap, and the shielding electrode 35 is configured to shield the impact of the data voltage jump on the key node and prevent the data voltage jump from affecting the potential of the key node of the pixel driving circuit. , improve the display effect.
  • the second conductive layer patterns of the E1 region, E2 region, E3 region, and E4 region in FIG. 10 are substantially the same as the second conductive layer patterns of the E0 region.
  • the second conductive layer pattern of the lead area in the bonding area may include at least a plurality of second lead electrodes 220 .
  • the shape of the second lead electrode 220 may be a strip shape extending along the second direction Y, and the second lead electrode 220 is configured to be connected to the data signal lines of the subsequently formed even-numbered cell columns.
  • the second lead electrodes 220 may be disposed between the adjacent first lead electrodes 210 in the first direction X, and the first lead electrodes 210 may be disposed between the adjacent second lead electrodes 220 in the first direction X.
  • the ends of the plurality of first lead electrodes 210 close to the display area and the ends of the plurality of second lead electrodes 220 close to the display area may be flush.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, patterning the fourth insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • multiple via holes are provided in each circuit unit, as shown in Figures 14a and 14b.
  • Figure 14a is an enlarged view of the E0 area in Figure 10
  • Figure 14b is an enlarged view of the F area in Figure 10.
  • the plurality of via holes of each circuit unit in the display area at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, and a fifth via hole.
  • V5 the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the tenth via V10, the eleventh via V11 and the twelfth via V12.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 36 of the second plate 33 on the substrate, and the fourth insulating layer in the first via hole V1 and The third insulating layer is etched away to expose the surface of the first electrode plate 25 , and the first via hole V1 is configured so that the second electrode of the subsequently formed first transistor T1 can communicate with the first electrode plate 25 through the via hole. connect.
  • the orthographic projection of the second via hole V2 on the substrate is within the range of the orthographic projection of the second plate 33 on the substrate, and the fourth insulating layer in the second via hole V2 is etched away. , exposing the surface of the second electrode plate 33 , and the second via hole V2 is configured so that the first electrode of the subsequently formed fifth transistor T5 is connected to the second electrode plate 33 through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is within the range of the orthographic projection of the first region of the fifth active layer on the substrate, and the fourth insulating layer in the third via hole V3 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fifth active layer, and the third via V3 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to pass through The via hole is connected to the first region of the fifth active layer.
  • the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away, exposing the surface of the second region of the sixth active layer, and the fourth via hole V4 is configured to make
  • the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) is connected to the sixth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, and the fourth insulating layer in the fifth via hole V5 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer, and the fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to pass through The via hole is connected to the first region of the fourth active layer.
  • the orthographic projection of the sixth via hole V6 on the substrate is within the range of the orthographic projection of the first region of the seventh active layer on the substrate, and the fourth insulating layer in the sixth via hole V6 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the seventh active layer, and the sixth via V6 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to pass through The via hole is connected to the first region of the seventh active layer.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first region of the third active layer on the substrate, and the fourth insulating layer in the seventh via hole V7 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the third active layer, and the seventh via V7 is configured to allow the first electrode of the subsequently formed third transistor T3 to pass through The via hole is connected to the first region of the third active layer.
  • the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer on the substrate, and the fourth insulating layer in the eighth via hole V8 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the second region of the fourth active layer, and the eighth via V8 is configured to allow the first electrode of the subsequently formed third transistor T3 to pass through The via hole is connected to the second region of the fourth active layer.
  • the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate.
  • the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away, exposing the surface of the second region of the first active layer, and the ninth via hole V9 is configured to
  • the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) is connected to the first active layer through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the first region of the first active layer on the substrate, and the fourth insulating layer in the tenth via hole V10 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the first active layer, and the tenth via hole V10 is configured to allow the first electrode of the subsequently formed first transistor T1 to pass through The via hole is connected to the first region of the first active layer.
  • the orthographic projection of the eleventh via hole V11 on the substrate is within the range of the orthographic projection of the first initial signal line 31 on the substrate, and the fourth insulating layer in the eleventh via hole V11 is It is etched away to expose the surface of the first initial signal line 31 , and the eleventh via hole V11 is configured so that the first pole of the subsequently formed first transistor T1 is connected to the first initial signal line 31 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is within the range of the orthographic projection of the second initial signal line 32 on the substrate, and the fourth insulating layer in the twelfth via hole V12 is It is etched away to expose the surface of the second initial signal line 32 , and the twelfth via hole V12 is configured so that the first electrode of the subsequently formed seventh transistor T7 is connected to the second initial signal line 32 through the via hole.
  • the plurality of via hole patterns in the E1 region, the E2 region, the E3 region, and the E4 region in FIG. 10 are substantially the same as the plurality of via hole patterns in the E0 region.
  • the plurality of via holes in the lead area in the bonding area at least include: a thirteenth via hole V13 and a fourteenth via hole V14.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is within the range of the orthographic projection of the first lead electrode 210 on the substrate, and the fourth insulating layer and the third insulating layer in the thirteenth via hole V13
  • the three insulating layers are etched away to expose the surface of the first lead electrode 210
  • the thirteenth via hole V13 is configured to allow the subsequently formed third lead electrode to be connected to the first lead electrode 210 through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is within the range of the orthographic projection of the second lead electrode 220 on the substrate, and the fourth insulating layer in the fourteenth via hole V14 is engraved
  • the surface of the second lead electrode 220 is etched away to expose the surface, and the fourteenth via hole V14 is configured to allow the subsequently formed fourth lead electrode to be connected to the second lead electrode 220 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a layer disposed on the fourth insulating layer.
  • the third conductive layer is as shown in Figure 15a to Figure 15f.
  • Figure 15a is an enlarged view of the E0 area in Figure 10.
  • Figure 15b is an enlarged view of the E1 area in Figure 10.
  • Figure 15c is an enlarged view of the E2 area in Figure 10.
  • Figure 15d is an enlarged view of the E3 area in Figure 10
  • Figure 15e is an enlarged view of the E4 area in Figure 10
  • Figure 15f is an enlarged view of the F area in Figure 10.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer patterns of the plurality of circuit units in the display area each include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode electrode 45, sixth connection electrode 46 and seventh connection electrode 47.
  • the shape of the first connection electrode 41 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the first connection electrode 41 communicates with the first plate 25 through the first via hole V1
  • the second end of the first connection electrode 41 is connected to the second area of the first active layer (also the first area of the second active layer) through the ninth via V9.
  • the first connection electrode 41 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, so that the first electrode plate 25, the second electrode of the first transistor T1 and the second electrode
  • the first pole of transistor T2 has the same potential (second node N2).
  • the shape of the second connection electrode 42 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the second connection electrode 42 communicates with the second electrode plate 33 through the second via hole V2 connection, the second end of the second connection electrode 42 is connected to the first region of the fifth active layer through the third via hole V3.
  • the second connection electrode 42 may serve as the first electrode of the fifth transistor T5, so that the second plate 33 and the first electrode of the fifth transistor T5 have the same potential, and the second connection electrode 42 is configured To connect with the first power line formed later.
  • the shape of the third connection electrode 43 may be a strip shape with a main body portion extending along the second direction Y, and the first end of the third connection electrode 43 communicates with the third active layer through the seventh via hole V7 The second end of the third connection electrode 43 is connected to the second area of the fourth active layer through the eighth via hole V8.
  • the third connection electrode 43 may serve as the first electrode of the third transistor T3 (and also the second electrode of the fourth transistor T4), so that the first electrode of the third transistor T3 and the third electrode of the fourth transistor T4 The second electrode and the second electrode of the fifth transistor T5 have the same potential (first node N1).
  • the shape of the fourth connection electrode 44 may be a rectangular shape, and the fourth connection electrode 44 is connected to the first region of the fourth active layer through the fifth via hole V5.
  • the fourth connection electrode 44 may serve as the first electrode of the fourth transistor T4, and the fourth connection electrode 44 is configured to be connected to a subsequently formed data signal line.
  • the shape of the fifth connection electrode 45 may be a rectangular shape, and the fifth connection electrode 45 communicates with the second area of the sixth active layer (also the second area of the seventh active layer) through the fourth via hole V4. area) connection.
  • the fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7), and the fifth connection electrode 45 is configured to be connected to the subsequently formed anode connection electrode.
  • the shape of the sixth connection electrode 46 may be a rectangular shape.
  • the first end of the sixth connection electrode 46 is connected to the first region of the first active layer through the tenth via hole V10.
  • the sixth connection electrode 46 may be in a rectangular shape.
  • the second end of 46 is connected to the first initial signal line 31 through the eleventh via hole V11.
  • the sixth connection electrode 46 can serve as the first pole of the first transistor T1, thereby enabling the first initial signal line 31 to write the first initial signal into the first pole of the first transistor T1.
  • the shape of the seventh connection electrode 47 may be a rectangular shape.
  • the first end of the seventh connection electrode 47 is connected to the first region of the seventh active layer through the sixth via V6.
  • the seventh connection electrode 47 may be in a rectangular shape.
  • the second end of 47 is connected to the second initial signal line 32 through the twelfth via V12.
  • the seventh connection electrode 47 can serve as the first pole of the seventh transistor T7, thereby enabling the second initial signal line 32 to write the second initial signal into the first pole of the seventh transistor T7.
  • the third conductive layer patterns of the plurality of circuit units in the third region may further include first power traces 91 , power connection electrodes 85 and power connection blocks 86 .
  • the shape of the first power trace 91 may be a line shape with the main body extending along the first direction X, and may be disposed on a side of the second scanning signal line 22 away from the first scanning signal line 21 .
  • the first power trace 91 may be connected to a bezel power lead in the bezel area and configured to transmit a low voltage signal (VSS).
  • VSS low voltage signal
  • the power connection electrode 85 may be in a rectangular shape and may be disposed on a side of the first power trace 91 close to the first scanning signal line 21 . In an exemplary embodiment, the power connection electrode 85 is configured to connect with a subsequently formed second power trace.
  • the power connection block 86 is disposed between the first power trace 91 and the power connection electrode 85 , a first end of the power connection block 86 is connected to the first power trace 91 , and a third end of the power connection block 86 is connected to the first power trace 91 .
  • the two ends are connected to the power connection electrode 85 , thus realizing the connection between the first power supply line 91 and the power connection electrode 85 .
  • the first power trace 91 , the power connection electrode 85 and the power connection block 86 of one circuit row in the third region may be an integral structure connected to each other.
  • the third conductive layer patterns of the plurality of circuit units in the first region may further include first connection lines 71 and dummy electrodes 87 .
  • the shape of the first connection line 71 of the data connection line may be a line shape with the main part extending along the first direction X, and may be disposed on the second scanning signal line 22 away from the first scanning signal line 21 one side.
  • the first connection line 71 is configured to connect with a subsequently formed second connection line of the data connection line.
  • the positions and shapes of the dummy electrodes 87 of the plurality of circuit units in the first region are substantially the same as the positions and shapes of the power connection electrodes 85 in the third region, except that the dummy electrodes 87 are
  • the isolation arrangement is neither connected to the first connection line 71 nor to other electrodes.
  • the dummy electrode 87 exhibits the same morphology and structure as the power connection electrode and the data connection electrode, which not only improves the uniformity of the preparation process, but also allows different areas to have substantially the same transfer connection structure. Different areas can achieve basically the same display effect under transmitted light and reflected light, effectively avoiding poor appearance of the display substrate and improving display quality and quality.
  • the third conductive layer patterns of the plurality of circuit units in the second region further include first power supply traces 91 and dummy electrodes 87 .
  • the positions and shapes of the first power traces 91 of the plurality of circuit units in the second region may be substantially the same as the positions and shapes of the first power traces 91 in the third region, and the second region
  • the positions, shapes and functions of the dummy electrodes 87 of the plurality of circuit units may be substantially the same as the positions, shapes and functions of the power connection electrodes 85 in the first region.
  • the third conductive layer pattern of at least one circuit unit in the boundary area of the first area and the third area may further include a first connection line 71, a data connection electrode 81 and a data connection block. 82.
  • the boundary area between the first area and the third area may include at least one circuit unit of the first area, at least one circuit unit of the third area, and a first connection unit.
  • the first connection unit may be a data A circuit unit in which the signal line and the first connection line are connected through the first connection hole.
  • the first connection unit may include a first connection line 71 , a data connection electrode 81 and a data connection block 82 .
  • the circuit unit of the first area may include a first connection line 71 and a dummy electrode 87, located on the right side of the first connection unit.
  • the circuit unit of the third area may include a first power supply trace 91 and a dummy electrode 87 located on the left side of the first connection unit.
  • the data connection electrode 81 may be in a rectangular shape and may be disposed on a side of the first connection line 71 away from the dummy electrode 87 .
  • the shape of the data connection block 82 may be rectangular, and may be disposed between the first connection line 71 and the data connection electrode 81 .
  • the first end of the data connection block 82 is connected to the first connection line 71
  • the second end of the data connection block 82 is connected to the first connection line 71 .
  • the terminal is connected to the data connection block 82, thereby realizing the connection between the first connection line 71 and the data connection electrode 81.
  • the data connection electrode 81 is configured to be connected to a subsequently formed data signal line.
  • the data connection electrode 81 may be connected to the fourth connection electrode 44 in the pixel driving circuit.
  • the fourth connection electrode 44 in the pixel driving circuit may serve as the data connection electrode 81 , that is, the data connection electrode 81 and the fourth connection electrode 44 (the first pole of the fourth transistor) have a common structure.
  • At least one circuit unit in the third area adjacent to the first connection unit may be provided with at least one first break DF1, which connects the first connection line 71 and the first break DF1 in the same circuit row.
  • the power trace 91 is cut off, and the side of the first break DF1 in the first direction X is the first connecting wire 71 , and the side of the first break DF1 in the opposite direction to the first direction X is the first power trace 91 .
  • the third conductive layer pattern of at least one circuit unit in the boundary area of the first area and the second area may further include a first connection line 71, a fan-out connection electrode 83 and a fan-out connection electrode 83.
  • Connect block 84 may further include a first connection line 71, a fan-out connection electrode 83 and a fan-out connection electrode 83.
  • the boundary area between the first area and the second area may include at least one circuit unit of the first area, at least one circuit unit of the second area, and a second connection unit, and the second connection unit may be a A circuit unit in which a connection line and a second connection line are connected through the second connection hole.
  • the second connection unit may include a first connection line 71 , a fan-out connection electrode 83 and a fan-out connection block 84 .
  • the circuit unit of the first area may include a first connection line 71 and a dummy electrode 87 located on the left side of the first connection unit.
  • the circuit unit of the second area may include a first power supply trace 91 and a dummy electrode 87 located on the lower side of the second connection unit.
  • the fan-out connection electrode 83 may be in a rectangular shape and may be disposed on a side of the first connection line 71 that is close to the second initial signal line 32 .
  • the shape of the fan-out connection block 84 may be rectangular, and may be disposed between the first connection line 71 and the fan-out connection electrode 83.
  • the first end of the fan-out connection block 84 is connected to the first connection line 71.
  • the fan-out connection block 84 The second end of 84 is connected to the fan-out connection electrode 83, thereby realizing the connection between the first connection line 71 and the fan-out connection electrode 83.
  • the fan-out connection electrode 83 is configured to connect with a subsequently formed second connection line.
  • At least one circuit unit in the first area adjacent to the second connection unit may be provided with at least one first break DF1, which connects the first connection line 71 and the first break DF1 in the same circuit row.
  • the power trace 91 is cut off, and the side of the first break DF1 in the first direction X is the first connecting wire 71 , and the side of the first break DF1 in the opposite direction to the first direction X is the first power trace 91 .
  • the third conductive layer pattern of the lead area in the bonding area at least includes: a plurality of third lead electrodes 230, a plurality of fourth lead electrodes 240, a bonding high voltage line 250 and a plurality of A high-voltage electrode 260 is bound.
  • the shape of the third lead electrode 230 may be a strip shape extending along the second direction Y, and the positions of the plurality of third lead electrodes 230 may correspond to the positions of the plurality of first lead electrodes 210,
  • the orthographic projection of the third lead electrode 230 on the substrate at least partially overlaps the orthographic projection of the first lead electrode 210 on the substrate, and the third lead electrode 230 is connected to the first lead electrode 210 through the thirteenth via hole V13.
  • the plurality of third lead electrodes 230 are configured to be connected correspondingly to the data signal lines of subsequently formed odd-numbered cell columns.
  • the shape of the fourth lead electrode 240 may be a strip shape extending along the second direction Y, and the positions of the plurality of fourth lead electrodes 240 may correspond to the positions of the plurality of second lead electrodes 220,
  • the orthographic projection of the fourth lead electrode 240 on the substrate at least partially overlaps the orthographic projection of the second lead electrode 220 on the substrate, and the fourth lead electrode 240 is connected to the second lead electrode 220 through the fourteenth via hole V14.
  • the plurality of fourth lead electrodes 240 are configured to be connected correspondingly to data signal lines of subsequently formed even-numbered cell columns.
  • the shape of the bonding high-voltage line 250 may be a strip shape extending along the first direction .
  • the shape of the binding high-voltage electrode 260 may be a strip shape extending along the second direction Y, and the plurality of binding high-voltage electrodes 260 may be sequentially arranged along the first direction X.
  • the plurality of binding high-voltage electrodes may be The first end of 260 is connected to the binding high-voltage line 250, and the second ends of the plurality of binding high-voltage electrodes 260 extend toward the direction of the display area.
  • a plurality of binding high-voltage electrodes 260 are configured to be connected correspondingly to a plurality of subsequently formed first power lines.
  • forming the first flat layer pattern may include: coating a first flat film on the substrate on which the foregoing pattern is formed, patterning the first flat film using a patterning process, and forming a covering third conductive layer.
  • the first flat layer is provided with multiple via holes, as shown in Figures 16a to 16f.
  • Figure 16a is an enlarged view of the E0 area in Figure 10
  • Figure 16b is an enlarged view of the E1 area in Figure 10
  • Figure 16c is an enlarged view of the E2 area in Figure 10
  • Figure 16d is an enlarged view of the E3 area in Figure
  • Figure 16e is an enlarged view of the E4 area in Figure 10
  • Figure 16f is an enlarged view of the F area in Figure 10.
  • the plurality of via holes of the plurality of circuit units in the display area each include: a twenty-first via hole V21, a twenty-second via hole V22, and a twenty-third via hole V23.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the second connection electrode 42 on the substrate, and the first flat layer in the twenty-first via hole V21 is removed to expose the surface of the second connection electrode 42, and the twenty-first via hole V21 is configured so that the first power line formed later is connected to the second connection electrode 42 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is within the range of the orthographic projection of the fourth connection electrode 44 on the substrate, and the first planar layer in the twenty-second via hole V22 is removed to expose the surface of the fourth connection electrode 44, and the twenty-second via hole V22 is configured to allow a subsequently formed data signal line to be connected to the fourth connection electrode 44 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the fifth connection electrode 45 on the substrate, and the first flat layer in the twenty-third via hole V23 is removed to expose the surface of the fifth connection electrode 45, and the twenty-third via hole V23 is configured to allow the subsequently formed anode connection electrode to be connected to the fifth connection electrode 45 through the via hole.
  • the plurality of circuit units in the third region further include a twenty-fourth via V24.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the power connection electrode 85 on the substrate, and the first flat layer in the twenty-fourth via hole V24 is Removed, the surface of the power connection electrode 85 is exposed, and the twenty-fourth via hole V24 is configured to allow a subsequently formed second power trace to be connected to the power connection electrode 85 through the via hole.
  • the twenty-fourth via hole V24 may be called a third connection hole.
  • the plurality of circuit units in the first area and the plurality of circuit units in the second area further include twenty-fifth via holes V25.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the dummy electrode 87 on the substrate, and the first flat layer in the twenty-fifth via hole V25 is removed. , exposing the surface of the dummy electrode 87 , and the twenty-fifth via hole V25 is configured so that the second power supply trace formed later is connected to the dummy electrode 87 through the via hole.
  • At least one circuit unit in the boundary area of the first area and the third area further includes a twenty-sixth via V26.
  • the orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the data connection electrode 81 on the substrate, and the first flat layer in the twenty-sixth via hole V26 is removed to expose the surface of the data connection electrode 81 , and the twenty-sixth via hole V26 is configured to allow the subsequently formed data signal line to pass through the via hole and the data connection electrode 81
  • the twenty-sixth via hole V26 and the twenty-second via hole V22 may be a common structure of the same hole.
  • the twenty-sixth via hole V26 may be called a first connection hole.
  • At least one circuit unit in the boundary area of the first area and the second area further includes a twenty-seventh via V27.
  • the orthographic projection of the twenty-seventh via hole V27 on the substrate is within the range of the orthographic projection of the fan-out connection electrode 83 on the substrate, and the first planar layer in the twenty-seventh via hole V27 is removed to expose the surface of the fan-out connection electrode 83 , and the twenty-seventh via hole V27 is configured to allow a subsequently formed second connection line to be connected to the fan-out connection electrode 83 through the via hole.
  • the twenty-seventh via hole V27 may be called a second connection hole.
  • the twenty-sixth via hole V26 may be located on the opposite side of the second direction Y of the first connection line 71
  • the twenty-seventh via hole V27 may be located on the second direction Y of the first connection line 71 one side, that is, the first connection hole (twenty-sixth via hole V26) and the second connection hole (twenty-seventh via hole V27) connected to the same first connection line 71 are respectively provided on the first connection line. 71 on both sides of the second direction Y.
  • the plurality of vias in the lead area in the bonding area at least include: the thirty-first via V31, the thirty-second via V32, and the thirty-third via V33. .
  • the orthographic projection of the thirty-first via hole V31 on the substrate is within the range of the orthographic projection of the third lead electrode 230 on the substrate, and the first planar layer in the thirty-first via hole V31 are removed to expose the surface of the third lead electrode 230 , and the thirty-first via hole V31 is configured so that the data signal lines in odd-numbered columns in the subsequently formed display area are connected to the third lead electrode 230 through the via hole.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is within the range of the orthographic projection of the fourth lead electrode 240 on the substrate, and the first planar layer in the thirty-second via hole V32 are removed to expose the surface of the fourth lead electrode 240 , and the thirty-second via hole V32 is configured so that the data signal lines of the even-numbered columns in the subsequently formed display area are connected to the fourth lead electrode 240 through the via hole.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is within the range of the orthographic projection of the binding high-voltage electrode 260 on the substrate, and the first flat layer in the thirty-third via hole V33 is removed to expose the surface of the binding high-voltage electrode 260, and the thirty-third via hole V33 is configured so that the first power line in the subsequently formed display area is connected to the binding high-voltage electrode 260 through this via hole.
  • forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the foregoing pattern is formed, patterning the fourth conductive film using a patterning process, and forming a pattern on the first planar layer.
  • the fourth conductive layer on the top is as shown in Figures 17a to 17f.
  • Figure 17a is an enlarged view of the E0 area in Figure 10.
  • Figure 17b is an enlarged view of the E1 area in Figure 10.
  • Figure 17c is an enlarged view of the E2 area in Figure 10.
  • Figure 17d is an enlarged view of the E3 area in Figure 10
  • Figure 17e is an enlarged view of the E4 area in Figure 10
  • Figure 17f is an enlarged view of the F area in Figure 10.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer patterns of the plurality of circuit units in the display area each include: a first power supply line 51 , an anode connection electrode 52 and a data signal line 60 .
  • the shape of the first power line 51 may be a polygonal shape with a main body portion extending along the second direction Y.
  • the first power line 51 passes through the twenty-first via hole V21 of the display area and connects to the second through hole V21 of the display area.
  • the two connection electrodes 42 are connected.
  • the first power line 51 extends to the lead area and is connected to the binding high-voltage electrode 260 through the thirty-third via hole V33 in the lead area.
  • the first power line 51 is realized to write the power signal to the first pole of the fifth transistor T5, and
  • the second plate of the storage capacitor has the same potential as the first power line 51 . Since the binding high-voltage electrode 260 is connected to the binding high-voltage line 250 , the binding high-voltage line 250 provides a high-level signal to the first power line 51 through the binding high-voltage electrode 260 .
  • the orthographic projection of the first power line 51 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 41 on the substrate, and the first power line 51 can effectively shield the pixel from the data voltage jump.
  • the influence of the second node N2 in the driving circuit avoids the data voltage jump from affecting the potential of the second node N2, thereby improving the display effect.
  • the orthographic projection of the first power line 51 on the substrate at least partially overlaps the orthographic projection of the second connection electrode 42 on the substrate.
  • the first power lines 51 may be designed with unequal widths.
  • the first power lines 51 with unequal widths can not only facilitate the layout of the pixel structure, but also reduce the distance between the first power lines and the data signal lines. parasitic capacitance between.
  • the shape of the data signal line 60 may be a straight line with the main body extending along the second direction Y.
  • the data signal line 60 is connected to the fourth through the twenty-second via hole V22 of the display area.
  • the electrode 44 is connected.
  • the data signal line 60 of the odd-numbered unit columns is connected to the third lead electrode 230 through the thirty-first via V31
  • the data signal line 60 of the even-numbered unit column is connected to the third lead electrode 230 through the thirty-first via V31. It is connected to the fourth lead electrode 240 through the thirty-second via hole V32. Since the fourth connection electrode 44 is connected to the first region of the fourth active layer through the via hole, the data signal line 60 is realized to write the data signal into the first electrode of the fourth transistor T4.
  • the third lead electrode 230 is connected to the first lead electrode 210 through the via hole, and the first lead electrode 210 is connected to the first lead line, it is realized that the data signal line 60 of the odd-numbered unit column is connected to the first lead electrode 210 through the via hole. Connection of the first lead of a conductive layer (GATE1). Since the fourth lead electrode 240 is connected to the second lead electrode 220 through the via hole, and the second lead electrode 220 is connected to the second lead line, the data signal line 60 of the even-numbered unit column is connected to the second conductive layer (GATE2). Connection of the second lead wire.
  • the plurality of lead lines may include a plurality of first lead lines disposed on the first conductive layer (GATE1) and a plurality of first lead lines disposed on the second conductive layer.
  • a plurality of second lead lines of the layer (GATE2), the plurality of first lead lines can be connected to the data signal lines 60 of the odd-numbered unit columns through the first lead electrode 210 and the third lead electrode 230, and the plurality of second lead lines can be The second lead electrode 220 and the fourth lead electrode 240 are connected correspondingly to the data signal lines 60 of the even-numbered cell columns.
  • a plurality of first lead-out lines may be connected correspondingly to the data signal lines of the even-numbered unit columns, and a plurality of second lead-out lines may be correspondingly connected to the data signal lines of the odd-numbered unit columns.
  • This disclosure is not limited here. .
  • the shape of the anode connection electrode 52 may be a rectangular shape, and the anode connection electrode 52 is connected to the fifth connection electrode 45 through the twenty-third via hole V23.
  • the anode connection electrode 52 is configured to be connected to the subsequently formed anode. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer through the via hole, the anode is realized through the anode connection electrode. 52 and the fifth connection electrode 45 are connected to the second electrode of the sixth transistor T6.
  • the fourth conductive layer patterns of the plurality of circuit units in the third region may further include second power supply traces 92 .
  • the shape of the second power trace 92 may be a straight line with the main part extending along the second direction Y, and the second power trace 92 is connected to the power connection electrode 85 through the twenty-fourth via V24 . Since the power connection electrode 85 is connected to the first power trace 91 through the power connection block 86, the second power trace 92 and the first power trace 91 are connected to each other, so that the first power trace extending along the first direction The power trace 91 and the second power trace 92 extending along the second direction Y form a mesh connection structure.
  • the power supply traces in multiple unit rows and multiple unit columns have the same potential, which not only effectively reduces the resistance of the power supply traces, but also reduces the risk of transmitting low-voltage signals.
  • voltage drop and effectively improves the uniformity of low-voltage signals in the display substrate, effectively improves display uniformity, and improves display quality and display quality.
  • the fourth conductive layer patterns of the plurality of circuit units in the first region may further include second power supply traces 92 .
  • the second power trace 92 is connected to the dummy electrode 87 through the twenty-fifth via V25.
  • the second power supply traces 92 of the plurality of circuit units in the first region are not in contact with the dummy electrodes 87 .
  • the hole connection structure of 87 is basically the same as the hole connection structure of other regional circuit units. It can not only improve the uniformity of the preparation process, but also achieve the same display effect in different areas under transmitted and reflected light, improving the display screen. of uniformity.
  • the fourth conductive layer pattern of at least one circuit unit in the second region may further include a second connection line 72 , and other circuit units may include a second power supply trace 92 .
  • the shape of the second connection line 72 may be a straight line with the main body extending along the second direction Y, and the second connection line 72 is connected to the dummy electrode 87 through the twenty-fifth via hole V25.
  • the second power supply trace 92 is connected to the dummy electrode 87 through the twenty-fifth via hole V25.
  • the data signal line 60 of at least one circuit unit in the boundary area of the first area and the third area is connected to the data connection electrode 81 through the twenty-sixth via hole V26. Since the data connection electrode 81 is connected to the first connection line 71 through the data connection block, the connection between the data signal line 60 and the first connection line 71 is realized.
  • the second power traces 92 of other circuit units in the boundary area of the first area and the third area are connected to the dummy electrodes 87 through the twenty-fifth via hole V25.
  • the orthographic projection of the first break DF1 located between the first connection line 71 and the first power trace 91 on the substrate at least partially overlaps with the orthographic projection of the second power trace 92 on the substrate.
  • the orthographic projection of the first break DF1 on the substrate may be located within the range of the orthographic projection of the second power trace 92 on the substrate.
  • the fourth conductive layer pattern of the second connection unit in the boundary area of the first area and the second area may further include a second connection line 72.
  • the shape of the second connection line 72 may be a straight line with the main body portion extending along the second direction Y, and the second connection line 72 is connected to the fan-out connection electrode 83 through the twenty-seventh via hole V27. Since the fan-out connection electrode 83 is connected to the first connection line 71 through the fan-out connection block 84, the second connection line 72 and the first connection line 71 are connected to each other. Since the first connection line 71 is connected to the data signal line, the data signal line 60 is connected to the second connection line 72 through the first connection line 71 .
  • the second power traces 92 of other circuit units in the boundary area of the first area and the second area are connected to the dummy electrodes 87 through the twenty-fifth via hole V25.
  • At least one circuit unit in the first area adjacent to the second connection unit may be provided with at least one second break DF2.
  • the second break DF2 connects the second connection line 72 and the second break in the same circuit column.
  • the power trace 92 is cut off, and the side of the second break DF2 in the second direction Y is the second connecting wire 72 , and the side of the second break DF2 in the opposite direction to the second direction Y is the second power trace 92 .
  • the orthographic projection of the second fracture DF2 on the substrate at least partially overlaps the orthographic projection of the first connection line 71 on the substrate.
  • the orthographic projection of the second fracture DF2 on the substrate may be located within the range of the orthographic projection of the first connection line 71 on the substrate.
  • the fourth conductive layer pattern of the lead area in the bonding area at least includes the bonded power lead 410.
  • the shape of the binding power lead 410 may be a strip shape extending along the first direction X, and the binding power lead 410 is respectively connected to a plurality of second power traces 92 in the display area.
  • the bonded power lead 410 is configured to continuously provide a low level signal to the plurality of second power traces 92 of the display area.
  • a plurality of lead openings 420 may be provided on the binding power lead 410, and the fourth conductive film in the lead openings 420 is removed to expose the first planar layer.
  • the plurality of lead openings 420 are configured to release moisture vapor in the first planar layer.
  • the bonded high-voltage line 250 and the bonded power lead 410 in the lead area can be connected to the bonding pad in the bonded pin area after crossing the bending area and the driver chip area, and the external control device can be connected through the flexible
  • the circuit board and the bonding pad provide high-voltage signals and low-voltage signals to the bonded high-voltage line 250 and the bonded power lead 410 respectively.
  • the plurality of first power traces in the display area may be connected to the frame power leads of the frame area, and the connection structure between the first power traces and the power lead frame is connected to the aforementioned second power traces.
  • the connection structure is basically the same as that of the bound power leads and will not be described again here.
  • Figure 18a is a schematic diagram of the present disclosure showing that the first conductive layer pattern is formed in the lead area of the substrate. Since the lead area shown in FIG. 12b is the lead area corresponding to the third area in the display area, in the first conductive layer pattern of the lead area, there are only the first lead electrodes connected to the data signal lines of the odd-numbered unit columns. 210. As shown in FIG. 18a, for the lead area corresponding to the second area in the display area, since a second connection line is subsequently formed, the first conductive layer pattern of the lead area may also include an eleventh lead electrode 310. The eleventh lead electrode 310 is configured to be connected to the subsequently formed second connection line through the thirteenth lead electrode.
  • the lead area corresponding to the second area in the display area includes not only a plurality of first lead electrodes 210 but also a plurality of eleventh lead electrodes 310 in the first conductive layer and the display area.
  • the number of lead electrodes in the lead area corresponding to the second area in the area is different from the number of lead electrodes in the lead area corresponding to the third area in the display area.
  • the structures of the eleventh lead electrode 310 and the first lead electrode 210 may be substantially the same.
  • the first conductive layer pattern in the binding area may further include a plurality of first lead lines (not shown).
  • the shape of the first lead lines may be linear or polygonal.
  • the plurality of first lead lines may be linear or polygonal.
  • the first ends of the lines are connected to the first lead electrode 210 and the eleventh lead electrode 310 , and the second ends of the plurality of first lead lines extend in a direction away from the display area to the bending area of the binding area.
  • FIG. 18b is a schematic diagram of the present disclosure showing that the second conductive layer pattern is formed in the lead area of the substrate. Since the lead area shown in FIG. 13b is the lead area corresponding to the third area in the display area, in the second conductive layer pattern of the lead area, there are only the second lead electrodes connected to the data signal lines of the even-numbered unit columns. 220. As shown in FIG. 18b, for the lead area corresponding to the second area in the display area, since a second connection line is subsequently formed, the second conductive layer pattern of the lead area may also include a twelfth lead electrode 320. The twelve lead electrodes 320 are configured to be connected to the subsequently formed second connection lines through the fourteenth lead electrode.
  • the lead area corresponding to the second area in the display area includes not only a plurality of second lead electrodes 220 but also a plurality of twelfth lead electrodes 320 in the second conductive layer and the display area.
  • the number of lead electrodes in the lead area corresponding to the second area in the area is different from the number of lead electrodes in the lead area corresponding to the third area in the display area.
  • the structures of the twelfth lead electrode 320 and the second lead electrode 220 may be substantially the same.
  • the second conductive layer pattern in the binding area may further include a plurality of second lead-out lines (not shown).
  • the shape of the second lead-out line may be a straight line or a polygonal line.
  • the plurality of second lead-out lines may be The first ends of the lines are connected to the second lead electrode 220 and the twelfth lead electrode 320 , and the second ends of the plurality of second lead lines extend in a direction away from the display area to the bending area of the binding area.
  • FIG. 18c is a schematic diagram of the present disclosure showing that the fourth insulating layer pattern is formed in the lead area of the substrate. Since the lead area shown in FIG. 14b is the lead area corresponding to the third area in the display area, there are only the thirteenth via hole V13 and the fourteenth via hole V14 in the fourth insulation layer pattern of the lead area. As shown in Figure 18c, for the lead area corresponding to the second area in the display area, since the lead area is provided with an eleventh lead electrode 310 and a twelfth lead electrode 320, the fourth insulating layer pattern of the lead area is also Including the fifteenth via V15 and the sixteenth via V16.
  • the fifteenth via hole V15 exposes the surface of the eleventh lead electrode 310 and is configured to allow the subsequently formed thirteenth lead electrode 330 to be connected to the eleventh lead electrode 310 through the via hole.
  • the sixteenth via hole V16 exposes the surface of the twelfth lead electrode 320 , and the twelfth lead electrode 320 is configured so that the subsequently formed fourteenth lead electrode 340 is connected to the twelfth lead electrode 320 through the via hole.
  • FIG. 18d is a schematic diagram of the disclosure showing that the third conductive layer pattern is formed in the lead area of the substrate. Since the lead area shown in FIG. 15f is the lead area corresponding to the third area in the display area, there are only the third lead electrode 230 and the fourth lead electrode 240 in the third conductive layer pattern of the lead area. As shown in Figure 18d, for the lead area corresponding to the second area in the display area, since the lead area is provided with an eleventh lead electrode 310 and a twelfth lead electrode 320, the second conductive layer pattern of the lead area is also Thirteenth lead electrodes 330 and fourteenth lead electrodes 340 may be included.
  • the thirteenth lead electrode 330 is connected to the eleventh lead electrode 310 through the fifteenth via hole, and the thirteenth lead electrode 330 is configured to be connected to a second connection line formed subsequently.
  • the fourteenth lead electrode 340 is connected to the twelfth lead electrode 320 through the sixteenth via hole, and the fourteenth lead electrode 340 is configured to be connected to a second connection line formed subsequently.
  • two lead electrodes may be provided between the bonded high-voltage electrodes 260 adjacent in the first direction X, and in the display area In the lead area corresponding to the third area, only one lead electrode is provided between the adjacent bonded high-voltage electrodes 260 in the first direction X, so the number of lead electrodes in the two areas is different.
  • the structures of the thirteenth and fourteenth lead electrodes 330 and 340 and the structures of the third and fourth lead electrodes 230 and 240 may be substantially the same.
  • Figure 18e is a schematic diagram of the present disclosure showing that the first flat layer pattern is formed in the lead area of the substrate. Since the lead area shown in FIG. 16f is the lead area corresponding to the third area in the display area, there are only the 31st via hole V31 and the 32nd via hole in the first flat layer pattern of the lead area. V32. As shown in Figure 18e, for the lead area corresponding to the second area in the display area, since the lead area is provided with the thirteenth lead electrode 330 and the fourteenth lead electrode 340, the first flat layer pattern of the lead area is also The forty-first via V41 and the forty-second via V42 may be included.
  • the forty-first via hole V41 exposes the surface of the thirteenth lead electrode 330, and the forty-first via hole V41 is configured to allow a subsequently formed second connection line to connect to the thirteenth lead electrode 330 through the via hole.
  • the forty-second via hole V42 exposes the fourteenth lead electrode 340, and the forty-second via hole V42 is configured to allow a subsequently formed second connection line to be connected to the thirteenth lead electrode 330 through the via hole.
  • Figure 18f is a schematic diagram of the present disclosure showing that the fourth conductive layer pattern is formed in the lead area of the substrate. Since the lead area shown in FIG. 17f is the lead area corresponding to the third area in the display area, in the fourth conductive layer pattern of the lead area, only the data signal line 60 is connected to the third lead electrode 230 and the third lead electrode 230 respectively.
  • Four lead electrodes 240 are connected.
  • a plurality of second connection lines 72 are provided in the lead area. On the one hand, a part of the second connection line 72 extends behind the lead area and is connected to the thirteenth lead electrode 330 through the 41st via hole V41. The other part of the second connection line 72 extends behind the lead area and passes through the 42nd via hole V41.
  • the via hole V42 is connected to the thirteenth lead electrode 330 .
  • connection structure between the second connection line and the lead electrode is basically the same as the connection structure between the data signal line and the lead electrode, and will not be described again here.
  • the driver circuit layer is prepared on the substrate.
  • the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, and a third scanning signal line connected to the pixel driving circuit. Scanning signal lines, light emission control lines, data signal lines, first power supply lines, first initial signal lines and second initial signal lines.
  • the driving circuit layer may at least include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, and a second conductive layer sequentially stacked on the substrate.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, and polyether ether ketone. , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • the materials of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo wait.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Can be single layer, multi-layer or composite layer.
  • the first insulating layer is called a buffer layer
  • the second insulating layer and the third insulating layer are called gate insulating (GI) layers
  • the fourth insulating layer is called an interlayer insulating (ILD) layer.
  • the first flat layer can be made of organic materials, such as resin.
  • the active layer can use amorphous indium gallium zinc oxide materials (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), Materials such as hexathiophene or polythiophene, that is, this disclosure is applicable to transistors manufactured based on oxide (Oxide) technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide materials
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • a light-emitting structure layer and a packaging structure layer can be sequentially prepared on the driving circuit layer, which will not be described again here.
  • the present disclosure not only facilitates the layout of data connection lines, but also reduces the load of data signals and improves display quality.
  • the present disclosure can not only effectively reduce the resistance of the power wiring, effectively reduce the voltage drop of the low-voltage power signal, achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate. , effectively improving display uniformity, improving display quality and display quality.
  • the present disclosure enables different areas to have basically the same transfer connection structure, and different areas can achieve basically the same display effect under transmitted light and reflected light, effectively avoiding the appearance of the display substrate. Bad, improved display quality and display quality.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the display substrate of the present disclosure can be applied in a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc., this disclosure is not limited here.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc.
  • the present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiments.
  • the display substrate includes a display area and a binding area located on one side of the display area.
  • the display area includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of strips and a binding area.
  • the data signal line and the plurality of data connection lines are extended along the second direction.
  • the data connection lines include a first connection line extending along the first direction and a second connection line extending along the second direction.
  • the first connection line extends along the second direction.
  • the data signal line and the first connection line are formed in at least one circuit unit, the first connection line is connected to the data signal line through a first connection hole, and two adjacent second connection lines in the first direction At least one data signal line is provided between one connection hole.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the embodiments of the present invention are not limited thereto.

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  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板及其制备方法、显示装置。显示基板包括构成多个单元行和多个单元列的多个电路单元、多条数据信号线(60)和多条数据连接线(70)，数据连接线(70)包括沿着第一方向(X)延伸的第一连接线(71)和沿着第二方向(Y)延伸的第二连接线(72)，第一连接线(71)和第二连接线(72)连接；至少一个电路单元中，第一连接线(71)通过第一连接孔(K1)与数据信号线(60)连接，在第一方向上相邻的两个第一连接孔(K1)之间，设置有至少一条数据信号线(60)。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括构成多个单元行和多个单元列的多个电路单元、多条数据信号线和多条数据连接线，所述数据连接线包括沿着第一方向延伸的第一连接线和沿着第二方向延伸的第二连接线，所述第一连接线和所述第二连接线连接，所述第一方向和所述第二方向交叉；至少一个电路单元中，所述数据信号线通过第一连接孔与所述第一连接线连接，在所述第一方向上相邻的两个第一连接孔之间，设置有至少一条数据信号线。
在示例性实施方式中，所述第一连接孔设置在奇数单元列的电路单元中，在所述第一方向上相邻的两个第一连接孔之间，设置有m条数据信号线，m为大于或等于1的奇数。
在示例性实施方式中，所述第一连接孔设置在偶数单元列的电路单元 中，在所述第一方向上相邻的两个第一连接孔之间，设置有m条数据信号线，m为大于或等于1的奇数。
在示例性实施方式中，所述第一连接孔设置在奇数单元列的电路单元中，与所述第一连接孔在所述第一方向上相邻的另一个第一连接孔设置在偶数单元列的电路单元中；在所述第一方向上相邻的两个第一连接孔之间，设置有2条数据信号线。
在示例性实施方式中，至少一条第二连接线设置在所述第一方向上相邻的两条数据信号线之间。
在示例性实施方式中，所述第二连接线通过第二连接孔与所述第一连接线连接，连接同一条第一连接线的第一连接孔和第二连接孔，分别设置在所述第一连接线所述第二方向的两侧。
在示例性实施方式中，所述电路单元至少包括像素驱动电路，所述数据信号线与一个单元列中多个电路单元的像素驱动电路连接；所述多个单元列至少包括第一单元列和第二单元列，所述第一单元列中多个电路单元的像素驱动电路分别与出射红色光线的红色发光器件和出射蓝色光线的蓝色发光器件连接，所述第二单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接，所述第一连接线与所述第一单元列的数据信号线连接，所述第一连接线与所述第二单元列的数据信号线不连接。
在示例性实施方式中，所述显示区域还包括多条沿着所述第一方向延伸的第一电源走线和多条沿着所述第二方向延伸的第二电源走线，所述第二电源走线通过第三连接孔与所述第一电源走线连接。
在示例性实施方式中，所述第二电源走线设置在所述第一方向上相邻的两条数据信号线之间。
在示例性实施方式中，所述绑定区域设置有绑定电源引线，所述绑定电源引线与所述显示区域的多条第二电源走线连接。
在示例性实施方式中，所述显示基板还包括位于所述显示区域其它侧的边框区域，所述边框区域设置有边框电源引线，所述边框电源引线与所述显示区域的多条第一电源走线连接。
在示例性实施方式中，所述第一电源走线和所述第一连接线同层设置，至少一个电路单元包括第一断口，所述第一断口设置在所述第一连接线和所述第一电源走线之间，所述第一断口在显示基板平面上的正投影与所述第二电源走线在显示基板平面上的正投影至少部分交叠。
在示例性实施方式中，所述第二电源走线和所述第二连接线同层设置，至少一个电路单元包括第二断口，所述第二断口设置在所述第二连接线和所述第二电源走线之间，所述第二断口在显示基板平面上的正投影与所述第一连接线在显示基板平面上的正投影至少部分交叠。
在示例性实施方式中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述多条引出线包括第一引出线组和第二引出线组，第一引出线组中的引出线通过所述数据连接线与所述数据信号线连接，所述第二引出线组中的引出线与所述数据信号线连接。
在示例性实施方式中，所述第一引出线组的多条引出线按照编号递增的方式沿着所述第一方向依次设置，所述第二引出线组的多条引出线按照编号递增的方式沿着所述第一方向的反方向依次设置；或者，所述第一引出线组的多条引出线按照编号递增的方式沿着所述第一方向的反方向依次设置，所述第二引出线组的多条引出线按照编号递增的方式沿着所述第一方向依次设置。
在示例性实施方式中，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个晶体管；在垂直于显示基板的平面内，所述驱动电路层包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述半导体层至少包括多个晶体管的有源层，所述第一导电层至少包括多个晶体管的栅电极和存储电容的第一极板，所述第二导电层至少包括存储电容的第二极板，所述第三导电层至少包括多个晶体管的第一极、第二极和所述第一连接线，所述第四导电层至少包括所述数据信号线、所述第二连接线和第一电源线，所述数据信号线通过第一连接孔与所述第一连接线的第一端连接，所述第二连接线通过第二连接孔与所述第一连接线的第二端连接。
在示例性实施方式中，所述绑定区域至少包括引线区，所述引线区至少 包括多条引出线，多条引出线包括设置在所述第一导电层中的多条第一引出线和设置在所述第二导电层中的多条第二引出线；所述第一引出线与所述显示区域中奇数单元列的数据信号线连接，所述第二引出线与所述显示区域中偶数单元列的数据信号线连接；或者，所述第一引出线与所述显示区域中偶数单元列的数据信号线连接，所述第二引出线与所述显示区域中奇数单元列的数据信号线连接。
在示例性实施方式中，所述第一导电层还包括多个第一引线电极，所述第一引线电极与所述第一引出线连接；所述第二导电层还包括多个第二引线电极，所述第二引线电极与所述第二引出线连接；所述第三导电层还包括多个第三引线电极和多个第四引线电极，所述第三引线电极通过过孔与所述第一引线电极连接，所述第四引线电极通过过孔与所述第二引线电极连接；所述显示区域中奇数单元列的数据信号线通过过孔与第三引线电极连接，所述显示区域中偶数单元列的数据信号线通过过孔与第四引线电极连接；或者，所述显示区域中偶数单元列的数据信号线通过过孔与第三引线电极连接，所述显示区域中奇数单元列的数据信号线通过过孔与第四引线电极连接。
在示例性实施方式中，所述第三导电层还包括多条沿着所述第一方向延伸的第一电源走线，所述第四导电层还包括多条沿着所述第二方向延伸的第二电源走线，所述第二电源走线通过第三连接孔与所述第一电源走线连接。
在示例性实施方式中，所述绑定区域至少包括引线区，所述引线区至少包括多个绑定高压电极，多个绑定高压电极沿着所述第一方向依次设置，所述绑定高压电极被配置为与所述第一电源线连接，在所述第一方向相邻的绑定高压电极之间，设置有一个与所述数据信号线连接的引线电极。
在示例性实施方式中，部分相邻的绑定高压电极之间，还设置有一个与所述第二连接线连接的引线电极。
在示例性实施方式中，所述多个晶体管至少包括驱动晶体管、复位晶体管和补偿晶体管，所述存储电容包括第一极板和第二极板，所述第三导电层还包括第一连接电极和第二连接电极，所述第一连接电极分别与所述第一极板、所述驱动晶体管的栅电极、所述复位晶体管的第二极和所述补偿晶体管的第一极连接，所述第二连接电极分别与所述第二极板和所述第一电源线连 接。
在示例性实施方式中，所述第一连接电极在基底上的正投影与所述第一电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述第二连接电极在基底上的正投影与所述第一电源线在基底上的正投影至少部分交叠。
在示例性实施方式中，所述多个晶体管至少包括数据写入晶体管，至少一个电路单元中，所述第三导电层图案还包括数据连接电极，所述数据连接电极与所述第一连接线连接，所述数据连接电极和所述数据写入晶体管的第一极为共用结构。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括构成多个单元行和多个单元列的多个电路单元、多条数据信号线和多条数据连接线，所述数据连接线包括沿着第一方向延伸的第一连接线和沿着第二方向延伸的第二连接线，所述第一连接线和所述第二连接线连接，所述第一方向和所述第二方向交叉；所述制备方法包括：
在至少一个电路单元中形成所述数据信号线和第一连接线，所述第一连接线通过第一连接孔与所述数据信号线连接，在所述第一方向上相邻的两个第一连接孔之间，设置有至少一条数据信号线。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示基板中显示区域的平面结构示意图；
图4为一种显示基板中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路示意图；
图6为本公开示例性实施例一种显示基板的平面结构示意图；
图7a至图7e为本公开示例性实施例数据连接线的排布示意图；
图8a至图8b为本公开示例性实施例另一种显示基板的平面结构示意图；
图9为本公开示例性实施例一种电源走线的平面结构示意图；
图10为本公开示例性实施例一种数据连接线的结构示意图；
图11a和图11b为本公开显示基板形成半导体层图案后的示意图；
图12a和图12b为本公开显示基板形成第一导电层图案后的示意图；
图13a和图13b为本公开显示基板形成第二导电层图案后的示意图；
图14a和图14b为本公开显示基板形成第四绝缘层图案后的示意图；
图15a至图15f为本公开显示基板形成第三导电层图案后的示意图；
图16a至图16f为本公开显示基板形成第一平坦层图案后的示意图；
图17a至图17f为本公开显示基板形成第四导电层图案后的示意图；
图18a至图18f为本公开显示基板中引线区的结构示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；         13—第三有源层；
14—第四有源层；       15—第五有源层；         16—第六有源层；
17—第七有源层；       21—第一扫描信号线；     21-1—栅极块；
22—第二扫描信号线；   23—第三扫描信号线；     24—发光控制线；
25—第一极板；         31—第一初始信号线；     32—第二初始信号线；
33—第二极板；         34—极板连接线；         35—屏蔽电极；
36—开口；             41—第一连接电极；       42—第二连接电极；
43—第三连接电极；     44—第四连接电极；       45—第五连接电极；
46—第六连接电极；     47—第七连接电极；       51—第一电源线；
52—阳极连接电极；     60—数据信号线；         70—数据连接线；
71—第一连接线；       72—第二连接线；         80—引出线；
81—数据连接电极；     82—数据连接块；         83—扇出连接电极；
84—扇出连接块；       85—电源连接电极；       86—电源连接块；
87—虚设电极；         91—第一电源走线；       92—第二电源走线；
100—显示区域；        101—基底；              102—驱动电路层；
103—发光结构层；      104—封装结构层；        110—第一区域；
120—第二区域；        130—第三区域；          200—绑定区域；
201—引线区；          210—第一引线电极；      220—第二引线电极；
230—第三引线电极；    240—第四引线电极；      250—绑定高压线；
260—绑定高压电极；    300—边框区域；          301—阳极；
302—像素定义层；      303—有机发光层；        304—阴极；
310—第十一引线电极；  320—第十二引线电极；    330—第十三引线电极；
340—第十四引线电极；  401—第一封装层；        402—第二封装层；
403—第三封装层；      410—绑定电源引线；      420—引线开口；
510—边框电源引线。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也 不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的 电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施例中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn， n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施例中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素Pxij，多个子像素Pxij被配置为显示动态图片或静止图像，显示区域100可以称为有效区域(AA)。在示例性实施例中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施例中，绑定区域200可以包括沿着远离显示区域方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区，扇出区连接到显示区域100，至少包括数据扇出线，多条数据扇出线被配置为以扇出走线方式连接显示区域的数据信号线。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以包括集成电路(Integrated Circuit，简称IC)，集成电路被配置为与多条数据扇出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，绑定焊盘被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施例中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区 域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中像素驱动电路的第一扫描线、第二扫描线和发光控制线连接。电源线区连接到电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施例中，绑定区域200中的扇出区和边框区域300中的电源线区可以设置有第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施例中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施例中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用钻石形(Diamond)方式排列，形成RGBG像素排布。在其它示例性实施例中，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在示例性实施例中，像素单元可以包括三个子像素，三个子像素可以采 用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施例中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括由多个晶体管和存储电容构成的像素驱动电路。每个子像素的发光结构层103可以至少包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301与像素驱动电路连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
在示例性实施例中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施例中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是各自连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施例中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。图5为一种像素驱动电路的等效电路示意图。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与8个信号线(数据信号线D、第一扫描信号线S1、第二 扫描信号线S2、发光信号线E、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VDD和第二电源线VSS)连接。
在示例性实施例中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施例中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据信号线D的数据电压输 入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施例中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施例中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供的低电平信号，第一电源线VDD的信号为持续提供的高电平信号。
在示例性实施例中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施例中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜 晶体管和氧化物薄膜晶体管集成在一个显示基板上，即LTPS+Oxide(简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施例中，以第一晶体管T1到第七晶体管T7均为P型晶体管为例，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，第一初始信号线INIT1的第一初始电压提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据信号线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得第二初始信号线INIT2的第二初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E 的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
随着OLED显示技术的发展，消费者对显示产品显示效果的要求越来越高，极窄边框成为显示产品发展的新趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，绑定区域通常包括沿着远离显示区域的方向依次设置的扇出区、弯折区、驱动芯片区和绑定引脚区。由于绑定区域的宽度小于显示区域的宽度，绑定区域中集成电路和绑定焊盘的信号线需要通过扇出区以扇出(Fanout)走线方式才能引入到较宽的显示区域，显示区域与绑定区域的宽度差距越大，扇形区中斜向扇出线越多，驱动芯片区与显示区域之间的距离就越大，因而扇形区占用空间较大，导致下边框的窄化设计难度较大，下边框一直维持在2.0mm左右。另一种显示基板中，边框区域通常设置边框电源引线，边框电源引线被配置为传输低电压电源信号，为了减小低电压电源信号的压降，边框电源引线的宽度较大，导致显示装置左右边框的宽度较大。
本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸数据信号线和多条数据连接线，所述数据连接线包括沿着第一方向延伸的第一连接线和沿着第二方向延伸的第二连接线，所述第一连接线和所述第二连接线连接，所述第一方向和所述第二方向交叉；至少一个电路单元中，所述第一连接线通过第一连接孔与所述数 据信号线连接，在所述第一方向上相邻的两个第一连接孔之间，设置有至少一条数据信号线。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
图6为本公开示例性实施例一种显示基板的平面结构示意图。在垂直于显示基板的平面内，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。如图6所示，在平行于显示基板的平面内，显示基板可以至少包括显示区域100、位于显示区域100第二方向Y一侧的绑定区域200和位于显示区域100其它侧的边框区域300。在示例性实施例中，显示区域100的驱动电路层可以包括构成多个单元行和多个单元列的多个电路单元、多条数据信号线60和多条数据连接线70，至少一个电路单元可以包括像素驱动电路，像素驱动电路被配置为向所连接的发光器件输出相应的电流。显示区域100的发光结构层可以包括构成像素阵列的多个子像素，至少一个子像素可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施例中，至少一条数据信号线60与一个单元列中的多个像素驱动电路连接，数据信号线60被配置为向所连接的像素驱动电路提供数据信号，至少一条数据连接线70与数据信号线60对应连接，数据连接线70被配置为使数据信号线60通过数据连接线70与绑定区域200中的引出线80对应连接。
在示例性实施例中，本公开中所说的子像素，是指按照发光器件划分的区域，本公开中所说的电路单元，是指按照像素驱动电路划分的区域。在示例性实施例中，子像素在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，子像素在基底上正投影的位置与电路单元在基底 上正投影的位置可以是不对应的。
在示例性实施例中，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
在示例性实施例中，第二方向Y可以是数据信号线的延伸方向(竖直方向)，第一方向X可以与第二方向Y垂直(水平方向)。
在示例性实施例中，绑定区域200可以包括沿着远离显示区域方向依次设置的引线区201、弯折区、驱动芯片区和绑定引脚区，引线区201连接到显示区域100，弯折区连接到引线区201。引线区201可以设置多条引出线80，多条引出线80沿着远离显示区域的方向延伸，一部分引出线80的第一端与显示区域100中的数据连接线70对应连接，另一部分引出线的第一端与显示区域100中的数据信号线60对应连接，所有引出线80的第二端跨过弯折区连接复合电路区的集成电路，使得集成电路通过引出线和数据连接线将数据信号施加到数据信号线。由于数据连接线设置在显示区域，因而可以有效减小引线区第二方向Y的长度，大大缩减下边框宽度，提高了屏占比，有利于实现全面屏显示。
在示例性实施例中，显示区域100的多条数据信号线可以沿着第二方向Y延伸，并按照编号递增的方式沿着第一方向X以设定的间隔顺序设置。多条数据信号线可以按照是否与数据连接线连接划分为第一数据信号线组和第二数据信号线组，第一数据信号线组中的多条数据信号线与数据连接线对应连接，第二数据信号线组中的多条数据信号线不与数据连接线连接。引线区201的多条引出线可以按照是与数据连接线连接还是与数据信号线连接划分为第一引出线组和第二引出线组，第一引出线组中的多条引出线与数据连接线对应连接，第二引出线组中的多条引出线与数据信号线对应连接。
在示例性实施例中，设置在显示区域100的多条数据连接线70的第一端通过第一连接孔与第一数据信号线组的多条数据信号线60对应连接，多条数据连接线70的第二端向着绑定区域200的方向延伸并跨过显示区域边界B，与引线区201中第一引出线组的多条引出线80对应连接，使得显示区域100 中第一数据信号线组的多条数据信号线60通过数据连接线70与引出线80间接连接。第二数据信号线组的多条数据信号线60向着绑定区域200的方向延伸并跨过显示区域边界B，与引线区201中第二引出线组的多条引出线80对应连接，使得显示区域100中第二数据信号线组的多条数据信号线60与引出线80直接连接。在示例性实施例中，显示区域边界B是显示区域100和绑定区域200的交界处。
在示例性实施例中，引出线80与数据信号线60、引出线80与数据连接线70可以直接连接，或者可以通过过孔连接，本公开在此不做限定。
在示例性实施例中，数据连接线70可以包括第一连接线和第二连接线，第一连接线和第二连接线相互连接。第一连接线的第一端通过第一连接孔与数据信号线连接，第一连接线的第二端沿着第一方向X或者第一方向X的反方向延伸后，与第二连接线的第一端连接，第二连接线的第二端沿着第二方向Y向着引线区的方向延伸后与引出线连接。
在示例性实施例中，在第一方向X上相邻的两个第一连接孔之间，可以设置有至少一条数据信号线。
在示例性实施例中，至少一条第二连接线可以设置在相邻的数据信号线之间，或者，至少一个第二连接孔可以设置在相邻的数据信号线之间。
在示例性实施例中，在第一方向X上相邻的第二连接线之间(在第一方向X上相邻的第二连接孔之间)，可以设置有n条数据信号线，n可以为大于或等于1的正整数。在示例性实施例中，n可以为1、2、3、4、5或6。例如，当n＝1时，相邻的第二连接线之间可以设置有1条数据信号线。又如，当n＝2时，相邻的第二连接线之间可以设置有2条数据信号线。再如，当n＝3时，相邻的第二连接线之间可以设置有3条数据信号线。
在示例性实施例中，多条第二连接线可以设置成与数据信号线平行，多条第一连接线可以设置成与数据信号线垂直。
在示例性实施例中，相邻第二连接线之间的间距可以基本上相同，相邻第一连接线之间的间距可以基本上相同，本公开在此不做限定。
在示例性实施例中，显示区域100可以具有中心线O，显示区域100中 的多条数据信号线60、多条数据连接线70和引线区201中的多条引出线80可以相对于中心线O对称设置，中心线O可以为平分显示区域100的多个单元列并沿着第二方向Y延伸的直线。
下面以显示区域100左侧包括NA条数据信号线、NB条数据连接线和NA条引出线为例进行说明，NA为大于或等于2的正整数，NB为大于或等于2且小于或等于NA的正整数。
在一种示例性实施例中，第一连接孔设置在奇数单元列的电路单元中，即第一数据信号线组可以包括NB条奇数的数据信号线，第二数据信号线组可以包括第一数据信号线组以外的数据信号线。例如，第一数据信号线组可以包括第一数据信号线、第三数据信号线、……、第2NB-1数据信号线，第二数据信号线组可以包括第二数据信号线、第四数据信号线、……、第2NB数据信号线至第NA数据信号线。本公开中，奇数的数据信号线是指设置在奇数单元列的数据信号线，偶数的数据信号线是指设置在偶数单元列的数据信号线。
在示例性实施例中，在第一方向X上相邻的两个第一连接孔之间，可以设置有m条数据信号线，m为大于或等于1的奇数。例如，第一数据信号线组包括第一数据信号线、第三数据信号线、……、第2NB-1数据信号线时，第一数据信号线组中相邻的2条数据信号线之间(相邻的两个第一连接孔之间)设置有1条第二数据信号线组的数据信号线。又如，第一数据信号线组包括第一数据信号线、第五数据信号线、……、第4NB-3数据信号线时，第一数据信号线组中相邻的2条数据信号线之间(相邻的两个第一连接孔之间)设置有3条第二数据信号线组的数据信号线。
在另一种示例性实施例中，第一连接孔设置在偶数单元列的电路单元中，即第一数据信号线组可以包括NB条偶数的数据信号线，第二数据信号线组可以包括第一数据信号线组以外的数据信号线。例如，第一数据信号线组可以包括第二数据信号线、第四数据信号线、……、第2NB数据信号线，第二数据信号线组可以包括第一数据信号线、第三数据信号线、……、第2NB-1数据信号线、第2NB+1数据信号线至第NA数据信号线。
在示例性实施例中，在第一方向X上相邻的两个第一连接孔之间，可以 设置有m条数据信号线，m为大于或等于1的奇数。例如，第一数据信号线组包括第二数据信号线、第四数据信号线、……、第2M数据信号线时，第一数据信号线组中相邻的2条数据信号线之间(相邻的两个第一连接孔之间)设置有1条第二数据信号线组的数据信号线。又如，第一数据信号线组包括第二数据信号线、第六数据信号线、……、第4NB-2数据信号线时，第一数据信号线组中相邻的2条数据信号线之间(相邻的两个第一连接孔之间)设置有3条第二数据信号线组的数据信号线。
在又一种示例性实施例中，第一连接孔可以分别设置在奇数单元列的电路单元和偶数单元列的电路单元中。一个第一连接孔可以设置在奇数单元列的电路单元中，与该第一连接孔在第一方向X上相邻的另一个第一连接孔可以设置在偶数单元列的电路单元中。或者，一个第一连接孔可以设置在偶数单元列的电路单元中，与该第一连接孔在第一方向X上相邻的另一个第一连接孔可以设置在奇数单元列的电路单元中。在第一方向X上相邻的两个第一连接孔之间，可以设置有2条数据信号线。例如，第一数据信号线组可以包括第一数据信号线、第四数据信号线、第七数据信号线、……、第3NB-2数据信号线，第一数据信号线和第四数据信号线之间设置有第二数据信号线和第三数据信号线。
在示例性实施例中，引线区左侧的NB条引出线中，第一引出线组的多条引出线可以按照编号递增的方式沿着第一方向X的反方向依次设置(逆序设计)，第二引出线组的多条引出线可以按照编号递增的方式沿着第一方向X依次设置(正序设计)。引线区右侧的NB条引出线中，第一引出线组的多条引出线可以按照编号递增的方式沿着第一方向X依次设置，第二引出线组的多条引出线可以按照编号递增的方式沿着第一方向X的反方向依次设置。
在示例性实施例中，第一引出线组中相邻的2条引出线之间设置有第二引出线组的n条引出线，n可以为1、2、3、4、5或6。例如，当n＝1时，第一引出线组中的相邻的引出线之间可以设置有第二引出线组的1条引出线。又如，当n＝2时，第一引出线组中的相邻的引出线之间可以设置有第二引出线组的2条引出线。
在一种示例性实施例中，第一引出线组可以包括NB条奇数的引出线，NB条奇数的引出线通过NB条数据连接线与第一数据信号线组的NB条奇数的数据信号线连接。第二引出线组可以包括第一引出线组以外的其它引出线，与第二数据信号线组的多条数据信号线连接。
在另一种示例性实施例中，第一引出线组可以包括NB条偶数的引出线，NB条偶数的引出线通过NB条数据连接线与第一数据信号线组的NB条偶数数据信号线连接。第二引出线组可以包括第一引出线组以外的其它引出线，与第二数据信号线组的多条数据信号线连接。
在又一种示例性实施例中，第一引出线组可以包括奇数的引出线和偶数的引出线。一条引出线可以是奇数的引出线，与该引出线在第一方向X上相邻的另一条引出线可以是偶数的引出线。第一引出线组的多条引出线通过多条数据连接线与第一数据信号线组的多条数据信号线连接，第二引出线组的多条引出线与第二数据信号线组的多条数据信号线连接。
在示例性实施例中，第二引出线组中的一部分引出线可以为与数据信号线平行的直线，另一部分引出线可以为折线。
图7a为本公开示例性实施例一种数据连接线的排布示意图，为图6中C1区域的放大图，示意了16条数据信号线、4条数据连接线和16条引出线的结构。图7a所示，在示例性实施例中，显示区域的多条数据信号线可以包括第一数据信号线60-1至第十六数据信号线60-16，显示区域的多条数据连接线可以包括第一数据连接线70-1至第四数据连接线70-4，引线区201的多条引出线可以包括第一引出线80-1至第十六引出线80-16。
在示例性实施例中，第一数据信号线组包括4个奇数的数据信号线(第一数据信号线60-1、第三数据信号线60-3、第五数据信号线60-5和第七数据信号线60-7)，第二数据信号线组包括其余的12条数据信号线，第一数据信号线60-1至第十六数据信号线60-16可以沿着第一方向X顺序设置。
在示例性实施例中，第一引出线组包括4个奇数的引出线(第一引出线80-1、第三引出线80-3、第五引出线80-5和第七引出线80-7)，第二引出线组包括其余的12条引出线，第一引出线组的多条引出线可以沿着第一方向X 的反方向顺序设置，第二引出线组的多条引出线可以沿着第一方向X顺序设置，且第一引出线组中相邻的引出线之间设置有2条第二引出线组的引出线。例如，多条引出线可以包括沿着第一方向X顺序设置的第二引出线80-2、第四引出线80-4、第六引出线80-6、第八引出线80-8、第九引出线80-9、第七引出线80-7、第十引出线80-10、第十一引出线80-11、第五引出线805、第十二引出线80-12、第十三引出线80-13、第三引出线803、第十四引出线80-14、第十五引出线80-15、第一引出线80-1和第十六引出线80-16。
在示例性实施例中，第一引出线80-1和第三引出线80-3之间可以设置有第十四引出线80-14和第十五引出线80-15，第三引出线80-3和第五引出线80-5之间可以设置有第十二引出线80-12和第十三引出线80-13，第五引出线80-5和第七引出线80-7之间可以设置有第十引出线80-10和第十一引出线80-11。
在示例性实施例中，第一连接孔设置在奇数单元列的电路单元中。第一数据连接线70-1的第一端在显示区域100通过第一连接孔与第一数据信号线60-1连接，第二端延伸到引线区201后与第一引出线80-1连接。第二数据连接线70-2的第一端在显示区域100通过第一连接孔与第三数据信号线60-3连接，第二端延伸到引线区201后与第三引出线80-3连接。第三数据连接线70-3的第一端在显示区域100通过第一连接孔与第五数据信号线60-5连接，第二端延伸到引线区201后与第五引出线80-5连接。第四数据连接线70-4的第一端在显示区域100通过第一连接孔与第七数据信号线60-7连接，第二端延伸到引线区201后与第七引出线80-7连接。
在示例性实施例中，第二数据信号线组的多条数据信号线延伸到引线区201后与第二引出线组的多条引出线对应连接。例如，第二数据信号线60-2、第四数据信号线60-4、第六数据信号线60-6、第八数据信号线60-8至第十六数据信号线60-16与相应的引出线对应连接。
在示例性实施例中，数据连接线与数据信号线对应连接的多个第一连接孔与显示区域边缘B的距离可以不同。例如，第一数据连接线70-1与第一数据信号线60-1连接的第一连接孔与显示区域边缘B的距离可以大于第二数据连接线70-2与第三数据信号线60-3连接的第一连接孔与显示区域边缘B的 距离。又如，第二数据连接线70-2与第三数据信号线60-3连接的第一连接孔与显示区域边缘B的距离可以大于第三数据连接线70-3与第五数据信号线60-5连接的第一连接孔与显示区域边缘B的距离。再如，第三数据连接线70-3与第五数据信号线60-5连接的第一连接孔与显示区域边缘B的距离可以大于第四数据连接线70-4与第七数据信号线60-7连接的第一连接孔与显示区域边缘B的距离。
在示例性实施例中，数据连接线可以包括依次连接的第一连接线和第二连接线。第一连接线的形状可以为沿着第一方向X延伸的直线状，第二连接线的形状可以为沿着第二方向Y延伸的直线状。第一连接线的第一端通过第一连接孔与数据信号线连接，第一连接线的第二端沿着第一方向X或者第一方向X的反方向延伸后与第二连接线的第一端连接，第二连接线的第二端沿着第二方向Y向着引线区的方向延伸后与引出线连接。
在示例性实施例中，在第一方向X上相邻的第二连接线之间，可以设置有2条数据信号线，形成数据连接线与奇数单元列的数据信号线连接、相邻的第二连接线之间设置有2条数据信号线的结构。例如，第一数据连接线70-1的第二连接线与第二数据连接线70-2的第二连接线之间可以设置有第十四数据信号线60-14和第十五数据信号线60-15。又如，第二数据连接线70-2的第二连接线与第三数据连接线70-3的第二连接线之间可以设置有第十二数据信号线60-12和第十三数据信号线60-13。再如，第三数据连接线70-3的第二连接线与第四数据连接线70-4的第二连接线之间可以设置有第十数据信号线60-10和第十一数据信号线60-11。
在示例性实施例中，第二引出线组中的一部分引出线为与数据信号线平行的直线，另一部分引出线为折线。例如，第十引出线80-10至第十六引出线80-16的形状可以为直线，第二引出线80-2、第四引出线80-4和第六引出线80-6的形状可以为折线。
在示例性实施例中，发光结构层中的多个子像素的位置与驱动结构层中多个电路单元的位置可以是对应的，奇数单元列可以称为第一单元列，奇数单元列的多个电路单元对应多个红色子像素和蓝色子像素，即奇数单元列中多个电路单元的像素驱动电路分别与出射红色光线的红色发光器件和出射蓝 色光线的蓝色发光器件连接，偶数单元列可以称为第二单元列，偶数单元列的多个电路单元对应多个绿色子像素，即偶数单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接。
在示例性实施例中，第一连接线通过第一连接孔与第一单元列的数据信号线连接，第一连接线与第二单元列的数据信号线不连接。本公开通过将第一连接孔设置在奇数单元列，即红色子像素和蓝色子像素的数据信号采用数据连接线传输，不仅可以方便数据连接线的布局，而且利用逆序设计可以实现负载无突变，提高显示品质。
图7b为本公开示例性实施例另一种数据连接线的排布示意图，为图6中C1区域的放大图，示意了16条数据信号线、4条数据连接线和16条引出线的结构。图7b所示，在示例性实施例中，本示例性实施例为数据连接线与奇数单元列的数据信号线连接、相邻的第二连接线之间设置有1条数据信号线的结构。
在示例性实施例中，第一数据信号线组包括4个奇数的数据信号线，与4条数据连接线的第一端对应连接，第一引出线组包括4个奇数的引出线，与4条数据连接线的第二端对应连接，第二数据信号线组的12条数据信号线与第二引出线组的12条引出线对应连接，连接结构与图7a所示结构基本上相同。所不同的是，第一引出线组中相邻的引出线之间设置有至1条第二引出线组的引出线，相邻的第二连接线之间设置有1条数据信号线。
在示例性实施例中，多条引出线可以包括沿着第一方向X依次设置的第二引出线80-2、第四引出线80-4、第六引出线80-6、第八引出线80-8、第七引出线80-7、第九引出线80-9、第五引出线80-5、第十引出线80-10、第三引出线80-3、第十一引出线80-11、第一引出线80-1、第十二引出线80-12、第十三引出线80-13、第十四引出线80-14、第十五引出线80-15和第十六引出线80-16。
在示例性实施例中，第一引出线80-1和第三引出线80-3之间可以设置有第十一引出线80-11，第三引出线80-3和第五引出线80-5之间可以设置有第十引出线80-10，第五引出线80-5和第七引出线80-7之间可以设置有第九引出线80-9。
在示例性实施例中，在第一方向X上相邻的第二连接线之间，可以设置有1条数据信号线。例如，第一数据连接线70-1的第二连接线与第二数据连接线70-2的第二连接线之间可以设置有第十一数据信号线60-11。又如，第二数据连接线70-2的第二连接线与第三数据连接线70-3的第二连接线之间可以设置有第十数据信号线60-10。再如，第三数据连接线70-3的第二连接线与第四数据连接线70-4的第二连接线之间可以设置有第九数据信号线60-9。
在示例性实施例中，本示例性实施例不仅可以方便数据连接线的布局和负载无突变，而且通过在相邻的第二连接线之间设置有1条数据信号线的结构，可以进一步压缩数据连接线的占用空间，可以最小化数据信号负载差异。
图7c为本公开示例性实施例又一种数据连接线的排布示意图，为图6中C1区域的放大图，示意了16条数据信号线、4条数据连接线和16条引出线的结构。图7c所示，在示例性实施例中，本示例性实施例为数据连接线与偶数单元列的数据信号线连接、相邻的第二连接线之间设置有2条数据信号线的结构。
在示例性实施例中，第一数据信号线组包括4个偶数的数据信号线(第二数据信号线60-2、第四数据信号线60-4、第六数据信号线60-6和第八数据信号线60-8)，第二数据信号线组包括其余的12条数据信号线，第一数据信号线60-1至第十六数据信号线60-16可以沿着第一方向X依次设置。
在示例性实施例中，第一引出线组包括4个偶数的引出线(第二引出线80-2、第四引出线80-4、第六引出线80-6和第八引出线80-8)，第二引出线组包括其余的12条引出线，第一引出线组的多条引出线可以沿着第一方向X的反方向依次设置，第二引出线组的多条引出线可以沿着第一方向X依次设置，且第一引出线组中相邻的引出线之间设置有2条第二引出线组的引出线。例如，多条引出线可以包括沿着第一方向X依次设置的第一引出线80-1、第三引出线80-3、第五引出线80-5、第七引出线80-7、第九引出线80-9、第八引出线80-8、第十引出线80-10、第十一引出线80-11、第六引出线80-6、第十二引出线80-12、第十三引出线80-13、第四引出线80-4、第十四引出线80-14、第十五引出线80-15、第二引出线80-2和第十六引出线80-16。
在示例性实施例中，第二引出线80-2和第四引出线80-4之间可以设置有第十四引出线80-14和第十五引出线80-15，第四引出线80-4和第六引出线80-6之间可以设置有第十二引出线80-12和第十三引出线80-13，第六引出线80-6和第八引出线80-8之间可以设置有第十引出线80-10和第十一引出线80-11。
在示例性实施例中，第一连接孔设置在偶数单元列的电路单元中。第一数据连接线70-1的第一端在显示区域100通过第一连接孔与第二数据信号线60-2连接，第二端延伸到引线区201后与第二引出线80-2连接。第二数据连接线70-2的第一端在显示区域100通过第一连接孔与第四数据信号线60-4连接，第二端延伸到引线区201后与第四引出线80-4连接。第三数据连接线70-3的第一端在显示区域100通过第一连接孔与第六数据信号线60-6连接，第二端延伸到引线区201后与第六引出线80-6连接。第四数据连接线70-4的第一端在显示区域100通过第一连接孔与第八数据信号线60-8连接，第二端延伸到引线区201后与第八引出线80-8连接。
在示例性实施例中，第二数据信号线组的多条数据信号线延伸到引线区201后与第二引出线组的多条引出线对应连接。例如，第一数据信号线60-1、第三数据信号线60-3、第五数据信号线60-5、第七数据信号线60-7、第九数据信号线60-9至第十六数据信号线60-16与相应的引出线对应连接。
在示例性实施例中，在第一方向X上相邻的第二连接线之间，可以设置有2条数据信号线，形成数据连接线与偶数单元列的数据信号线连接、相邻的第二连接线之间设置有2条数据信号线的结构。例如，第一数据连接线70-1的第二连接线与第二数据连接线70-2的第二连接线之间可以设置有第十四数据信号线60-14和第十五数据信号线60-15。又如，第二数据连接线70-2的第二连接线与第三数据连接线70-3的第二连接线之间可以设置有第十二数据信号线60-12和第十三数据信号线60-13。再如，第三数据连接线70-3的第二连接线与第四数据连接线70-4的第二连接线之间可以设置有第十数据信号线60-10和第十一数据信号线60-11。
在示例性实施例中，第二引出线组中的一部分引出线为与数据信号线平行的直线，另一部分引出线为折线。例如，第九引出线80-9至第十六引出线 80-16的形状可以为直线，第一数据信号线60-1、第三数据信号线60-3、第五数据信号线60-5和第七数据信号线60-7的形状可以为折线。
在示例性实施例中，发光结构层中的多个子像素的位置与驱动结构层中多个电路单元的位置可以是对应的，奇数单元列的多个电路单元对应多个红色子像素和蓝色子像素，偶数单元列的多个电路单元对应多个绿色子像素。本公开通过将数据连接线设置在偶数单元列，即绿色子像素的数据信号采用数据连接线传输，不仅可以方便数据连接线的布局，而且利用逆序设计可以实现负载无突变，提高显示品质。
图7d为本公开示例性实施例又一种数据连接线的排布示意图，为图6中C1区域的放大图，示意了16条数据信号线、4条数据连接线和16条引出线的结构。图7d所示，在示例性实施例中，本示例性实施例为数据连接线与偶数单元列的数据信号线连接、相邻的第二连接线之间设置有1条数据信号线的结构。
在示例性实施例中，第一数据信号线组包括4个偶数的数据信号线，与4条数据连接线的第一端对应连接，第一引出线组包括4个偶数的引出线，与4条数据连接线的第二端对应连接，第二数据信号线组的12条数据信号线与第二引出线组的12条引出线对应连接，连接结构与图7c所示结构基本上相同。所不同的是，第一引出线组中相邻的引出线之间设置有至1条第二引出线组的引出线，相邻的第二连接线之间设置有1条数据信号线。
在示例性实施例中，多条引出线可以包括沿着第一方向X依次设置的第一引出线80-1、第三引出线80-3、第五引出线80-5、第七引出线80-7、第九引出线80-9、第八引出线80-8、第十引出线80-10、第六引出线80-6、第十一引出线80-11、第四引出线80-4、第十二引出线80-12、第二引出线80-2、第十三引出线80-13、第十四引出线80-14、第十五引出线80-15和第十六引出线80-16。
在示例性实施例中，第二引出线80-2和第四引出线80-4之间可以设置有第十二引出线80-12，第四引出线80-4和第六引出线80-6之间可以设置有第十一引出线80-11，第六引出线80-6和第八引出线80-8之间可以设置有第十引出线80-10。
在示例性实施例中，在第一方向X上相邻的第二连接线之间，可以设置有1条数据信号线。例如，第一数据连接线70-1的第二连接线与第二数据连接线70-2的第二连接线之间可以设置有第十二数据信号线60-12。又如，第二数据连接线70-2的第二连接线与第三数据连接线70-3的第二连接线之间可以设置有第十一数据信号线60-11。再如，第三数据连接线70-3的第二连接线与第四数据连接线70-4的第二连接线之间可以设置有第十数据信号线60-10。
在示例性实施例中，本示例性实施例不仅可以方便数据连接线的布局和负载无突变，而且通过在相邻的第二连接线之间设置有1条数据信号线的结构，可以进一步压缩数据连接线的占用空间，可以最小化数据信号负载差异。
图7a至图7d分别示意了第一数据信号线组中相邻的数据信号线之间设置第二数据信号线组的1条数据信号线的示例性结构，在一些其它的示例性实施例中，第一数据信号线组中相邻的数据信号线之间可以设置有3条以上的奇数条第二数据信号线组的数据信号线，本公开在此不做限定。
图7a和图7c分别示意了相邻的第二连接线之间设置有2条数据信号线的示例性结构，图7b和图7d分别示意了相邻的第二连接线之间设置有1条数据信号线的示例性结构，在一些其它的示例性实施例中，相邻的第二连接线之间可以设置有3条以上数据信号线，本公开在此不做限定。
图7e为本公开示例性实施例又一种数据连接线的排布示意图，为图6中C1区域的放大图，示意了16条数据信号线、4条数据连接线和16条引出线的结构。图7e所示，在示例性实施例中，本示例性实施例的第一连接孔分别设置在奇数单元列的电路单元和偶数单元列的电路单元中。
在示例性实施例中，第一数据信号线组包括2个奇数的数据信号线(第一数据信号线60-1和第七数据信号线60-7)和2个偶数的数据信号线(第四数据信号线60-4和第十数据信号线60-10)，第二数据信号线组包括其余的12条数据信号线，第一数据信号线60-1至第十六数据信号线60-16可以沿着第一方向X依次设置。
在示例性实施例中，第一引出线组包括2个奇数的引出线(第一引出线80-1和第七引出线80-7)和2个偶数的引出线(第四引出线80-4和第十引出 线80-10)，第二引出线组包括其余的12条引出线，第一引出线组的多条引出线可以沿着第一方向X的反方向依次设置，第二引出线组的多条引出线可以沿着第一方向X依次设置，且第一引出线组中相邻的引出线之间设置有1条第二引出线组的引出线。
在示例性实施例中，第一连接孔分别设置在奇数单元列的电路单元和偶数单元列的电路单元中。第一数据连接线70-1的第一端在显示区域100通过第一连接孔与第一数据信号线60-1连接，第二端延伸到引线区201后与第一引出线80-1连接。第二数据连接线70-2的第一端在显示区域100通过第一连接孔与第四数据信号线60-4连接，第二端延伸到引线区201后与第四引出线80-4连接。第三数据连接线70-3的第一端在显示区域100通过第一连接孔与第七数据信号线60-7连接，第二端延伸到引线区201后与第七引出线80-7连接。第四数据连接线70-4的第一端在显示区域100通过第一连接孔与第十数据信号线60-10连接，第二端延伸到引线区201后与第十引出线80-10连接。
在示例性实施例中，在第一方向X上相邻的第二连接线之间，可以设置有1条数据信号线，形成相邻的第二连接线之间设置有1条数据信号线的结构。
图8a为本公开示例性实施例另一种显示基板的平面结构示意图，图8b为图8a中C2区域的放大图。显示区域100的驱动电路层可以包括组成电路单元阵列的多个电路单元、多条数据信号线60、多条数据连接线70和网状连通结构的电源走线90，多个电路单元、多条数据信号线60和多条数据连接线70的布局和结构与前述图6所示布局和结构基本上相同。
在示例性实施例中，数据连接线70可以包括沿着第一方向X延伸的第一连接线71和沿着第二方向Y延伸的第二连接线72。第一连接线71和第二连接线72可以设置在不同的导电层中，第一连接线71和数据信号线60可以设置在不同的导电层中，第一连接线71的第一端通过第一连接孔K1与数据信号线60连接，第一连接线71的第二端沿着第一方向X或者第一方向X的反方向延伸后，通过第二连接孔K2与第二连接线72的第一端连接，第二连接线72的第二端沿着第二方向Y向着引线区的方向延伸后与引出线80连接， 第二连接线72可以设置在相邻的数据信号线60之间。
在示例性实施例中，连接同一条第一连接线71的第一连接孔K1和第二连接孔K2，可以分别设置在该第一连接线71第二方向Y的两侧。
在示例性实施例中，电源走线90可以包括多条沿着第一方向X延伸的第一电源走线91和多条沿着第二方向Y延伸的第二电源走线92，多条第一电源走线91可以沿着第二方向Y依次设置，多条第二电源走线92可以沿着第一方向X依次设置。
在示例性实施例中，第一电源走线91和第二电源走线92可以设置在不同的导电层中，第二电源走线92可以设置在相邻的数据信号线60之间，至少一条第二电源走线92可以通过第三连接孔K3与至少一条第一电源走线91连接，使得多条第一电源走线91和多条第二电源走线92构成网状连通结构的电源走线90。
在示例性实施例中，第一连接孔K1可以设置在奇数单元列的电路单元中，在第一方向X上相邻的两个第一连接孔K1之间，可以设置有1条数据信号线60和2条第二电源走线92。
在示例性实施例中，在第一方向X上相邻的两条第二连接线72之间，可以设置有2条数据信号线60和1条第二电源走线92。
在示例性实施例中，第一电源走线91和第一连接线71可以同层设置，且通过同一次图案化工艺同步形成，第二电源走线92和第二连接线72可以同层设置，且通过同一次图案化工艺同步形成。
在示例性实施例中，至少一个电路行中可以仅设置有一条第一电源走线91，且该电路行中没有设置第一连接线71。
在示例性实施例中，至少一个电路行中可以设置有至少一条第一电源走线91和至少一条第一连接线71，第一电源走线91和第一连接线71之间设置有第一断口DF1，第一断口DF1被配置为实现第一电源走线91和第一连接线71之间的绝缘。
在示例性实施例中，至少一个电路列中可以仅设置有一条第二电源走线92，且该电路列中没有设置第二连接线72。
在示例性实施例中，至少一个电路列可以设置有至少一条第二电源走线92和至少一条第二连接线72，第二电源走线92和第二连接线72之间设置有第二断口DF2，第二断口DF2被配置为实现第二电源走线92和第二连接线72之间的绝缘。
在示例性实施例中，电源走线90可以为持续提供的低电平信号。例如，电源走线90可以为第二电源线VSS。
图9为本公开示例性实施例一种电源走线的平面结构示意图。如图9所示，显示基板可以包括显示区域100、位于显示区域100第二方向Y一侧的绑定区域200以及位于显示区域100其它侧的边框区域300，显示区域100设置有网格状的电源走线90，绑定区域200设置有绑定电源引线410，边框区域300设置有边框电源引线510，电源走线90分别与绑定电源引线410和边框电源引线510连接。
在示例性实施例中，绑定区域200的绑定电源引线410和边框区域300的边框电源引线510可以为相互连接的一体结构。
在示例性实施例中，显示区域100的电源走线90可以包括多条沿着第一方向X延伸的第一电源走线91和多条沿着第二方向Y延伸的第二电源走线92，多条第一电源走线91可以沿着第二方向Y依次设置，且第一方向X的一端或两端与边框电源引线510连接，多条第二电源走线92可以沿着第一方向X依次设置，且第二方向Y的一端与绑定电源引线410连接。
在示例性实施例中，第二电源走线92第二方向Y的反方向的一端可以与边框电源引线510连接。
在示例性实施例中，第一电源走线91和第二电源走线92可以设置在不同的导电层中，至少一条第二电源走线92可以通过第三连接孔与至少一条第一电源走线91连接，使得多条第一电源走线91和多条第二电源走线92具有相同的电位。本公开通过在显示区域内设置电源走线，实现了低压线设置在子像素(VSS in pixel)的结构，可以大幅度减小边框电源引线的宽度，有利于实现窄边框。本公开通过将电源走线设置成网状连通结构，不仅可以有效降低电源走线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可 以有效提升显示基板中电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
图10为本公开示例性实施例一种数据连接线的结构示意图。如图10所示，由于数据连接线设置在显示区域中的部分区域，且数据连接线包括沿着第一方向X延伸的第一连接线和沿着第二方向Y延伸的第二连接线，因而可以按照有无数据连接线以及数据连接线的延伸方向作为划分依据，将显示区域划分为第一区域110、第二区域120和第三区域130，第一区域110可以是设置有第一连接线71的区域(扇出线横向走线区域)，第二区域120可以是设置有第二连接线72的区域(扇出线纵向走线区域)，第三区域130可以是没有设置第一连接线71和第二连接线72的区域(正常区域)。
在示例性实施例中，第一区域110可以包括多个电路单元，第一连接线71在显示基板平面上的正投影与第一区域110的多个电路单元中像素驱动电路在显示基板平面上的正投影至少部分交叠，第一区域110的多个电路单元中像素驱动电路在显示基板平面上的正投影与第二连接线72在显示基板平面上的正投影没有重叠。
在示例性实施例中，第二区域120可以包括多个电路单元，第二连接线72在显示基板平面上的正投影与第二区域120的多个电路单元中像素驱动电路在显示基板平面上的正投影至少部分交叠，第二区域120的多个电路单元中像素驱动电路在显示基板平面上的正投影与第一连接线71在显示基板平面上的正投影没有重叠。
在示例性实施例中，第三区域130可以包括多个电路单元，第三区域130的多个电路单元中像素驱动电路在显示基板平面上的正投影与第一连接线71和第二连接线72在显示基板平面上的正投影没有重叠。
在示例性实施例中，图10所示各个区域的划分仅仅是一种示例性说明。由于第一区域110、第二区域120和第三区域130是按照有无数据连接线和数据连接线的延伸方向作为划分依据，因而三个区域的形状可以是规则的多边形，或者是不规则的多边形，显示区域可以划分出一个或多个第一区域110、一个或多个第二区域120以及一个或多个第三区域130，本公开在此不做限定。
在示例性实施例中，在垂直于显示基板的平面内，所述驱动电路层包括在基底上依次设置的第一导电层、第二导电层、第三导电层和第四导电层，所述第三导电层至少包括所述第一连接线，所述第四导电层至少包括所述数据信号线和所述第二连接线，所述数据信号线通过第一连接孔与所述第一连接线的第一端连接，所述第二连接线通过第二连接孔与所述第一连接线的第二端连接。
在示例性实施例中，所述第三导电层还包括多条沿着所述第一方向延伸的第一电源走线，所述第四导电层还包括多条沿着所述第二方向延伸的第二电源走线，所述第二电源走线通过第三连接孔与所述第一电源走线连接。
在示例性实施例中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，多条引出线包括设置在所述第一导电层中的多条第一引出线和设置在所述第二导电层中的多条第二引出线；所述第一引出线与所述显示区域中奇数单元列的数据信号线连接，所述第二引出线与所述显示区域中偶数单元列的数据信号线连接；或者，所述第一引出线与所述显示区域中偶数单元列的数据信号线连接，所述第二引出线与所述显示区域中奇数单元列的数据信号线连接。
在示例性实施例中，所述第一导电层还包括多个第一引线电极，所述第一引线电极与所述第一引出线连接；所述第二导电层还包括多个第二引线电极，所述第二引线电极与所述第二引出线连接；所述第三导电层还包括多个第三引线电极和多个第四引线电极，所述第三引线电极通过过孔与所述第一引线电极连接，所述第四引线电极通过过孔与所述第二引线电极连接；所述显示区域中奇数单元列的数据信号线通过过孔与第三引线电极连接，所述显示区域中偶数单元列的数据信号线通过过孔与第四引线电极连接；或者，所述显示区域中偶数单元列的数据信号线通过过孔与第三引线电极连接，所述显示区域中奇数单元列的数据信号线通过过孔与第四引线电极连接。
在示例性实施例中，驱动电路层还可以至少包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第一平坦层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电 层之间，第一平坦层设置在第三导电层与第四导电层之间。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施例中，显示基板的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图11a和图11b所示，图11a为图10中E0区域的放大图，图11b为图10中F区域的放大图。
在示例性实施例中，显示区域中每个电路单元的半导体层可以至少包括第一晶体管T1的第一有源层11至第七晶体管T7的第七有源层17，且第一有源层11至第三有源层13、第五有源层15至第七有源层17可以为相互连接的一体结构，第四有源层14可以单独设置。
在示例性实施例中，第一有源层11和第二有源层12可以位于本电路单元的第三有源层13第二方向Y的反方向的一侧，第四有源层14、第五有源层15、第六有源层16和第七有源层17可以位于本电路单元的第三有源层13 第二方向Y的一侧。
在示例性实施例中，第一有源层11的形状可以呈“n”字形，第二有源层12和第五有源层15的形状可以呈“L”字形，第三有源层13的形状可以呈“Ω”字形，第四有源层14、第六有源层16和第七有源层17的形状可以呈“I”字形。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源层11的第一区11-1、第四有源层14的第一区14-1、第四有源层14的第二区14-2、第五有源层15的第一区15-1和第七有源层17的第一区17-1可以单独设置，第一有源层11的第二区11-2可以作为第二有源层12的第一区12-1，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2，第三有源层13的第二区13-2可以同时作为第二有源层12的第二区12-2和第六有源层16的第一区16-1，第六有源层16的第二区16-2可以作为第七有源层17的第二区17-2。
在示例性实施例中，第三有源层的第一区可以作为第三晶体管(驱动晶体管)的第一极，第四有源层的第二区可以作为第四晶体管(数据写入晶体管)的第二极，第五有源层的第二区可以作为第五晶体管的第二极，第三晶体管的第一极、第四晶体管的第二极和第五晶体管的第二极相互连接，连接点为像素驱动电路的第一节点N1。
在示例性实施例中，图10中E1区域、E2区域、E3区域和E4区域的半导体图案与E0区域的半导体图案基本上相同，绑定区域中引线区没有设置半导体图案。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图12a和图12b所示，图12a为图10中E0区域的放大图，图12b为图10中F区域的放大图。在示例性实施例中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施例中，显示区域中每个电路单元的第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、发光控 制线24和存储电容的第一极板25。
在示例性实施例中，存储电容的第一极板25的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板25在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影存在重叠区域。在示例性实施例中，第一极板25可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23和发光控制线24的形状可以为主体部分沿着第一方向X延伸的线形状。第一扫描信号线21和第二扫描信号线22可以位于本电路单元的第一极板25第二方向Y的反方向的一侧，第二扫描信号线22可以位于本电路单元的第一扫描信号线21远离第一极板25的一侧，第三扫描信号线23和发光控制线24可以位于本电路单元的第一极板25第二方向Y的一侧，第三扫描信号线23可以位于本电路单元的发光控制线24远离第一极板25的一侧。
在示例性实施例中，第一扫描信号线21可以设置有向第二扫描信号线22一侧凸起的栅极块21-1，第一扫描信号线21和栅极块21-1与第二有源层相重叠的区域可以作为第二晶体管T2的栅电极，形成双栅结构的第二晶体管T2。
在示例性实施例中，第二扫描信号线22与第一有源层相重叠的区域可以作为双栅结构的第一晶体管T1的栅电极。第三扫描信号线23与第四有源层相重叠的区域可以作为第四晶体管T4的栅电极，第三扫描信号线23与第七有源层相重叠的区域可以作为第七晶体管T7的栅电极。发光控制线24与第五有源层相重叠的区域可以作为第五晶体管T5的栅电极，发光控制线24与第六有源层相重叠的区域可以作为第六晶体管T6的栅电极。
在示例性实施例中，第一扫描信号线21和第三扫描信号线23可以连接相同的信号源，即第一扫描信号线21和第三扫描信号线23的输出信号相同。
在示例性实施例中，图10中E1区域、E2区域、E3区域和E4区域的第一导电层图案与E0区域的第一导电层图案基本上相同。
在示例性实施例中，绑定区域中引线区的第一导电层图案可以至少包括多个第一引线电极210。
在示例性实施例中，第一引线电极210的形状可以为沿着第二方向Y延伸的条形状，第一引线电极210被配置为与后续形成的奇数单元列的数据信号线连接。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第七有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：如图13a和图13b所示，图13a为图10中E0区域的放大图，图13b为图10中F区域的放大图。在示例性实施例中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施例中，显示区域中每个电路单元的第二导电层图案至少包括：第一初始信号线31、第二初始信号线32、存储电容的第二极板33、极板连接线34和屏蔽电极35。
在示例性实施例中，第一初始信号线31和第二初始信号线32的形状可以为主体部分可以沿第一方向X延伸的线形状。第一初始信号线31可以位于本电路单元的第一扫描信号线21和第二扫描信号线22之间，第二初始信号线32可以位于本电路单元的第三扫描信号线23远离发光控制线24的一侧。
在示例性实施例中，第二极板33的轮廓形状可以为矩形状，矩形状的角部可以设置倒角，第二极板33在基底上的正投影与第一极板25在基底上的正投影存在重叠区域，第二极板33作为存储电容的另一个极板，位于本电路单元的第一扫描信号线21和发光控制线24之间，第一极板25和第二极板33构成像素驱动电路的存储电容。
在示例性实施例中，极板连接线34可以设置在第二极板33第一方向X或第一方向X的反方向的一侧，极板连接线34的第一端与本电路单元的第 二极板33连接，极板连接线34的第二端沿着第一方向X或者第一方向X的反方向延伸后，与相邻电路单元的第二极板33连接，使一单元行上相邻电路单元的第二极板33相互连接。在示例性实施例中，通过极板连接线可以使一单元行中多个电路单元的第二极板形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号连接线，保证一单元行中的多个第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第二极板33上设置有开口36，开口36可以位于第二极板33的中部，开口36可以为矩形，使第二极板33形成环形结构。开口36暴露出覆盖第一极板25的第三绝缘层，且第一极板25在基底上的正投影包含开口36在基底上的正投影。在示例性实施例中，开口36被配置为容置后续形成的第一过孔，第一过孔位于开口36内并暴露出第一极板25，使后续形成的第一晶体管T1的第二极与第一极板25连接。
在示例性实施例中，第二极板33在基底上的正投影与第一节点N1在基底上的正投影至少部分交叠，由于第二极板33与后续形成的第一信号线连接，因而第二极板33可以有效屏蔽第一节点N1，避免第一节点N1的电位受外界影响，提高显示效果。
在示例性实施例中，屏蔽电极35可以位于第一初始信号线31靠近第一扫描信号线21的一侧，且与第一初始信号线31连接，屏蔽电极35在基底上的正投影与第二有源层的第一区在基底上的正投影至少部分交叠，屏蔽电极35被配置为屏蔽数据电压跳变对关键节点的影响，避免数据电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，图10中E1区域、E2区域、E3区域和E4区域的第二导电层图案与E0区域的第二导电层图案基本上相同。
在示例性实施例中，绑定区域中引线区的第二导电层图案可以至少包括多个第二引线电极220。
在示例性实施例中，第二引线电极220的形状可以为沿着第二方向Y延伸的条形状，第二引线电极220被配置为与后续形成的偶数单元列的数据信号线连接。
在示例性实施例中，第二引线电极220可以设置在第一方向X相邻的第一引线电极210之间，第一引线电极210可以设置在第一方向X相邻的第二引线电极220之间，多个第一引线电极210靠近显示区域的端部和多个第二引线电极220靠近显示区域的端部可以平齐。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，如图14a和图14b所示，图14a为图10中E0区域的放大图，图14b为图10中F区域的放大图。
在示例性实施例中，显示区域中每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11和第十二过孔V12。
在示例性实施例中，第一过孔V1在基底上的正投影位于第二极板33的开口36在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板25的表面，第一过孔V1被配置为使后续形成的第一晶体管T1的第二极与通过该过孔与第一极板25连接。
在示例性实施例中，第二过孔V2在基底上的正投影位于第二极板33在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层被刻蚀掉，暴露出第二极板33的表面，第二过孔V2被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第二极板33连接。
在示例性实施例中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层的第一区连接。
在示例性实施例中，第四过孔V4在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有 源层的第二区的表面，第四过孔V4被配置为使后续形成的第六晶体管T6的第二极(也是第七晶体管T7的第二极)通过该过孔与第六有源层连接。
在示例性实施例中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的第四晶体管T4的第一极通过该过孔与第四有源层的第一区连接。
在示例性实施例中，第六过孔V6在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第六过孔V6被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第七有源层的第一区连接。
在示例性实施例中，第七过孔V7在基底上的正投影位于第三有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第一区的表面，第七过孔V7被配置为使后续形成的第三晶体管T3的第一极通过该过孔与第三有源层的第一区连接。
在示例性实施例中，第八过孔V8在基底上的正投影位于第四有源层的第二区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第八过孔V8被配置为使后续形成的第三晶体管T3的第一极通过该过孔与第四有源层的第二区连接。
在示例性实施例中，第九过孔V9在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第九过孔V9被配置为使后续形成的第一晶体管T1的第二极(也是第二晶体管T2的第一极)通过该过孔与第一有源层连接。
在示例性实施例中，第十过孔V10在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层、第三 绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第十过孔V10被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层的第一区连接。
在示例性实施例中，第十一过孔V11在基底上的正投影位于第一初始信号线31在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出第一初始信号线31的表面，第十一过孔V11被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一初始信号线31连接。
在示例性实施例中，第十二过孔V12在基底上的正投影位于第二初始信号线32在基底上的正投影的范围之内，第十二过孔V12内的第四绝缘层被刻蚀掉，暴露出第二初始信号线32的表面，第十二过孔V12被配置为使后续形成的第七晶体管T7的第一极通过该过孔与第二初始信号线32连接。
在示例性实施例中，图10中E1区域、E2区域、E3区域和E4区域的多个过孔图案与E0区域的多个过孔图案基本上相同。
在示例性实施例中，绑定区域中引线区的多个过孔至少包括：第十三过孔V13和第十四过孔V14。
在示例性实施例中，第十三过孔V13在基底上的正投影位于第一引线电极210在基底上的正投影的范围之内，第十三过孔V13内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一引线电极210的表面，第十三过孔V13被配置为使后续形成的第三引线电极通过该过孔与第一引线电极210连接。
在示例性实施例中，第十四过孔V14在基底上的正投影位于第二引线电极220在基底上的正投影的范围之内，第十四过孔V14内的第四绝缘层被刻蚀掉，暴露出第二引线电极220的表面，第十四过孔V14被配置为使后续形成的第四引线电极通过该过孔与第二引线电极220连接。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图15a至图15f所示，图15a为图10中E0区域的放大图，图15b为图10中E1区域的放大图，图15c为图10中E2区域的放大图，图15d为图10中E3区域的放大图，图15e为图10中E4区域的放大图，图15f为图10中F区域的放大 图。在示例性实施例中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施例中，显示区域中多个电路单元的第三导电层图案均包括：第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45、第六连接电极46和第七连接电极47。
在示例性实施例中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的条形状，第一连接电极41的第一端通过第一过孔V1与第一极板25连接，第一连接电极41的第二端通过第九过孔V9与第一有源层的第二区(也是第二有源层的第一区)连接。在示例性实施例中，第一连接电极41可以作为第一晶体管T1的第二极和第二晶体管T2的第一极，使第一极板25、第一晶体管T1的第二极和第二晶体管T2的第一极具有相同的电位(第二节点N2)。
在示例性实施例中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的条形状，第二连接电极42的第一端通过第二过孔V2与第二极板33连接，第二连接电极42的第二端通过第三过孔V3与第五有源层的第一区连接。在示例性实施例中，第二连接电极42可以作为第五晶体管T5的第一极，使第二极板33和第五晶体管T5的第一极具有相同的电位，第二连接电极42被配置为与后续形成的第一电源线连接。
在示例性实施例中，第三连接电极43的形状可以为主体部分沿着第二方向Y延伸的条形状，第三连接电极43的第一端通过第七过孔V7与第三有源层的第一区连接，第三连接电极43的第二端通过第八过孔V8与第四有源层的第二区连接。在示例性实施例中，第三连接电极43可以作为第三晶体管T3的第一极(也是第四晶体管T4的第二极)，使第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极具有相同的电位(第一节点N1)。
在示例性实施例中，第四连接电极44的形状可以为矩形状，第四连接电极44通过第五过孔V5与第四有源层的第一区连接。第四连接电极44可以作为第四晶体管T4的第一极，第四连接电极44被配置为与后续形成的数据信号线连接。
在示例性实施例中，第五连接电极45的形状可以为矩形状，第五连接电 极45通过第四过孔V4与第六有源层的第二区(也是第七有源层的第二区)连接。第五连接电极45可以作为第六晶体管T6的第二极(也是第七晶体管T7的第二极)，第五连接电极45被配置为与后续形成的阳极连接电极连接。
在示例性实施例中，第六连接电极46的形状可以为矩形状，第六连接电极46的第一端通过第十过孔V10与第一有源层的第一区连接，第六连接电极46的第二端通过第十一过孔V11与第一初始信号线31连接。第六连接电极46可以作为第一晶体管T1的第一极，因而实现了第一初始信号线31将第一初始信号写入第一晶体管T1的第一极。
在示例性实施例中，第七连接电极47的形状可以为矩形状，第七连接电极47的第一端通过第六过孔V6与第七有源层的第一区连接，第七连接电极47的第二端通过第十二过孔V12与第二初始信号线32连接。第七连接电极47可以作为第七晶体管T7的第一极，因而实现了第二初始信号线32将第二初始信号写入第七晶体管T7的第一极。
如图15a所示，在示例性实施例中，第三区域中多个电路单元的第三导电层图案还可以包括第一电源走线91、电源连接电极85和电源连接块86。
在示例性实施例中，第一电源走线91的形状可以为主体部分沿着第一方向X延伸的线形状，可以设置在第二扫描信号线22远离第一扫描信号线21的一侧。在示例性实施例中，第一电源走线91可以与边框区域的边框电源引线连接，被配置为传输低电压信号(VSS)。
在示例性实施例中，电源连接电极85的形状可以为矩形状，可以设置在第一电源走线91靠近第一扫描信号线21的一侧。在示例性实施例中，电源连接电极85被配置为与后续形成的第二电源走线连接。
在示例性实施例中，电源连接块86设置在第一电源走线91和电源连接电极85之间，电源连接块86的第一端与第一电源走线91连接，电源连接块86的第二端与电源连接电极85连接，因而实现了第一电源走线91和电源连接电极85的连接。
在示例性实施例中，第三区域中一个电路行的第一电源走线91、电源连接电极85和电源连接块86可以为相互连接的一体结构。
如图15b所示，在示例性实施例中，第一区域中多个电路单元的第三导电层图案还可以包括第一连接线71和虚设电极87。
在示例性实施例中，数据连接线的第一连接线71的形状可以为主体部分沿着第一方向X延伸的线形状，可以设置在第二扫描信号线22远离第一扫描信号线21的一侧。在示例性实施例中，第一连接线71被配置为与后续形成的数据连接线的第二连接线连接。
在示例性实施例中，第一区域中多个电路单元的虚设电极87的位置和形状可以第三区域中的电源连接电极85的位置和形状基本上相同，所不同的是，虚设电极87为隔离设置，既不与第一连接线71连接，也不与其它电极连接。在示例性实施例中，虚设电极87呈现出的形貌和结构与电源连接电极和数据连接电极相同，不仅可以提高制备工艺的均一性，而且使得不同区域具有基本上相同的转接连接结构，不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效避免了显示基板的外观不良，提高了显示品质和显示质量。
如图15c所示，在示例性实施例中，第二区域中多个电路单元的第三导电层图案还包括第一电源走线91和虚设电极87。
在示例性实施例中，第二区域中多个电路单元的第一电源走线91的位置和形状可以与第三区域中的第一电源走线91的位置和形状基本上相同，第二区域中多个电路单元的虚设电极87的位置、形状和作用可以与第一区域中的电源连接电极85的位置、形状和作用基本上相同。
如图15d所示，在示例性实施例中，第一区域和第三区域交界区域的至少一个电路单元的第三导电层图案还可以包括第一连接线71、数据连接电极81和数据连接块82。
在示例性实施例中，第一区域和第三区域两者交界区域可以包括第一区域的至少一个电路单元、第三区域的至少一个电路单元和第一连接单元，第一连接单元可以是数据信号线与第一连接线通过第一连接孔实现连接的电路单元。
在示例性实施例中，第一连接单元可以包括第一连接线71、数据连接电极81和数据连接块82。第一区域的电路单元可以包括第一连接线71和虚设 电极87，位于第一连接单元的右侧。第三区域的电路单元可以包括第一电源走线91和虚设电极87，位于第一连接单元的左侧。
在示例性实施例中，数据连接电极81的形状可以为矩形状，可以设置在第一连接线71远离虚设电极87的一侧。数据连接块82的形状可以为矩形状，可以设置在第一连接线71和数据连接电极81之间，数据连接块82的第一端与第一连接线71连接，数据连接块82的第二端与数据连接块82连接，因而实现了第一连接线71和数据连接电极81的连接。在示例性实施例中，数据连接电极81被配置为与后续形成的数据信号线连接。
在示例性实施例中，数据连接电极81可以与像素驱动电路中的第四连接电极44连接。
在示例性实施例中，像素驱动电路中的第四连接电极44可以作为数据连接电极81，即数据连接电极81和第四连接电极44(第四晶体管的第一极)为共用结构。
在示例性实施例中，与第一连接单元邻近的第三区域的至少一个电路单元可以设置有至少一个第一断口DF1，第一断口DF1将同一电路行中的第一连接线71和第一电源走线91截断，第一断口DF1第一方向X一侧为第一连接线71，第一断口DF1第一方向X的反方向一侧为第一电源走线91。
如图15e所示，在示例性实施例中，第一区域和第二区域交界区域的至少一个电路单元的第三导电层图案还可以包括第一连接线71、扇出连接电极83和扇出连接块84。
在示例性实施例中，第一区域和第二区域两者交界区域可以包括第一区域的至少一个电路单元、第二区域的至少一个电路单元和第二连接单元，第二连接单元可以是第一连接线与第二连接线通过第二连接孔实现连接的电路单元。
在示例性实施例中，第二连接单元可以包括第一连接线71、扇出连接电极83和扇出连接块84。第一区域的电路单元可以包括第一连接线71和虚设电极87，位于第一连接单元的左侧。第二区域的电路单元可以包括第一电源走线91和虚设电极87，位于第二连接单元的下侧。
在示例性实施例中，扇出连接电极83的形状可以为矩形状，可以设置在第一连接线71靠近远离第二初始信号线32的一侧。扇出连接块84的形状可以为矩形状，可以设置在第一连接线71和扇出连接电极83之间，扇出连接块84的第一端与第一连接线71连接，扇出连接块84的第二端与扇出连接电极83连接，因而实现了第一连接线71和扇出连接电极83的连接。在示例性实施例中，扇出连接电极83被配置为与后续形成的第二连接线连接。
在示例性实施例中，与第二连接单元邻近的第一区域的至少一个电路单元可以设置有至少一个第一断口DF1，第一断口DF1将同一电路行中的第一连接线71和第一电源走线91截断，第一断口DF1第一方向X一侧为第一连接线71，第一断口DF1第一方向X的反方向一侧为第一电源走线91。
如图15f所示，在示例性实施例中，绑定区域中引线区的第三导电层图案至少包括：多个第三引线电极230、多个第四引线电极240、绑定高压线250和多个绑定高压电极260。
在示例性实施例中，第三引线电极230的形状可以为沿着第二方向Y延伸的条形状，多个第三引线电极230的位置可以与多个第一引线电极210的位置相对应，第三引线电极230在基底上的正投影与第一引线电极210在基底上的正投影至少部分交叠，第三引线电极230通过第十三过孔V13与第一引线电极210连接。在示例性实施例中，多个第三引线电极230被配置为与后续形成的奇数单元列的数据信号线对应连接。
在示例性实施例中，第四引线电极240的形状可以为沿着第二方向Y延伸的条形状，多个第四引线电极240的位置可以与多个第二引线电极220的位置相对应，第四引线电极240在基底上的正投影与第二引线电极220在基底上的正投影至少部分交叠，第四引线电极240通过第十四过孔V14与第二引线电极220连接。在示例性实施例中，多个第四引线电极240被配置为与后续形成的偶数单元列的数据信号线对应连接。
在示例性实施例中，绑定高压线250的形状可以为沿着第一方向X延伸的条形状，绑定高压线250被配置为向显示区域的多条第一电源线持续提供的高电平信号。
在示例性实施例中，绑定高压电极260的形状可以为沿着第二方向Y延 伸的条形状，多个绑定高压电极260可以沿着第一方向X依次设置，多个绑定高压电极260的第一端与绑定高压线250连接，多个绑定高压电极260的第二端向着显示区域的方向延伸。在示例性实施例中，多个绑定高压电极260被配置为与后续形成的多条第一电源线对应连接。
(6)形成第一平坦层图案。在示例性实施例中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，第一平坦层上设置有多个过孔，如图16a至图16f所示，图16a为图10中E0区的放大图，图16b为图10中E1区域域的放大图，图16c为图10中E2区域的放大图，图16d为图10中E3区域的放大图，图16e为图10中E4区域的放大图，图16f为图10中F区域的放大图。
在示例性实施例中，显示区域中多个电路单元的多个过孔均包括：第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施例中，第二十一过孔V21在基底上的正投影位于第二连接电极42在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层被去掉，暴露出第二连接电极42的表面，第二十一过孔V21被配置为使后续形成的第一电源线通过该过孔与第二连接电极42连接。
在示例性实施例中，第二十二过孔V22在基底上的正投影位于第四连接电极44在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层被去掉，暴露出第四连接电极44的表面，第二十二过孔V22被配置为使后续形成的数据信号线通过该过孔与第四连接电极44连接。
在示例性实施例中，第二十三过孔V23在基底上的正投影位于第五连接电极45在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层被去掉，暴露出第五连接电极45的表面，第二十三过孔V23被配置为使后续形成的阳极连接电极通过该过孔与第五连接电极45连接。
如图16a所示，在示例性实施例中，第三区域中多个电路单元还包括第二十四过孔V24。
在示例性实施例中，第二十四过孔V24在基底上的正投影位于电源连接电极85在基底上的正投影的范围之内，第二十四过孔V24内的第一平坦层 被去掉，暴露出电源连接电极85的表面，第二十四过孔V24被配置为使后续形成的第二电源走线通过该过孔与电源连接电极85连接。在示例性实施例中，第二十四过孔V24可以称为第三连接孔。
如图16b和图16c所示，在示例性实施例中，第一区域中多个电路单元和第二区域中多个电路单元还包括第二十五过孔V25。
在示例性实施例中，第二十五过孔V25在基底上的正投影位于虚设电极87在基底上的正投影的范围之内，第二十五过孔V25内的第一平坦层被去掉，暴露出虚设电极87的表面，第二十五过孔V25被配置为使后续形成的第二电源走线通过该过孔与虚设电极87连接。
如图16d所示，在示例性实施例中，第一区域和第三区域交界区域的至少一个电路单元还包括第二十六过孔V26。
在示例性实施例中，第二十六过孔V26在基底上的正投影位于数据连接电极81在基底上的正投影的范围之内，第二十六过孔V26内的第一平坦层被去掉，暴露出数据连接电极81的表面，第二十六过孔V26被配置为使后续形成的数据信号线通过该过孔与数据连接电极81
在示例性实施例中，第二十六过孔V26和第二十二过孔V22可以为同一个孔的共用结构。在示例性实施例中，第二十六过孔V26可以称为第一连接孔。
如图16e所示，在示例性实施例中，第一区域和第二区域交界区域的至少一个电路单元还包括第二十七过孔V27。
在示例性实施例中，第二十七过孔V27在基底上的正投影位于扇出连接电极83在基底上的正投影的范围之内，第二十七过孔V27内的第一平坦层被去掉，暴露出扇出连接电极83的表面，第二十七过孔V27被配置为使后续形成的第二连接线通过该过孔与扇出连接电极83连接。在示例性实施例中，第二十七过孔V27可以称为第二连接孔。
在示例性实施例中，第二十六过孔V26可以位于第一连接线71第二方向Y的反方向的一侧，第二十七过孔V27可以位于第一连接线71第二方向Y的一侧，即连接同一条第一连接线71的第一连接孔(第二十六过孔V26) 和第二连接孔(第二十七过孔V27)，分别设置在该第一连接线71第二方向Y的两侧。
如图16f所示，在示例性实施例中，绑定区域中引线区的多个过孔至少包括：第三十一过孔V31、第三十二过孔V32和第三十三过孔V33。
在示例性实施例中，第三十一过孔V31在基底上的正投影位于第三引线电极230在基底上的正投影的范围之内，第三十一过孔V31内的第一平坦层被去掉，暴露出第三引线电极230的表面，第三十一过孔V31被配置为使后续形成的显示区域中奇数列的数据信号线通过该过孔与第三引线电极230连接。
在示例性实施例中，第三十二过孔V32在基底上的正投影位于第四引线电极240在基底上的正投影的范围之内，第三十二过孔V32内的第一平坦层被去掉，暴露出第四引线电极240的表面，第三十二过孔V32被配置为使后续形成的显示区域中偶数列的数据信号线通过该过孔与第四引线电极240连接。
在示例性实施例中，第三十三过孔V33在基底上的正投影位于绑定高压电极260在基底上的正投影的范围之内，第三十三过孔V33内的第一平坦层被去掉，暴露出绑定高压电极260的表面，第三十三过孔V33被配置为使后续形成的显示区域中第一电源线通过该过孔与绑定高压电极260连接。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图17a至图17f所示，图17a为图10中E0区域的放大图，图17b为图10中E1区域的放大图，图17c为图10中E2区域的放大图，图17d为图10中E3区域的放大图，图17e为图10中E4区域的放大图，图17f为图10中F区域的放大图。在示例性实施例中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施例中，显示区域中多个电路单元的第四导电层图案均包括：第一电源线51、阳极连接电极52和数据信号线60。
在示例性实施例中，第一电源线51的形状可以为主体部分沿着第二方向Y延伸的折线状，一方面，第一电源线51通过显示区域的第二十一过孔V21 与第二连接电极42连接连接，另一方面，第一电源线51延伸到引线区后，通过引线区的第三十三过孔V33与绑定高压电极260连接。由于第二连接电极42通过过孔分别与第二极板和第五有源层的第一区连接，因而实现了第一电源线51将电源信号写入第五晶体管T5的第一极，且存储电容的第二极板与第一电源线51具有相同的电位。由于绑定高压电极260与绑定高压线250连接，因而实现了绑定高压线250通过绑定高压电极260向第一电源线51提供高电平信号。
在示例性实施例中，第一电源线51在基底上的正投影与第一连接电极41在基底上的正投影至少部分交叠，第一电源线51可以有效屏蔽了数据电压跳变对像素驱动电路中第二节点N2的影响，避免了数据电压跳变影响第二节点N2的电位，提高了显示效果。
在示例性实施例中，第一电源线51在基底上的正投影与第二连接电极42在基底上的正投影至少部分交叠。
在示例性实施例中，第一电源线51可以为非等宽度设计，采用非等宽度设计的第一电源线51不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施例中，数据信号线60的形状可以为主体部分沿着第二方向Y延伸的直线状，一方面，数据信号线60通过显示区域的第二十二过孔V22与第四连接电极44连接，另一方面，数据信号线60延伸到引线区后，奇数单元列的数据信号线60通过第三十一过孔V31与第三引线电极230连接，偶数单元列的数据信号线60通过第三十二过孔V32与第四引线电极240连接。由于第四连接电极44通过过孔与第四有源层的第一区连接，因而实现了数据信号线60将数据信号写入第四晶体管T4的第一极。
在示例性实施例中，由于第三引线电极230通过过孔与第一引线电极210连接，第一引线电极210与第一引出线连接，因而实现了奇数单元列的数据信号线60与位于第一导电层(GATE1)的第一引出线的连接。由于第四引线电极240通过过孔与第二引线电极220连接，第二引线电极220与第二引出线连接，因而实现了偶数单元列的数据信号线60与位于第二导电层(GATE2)的第二引出线的连接。
在示例性实施例中，在与显示区域中第三区域对应位置的引线区中，多条引出线可以包括设置在第一导电层(GATE1)的多条第一引出线和设置在第二导电层(GATE2)的多条第二引出线，多条第一引出线可以通过第一引线电极210和第三引线电极230与奇数单元列的数据信号线60对应连接，多条第二引出线可以通过第二引线电极220和第四引线电极240与偶数单元列的数据信号线60对应连接。本公开通过将多条引出线设置在两个导电层中，可以在避免短路的前提下增加引出线宽度，提高数据传输的可靠性。
在示例性实施例中，多条第一引出线可以与偶数单元列的数据信号线对应连接，多条第二引出线可以与奇数单元列的数据信号线对应连接，本公开在此不做限定。
在示例性实施例中，阳极连接电极52的形状可以为矩形状，阳极连接电极52通过第二十三过孔V23与第五连接电极45连接。在示例性实施例中，阳极连接电极52被配置为与后续形成的阳极连接，由于第五连接电极45通过过孔与第六有源层的第二区连接，因而实现了阳极通过阳极连接电极52和第五连接电极45与第六晶体管T6的第二极连接。
如图17a所示，在示例性实施例中，第三区域的多个电路单元的第四导电层图案还可以包括第二电源走线92。
在示例性实施例中，第二电源走线92的形状可以为主体部分沿着第二方向Y延伸的直线状，第二电源走线92通过第二十四过孔V24与电源连接电极85连接。由于电源连接电极85通过电源连接块86与第一电源走线91连接，因而实现了第二电源走线92与第一电源走线91的相互连接，使得沿着第一方向X延伸的第一电源走线91和沿着第二方向Y延伸的第二电源走线92构成网状连通结构。本公开通过设置网状连通结构的电源走线，多个单元行和多个单元列中的电源走线具有相同的电位，不仅有效降低了电源走线的电阻，减小了传输低电压信号的电压压降，而且有效提升了显示基板中低电压信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
如图17b所示，在示例性实施例中，第一区域中多个电路单元的第四导电层图案还可以包括第二电源走线92。
在示例性实施例中，第二电源走线92通过第二十五过孔V25与虚设电 极87连接。
在示例性实施例中，由于虚设电极87的位置和形状与电源连接电极和数据连接电极的位置和形状基本上相同，因而第一区域中多个电路单元的第二电源走线92与虚设电极87的孔连接结构与其它区域电路单元的孔连接结构基本上相同，不仅可以提高制备工艺的均一性，而且可以实现不同区域在透射及反射光下均能达到相同的显示效果，提高了显示画面的均一性。
如图17c所示，在示例性实施例中，第二区域中至少一个电路单元的第四导电层图案还可以包括第二连接线72，其它电路单元可以包括第二电源走线92。
在示例性实施例中，第二连接线72的形状可以为主体部分沿着第二方向Y延伸的直线状，第二连接线72通过第二十五过孔V25与虚设电极87连接。
在示例性实施例中，第二电源走线92通过第二十五过孔V25与虚设电极87连接。
如图17d所示，在示例性实施例中，第一区域和第三区域交界区域的至少一个电路单元的数据信号线60通过第二十六过孔V26与数据连接电极81连接。由于数据连接电极81通过数据连接块与第一连接线71连接，因而实现了数据信号线60与第一连接线71的连接。
在示例性实施例中，第一区域和第三区域交界区域的其它电路单元的第二电源走线92通过第二十五过孔V25与虚设电极87连接。
在示例性实施例中，位于第一连接线71和第一电源走线91之间的第一断口DF1在基底上的正投影与第二电源走线92在基底上的正投影至少部分交叠。
在示例性实施例中，第一断口DF1在基底上的正投影可以位于第二电源走线92在基底上的正投影的范围之内。
如图17e所示，在示例性实施例中，第一区域和第二区域交界区域的第二连接单元的第四导电层图案还可以包括第二连接线72。
在示例性实施例中，第二连接线72的形状可以为主体部分沿着第二方向Y延伸的直线状，第二连接线72通过第二十七过孔V27与扇出连接电极83 连接。由于扇出连接电极83通过扇出连接块84与第一连接线71连接，因而实现了第二连接线72与第一连接线71的相互连接。由于第一连接线71与数据信号线连接，因而实现了数据信号线60通过第一连接线71与第二连接线72的连接。
在示例性实施例中，第一区域和第二区域交界区域的其它电路单元的第二电源走线92通过第二十五过孔V25与虚设电极87连接。
在示例性实施例中，与第二连接单元邻近的第一区域的至少一个电路单元可以设置有至少一个第二断口DF2，第二断口DF2将同一电路列中的第二连接线72和第二电源走线92截断，第二断口DF2第二方向Y一侧为第二连接线72，第二断口DF2第二方向Y的反方向的一侧为第二电源走线92。
在示例性实施例中，第二断口DF2在基底上的正投影与第一连接线71在基底上的正投影至少部分交叠。
在示例性实施例中，第二断口DF2在基底上的正投影可以位于第一连接线71在基底上的正投影的范围之内。
如图17f所示，在示例性实施例中，绑定区域中引线区的第四导电层图案至少包括绑定电源引线410。
在示例性实施例中，绑定电源引线410的形状可以为沿着第一方向X延伸的条形状，绑定电源引线410分别与显示区域的多条第二电源走线92连接。在示例性实施例中，绑定电源引线410被配置为向显示区域的多条第二电源走线92持续提供的低电平信号。
在示例性实施例中，绑定电源引线410上可以设置有多个引线开口420，引线开口420内的第四导电薄膜被去掉，暴露出第一平坦层。在示例性实施例中，多个引线开口420被配置为释放第一平坦层中的水汽。
在示例性实施例中，引线区的绑定高压线250和绑定电源引线410可以跨过弯折区和驱动芯片区后，与绑定引脚区的绑定焊盘连接，外部控制装置通过柔性线路板和绑定焊盘向绑定高压线250和绑定电源引线410分别提供高压信号和低压信号。
在示例性实施例中，显示区域中的多条第一电源走线可以与边框区域的 边框电源引线连接，第一电源走线和电源引线边框之间的连接结构与前述的第二电源走线和绑定电源引线之间的连接结构基本上相同，这里不再赘述。
图18a为本公开显示基板引线区形成第一导电层图案后的示意图。由于前述图12b所示的引线区为与显示区域中第三区域对应位置的引线区，因而在该引线区的第一导电层图案中，只有连接奇数单元列的数据信号线的第一引线电极210。如图18a所示，对于与显示区域中第二区域对应位置的引线区，由于后续形成有第二连接线，因而该引线区的第一导电层图案还可以包括第十一引线电极310，第十一引线电极310被配置为通过第十三引线电极与后续形成的第二连接线连接。
在示例性实施例中，与显示区域中第二区域对应位置的引线区，不仅包括多个第一引线电极210，还包括多个第十一引线电极310，在第一导电层中，与显示区域中第二区域对应位置的引线区中引线电极的数量与显示区域中第三区域对应位置的引线区中引线电极的数量不同。
在示例性实施例中，第十一引线电极310和第一引线电极210的结构可以基本上相同。
在示例性实施例中，绑定区域的第一导电层图案还可以包括多条第一引出线(未示出)，第一引出线的形状可以为直线状或者折线状，多条第一引出线的第一端与第一引线电极210和第十一引线电极310连接，多条第一引出线的第二端沿着远离显示区域的方向延伸到绑定区域的弯折区。
图18b为本公开显示基板引线区形成第二导电层图案后的示意图。由于前述图13b所示的引线区为与显示区域中第三区域对应位置的引线区，因而在该引线区的第二导电层图案中，只有连接偶数单元列的数据信号线的第二引线电极220。如图18b所示，对于与显示区域中第二区域对应位置的引线区，由于后续形成有第二连接线，因而该引线区的第二导电层图案还可以包括第十二引线电极320，第十二引线电极320被配置为通过第十四引线电极与后续形成的第二连接线连接。
在示例性实施例中，与显示区域中第二区域对应位置的引线区，不仅包括多个第二引线电极220，还包括多个第十二引线电极320，在第二导电层中，与显示区域中第二区域对应位置的引线区中引线电极的数量与显示区域中第 三区域对应位置的引线区中引线电极的数量不同。
在示例性实施例中，第十二引线电极320和第二引线电极220的结构可以基本上相同。
在示例性实施例中，绑定区域的第二导电层图案还可以包括多条第二引出线(未示出)，第二引出线的形状可以为直线状或者折线状，多条第二引出线的第一端与第二引线电极220和第十二引线电极320连接，多条第二引出线的第二端沿着远离显示区域的方向延伸到绑定区域的弯折区。
图18c为本公开显示基板引线区形成第四绝缘层图案后的示意图。由于前述图14b所示的引线区为与显示区域中第三区域对应位置的引线区，因而该引线区的第四绝缘层图案中，只有第十三过孔V13和第十四过孔V14。如图18c所示，对于与显示区域中第二区域对应位置的引线区，由于引线区设置有第十一引线电极310和第十二引线电极320，因而该引线区的第四绝缘层图案还包括第十五过孔V15和第十六过孔V16。第十五过孔V15暴露出第十一引线电极310的表面，第十五过孔被配置为使后续形成的第十三引线电极330通过该过孔与第十一引线电极310连接。第十六过孔V16暴露出第十二引线电极320的表面，第十二引线电极320被配置为使后续形成的第十四引线电极340通过该过孔与第十二引线电极320连接。
图18d为本公开显示基板引线区形成第三导电层图案后的示意图。由于前述图15f所示的引线区为与显示区域中第三区域对应位置的引线区，因而在该引线区的第三导电层图案中，只有第三引线电极230和第四引线电极240。如图18d所示，对于与显示区域中第二区域对应位置的引线区，由于引线区设置有第十一引线电极310和第十二引线电极320，因而该引线区的第二导电层图案还可以包括第十三引线电极330和第十四引线电极340。第十三引线电极330通过第十五过孔与第十一引线电极310连接，第十三引线电极330被配置为与后续形成的第二连接线连接。第十四引线电极340通过第十六过孔与第十二引线电极320连接，第十四引线电极340被配置为与后续形成的第二连接线连接。
在示例性实施例中，与显示区域中第二区域对应位置的引线区中，在第一方向X相邻的绑定高压电极260之间可以设置有2个引线电极，而在与显 示区域中第三区域对应位置的引线区中，在第一方向X相邻的绑定高压电极260之间仅设置有1个引线电极，因而两个区域引线电极的数量不同。
在示例性实施例中，第十三引线电极330和第十四引线电极340的结构与第三引线电极230和第四引线电极240的结构可以基本上相同。
图18e为本公开显示基板引线区形成第一平坦层图案后的示意图。由于前述图16f所示的引线区为与显示区域中第三区域对应位置的引线区，因而该引线区的第一平坦层图案中，只有第三十一过孔V31和第三十二过孔V32。如图18e所示，对于与显示区域中第二区域对应位置的引线区，由于引线区设置有第十三引线电极330和第十四引线电极340，因而该引线区的第一平坦层图案还可以包括第四十一过孔V41和第四十二过孔V42。第四十一过孔V41暴露出第十三引线电极330的表面，第四十一过孔V41被配置为使后续形成的第二连接线通过该过孔与第十三引线电极330连接。第四十二过孔V42暴露出第十四引线电极340，第四十二过孔V42被配置为使后续形成的第二连接线通过该过孔与第十三引线电极330连接。
图18f为本公开显示基板引线区形成第四导电层图案后的示意图。由于前述图17f所示的引线区为与显示区域中第三区域对应位置的引线区，因而在该引线区的第四导电层图案中，只有数据信号线60分别与第三引线电极230和第四引线电极240连接。如图18f所示，对于与显示区域中第二区域对应位置的引线区，该引线区设置有多条第二连接线72。一方面，一部分第二连接线72延伸到引线区后，通过第四十一过孔V41与第十三引线电极330连接，另一部分第二连接线72延伸到引线区后，通过第四十二过孔V42与第十三引线电极330连接。
在示例性实施例中，第二连接线和引线电极之间的连接结构与数据信号线和引线电极之间的连接结构基本上相同，这里不再赘述。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、发光控制线、数据信号线、第一电源线、第一初始信号线和第二初始信号线。在垂直于显示基板的平面内，驱动电路层可以至少包括在基底上依次 叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层。
在示例性实施例中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施例中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层。第一平坦层可以采用有机材料，如树脂等。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施例中，制备完成驱动电路层后，可以在驱动电路层上依次制备发光结构层和封装结构层，在此不再赘述。
从以上描述的显示基板的结构以及制备过程可以看出，本公开通过在显示区域内设置数据连接线，使得绑定区域的引出线通过数据连接线与数据信号线连接，使得引线区中不需要设置扇形状的斜线，有效减小了引线区的长 度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。本公开通过在显示区域内设置电源走线，实现了VSS in pixel的结构，可以大幅度减小边框电源引线的宽度，大大缩减了左右边框宽度，提高了屏占比，有利于实现全面屏显示。本公开通过将数据连接线设置在奇数单元列或者偶数单元列中，不仅可以方便数据连接线的布局，而且可以减少数据信号的负载，提高显示品质。本公开通过将电源走线设置成网状连通结构，不仅可以有效降低电源走线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可以有效提升显示基板中电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开通过在显示区域内设置虚设电极，使得不同区域具有基本上相同的转接连接结构，不同区域在透射光及反射光下均能达到基本上相同的显示效果，有效避免了显示基板的外观不良，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施例中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施例中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施例中，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括构成多个单元行和多个单元列的多个电路单元、多条沿着第二方向延伸数据信号线和多条数据连接线，所述数据连接线包括沿着第一方向延伸的第一连接线和沿着第二方向延伸的第二连接线，所述第一连接线和所述第二连接线连接，所述第一方向和所述第二方向交叉；所述制备方法可以包括：
在至少一个电路单元中形成所述数据信号线和第一连接线，所述第一连接线通过第一连接孔与所述数据信号线连接，在所述第一方向上相邻的两个 第一连接孔之间，设置有至少一条数据信号线。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (27)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括构成多个单元行和多个单元列的多个电路单元、多条数据信号线和多条数据连接线，所述数据连接线包括沿着第一方向延伸的第一连接线和沿着第二方向延伸的第二连接线，所述第一连接线和所述第二连接线连接，所述第一方向和所述第二方向交叉；至少一个电路单元中，所述数据信号线通过第一连接孔与所述第一连接线连接，在所述第一方向上相邻的两个第一连接孔之间，设置有至少一条数据信号线。
  2. 根据权利要求1所述的显示基板，其中，所述第一连接孔设置在奇数单元列的电路单元中，在所述第一方向上相邻的两个第一连接孔之间，设置有m条数据信号线，m为大于或等于1的奇数。
  3. 根据权利要求1所述的显示基板，其中，所述第一连接孔设置在偶数单元列的电路单元中，在所述第一方向上相邻的两个第一连接孔之间，设置有m条数据信号线，m为大于或等于1的奇数。
  4. 根据权利要求1所述的显示基板，其中，所述第一连接孔设置在奇数单元列的电路单元中，与所述第一连接孔在所述第一方向上相邻的另一个第一连接孔设置在偶数单元列的电路单元中；在所述第一方向上相邻的两个第一连接孔之间，设置有2条数据信号线。
  5. 根据权利要求1所述的显示基板，其中，至少一条第二连接线设置在所述第一方向上相邻的两条数据信号线之间。
  6. 根据权利要求1所述的显示基板，其中，所述第二连接线通过第二连接孔与所述第一连接线连接，连接同一条第一连接线的第一连接孔和第二连接孔，分别设置在所述第一连接线所述第二方向的两侧。
  7. 根据权利要求1所述的显示基板，其中，所述电路单元至少包括像素驱动电路，所述数据信号线与一个单元列中多个电路单元的像素驱动电路连接；所述多个单元列至少包括第一单元列和第二单元列，所述第一单元列中多个电路单元的像素驱动电路分别与出射红色光线的红色发光器件和出射蓝色光线的蓝色发光器件连接，所述第二单元列中多个电路单元的像素驱动 电路与出射绿色光线的绿色发光器件连接，所述第一连接线与所述第一单元列的数据信号线连接，所述第一连接线与所述第二单元列的数据信号线不连接。
  8. 根据权利要求1所述的显示基板，其中，所述显示区域还包括多条沿着所述第一方向延伸的第一电源走线和多条沿着所述第二方向延伸的第二电源走线，所述第二电源走线通过第三连接孔与所述第一电源走线连接。
  9. 根据权利要求8所述的显示基板，其中，所述第二电源走线设置在所述第一方向上相邻的两条数据信号线之间。
  10. 根据权利要求8所述的显示基板，其中，所述绑定区域设置有绑定电源引线，所述绑定电源引线与所述显示区域的多条第二电源走线连接。
  11. 根据权利要求8所述的显示基板，其中，所述显示基板还包括位于所述显示区域其它侧的边框区域，所述边框区域设置有边框电源引线，所述边框电源引线与所述显示区域的多条第一电源走线连接。
  12. 根据权利要求8所述的显示基板，其中，所述第一电源走线和所述第一连接线同层设置，至少一个电路单元包括第一断口，所述第一断口设置在所述第一连接线和所述第一电源走线之间，所述第一断口在显示基板平面上的正投影与所述第二电源走线在显示基板平面上的正投影至少部分交叠。
  13. 根据权利要求12所述的显示基板，其中，所述第二电源走线和所述第二连接线同层设置，至少一个电路单元包括第二断口，所述第二断口设置在所述第二连接线和所述第二电源走线之间，所述第二断口在显示基板平面上的正投影与所述第一连接线在显示基板平面上的正投影至少部分交叠。
  14. 根据权利要求1所述的显示基板，其中，所述绑定区域至少包括引线区，所述引线区包括多条引出线，所述多条引出线包括第一引出线组和第二引出线组，第一引出线组中的引出线通过所述数据连接线与所述数据信号线连接，所述第二引出线组中的引出线与所述数据信号线连接。
  15. 根据权利要求14所述的显示基板，其中，所述第一引出线组的多条引出线按照编号递增的方式沿着所述第一方向依次设置，所述第二引出线组的多条引出线按照编号递增的方式沿着所述第一方向的反方向依次设置； 或者，所述第一引出线组的多条引出线按照编号递增的方式沿着所述第一方向的反方向依次设置，所述第二引出线组的多条引出线按照编号递增的方式沿着所述第一方向依次设置。
  16. 根据权利要求1至15任一项所述的显示基板，其中，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个晶体管；在垂直于显示基板的平面内，所述驱动电路层包括在基底上依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述半导体层至少包括多个晶体管的有源层，所述第一导电层至少包括多个晶体管的栅电极和存储电容的第一极板，所述第二导电层至少包括存储电容的第二极板，所述第三导电层至少包括多个晶体管的第一极、第二极和所述第一连接线，所述第四导电层至少包括所述数据信号线、所述第二连接线和第一电源线，所述数据信号线通过第一连接孔与所述第一连接线的第一端连接，所述第二连接线通过第二连接孔与所述第一连接线的第二端连接。
  17. 根据权利要求16所述的显示基板，其中，所述绑定区域至少包括引线区，所述引线区至少包括多条引出线，多条引出线包括设置在所述第一导电层中的多条第一引出线和设置在所述第二导电层中的多条第二引出线；所述第一引出线与所述显示区域中奇数单元列的数据信号线连接，所述第二引出线与所述显示区域中偶数单元列的数据信号线连接；或者，所述第一引出线与所述显示区域中偶数单元列的数据信号线连接，所述第二引出线与所述显示区域中奇数单元列的数据信号线连接。
  18. 根据权利要求17所述的显示基板，其中，所述第一导电层还包括多个第一引线电极，所述第一引线电极与所述第一引出线连接；所述第二导电层还包括多个第二引线电极，所述第二引线电极与所述第二引出线连接；所述第三导电层还包括多个第三引线电极和多个第四引线电极，所述第三引线电极通过过孔与所述第一引线电极连接，所述第四引线电极通过过孔与所述第二引线电极连接；所述显示区域中奇数单元列的数据信号线通过过孔与第三引线电极连接，所述显示区域中偶数单元列的数据信号线通过过孔与第四引线电极连接；或者，所述显示区域中偶数单元列的数据信号线通过过孔与第三引线电极连接，所述显示区域中奇数单元列的数据信号线通过过孔与 第四引线电极连接。
  19. 根据权利要求16所述的显示基板，其中，所述第三导电层还包括多条沿着所述第一方向延伸的第一电源走线，所述第四导电层还包括多条沿着所述第二方向延伸的第二电源走线，所述第二电源走线通过第三连接孔与所述第一电源走线连接。
  20. 根据权利要求19所述的显示基板，其中，所述绑定区域至少包括引线区，所述引线区至少包括多个绑定高压电极，多个绑定高压电极沿着所述第一方向依次设置，所述绑定高压电极被配置为与所述第一电源线连接，在所述第一方向相邻的绑定高压电极之间，设置有一个与所述数据信号线连接的引线电极。
  21. 根据权利要求20所述的显示基板，其中，部分相邻的绑定高压电极之间，还设置有一个与所述第二连接线连接的引线电极。
  22. 根据权利要求16所述的显示基板，其中，所述多个晶体管至少包括驱动晶体管、复位晶体管和补偿晶体管，所述存储电容包括第一极板和第二极板，所述第三导电层还包括第一连接电极和第二连接电极，所述第一连接电极分别与所述第一极板、所述驱动晶体管的栅电极、所述复位晶体管的第二极和所述补偿晶体管的第一极连接，所述第二连接电极分别与所述第二极板和所述第一电源线连接。
  23. 根据权利要求22所述的显示基板，其中，所述第一连接电极在基底上的正投影与所述第一电源线在基底上的正投影至少部分交叠。
  24. 根据权利要求22所述的显示基板，其中，所述第二连接电极在基底上的正投影与所述第一电源线在基底上的正投影至少部分交叠。
  25. 根据权利要求16所述的显示基板，其中，所述多个晶体管至少包括数据写入晶体管，至少一个电路单元中，所述第三导电层图案还包括数据连接电极，所述数据连接电极与所述第一连接线连接，所述数据连接电极和所述数据写入晶体管的第一极为共用结构。
  26. 一种显示装置，包括如权利要求1至25任一项所述的显示基板。
  27. 一种显示基板的制备方法，所述显示基板包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括构成多个单元行和多个单元列的多个电路单元、多条数据信号线和多条数据连接线，所述数据连接线包括沿着第一方向延伸的第一连接线和沿着第二方向延伸的第二连接线，所述第一连接线和所述第二连接线连接，所述第一方向和所述第二方向交叉；所述制备方法包括：
    在至少一个电路单元中形成所述数据信号线和第一连接线，所述第一连接线通过第一连接孔与所述数据信号线连接，在所述第一方向上相邻的两个第一连接孔之间，设置有至少一条数据信号线。
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