WO2023221040A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023221040A1
WO2023221040A1 PCT/CN2022/093857 CN2022093857W WO2023221040A1 WO 2023221040 A1 WO2023221040 A1 WO 2023221040A1 CN 2022093857 W CN2022093857 W CN 2022093857W WO 2023221040 A1 WO2023221040 A1 WO 2023221040A1
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Prior art keywords
connection electrode
pixel
sub
signal line
line
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PCT/CN2022/093857
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001294.2A priority Critical patent/CN117441420A/zh
Priority to PCT/CN2022/093857 priority patent/WO2023221040A1/zh
Publication of WO2023221040A1 publication Critical patent/WO2023221040A1/zh

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  • the present disclosure relates to but is not limited to the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT thin film transistors
  • the present disclosure provides a display substrate including a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit, the pixel driving circuit is respectively connected to a scanning signal line extending along a first direction and a scanning signal line extending along a second direction.
  • the first power line is connected to the scanning signal line, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit, the first power line is configured to provide a power signal to the pixel driving circuit, the first direction is connected to The second direction crosses; in at least one sub-pixel, the scanning signal line is provided with at least one fracture that cuts off the scanning signal line, and the scanning signal lines on both sides of the fracture are connected to each other through signal connection electrodes, and the signal
  • the length of the connection electrode is greater than the width of the first power line, the length of the signal connection electrode is less than the sub-pixel width, the length is the size of the signal connection electrode in the first direction, and the width is the size of the first power line.
  • the size of a power line in the first direction, and the sub-pixel width is the size of the sub-pixel in the first direction X.
  • the scan signal line includes a first scan signal line that provides a first scan signal to the pixel driving circuit
  • the break includes a first break that cuts off the first scan signal line
  • the The signal connection electrode includes a first signal connection electrode, the first end of the first signal connection electrode is connected to the first scanning signal line on the side of the first fracture through a via hole, and the first signal connection electrode The second end is connected to the first scanning signal line on the other side of the first break through a via hole.
  • the length of the first signal connection electrode is greater than the width of the first power line.
  • the first signal connection The length of the electrode is less than the sub-pixel width.
  • the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel sequentially arranged along the first direction, and the first break and the fourth sub-pixel are arranged sequentially along the first direction.
  • a signal connection electrode is arranged in the first sub-pixel, or the first break and the first signal connection electrode are set in the second sub-pixel, or the first break and the first signal connection electrode is provided in the third sub-pixel, or the first break and the first signal connection electrode are provided in the fourth sub-pixel.
  • the display substrate on a plane perpendicular to the display substrate, includes a plurality of conductive layers, the first signal connection electrode and the first power supply line are provided in the same conductive layer, and the The first scanning signal line and the first power supply line are provided in different conductive layers.
  • the scan signal line includes a second scan signal line that provides a second scan signal to the pixel driving circuit
  • the break includes a second break that cuts off the second scan signal line
  • the The signal connection electrode includes a second signal connection electrode, the first end of the second signal connection electrode is connected to the second scanning signal line on the side of the second fracture through a via hole, and the second signal connection electrode The second end is connected to the second scanning signal line on the other side of the second break through a via hole.
  • the length of the second signal connection electrode is greater than the width of the first power line.
  • the second signal connection The length of the electrode is smaller than the sub-pixel width.
  • the display substrate on a plane perpendicular to the display substrate, includes a plurality of conductive layers, the second signal connection electrode and the first power supply line are provided in the same conductive layer, and the The second scanning signal line and the first power supply line are provided in different conductive layers.
  • the pixel driving circuit is further connected to a compensation signal line, and the compensation signal line is configured to provide a compensation signal to the pixel driving circuit; in at least one sub-pixel, the compensation signal line at least includes A compensation connection electrode and a first compensation signal line and a second compensation signal line arranged at intervals.
  • the first end of the compensation connection electrode is connected to the first compensation signal line through a via hole.
  • the second end of the compensation connection electrode It is connected to the second compensation signal line through a via hole.
  • the orthographic projection of the compensation connection electrode on the display substrate at least partially overlaps the orthographic projection of the second fracture on the display substrate.
  • an orthographic projection of the compensation connection electrode on the display substrate at least partially overlaps an orthographic projection of the second signal connection electrode on the display substrate.
  • At least one through hole is provided on the second signal connection electrode, and an orthographic projection of the through hole on the display substrate at least partially overlaps with an orthographic projection of the compensation connection electrode on the display substrate.
  • the plurality of sub-pixels include first, second, third and fourth sub-pixels sequentially arranged along the first direction, and the first compensation signal line , the second compensation signal line and the compensation connection electrode are arranged between the second sub-pixel and the third sub-pixel.
  • the scan signal line includes a second scan signal line that provides a second scan signal to the pixel driving circuit
  • the break includes a second break that cuts off the second scan signal line
  • the The signal connection electrode includes a third signal connection electrode, a fourth signal connection electrode and a fifth signal connection electrode.
  • the first end of the third signal connection electrode and the second scanning signal line on the side of the second break are respectively
  • the second end of the third signal connection electrode and the second scanning signal line on the other side of the second break are connected to the fourth signal connection electrode through a via hole, respectively.
  • the signal connection electrodes are connected, the length of the third signal connection electrode is greater than the width of the first power supply line, and the length of the third signal connection electrode is less than the width of the sub-pixel.
  • the display substrate on a plane perpendicular to the display substrate, includes a plurality of conductive layers, the fourth signal connection electrode, the fifth signal connection electrode and the first power line are disposed on In the same conductive layer, the second scanning signal line and the first power supply line are provided in different conductive layers.
  • the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel sequentially arranged along the first direction, and the fourth signal connection electrode is disposed in the second sub-pixel, and the fifth signal connection electrode is disposed in the third sub-pixel.
  • the scanning signal lines include a first scanning signal line that provides a first scanning signal to the pixel driving circuit and a second scanning signal line that provides a second scanning signal to the pixel driving circuit, so
  • the fracture includes a first fracture that intercepts the first scanning signal line and a second fracture that intercepts the second scanning signal line.
  • the signal connection electrode includes a first signal connection electrode and a second signal connection electrode.
  • the third signal connection electrode A signal connection electrode is connected to the first signal connection electrode on both sides of the first fracture through a via hole, and the second signal connection electrode is connected to the second signal connection electrode on both sides of the second fracture through a via hole. Signal connection electrode connection.
  • the pixel driving circuit at least includes a storage capacitor; on a plane perpendicular to the display substrate, the display substrate includes a transparent conductive layer, a first conductive layer, a semiconductor layer, and a third conductive layer sequentially disposed on the substrate.
  • the transparent conductive layer at least includes the first plate of the storage capacitor
  • the semiconductor layer at least includes the second plate of the storage capacitor
  • the second conductive layer at least includes The scanning signal line
  • the third conductive layer at least includes the first power line
  • the signal connection electrodes are provided in the third conductive layer, or the signal connection electrodes are respectively provided on the first conductive layer and the third conductive layer.
  • the scanning signal line includes a first scanning signal line
  • the signal connection electrode includes a first signal connection electrode
  • the first scanning signal line is provided in the second conductive layer
  • the A first signal connection electrode is provided in the third conductive layer.
  • the scanning signal line includes a second scanning signal line
  • the signal connection electrode includes a second signal connection electrode
  • the second scanning signal line is provided in the second conductive layer
  • the A second signal connection electrode is provided in the third conductive layer.
  • the first conductive layer further includes a compensation connection electrode
  • the third conductive layer further includes a first compensation signal line and a second compensation signal line.
  • the scan signal line includes a second scan signal line
  • the signal connection electrode includes a third signal connection electrode, a fourth signal connection electrode, and a fifth signal connection electrode
  • the second scan signal line Disposed in the second conductive layer
  • the third signal connection electrode is disposed in the first conductive layer
  • the fourth signal connection electrode and the fifth signal connection electrode are disposed in the third conductive layer.
  • the present disclosure also provides a display device, including the aforementioned display substrate.
  • the present disclosure also provides a method of manufacturing a display substrate, the display substrate including a plurality of sub-pixels, the manufacturing method includes:
  • a pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit is respectively connected to a scanning signal line extending along a first direction and a first power supply line extending along a second direction, and the scanning signal line is configured to A scanning signal is provided to the pixel driving circuit, the first power supply line is configured to provide a power signal to the pixel driving circuit, the first direction intersects the second direction; the scanning signal line is provided with at least A break that cuts off the scanning signal line.
  • the scanning signal lines on both sides of the break are connected to each other through signal connection electrodes. The length of the signal connection electrode is greater than the width of the first power line.
  • the length of the signal connection electrode is Less than the sub-pixel width, the length is the size of the signal connection electrode in the first direction, the width is the size of the first power line in the first direction, and the sub-pixel width is the sub-pixel width.
  • the size of the first direction X is Less than the sub-pixel width, the length is the size of the signal connection electrode in the first direction, the width is the size of the first power line in the first direction, and the sub-pixel width is the sub-pixel width.
  • Figure 1 is a schematic structural diagram of a display device
  • Figure 2 is a schematic diagram of the planar structure of a display substrate
  • Figure 3 is a schematic cross-sectional structural diagram of a display substrate
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit
  • Figure 5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 6 is a schematic diagram after forming a transparent conductive layer pattern according to an embodiment of the present disclosure.
  • FIG. 7a and 7b are schematic diagrams after forming a first conductive layer pattern according to an embodiment of the present disclosure
  • FIGS. 8a and 8b are schematic diagrams after forming a semiconductor layer pattern according to an embodiment of the present disclosure.
  • 9a and 9b are schematic diagrams after forming a second conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram after forming a third insulating layer pattern according to an embodiment of the present disclosure.
  • 11a and 11b are schematic diagrams after forming a third conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram after forming a flat layer pattern according to an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram after forming an anode conductive layer pattern according to an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram after forming a pixel definition layer pattern according to an embodiment of the present disclosure.
  • Figure 15 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 16 is a schematic diagram after forming a first conductive layer pattern according to another embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram after forming a semiconductor layer pattern according to another embodiment of the present disclosure.
  • Figure 18 is another schematic diagram after forming a second conductive layer pattern according to another embodiment of the present disclosure.
  • Figure 19 is another schematic diagram after forming a third insulating layer pattern according to another embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram after forming a third conductive layer pattern according to another embodiment of the present disclosure.
  • 21 power connection line
  • 22 compressor connection line
  • 23 shielding layer
  • 70 data signal line
  • 80 compressor signal line
  • 81 first compensation signal line
  • 103 Light-emitting structural layer
  • 104 Packaging structural layer
  • 301 Anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 the first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged with each other. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other, and “source terminal” and “drain terminal” can be interchanged with each other.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • Figure 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver and a pixel array.
  • the timing controller is connected to the data driver and the scan driver respectively.
  • the data driver is connected to a plurality of data signal lines (D1 to Dn).
  • the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scanning signal line and Data signal line connection.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver. driver.
  • the data driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and D using the grayscale values and control signals received from the timing controller.
  • the data driver may sample a grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to D in pixel row units, and n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller.
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may generate the scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal , m can be a natural number.
  • Figure 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P may include a first sub-pixel P1 that emits light of a first color, a first sub-pixel P1 that emits light of a second color. The second sub-pixel P2, the third sub-pixel P3 that emits light of the third color, and the fourth sub-pixel P4 that emits light of the fourth color.
  • Each of the four sub-pixels may include a circuit unit and a light-emitting device, and the circuit unit may include a pixel driving circuit. The pixel driving circuit is connected to the scanning signal line and the data signal line respectively.
  • the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scanning signal line.
  • the light-emitting device in each pixel unit is respectively connected to the pixel driving circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a white sub-pixel (W) emitting white light
  • the third sub-pixel P3 may be A blue sub-pixel (B) that emits blue light
  • the fourth sub-pixel P4 may be a green sub-pixel (G) that emits green light.
  • the shape of the sub-pixel may be a rectangular shape, a rhombus shape, a pentagonal shape, or a hexagonal shape.
  • four sub-pixels may be arranged horizontally in parallel to form an RWBG pixel arrangement.
  • the four sub-pixels may be arranged in a square, diamond, or vertical arrangement, which is not limited in this disclosure.
  • a plurality of sub-pixels arranged in sequence in the horizontal direction are called pixel rows, and a plurality of sub-pixels arranged in sequence in the vertical direction are called pixel columns.
  • the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. .
  • FIG. 3 is a schematic cross-sectional structural diagram of a display substrate, illustrating the structure of four sub-pixels of the display substrate.
  • each sub-pixel in the display substrate may include a driving circuit layer 102 provided on the substrate 101 , a light-emitting structure layer 103 provided on the side of the driving circuit layer 102 away from the substrate, and The packaging structure layer 104 is provided on the side of the light-emitting structure layer 103 away from the substrate.
  • substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may at least include a pixel driving circuit composed of a plurality of transistors and storage capacitors.
  • the light-emitting structure layer 103 of each sub-pixel may at least include a light-emitting device and a pixel definition layer 302.
  • the light-emitting device may include an anode 301, an organic light-emitting layer 303 and a cathode 304.
  • the anode 301 is connected to the pixel driving circuit, and the organic light-emitting layer 303 is connected to the anode 301.
  • the packaging structure layer 104 may include a stacked first packaging layer 401, a second packaging layer 402, and a third packaging layer 403.
  • the first packaging layer 401 and the third packaging layer 403 may be made of inorganic materials
  • the second packaging layer 402 may be made of Organic material
  • the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light emitting layer (EML), a hole blocking layer (HBL) ), electron transport layer (ETL) and electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EML light emitting layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be a common layer connected together, and the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer of all sub-pixels may be connected together.
  • the light-emitting layers may be a common layer connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap.
  • the display substrate may include other film layers, which is not limited in this disclosure.
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit has a 3T1C structure and may include 3 transistors (first transistor T1, second transistor T2 and third transistor T3), 1 storage capacitor C and 6 signal lines (data signal line D , the first scanning signal line S1, the second scanning signal line S2, the compensation signal line S, the first power supply line VDD and the second power supply line VSS).
  • the first transistor T1 is a switching transistor
  • the second transistor T2 is a driving transistor
  • the third transistor T3 is a compensation transistor.
  • the first electrode of the storage capacitor C is coupled to the gate electrode of the second transistor T2, and the second electrode of the storage capacitor C is coupled to the second electrode of the second transistor T2.
  • the storage capacitor C is used to store the gate electrode of the second transistor T2. potential.
  • the gate electrode of the first transistor T1 is coupled to the first scanning signal line S1, the first electrode of the first transistor T1 is coupled to the data signal line D, and the second electrode of the first transistor T1 is coupled to the gate of the second transistor T2.
  • the first transistor T1 is used to receive the data signal transmitted by the data signal line D under the control of the first scanning signal line S1, so that the gate electrode of the second transistor T2 receives the data signal.
  • the gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1
  • the first electrode of the second transistor T2 is coupled to the first power line VDD
  • the second electrode of the second transistor T2 is coupled to the light emitting device.
  • the first pole and the second transistor T2 are used to generate a corresponding current at the second pole under the control of the data signal received by its gate electrode.
  • the gate electrode of the third transistor T3 is coupled to the second scanning signal line S2, the first electrode of the third transistor T3 is coupled to the compensation signal line S, and the second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2.
  • the second transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate the threshold voltage Vth.
  • the light-emitting device may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).
  • the first electrode of the OLED is coupled to the second electrode of the second transistor T2. pole, the second pole of the OLED is coupled to the second power line VSS, and the OLED is used to respond to the current of the second pole of the second transistor T2 to emit light with corresponding brightness.
  • the signal of the first power line VDD is a continuously provided high-level signal
  • the signal of the second power line VSS is a continuously provided low-level signal.
  • the first to third transistors T1 to T3 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel drive circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield.
  • the first to third transistors T1 to T3 may employ low-temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of low temperature polysilicon thin film transistors uses low temperature polysilicon (LTPS), and the active layer of oxide thin film transistors uses oxide (Oxide).
  • LTPS low temperature polysilicon
  • Oxide oxide
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current.
  • a low temperature polycrystalline silicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (LTPO) display substrate, and the advantages of both can be utilized. It can achieve high resolution (Pixel Per Inch, referred to as PPI) and low-frequency driving, which can reduce power consumption and improve display quality.
  • the working process of the pixel driving circuit illustrated in Figure 4 may include:
  • the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals
  • the data signal line D outputs the data voltage
  • the compensation signal line S outputs the compensation voltage
  • the signal of the first power line VDD is High level
  • the signal of the second power line VSS is low level.
  • the signal of the first scanning signal line S1 is a high-level signal, which turns on the first transistor T1.
  • the signal of the second scanning signal line S2 is a high-level signal, turning on the third transistor T3, and the compensation voltage output by the compensation signal line S is written into the second node N2.
  • the first pole of the OLED provides a driving voltage to drive the OLED to emit light.
  • the signals of the first scanning signal line S1 and the second scanning signal line S2 are low-level signals, causing the first transistor T1 and the third transistor T3 to turn off, and the voltage in the storage capacitor C still causes the second transistor to turn off.
  • T2 is in the on state, the power supply voltage output by the first power line VDD continues to raise the potential of the second node N2, and the OLED continues to emit light.
  • the potential of the second node N2 is equal to V data -V th , the second transistor T2 is turned off, and the OLED no longer emits light.
  • both the OLED and the second transistor T2 are forward biased.
  • the power supply voltage output by the first power supply line VDD is greater than the data voltage output by the data signal line D.
  • the data voltage output by the signal line D is greater than the compensation voltage output by the compensation signal line S, and the compensation voltage output by the compensation signal line S is greater than the power supply voltage output by the second power supply line VSS.
  • Exemplary embodiments of the present disclosure provide a display substrate including a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit, the pixel driving circuit is connected to a scanning signal line extending along a first direction and a scanning signal line extending along a second direction respectively.
  • An extended first power supply line is connected, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit, the first power supply line is configured to provide a high voltage signal to the pixel driving circuit, the first The direction intersects the second direction; in at least one sub-pixel, the scanning signal line is provided with at least one fracture that cuts off the scanning signal line, and the scanning signal lines on both sides of the fracture are connected to each other through signal connection electrodes, so The length of the signal connection electrode is greater than the width of the first power line, the length of the signal connection electrode is less than the sub-pixel width, the length is the size of the signal connection electrode in the first direction, and the width is the The size of the first power line in the first direction, and the sub-pixel width is the size of the sub-pixel in the first direction X.
  • the scan signal line includes a first scan signal line that provides a first scan signal to the pixel driving circuit, and the break includes a first break that cuts off the first scan signal line
  • the signal connection electrode includes a first signal connection electrode, a first end of the first signal connection electrode is connected to the first scanning signal line on one side of the first fracture through a via hole, and the first signal connection The second end of the electrode is connected to the first scanning signal line on the other side of the first break through a via hole.
  • the length of the first signal connection electrode is greater than the width of the first power line.
  • the first The length of the signal connection electrode is smaller than the width of the sub-pixel.
  • the scan signal line includes a second scan signal line that provides a second scan signal to the pixel driving circuit
  • the break includes a second break that cuts off the second scan signal line.
  • the signal connection electrode includes a second signal connection electrode, the first end of the second signal connection electrode is connected to the second scanning signal line on the side of the second fracture through a via hole, the second signal connection electrode The second end of the connection electrode is connected to the second scanning signal line on the other side of the second break through a via hole.
  • the length of the second signal connection electrode is greater than the width of the first power line.
  • the length of the two signal connection electrodes is smaller than the width of the sub-pixel.
  • the scan signal line includes a second scan signal line that provides a second scan signal to the pixel driving circuit, and the break includes a second break that cuts off the second scan signal line.
  • the signal connection electrode includes a third signal connection electrode, a fourth signal connection electrode and a fifth signal connection electrode, the first end of the third signal connection electrode and the second scan on one side of the second fracture
  • the signal lines are respectively connected to the fourth signal connection electrode through via holes, and the second end of the third signal connection electrode and the second scanning signal line on the other side of the second fracture are respectively connected to the fourth signal connection electrode through via holes.
  • the fifth signal connection electrode is connected, the length of the third signal connection electrode is greater than the width of the first power line, and the length of the third signal connection electrode is less than the width of the sub-pixel.
  • the scan signal line includes a first scan signal line that provides a first scan signal to the pixel drive circuit and a second scan signal line that provides a second scan signal to the pixel drive circuit.
  • the fracture includes a first fracture that intercepts the first scanning signal line and a second fracture that intercepts the second scanning signal line
  • the signal connection electrode includes a first signal connection electrode and a second signal connection electrode
  • FIG. 5 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a driving circuit layer of a pixel unit (four sub-pixels) in a bottom-emission display substrate.
  • at least one pixel unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3 and a third sub-pixel P1, which are sequentially arranged along the first direction X.
  • each sub-pixel may include a pixel driving circuit and a storage capacitor.
  • sub-pixel refers to the area where the pixel driving circuit is installed.
  • At least one pixel unit may include a first scanning signal line 41, a second scanning signal line 42, two first power supply lines 60, four data signal lines 70, and a compensation signal line 80, as described above.
  • the signal lines are all connected to the pixel driving circuits in the four sub-pixels.
  • the shape of the first scanning signal line 41 and the second scanning signal line 42 may be a straight line extending along the first direction
  • the second directions Y are arranged in sequence, and the first direction X and the second direction Y intersect.
  • the shape of the first power supply line 60 , the data signal line 70 and the compensation signal line 80 may be a straight line extending along the second direction Y.
  • two first power lines 60 may be respectively disposed on both sides of the first direction X of the pixel unit, and four data signal lines 70 and one compensation signal line 80 may be disposed between the two first power lines 60 During the period, two of the four data signal lines 70 may be located between the compensation signal line 80 and a first power line 60, and the other two of the four data signal lines 70 may be located between the compensation signal line 80 and the first power supply line 60. between the line 80 and another first power line 60 . In this way, four sub-pixels can be formed by arranging four data signal lines 70 and one compensation signal line 80 between the two first power lines 60.
  • two first power lines 60 are arranged between the two compensation signal lines 80. and four data signal lines 70 may also form four sub-pixels.
  • a first sub-pixel P1 is formed between a first power line 60 and a data signal line 70 adjacent to the first direction X, and a compensation signal line 80 is adjacent to a data signal line 70 in the opposite direction of the first direction X.
  • the second sub-pixel P2 is formed between the signal lines 70, the third sub-pixel P3 is formed between the compensation signal line 80 and a data signal line 70 adjacent to the first direction
  • a fourth sub-pixel P4 is formed between one data signal line 70 adjacent in the opposite direction.
  • the pixel driving circuit of at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor.
  • the first transistor T1, the second transistor T2 and the third transistor T3 may each include an active layer, a gate electrode, a first electrode and a second electrode, and the storage capacitor may include a transparent first plate and a transparent second plate, Form a transparent storage capacitor.
  • the first scanning signal line 41 is connected to the gate electrode of the first transistor T1 in each sub-pixel
  • the second scanning signal line 42 is connected to the gate electrode of the third transistor T3 in each sub-pixel
  • the data signal line 70 is connected to the first electrode of the first transistor T1 in each sub-pixel
  • the compensation signal line 80 is connected to the first electrode of the third transistor T3 in each sub-pixel
  • the first power supply line 60 is connected to the first electrode of the second transistor T2 in each sub-pixel.
  • the first electrode is connected, the second electrode of the first transistor T1 in each sub-pixel is connected to the gate electrode of the second transistor T2, the second electrode of the second transistor T2 in each sub-pixel is connected to the first electrode of the third transistor T3 and emits light.
  • the anode of the device is connected, the first plate in each sub-pixel is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3, and the second plate in each sub-pixel is connected to the third electrode of the first transistor T1 respectively.
  • the diode is connected to the gate electrode of the second transistor T2.
  • At least one pixel unit may further include a plurality of connection lines, and the plurality of connection lines may include at least two power supply connection lines 21 extending along the first direction X and two power connection lines 21 extending along the first direction X.
  • the compensation connection line 22 forms a one-to-two structure of the first power line and a one-to-four structure of the compensation signal line.
  • a power connection line 21 is provided at the first sub-pixel P1 and the second sub-pixel P2, and a first end of the power connection line 21 is connected to the first power supply located in the first sub-pixel P1 through a via hole.
  • the line 60 is connected, and the second end is connected to the second transistor T2 in the second sub-pixel P2 through a via hole.
  • Another power connection line 21 is provided in the third sub-pixel P3 and the fourth sub-pixel P4.
  • the first end of the power connection line 21 is connected to the first power line 60 in the fourth sub-pixel P4 through a via hole.
  • the terminal is connected to the second transistor T2 in the third sub-pixel P3 through a via hole.
  • a compensation connection line 22 is provided at the first sub-pixel P1 and the second sub-pixel P2.
  • the compensation connection line 22 is connected to the compensation signal line 80 through the via hole, and on the other hand, the compensation connection line 22 is connected to the compensation signal line 80 through the via hole respectively.
  • the third transistor T3 is connected to the first sub-pixel P1 and the second sub-pixel P2.
  • Another compensation connection line 22 is provided in the third sub-pixel P3 and the fourth sub-pixel P4.
  • the compensation connection line 22 is connected to the compensation signal line 80 through the via hole, and on the other hand, it is connected to the third sub-pixel P3 through the via hole. Connected to the third transistor T3 in the fourth sub-pixel P4. In this way, one compensation signal line 80 can provide compensation signals to the pixel driving circuits of four sub-pixels.
  • the embodiments of the present disclosure save the number of signal lines and reduce the occupied space through the one-to-two structure of the first power line and the one-to-four structure of the compensation signal line.
  • the structure is simple, the layout is reasonable, and the layout space is fully utilized. Improves space utilization and helps improve resolution.
  • At least one of the first scanning signal line 41 and the second scanning signal line 42 is provided with at least one break that cuts off the scan signal line, and the scan signal lines on both sides of the break are connected to each other through signal connection electrodes.
  • the first scanning signal line 41 in at least one sub-pixel is provided with a first break K1 that cuts off the first scanning signal line 41, and the first scanning signal lines 41 on both sides of the first break K1 pass through
  • the first signal connection electrode 91 is connected.
  • the first end of the first signal connection electrode 91 is connected to the first scanning signal line 41 on the opposite side of the first direction X of the first break K1 through a via hole.
  • the second end is connected to the first scanning signal line 41 on the first direction X side of the first break K1 through a via hole, thereby realizing continuous transmission of the first scanning signal.
  • the first signal connection electrode 92 has a first length L1 and the first power supply line 60 has a width M.
  • the first length L1 may be the size of the first signal connection electrode 91 in the first direction X, that is, the size of the extension direction of the first signal connection electrode 91 .
  • the width M may be the size of the first power line 60 in the second direction Y, that is, the size perpendicular to the extending direction of the first power line 60 .
  • the width M may be the maximum size of the first power line 60 in the second direction Y, or the width M may be the average size of the first power line 60 in the second direction Y.
  • the first length L1 of the first signal connection electrode 91 may be greater than the width M of the first power line 60 .
  • At least one sub-pixel has a sub-pixel width
  • the sub-pixel width may be a size of the sub-pixel in the first direction X
  • the first length L1 of the first signal connection electrode 91 may be smaller than the sub-pixel width
  • the first length L1 of the first signal connection electrode 91 may be approximately 50% to 80% of the sub-pixel width.
  • the orthographic projection of the first signal connection electrode 91 on the display substrate does not overlap with the orthographic projection of the first power supply line 60 and the data signal line 70 on the display substrate.
  • the first break K1 and the first signal connection electrode 91 may be disposed in the first sub-pixel P1, or the first break K1 and the first signal connection electrode 91 may be disposed in the second sub-pixel P2 , or the first break K1 and the first signal connection electrode 91 may be disposed in the third sub-pixel P3, or the first break K1 and the first signal connection electrode 91 may be disposed in the fourth sub-pixel P4.
  • the second scanning signal line 42 in at least one sub-pixel is provided with a second break K2 that cuts off the second scanning signal line 42, and the second scanning signal lines 42 on both sides of the second break K2
  • the connection is made via the second signal connection electrode 92 .
  • the first end of the second signal connection electrode 92 is connected to the second scanning signal line 42 on the opposite side of the first direction X of the second break K2 through a via hole.
  • the second end is connected to the second scanning signal line 42 on the first direction X side of the second break K2 through a via hole, thereby realizing continuous transmission of the second scanning signal.
  • the second signal connection electrode 92 has a second length L2
  • the first power line 60 has a width M
  • the second length L2 may be a size of the second signal connection electrode 92 in the first direction X, that is, the second The size in the extending direction of the signal connection electrode 92.
  • the second length L2 of the second signal connection electrode 92 may be greater than the width M of the first power line 60 .
  • the second length L2 of the second signal connection electrode 92 may be smaller than the sub-pixel width.
  • the second length L2 of the second signal connection electrode 92 may be approximately 50% to 80% of the sub-pixel width.
  • the orthographic projection of the second signal connection electrode 92 on the display substrate does not overlap with the orthographic projection of the first power supply line 60 and the data signal line 70 on the display substrate.
  • the second break K2 and the second signal connection electrode 92 may be disposed in a region between the second sub-pixel P2 and the third sub-pixel P3.
  • the compensation signal line 80 in at least one sub-pixel may include at least a first compensation signal line 81 and a second compensation signal line 82 arranged at intervals, and connect the first compensation signal line 81 and the second compensation signal
  • the compensation of line 82 is connected to electrode 83 .
  • the first end of the compensation connection electrode 83 is connected to the first compensation signal line 81 through the via hole, and the second end of the compensation connection electrode 83 is connected to the second compensation signal line 82 through the via hole, thereby realizing continuous transmission of the compensation signal.
  • the first compensation signal line 81 , the second compensation signal line 82 and the compensation connection electrode 83 may be disposed between the second sub-pixel P2 and the third sub-pixel P3 .
  • the orthographic projection of the compensation connection electrode 83 on the display substrate at least partially overlaps the orthographic projection of the second fracture K2 on the display substrate.
  • the orthographic projection of the compensation connection electrode 83 on the display substrate at least partially overlaps the orthographic projection of the second signal connection electrode 92 on the display substrate.
  • At least one through hole is provided on the second signal connection electrode, and the orthographic projection of the through hole on the display substrate at least partially overlaps the orthographic projection of the compensation connection electrode 83 on the display substrate.
  • the first scanning signal line 41 in at least one sub-pixel is provided with a first break K1 that cuts off the first scanning signal line 41
  • the second scanning signal line 42 in at least one sub-pixel is provided with There is a second break K2 that cuts off the second scanning signal line 42.
  • the first scanning signal lines 41 on both sides of the first break K1 are connected through the first signal connection electrodes 91.
  • the second scanning signal lines 42 on both sides of the second break K2 pass through The second signal connection electrode 92 is connected.
  • the first break K1 and the first signal connection electrode 91 may be disposed at any one or more of the following positions: the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, the fourth sub-pixel Pixel P4, the area between the second sub-pixel P2 and the third sub-pixel P3.
  • the second break K2 and the second signal connection electrode 92 can be arranged at any one or more of the following positions: the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, the fourth sub-pixel P4, the second sub-pixel The area between P2 and the third sub-pixel P3.
  • the first break K1 and the first signal connection electrode 91 may be disposed in at least one sub-pixel of the first to fourth sub-pixels P1 to P4, and the second break K2 and the second signal connection electrode 92 may be disposed in the first sub-pixel P1 to the fourth sub-pixel P4. Within at least one sub-pixel from the sub-pixel P1 to the fourth sub-pixel P4.
  • the first break K1 and the first signal connection electrode 91 may be disposed in at least one sub-pixel of the first to fourth sub-pixels P1 to P4, and the second break K2 and the second signal connection electrode 92 may be disposed in the first sub-pixel P1 to the fourth sub-pixel P4.
  • first break K1 and the first signal connection electrode 91 can be disposed in the area between the second sub-pixel P2 and the third sub-pixel P3, and the second break K2 and the second signal connection electrode 92 can be disposed in the first sub-pixel.
  • the first break K1 and the first signal connection electrode 91 may be disposed in the area between the second sub-pixel P2 and the third sub-pixel P3, and the second break K2 and the second signal connection electrode 92 may be disposed in the second sub-pixel P3. The area between pixel P2 and third sub-pixel P3.
  • the display substrate in a direction perpendicular to the display substrate, may include a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, and a second insulating layer stacked on a substrate. a conductive layer, a third insulating layer and a third conductive layer.
  • the transparent conductive layer may include at least a first electrode plate of the storage capacitor
  • the semiconductor layer may include at least a second electrode plate of the storage capacitor
  • the orthographic projection of the first electrode plate on the substrate is consistent with the second electrode plate. Orthographic projections of the plates on the substrate at least partially overlap, forming a transparent storage capacitor.
  • the second conductive layer may include at least the first scanning signal line 41 and the second scanning signal line 42
  • the third conductive layer may include at least the first power supply line 60, the first signal connection electrode 91 and the second signal connection electrode 92, that is, the third conductive layer may include at least the first scanning signal line 41 and the second scanning signal line 42.
  • a signal connection electrode 91 and a second signal connection electrode 92 may be arranged in the same layer as the first power supply line 60 , and the first scanning signal line 41 and the second scanning signal line 42 may be arranged in a different layer from the first power supply line 60 .
  • the first conductive layer may further include a compensation connection electrode 83
  • the third conductive layer may further include a first compensation signal line 81 and a second compensation signal line 82 .
  • the transparent conductive layer may include at least the first plate of the storage capacitor, the first conductive layer may include at least the power connection line 21, the compensation connection line 22, the shielding layer 23 and the compensation connection electrode 83, and the semiconductor layer may It includes at least a second plate of a storage capacitor and an active layer of three transistors.
  • the second conductive layer may include at least a first scanning signal line 41, a second scanning signal line 42 and gate electrodes of the three transistors.
  • the third conductive layer It may include at least a first power supply line 60 , a data signal line 70 , a compensation signal line 80 , first and second poles of three transistors, a first signal connection electrode 91 and a second signal connection electrode 92 .
  • an orthographic projection of the active layer of the second transistor on the substrate is within a range of an orthographic projection of the blocking layer on the substrate.
  • a plurality of through holes may be provided on the first scanning signal line 41 and the second scanning signal line 42, and the orthographic projection of the through holes on the substrate is in direct contact with the first power supply line 60, the data signal line 70 and the compensation line. Orthographic projections of the signal lines 80 on the substrate at least partially overlap.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • Form a transparent conductive layer pattern may include: depositing a transparent conductive film on a substrate, patterning the transparent conductive film through a patterning process, and forming a transparent conductive layer pattern on the substrate, as shown in FIG. 6 .
  • the transparent conductive layer may be called an ITO layer.
  • the transparent conductive layer pattern of each sub-pixel may include at least the first plate 11 of the storage capacitor, the connection plate 12 and the connection line 13 .
  • the shape of the first plate 11 may be a rectangle, the corners of the rectangle may be chamfered, and the edges of the rectangle may be folded lines, and the first plate 11 may be disposed in the second direction of the sub-pixel. In the middle region of Y, the first plate 11 is configured to form a transparent plate of a transparent storage capacitor.
  • the shape of the connecting plate 12 may be a polygonal shape
  • the connecting plate 12 may be disposed on one side of the first pole plate 11 in the second direction Y, and be connected to the first pole plate 11
  • the connecting plate 12 is configured To connect with the subsequent occlusion layer.
  • the shape of the connecting line 13 may be a strip shape extending along the second direction Y.
  • the connecting line 13 may be disposed on a side of the first plate 11 away from the connecting plate 12 and connected with the first plate 11 . 11 connections.
  • the end of the connecting wire 13 away from the first plate 11 may be provided with a connecting block 13-1.
  • the shape of the connecting block 13-1 may be a strip shape extending along the first direction X and is connected to the connecting wire 13.
  • the connecting block 13-1 13-1 is configured to be connected to a subsequently formed interlayer connection electrode.
  • the first pole plate 11 , the connecting plate 12 and the connecting wire 13 may be an integral structure connected to each other.
  • forming the first conductive layer pattern may include: depositing a first conductive film on a substrate on which the foregoing pattern is formed, patterning the first conductive film through a patterning process, and forming a first conductive film on the transparent conductive layer.
  • the conductive layer pattern is shown in Figures 7a and 7b.
  • Figure 7b is a schematic plan view of the first conductive layer in Figure 7a.
  • the first conductive layer may be referred to as a shield metal (SHL) layer.
  • SHL shield metal
  • the first conductive layer pattern in each sub-pixel may include at least a power supply connection line 21 , a compensation connection line 22 , a shielding layer 23 and an interlayer connection electrode 24 .
  • the shape of the power connection line 21 may be a strip shape extending along the first direction is connected to provide the power supply voltage to the second transistor T2 of the sub-pixel.
  • the power connection lines 21 of adjacent sub-pixels in the first direction X may be an integral structure connected to each other.
  • the power supply connection lines 21 in the first sub-pixel P1 and the second sub-pixel P2 are connected to each other, and the power supply connection lines 21 in the third sub-pixel P3 and the fourth sub-pixel P3 are connected to each other, but the second sub-pixel P2 and the third sub-pixel P3 are connected to each other.
  • the power connection line 21 in the third sub-pixel P3 is not connected.
  • the shape of the compensation connection line 22 may be a strip shape extending along the first direction , providing a compensation voltage to the third transistor T3 of the sub-pixel.
  • the compensation connection lines 22 of adjacent sub-pixels in the first direction X may be an integral structure connected to each other.
  • the compensation connection lines 22 in the first sub-pixel P1 and the second sub-pixel P2 are connected to each other, and the compensation connection lines 22 in the third sub-pixel P3 and the fourth sub-pixel P3 are connected to each other, but the second sub-pixel P2 and the third sub-pixel P3 are connected to each other.
  • the compensation connection lines 22 in the three sub-pixels P3 are not connected.
  • the shielding layer 23 may be in a rectangular shape and may be disposed between the power connection line 21 and the compensation connection line 22 .
  • the shielding layer 23 is configured to provide shielding for the second transistor T2 to avoid light from entering the trench. The channel is affected and the leakage current is reduced, thereby avoiding the impact of light on the characteristics of the transistor and ensuring the electrical performance of the second transistor T2.
  • the orthographic projection of the shielding layer 23 on the substrate may be located within the range of the orthographic projection of the connecting plate 12 on the substrate, and the shielding layer 23 directly overlaps the connecting plate 12 .
  • the interlayer connection electrode 24 may be in a rectangular shape and may be disposed between the shielding layer 23 and the compensation connection line 22 .
  • the interlayer connection electrode 24 is configured to connect with the subsequently formed third transistor T3 Second pole connection.
  • the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps the orthographic projection of the connection block 13 - 1 of the connection line 13 on the substrate, and the interlayer connection electrode 24 and the connection block 13 - 1 Direct overlap.
  • the transparent conductive layer pattern of each pixel unit may further include a compensation connection electrode 83 .
  • the shape of the compensation connection electrode 83 may be a strip shape extending along the second direction Y.
  • the compensation connection electrode 83 may be disposed between adjacent compensation connection lines 22 in the first direction X. That is, the compensation connection electrode 83 may be disposed in the first direction X.
  • the compensation connection electrode 83 is configured as a connection electrode for the compensation signal line, and connects the first compensation signal line and the second spaced-apart compensation signal line by connecting to the compensation signal line formed subsequently. Connect the compensation signal lines.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the foregoing pattern is formed, patterning the semiconductor film through a patterning process, and forming a layer covering the first conductive layer.
  • the first insulating layer, and the semiconductor layer pattern provided on the first insulating layer, are shown in Figures 8a and 8b.
  • Figure 8b is a schematic plan view of the semiconductor layer in Figure 8a.
  • the semiconductor layer pattern in each sub-pixel may include at least a first active layer 31 , a second active layer 32 , a third active layer 33 and a second plate 34 .
  • the shape of the second pole plate 34 may be a rectangular shape.
  • An orthographic projection of the second pole plate 34 on the substrate at least partially overlaps an orthographic projection of the first pole plate 11 on the substrate.
  • the second pole plate 34 may be in a rectangular shape.
  • the plate 34 is configured as another transparent plate forming a transparent storage capacitor, the first plate 11 and the second plate 34 forming a transparent storage capacitor.
  • the first active layer 31 may serve as an active layer of the first transistor T1
  • the second active layer 32 may serve as an active layer of the second transistor T2
  • the third active layer 33 may serve as an active layer of the second transistor T2.
  • the active layer of the three transistor T3, the first active layer 31 and the second active layer 32 can be disposed between the power connection line 21 and the second plate 34, and the third active layer 33 can be disposed between the compensation connection line 22 and the second plate 34.
  • each of the first active layer 31 , the second active layer 32 and the third active layer 33 may include a channel region and first and second regions located on both sides of the channel region.
  • the first active layer 31 may be in an "L" shape, and the first region 31-1 of the first active layer 31 may be located on a side of the channel region away from the second plate 34, The second area 31-2 of the first active layer 31 may be located on the side of the channel area close to the second plate 34.
  • the orthographic projection of the second area 31-2 of the first active layer 31 on the substrate is different from the shielding layer. 23 Orthographic projections on the substrate at least partially overlap.
  • the second region 31 - 2 of the first active layer 31 may be connected to the second electrode plate 34 , and the first active layer 31 and the second electrode plate 34 may be an integral structure connected to each other.
  • the shape of the second active layer 32 may be an "I" shape, and the orthographic projection of the second active layer 32 on the substrate at least partially overlaps the orthographic projection of the blocking layer 23 on the substrate.
  • the orthographic projection of the channel area of the second active layer 32 on the substrate can be located within the range of the orthographic projection of the blocking layer 23 on the substrate.
  • the blocking layer 23 can block the channel area of the second active layer 32 to avoid light. It affects the channel and reduces the leakage current, thereby avoiding the impact of light on the transistor characteristics.
  • the first region 32-1 of the second active layer 32 may be located on a side of the channel region away from the second electrode plate 34, and the orthographic projection of the first region 32-1 of the second active layer 32 on the substrate may be located on the shielding side.
  • Layer 23 is within the orthographic projection on the substrate.
  • the second region 32-2 of the second active layer 32 may be located on a side of the channel region close to the second electrode plate 34, and the orthographic projection of the second region 32-2 of the second active layer 32 on the substrate may be located on the shielding side.
  • Layer 23 is within the orthographic projection on the substrate.
  • the shape of the third active layer 33 may be in an "I" shape, and the orthographic projection of the third active layer 33 on the substrate is spaced apart from the orthographic projection of the second electrode plate 34 on the substrate, that is, There is no overlapping area between the third active layer 33 and the second plate 42, which is beneficial to designing the channel width-to-length ratio of the third transistor according to relevant requirements.
  • the first region 33-1 of the third active layer 33 may be located on a side of the channel region away from the second plate 34, and the orthographic projection of the first region 33-1 of the third active layer 33 on the substrate is connected to the compensation
  • the orthographic projections of lines 22 on the substrate at least partially overlap.
  • the second area 33-2 of the third active layer 33 may be located on the side of the channel area close to the second plate 34.
  • the orthographic projection of the second area 33-2 of the third active layer 33 on the substrate is different from the interlayer
  • the orthographic projections of the connecting electrodes 24 on the substrate at least partially overlap.
  • the semiconductor layer may adopt a metal oxide, such as an oxide including indium and tin, an oxide including tungsten and indium, an oxide including tungsten and indium and zinc, an oxide including titanium and indium, Oxides containing titanium and indium and tin, oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • the semiconductor layer may be a single layer, or may be a double layer, or may be multiple layers.
  • forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the foregoing pattern is formed, patterning the second conductive film through a patterning process, and forming The second insulating layer covering the semiconductor layer and the second conductive layer pattern disposed on the second insulating layer are shown in Figures 9a and 9b.
  • Figure 9b is a schematic plan view of the second conductive layer in Figure 9a.
  • the second conductive layer may be referred to as a gate metal (GATE) layer.
  • GATE gate metal
  • the second conductive layer pattern in each pixel unit may include at least a first scanning signal line 41 , a second scanning signal line 42 , a second gate electrode 43 , an auxiliary power supply line 44 , and an auxiliary data line 45 and auxiliary compensation line 46.
  • the shape of the first scanning signal line 41 may be a strip shape extending along the first direction X, and the first scanning signal line 41 may be located on one side of the second plate 34 in the second direction Y, each A first gate electrode 41-1 is provided on the first scanning signal line 41 of the sub-pixel.
  • the first gate electrode 41-1 serves as the gate electrode of the first transistor T1.
  • the orthographic projection of the first gate electrode 41-1 on the substrate is the same as that of the first gate electrode 41-1. Orthographic projections of the first active layer 31 on the substrate at least partially overlap.
  • the first scanning signal line 41 may be provided with a constant width, and the width is the size of the first scanning signal line 41 in the second direction Y.
  • a plurality of through holes may be provided on the first scanning signal line 41 , and the orthographic projections of the plurality of through holes on the substrate at least partially overlap with the orthographic projections of the subsequently formed first power lines, data signal lines and compensation signal lines on the substrate.
  • the plurality of via holes are configured to reduce parasitic capacitance between the first scanning signal line 41 and the first power supply line, data signal line and compensation signal line.
  • the shape of the second scanning signal line 42 may be a strip shape extending along the first direction X, and the second scanning signal line 42 may be located on a side of the second plate 34 away from the first scanning signal line 41 side, the orthographic projection of the second scanning signal line 42 on the substrate at least partially overlaps the orthographic projection of the third active layer 33 in each sub-pixel on the substrate, and the second scanning signal line 42 in the overlapping area can serve as a third transistor.
  • the second scanning signal line 42 may be provided with unequal widths, and the width is the size of the second scanning signal line 42 in the second direction Y.
  • the second scanning signal line 42 includes an area that overlaps with the third active layer 33 and an area that does not overlap with the third active layer 33 .
  • the second scanning signal line 42 in the area that overlaps with the third active layer 33 The width of may be smaller than the width of the second scanning signal line 42 in the area that does not overlap with the third active layer 33 .
  • a plurality of through holes may be provided on the second scanning signal line 42.
  • the orthogonal projection of the plurality of through holes on the substrate is related to the subsequently formed first power lines and data signals.
  • the orthographic projections of the lines and the compensation signal lines on the substrate at least partially overlap, and the plurality of through holes are configured to reduce parasitic capacitances between the second scanning signal line 42 and the first power supply line, data signal line and compensation signal line.
  • the first scanning signal line 41 and the second scanning signal line 42 may be arranged in parallel.
  • both the first scanning signal line 41 and the second scanning signal line 42 are arranged discontinuously.
  • at least one first break K1 is provided on the first scanning signal line 41.
  • At least one second break K2 is provided on the two scanning signal lines 42 .
  • the first break K1 can be set at any one or more of the following positions: the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, the fourth sub-pixel P4, the second sub-pixel between P2 and the third sub-pixel P3.
  • the second break K2 can be set at any one or more of the following positions: the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, the fourth sub-pixel P4, the second sub-pixel P2 and the third sub-pixel P3. between.
  • At least one first break K1 may be provided at the first sub-pixel P1, and the first break K1 disconnects the first scanning signal line 41 to form a discontinuous structure of the first scanning signal line 41.
  • the first scanning signal lines 41 on both sides of the first break K1 may be connected to each other through the first signal connection electrodes formed subsequently to realize the transmission of the first scanning signal.
  • At least one second break K2 may be disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the second break K2 disconnects the second scanning signal line 42 to form a discontinuous structure of the second break K2.
  • the second scanning signal lines 42 on both sides of the second break K2 may be connected to each other through second signal connection electrodes formed subsequently to realize the transmission of the second scanning signal.
  • the compensation connection electrode 83 may be disposed within the second fracture K2, and the orthographic projection of the compensation connection electrode 83 on the substrate at least partially overlaps with the orthographic projection of the second fracture K2 on the substrate.
  • the shape of the second gate electrode 43 may be a strip shape extending along the first direction X, and the second gate electrode 43 may serve as the gate electrode of the second transistor T2.
  • the orthographic projection of the second gate electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer 32 on the substrate, and on the other hand, the orthographic projection of the second gate electrode 43 on the substrate The orthographic projection at least partially overlaps the second region 31 - 2 of the first active layer 31 .
  • the shape of the auxiliary power line 44 may be a strip shape extending along the second direction Y, and may be respectively provided in the first sub-pixel P1 and the fourth sub-pixel P4.
  • the auxiliary power line 44 is located on the side opposite to the first direction X of the second plate 34.
  • the auxiliary power line 44 is located on one side of the second plate 34 in the first direction X.
  • the auxiliary power line 44 is configured to connect with the subsequently formed first power line to form a double-layer wiring, ensuring the reliability of power signal transmission and reducing the resistance of the first power line.
  • the shape of the auxiliary data line 45 may be a strip shape extending along the second direction Y, and may be respectively provided in each sub-pixel.
  • the auxiliary data line 45 is located on one side of the second plate 34 in the first direction X.
  • the auxiliary data line 45 is located on the side opposite to the first direction X of the second plate 34.
  • the auxiliary data line 45 is configured to connect with the subsequently formed data signal line to form a double-layer wiring to ensure the reliability of data signal transmission and reduce the resistance of the data signal line.
  • the shape of the auxiliary compensation line 46 may be a strip shape extending along the second direction Y, and may be disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the auxiliary compensation line 46 is configured to connect with the compensation signal line formed later to form a double-layer wiring, ensuring the reliability of the compensation signal transmission and reducing the resistance of the compensation signal line.
  • main body portions of the auxiliary power line 44 , the auxiliary data line 45 and the auxiliary compensation line 46 may be arranged in parallel.
  • the second gate electrode 43 in the first sub-pixel P1 and the fourth sub-pixel P4 may be arranged in mirror symmetry with respect to the auxiliary compensation line 46, and the second gate electrode 43 in the second sub-pixel P2 and the third sub-pixel P3 may be arranged in mirror symmetry with respect to the auxiliary compensation line 46.
  • the second gate electrode 43 may be arranged in mirror symmetry with respect to the auxiliary compensation line 46 .
  • the auxiliary power supply lines 44 in the first sub-pixel P1 and the fourth sub-pixel P4 may be arranged in mirror symmetry with respect to the auxiliary compensation line 46
  • the second scanning signal line 42 may be arranged in mirror symmetry with respect to the auxiliary compensation line 46 set up.
  • this process also includes a conductorization process.
  • the conductive treatment is to perform plasma treatment using the second conductive layer as a shield after forming the second conductive layer pattern.
  • the semiconductor layer blocked by the second conductive layer serves as the channel region of the transistor, and the semiconductor layer not blocked by the second conductive layer
  • the layer is processed into a conductive layer to form a conductive second plate 34 and conductive source and drain regions.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the foregoing pattern is formed, patterning the third insulating film using a patterning process, and forming a pattern covering the second conductive layer.
  • the third insulating layer has a plurality of via holes, as shown in Figure 10.
  • the plurality of via holes at least include: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6,
  • the first via V1 may be disposed in each sub-pixel, and the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate.
  • the third insulating layer and the second insulating layer in the first via hole V1 are etched away, exposing the surface of the first region of the first active layer, the first via hole V1 is configured to enable the subsequently formed data signal
  • the line is connected to the first region of the first active layer through the via hole.
  • the second via hole V2 may be disposed in each sub-pixel, and the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate. , and the orthographic projection of the second via hole V2 on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 43 on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away, The surface of the second region of the first active layer and the surface of the second gate electrode 43 are simultaneously exposed.
  • the second via hole V2 is a transfer via hole.
  • the transfer via hole is composed of two half holes.
  • the second via hole V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to pass through the via hole while being connected to the second gate electrode 43 and the second region of the first active layer.
  • the third via V3 may be disposed in each sub-pixel, and the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate. , the third insulating layer and the second insulating layer in the third via hole V3 are etched away, exposing the surface of the first region of the second active layer, and the third via hole V3 is configured to enable the subsequently formed first The power line is connected to the first area of the second active layer through the via hole.
  • the fourth via hole V4 may be disposed in each sub-pixel.
  • the orthographic projection of the fourth via hole V4 on the substrate is at least the same as the orthographic projection of the second region of the second active layer on the substrate. partially overlap.
  • the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps the orthographic projection of the shielding layer 23 on the substrate.
  • the third insulating layer, the second insulating layer and the third insulating layer in the fourth via hole V4 An insulating layer is etched away, simultaneously exposing the surface of the second region of the second active layer and the surface of the shielding layer 23 , and the fourth via V4 is configured to allow the second electrode of the subsequently formed second transistor T2 to pass through.
  • This via hole is connected to the second area of the second active layer and the shielding layer 23 at the same time.
  • the fifth via hole V5 may be disposed in each sub-pixel.
  • the orthogonal projection of the fifth via hole V5 on the substrate is at least the same as the orthogonal projection of the first region of the third active layer on the substrate. partially overlap.
  • the orthographic projection of the fifth via hole V5 on the substrate and the orthographic projection of the compensation connecting line 22 on the substrate at least partially overlap.
  • the third insulating layer, the second insulating layer and the The first insulating layer is etched away, while exposing the surface of the first region of the third active layer and the surface of the compensation connection line 22, and the fifth via V5 is configured to enable the first conductor of the subsequently formed third transistor T3.
  • the pole is simultaneously connected to the compensation connection line 22 and the first region of the third active layer through the via hole.
  • the sixth via hole V6 may be disposed in each sub-pixel.
  • the orthographic projection of the sixth via hole V6 on the substrate is at least the same as the orthographic projection of the second region of the third active layer on the substrate. partially overlap.
  • the orthographic projection of the sixth via hole V6 on the substrate and the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlap.
  • the third insulating layer and the second insulating layer in the sixth via hole V6 and the first insulating layer is etched away, while exposing the surface of the second region of the third active layer and the surface of the interlayer connection electrode 24, the sixth via V6 is configured to enable the subsequently formed third transistor T3
  • the second electrode is simultaneously connected to the interlayer connection electrode 24 and the second region of the third active layer through the via hole.
  • the seventh via hole V7 may be disposed in the first sub-pixel P1 and the fourth sub-pixel P4, and the orthographic projection of the seventh via hole V7 on the substrate is located on the first end of the power connection line 21 on the substrate.
  • the third insulating layer, the second insulating layer and the first insulating layer in the seventh via hole V7 are etched away, exposing the surface of the first end of the power connection line 21, and the seventh via hole V7
  • the hole V7 is configured to allow a subsequently formed first power line to be connected to the first end of the power connection line 21 through the via hole.
  • the eighth via V8 may be disposed in the second sub-pixel P2 and the third sub-pixel P3, and the orthographic projection of the eighth via V8 on the substrate is located on the second end of the power connection line 21 on the substrate.
  • the third insulating layer, the second insulating layer and the first insulating layer in the eighth via hole V8 are etched away, exposing the surface of the second end of the power connection line 21, and the eighth via hole V8 V8 is configured to connect the first pole of the subsequently formed second transistor T2 to the second end of the power connection line 21 through the via hole.
  • the ninth via V9 may be disposed in the first sub-pixel P1 and the fourth sub-pixel P4, and the orthographic projection of the ninth via V9 on the substrate is located at the orthographic projection of the auxiliary power line 44 on the substrate.
  • the third insulating layer in the ninth via hole V9 is etched away, exposing the surface of the auxiliary power line 44.
  • the ninth via hole V9 is configured to allow the subsequently formed first power line to pass through the via hole and the auxiliary power line 44.
  • the ninth via holes V9 may include multiple ninth via holes V9 , and the plurality of ninth via holes V9 may be arranged sequentially along the second direction Y to increase the connection reliability between the first power line and the auxiliary power line 44 .
  • the tenth via hole V10 may be disposed in each sub-pixel, and the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the auxiliary data line 45 on the substrate.
  • the third insulating layer in V10 is etched away, exposing the surface of the auxiliary data line 45 , and the tenth via hole V10 is configured so that the subsequently formed data signal line is connected to the auxiliary data line 45 through the via hole.
  • the tenth via holes V10 may include multiple tenth via holes V10 , and the plurality of tenth via holes V10 may be arranged sequentially along the second direction Y to increase the connection reliability between the data signal line and the auxiliary data line 45 .
  • the eleventh via hole V11 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, and the orthographic projection of the eleventh via hole V11 on the substrate is located on the auxiliary compensation line 46 on the substrate. Within the orthographic projection range of The auxiliary compensation line 46 is connected through this via hole.
  • the eleventh via holes V11 may include multiple eleventh via holes V11 , and the plurality of eleventh via holes V11 may be arranged sequentially along the second direction Y to increase the connection reliability of the compensation signal line and the auxiliary compensation line 46 .
  • the thirteenth via hole V13 and the fourteenth via hole V14 may be disposed in the first sub-pixel P1, and the orthographic projection of the thirteenth via hole V13 on the substrate may be located on one side of the first fracture K1
  • the orthographic projection of the fourteenth via hole V14 on the substrate may be located at the orthogonal projection of the first scanning signal line 41 on the other side of the first break K1 on the substrate.
  • the third insulating layer in the thirteenth via hole V13 and the fourteenth via hole V14 is etched away, respectively exposing the surfaces of the first scanning signal line 41 on both sides of the first fracture K1.
  • the thirteenth via hole V13 and the fourteenth via hole V14 are configured so that the first signal connection electrode formed later is connected to the first scanning signal line 41 through the via hole.
  • the fifteenth via hole V15 may be disposed in the second sub-pixel P2, the sixteenth via hole V16 may be disposed in the third sub-pixel P3, and the orthographic projection of the fifteenth via hole V15 on the substrate may be
  • the second scanning signal line 42 located on one side of the second break K2 is within the range of the orthographic projection on the substrate, and the orthographic projection of the sixteenth via V16 on the substrate can be located on the second scan on the other side of the second break K2
  • the third insulating layer in the fifteenth via hole V15 and the sixteenth via hole V16 is etched away, respectively exposing the second insulating layer on both sides of the second fracture K2.
  • the fifteenth via hole V15 and the sixteenth via hole V16 are configured so that a subsequently formed second signal connection electrode is connected to the second scanning signal line 42 through the via hole.
  • the seventeenth via hole V17 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, and the orthographic projection of the seventeenth via hole V17 on the substrate may be located on the first side of the compensation connection electrode 83 One end is within the range of the orthographic projection on the substrate, and the third insulating layer, the second insulating layer and the first insulating layer in the seventeenth via hole V17 are etched away, exposing the first end of the compensation connection electrode 83
  • the seventeenth via hole V17 is configured to allow a subsequently formed compensation signal line to be connected to the first end of the compensation connection electrode 83 through the via hole.
  • the eighteenth via hole V18 may be disposed between the second sub-pixel P2 and the third sub-pixel P3, and the orthographic projection of the eighteenth via hole V18 on the substrate may be located on the first side of the compensation connection electrode 83 Within the range of the orthographic projection of the two ends on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the eighteenth via hole V18 are etched away, exposing the second end of the compensation connection electrode 83 On the surface, the eighteenth via hole V18 is configured to allow a subsequently formed compensation signal line to be connected to the second end of the compensation connection electrode 83 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the foregoing pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive film disposed on the third insulating layer.
  • the third conductive layer is as shown in Figures 11a and 11b.
  • Figure 11b is a schematic plan view of the third conductive layer in Figure 11a.
  • the third conductive layer may be referred to as a source-drain metal (SD) layer.
  • SD source-drain metal
  • the third conductive layer pattern in each pixel unit at least includes: a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a fourth connection electrode 54 , and a fifth connection electrode 55 , the sixth connection electrode 56, the first power supply line 60, the data signal line 70, the compensation signal line 80, the first signal connection electrode 91 and the second signal connection electrode 92.
  • the first power supply line 60 may be provided at the first sub-pixel P1 and the fourth sub-pixel P4 respectively, and the shape of the first power supply line 60 may be a line shape in which the main body portion extends along the second direction Y.
  • the first power line 60 is connected to the first area of the second active layer through the third via V3 to write the power signal into the second transistor T2.
  • the first power line 60 passes through the seventh via V3.
  • the hole V7 is connected to the first end of the power connection line 21.
  • the first power line 60 transmits the power signal to the power connection line 21, so that the power connection line 21 can transmit the power signal to the second sub-pixel P2 and the third sub-pixel respectively.
  • the first power line 60 is connected to the auxiliary power line 44 through a plurality of ninth vias V9, so that the first power line 60 and the auxiliary power line 44 form a double-layer wiring.
  • the first power line 60 may be a straight line or a polyline of equal width, or a straight line or a polyline of unequal width. Using a straight line or a polyline of variable width not only facilitates the layout of the pixel structure, but also reduces the cost. parasitic capacitance.
  • the data signal line 70 is provided in each sub-pixel respectively, and the shape of the data signal line 70 may be a line shape in which the main body part extends along the second direction Y.
  • the data signal line 70 is connected to the first area of the first active layer through the first via V1 to write the data signal into the first transistor T1.
  • the data signal line 70 passes through a plurality of tenth vias.
  • the hole V10 is connected to the auxiliary data line 45, so that the data signal line 70 and the auxiliary data line 45 form a double-layer wiring.
  • the data signal lines 70 may be straight lines or polygonal lines of equal width, or straight lines or polygonal lines of non-equal width. Using straight lines or polygonal lines with variable widths not only facilitates the layout of the pixel structure, but also reduces the cost. parasitic capacitance.
  • the compensation signal line is disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the compensation signal line may include first compensation signals respectively disposed on both sides of the second signal connection electrode 92 in the second direction Y.
  • the shape of the line 81 and the second compensation signal line 82, the first compensation signal line 81 and the second compensation signal line 82 may be a strip shape with the main part extending along the second direction Y, forming spaced compensation signal lines.
  • the first compensation signal line 81 is connected to the first end of the compensation connection electrode 83 through the seventeenth via hole V17
  • the second compensation signal line 82 is connected to the first end of the compensation connection electrode 83 through the eighteenth via hole V18.
  • the second end is connected such that the first compensation signal line 81 and the second compensation signal line 82 on both sides of the second signal connection electrode 92 are connected to each other through the compensation connection electrode 83 .
  • the second compensation signal line 82 may also be connected to the auxiliary compensation line 46 through a plurality of eleventh vias V11 , so that the second compensation signal line 82 and the auxiliary compensation line 46 form a double-layer wiring.
  • the first compensation signal line 81 and the second compensation signal line 82 may be straight lines or polygonal lines of equal width, or straight lines or polygonal lines of non-equal width. Using straight lines or polygonal lines with variable widths, not only can It facilitates the layout of the pixel structure and can reduce parasitic capacitance.
  • the shape of the first connection electrode 51 may be a rectangular shape, and may be provided in each sub-pixel respectively.
  • the first connection electrode 51 in each sub-pixel is connected to the first active electrode 51 through the second via hole V2 at the same time.
  • the second region of the layer is connected to the second gate electrode.
  • the first connection electrode 51 may serve as the second electrode of the first transistor T1. Since the second region of the first active layer is connected to the second plate 34, the first connection electrode 51 enables the first The second electrode of the transistor T1, the second gate electrode 43 and the second plate 34 have the same potential, that is, the potential of the first node N1 in the pixel driving circuit.
  • the shape of the second connection electrode 52 may be a rectangular shape, and may be respectively provided in each sub-pixel.
  • the second connection electrode 52 in each sub-pixel is connected to the second active electrode 52 through the fourth via hole V4 at the same time.
  • the second area of the layer is connected to the occlusion layer 23 .
  • the second connection electrode 52 may serve as the second electrode of the second transistor T2. Since the shielding layer 23 is connected to the connection plate 12 and the connection plate 12 is connected to the first plate 11, the second connection electrode 52 Therefore, the second electrode of the second transistor T2 and the first electrode plate 11 have the same potential.
  • the third connection electrode 53 may be in a rectangular shape and may be provided in each sub-pixel respectively.
  • the third connection electrode 53 in each sub-pixel is connected to the third active electrode through the sixth via V6 at the same time.
  • the second region of the layer is connected to the interlayer connecting electrode.
  • the third connection electrode 53 may serve as the second electrode of the third transistor T3. Since the interlayer connection electrode 24 is connected to the connection line 13 and the connection line 13 is connected to the first plate 11, the third connection The electrode 53 causes the second electrode of the third transistor T3 and the first plate 11 to have the same potential.
  • the third connection electrode 53 makes the first plate 11 and the third transistor T3 have the same potential.
  • the second pole has the same potential, so the second pole of the second transistor T2, the second pole of the third transistor T3 and the first plate 11 have the same potential, that is, the potential of the second node N2 in the pixel driving circuit.
  • the shape of the fourth connection electrode 54 may be a rectangle, and may be provided in each sub-pixel respectively.
  • the fourth connection electrode 54 in each sub-pixel is connected to the fifth via hole V5 of the sub-pixel at the same time.
  • the first area of the third active layer is connected to the compensation connection line 22 .
  • the fourth connection electrode 54 may serve as the first pole of the third transistor T3. Since the compensation connection line 22 is connected to the first compensation signal line 81, the fourth connection electrode 54 may write the compensation signal into each The first pole of the third transistor T3 of the sub-pixel.
  • the shape of the fifth connection electrode 55 may be a strip shape extending along the first direction X, and may be provided in the second sub-pixel P2 and the third sub-pixel P3 respectively.
  • the first end is connected to the first compensation signal line 81
  • the second end of the fifth connection electrode 55 extends to the second sub-pixel P2 along the opposite direction of the first direction X or extends to the third sub-pixel along the first direction X.
  • P3 is connected to the fourth connection electrode 54 of the sub-pixel.
  • the fifth connection electrode 55 may serve as an auxiliary connection line.
  • the fourth connection electrode 54 is connected to the fifth connection electrode 55 , and the compensation connection line 22 is connected to the first compensation signal line 81 .
  • the fourth connection electrode 54 is connected, thus realizing the connection between the compensation connection line 22 and the first compensation signal line 81 , and the first compensation signal line 81 transmits the compensation signal to the compensation connection line 22 .
  • the first compensation signal line 81 , the fourth connection electrode 54 and the fifth connection electrode 55 in the second sub-pixel P2 and the third sub-pixel P3 may be an integral structure connected to each other.
  • the shape of the sixth connection electrode 56 may be a strip shape extending along the second direction Y, and may be provided in the second sub-pixel P2 and the third sub-pixel P3 respectively.
  • the first end is connected to the power connection line 21 through the eighth via hole V8, and the second end of the sixth connection electrode 56 is connected to the first region of the second active layer through the third via hole V3 of the sub-pixel.
  • the sixth connection electrode 56 may serve as the first pole of the second transistor T2. Since the power connection line 21 is connected to the first power line 60, the sixth connection electrode 56 may write the power signal into the second transistor T2.
  • the shape of the first signal connection electrode 91 may be a strip shape extending along the first direction
  • the thirteenth via hole V13 is connected to the first scanning signal line 41 located on one side of the first break K1, and the second end of the first signal connection electrode 91 is connected to the third scan signal line 41 located on the other side of the first break K1 through the fourteenth via hole V14.
  • a scanning signal line 41 is connected, so that the first scanning signal lines 41 on both sides of the first break K1 are connected to each other through the first signal connection electrode 91 .
  • the first signal connection electrode 92 may have a first length L1 and the first power line 60 may have a width M.
  • the first length L1 may be the size of the first signal connection electrode 91 in the first direction X, that is, the size of the extension direction of the first signal connection electrode 91 .
  • the width M may be the size of the first power line 60 in the second direction Y, that is, the size perpendicular to the extending direction of the first power line 60 .
  • the width M may be the maximum size of the first power line 60 in the second direction Y, or the width M may be the average size of the first power line 60 in the second direction Y.
  • the first length L1 of the first signal connection electrode 91 may be greater than the width M of the first power line 60 .
  • At least one sub-pixel has a sub-pixel width
  • the sub-pixel width may be a size of the sub-pixel in the first direction X
  • the first length L1 of the first signal connection electrode 91 may be smaller than the sub-pixel width
  • the first length L1 of the first signal connection electrode 91 may be approximately 50% to 80% of the sub-pixel width.
  • the shape of the second signal connection electrode 92 may be a strip shape extending along the first direction X, and may be disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the first end of 92 is connected to the second scanning signal line 42 located on the side of the second break K2 through the fifteenth via V15, and the second end of the second signal connection electrode 92 is connected to the second scanning signal line 42 located on the side of the second break K2 through the sixteenth via V16.
  • the second scanning signal lines 42 on the other side of the break K2 are connected, so that the second scanning signal lines 42 on both sides of the second break K2 are connected to each other through the second signal connection electrode 92 .
  • the second signal connection electrode 92 may be provided with at least one through hole, and the orthographic projection of the through hole on the substrate and the compensation connection electrode 83 are configured to reduce the connection between the second signal connection electrode 92 and the compensation connection.
  • the parasitic capacitance between the electrodes 83 is reduced, that is, the parasitic capacitance between the second scanning signal line and the compensation signal line is reduced.
  • the second signal connection electrode 92 has a second length L2, and the second length L2 may be the size of the second signal connection electrode 92 in the first direction X, that is, the size of the extension direction of the second signal connection electrode 92 .
  • the second length L2 of the second signal connection electrode 92 may be greater than the width M of the first power line 60 .
  • the second length L2 of the second signal connection electrode 92 may be smaller than the sub-pixel width.
  • the second length L2 of the second signal connection electrode 92 may be approximately 50% to 80% of the sub-pixel width.
  • a data signal line 70 extending along the second direction Y is provided in each sub-pixel, and the data signal line 70 is connected to the first transistor T1 of the sub-pixel through a via hole, thereby achieving the respective writing of data signals. into the first pole of the first transistor T1 of the four sub-pixels.
  • Exemplary embodiments of the present disclosure implement writing of power signals respectively by arranging two first power lines 60 extending along the second direction Y and two power connection lines 21 extending along the first direction X in the pixel unit. into the second transistor T2 of four sub-pixels.
  • the first power line 60 is directly connected to the first electrode of the second transistor T2 through via holes respectively.
  • the first power supply line 60 is connected to the first electrode of the second transistor T2 through the sixth connection electrode 56 respectively.
  • Exemplary embodiments of the present disclosure provide a compensation signal line (a first compensation signal line 81 and a second compensation signal line 82 connected through a compensation connection electrode 83 ) whose main body part extends along the second direction Y in the pixel unit and a compensation signal line along the second direction Y.
  • the two compensation connection lines 22 extending in the first direction X enable the compensation signals to be respectively written into the third transistor T3 of the four sub-pixels.
  • the compensation signal line is connected to the first electrode of the third transistor T3 through the fifth connection electrode 55 and the fourth connection electrode 54 respectively.
  • the compensation signal line is connected to the first electrode of the third transistor T3 through the compensation connection line 22 and the fourth connection electrode 54 respectively.
  • This disclosure provides a compensation signal to four sub-pixels by setting up a compensation signal line, which can ensure that the RC delay of the compensation signal is basically the same before being written into the transistor, thereby ensuring display uniformity.
  • Exemplary embodiments of the present disclosure provide at least one first break on the first scan signal line, and the first scan signal lines on both sides of the first break are connected to each other through first signal connection electrodes.
  • exemplary embodiments of the present disclosure divide the first scanning signal line into multiple segments, and the first length of the first signal connection electrode is greater than the width of the first power line, which not only effectively reduces.
  • the amount of static electricity generated by scanning signal lines during the dry etching process avoids the breakdown of transistor channels due to static electricity accumulation, effectively avoiding edge dark spots in the display device, and improving the efficiency of the first scan signal while ensuring continuous transmission.
  • the yield rate is improved and the display quality is improved.
  • Exemplary embodiments of the present disclosure provide at least one second break on the second scan signal line, and the second scan signal lines on both sides of the second break are connected to each other through second signal connection electrodes.
  • exemplary embodiments of the present disclosure divide the second scanning signal line into multiple segments, and the second length of the second signal connection electrode is greater than the width of the second power line, which not only effectively reduces During the dry etching process, the amount of static electricity generated by the scanning signal lines is avoided, and the breakdown of the transistor channel caused by static electricity accumulation is effectively avoided, which effectively avoids edge dark spots in the display device.
  • the premise of ensuring the continuous transmission of the second scanning signal it improves the The yield rate is improved and the display quality is improved.
  • Exemplary embodiments of the present disclosure divide the compensation signal line into multiple segments by arranging the second break between the second sub-pixel P2 and the third sub-pixel P3.
  • the compensation signal lines are connected to each other through the compensation connection electrode, effectively reducing the During the dry etching process, the amount of static electricity generated by the signal line is compensated, and the breakdown of the transistor channel caused by static electricity accumulation is avoided, effectively avoiding edge dark spots in the display device, and improving the efficiency while ensuring the continuous transmission of the compensation signal line.
  • the yield rate is improved and the display quality is improved.
  • forming the flat layer pattern may include: coating a flat thin film on the substrate on which the foregoing pattern is formed, patterning the flat thin film using a patterning process, and forming a flat layer pattern covering the third conductive layer. Multiple via holes are opened on the layer, and the multiple via holes include at least the twenty-first via hole V21 located in each sub-pixel, as shown in Figure 12.
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the second connection electrode 52 on the substrate, and the flat layer in the twenty-first via hole V21 is removed. , exposing the surface of the second connection electrode 52 , and the twenty-first via hole V21 is configured so that the subsequently formed anode is connected to the second connection electrode 52 through the via hole.
  • the display substrate may include a fourth insulating layer and a color filter layer.
  • the fourth insulating layer is first formed, and then the color filter layer is formed on the fourth insulating layer, and then the color filter layer is coated.
  • Cover the flat film and use a patterning process to pattern the flat film and the fourth insulating film to form a fourth insulating layer covering the third conductive layer, a color filter layer disposed on the fourth insulating layer, and a flat film covering the color filter layer.
  • Layer pattern, multiple via holes are opened on the flat layer and the fourth insulating layer.
  • forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the foregoing pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer disposed on the flat layer. Pattern, the anode conductive layer pattern at least includes an anode 301 located in each sub-pixel, as shown in FIG. 13 .
  • the anode conductive layer pattern may include a red anode located in the first sub-pixel P1, a white anode located in the second sub-pixel P2, a blue anode located in the third sub-pixel P3 and a fourth sub-pixel P1.
  • the green anode in sub-pixel P4 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 serves as the second pole of the second transistor T2, the connection between the anode 301 and the second pole of the second transistor T2 is achieved.
  • the anode 301 may be in a strip shape extending along the second direction Y, and a protrusion is provided on one side of the anode in the second direction Y in each sub-pixel, and the protrusion passes through the twenty-first pass.
  • the hole V21 is connected to the second connection electrode 52 .
  • the orthographic projection of the anode in each sub-pixel on the substrate includes the orthographic projection of the storage capacitor in the sub-pixel on the substrate.
  • forming the pixel definition layer pattern may include: coating a pixel definition film on the substrate on which the foregoing pattern is formed, patterning the pixel definition film using a patterning process, and forming a pixel definition layer pattern, the pixel definition layer pattern It includes at least a pixel opening 302K located in each sub-pixel, as shown in FIG. 14 .
  • the shapes and areas of the pixel openings 302K of different sub-pixels may be different.
  • Exemplary embodiments of the present disclosure can adapt to the transmittance of different sub-pixel color film layers by designing four sub-pixels with different aperture ratios, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, maximizing optimization It extends the life of the four sub-pixel light-emitting devices and ensures product life.
  • the shapes of the pixel openings of the four sub-pixels may be the same or different, and the areas of the pixel openings of the four sub-pixels may be the same or different.
  • the shape of the pixel opening may include any one or more of the following: triangle, rectangle, trapezoid, parallelogram, five-frame, six-frame, circle, and oval.
  • the orthographic projection of the pixel opening 302K in each sub-pixel on the substrate at least partially overlaps the orthographic projection of the storage capacitor in the sub-pixel on the substrate.
  • the orthographic projection of the storage capacitor in each sub-pixel on the substrate may be located within the range of the orthographic projection of the pixel opening 302K in the corresponding sub-pixel on the substrate.
  • the subsequent preparation process may include: using an evaporation or inkjet printing process to form an organic light-emitting layer, the organic light-emitting layer is connected to the anode through the pixel opening, forming a cathode on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer. .
  • Form an encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may use inorganic materials
  • the second encapsulation layer may use organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the driving circuit layer may include a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, and a third layer sequentially stacked on the substrate. Insulating layer, third conductive layer and planar layer.
  • the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may be, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, and polyether ether ketone. , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, the first flexible material layer and the second flexible material layer.
  • the material of the material layer can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film.
  • PI polyimide
  • PET polyethylene terephthalate
  • the materials of the first inorganic material layer and the second inorganic material layer Silicon nitride (SiNx) or silicon oxide (SiOx) can be used to improve the water and oxygen resistance of the substrate.
  • the material of the semiconductor layer can be amorphous silicon (a-si).
  • the transparent conductive layer and the anode conductive layer may use transparent conductive materials, such as indium tin oxide ITO or indium zinc oxide IZO.
  • the first conductive layer, the second conductive layer and the third conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above Metal alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can have a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the first insulating layer, the second insulating layer and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, Multiple or composite layers.
  • the first insulating layer is called a buffer layer
  • the second insulating layer is called a gate insulating (GI) layer
  • the third insulating layer is called an interlayer insulating (ILD) layer.
  • the flat layer can be made of organic materials, such as resin
  • the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate.
  • the display substrate provided by exemplary embodiments of the present disclosure may include:
  • a first conductive layer provided on the transparent conductive layer.
  • the first conductive layer at least includes a power connection line 21, a compensation connection line 22, a shielding layer 23 and a compensation connection electrode 83.
  • the shielding layer 23 is connected to the first plate 11;
  • the semiconductor layer at least includes a first active layer 31, a second active layer 32, a third active layer 33 and a second electrode plate 34.
  • the first active layer 31 and the The two-pole plates 34 can be an integrated structure connected to each other, and the second pole plate 34 and the first pole plate 11 form a transparent storage capacitor;
  • a second conductive layer is provided on the second insulating layer.
  • the second conductive layer at least includes a first scanning signal line 41, a second scanning signal line 42 and a second gate electrode 43.
  • the first scanning signal line 41 is provided with at least one The first break K1, and at least one second break K2 is provided on the second scanning signal line 42;
  • a third insulating layer covering the second conductive layer, with a plurality of via holes provided in the third insulating layer
  • a third conductive layer is provided on the third insulating layer.
  • the third conductive layer at least includes a first power supply line 60, a data signal line 70, a first compensation signal line 81 and a second compensation signal line 81 of the compensation signal line, a first
  • the first signal connection electrode 91 and the second signal connection electrode 92 are connected to the first scanning signal lines 41 on both sides of the first break K1, and the second signal connection electrode 92 is connected to the second scanning signal lines 41 on both sides of the second break K2.
  • the signal line 42, the first compensation signal line 81 and the second compensation signal line 81 are connected to each other through the compensation connection electrode 83;
  • the flat layer covering the third conductive layer has a plurality of via holes on it;
  • the pixel definition layer has a pixel opening 302K exposing the anode 301 thereon.
  • Exemplary embodiments of the present disclosure provide a display substrate that divides a scanning signal line into multiple segments. At least one first break is provided on the first scanning signal line, and the first scanning signal lines on both sides of the first break are connected through the first signal.
  • the electrodes are connected to each other, at least one second break is provided on the second scan signal line, and the second scan signal lines on both sides of the second break are connected to each other through the second signal connection electrodes, which not only effectively reduces the scan signal during the dry etching process.
  • the amount of static electricity generated by wires is eliminated, and the breakdown of the transistor channel caused by static electricity accumulation is effectively avoided, which effectively avoids edge dark spots in the display device. It improves the yield rate and display quality while ensuring the continuous transmission of scanning signals. .
  • Exemplary embodiments of the present disclosure display substrates by using transparent storage capacitors.
  • the storage capacitors are composed of a transparent transparent conductive layer and a transparent semiconductor layer. Since light can emit through the transparent storage capacitor, the storage capacitor can be disposed in the pixel opening, effectively The capacitance of the storage capacitor is increased, effectively increasing the pixel aperture ratio.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment. It has little improvement to the existing process and can be well compatible with the existing preparation process. The process is simple to realize, easy to implement, has high production efficiency and low production cost. The yield rate is high.
  • FIG. 15 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a driving circuit layer of a pixel unit (four sub-pixels) in a bottom-emission display substrate.
  • the main structure of the display substrate of this embodiment is basically the same as that of the previous embodiment. The difference is that the first break K1 provided on the first scanning signal line 41 is connected through the first signal. The electrodes 91 are connected, and the second break K2 on the second scanning signal line 42 is connected through the third signal connection electrode 93 , the fourth signal connection electrode 94 and the fifth signal connection electrode 95 .
  • the structures of the first scanning signal line 41, the first break K1, and the first signal connection electrode 91 may be substantially the same as in the previous embodiment.
  • the second scan signal line 42 is provided with a second break K2 that cuts off the second scan signal line 42.
  • the second break K2 may be disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the four signal connection electrodes 94 may be provided in the second sub-pixel P2, the fifth signal connection electrode 95 may be provided in the third sub-pixel P3, and the first end of the third signal connection electrode 93 is connected to the fourth signal connection electrode through a via hole on the one hand.
  • 94 is connected, on the other hand, it is connected to the second scanning signal line 42 on the side of the second sub-pixel P2 of the second break K2 through a via hole.
  • the second end of the third signal connection electrode 93 is connected to the fifth signal through a via hole.
  • the electrode 95 is connected, and on the other hand, is connected to the second scanning signal line 42 on the third sub-pixel P3 side of the second break K2 through a via hole, so that the second scanning signal line 42 on both sides of the second break K2 is connected through the fourth signal.
  • the electrode 94, the third signal connection electrode 93 and the fifth signal connection electrode 95 are connected to realize the continuous transmission of the second scanning signal line 42.
  • the fourth signal connection electrode 94 and the fifth signal connection electrode 95 may be arranged in the same layer as the first power supply line 60 , and the first scanning signal line 41 and the second scanning signal line 42 may be arranged in the same layer as the first power supply line 60 . 60 different layer settings.
  • the third signal connection electrode 93 has a third length L3, and the third length L2 may be greater than the width M of the first power line 60.
  • the third length L3 of the third signal connection electrode 93 may be smaller than the sub-pixel width.
  • the third length L3 of the third signal connection electrode 93 may be approximately 50% to 80% of the sub-pixel width.
  • the orthographic projection of the third signal connection electrode 93 on the display substrate does not overlap with the orthographic projection of the first power line 60 and the data signal line 70 on the display substrate.
  • the compensation signal line 80 may be in a continuously arranged line shape, and the orthographic projection of the compensation signal line 80 on the display substrate at least partially overlaps the orthographic projection of the third signal connection electrode 93 on the display substrate.
  • the third signal connection electrode 93 is provided with at least one through hole, and the orthographic projection of the through hole on the display substrate at least partially overlaps the orthographic projection of the compensation signal line 80 on the display substrate.
  • the display substrate in a direction perpendicular to the display substrate, may include a transparent conductive layer, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, and a second insulating layer stacked on a substrate. a conductive layer, a third insulating layer and a third conductive layer.
  • the transparent conductive layer may include at least the first plate of the storage capacitor.
  • the first conductive layer may include at least the power connection line 21, the compensation connection line 22, the shielding layer 23 and the third signal connection electrode 93.
  • the semiconductor layer may include at least the third plate of the storage capacitor.
  • the diode plate and the active layer of the three transistors, the second conductive layer may include at least the first scanning signal line 41, the second scanning signal line 42 and the gate electrodes of the three transistors, and the third conductive layer may include at least the first power supply line 60, data signal line 70, compensation signal line 80, first and second poles of three transistors, first signal connection electrode 91, fourth signal connection electrode 94 and fifth signal connection electrode 95.
  • this exemplary embodiment shows that the preparation process of the substrate may include the following operations.
  • Form a transparent conductive layer pattern In exemplary embodiments, forming the transparent conductive layer pattern may be substantially the same as step (11) of the previous embodiment, and the formed transparent conductive layer structure may be substantially the same as that of the previous embodiment.
  • first conductive layer pattern Form a first conductive layer pattern.
  • forming the first conductive layer pattern may be basically the same as step (12) of the previous embodiment.
  • the formed first conductive layer pattern may include at least a power connection line 21, a compensation connection line 22, and a shielding layer 23. , interlayer connection electrode 24 and third signal connection electrode 93, as shown in Figure 16.
  • the structures of the power supply connection lines 21 , the compensation connection lines 22 , the shielding layer 23 and the interlayer connection electrodes 24 are basically the same as those in the previous embodiments, and will not be described again here.
  • the shape of the third signal connection electrode 93 may be a strip shape extending along the first direction X, and may be disposed between the second sub-pixel P2 and the third sub-pixel P3. 93 is configured to connect the second scanning signal lines on both sides of the subsequently formed second break through the subsequently formed fourth signal connection electrode and fifth signal connection electrode.
  • the third signal connection electrode 93 may be provided with at least one through hole, and the orthographic projection of the through hole on the substrate at least partially overlaps the orthographic projection of the subsequently formed compensation signal line on the substrate to reduce the risk of the third signal connection electrode 93 .
  • the third signal connection electrode 93 has a third length L3, and the third length L3 may be the size of the third signal connection electrode 93 in the first direction X, that is, the size of the extension direction of the third signal connection electrode 93 .
  • the third length L3 of the third signal connection electrode 93 may be greater than the width of the subsequently formed first power line 60 .
  • the third length L3 of the third signal connection electrode 93 may be smaller than the sub-pixel width.
  • the third length L3 of the third signal connection electrode 93 may be approximately 50% to 80% of the sub-pixel width.
  • Form a semiconductor layer pattern may be substantially the same as step (13) of the previous embodiment, and the formed semiconductor layer structure may be substantially the same as that of the previous embodiment, as shown in FIG. 17 .
  • forming the second conductive layer pattern may be basically the same as step (14) of the previous embodiment, and the formed second conductive layer structure is basically the same as the second conductive layer structure of the previous embodiment, as shown in FIG. Shown in 18.
  • forming the third insulating layer pattern may be basically the same as step (15) of the previous embodiment.
  • the plurality of via holes formed at least include: first via hole V1 to eleventh via hole V11, The thirteenth via hole V13 to the eighteenth via hole V18 are shown in Figure 19.
  • the first to eleventh via holes V1 to V11 and the thirteenth to fourteenth via holes V13 to V14 are substantially the same as the via holes of the previous embodiment.
  • the fifteenth via hole V15 and the seventeenth via hole V17 may be provided in the second sub-pixel P2.
  • the orthographic projection of the fifteenth via hole V15 on the substrate can be located within the range of the orthographic projection of the second scanning signal line 42 on the side of the second break K2 on the substrate, and the third insulating layer in the fifteenth via hole V15 is etched away, exposing the surface of the second scanning signal line 42 on the side of the second fracture K2.
  • the orthographic projection of the seventeenth via hole V17 on the substrate may be located within the range of the orthographic projection of the third signal connection electrode 93 on the substrate.
  • the third insulating layer, the second insulating layer and the third insulating layer in the seventeenth via hole V17 An insulating layer is etched away, exposing the surface of the third signal connection electrode 93 .
  • the fifteenth via hole V15 and the seventeenth via hole V17 are configured to allow the subsequently formed fourth signal connection electrode to pass through the via holes to communicate with the third signal connection electrode 93 and the second scanning signal line on the side of the second break K2 respectively. 42 connections.
  • the sixteenth via hole V16 and the eighteenth via hole V18 may be provided in the third sub-pixel P3.
  • the orthographic projection of the sixteenth via hole V16 on the substrate may be located within the range of the orthographic projection of the second scanning signal line 42 on the other side of the second break K2, and the third insulation in the sixteenth via hole V16
  • the layer is etched away, exposing the surface of the second scanning signal line 42 on the other side of the second break K2.
  • the orthographic projection of the eighteenth via hole V18 on the substrate may be located within the range of the orthographic projection of the third signal connection electrode 93 on the substrate.
  • the third insulating layer, the second insulating layer and the third insulating layer in the eighteenth via hole V18 An insulating layer is etched away, exposing the surface of the third signal connection electrode 93 .
  • the sixteenth via hole V16 and the eighteenth via hole V18 are configured to allow the subsequently formed fifth signal connection electrode to pass through the via hole to communicate with the third signal connection electrode 93 and the second scan signal on the other side of the second break K2 respectively. Wire 42 connection.
  • the formed third conductive layer structure at least includes: a first connection electrode 51, a second connection electrode 52, a third Connection electrode 53, fourth connection electrode 54, fifth connection electrode 55, sixth connection electrode 56, first power supply line 60, data signal line 70, first signal connection electrode 91, fourth signal connection electrode 94 and fifth signal Connect electrode 95 as shown in Figure 20.
  • the structures of the first to sixth connection electrodes 51 to 56 , the first power supply line 60 , the data signal line 70 , the compensation signal line 80 and the first signal connection electrode 91 are basically the same as those in the previous embodiment. , we won’t go into details here.
  • the fourth signal connection electrode 94 may be disposed in the second sub-pixel P2, the fifth signal connection electrode 95 may be disposed in the third sub-pixel P3, the fourth signal connection electrode 94 and the fifth signal connection electrode 94 may be disposed in the third sub-pixel P3.
  • the shape of the electrode 95 may be a rectangular shape.
  • the fourth signal connection electrode 94 is connected to the second scanning signal line 42 on the side of the second break K2 through the fifteenth via hole V15, and on the other hand, it is connected to the third signal connection electrode 93 through the seventeenth via hole V17.
  • the second scanning signal line 42 and the third signal connection electrode 93 on the side of the second break K2 are connected through the fourth signal connection electrode 94 .
  • the fifth signal connection electrode 95 is connected to the second scanning signal line 42 on the other side of the second break K2 through the sixteenth via hole V16, and on the other hand, it is connected to the third signal connection electrode 93 through the eighteenth via hole V18. , so that the second scanning signal line 42 and the third signal connection electrode 93 on the other side of the second break K2 are connected through the fifth signal connection electrode 95 . In this way, the second scanning signal lines 42 on both sides of the second break K2 are connected through the fourth signal connection electrode 94 , the third signal connection electrode 93 and the fifth signal connection electrode 95 .
  • the compensation signal line 80 is disposed between the second sub-pixel P2 and the third sub-pixel P3.
  • the shape of the compensation signal line 80 may be a strip shape with a main body portion extending along the second direction Y.
  • the compensation signal line 80 may be in a strip shape.
  • Line 80 is a continuous structure.
  • the orthographic projection of the compensation signal line 80 on the substrate at least partially overlaps the orthographic projection of the third signal connection electrode 93 on the substrate, and the orthographic projection of the compensation signal line 80 on the substrate overlaps with the fourth signal connection electrode 93 .
  • the orthographic projection of 94 on the substrate does not overlap, and the orthographic projection of the compensation signal line 80 on the substrate does not overlap with the orthographic projection of the fifth signal connection electrode 95 on the substrate.
  • Form flat layer, anode conductive layer, pixel definition layer, organic light-emitting layer, cathode and packaging structure layer patterns may be basically the same as in the previous embodiments, and will not be described again here.
  • the display substrate provided by exemplary embodiments of the present disclosure may include:
  • a first conductive layer provided on the transparent conductive layer.
  • the first conductive layer at least includes a power connection line 21, a compensation connection line 22, a shielding layer 23 and a third signal connection electrode 93.
  • the shielding layer 23 is connected to the first plate 11;
  • the semiconductor layer at least includes a first active layer 31, a second active layer 32, a third active layer 33 and a second electrode plate 34.
  • the first active layer 31 and the The two-pole plates 34 can be an integrated structure connected to each other, and the second pole plate 34 and the first pole plate 11 form a transparent storage capacitor;
  • a second conductive layer is provided on the second insulating layer.
  • the second conductive layer at least includes a first scanning signal line 41, a second scanning signal line 42 and a second gate electrode 43.
  • the first scanning signal line 41 is provided with at least one The first break K1, and at least one second break K2 is provided on the second scanning signal line 42;
  • a third insulating layer covering the second conductive layer, with a plurality of via holes provided in the third insulating layer
  • a third conductive layer is provided on the third insulating layer.
  • the third conductive layer at least includes a first power supply line 60, a data signal line 70, a first compensation signal line 81 and a second compensation signal line 81 of the compensation signal line, a first The signal connection electrode 91, the fourth signal connection electrode 94 and the fifth signal connection electrode 95, the first signal connection electrode 91 is connected to the first scanning signal lines 41 on both sides of the first break K1, and the second scan signal lines 41 on both sides of the second break K2
  • the signal lines 42 are connected to each other through the fourth signal connection electrode 94, the third signal connection electrode 93 and the fifth signal connection electrode 95;
  • the flat layer covering the third conductive layer has a plurality of via holes on it;
  • the pixel definition layer has a pixel opening exposing the anode 301 thereon.
  • Exemplary embodiments of the present disclosure provide another display substrate that divides a scanning signal line into multiple segments. At least one first break is provided on the first scanning signal line, and the first scanning signal lines on both sides of the first break pass through the first signal line.
  • the connection electrodes are connected to each other, and at least one second break is provided on the second scan signal line.
  • the second scan signal lines on both sides of the second break are connected through the fourth signal connection electrode 94, the third signal connection electrode 93 and the fifth signal connection electrode.
  • the electrodes 95 are connected to each other, which not only effectively reduces the amount of static electricity generated by the scanning signal lines during the dry etching process, but also avoids breakdown of the transistor channel due to static electricity accumulation, effectively avoiding edge dark spots in the display device, and ensuring scanning Under the premise of continuous signal transmission, the yield rate and display quality are improved.
  • the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc., this disclosure is not limited here.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display ( QDLED), etc.
  • Exemplary embodiments of the present disclosure also provide a method of manufacturing a display substrate, which may include multiple sub-pixels; the manufacturing method may include:
  • a pixel driving circuit is formed in at least one sub-pixel, the pixel driving circuit is respectively connected to a scanning signal line extending along a first direction and a first power supply line extending along a second direction, and the scanning signal line is configured to A scanning signal is provided to the pixel driving circuit, the first power supply line is configured to provide a power signal to the pixel driving circuit, the first direction intersects the second direction; the scanning signal line is provided with at least A break that cuts off the scanning signal line.
  • the scanning signal lines on both sides of the break are connected to each other through signal connection electrodes. The length of the signal connection electrode is greater than the width of the first power line.
  • the length of the signal connection electrode is Less than the sub-pixel width, the length is the size of the signal connection electrode in the first direction, the width is the size of the first power line in the first direction, and the sub-pixel width is the sub-pixel width.
  • the size of the first direction X is Less than the sub-pixel width, the length is the size of the signal connection electrode in the first direction, the width is the size of the first power line in the first direction, and the sub-pixel width is the sub-pixel width.
  • the present disclosure also provides a display device, including the display substrate of the aforementioned embodiment.
  • the display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame, a navigator, or any other product or component with a display function.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括多个子像素，至少一个子像素包括像素驱动电路，像素驱动电路分别与扫描信号线(41，42)和第一电源线(60)连接；至少一个子像素中，扫描信号线(41，42)设置有至少一个断口(K1，K2)，断口(K1，K2)两侧的扫描信号线(41，42)通过信号连接电极(91，92)相互连接，信号连接电极(91，92)的长度大于第一电源线(60)的宽度，信号连接电极(91，92)的长度小于子像素宽度。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路分别与沿着第一方向延伸的扫描信号线和沿着第二方向延伸的第一电源线连接，所述扫描信号线被配置为向所述像素驱动电路提供扫描信号，所述第一电源线被配置为向所述像素驱动电路提供电源信号，所述第一方向与所述第二方向交叉；至少一个子像素中，所述扫描信号线设置有至少一个截断所述扫描信号线的断口，所述断口两侧的扫描信号线通过信号连接电极相互连接，所述信号连接电极的长度大于所述第一电源线的宽度，所述信号连接电极的长度小于子像素宽度，所述长度为所述信号连接电极所述第一方向的尺寸，所述宽度为所述第一电源线所述第一方向的尺寸，子像素宽度为所述子像素所述第一方向X的尺寸。
在示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第 一扫描信号的第一扫描信号线，所述断口包括截断所述第一扫描信号线的第一断口，所述信号连接电极包括第一信号连接电极，所述第一信号连接电极的第一端通过过孔与所述第一断口一侧的所述第一扫描信号线连接，所述第一信号连接电极的第二端通过过孔与所述第一断口另一侧的所述第一扫描信号线连接，所述第一信号连接电极的长度大于所述第一电源线的宽度，所述第一信号连接电极的长度小于子像素宽度。
在示例性实施方式中，所述多个子像素包括沿着所述第一方向依次设置的第一子像素、第二子像素、第三子像素和第四子像素，所述第一断口和第一信号连接电极设置在所述第一子像素内，或者，所述第一断口和第一信号连接电极设置在所述第二子像素内，或者，所述第一断口和第一信号连接电极设置在所述第三子像素内，或者，所述第一断口和第一信号连接电极设置在所述第四子像素内。
在示例性实施方式中，在垂直于显示基板的平面上，所述显示基板包括多个导电层，所述第一信号连接电极和所述第一电源线设置在相同的导电层中，所述第一扫描信号线和所述第一电源线设置在不同的导电层中。
在示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第二扫描信号线的第二断口，所述信号连接电极包括第二信号连接电极，所述第二信号连接电极的第一端通过过孔与所述第二断口一侧的所述第二扫描信号线连接，所述第二信号连接电极的第二端通过过孔与所述第二断口另一侧的所述第二扫描信号线连接，所述第二信号连接电极的长度大于所述第一电源线的宽度，所述第二信号连接电极的长度小于所述子像素宽度。
在示例性实施方式中，在垂直于显示基板的平面上，所述显示基板包括多个导电层，所述第二信号连接电极和所述第一电源线设置在相同的导电层中，所述第二扫描信号线和所述第一电源线设置在不同的导电层中。
在示例性实施方式中，所述像素驱动电路还与补偿信号线连接，所述补偿信号线被配置为向所述像素驱动电路提供补偿信号；至少一个子像素中，所述补偿信号线至少包括补偿连接电极以及间隔设置的第一补偿信号线和第二补偿信号线，所述补偿连接电极的第一端通过过孔与所述第一补偿信号线 连接，所述补偿连接电极的第二端通过过孔与所述第二补偿信号线连接。
在示例性实施方式中，所述补偿连接电极在显示基板上的正投影与所述第二断口在显示基板上的正投影至少部分交叠。
在示例性实施方式中，所述补偿连接电极在显示基板上的正投影与所述第二信号连接电极在显示基板上的正投影至少部分交叠。
在示例性实施方式中，所述第二信号连接电极上设置有至少一个通孔，所述通孔在显示基板上的正投影与所述补偿连接电极在显示基板上的正投影至少部分重叠。
在示例性实施方式中，所述多个子像素包括沿着所述第一方向依次设置的第一子像素、第二子像素、第三子像素和第四子像素，所述第一补偿信号线、第二补偿信号线和补偿连接电极设置在所述第二子像素和第三子像素之间。
在示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第二扫描信号线的第二断口，所述信号连接电极包括第三信号连接电极、第四信号连接电极和第五信号连接电极，所述第三信号连接电极的第一端和所述第二断口一侧的所述第二扫描信号线分别通过过孔与所述第四信号连接电极连接，所述第三信号连接电极的第二端和所述第二断口另一侧的所述第二扫描信号线分别通过过孔与所述第五信号连接电极连接，所述第三信号连接电极的长度大于所述第一电源线的宽度，所述第三信号连接电极的长度小于所述子像素宽度。
在示例性实施方式中，在垂直于显示基板的平面上，所述显示基板包括多个导电层，所述第四信号连接电极、所述第五信号连接电极和所述第一电源线设置在相同的导电层中，所述第二扫描信号线和所述第一电源线设置在不同的导电层中。
在示例性实施方式中，所述多个子像素包括沿着所述第一方向依次设置的第一子像素、第二子像素、第三子像素和第四子像素，所述第四信号连接电极设置在所述第二子像素内，所述第五信号连接电极设置在所述第三子像素内。
在示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第一扫描信号的第一扫描信号线和向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第一扫描信号线的第一断口和截断所述第二扫描信号线的第二断口，所述信号连接电极包括第一信号连接电极和第二信号连接电极，所述第一信号连接电极分别通过过孔与所述第一断口两侧的所述第一信号连接电极连接，所述第二信号连接电极分别通过过孔与所述第二断口两侧的所述第二信号连接电极连接。
在示例性实施方式中，所述像素驱动电路至少包括存储电容；在垂直于显示基板的平面上，所述显示基板包括在基底上依次设置的透明导电层、第一导电层、半导体层、第二导电层和第三导电层，所述透明导电层至少包括所述存储电容的第一极板，所述半导体层至少包括所述存储电容的第二极板，所述第二导电层至少包括所述扫描信号线，所述第三导电层至少包括所述第一电源线，所述信号连接电极设置在所述第三导电层中，或者，所述信号连接电极分别设置在所述第一导电层和所述第三导电层中。
在示例性实施方式中，所述扫描信号线包括第一扫描信号线，所述信号连接电极包括第一信号连接电极，所述第一扫描信号线设置在所述第二导电层中，所述第一信号连接电极设置在所述第三导电层中。
在示例性实施方式中，所述扫描信号线包括第二扫描信号线，所述信号连接电极包括第二信号连接电极，所述第二扫描信号线设置在所述第二导电层中，所述第二信号连接电极设置在所述第三导电层中。
在示例性实施方式中，所述第一导电层还包括补偿连接电极，所述第三导电层还包括第一补偿信号线和第二补偿信号线。
在示例性实施方式中，所述扫描信号线包括第二扫描信号线，所述信号连接电极包括第三信号连接电极、第四信号连接电极和第五信号连接电极，所述第二扫描信号线设置在所述第二导电层中，所述第三信号连接电极设置在所述第一导电层中，所述第四信号连接电极和第五信号连接电极设置在所述第三导电层中。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括多个子像素，所述制备方法包括：
在至少一个子像素中形成像素驱动电路，所述像素驱动电路分别与沿着第一方向延伸的扫描信号线和沿着第二方向延伸的第一电源线连接，所述扫描信号线被配置为向所述像素驱动电路提供扫描信号，所述第一电源线被配置为向所述像素驱动电路提供电源信号，所述第一方向与所述第二方向交叉；所述扫描信号线设置有至少一个截断所述扫描信号线的断口，所述断口两侧的扫描信号线通过信号连接电极相互连接，所述信号连接电极的长度大于所述第一电源线的宽度，所述信号连接电极的长度小于子像素宽度，所述长度为所述信号连接电极所述第一方向的尺寸，所述宽度为所述第一电源线所述第一方向的尺寸，子像素宽度为所述子像素所述第一方向X的尺寸。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为本公开示例性实施例一种显示基板的结构示意图；
图6为本公开实施例一种形成透明导电层图案后的示意图；
图7a和图7b为本公开实施例一种形成第一导电层图案后的示意图；
图8a和图8b为本公开实施例一种形成半导体层图案后的示意图；
图9a和图9b为本公开实施例一种形成第二导电层图案后的示意图；
图10为本公开实施例一种形成第三绝缘层图案后的示意图；
图11a和图11b为本公开实施例一种形成第三导电层图案后的示意图；
图12为本公开实施例一种形成平坦层图案后的示意图；
图13为本公开实施例一种形成阳极导电层图案后的示意图；
图14为本公开实施例一种形成像素定义层图案后的示意图；
图15为本公开示例性实施例另一种显示基板的结构示意图；
图16为本公开实施例另一种形成第一导电层图案后的示意图；
图17为本公开实施例另一种形成半导体层图案后的示意图；
图18为本公开实施例另一种形成第二导电层图案后的示意图；
图19为本公开实施例另一种形成第三绝缘层图案后的示意图；
图20为本公开实施例另一种形成第三导电层图案后的示意图。
附图标记说明:
11—第一极板；         12—连接板；           13—连接线；
21—电源连接线；       22—补偿连接线；       23—遮挡层；
24—层间连接电极；     31—第一有源层；       32—第二有源层；
33—第三有源层；       34—第二极板；         41—第一扫描信号线；
42—第二扫描信号线；   43—第二栅电极；       44—辅助电源线；
45—辅助数据线；       46—辅助补偿线；       51—第一连接电极；
52—第二连接电极；     53—第三连接电极；     54—第四连接电极；
55—第五连接电极；     56—第六连接电极；     60—第一电源线；
70—数据信号线；       80—补偿信号线；       81—第一补偿信号线；
82—第二补偿信号线；   83—补偿连接电极；     91—第一信号连接电极；
92—第二信号连接电极； 93—第三信号连接电极； 94—第四信号连接电极；
95—第五信号连接电极； 101—基底；            102—驱动电路层；
103—发光结构层；      104—封装结构层；      301—阳极；
302—像素定义层；      303—有机发光层；      304—阴极；
401—第一封装层；      402—第二封装层；      403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器和像素阵列，时序控制器分别与数据驱 动器和扫描驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路与扫描信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和D的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至D，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2、出射第三颜色光线的第三子像素P3和出射第四颜色光线的第四子像素P4，四个子像素可以均包括电路单元和发光器件，电路单元可以包括像素驱动电路，像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个像素单元中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射白色光线的白色子像素(W)，第三子 像素P3可以是出射蓝色光线的蓝色子像素(B)，第四子像素P4可以是出射绿色光线的绿色子像素(G)。
在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形。在一种示例性实施方式中，四个子像素可以采用水平并列方式排列，形成RWBG像素排布。在另一种示例性实施方式中，四个子像素可以采用正方形(Square)、钻石形(Diamond)或竖直并列等方式排列，本公开在此不做限定。
在示例性实施方式中，水平方向依次设置的多个子像素称为像素行，竖直方向依次设置的多个子像素称为像素列，多个像素行和多个像素列构成阵列排布的像素阵列。
图3为一种显示基板的剖面结构示意图，示意了显示基板四个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板中每个子像素可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底一侧的发光结构层103以及设置在发光结构层103远离基底一侧的封装结构层104。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以至少包括由多个晶体管和存储电容构成的像素驱动电路。每个子像素的发光结构层103可以至少包括发光器件和像素定义层302，发光器件可以包括阳极301、有机发光层303和阴极304，阳极301与像素驱动电路连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、发光层(EML)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中， 所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层可以是连接在一起的共通层，所有子像素的发光层可以是连接在一起的共通层，或者可以是相互隔离的，相邻子像素的发光层可以有少量的交叠。在一些可能的实现方式中，显示基板可以包括其它膜层，本公开在此不做限定。
图4为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图4所示，像素驱动电路为3T1C结构，可以包括3个晶体管(第一晶体管T1、第二晶体管T2和第三晶体管T3)、1个存储电容C和6个信号线(数据信号线D、第一扫描信号线S1、第二扫描信号线S2、补偿信号线S、第一电源线VDD和第二电源线VSS)。
在示例性实施方式中，第一晶体管T1为开关晶体管，第二晶体管T2为驱动晶体管，第三晶体管T3为补偿晶体管。存储电容C的第一极与第二晶体管T2的栅电极耦接，存储电容C的第二极与第二晶体管T2的第二极耦接，存储电容C用于存储第二晶体管T2的栅电极的电位。第一晶体管T1的栅电极耦接于第一扫描信号线S1，第一晶体管T1的第一极耦接于数据信号线D，第一晶体管T1的第二极耦接于第二晶体管T2的栅电极，第一晶体管T1用于在第一扫描信号线S1控制下，接收数据信号线D传输的数据信号，使第二晶体管T2的栅电极接收所述数据信号。第二晶体管T2的栅电极耦接于第一晶体管T1的第二极，第二晶体管T2的第一极耦接于第一电源线VDD，第二晶体管T2的第二极耦接于发光器件的第一极，第二晶体管T2用于在其栅电极所接收的数据信号控制下，在第二极产生相应的电流。第三晶体管T3的栅电极耦接于第二扫描信号线S2，第三晶体管T3的第一极耦接于补偿信号线S，第三晶体管T3的第二极耦接于第二晶体管T2的第二极，第三晶体管T3用于响应补偿时序提取第二晶体管T2的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，OLED的第一极耦接于第二晶体管T2的第二极，OLED的第二极耦接于第二电源线VSS，OLED用于响应第二晶 体管T2的第二极的电流而发出相应亮度的光。
在示例性实施方式中，第一电源线VDD的信号为持续提供的高电平信号，第二电源线VSS的信号为持续提供的低电平信号。第一晶体管T1到第三晶体管T3可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。
在示例性实施方式中，第一晶体管T1到第三晶体管T3可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现高分辨率(Pixel Per Inch，简称PPI)，低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，以3个晶体管均为N型晶体管为例，图4示例的像素驱动电路的工作过程可以包括：
第一阶段A1，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号，数据信号线D输出数据电压，补偿信号线S输出补偿电压，第一电源线VDD的信号为高电平，第二电源线VSS的信号为低电平。第一扫描信号线S1的信号为高电平信号，使第一晶体管T1导通，数据信号线D输出的数据电压写入第一节点N1，将第一节点N1的电位拉高，对存储电容C进行充电，此时第一节点N1的电位为V 1＝V data。第二扫描信号线S2的信号为高电平信号，使第三晶体管T3导通，补偿信号线S输出的补偿电压写入第二节点N2，此时第二节点N2的电位V 2＝V s。由于第一节点N1和第二节点N2的电位之差大于第二晶体管T2的阈值电压V th，第二晶体管T2导通，第一电源线VDD输出的电源电压通过导通的第二晶体管T2向OLED的第一极提供驱动电压，驱动OLED发光。
第二阶段A2，第一扫描信号线S1和第二扫描信号线S2的信号为低电平信号，使第一晶体管T1和第三晶体管T3关断，存储电容C中的电压仍使得第二晶体管T2处于导通状态，第一电源线VDD输出的电源电压持续拉高第二节点N2的电位，OLED持续发光。当第二节点N2的电位等于V data-V th时，第二晶体管T2关断，OLED不再发光。
在示例性实施方式中，为了驱动OLED正常发光，OLED和第二晶体管T2均正向偏置，在第一阶段中，第一电源线VDD输出的电源电压大于数据信号线D输出数据电压，数据信号线D输出数据电压大于补偿信号线S输出的补偿电压，补偿信号线S输出的补偿电压大于第二电源线VSS输出的电源电压。
本公开示例性实施例提供了一种显示基板，包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路分别与沿着第一方向延伸的扫描信号线和沿着第二方向延伸的第一电源线连接，所述扫描信号线被配置为向所述像素驱动电路提供扫描信号，所述第一电源线被配置为向所述像素驱动电路提供高电压信号，所述第一方向与所述第二方向交叉；至少一个子像素中，所述扫描信号线设置有至少一个截断所述扫描信号线的断口，所述断口两侧的扫描信号线通过信号连接电极相互连接，所述信号连接电极的长度大于所述第一电源线的宽度，所述信号连接电极的长度小于子像素宽度，所述长度为所述信号连接电极所述第一方向的尺寸，所述宽度为所述第一电源线所述第一方向的尺寸，子像素宽度为所述子像素所述第一方向X的尺寸。
在一种示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第一扫描信号的第一扫描信号线，所述断口包括截断所述第一扫描信号线的第一断口，所述信号连接电极包括第一信号连接电极，所述第一信号连接电极的第一端通过过孔与所述第一断口一侧的所述第一扫描信号线连接，所述第一信号连接电极的第二端通过过孔与所述第一断口另一侧的所述第一扫描信号线连接，所述第一信号连接电极的长度大于所述第一电源线的宽度，所述第一信号连接电极的长度小于所述子像素宽度。
在另一种示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第二扫描信号 线的第二断口，所述信号连接电极包括第二信号连接电极，所述第二信号连接电极的第一端通过过孔与所述第二断口一侧的所述第二扫描信号线连接，所述第二信号连接电极的第二端通过过孔与所述第二断口另一侧的所述第二扫描信号线连接，所述第二信号连接电极的长度大于所述第一电源线的宽度，所述第二信号连接电极的长度小于所述子像素宽度。
在又一种示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第二扫描信号线的第二断口，所述信号连接电极包括第三信号连接电极、第四信号连接电极和第五信号连接电极，所述第三信号连接电极的第一端和所述第二断口一侧的所述第二扫描信号线分别通过过孔与所述第四信号连接电极连接，所述第三信号连接电极的第二端和所述第二断口另一侧的所述第二扫描信号线分别通过过孔与所述第五信号连接电极连接，所述第三信号连接电极的长度大于所述第一电源线的宽度，所述第三信号连接电极的长度小于所述子像素宽度。
在又一种示例性实施方式中，所述扫描信号线包括向所述像素驱动电路提供第一扫描信号的第一扫描信号线和向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第一扫描信号线的第一断口和截断所述第二扫描信号线的第二断口，所述信号连接电极包括第一信号连接电极和第二信号连接电极，所述第一信号连接电极分别通过过孔与所述第一断口两侧的所述第一信号连接电极连接，所述第二信号连接电极分别通过过孔与所述第二断口两侧的所述第二信号连接电极连接。
图5为本公开示例性实施例一种显示基板的结构示意图，示意了一种底发射显示基板中一个像素单元(四个子像素)的驱动电路层的结构。如图5所示，在平行于显示基板的方向上，至少一个像素单元可以包括沿着第一方向X依次排布的第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4，每个子像素均可以包括像素驱动电路和存储电容。后面描述中，子像素均是指设置像素驱动电路的区域。
在示例性实施方式中，至少一个像素单元可以包括一条第一扫描信号线41、一条第二扫描信号线42、两条第一电源线60、四条数据信号线70、一 条补偿信号线80，上述信号线均与四个子像素中的像素驱动电路连接。
在示例性实施方式中，第一扫描信号线41和第二扫描信号线42的形状可以为沿着第一方向X延伸的直线状，第一扫描信号线41和第二扫描信号线42沿着第二方向Y依次设置，第一方向X与第二方向Y交叉。
在示例性实施方式中，第一电源线60、数据信号线70和补偿信号线80的形状可以为沿着第二方向Y延伸的直线状。
在示例性实施方式中，两条第一电源线60可以分别设置在像素单元第一方向X的两侧，四条数据信号线70和一条补偿信号线80可以设置在两条第一电源线60之间，四条数据信号线70中的两条数据信号线70可以位于补偿信号线80与一条第一电源线60之间，四个数据信号线70中的另两条数据信号线70可以位于补偿信号线80与另一条第一电源线60之间。这样，两条第一电源线60之间通过设置四条数据信号线70和一条补偿信号线80可以形成四个子像素，相应的，两条补偿信号线80之间通过设置两条第一电源线60和四条数据信号线70也可以形成四个子像素。
在示例性实施方式中，一条第一电源线60与第一方向X邻近的一条数据信号线70之间形成第一子像素P1，补偿信号线80与第一方向X的反方向邻近的一条数据信号线70之间形成第二子像素P2，补偿信号线80与第一方向X邻近的一条数据信号线70之间形成第三子像素P3，另一条第一电源线60与第一方向X的反方向邻近的一条数据信号线70之间形成第四子像素P4。
在示例性实施方式中，像素单元的四个子像素中，至少一个子像素的像素驱动电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3和存储电容。第一晶体管T1、第二晶体管T2和第三晶体管T3均可以包括有源层、栅电极、第一极和第二极，存储电容可以包括透明的第一极板和透明的第二极板，形成透明的存储电容。
在示例性实施方式中，第一扫描信号线41与每个子像素中第一晶体管T1的栅电极连接，第二扫描信号线42与每个子像素中第三晶体管T3的栅电极连接，数据信号线70与每个子像素中第一晶体管T1的第一极连接，补偿 信号线80与每个子像素中第三晶体管T3的第一极连接，第一电源线60与每个子像素中第二晶体管T2的第一极连接，每个子像素中第一晶体管T1的第二极与第二晶体管T2的栅电极连接，每个子像素中第二晶体管T2的第二极与第三晶体管T3的第一极和发光器件的阳极连接，每个子像素中第一极板分别与第二晶体管T2的第二极和第三晶体管T3的第二极连接，每个子像素中第二极板分别与第一晶体管T1的第二极和第二晶体管T2的栅电极连接。
在示例性实施方式中，至少一个像素单元还可以包括多条连接线，多条连接线可以至少包括两条沿着第一方向X延伸的电源连接线21和两条沿着第一方向X延伸的补偿连接线22，形成第一电源线的一拖二结构和补偿信号线的一拖四结构。
在示例性实施方式中，一条电源连接线21设置在第一子像素P1和第二子像素P2，该电源连接线21的第一端通过过孔与位于第一子像素P1中的第一电源线60连接，第二端通过过孔与第二子像素P2中的第二晶体管T2连接。另一条电源连接线21设置在第三子像素P3和第四子像素P4，该电源连接线21的第一端通过过孔与位于第四子像素P4中的第一电源线60连接，第二端通过过孔与第三子像素P3中的第二晶体管T2连接。这样，一条第一电源线60通过一条电源连接线21能够向两个子像素的像素驱动电路提供电源信号。
在示例性实施方式中，一条补偿连接线22设置在第一子像素P1和第二子像素P2，该补偿连接线22一方面通过过孔与补偿信号线80连接，另一方面通过过孔分别与第一子像素P1和第二子像素P2的第三晶体管T3连接。另一条补偿连接线22设置在第三子像素P3和第四子像素P4，该补偿连接线22一方面通过过孔与补偿信号线80连接，另一方面通过过孔分别与第三子像素P3和第四子像素P4中的第三晶体管T3连接。这样，一条补偿信号线80能够向四个子像素的像素驱动电路提供补偿信号。
本公开实施例实施例通过第一电源线的一拖二结构和补偿信号线的一拖四结构，节省了信号线数量，减小了占用空间，结构简洁，布局合理，充分利用布图空间，提高了空间利用率，有利于提高分辨率。
在示例性实施方式中，第一扫描信号线41和第二扫描信号线42中的至少一个设置有至少一个截断扫描信号线的断口，断口两侧的扫描信号线通过信号连接电极相互连接。
在一种示例性实施方式中，至少一个子像素中的第一扫描信号线41设置有截断第一扫描信号线41的第一断口K1，第一断口K1两侧的第一扫描信号线41通过第一信号连接电极91连接。在示例性实施方式中，第一信号连接电极91的第一端通过过孔与第一断口K1第一方向X的反方向一侧的第一扫描信号线41连接，第一信号连接电极91的第二端通过过孔与第一断口K1第一方向X一侧的第一扫描信号线41连接，因而实现了第一扫描信号的连续传输。
在示例性实施方式中，第一信号连接电极92具有第一长度L1，第一电源线60具有宽度M。第一长度L1可以为第一信号连接电极91第一方向X的尺寸，即第一信号连接电极91延伸方向的尺寸。宽度M可以为第一电源线60第二方向Y的尺寸，即垂直于第一电源线60延伸方向的尺寸。在示例性实施方式中，宽度M可以为第一电源线60第二方向Y的最大尺寸，或者，宽度M可以为第一电源线60第二方向Y的平均尺寸。
在示例性实施方式中，第一信号连接电极91的第一长度L1可以大于第一电源线60的宽度M。
在示例性实施方式中，至少一个子像素具有子像素宽度，子像素宽度可以为子像素第一方向X的尺寸，第一信号连接电极91的第一长度L1可以小于子像素宽度。
在示例性实施方式中，第一信号连接电极91的第一长度L1可以约为子像素宽度的50％至80％。
在示例性实施方式中，第一信号连接电极91在显示基板上的正投影与第一电源线60和数据信号线70在显示基板上的正投影没有交叠。
在示例性实施方式中，第一断口K1和第一信号连接电极91可以设置在第一子像素P1内，或者，第一断口K1和第一信号连接电极91可以设置在第二子像素P2内，或者，第一断口K1和第一信号连接电极91可以设置在 第三子像素P3内，或者，第一断口K1和第一信号连接电极91可以设置在第四子像素P4内。
在另一种示例性实施方式中，至少一个子像素中的第二扫描信号线42设置有截断第二扫描信号线42的第二断口K2，第二断口K2两侧的第二扫描信号线42通过第二信号连接电极92连接。在示例性实施方式中，第二信号连接电极92的第一端通过过孔与第二断口K2第一方向X的反方向一侧的第二扫描信号线42连接，第二信号连接电极92的第二端通过过孔与第二断口K2第一方向X一侧的第二扫描信号线42连接，因而实现了第二扫描信号的连续传输。
在示例性实施方式中，第二信号连接电极92具有第二长度L2，第一电源线60具有宽度M，第二长度L2可以为第二信号连接电极92第一方向X的尺寸，即第二信号连接电极92延伸方向的尺寸。
在示例性实施方式中，第二信号连接电极92的第二长度L2可以大于第一电源线60的宽度M。
在示例性实施方式中，第二信号连接电极92的第二长度L2可以小于子像素宽度。
在示例性实施方式中，第二信号连接电极92的第二长度L2可以约为子像素宽度的50％至80％。
在示例性实施方式中，第二信号连接电极92在显示基板上的正投影与第一电源线60和数据信号线70在显示基板上的正投影没有交叠。
在示例性实施方式中，第二断口K2和第二信号连接电极92可以设置在第二子像素P2和第三子像素P3之间的区域。
在示例性实施方式中，至少一个子像素中的补偿信号线80可以至少包括间隔设置的第一补偿信号线81和第二补偿信号线82，以及连接第一补偿信号线81和第二补偿信号线82的补偿连接电极83。补偿连接电极83的第一端通过过孔与第一补偿信号线81连接，补偿连接电极83的第二端通过过孔与第二补偿信号线82连接，因而实现了补偿信号的连续传输。
在示例性实施方式中，第一补偿信号线81、第二补偿信号线82和补偿连接电极83可以设置在第二子像素P2和第三子像素P3之间。
在示例性实施方式中，补偿连接电极83在显示基板上的正投影与第二断口K2在显示基板上的正投影至少部分交叠。
在示例性实施方式中，补偿连接电极83在显示基板上的正投影与第二信号连接电极92在显示基板上的正投影至少部分交叠。
在示例性实施方式中，第二信号连接电极上设置有至少一个通孔，通孔在显示基板上的正投影与补偿连接电极83在显示基板上的正投影至少部分重叠。
在又一种示例性实施方式中，至少一个子像素中的第一扫描信号线41设置有截断第一扫描信号线41的第一断口K1，至少一个子像素中的第二扫描信号线42设置有截断第二扫描信号线42的第二断口K2，第一断口K1两侧的第一扫描信号线41通过第一信号连接电极91连接，第二断口K2两侧的第二扫描信号线42通过第二信号连接电极92连接。
在示例性实施方式中，第一断口K1和第一信号连接电极91可以设置在如下任意一个或多个位置：第一子像素P1，第二子像素P2，第三子像素P3，第四子像素P4，第二子像素P2和第三子像素P3之间的区域。第二断口K2和第二信号连接电极92可以设置在如下任意一个或多个位置：第一子像素P1，第二子像素P2，第三子像素P3，第四子像素P4，第二子像素P2和第三子像素P3之间的区域。例如，第一断口K1和第一信号连接电极91可以设置在第一子像素P1至第四子像素P4的至少一个子像素内，第二断口K2和第二信号连接电极92可以设置在第一子像素P1至第四子像素P4的至少一个子像素内。又如，第一断口K1和第一信号连接电极91可以设置在第一子像素P1至第四子像素P4的至少一个子像素内，第二断口K2和第二信号连接电极92可以设置在第二子像素P2和第三子像素P3之间的区域。再如，第一断口K1和第一信号连接电极91可以设置在第二子像素P2和第三子像素P3之间的区域，第二断口K2和第二信号连接电极92可以设置在第一子像素P1至第四子像素P4的至少一个子像素内。再如，第一断口K1和第一信号连接电极91可以设置在第二子像素P2和第三子像素P3之间的区域， 第二断口K2和第二信号连接电极92可以设置在第二子像素P2和第三子像素P3之间的区域。
在示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括在基底上叠设的透明导电层、第一导电层、第一绝缘层、半导体层、第二绝缘层、第二导电层、第三绝缘层和第三导电层。
在示例性实施方式中，透明导电层可以至少包括存储电容的第一极板，半导体层可以至少包括所述存储电容的第二极板，第一极板在基底上的正投影与第二极板在基底上的正投影至少部分交叠，形成透明的存储电容。第二导电层可以至少包括第一扫描信号线41和第二扫描信号线42，第三导电层可以至少包括第一电源线60、第一信号连接电极91和第二信号连接电极92，即第一信号连接电极91和第二信号连接电极92可以与第一电源线60同层设置，第一扫描信号线41和第二扫描信号线42可以与第一电源线60异层设置。
在示例性实施方式中，第一导电层还可以包括补偿连接电极83，第三导电层还可以包括第一补偿信号线81和第二补偿信号线82。
在示例性实施方式中，透明导电层可以至少包括存储电容的第一极板，第一导电层可以至少包括电源连接线21、补偿连接线22、遮挡层23和补偿连接电极83，半导体层可以至少包括存储电容的第二极板以及三个晶体管的有源层，第二导电层可以至少包括第一扫描信号线41、第二扫描信号线42以及三个晶体管的栅电极，第三导电层可以至少包括第一电源线60、数据信号线70、补偿信号线80、三个晶体管的第一极和第二极、第一信号连接电极91以及第二信号连接电极92。
在示例性实施方式中，第二晶体管的有源层在基底上的正投影位于遮挡层在基底上的正投影的范围之内。
在示例性实施方式中，第一扫描信号线41和第二扫描信号线42上可以设置有多个通孔，通孔在基底上的正投影与第一电源线60、数据信号线70和补偿信号线80在基底上的正投影至少部分重叠。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、 显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以四个子像素(第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4)为例，显示基板的制备过程可以包括如下操作。
(11)形成透明导电层图案。在示例性实施方式中，形成透明导电层图案可以包括：在基底上沉积透明导电薄膜，通过图案化工艺对透明导电薄膜进行图案化，在基底上形成透明导电层图案，如图6所示。在示例性实施例中，透明导电层可以称为ITO层。
在示例性实施方式中，每个子像素的透明导电层图案可以至少包括存储电容的第一极板11、连接板12和连接线13。
在示例性实施方式中，第一极板11的形状可以为矩形状，矩形状的角部可以设置倒角，矩形状的边缘可以为折线，第一极板11可以设置在子像素第二方向Y的中部区域，第一极板11被配置为形成透明的存储电容的一个透明极板。
在示例性实施方式中，连接板12的形状可以为多边形状，连接板12可以设置在第一极板11第二方向Y的一侧，且与第一极板11连接，连接板12被配置为与后续形成的遮挡层连接。
在示例性实施方式中，连接线13的形状可以为沿着第二方向Y延伸的条形状，连接线13可以设置在第一极板11远离连接板12的一侧，且与第一极板11连接。连接线13远离第一极板11的端部可以设置有连接块13-1，连接块13-1的形状可以为沿着第一方向X延伸的条形状，且与连接线13连接，连接块13-1被配置为与后续形成的层间连接电极连接。
在示例性实施方式中，第一极板11、连接板12和连接线13可以为相互连接的一体结构。
(12)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上沉积第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，在透明导电层上形成第一导电层图案，如图7a和图7b所示，图7b为图7a中第一导电层的平面示意图。在示例性实施例中，第一导电层可以称为遮挡金属(SHL)层。
在示例性实施方式中，每个子像素中的第一导电层图案可以至少包括电源连接线21、补偿连接线22、遮挡层23和层间连接电极24。
在示例性实施方式中，电源连接线21的形状可以为沿着第一方向X延伸的条形状，电源连接线21复用为像素单元的电源横向连接线，通过与后续形成的第一电源线连接，向所在子像素的第二晶体管T2提供电源电压。
在示例性实施方式中，在第一方向X上相邻的子像素的电源连接线21可以为相互连接的一体结构。例如，第一子像素P1和第二子像素P2中的电源连接线21相互连接，第三子像素P3和第四子像素P3中的电源连接线21相互连接，但第二子像素P2和第三子像素P3中的电源连接线21没有连接。
在示例性实施方式中，补偿连接线22的形状可以为沿着第一方向X延伸的条形状，补偿连接线22复用为像素单元的补偿横向连接线，通过与后续形成的补偿信号线连接，向所在子像素的第三晶体管T3提供补偿电压。
在示例性实施方式中，在第一方向X上相邻的子像素的补偿连接线22可以为相互连接的一体结构。例如，第一子像素P1和第二子像素P2中的补偿连接线22相互连接，第三子像素P3和第四子像素P3中的补偿连接线22相互连接，但第二子像素P2和第三子像素P3中的补偿连接线22没有连接。
在示例性实施方式中，遮挡层23的形状可以为矩形状，可以设置在电源连接线21和补偿连接线22之间，遮挡层23被配置为对第二晶体管T2提供遮挡，避免光线对沟道产生影响，降低漏电流，从而避免光照对晶体管特性的影响，保证第二晶体管T2的电学性能。
在示例性实施方式中，遮挡层23在基底上的正投影可以位于连接板12在基底上的正投影的范围之内，且遮挡层23与连接板12直接搭接。
在示例性实施方式中，层间连接电极24的形状可以为矩形状，可以设置在遮挡层23和补偿连接线22之间，层间连接电极24被配置为与后续形成的第三晶体管T3的第二极连接。
在示例性实施方式中，层间连接电极24在基底上的正投影与连接线13的连接块13-1在基底上的正投影至少部分交叠，且层间连接电极24与连接块13-1直接搭接。
在示例性实施方式中，每个像素单元的透明导电层图案还可以包括补偿连接电极83。补偿连接电极83的形状可以为沿着第二方向Y延伸的条形状，补偿连接电极83可以设置在第一方向X上相邻的补偿连接线22之间，即补偿连接电极83可以设置在第二子像素P2和第三子像素P3之间，补偿连接电极83被配置为作为补偿信号线的连接电极，通过与后续形成的补偿信号线连接，将间隔设置的第一补偿信号线和第二补偿信号线连接起来。
(13)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在形成前述图案的基底上，依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖第一导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图8a和图8b所示，图8b为图8a中半导体层的平面示意图。
在示例性实施方式中，每个子像素中的半导体层图案可以至少包括第一有源层31、第二有源层32、第三有源层33和第二极板34。
在示例性实施方式中，第二极板34的形状可以为矩形状，第二极板34在基底上的正投影与第一极板11在基底上的正投影至少部分交叠，第二极板34被配置为形成透明的存储电容的另一个透明极板，第一极板11和第二极 板34构成透明的存储电容。
在示例性实施方式中，第一有源层31可以作为第一晶体管T1的有源层，第二有源层32可以作为第二晶体管T2的有源层，第三有源层33可以作为第三晶体管T3的有源层，第一有源层31和第二有源层32可以设置在电源连接线21和第二极板34之间，第三有源层33可以设置在补偿连接线22和第二极板34之间。
在示例性实施方式中，第一有源层31、第二有源层32和第三有源层33均可以包括沟道区和位于沟道区两侧的第一区和第二区。
在示例性实施方式中，第一有源层31的形状可以呈“L”字形，第一有源层31的第一区31-1可以位于沟道区远离第二极板34的一侧，第一有源层31的第二区31-2可以位于沟道区靠近第二极板34的一侧，第一有源层31的第二区31-2在基底上的正投影与遮挡层23在基底上的正投影至少部分重叠。
在示例性实施方式中，第一有源层31的第二区31-2可以与第二极板34连接，第一有源层31和第二极板34可以为相互连接的一体结构。
在示例性实施方式中，第二有源层32的形状可以呈“I”字形，第二有源层32在基底上的正投影与遮挡层23在基底上的正投影至少部分重叠。第二有源层32的沟道区在基底上的正投影可以位于遮挡层23在基底上的正投影的范围之内，遮挡层23可以遮挡第二有源层32的沟道区，避免光线对沟道产生影响，降低漏电流，从而避免光照对晶体管特性的影响。第二有源层32的第一区32-1可以位于沟道区远离第二极板34的一侧，第二有源层32的第一区32-1在基底上的正投影可以位于遮挡层23在基底上的正投影的范围之内。第二有源层32的第二区32-2可以位于沟道区靠近第二极板34的一侧，第二有源层32的第二区32-2在基底上的正投影可以位于遮挡层23在基底上的正投影的范围之内。
在示例性实施方式中，第三有源层33的形状可以呈“I”字形，第三有源层33在基底上的正投影与第二极板34在基底上的正投影间隔设置，即第三有源层33与第二极板42之间没有交叠区域，有利于根据相关需求设计第三 晶体管的沟道宽长比。第三有源层33的第一区33-1可以位于沟道区远离第二极板34的一侧，第三有源层33的第一区33-1在基底上的正投影与补偿连接线22在基底上的正投影至少部分重叠。第三有源层33的第二区33-2可以位于沟道区靠近第二极板34的一侧，第三有源层33的第二区33-2在基底上的正投影与层间连接电极24在基底上的正投影至少部分重叠。
在示例性实施方式中，半导体层可以采用金属氧化物，如包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。半导体层可以单层，或者可以是双层，或者可以是多层。
(14)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖半导体层的第二绝缘层，以及设置在第二绝缘层上的第二导电层图案，如图9a和图9b所示，图9b为图9a中第二导电层的平面示意图。在示例性实施例中，第二导电层可以称为栅金属(GATE)层。
在示例性实施方式中，每个像素单元中的第二导电层图案可以至少包括第一扫描信号线41、第二扫描信号线42、第二栅电极43、辅助电源线44、辅助数据线45和辅助补偿线46。
在示例性实施方式中，第一扫描信号线41的形状可以为沿着第一方向X延伸的条形状，第一扫描信号线41可以位于第二极板34第二方向Y的一侧，每个子像素的第一扫描信号线41上设置有第一栅电极41-1，第一栅电极41-1作为第一晶体管T1的栅电极，第一栅电极41-1在基底上的正投影与第一有源层31在基底上的正投影至少部分重叠。
在示例性实施方式中，第一扫描信号线41可以为等宽度设置，宽度为第一扫描信号线41第二方向Y的尺寸。第一扫描信号线41上可以设置有多个通孔，多个通孔在基底上的正投影与后续形成的第一电源线、数据信号线和补偿信号线在基底上的正投影至少部分重叠，多个通孔被配置为降低第一扫描信号线41与第一电源线、数据信号线和补偿信号线之间的寄生电容。
在示例性实施方式中，第二扫描信号线42的形状可以为沿着第一方向X延伸的条形状，第二扫描信号线42可以位于第二极板34远离第一扫描信号线41的一侧，第二扫描信号线42在基底上的正投影与每个子像素中的第三有源层33在基底上的正投影至少部分重叠，重叠区域的第二扫描信号线42可以作为第三晶体管T3的栅电极。
在示例性实施方式中，第二扫描信号线42可以为非等宽度设置，宽度为第二扫描信号线42第二方向Y的尺寸。第二扫描信号线42包括与第三有源层33相重叠的区域和与第三有源层33不相重叠的区域，与第三有源层33相重叠的区域的第二扫描信号线42的宽度可以小于与第三有源层33不相重叠的区域的第二扫描信号线42的宽度。与第三有源层33不相重叠的区域中，第二扫描信号线42上可以设置有多个通孔，多个通孔在基底上的正投影与后续形成的第一电源线、数据信号线和补偿信号线在基底上的正投影至少部分重叠，多个通孔被配置为降低第二扫描信号线42与第一电源线、数据信号线和补偿信号线之间的寄生电容。
在示例性实施方式中，第一扫描信号线41和第二扫描信号线42可以平行设置。
在示例性实施方式中，第一扫描信号线41和第二扫描信号线42均为非连续设置，在至少一个子像素中，第一扫描信号线41上设置有至少一个第一断口K1，第二扫描信号线42上设置有至少一个第二断口K2。
在示例性实施方式中，第一断口K1可以设置在如下任意一个或多个位置：第一子像素P1，第二子像素P2，第三子像素P3，第四子像素P4，第二子像素P2和第三子像素P3之间。第二断口K2可以设置在如下任意一个或多个位置：第一子像素P1，第二子像素P2，第三子像素P3，第四子像素P4，第二子像素P2和第三子像素P3之间。
在示例性实施方式中，至少一个第一断口K1可以设置在第一子像素P1，第一断口K1将第一扫描信号线41断开，形成非连续结构的第一扫描信号线41。在示例性实施方式中，第一断口K1两侧的第一扫描信号线41可以通过后续形成的第一信号连接电极相互连接，实现第一扫描信号的传输。
在示例性实施方式中，至少一个第二断口K2可以设置在第二子像素P2和第三子像素P3之间，第二断口K2将第二扫描信号线42断开，形成非连续结构的第二扫描信号线42。在示例性实施方式中，第二断口K2两侧的第二扫描信号线42可以通过后续形成的第二信号连接电极相互连接，实现第二扫描信号的传输。
在示例性实施方式中，补偿连接电极83可以设置在第二断口K2内，补偿连接电极83在基底上的正投影与第二断口K2在基底上的正投影至少部分交叠。
在示例性实施方式中，第二栅电极43的形状可以为沿着第一方向X延伸的条形状，第二栅电极43可以作为第二晶体管T2的栅电极。在每个子像素内，一方面，第二栅电极43在基底上的正投影与第二有源层32在基底上的正投影至少部分重叠，另一方面，第二栅电极43在基底上的正投影与第一有源层31的第二区31-2至少部分重叠。
在示例性实施方式中，辅助电源线44的形状可以为沿着第二方向Y延伸的条形状，可以分别设置在第一子像素P1和第四子像素P4内。在第一子像素P1内，辅助电源线44位于第二极板34第一方向X的反方向的一侧。在第四子像素P4内，辅助电源线44位于第二极板34第一方向X的一侧。辅助电源线44被配置为与后续形成的第一电源线连接，形成双层走线，保证电源信号传输的可靠性，并降低第一电源线的电阻。
在示例性实施方式中，辅助数据线45的形状可以为沿着第二方向Y延伸的条形状，可以分别设置在每个子像素内。在第一子像素P1和第三子像素P3内，辅助数据线45位于第二极板34第一方向X的一侧。在第二子像素P2和第四子像素P4内，辅助数据线45位于第二极板34第一方向X的反方向的一侧。辅助数据线45被配置为与后续形成的数据信号线连接，形成双层走线，保证数据信号传输的可靠性，并降低数据信号线的电阻。
在示例性实施方式中，辅助补偿线46的形状可以为沿着第二方向Y延伸的条形状，可以设置在第二子像素P2和第三子像素P3之间。辅助补偿线46被配置为与后续形成的补偿信号线连接，形成双层走线，保证补偿信号传输的可靠性，并降低补偿信号线的电阻。
在示例性实施方式中，辅助电源线44、辅助数据线45和辅助补偿线46的主体部分可以平行设置。
在示例性实施方式中，第一子像素P1和第四子像素P4内的第二栅电极43可以相对于辅助补偿线46镜像对称设置，第二子像素P2和第三子像素P3内的第二栅电极43可以相对于辅助补偿线46镜像对称设置。
在示例性实施方式中，第一子像素P1和第四子像素P4内的辅助电源线44可以相对于辅助补偿线46镜像对称设置，第二扫描信号线42可以相对于辅助补偿线46镜像对称设置。
在示例性实施方式中，本次工艺还包括导体化处理。导体化处理是在形成第二导电层图案后，利用第二导电层作为遮挡进行等离子体处理，被第二导电层遮挡的半导体层作为晶体管的沟道区域，未被第二导电层遮挡的半导体层被处理成导体化层，形成导体化的第二极板34和导体化的源漏区域。
(15)形成第三绝缘层图案。在示例性实施例中，形成第三绝缘层图案可以包括：在形成前述图案的基底上，沉积第三绝缘薄膜，采用图案化工艺对第三绝缘薄膜进行图案化，形成覆盖第二导电层的第三绝缘层，第三绝缘层上设置有多个过孔，如图10所示。
在示例性实施方式中，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16、第十七过孔V17和第十八过孔V18。
在示例性实施例中，第一过孔V1可以设置在每个子像素，第一过孔V1在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第一过孔V1被配置为使后续形成的数据信号线与通过该过孔与第一有源层的第一区连接。
在示例性实施例中，第二过孔V2可以设置在每个子像素，第二过孔V2在基底上的正投影位于第一有源层的第二区在基底上的正投影的范围之内，且第二过孔V2在基底上的正投影与第二栅电极43在基底上的正投影至少部 分重叠，第二过孔V2内的第三绝缘层和第二绝缘层被刻蚀掉，同时暴露出第一有源层的第二区的表面和第二栅电极43的表面。第二过孔V2为转接过孔，转接过孔由两个半孔组成，一个半孔形成在第一有源层的第二区上，另一个半孔形成在第二栅电极43上，使得两个半孔组成的转接过孔同时暴露出第一有源层的第二区的表面和第二栅电极43的表面。在示例性实施例中，第二过孔V2被配置为使后续形成的第一晶体管T1的第二极通过该过孔同时与第二栅电极43和第一有源层的第二区连接。
在示例性实施例中，第三过孔V3可以设置在每个子像素，第三过孔V3在基底上的正投影位于第二有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区的表面，第三过孔V3被配置为使后续形成的第一电源线通过该过孔与第二有源层的第一区连接。
在示例性实施例中，第四过孔V4可以设置在每个子像素，一方面，第四过孔V4在基底上的正投影与第二有源层的第二区在基底上的正投影至少部分重叠，另一方面，第四过孔V4在基底上的正投影与遮挡层23在基底上的正投影至少部分重叠，第四过孔V4内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，同时暴露出第二有源层的第二区的表面和遮挡层23的表面，第四过孔V4被配置为使后续形成的第二晶体管T2的第二极通过该过孔同时与第二有源层的第二区和遮挡层23连接。
在示例性实施例中，第五过孔V5可以设置在每个子像素，一方面，第五过孔V5在基底上的正投影与第三有源层的第一区在基底上的正投影至少部分重叠，另一方面，第五过孔V5在基底上的正投影与补偿连接线22在基底上的正投影至少部分重叠，第五过孔V5内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，同时暴露出第三有源层的第一区的表面和补偿连接线22的表面，第五过孔V5被配置为使后续形成的第三晶体管T3的第一极通过该过孔同时与补偿连接线22和第三有源层的第一区连接。
在示例性实施例中，第六过孔V6可以设置在每个子像素，一方面，第六过孔V6在基底上的正投影与第三有源层的第二区在基底上的正投影至少部分重叠，另一方面，第六过孔V6在基底上的正投影与层间连接电极24在 基底上的正投影至少部分重叠，第六过孔V6内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，同时暴露出第三有源层的第二区的表面和层间连接电极24的表面，第六过孔V6被配置为使后续形成的第三晶体管T3的第二极通过该过孔同时与层间连接电极24和第三有源层的第二区连接。
在示例性实施例中，第七过孔V7可以设置在第一子像素P1和第四子像素P4，第七过孔V7在基底上的正投影位于电源连接线21的第一端在基底上的正投影的范围之内，第七过孔V7内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出电源连接线21的第一端的表面，第七过孔V7被配置为使后续形成的第一电源线通过该过孔与电源连接线21的第一端连接。
在示例性实施例中，第八过孔V8可以设置在第二子像素P2和第三子像素P3，第八过孔V8在基底上的正投影位于电源连接线21的第二端在基底上的正投影的范围之内，第八过孔V8内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出电源连接线21的第二端的表面，第八过孔V8被配置为使后续形成的第二晶体管T2的第一极通过该过孔与电源连接线21的第二端连接。
在示例性实施例中，第九过孔V9可以设置在第一子像素P1和第四子像素P4，第九过孔V9在基底上的正投影位于辅助电源线44在基底上的正投影的范围之内，第九过孔V9内的第三绝缘层被刻蚀掉，暴露出辅助电源线44的表面，第九过孔V9被配置为使后续形成的第一电源线通过该过孔与辅助电源线44连接。在示例性实施例中，第九过孔V9可以包括多个，多个第九过孔V9可以沿着第二方向Y依次排列，以增加第一电源线与辅助电源线44的连接可靠性。
在示例性实施例中，第十过孔V10可以设置在每个子像素，第十过孔V10在基底上的正投影位于辅助数据线45在基底上的正投影的范围之内，第十过孔V10内的第三绝缘层被刻蚀掉，暴露出辅助数据线45的表面，第十过孔V10被配置为使后续形成的数据信号线通过该过孔与辅助数据线45连接。在示例性实施例中，第十过孔V10可以包括多个，多个第十过孔V10可以沿着第二方向Y依次排列，以增加数据信号线与辅助数据线45的连接可靠性。
在示例性实施例中，第十一过孔V11可以设置在第二子像素P2和第三子像素P3之间，第十一过孔V11在基底上的正投影位于辅助补偿线46在基底上的正投影的范围之内，第十一过孔V11内的第三绝缘层被刻蚀掉，暴露出辅助补偿线46的表面，第十一过孔V11被配置为使后续形成的补偿信号线通过该过孔与辅助补偿线46连接。在示例性实施例中，第十一过孔V11可以包括多个，多个第十一过孔V11可以沿着第二方向Y依次排列，以增加补偿信号线与辅助补偿线46的连接可靠性。
在示例性实施例中，第十三过孔V13和第十四过孔V14可以设置在第一子像素P1，第十三过孔V13在基底上的正投影可以位于第一断口K1一侧的第一扫描信号线41在基底上的正投影的范围之内，第十四过孔V14在基底上的正投影可以位于第一断口K1另一侧的第一扫描信号线41在基底上的正投影的范围之内，第十三过孔V13和第十四过孔V14内的第三绝缘层被刻蚀掉，分别暴露出第一断口K1两侧的第一扫描信号线41的表面，第十三过孔V13和第十四过孔V14被配置为使后续形成的第一信号连接电极通过该过孔与第一扫描信号线41连接。
在示例性实施例中，第十五过孔V15可以设置在第二子像素P2，第十六过孔V16可以设置在第三子像素P3，第十五过孔V15在基底上的正投影可以位于第二断口K2一侧的第二扫描信号线42在基底上的正投影的范围之内，第十六过孔V16在基底上的正投影可以位于第二断口K2另一侧的第二扫描信号线42在基底上的正投影的范围之内，第十五过孔V15和第十六过孔V16内的第三绝缘层被刻蚀掉，分别暴露出第二断口K2两侧的第二扫描信号线42的表面，第十五过孔V15和第十六过孔V16被配置为使后续形成的第二信号连接电极通过该过孔与第二扫描信号线42连接。
在示例性实施例中，第十七过孔V17可以设置在第二子像素P2和第三子像素P3之间，第十七过孔V17在基底上的正投影可以位于补偿连接电极83的第一端在基底上的正投影的范围之内，第十七过孔V17内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出补偿连接电极83的第一端的表面，第十七过孔V17被配置为使后续形成的补偿信号线通过该过孔与补偿连接电极83的第一端连接。
在示例性实施例中，第十八过孔V18可以设置在第二子像素P2和第三子像素P3之间，第十八过孔V18在基底上的正投影可以位于补偿连接电极83的第二端在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出补偿连接电极83的第二端的表面，第十八过孔V18被配置为使后续形成的补偿信号线通过该过孔与补偿连接电极83的第二端连接。
(16)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第三绝缘层上的第三导电层，如图11a和图11b所示，图11b为图11a中第三导电层的平面示意图。在示例性实施例中，第三导电层可以称为源漏金属(SD)层。
在示例性实施方式中，每个像素单元中的第三导电层图案至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第一电源线60、数据信号线70、补偿信号线80、第一信号连接电极91和第二信号连接电极92。
在示例性实施例中，第一电源线60可以分别设置在第一子像素P1和第四子像素P4，第一电源线60的形状可以为主体部分沿着第二方向Y延伸的线形状。一方面，第一电源线60通过第三过孔V3与第二有源层的第一区连接，实现将电源信号写入第二晶体管T2，另一方面，第一电源线60通过第七过孔V7与电源连接线21的第一端连接，第一电源线60将电源信号传输给电源连接线21，使得电源连接线21可以将电源信号分别传输到第二子像素P2和第三子像素P3，又一方面，第一电源线60通过多个第九过孔V9与辅助电源线44连接，使得第一电源线60和辅助电源线44形成双层走线。
在示例性实施方式中，第一电源线60可以为等宽度的直线或折线，或者为非等宽度的直线或折线，采用变宽度的直线或折线，不仅可以便于像素结构的布局，而且可以降低寄生电容。
在示例性实施例中，数据信号线70分别设置在每个子像素，数据信号线70的形状可以为主体部分沿着第二方向Y延伸的线形状。一方面，数据信号线70通过第一过孔V1与第一有源层的第一区连接，实现将数据信号写入第 一晶体管T1，另一方面，数据信号线70通过多个第十过孔V10与辅助数据线45连接，使得数据信号线70和辅助数据线45形成双层走线。
在示例性实施方式中，数据信号线70可以为等宽度的直线或折线，或者为非等宽度的直线或折线，采用变宽度设置的直线或折线，不仅可以便于像素结构的布局，而且可以降低寄生电容。
在示例性实施例中，补偿信号线设置在第二子像素P2和第三子像素P3之间，补偿信号线可以包括分别设置第二信号连接电极92第二方向Y两侧的第一补偿信号线81和第二补偿信号线82，第一补偿信号线81和第二补偿信号线82的形状可以为主体部分沿着第二方向Y延伸的条形状，形成间隔设置的补偿信号线。
在示例性实施例中，第一补偿信号线81通过第十七过孔V17与补偿连接电极83的第一端连接，第二补偿信号线82通过第十八过孔V18与补偿连接电极83的第二端连接，使得第二信号连接电极92两侧的第一补偿信号线81和第二补偿信号线82通过补偿连接电极83实现了相互连接。
在示例性实施例中，第二补偿信号线82还可以通过多个第十一过孔V11与辅助补偿线46连接，使得第二补偿信号线82和辅助补偿线46形成双层走线。
在示例性实施方式中，第一补偿信号线81和第二补偿信号线82可以为等宽度的直线或折线，或者为非等宽度的直线或折线，采用变宽度设置的直线或折线，不仅可以便于像素结构的布局，而且可以降低寄生电容。
在示例性实施例中，第一连接电极51的形状可以为矩形状，可以分别设置在每个子像素中，每个子像素中的第一连接电极51通过第二过孔V2同时与第一有源层的第二区和第二栅电极连接。在示例性实施例中，第一连接电极51可以作为第一晶体管T1的第二极，由于第一有源层的第二区与第二极板34连接，因而第一连接电极51使得第一晶体管T1的第二极、第二栅电极43和第二极板34具有相同的电位，即像素驱动电路中第一节点N1的电位。
在示例性实施例中，第二连接电极52的形状可以为矩形状，可以分别设置在每个子像素中，每个子像素中的第二连接电极52通过第四过孔V4同时 与第二有源层的第二区和遮挡层23连接。在示例性实施例中，第二连接电极52可以作为第二晶体管T2的第二极，由于遮挡层23与连接板12连接，连接板12与第一极板11连接，因而第二连接电极52使得第二晶体管T2的第二极和第一极板11具有相同的电位。
在示例性实施例中，第三连接电极53的形状可以为矩形状，可以分别设置在每个子像素中，每个子像素中的第三连接电极53通过第六过孔V6同时与第三有源层的第二区和层间连接电极连接。在示例性实施例中，第三连接电极53可以作为第三晶体管T3的第二极，由于层间连接电极24与连接线13连接，连接线13与第一极板11连接，因而第三连接电极53使得第三晶体管T3的第二极和第一极板11具有相同的电位。
在示例性实施例中，由于第二连接电极52使得第一极板11与第二晶体管T2的第二极具有相同的电位，第三连接电极53使得第一极板11与第三晶体管T3的第二极具有相同的电位，因而第二晶体管T2的第二极、第三晶体管T3的第二极和第一极板11具有相同的电位，即像素驱动电路中第二节点N2的电位。
在示例性实施例中，第四连接电极54的形状可以为矩形状，可以分别设置在每个子像素中，每个子像素中的第四连接电极54通过该子像素的第五过孔V5同时与第三有源层的第一区和补偿连接线22连接。在示例性实施例中，第四连接电极54可以作为第三晶体管T3的第一极，由于补偿连接线22与第一补偿信号线81连接，因而第四连接电极54可以将补偿信号写入每个子像素的第三晶体管T3的第一极。
在示例性实施例中，第五连接电极55的形状可以为沿着第一方向X延伸的条形状，可以分别设置在第二子像素P2和第三子像素P3中，第五连接电极55的第一端与第一补偿信号线81连接，第五连接电极55的第二端沿着第一方向X的反方向延伸到第二子像素P2或者沿着第一方向X延伸到第三子像素P3，与所在子像素的第四连接电极54连接。在示例性实施例中，第五连接电极55可以作为辅助连接线，由于第五连接电极55与第一补偿信号线81连接，第四连接电极54与第五连接电极55，补偿连接线22与第四连接电极54连接，因而实现了补偿连接线22与第一补偿信号线81的连接，第 一补偿信号线81将补偿信号传输给补偿连接线22。
在示例性实施例中，第二子像素P2和第三子像素P3中的第一补偿信号线81、第四连接电极54和第五连接电极55可以为相互连接的一体结构。
在示例性实施例中，第六连接电极56的形状可以为沿着第二方向Y延伸的条形状，可以分别设置在第二子像素P2和第三子像素P3中，第六连接电极56的第一端通过第八过孔V8与电源连接线21连接，第六连接电极56的第二端通过该子像素的第三过孔V3与第二有源层的第一区连接。在示例性实施例中，第六连接电极56可以作为第二晶体管T2的第一极，由于电源连接线21与第一电源线60连接，因而第六连接电极56可以将电源信号写入第二子像素P2和第三子像素P3的第二晶体管T2的第一极。
在示例性实施例中，第一信号连接电极91的形状可以为沿着第一方向X延伸的条形状，可以设置在第一子像素P1中，第一信号连接电极91的第一端通过第十三过孔V13与位于第一断口K1一侧的第一扫描信号线41连接，第一信号连接电极91的第二端通过第十四过孔V14与位于第一断口K1另一侧的第一扫描信号线41连接，使得第一断口K1两侧的第一扫描信号线41通过第一信号连接电极91实现了相互连接。
在示例性实施方式中，第一信号连接电极92可以具有第一长度L1，第一电源线60具有宽度M。第一长度L1可以为第一信号连接电极91第一方向X的尺寸，即第一信号连接电极91延伸方向的尺寸。宽度M可以为第一电源线60第二方向Y的尺寸，即垂直于第一电源线60延伸方向的尺寸。在示例性实施方式中，宽度M可以为第一电源线60第二方向Y的最大尺寸，或者，宽度M可以为第一电源线60第二方向Y的平均尺寸。
在示例性实施方式中，第一信号连接电极91的第一长度L1可以大于第一电源线60的宽度M。
在示例性实施方式中，至少一个子像素具有子像素宽度，子像素宽度可以为子像素第一方向X的尺寸，第一信号连接电极91的第一长度L1可以小于子像素宽度。
在示例性实施方式中，第一信号连接电极91的第一长度L1可以约为子像素宽度的50％至80％。
在示例性实施例中，第二信号连接电极92的形状可以为沿着第一方向X延伸的条形状，可以设置在第二子像素P2和第三子像素P3之间，第二信号连接电极92的第一端通过第十五过孔V15与位于第二断口K2一侧的第二扫描信号线42连接，第二信号连接电极92的第二端通过第十六过孔V16与位于第二断口K2另一侧的第二扫描信号线42连接，使得第二断口K2两侧的第二扫描信号线42通过第二信号连接电极92实现了相互连接。
在示例性实施例中，第二信号连接电极92上可以设置有至少一个通孔，通孔在基底上的正投影与补偿连接电极83通孔被配置为降低第二信号连接电极92与补偿连接电极83之间的寄生电容，即降低第二扫描信号线与补偿信号线之间的寄生电容。
在示例性实施方式中，第二信号连接电极92具有第二长度L2，第二长度L2可以为第二信号连接电极92第一方向X的尺寸，即第二信号连接电极92延伸方向的尺寸。
在示例性实施方式中，第二信号连接电极92的第二长度L2可以大于第一电源线60的宽度M。
在示例性实施方式中，第二信号连接电极92的第二长度L2可以小于子像素宽度。
在示例性实施方式中，第二信号连接电极92的第二长度L2可以约为子像素宽度的50％至80％。
本公开示例性实施例通过在每个子像素中设置沿着第二方向Y延伸的数据信号线70，数据信号线70通过过孔与本子像素的第一晶体管T1连接，实现了将数据信号分别写入四个子像素的第一晶体管T1的第一极。
本公开示例性实施例通过在像素单元中设置沿着第二方向Y延伸的两条第一电源线60和沿着第一方向X延伸的两条电源连接线21，实现了将电源信号分别写入四个子像素的第二晶体管T2。其中，在第一子像素P1和第四子像素P4，第一电源线60分别通过过孔与第二晶体管T2的第一极直接连接。 在第二子像素P2和第三子像素P3，第一电源线60分别通过第六连接电极56与第二晶体管T2的第一极连接。
本公开示例性实施例通过在像素单元中设置主体部分沿着第二方向Y延伸的一条补偿信号线(通过补偿连接电极83连接的第一补偿信号线81和第二补偿信号线82)和沿着第一方向X延伸的两条补偿连接线22，实现了将补偿信号分别写入四个子像素的第三晶体管T3。其中，在第二子像素P2和第三子像素P3，补偿信号线分别通过第五连接电极55和第四连接电极54与第三晶体管T3的第一极连接。在第一子像素P1和第四子像素P4，补偿信号线分别通过补偿连接线22和第四连接电极54与第三晶体管T3的第一极连接。本公开通过设置一条补偿信号线向四个子像素提供补偿信号，可以保证补偿信号在写入晶体管前RC延迟基本上相同，保证了显示均一性。
本公开示例性实施例在第一扫描信号线上设置至少一个第一断口，第一断口两侧的第一扫描信号线通过第一信号连接电极相互连接。与显示基板采用连续的扫描信号线相比，本公开示例性实施例通过将第一扫描信号线分成多段，第一信号连接电极的第一长度大于第一电源线的宽度，不仅有效减小了干刻过程中扫描信号线产生的静电量，而且避免了因静电集聚导致击穿晶体管沟道的情况，有效避免了显示装置出现边缘暗点，在保证第一扫描信号连续传输的前提下，提高了良品率，提高了显示品质。
本公开示例性实施例在第二扫描信号线上设置至少一个第二断口，第二断口两侧的第二扫描信号线通过第二信号连接电极相互连接。与显示基板采用连续的扫描信号线相比，本公开示例性实施例通过将第二扫描信号线分成多段，第二信号连接电极的第二长度大于第二电源线的宽度，不仅有效减小了干刻过程中扫描信号线产生的静电量，而且避免了因静电集聚导致击穿晶体管沟道的情况，有效避免了显示装置出现边缘暗点，在保证第二扫描信号连续传输的前提下，提高了良品率，提高了显示品质。
本公开示例性实施例通过将第二断口设置在第二子像素P2和第三子像素P3之间，将补偿信号线分成多段，补偿信号线通过补偿连接电极实现了相互连接，有效减小了干刻过程中补偿信号线产生的静电量，而且避免了因静电集聚导致击穿晶体管沟道的情况，有效避免了显示装置出现边缘暗点， 在保证补偿信号线连续传输的前提下，提高了良品率，提高了显示品质。
(17)形成平坦层图案。在示例性实施例中，形成平坦层图案可以包括：在形成前述图案的基底上，涂覆平坦薄膜，采用图案化工艺对平坦薄膜进行图案化，形成覆盖第三导电层的平坦层图案，平坦层上开设有多个过孔，多个过孔至少包括位于每个子像素中第二十一过孔V21，如图12所示。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第二连接电极52在基底上的正投影的范围之内，第二十一过孔V21内的平坦层被去掉，暴露出第二连接电极52的表面，第二十一过孔V21被配置为使后续形成的阳极通过该过孔与第二连接电极52连接。
在示例性实施方式中，显示基板可以包括第四绝缘层和彩膜层，在形成有前述图案的基底上，先形成第四绝缘层，然后在第四绝缘层上形成彩膜层，随后涂覆平坦薄膜，采用图案化工艺对平坦薄膜和第四绝缘薄膜进行图案化，形成覆盖第三导电层的第四绝缘层、设置在第四绝缘层上的彩膜层以及覆盖彩膜层的平坦层图案，平坦层和第四绝缘层上开设有多个过孔。
(18)形成阳极导电层图案。在示例性实施例中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在平坦层上的阳极导电层图案，阳极导电层图案至少包括位于每个子像素中阳极301，如图13所示。
在示例性实施方式中，阳极导电层图案可以包括位于第一子像素P1中的红色阳极、位于第二子像素P2中的白色阳极、位于第三子像素P3中的蓝色阳极和位于第四子像素P4中的绿色阳极，每个子像素中的阳极通过第二十一过孔V21与第二连接电极52连接。由于第二连接电极52作为第二晶体管T2的第二极，因而实现了阳极301与第二晶体管T2的第二极的连接。
在示例性实施方式中，阳极301可以为沿着第二方向Y延伸的条形状，每个子像素中的阳极第二方向Y的一侧设置有凸起部，凸起部通过第二十一过孔V21与第二连接电极52连接。
在示例性实施方式中，每个子像素中的阳极在基底上的正投影包含所在子像素中的存储电容在基底上的正投影。
(19)形成像素定义层图案。在示例性实施例中，形成像素定义层图案可以包括：在形成前述图案的基底上涂覆像素定义薄膜，采用图案化工艺对像素定义薄膜进行图案化，形成像素定义层图案，像素定义层图案至少包括位于每个子像素中像素开口302K，如图14所示。
在示例性实施例中，不同子像素的像素开口302K的形状和面积可以不同。本公开示例性实施例通过将四个子像素设计成不同开口率，可以适应不同子像素彩膜层的透过率，使得四个子像素的发光器件可以在不同电流时出射相同亮度，最大限度地优化了四个子像素发光器件的寿命，保证了产品寿命。
在示例性实施方式中，四个子像素的像素开口的形状可以相同，或者可以不同，四个子像素的像素开口的面积可以相同，或者可以不同。
在示例性实施方式中，像素开口的形状可以包括如下任意一种或多种：三角形、矩形、梯形、平行四框形、五框形、六框形、圆形和椭圆形。
在示例性实施例中，每个子像素中的像素开口302K在基底上的正投影与所在子像素中存储电容在基底上的正投影至少部分重叠。
在示例性实施例中，每个子像素中存储电容在基底上的正投影可以位于所在子像素中像素开口302K在基底上的正投影的范围之内。
在示例性实施例中，后续制备流程可以包括：采用蒸镀或喷墨打印工艺形成有机发光层，有机发光层通过像素开口与阳极连接，在有机发光层上形成阴极，阴极与有机发光层连接。形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
至此，在基底上制备完成驱动电路层、设置在驱动电路层上的发光结构层和设置在发光结构层上的，封装结构层。在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次叠设的透明导电层、第一导电层、第一绝缘层、半导体层、第二绝缘层、第二导电层、第三绝缘层、第三导电层和平坦层。发光结构层可以包括在阳极、像素定义层、有机发光层和阴极，封装结 构层可以包括叠设的第一封装层、第二封装层和第三封装层。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，透明导电层和阳极导电层可以采用透明导电材料，如氧化铟锡ITO或氧化铟锌IZO等。第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层和第三绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，第二绝缘层称为栅绝缘(GI)层，第三绝缘层称为层间绝缘(ILD)层。平坦层可以采用有机材料，如树脂等，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯。
如图6至图14所示，本公开示例性实施例所提供的显示基板可以包括：
基底；
设置在基底上的透明导电层，透明导电层至少包括第一极板11；
设置在透明导电层上的第一导电层，第一导电层至少包括电源连接线21、补偿连接线22、遮挡层23和补偿连接电极83，遮挡层23与第一极板11连接；
覆盖第一导电层的第一绝缘层；
设置在第一绝缘层上的半导体层，半导体层至少包括第一有源层31、第二有源层32、第三有源层33和第二极板34，第一有源层31和第二极板34可以为相互连接的一体结构，第二极板34与第一极板11构成透明的存储电容；
覆盖半导体层的第二绝缘层；
设置在第二绝缘层上的第二导电层，第二导电层至少包括第一扫描信号线41、第二扫描信号线42和第二栅电极43，第一扫描信号线41上设置有至少一个第一断口K1，第二扫描信号线42上设置有至少一个第二断口K2；
覆盖第二导电层的第三绝缘层，第三绝缘层开设有多个过孔；
设置在第三绝缘层上的第三导电层，第三导电层至少包括第一电源线60、数据信号线70、补偿信号线的第一补偿信号线81和第二补偿信号线81、第一信号连接电极91以及第二信号连接电极92，第一信号连接电极91与第一断口K1两侧第一扫描信号线41连接，第二信号连接电极92与第二断口K2两侧的第二扫描信号线42，第一补偿信号线81和第二补偿信号线81通过补偿连接电极83相互连接；
覆盖第三导电层的平坦层，其上开设有多个过孔；
设置在平坦层上的阳极导电层，阳极导电层至少包括阳极301；
像素定义层，其上开设有暴露出阳极301的像素开口302K。
随着显示技术的发展，超大尺寸显示装置的应用越来越广泛。研究表明，由于超大尺寸显示装置的扫描线较长，在干刻过程会出现大量静电，静电集聚会击穿晶体管的沟道，导致面板发生边缘暗点，影响产品良率。本公开示例性实施例提供了一种将扫描信号线分成多段的显示基板，在第一扫描信号线上设置至少一个第一断口，第一断口两侧的第一扫描信号线通过第一信号连接电极相互连接，在第二扫描信号线上设置至少一个第二断口，在第二断口两侧的第二扫描信号线通过第二信号连接电极相互连接，不仅有效减小了干刻过程中扫描信号线产生的静电量，而且避免了因静电集聚导致击穿晶体管沟道的情况，有效避免了显示装置出现边缘暗点，在保证扫描信号连续传输的前提下，提高了良品率，提高了显示品质。
本公开示例性实施例显示基板通过采用透明存储电容，存储电容由透明的透明导电层和透明的半导体层组成，由于光线可以透过透明存储电容出射，因而存储电容可以设置在像素开口内，有效增加了存储电容的电容量，有效增加了像素开口率。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图15为本公开示例性实施例另一种显示基板的结构示意图，示意了一种底发射显示基板中一个像素单元(四个子像素)的驱动电路层的结构。如图15所示，本实施例显示基板的主体结构与前述实施例显示基板的主体结构基本上相同，所不同的是，第一扫描信号线41上设置的第一断口K1通过第一信号连接电极91连接，第二扫描信号线42上的第二断口K2通过第三信号连接电极93、第四信号连接电极94和第五信号连接电极95连接。
在示例性实施方式中，第一扫描信号线41、第一断口K1和第一信号连接电极91的结构可以与前述实施例基本上相同。
在示例性实施方式中，第二扫描信号线42设置有截断第二扫描信号线42的第二断口K2，第二断口K2可以设置在第二子像素P2和第三子像素P3之间，第四信号连接电极94可以设置在第二子像素P2，第五信号连接电极95可以设置在第三子像素P3，第三信号连接电极93的第一端一方面通过过孔与第四信号连接电极94连接，另一方面通过过孔与第二断口K2第二子像素P2一侧的第二扫描信号线42连接，第三信号连接电极93的第二端一方面通过过孔与第五信号连接电极95连接，另一方面通过过孔与第二断口K2第三子像素P3一侧的第二扫描信号线42连接，使得第二断口K2两侧的第二扫描信号线42通过第四信号连接电极94、第三信号连接电极93和第五信号连接电极95实现连接，实现了第二扫描信号线42的连续传输。
在示例性实施方式中，第四信号连接电极94和第五信号连接电极95可以与第一电源线60同层设置，第一扫描信号线41和第二扫描信号线42可以与第一电源线60异层设置。
在示例性实施方式中，第三信号连接电极93具有第三长度L3，第三长度L2可以大于第一电源线60的宽度M。
在示例性实施方式中，第三信号连接电极93的第三长度L3可以小于子像素宽度。
在示例性实施方式中，第三信号连接电极93的第三长度L3可以约为子像素宽度的50％至80％。
在示例性实施方式中，第三信号连接电极93在显示基板上的正投影与第一电源线60和数据信号线70在显示基板上的正投影没有交叠。
在示例性实施方式中，补偿信号线80可以为连续设置的线形状，补偿信号线80在显示基板上的正投影与第三信号连接电极93在显示基板上的正投影至少部分交叠。
在示例性实施方式中，第三信号连接电极93上设置有至少一个通孔，通孔在显示基板上的正投影与补偿信号线80在显示基板上的正投影至少部分重叠。
在示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括在基底上叠设的透明导电层、第一导电层、第一绝缘层、半导体层、第二绝缘层、第二导电层、第三绝缘层和第三导电层。透明导电层可以至少包括存储电容的第一极板，第一导电层可以至少包括电源连接线21、补偿连接线22、遮挡层23第三信号连接电极93，半导体层可以至少包括存储电容的第二极板以及三个晶体管的有源层，第二导电层可以至少包括第一扫描信号线41、第二扫描信号线42以及三个晶体管的栅电极，第三导电层可以至少包括第一电源线60、数据信号线70、补偿信号线80、三个晶体管的第一极和第二极、第一信号连接电极91、第四信号连接电极94和第五信号连接电极95。
在示例性实施方式中，本示例性实施例显示基板的制备过程可以包括如下操作。
(21)形成透明导电层图案。在示例性实施方式中，形成透明导电层图案可以与前述实施例步骤(11)基本上相同，所形成的透明导电层结构与前述实施例的透明导电层结构基本上相同。
(22)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以与前述实施例步骤(12)基本上相同，所形成的第一导电层图案可以 至少包括电源连接线21、补偿连接线22、遮挡层23、层间连接电极24和第三信号连接电极93，如图16所示。
在示例性实施方式中，电源连接线21、补偿连接线22、遮挡层23和层间连接电极24的结构与前述实施例基本上相同，这里不再赘述。
在示例性实施方式中，第三信号连接电极93的形状可以为沿着第一方向X延伸的条形状，可以设置在第二子像素P2和第三子像素P3之间，第三信号连接电极93被配置为通过后续形成的第四信号连接电极和第五信号连接电极使后续形成的第二断口两侧的第二扫描信号线连接起来。
在示例性实施例中，第三信号连接电极93上可以设置有至少一个通孔，通孔在基底上的正投影与后续形成的补偿信号线在基底上的正投影至少部分重叠，以降低第三信号连接电极与补偿信号线之间的寄生电容。
在示例性实施方式中，第三信号连接电极93具有第三长度L3，第三长度L3可以为第三信号连接电极93第一方向X的尺寸，即第三信号连接电极93延伸方向的尺寸。
在示例性实施方式中，第三信号连接电极93的第三长度L3可以大于后续形成的第一电源线60的宽度。
在示例性实施方式中，第三信号连接电极93的第三长度L3可以小于子像素宽度。
在示例性实施方式中，第三信号连接电极93的第三长度L3可以约为子像素宽度的50％至80％。
(23)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以与前述实施例步骤(13)基本上相同，所形成的半导体层结构与前述实施例的半导体层结构基本上相同，如图17所示。
(24)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以与前述实施例步骤(14)基本上相同，所形成的第二导电层结构与前述实施例的第二导电层结构基本上相同，如图18所示。
(25)形成第三绝缘层图案。在示例性实施例中，形成第三绝缘层图案 可以与前述实施例步骤(15)基本上相同，所形成的多个过孔至少包括：第一过孔V1至第十一过孔V11、第十三过孔V13至第十八过孔V18，如图19所示。
在示例性实施方式中，第一过孔V1至第十一过孔V11、第十三过孔V13至第十四过孔V14与前述实施例的过孔基本上相同。
在示例性实施例中，第十五过孔V15和第十七过孔V17可以设置在第二子像素P2。第十五过孔V15在基底上的正投影可以位于第二断口K2一侧的第二扫描信号线42在基底上的正投影的范围之内，第十五过孔V15内的第三绝缘层被刻蚀掉，暴露出第二断口K2一侧的第二扫描信号线42的表面。第十七过孔V17在基底上的正投影可以位于第三信号连接电极93在基底上的正投影的范围之内，第十七过孔V17内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三信号连接电极93的表面。第十五过孔V15和第十七过孔V17被配置为使后续形成的第四信号连接电极通过该过孔分别与第三信号连接电极93和第二断口K2一侧的第二扫描信号线42连接。
在示例性实施方式中，第十六过孔V16和第十八过孔V18可以设置在第三子像素P3。第十六过孔V16在基底上的正投影可以位于第二断口K2另一侧的第二扫描信号线42在基底上的正投影的范围之内，第十六过孔V16内的第三绝缘层被刻蚀掉，暴露出第二断口K2另一侧的第二扫描信号线42的表面。第十八过孔V18在基底上的正投影可以位于第三信号连接电极93在基底上的正投影的范围之内，第十八过孔V18内的第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出第三信号连接电极93的表面。第十六过孔V16和第十八过孔V18被配置为使后续形成的第五信号连接电极通过该过孔分别与第三信号连接电极93和第二断口K2另一侧的第二扫描信号线42连接。
(26)形成第三导电层图案。在示例性实施例中，形成第三导电层可以与前述实施例步骤(16)基本上相同，所形成的第三导电层结构至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第一电源线60、数据信号线70、第一信号连接电极91、第四信号连接电极94和第五信号连接电极95，如图20 所示。
在示例性实施方式中，第一连接电极51至第六连接电极56、第一电源线60、数据信号线70、补偿信号线80和第一信号连接电极91的结构与前述实施例基本上相同，这里不再赘述。
在示例性实施方式中，第四信号连接电极94可以设置在第二子像素P2内，第五信号连接电极95可以设置在第三子像素P3内，第四信号连接电极94和第五信号连接电极95的形状可以为矩形状。第四信号连接电极94一方面通过第十五过孔V15与第二断口K2一侧的第二扫描信号线42连接，另一方面通过第十七过孔V17与第三信号连接电极93连接，使得第二断口K2一侧的第二扫描信号线42和第三信号连接电极93通过第四信号连接电极94连接起来。第五信号连接电极95一方面通过第十六过孔V16与第二断口K2另一侧的第二扫描信号线42连接，另一方面通过第十八过孔V18与第三信号连接电极93连接，使得第二断口K2另一侧的第二扫描信号线42和第三信号连接电极93通过第五信号连接电极95连接起来。这样，使得第二断口K2两侧的第二扫描信号线42通过第四信号连接电极94、第三信号连接电极93和第五信号连接电极95连接起来。
在示例性实施方式中，补偿信号线80设置在第二子像素P2和第三子像素P3之间，补偿信号线80的形状可以为主体部分沿着第二方向Y延伸的条形状，补偿信号线80为连续结构。
在示例性实施方式中，补偿信号线80在基底上的正投影与第三信号连接电极93在基底上的正投影至少部分重叠，补偿信号线80在基底上的正投影与第四信号连接电极94在基底上的正投影没有交叠，补偿信号线80在基底上的正投影与第五信号连接电极95在基底上的正投影没有交叠。
(27)形成平坦层、阳极导电层、像素定义层、有机发光层、阴极以及封装结构层图案。在示例性实施例中，形成平坦层、阳极导电层、像素定义层、有机发光层、阴极以及封装结构层图案可以与前述实施例基本上相同，这里不再赘述。
如图16至图20所示，本公开示例性实施例所提供的显示基板可以包 括：
基底；
设置在基底上的透明导电层，透明导电层至少包括第一极板11；
设置在透明导电层上的第一导电层，第一导电层至少包括电源连接线21、补偿连接线22、遮挡层23和第三信号连接电极93，遮挡层23与第一极板11连接；
覆盖第一导电层的第一绝缘层；
设置在第一绝缘层上的半导体层，半导体层至少包括第一有源层31、第二有源层32、第三有源层33和第二极板34，第一有源层31和第二极板34可以为相互连接的一体结构，第二极板34与第一极板11构成透明的存储电容；
覆盖半导体层的第二绝缘层；
设置在第二绝缘层上的第二导电层，第二导电层至少包括第一扫描信号线41、第二扫描信号线42和第二栅电极43，第一扫描信号线41上设置有至少一个第一断口K1，第二扫描信号线42上设置有至少一个第二断口K2；
覆盖第二导电层的第三绝缘层，第三绝缘层开设有多个过孔；
设置在第三绝缘层上的第三导电层，第三导电层至少包括第一电源线60、数据信号线70、补偿信号线的第一补偿信号线81和第二补偿信号线81、第一信号连接电极91、第四信号连接电极94和第五信号连接电极95，第一信号连接电极91与第一断口K1两侧第一扫描信号线41连接，第二断口K2两侧的第二扫描信号线42通过第四信号连接电极94、第三信号连接电极93和第五信号连接电极95相互连接；
覆盖第三导电层的平坦层，其上开设有多个过孔；
设置在平坦层上的阳极导电层，阳极导电层至少包括阳极；
像素定义层，其上开设有暴露出阳极301的像素开口。
本公开示例性实施例提供了另一种将扫描信号线分成多段的显示基板， 在第一扫描信号线上设置至少一个第一断口，第一断口两侧的第一扫描信号线通过第一信号连接电极相互连接，在第二扫描信号线上设置至少一个第二断口，在第二断口两侧的第二扫描信号线通过第四信号连接电极94、第三信号连接电极93和第五信号连接电极95相互连接，不仅有效减小了干刻过程中扫描信号线产生的静电量，而且避免了因静电集聚导致击穿晶体管沟道的情况，有效避免了显示装置出现边缘暗点，在保证扫描信号连续传输的前提下，提高了良品率，提高了显示品质。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开示例性实施例还提供了一种显示基板的制备方法，所述显示基板可以包括多个子像素；所述制备方法可以包括：
在至少一个子像素中形成像素驱动电路，所述像素驱动电路分别与沿着第一方向延伸的扫描信号线和沿着第二方向延伸的第一电源线连接，所述扫描信号线被配置为向所述像素驱动电路提供扫描信号，所述第一电源线被配置为向所述像素驱动电路提供电源信号，所述第一方向与所述第二方向交叉；所述扫描信号线设置有至少一个截断所述扫描信号线的断口，所述断口两侧的扫描信号线通过信号连接电极相互连接，所述信号连接电极的长度大于所述第一电源线的宽度，所述信号连接电极的长度小于子像素宽度，所述长度为所述信号连接电极所述第一方向的尺寸，所述宽度为所述第一电源线所述第一方向的尺寸，子像素宽度为所述子像素所述第一方向X的尺寸。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (22)

  1. 一种显示基板，包括多个子像素，至少一个子像素包括像素驱动电路，所述像素驱动电路分别与沿着第一方向延伸的扫描信号线和沿着第二方向延伸的第一电源线连接，所述扫描信号线被配置为向所述像素驱动电路提供扫描信号，所述第一电源线被配置为向所述像素驱动电路提供电源信号，所述第一方向与所述第二方向交叉；至少一个子像素中，所述扫描信号线设置有至少一个截断所述扫描信号线的断口，所述断口两侧的扫描信号线通过信号连接电极相互连接，所述信号连接电极的长度大于所述第一电源线的宽度，所述信号连接电极的长度小于子像素宽度，所述长度为所述信号连接电极所述第一方向的尺寸，所述宽度为所述第一电源线所述第一方向的尺寸，子像素宽度为所述子像素所述第一方向X的尺寸。
  2. 根据权利要求1所述的显示基板，其中，所述扫描信号线包括向所述像素驱动电路提供第一扫描信号的第一扫描信号线，所述断口包括截断所述第一扫描信号线的第一断口，所述信号连接电极包括第一信号连接电极，所述第一信号连接电极的第一端通过过孔与所述第一断口一侧的所述第一扫描信号线连接，所述第一信号连接电极的第二端通过过孔与所述第一断口另一侧的所述第一扫描信号线连接，所述第一信号连接电极的长度大于所述第一电源线的宽度，所述第一信号连接电极的长度小于所述子像素宽度。
  3. 根据权利要求2所述的显示基板，其中，所述多个子像素包括沿着所述第一方向依次设置的第一子像素、第二子像素、第三子像素和第四子像素，所述第一断口和第一信号连接电极设置在所述第一子像素内，或者，所述第一断口和第一信号连接电极设置在所述第二子像素内，或者，所述第一断口和第一信号连接电极设置在所述第三子像素内，或者，所述第一断口和第一信号连接电极设置在所述第四子像素内。
  4. 根据权利要求2所述的显示基板，其中，在垂直于显示基板的平面上，所述显示基板包括多个导电层，所述第一信号连接电极和所述第一电源线设置在相同的导电层中，所述第一扫描信号线和所述第一电源线设置在不同的导电层中。
  5. 根据权利要求1所述的显示基板，其中，所述扫描信号线包括向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第二扫描信号线的第二断口，所述信号连接电极包括第二信号连接电极，所述第二信号连接电极的第一端通过过孔与所述第二断口一侧的所述第二扫描信号线连接，所述第二信号连接电极的第二端通过过孔与所述第二断口另一侧的所述第二扫描信号线连接，所述第二信号连接电极的长度大于所述第一电源线的宽度，所述第二信号连接电极的长度小于所述子像素宽度。
  6. 根据权利要求5所述的显示基板，其中，在垂直于显示基板的平面上，所述显示基板包括多个导电层，所述第二信号连接电极和所述第一电源线设置在相同的导电层中，所述第二扫描信号线和所述第一电源线设置在不同的导电层中。
  7. 根据权利要求5所述的显示基板，其中，所述像素驱动电路还与补偿信号线连接，所述补偿信号线被配置为向所述像素驱动电路提供补偿信号；至少一个子像素中，所述补偿信号线至少包括补偿连接电极以及间隔设置的第一补偿信号线和第二补偿信号线，所述补偿连接电极的第一端通过过孔与所述第一补偿信号线连接，所述补偿连接电极的第二端通过过孔与所述第二补偿信号线连接。
  8. 根据权利要求7所述的显示基板，其中，所述补偿连接电极在显示基板上的正投影与所述第二断口在显示基板上的正投影至少部分交叠。
  9. 根据权利要求7所述的显示基板，其中，所述补偿连接电极在显示基板上的正投影与所述第二信号连接电极在显示基板上的正投影至少部分交叠。
  10. 根据权利要求7所述的显示基板，其中，所述第二信号连接电极上设置有至少一个通孔，所述通孔在显示基板上的正投影与所述补偿连接电极在显示基板上的正投影至少部分重叠。
  11. 根据权利要求7所述的显示基板，其中，所述多个子像素包括沿着所述第一方向依次设置的第一子像素、第二子像素、第三子像素和第四子像素，所述第一补偿信号线、第二补偿信号线和补偿连接电极设置在所述第二 子像素和第三子像素之间。
  12. 根据权利要求1所述的显示基板，其中，所述扫描信号线包括向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第二扫描信号线的第二断口，所述信号连接电极包括第三信号连接电极、第四信号连接电极和第五信号连接电极，所述第三信号连接电极的第一端和所述第二断口一侧的所述第二扫描信号线分别通过过孔与所述第四信号连接电极连接，所述第三信号连接电极的第二端和所述第二断口另一侧的所述第二扫描信号线分别通过过孔与所述第五信号连接电极连接，所述第三信号连接电极的长度大于所述第一电源线的宽度，所述第三信号连接电极的长度小于所述子像素宽度。
  13. 根据权利要求12所述的显示基板，其中，在垂直于显示基板的平面上，所述显示基板包括多个导电层，所述第四信号连接电极、所述第五信号连接电极和所述第一电源线设置在相同的导电层中，所述第二扫描信号线和所述第一电源线设置在不同的导电层中。
  14. 根据权利要求12所述的显示基板，其中，所述多个子像素包括沿着所述第一方向依次设置的第一子像素、第二子像素、第三子像素和第四子像素，所述第四信号连接电极设置在所述第二子像素内，所述第五信号连接电极设置在所述第三子像素内。
  15. 根据权利要求1所述的显示基板，其中，所述扫描信号线包括向所述像素驱动电路提供第一扫描信号的第一扫描信号线和向所述像素驱动电路提供第二扫描信号的第二扫描信号线，所述断口包括截断所述第一扫描信号线的第一断口和截断所述第二扫描信号线的第二断口，所述信号连接电极包括第一信号连接电极和第二信号连接电极，所述第一信号连接电极分别通过过孔与所述第一断口两侧的所述第一信号连接电极连接，所述第二信号连接电极分别通过过孔与所述第二断口两侧的所述第二信号连接电极连接。
  16. 根据权利要求1到15任一项所述的显示基板，其中，所述像素驱动电路至少包括存储电容；在垂直于显示基板的平面上，所述显示基板包括在基底上依次设置的透明导电层、第一导电层、半导体层、第二导电层和第三导电层，所述透明导电层至少包括所述存储电容的第一极板，所述半导体层 至少包括所述存储电容的第二极板，所述第二导电层至少包括所述扫描信号线，所述第三导电层至少包括所述第一电源线，所述信号连接电极设置在所述第三导电层中，或者，所述信号连接电极分别设置在所述第一导电层和所述第三导电层中。
  17. 根据权利要求16所述的显示基板，其中，所述扫描信号线包括第一扫描信号线，所述信号连接电极包括第一信号连接电极，所述第一扫描信号线设置在所述第二导电层中，所述第一信号连接电极设置在所述第三导电层中。
  18. 根据权利要求16所述的显示基板，其中，所述扫描信号线包括第二扫描信号线，所述信号连接电极包括第二信号连接电极，所述第二扫描信号线设置在所述第二导电层中，所述第二信号连接电极设置在所述第三导电层中。
  19. 根据权利要求18所述的显示基板，其中，所述第一导电层还包括补偿连接电极，所述第三导电层还包括第一补偿信号线和第二补偿信号线。
  20. 根据权利要求15所述的显示基板，其中，所述扫描信号线包括第二扫描信号线，所述信号连接电极包括第三信号连接电极、第四信号连接电极和第五信号连接电极，所述第二扫描信号线设置在所述第二导电层中，所述第三信号连接电极设置在所述第一导电层中，所述第四信号连接电极和第五信号连接电极设置在所述第三导电层中。
  21. 一种显示装置，其中，包括如权利要求1到20任一项所述的显示基板。
  22. 一种显示基板的制备方法，所述显示基板包括多个子像素，所述制备方法包括：
    在至少一个子像素中形成像素驱动电路，所述像素驱动电路分别与沿着第一方向延伸的扫描信号线和沿着第二方向延伸的第一电源线连接，所述扫描信号线被配置为向所述像素驱动电路提供扫描信号，所述第一电源线被配置为向所述像素驱动电路提供电源信号，所述第一方向与所述第二方向交叉；所述扫描信号线设置有至少一个截断所述扫描信号线的断口，所述断口两侧 的扫描信号线通过信号连接电极相互连接，所述信号连接电极的长度大于所述第一电源线的宽度，所述信号连接电极的长度小于子像素宽度，所述长度为所述信号连接电极所述第一方向的尺寸，所述宽度为所述第一电源线所述第一方向的尺寸，子像素宽度为所述子像素所述第一方向X的尺寸。
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CN102645801A (zh) * 2011-04-07 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管阵列基板、彩膜基板、制作方法和显示设备
CN104253159A (zh) * 2014-08-19 2014-12-31 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
US20210013299A1 (en) * 2018-03-26 2021-01-14 Sharp Kabushiki Kaisha Method for manufacturing display device and display device

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Publication number Priority date Publication date Assignee Title
CN102645801A (zh) * 2011-04-07 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管阵列基板、彩膜基板、制作方法和显示设备
CN104253159A (zh) * 2014-08-19 2014-12-31 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
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