WO2022160535A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2022160535A1
WO2022160535A1 PCT/CN2021/096915 CN2021096915W WO2022160535A1 WO 2022160535 A1 WO2022160535 A1 WO 2022160535A1 CN 2021096915 W CN2021096915 W CN 2021096915W WO 2022160535 A1 WO2022160535 A1 WO 2022160535A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
electrode plate
conductive layer
layer
Prior art date
Application number
PCT/CN2021/096915
Other languages
English (en)
French (fr)
Inventor
郑灿
王丽
韩龙
朱健超
刘利宾
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/764,993 priority Critical patent/US20230200129A1/en
Priority to CN202180001335.3A priority patent/CN115298830A/zh
Priority to DE112021001804.3T priority patent/DE112021001804T5/de
Publication of WO2022160535A1 publication Critical patent/WO2022160535A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • This article relates to the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • the application provides a display substrate, the display substrate includes a base and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit includes a plurality of transistors, at least A transistor includes an active layer and two gate electrodes; the substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, There is an overlapping area between the orthographic projection of the electrode plate on the substrate and the orthographic projection of the active layer between the two gate electrodes on the substrate.
  • the plurality of conductive layers include a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on a side of the semiconductor layer away from the substrate, and the electrode plate is disposed on the side of the semiconductor layer. on the first conductive layer, the second conductive layer or the third conductive layer.
  • the display substrate further includes a first power supply line connected to the pixel driving circuit, and at least one electrode plate is connected to the first power supply line.
  • the plurality of transistors include at least a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; a first electrode of the first transistor is connected to a data signal line, so The second pole of the first transistor is connected to the third node; the first pole of the second transistor is connected to the first node, and the second pole of the second transistor is connected to the fourth node; The gate electrode is connected to the first node, the first pole of the third transistor is connected to the first power supply line, the second pole of the third transistor is connected to the fourth node; the first pole of the fourth transistor is connected to the initial The signal line is connected, the second pole of the fourth transistor is connected to the first node; the first pole of the fifth transistor is connected to the first power line, and the second pole of the fifth transistor is connected to the second node.
  • the pixel driving circuit further includes a storage capacitor and a threshold capacitor, the storage capacitor includes a first plate of the storage capacitor and a second plate of the storage capacitor, and the threshold capacitor includes a first plate of the threshold capacitor and the second plate of the threshold capacitor; the first plate of the storage capacitor is connected to the third node, the second plate of the storage capacitor is connected to the second node; the first plate of the threshold capacitor is connected to the third node The first node is connected, and the second electrode plate of the threshold capacitor is connected to the second node.
  • the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are arranged on the first conductive layer, and the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are arranged at intervals, The first electrode plate of the storage capacitor does not overlap with the semiconductor layer.
  • the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor are arranged on the second conductive layer, and the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor are connected to each other,
  • the orthographic projection of the second electrode plate of the storage capacitor on the substrate and the orthographic projection of the first electrode plate of the storage capacitor on the substrate have an overlapping area
  • the second electrode plate of the threshold capacitor is on the substrate.
  • the orthographic projection of , and the orthographic projection of the first electrode plate of the threshold capacitor on the substrate have an overlapping area.
  • the fifth transistor is a double-gate transistor, and the fifth transistor includes at least a fifth active layer and two fifth gate electrodes; the electrode plate includes a first electrode plate, and the fifth transistor includes a first electrode plate. There is an overlapping area between the orthographic projection of an electrode plate on the substrate and the orthographic projection of the fifth active layer located between the two fifth gate electrodes on the substrate.
  • the two fifth gate electrodes are disposed on the first conductive layer, the first electrode plate is disposed on the first conductive layer or the second conductive layer, and the first power line is disposed on the third conductive layer, and the first power line is connected to the first electrode plate through a via hole.
  • the second conductive layer further includes a first power supply connection line, the first electrode plate is connected to the first power supply connection line, and the first power supply line is connected to the first power supply line through a via hole. A power cable is connected.
  • the second transistor is a double-gate transistor, and the second transistor includes at least a second active layer and two second gate electrodes; the electrode plate includes a second electrode plate, and the first There is an overlapping area between the orthographic projection of the two electrode plates on the substrate and the orthographic projection of the second active layer located between the two second gate electrodes on the substrate.
  • the two second gate electrodes are disposed on the first conductive layer, the second electrode plate is disposed on the first conductive layer or the second conductive layer, and the third conductive layer A first connection electrode is also provided, and the first connection electrode is connected to the second electrode plate through a via hole.
  • the first connection electrode serves as the second electrode of the first transistor, and is connected to the first electrode plate of the storage capacitor through a via hole.
  • the fourth transistor is a double-gate transistor, and the fourth transistor includes at least a fourth active layer and two fourth gate electrodes; the first connection electrodes are on the first power supply line. There is an overlapping area between the orthographic projection and the orthographic projection of the fourth active layer located between the two fourth gate electrodes on the first power supply line.
  • the third conductive layer is further provided with a second connection electrode, and the second connection electrode simultaneously serves as the first electrode of the second transistor and the second electrode of the fourth transistor, so The second connection electrode is connected to the first electrode plate of the threshold capacitor through a via hole.
  • the third conductive layer is further provided with a second connection electrode, the third connection electrode serves as a first electrode of the fourth transistor, and the third connection electrode is connected to the third connection electrode through a via hole.
  • the orthographic projection of the third connection electrode on the substrate and the orthographic projection of the fourth active layer between the two gate electrodes of the fourth transistor on the substrate have an overlapping area.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the pixel driving circuit includes a plurality of sub-pixels transistors, at least one transistor includes an active layer and two gate electrodes; the preparation method includes:
  • a semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate are formed on the substrate, at least one conductive layer is provided with at least one electrode plate, the orthographic projection of the electrode plate on the substrate There is an overlapping area with the orthographic projection of the active layer between the two gate electrodes on the substrate.
  • forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate include:
  • a first conductive layer, a second conductive layer and a third conductive layer are sequentially formed on the semiconductor layer, and the electrode plate is on the first conductive layer, the second conductive layer or the third conductive layer.
  • At least one conductive layer is provided with a first power supply line connected to the pixel driving circuit, and at least one electrode plate is connected to the first power supply line.
  • 1 is a schematic structural diagram of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed
  • FIG. 8 is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of an exemplary embodiment of the present disclosure after a fifth insulating layer pattern is formed;
  • FIG. 13 is a schematic diagram of an exemplary embodiment of the present disclosure after a fourth conductive layer pattern is formed
  • FIG. 14 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • 101 substrate
  • 102 drive circuit layer
  • 103 light emitting device
  • 104 encapsulation layer
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited to this, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be carried out according to actual needs. Adjustment.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only schematic structural diagrams, and an embodiment of the present disclosure is not limited to the figures. The shape or value shown in the figure, etc.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the OLED display device may include a scan signal driver, a data signal driver, a lighting signal driver, an OLED display substrate, a first power supply unit, a second power supply unit and an initial power supply unit.
  • the OLED display substrate includes at least a plurality of scan signal lines (S 1 to SN ), a plurality of data signal lines (D 1 to DM ), and a plurality of light emission signal lines (EM 1 to EM N )
  • the scan signal driver is configured to sequentially provide scan signals to the plurality of scan signal lines (S 1 to S N )
  • the data signal driver is configured to provide data signals to the plurality of data signal lines (D 1 to DM )
  • the light-emitting signal The driver is configured to sequentially supply light emission control signals to the plurality of light emission signal lines (EM 1 to EM N ).
  • the plurality of scan signal lines and the plurality of light emitting signal lines extend in the horizontal direction
  • the plurality of data signal lines extend in the vertical direction.
  • the display device includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device, and the pixel driving circuit of one sub-pixel can be connected to a scanning signal line, a light-emitting control line and a data signal line.
  • the first power supply unit, the second power supply unit and the initial power supply unit are respectively configured to supply the first power supply voltage, the second power supply voltage and the initial power supply voltage to the pixel driving circuit through the first power supply line, the second power supply line and the initial signal line.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a sub-pixel P1 that emits light of a second color.
  • the second sub-pixel P2 and the third sub-pixel P3 emitting light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light-emitting signal line. Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, and blue sub-pixels and white (W) sub-pixels, which are not limited in this disclosure.
  • the shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagon or hexagonal.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. The arrangement is not limited in this disclosure.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light emitting device 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and a light emitting device 103 disposed on the side
  • the encapsulation layer 104 on the side of the device 103 away from the substrate 101 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and FIG. 3 takes the example of including one driving transistor and one storage capacitor in each sub-pixel for illustration.
  • the driving circuit layer 102 of each sub-pixel may include: a first insulating layer disposed on the substrate; an active layer disposed on the first insulating layer; and a second insulating layer covering the active layer The grid electrode and the first polar plate arranged on the second insulating layer; the third insulating layer covering the grid electrode and the first polar plate; the second polar plate arranged on the third insulating layer;
  • the fourth insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are provided with via holes, and the via holes expose the active layer; the source electrode and the drain electrode arranged on the fourth insulating layer, the source electrode and the The drain electrodes are respectively connected with the active layer through via holes; the flat layer covering the
  • the light emitting device 103 may include an anode 301 , a pixel definition layer 302 , an organic light emitting layer 303 and a cathode 304 .
  • the anode 301 is arranged on the flat layer, and is connected to the drain electrode of the driving transistor 210 through a via hole opened on the flat layer;
  • the pixel definition layer 302 is arranged on the anode 301 and the flat layer, and a pixel opening is arranged on the pixel definition layer 302, and the pixel opening
  • the anode 301 is exposed;
  • the organic light-emitting layer 303 is at least partially disposed in the pixel opening, and the organic light-emitting layer 303 is connected to the anode 301;
  • the cathode 304 is disposed on the organic light-emitting layer 303, and the cathode 304 is connected to the organic light-emitting layer 303;
  • the anode 301 and the cathode 304 are driven to emit
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials.
  • the second encapsulation layer 402 can be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting device 103 .
  • the organic light emitting layer 303 may include at least a hole injection layer, a hole transport layer, a light emitting layer and a hole blocking layer stacked on the anode 301 .
  • the hole injection layers of all subpixels are a common layer connected together
  • the hole transport layers of all subpixels are a common layer connected together
  • the light emitting layers of adjacent subpixels may have a small amount of Overlapping, or possibly isolated, hole blocking layers are common layers that are joined together.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T2C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit, illustrating an 8T2C structure. As shown in FIG.
  • the pixel driving circuit may include 8 switching transistors (the first transistor T1 to the eighth transistor T8 ), 2 capacitors (the storage capacitor Cst and the threshold capacitor CVth), and the pixel driving circuit is respectively connected with 9 signal lines , the 9 signal lines include the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the light-emitting signal line EM, the reference signal line REF, the initial signal line INIT, the data signal line DATA, the first power supply line VDD and the second power supply line VSS.
  • the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the data signal line DATA, and the second electrode of the first transistor is connected to the second node N3 connect.
  • the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the fourth node N4.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first power supply line VDD, and the second electrode of the third transistor T3 is connected to the fourth node N4.
  • the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the initial signal line INIT, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the gate electrode of the fifth transistor T5 is connected to the third scan signal line S3, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the gate electrode of the sixth transistor T6 is connected to the second scan signal line S2, the first electrode of the sixth transistor T6 is connected to the initial signal line INIT, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the gate electrode of the seventh transistor T7 is connected to the light emitting signal line EM, the first electrode of the seventh transistor T7 is connected to the fourth node N4, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the gate electrode of the eighth transistor T8 is connected to the light-emitting signal line EM, the first pole of the eighth transistor T8 is connected to the reference signal line REF, and the second pole of the eighth transistor T8 is connected to the third node N3.
  • the first end of the threshold capacitor CVth is connected to the first node N1, and the second end of the threshold capacitor CVth is connected to the second node N2.
  • the first end of the storage capacitor Cst is connected to the second node N2, and the second end of the storage capacitor Cst is connected to the third node N3.
  • the first to eighth transistors T1 to T8 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to eighth transistors T1 to T8 may include P-type transistors and N-type transistors.
  • the second pole of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuous high-level signal.
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the display row
  • the third scan signal line S3 is the scan signal line in the pixel driving circuit of the previous display row.
  • the second scanning signal line S2 is S(n)
  • the third scanning signal line S3 is S(n-1)
  • the third scanning signal line S3 of this display line is the same as the first line in the pixel driving circuit of the previous display line.
  • the two scan signal lines S2 can be the same signal line, or in other words, the second scan signal line S2 of the current display line and the third scan signal line S3 in the pixel driving circuit of the next display line can be the same signal line, so as to reduce the number of display panels
  • the signal line of the display panel can realize the narrow border of the display panel.
  • the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the emission signal line EM, and the initial signal line INIT may extend in a horizontal direction
  • the data signal line DATA, the first The power line VDD, the second power line VSS and the reference signal line REF may extend in a vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a working timing diagram of a pixel driving circuit.
  • the pixel driving circuit in FIG. 4 includes 8 switching transistors (the first transistor T1 to the eighth transistor T8 ), 2 capacitors (storage capacitors) Cst and threshold capacitance CVth) and 9 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, light-emitting signal line EM, reference signal line REF, initial signal line INIT, data signal line DATA, the first power supply line VDD and the second power supply line VSS), the eight transistors are all P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset and data refresh stage.
  • the signals of the first scanning signal line S1 and the third scanning signal line S3 are low-level signals, and the signals of the second scanning signal line S2 and the light-emitting signal line EM are high-level signals. flat signal.
  • the signal of the first scan signal line S1 is a low-level signal, so that the first transistor T1 and the fourth transistor T4 are turned on.
  • the first transistor T1 is turned on so that the data voltage output from the data signal line DATA is supplied to the third node N3, and the third node N3 writes the data voltage Vdt.
  • the fourth transistor T4 is turned on so that the initial signal of the initial signal line INIT is supplied to the first node N1, and the first node N1 is reset to the initial voltage Vinit.
  • the signal of the third scanning signal line S3 is a low level signal, which turns on the fifth transistor T5, the power supply voltage output from the first power supply line VDD is supplied to the second node N2, and the second node N2 writes the power supply voltage Vdd.
  • the second stage A2 is called the threshold value acquisition stage.
  • the signals of the second scanning signal line S2 and the third scanning signal line S3 are low-level signals, and the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals. .
  • the signal of the third scanning signal line S3 is a low level signal, so that the fifth transistor T5 continues to be turned on, the power supply voltage output by the first power supply line VDD is supplied to the second node N2, and the second node N2 maintains the power supply voltage Vdd.
  • the signal of the second scanning signal line S2 is a low-level signal, so that the second transistor T2 and the sixth transistor T6 are turned on.
  • the second transistor T2 is turned on so that the first node N1 and the fourth node N4 have the same potential, the third transistor T3 forms a "diode connection" structure, the first power line VDD charges the first node N1, and the first node N1 charges to Vdd- After the
  • the sixth transistor T6 is turned on so that the initial signal of the initial signal line INIT is supplied to the first electrode of the OLED, and the first electrode of the OLED is reset to the initial voltage Vinit.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scan signal line S1 , the second scan signal line S2 and the third scan signal line S3 are high-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal, so that the seventh transistor T7 and the eighth transistor T8 are turned on.
  • the seventh transistor T7 is turned on, the potential of the first node N1 makes the third transistor T3 turn on, and the power supply voltage output by the first power supply line VDD is supplied to the first electrode of the OLED through the turned-on third transistor T3 and the seventh transistor T7
  • the driving voltage drives the OLED to emit light.
  • the eighth transistor T8 is turned on so that the reference signal of the reference signal line REF is supplied to the third node N3, and the potential of the third node N3 changes from the data voltage Vdt to the reference voltage Vref. After the signals are superimposed, the potential of the first node N1 becomes: Vdd-
  • the signal of the first scan signal line S1 is a low level signal, which turns on the first transistor T1, the data signal line DATA outputs the data voltage to the second node N2, and the second node N2 writes the data voltage Vdt.
  • the potential of the first node N1 is Vdd-
  • the driving current flowing through the third transistor T3 driving transistor is determined by the voltage difference between its gate electrode and the first electrode, and thus flows through the third transistor according to the potential of the first node N1
  • the drive current of T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • ⁇ is a constant
  • Vdt is the data voltage output by the data signal line DATA
  • Vref is the reference voltage output by the reference signal line REF.
  • the potential of the first node N1 is the initial voltage Vinit
  • the potential of the second node N2 is the power supply voltage Vdd
  • the potential of the third node N3 is the data voltage Vdt.
  • the potential of the first node N1 is Vdd-
  • the potential of the second node N2 is the power supply voltage Vdd
  • the potential of the third node N3 is the data voltage Vdt.
  • the potential of the first node N1 is Vdd-
  • the potential of the second node N2 is Vdd+Vref-Vdt
  • the potential of the third node N3 is the reference voltage Vref.
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of three sub-pixels.
  • the sub-pixels of the display substrate are provided with a first scan signal line 21 and two second scan signal lines 22 (the second scan signal line 22-1 and the second scan signal line scan signal line 22-2), third scan signal line 23, light emission control line 24, initial signal line 31, first power supply line 71, reference signal line 72, data signal line 73, second power supply line 74, pixel drive circuit and light-emitting device
  • the pixel drive circuit may include a storage capacitor, a threshold capacitor and a plurality of transistors, each transistor includes an active layer, a gate electrode, a first electrode and a second electrode, the storage capacitor includes a storage capacitor first plate 26 and a storage capacitor.
  • the second electrode plate 34 of the capacitor, and the threshold capacitor includes the first electrode plate 27 of the threshold capacitor and the second electrode plate 35 of the threshold capacitor.
  • the pixel driving circuit is connected to the first power supply line 71, and the first power supply line 71 provides a high-level signal to the pixel driving circuit.
  • at least one transistor is a dual-gate transistor including an active layer, two gate electrodes, a first electrode and a second electrode.
  • the display substrate further includes at least one electrode plate, and an orthographic projection of the at least one electrode plate on the substrate and an orthographic projection of the active layer located between the two gate electrodes on the substrate have an overlapping area, At least one electrode plate is connected to the first power line 71 .
  • the display substrate may include a semiconductor layer and a plurality of conductive layers arranged in sequence on the substrate, and at least one of the conductive layers is provided with an electrode plate.
  • the plurality of conductive layers may include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the semiconductor layer, and at least one electrode plate may be disposed on the first conductive layer layer or the second conductive layer, the first power line 71 is arranged on the third conductive layer, and the first power line 71 is connected to the electrode plate through a via hole.
  • the semiconductor layer may include an active layer of a plurality of transistors
  • the first conductive layer may include a first scan signal line 21, a second scan signal line 22-1, a second scan signal line 22-2
  • the third scanning signal line 23 the light-emitting control line, the first electrode plate 26 of the storage capacitor and the first electrode plate 27 of the threshold capacitor
  • the second conductive layer may include the initial signal line 31, the second electrode plate 34 of the storage capacitor and the second electrode plate 34 of the threshold capacitor
  • the third conductive layer may include a first power line 71 , a reference signal line 72 and a data signal line 73
  • the fourth conductive layer may include a second power line 74 .
  • the first scan signal line 21, the second scan signal line 22-1, the second scan signal line 22-2, the third scan signal line 23 and the light emission control line 24 extend along the first direction X
  • the first electrode plate 26 of the storage capacitor and the first electrode plate 27 of the threshold capacitor are arranged at intervals.
  • the initial signal line 31 extends along the first direction X
  • the second electrode plate 34 of the storage capacitor and the second electrode plate 35 of the threshold capacitor are an integral structure connected to each other.
  • the first power line 71 , the reference signal line 72 , the data signal line 73 and the second power line 74 extend along the second direction Y.
  • the first direction X may be the extension direction of the scan signal lines
  • the second direction Y may be the extension direction of the data signal lines.
  • the second conductive layer may include a reference signal connection line 32 and a first power supply connection line 33 .
  • the reference signal connection line 32 and the first power supply connection line 33 both extend along the first direction X, the reference signal connection line 32 is connected with the reference signal line 72, and the first power supply connection line 33 is connected with the first power supply line 71, so that a sub-pixel row is Each sub-pixel has the same reference voltage and power supply voltage to improve display uniformity.
  • the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5; the first electrode of the first transistor T1 and the data signal line 74 connected, the second pole of the first transistor T1 is connected to the first plate 26 of the storage capacitor; the first pole of the second transistor T2 is connected to the first plate 27 of the threshold capacitor, and the second pole of the second transistor T2 is connected to the third transistor The second pole of T3 is connected; the gate electrode of the third transistor T3 is connected to the first plate 27 of the threshold capacitor; the first pole of the third transistor T3 is connected to the first power line 71; the first pole of the fourth transistor T4 is connected to the initial The signal line 31 is connected, the second pole of the fourth transistor T4 is connected to the first plate 27 of the threshold capacitor; the first pole of the fifth transistor T5 is connected to the first power line 71, and the second pole of the fifth transistor T5 is connected to the storage capacitor
  • the second electrode plate 34 is connected to
  • the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are dual gate transistors.
  • the second conductive layer may include the first electrode plate 36 and the second electrode plate 37 .
  • the first electrode plate 36 is configured to introduce a first parasitic capacitance at the double gate intermediate node of the fifth transistor T5, and the second electrode plate 37 is configured to introduce a second parasitic capacitance at the double gate intermediate node of the second transistor T2.
  • the third conductive layer may include a first connection electrode 41 configured to introduce a third parasitic capacitance at a double-gate intermediate node of the fourth transistor T4.
  • the first electrode plate 36 is directly connected with the first power connection line 33
  • the second electrode plate 37 is connected with the first connection electrode 41 through via holes.
  • the third conductive layer may include a first connection electrode 41 , a second connection electrode 42 , a third connection electrode 43 , a fourth connection electrode 44 , a fifth connection electrode 45 and a sixth connection electrode 46 .
  • the first connection electrode 41 simultaneously serves as the second electrode of the first transistor T1 and the second electrode of the eighth transistor T8, the second connection electrode 42 simultaneously serves as the first electrode of the second transistor T2 and the second electrode of the fourth transistor T4,
  • the third connection electrode 43 simultaneously serves as the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6, the fourth connection electrode 44 simultaneously serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7
  • the fifth connection electrode 45 simultaneously serves as the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the seventh transistor T7, and the sixth connection electrode 46 serves as the second electrode of the fifth transistor T5.
  • the fourth conductive layer may include an anode connection electrode 51 configured to connect the fourth connection electrode 44 and an anode of the light emitting device and a second power supply connection line 52 along the second power supply connection line 52
  • the second power supply line 74 extends in the first direction X, so that each subpixel in a subpixel row has the same second power supply voltage, which improves display uniformity.
  • the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, the first insulating layer is disposed between the substrate and the semiconductor layer, and the first insulating layer is disposed between the substrate and the semiconductor layer.
  • the second insulating layer is provided between the semiconductor layer and the first conductive layer
  • the third insulating layer is provided between the first conductive layer and the second conductive layer
  • the fourth insulating layer is provided between the second conductive layer and the third conductive layer
  • the fifth insulating layer is arranged between the third conductive layer and the fourth conductive layer.
  • the display substrate provided by the exemplary embodiments of the present disclosure, by setting parasitic capacitances at the double-gate intermediate nodes of the dual-gate transistors, the instantaneous high voltage of the double-gate intermediate nodes is avoided, the reverse leakage of the double-gate intermediate nodes is eliminated, and the key is effectively stabilized.
  • the potential of the node can ensure the accuracy of the driving current and improve the display effect.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process" mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other processes, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, coating can use any one or more of spraying, spin coating and inkjet printing, etching can use dry etching and wet etching Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes. If the “film” does not require a patterning process during the entire fabrication process, the “film” can also be referred to as a "layer”. If the "thin film” needs a patterning process during the whole production process, it is called a “thin film” before the patterning process, and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. In the present disclosure, “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • A's orthographic projection includes B's orthographic projection means that the boundary of B's orthographic projection falls within the boundary of A's orthographic projection, or the boundary of A's orthographic projection overlaps with the boundary of B's orthographic projection.
  • the preparation process of the display substrate may include the following operations.
  • a semiconductor layer pattern is formed.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate The semiconductor layer on the first insulating layer is shown in FIG. 7 .
  • the semiconductor layer of the at least one sub-pixel may include the first active layer of the first transistor T1 to the eighth active layer of the eighth transistor T8, the first active layer 11 of the first transistor T1 and the eighth active layer of the eighth transistor T8.
  • the eighth active layer 18 of the eighth transistor T8 is an integral structure connected to each other, the second active layer 12 of the second transistor T2 and the third active layer 13 of the third transistor T3 are an integral structure connected to each other, the sixth The sixth active layer 16 of the transistor T6 and the seventh active layer 17 of the seventh transistor T7 are integral structures connected to each other, the fourth active layer 14 of the fourth transistor T4 is provided separately, and the fifth transistor T5 The active layer 15 is provided separately.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the first region 11-1 of the first active layer 11 is provided separately, and the second region 11-2 of the first active layer 11 simultaneously serves as the second region 18-2 of the eighth active layer 18. 2, that is, the second region 11-2 of the first active layer 11 and the second region 18-2 of the eighth active layer 18 are connected to each other.
  • the first region 12-1 of the second active layer 12 is provided separately, and the second region 12-2 of the second active layer 12 simultaneously serves as the second region 13-1 of the third active layer 13. 2, that is, the second region 12-2 of the second active layer 12 and the second region 13-2 of the third active layer 13 are connected to each other.
  • the first region 13-1 of the third active layer 13 is provided separately, and the second region 13-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12. 2, that is, the second region 13-2 of the third active layer 13 and the second region 12-2 of the second active layer 12 are connected to each other.
  • first region 14-1 of the fourth active layer 14 and the second region 14-2 of the fourth active layer 14 are each provided separately. Both the first region 15-1 of the fifth active layer 15 and the second region 15-2 of the fifth active layer 15 are provided separately.
  • the first region 16-1 of the sixth active layer 16 is provided separately, and the second region 16-2 of the sixth active layer 16 simultaneously serves as the second region 17-2 of the seventh active layer 17. 2, that is, the second region 16-2 of the sixth active layer 16 and the second region 17-2 of the seventh active layer 17 are connected to each other.
  • the first region 17-1 of the seventh active layer 17 is provided separately, and the second region 17-2 of the seventh active layer 17 simultaneously serves as the second region 16-2 of the sixth active layer 16. 2, that is, the second region 17-2 of the seventh active layer 17 and the second region 16-2 of the sixth active layer 16 are connected to each other.
  • the first region 18-1 of the eighth active layer 18 is provided separately, and the second region 18-2 of the eighth active layer 18 simultaneously serves as the second region 11-2 of the first active layer 11. 2, that is, the second region 18-2 of the eighth active layer 18 and the second region 11-2 of the first active layer 11 are connected to each other.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, and patterning the first metal film through a patterning process to form A second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22-1, a first scan signal line 22-1, a Two scan signal lines 22 - 2 , a third scan signal line 23 , a light emission control line 24 , a first electrode plate 26 of a storage capacitor and a first electrode plate 27 of a threshold capacitor, as shown in FIG. 8 .
  • the first scan signal line 21 , the second scan signal line 22 - 1 , the second scan signal line 22 - 2 , the third scan signal line 23 and the light emission control line 24 may be along the first direction X extend.
  • the first electrode plate 26 of the storage capacitor and the first electrode plate 27 of the threshold capacitor are arranged at intervals, and both are arranged between the second scanning signal line 22-2 and the third scanning signal line 23, and the first electrode plate 26 of the storage capacitor is close to the third scanning signal line 23-2.
  • the first electrode plate 27 of the threshold capacitor is close to the second scanning signal line 22-2.
  • the first scan signal line 21 is arranged on the side of the second scan signal line 22-2 away from the first electrode plate 27 of the threshold capacitor, and the light emission control line 24 is arranged on the side of the first scan signal line 21 away from the third scan signal line 23 .
  • the second scan signal line 22-1 and the second scan signal line 22-2 are connected to the same signal source and output the same signal.
  • the outline of the first electrode plate 26 of the storage capacitor may be rectangular, and the corners may be chamfered.
  • the outline of the first electrode plate 27 of the threshold capacitor may be rectangular, and the rectangular shape may be provided with grooves near the corners of the first region of the third active layer 13 , and the corners may be provided with chamfers.
  • the first scan signal line 21, the second scan signal line 22-1, the second scan signal line 22-2, the third scan signal line 23 and the light emission control line 24 may be set to have equal widths, or It can be set to unequal width, and the width is the dimension of the second direction Y.
  • a plurality of first gate blocks and a plurality of second gate blocks may be disposed on the third scan signal line 23 (which is also the second scan signal line of the sub-pixels in the previous sub-pixel row).
  • a first gate block and a second gate block may be set in each sub-pixel.
  • One end of the first gate block is connected to the third scan signal line 23, and the other end extends along the second direction Y.
  • the second gate block One end is connected to the third scan signal line 23, the other end extends along the opposite direction of the second direction Y, and the first gate block and the second gate block are configured to form a double gate electrode.
  • the region where the first scan signal line 21 overlaps with the first active layer 11 serves as the gate electrode of the first transistor T1
  • the region where the first scan signal line 21 overlaps with the fourth active layer 14 is used as the gate electrode of the first transistor T1
  • the region where the second scanning signal line 22-2 overlaps with the second active layer 12 is used as the gate electrode of the second transistor T2 (dual gate structure)
  • the second scanning The region where the signal line 22-1 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6, and the region where the third scanning signal line 23 and the fifth active layer 15 overlap serves as the gate electrode of the fifth transistor T5 (Double gate structure)
  • the area where the light emission control line 24 and the seventh active layer 17 overlap serves as the gate electrode of the seventh transistor T7
  • the area where the light emission control line 24 and the eighth active layer 18 overlap serves as the eighth transistor T8
  • the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all switching transistors
  • the third transistor T3 is a driving transistor.
  • the orthographic projection of the first electrode plate 26 of the storage capacitor on the substrate has no overlapping area with the orthographic projection of the third active layer 13 on the substrate.
  • the storage capacitor first plates 26 of adjacent sub-pixels in a sub-pixel row are arranged in isolation, and the threshold capacitor first plates 27 of adjacent sub-pixels are arranged in isolation.
  • the first conductive layer may be used as a shield to conduct a conductorization process on the semiconductor layer, and the semiconductor layers in the shielded regions of the first conductive layer form the first transistors T1 to T1 to eighth In the channel region of the transistor T8, the semiconductor layer in the region not shielded by the first conductive layer is conductive, that is, the first and second regions from the first active layer to the eighth active layer are all conductive.
  • a second conductive layer pattern is formed.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film using a patterning process to form A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least includes: an initial signal line 31, a reference signal connection line 32, and a first power supply connection line 33.
  • the storage capacitor second plate 34 and the threshold capacitor second plate 35 are disposed between the second scan signal line 22-2 and the third scan signal line 23, the storage capacitor second plate 34 and The second electrode plate 35 of the threshold capacitor may be an integral structure connected to each other.
  • the storage capacitor second electrode plate 34 and the threshold capacitor second electrode plate 35 of the integrated structure may be rectangular, and the corners of the rectangular shape may be provided with chamfers.
  • the orthographic projection of the second electrode plate 34 of the storage capacitor on the substrate and the orthographic projection of the first electrode plate 26 of the storage capacitor on the substrate have an overlapping area.
  • the second electrode plate 34 of the storage capacitor is provided with a first opening 34-1.
  • the first opening 34-1 can be a rectangle and is located in the middle of the second electrode plate 34 of the storage capacitor.
  • the first opening 34-1 allows the second electrode of the storage capacitor to be opened.
  • the plate 34 forms an annular structure.
  • the first opening 34-1 exposes the third insulating layer covering the first electrode plate 26 of the storage capacitor, and the orthographic projection of the first electrode plate 26 of the storage capacitor on the substrate includes the orthographic projection of the first opening 34-1 on the substrate.
  • the first opening 34-1 is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the first opening 34-1 and exposes the first electrode plate 26 of the storage capacitor, so that the subsequent via hole is located in the first opening 34-1 and exposes the first electrode plate 26 of the storage capacitor.
  • the formed first connection electrode is connected to the first electrode plate 26 of the storage capacitor through the first via hole.
  • the orthographic projection of the threshold capacitor second plate 35 on the substrate and the orthographic projection of the threshold capacitor first plate 27 on the substrate have an overlapping area.
  • the second electrode plate 35 of the threshold capacitor is provided with a second opening 35-1.
  • the second opening 35-1 can be rectangular and is located in the middle of the second electrode plate 35 of the threshold capacitor.
  • the second opening 35-1 makes the second electrode of the threshold capacitor 35-1.
  • the plate 35 forms an annular structure.
  • the second opening 35-1 exposes the third insulating layer covering the first threshold capacitor plate 27, and the orthographic projection of the first threshold capacitor plate 27 on the substrate includes the orthographic projection of the second opening 35-1 on the substrate.
  • the second opening 35-1 is configured to accommodate a second via hole formed later, the second via hole is located in the second opening 35-1 and exposes the first electrode plate 27 of the threshold capacitor, so that the subsequent via hole is located in the second opening 35-1 and exposes the first electrode plate 27 of the threshold capacitor.
  • the formed second connection electrode is connected to the first electrode plate 27 of the threshold capacitor through the second via hole.
  • the storage capacitor first plate 26 and the storage capacitor second plate 34 constitute the storage capacitor Cst of the pixel driving circuit
  • the storage capacitor first plate 26 serves as the second end of the storage capacitor Cst
  • the storage capacitor first The diode plate 34 serves as the first terminal of the storage capacitor Cst.
  • the first electrode plate 27 of the threshold capacitor and the second electrode plate 35 of the threshold capacitor constitute the threshold capacitor CVth of the pixel driving circuit.
  • the first electrode plate 27 of the threshold capacitor serves as the first end of the threshold capacitor CVth and serves as the gate electrode of the third transistor T3.
  • the second electrode plate 35 of the threshold capacitor serves as the second terminal of the threshold capacitor.
  • the first end of the storage capacitor Cst and the second end of the threshold capacitor CVth are connected to each other, and the first end of the storage capacitor Cst simultaneously serves as the second end of the threshold capacitor CVth.
  • the storage capacitor second plates 34 of adjacent sub-pixels in a sub-pixel row are arranged at intervals, and the threshold capacitor second plates 35 of adjacent sub-pixels in a sub-pixel row are arranged at intervals.
  • the initial signal line 31 , the reference signal connection line 32 and the first power supply connection line 33 extend along the first direction X, and the initial signal line 31 is disposed at the position of the light emission control line 24 away from the first scan signal line 21 .
  • the reference signal connecting line 32 and the first power supply connecting line 33 are arranged between the third scanning signal line 23 and the first plate 26 of the storage capacitor, the reference signal connecting line 32 is close to the first plate 26 of the storage capacitor, the first The power connection line 33 is close to the third scan signal line 23 .
  • the reference signal connection line 32 is configured to be connected to a subsequently formed reference signal line, so the reference signal connection line 32 in a sub-pixel row is used as a connection line, so that each sub-pixel in a sub-pixel row has the same
  • the reference voltage improves display uniformity.
  • the first power supply connection line 33 is configured to be connected with the first power supply line formed subsequently, so the first power supply connection line 33 in a sub-pixel row is used as a connection line, so that each sub-pixel row in a sub-pixel row is used as a connection line.
  • the pixels have the same first power supply voltage, which improves display uniformity.
  • the initial signal line 31 , the reference signal connection line 32 and the first power supply connection line 33 may be provided with equal widths or may be provided with unequal widths.
  • one end of the first electrode plate 36 is connected to the first power connection line 33, and the other end extends along the second direction Y, and the orthographic projection of the first electrode plate 36 on the substrate is the same as that of the double gate structure.
  • the orthographic projection of the fifth active layer 15 on the substrate between the two gate electrodes of the fifth transistor T5 has an overlapping area.
  • the first electrode plate 36 is configured to introduce a first parasitic capacitance at the double-gate intermediate node of the fifth transistor T5, and the first parasitic capacitance is used to stabilize the potential of the double-gate intermediate node of the fifth transistor T5, thereby stabilizing the potential of the second node.
  • the size of the first parasitic capacitance can be adjusted by adjusting the overlapping area of the fifth active layer 15 between the first electrode plate 36 and the two gate electrodes of the fifth transistor T5.
  • areas of overlapping regions of the fifth active layer 15 between the two gate electrodes of the first electrode plate 36 and the fifth transistor T5 may be different.
  • the second electrode plate 37 is disposed between the first scan signal line 21 and the second scan signal line 22-2, and the orthographic projection of the second electrode plate 37 on the substrate is the same as that of the double gate structure.
  • the orthographic projection of the second active layer 12 on the substrate between the two gate electrodes of the transistor T2 has an overlapping area.
  • the second electrode plate 37 is configured to introduce a second parasitic capacitance at the double gate intermediate node of the second transistor T2 to stabilize the potential of the first node N1.
  • the size of the second parasitic capacitance can be adjusted by adjusting the overlapping area of the second active layer 12 between the second electrode plate 37 and the two gate electrodes of the second transistor T2.
  • the overlapping area of the second active layer 12 between the second electrode plate 37 and the two gate electrodes of the second transistor T2 may be different.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • the fourth insulating layer, the fourth insulating layer is provided with a plurality of vias, and the plurality of vias at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via Via V5, sixth via V6, seventh via V7, eighth via V8, ninth via V9, tenth via V10, eleventh via V11, twelfth via V12, tenth via
  • the first via hole V1 is located in the region where the first opening 34-1 provided on the second electrode plate 34 of the storage capacitor is located, and the orthographic projection of the first via hole V1 on the substrate is located in the region where the first opening 34-1 is located.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 26 of the storage capacitor, and the first via hole V1 is configured as The first connection electrode formed subsequently is connected to the first electrode plate 26 of the storage capacitor through the via hole.
  • the second via hole V2 is located in the region where the second opening 35-1 provided in the second threshold capacitor plate 35 is located, and the fourth insulating layer and the third insulating layer in the second via hole V2 are etched The surface of the first electrode plate 27 of the threshold capacitor is exposed, and the second via hole V2 is configured so that the second connection electrode formed subsequently is connected to the first electrode plate 27 of the threshold value capacitor through the through hole.
  • the third via hole V3 is located in the region where the second electrode plate 37 is located, the fourth insulating layer in the third via hole V3 is etched away, exposing the surface of the second electrode plate 37, and the third via hole V3 is etched away.
  • the hole V3 is configured so that the first connection electrode formed later is connected to the second electrode plate 37 through the via hole.
  • the fourth via hole V4 is located in the region where the first region of the first active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the fourth via hole V4 are etched is removed, exposing the surface of the first region of the first active layer, and the fourth via hole V4 is configured to connect the subsequently formed data signal line to the first active layer through the via hole.
  • the fifth via hole V5 is located in the region where the second region of the first active layer (also the second region of the eighth active layer) is located, and the fourth insulating layer, the first The three insulating layers and the second insulating layer 62 are etched away, exposing the surface of the second region of the first active layer, and the fifth via hole V5 is configured to allow the subsequently formed first connection electrode to pass through the via hole to communicate with the first Active layer connection.
  • the sixth via hole V6 is located in the region where the first region of the eighth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 of the sixth via hole V6 are etched away , the surface of the first region of the eighth active layer is exposed, and the sixth via hole V6 is configured to connect the subsequently formed reference signal line to the eighth active layer through the via hole.
  • the seventh via hole V7 is located in the region where the first region of the second active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the seventh via hole V7 are etched is removed, exposing the surface of the first region of the second active layer, and the seventh via hole V7 is configured to connect the second connection electrode formed subsequently to the second active layer through the via hole.
  • the eighth via hole V8 is located in the region where the second region of the fourth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the eighth via hole V8 are etched is removed, exposing the surface of the second region of the fourth active layer, and the eighth via hole V8 is configured to connect the second connection electrode formed subsequently to the fourth active layer through the via hole.
  • the ninth via hole V9 is located in the region where the first region of the fourth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the ninth via hole V9 are etched is removed, exposing the surface of the first region of the fourth active layer, and the ninth via hole V9 is configured to connect the third connection electrode formed subsequently to the fourth active layer through the via hole.
  • the tenth via hole V10 is located in the area where the initial signal line 31 is located, the fourth insulating layer in the tenth via hole V10 is etched away, exposing the surface of the initial signal line 31, and the tenth via hole V10
  • the configuration is such that the third connection electrode formed later is connected to the initial signal line 31 through the via hole.
  • the eleventh via hole V11 is located in the region where the first region of the sixth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the eleventh via hole V11 are It is etched away to expose the surface of the first region of the sixth active layer, and the eleventh via hole V11 is configured to connect the third connection electrode formed subsequently to the sixth active layer through the via hole.
  • the twelfth via hole V12 is located in the region where the second region of the sixth active layer (also the second region of the seventh active layer) is located, and the fourth insulating layer in the twelfth via hole V12 , the third insulating layer and the second insulating layer 62 are etched away, exposing the surface of the second region of the sixth active layer, and the twelfth via hole V12 is configured to allow the fourth connection electrode formed subsequently to pass through the via hole connected to the sixth active layer.
  • the thirteenth via hole V13 is located in the region where the first region of the seventh active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the thirteenth via hole V13 are The surface of the first region of the seventh active layer is exposed by etching, and the thirteenth via hole V13 is configured to connect the fifth connection electrode formed subsequently to the seventh active layer through the via hole.
  • the fourteenth via hole V14 is located in the region where the second region of the second active layer (also the second region of the third active layer) is located, and the fourth insulating layer in the fourteenth via hole V14 , the third insulating layer and the second insulating layer 62 are etched away, exposing the surface of the second region of the second active layer, and the fourteenth via hole V14 is configured to allow the subsequently formed fifth connection electrode to pass through the via hole connected to the second active layer.
  • the fifteenth via hole V15 is located in the area where the second electrode plate 34 of the storage capacitor is located, and the fourth insulating layer in the fifteenth via hole V15 is etched away, exposing the second electrode plate 34 of the storage capacitor , the fifteenth via hole V15 is configured so that the sixth connection electrode formed subsequently is connected to the second electrode plate 34 of the storage capacitor through the via hole.
  • the sixteenth via hole V16 is located in the region where the second region of the fifth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the sixteenth via hole V16 are It is etched away to expose the surface of the second region of the fifth active layer, and the sixteenth via hole V16 is configured to connect the sixth connection electrode formed subsequently to the fifth active layer through the via hole.
  • the seventeenth via hole V17 is located in the area where the reference signal connection line 32 is located, and the fourth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the reference signal connection line 32.
  • the seventeen via holes V17 are configured so that the reference signal lines formed later are connected to the reference signal connection lines 32 through the via holes.
  • the eighteenth via hole V18 is located in the region where the first region of the third active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the eighteenth via hole V18 are The surface of the first region of the third active layer is exposed by etching, and the eighteenth via hole V18 is configured to connect the first power supply line formed subsequently to the third active layer through the via hole.
  • the nineteenth via hole V19 is located in the region where the first region of the fifth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer 62 in the nineteenth via hole V19 are The surface of the first region of the fifth active layer is exposed by etching, and the nineteenth via hole V19 is configured to connect the first power supply line formed subsequently to the fifth active layer through the via hole.
  • the twentieth via hole V20 is located in the region where the first power supply connection line 33 is located, and the fourth insulating layer in the twentieth via hole V20 is etched away, exposing the surface of the first power supply connection line 33 , the twentieth via hole V20 is configured so that the first power supply line 71 formed later is connected to the first power supply line 33 through the via hole.
  • a third conductive layer pattern is formed.
  • forming the third conductive layer may include: depositing a third metal thin film on the substrate on which the aforementioned patterns are formed, patterning the third metal thin film by a patterning process, and forming a third metal thin film disposed on the fourth insulating layer
  • the third conductive layer includes at least: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a A power supply line 71 , a reference signal line 72 and a data signal line 73 , as shown in FIG. 11 .
  • the first power line 71 , the reference signal line 72 and the data signal line 73 extend along the second direction Y, and the first power line 71 , the reference signal line 72 and the data signal line 73 may be provided with equal widths , it can also be set to unequal width, it can be a straight line, or it can be a polyline.
  • the first power line 71 is connected to the first region of the third active layer through the eighteenth via hole V18, and is connected to the first region of the fifth active layer through the nineteenth via hole V19, It is connected to the first power connection line 33 through the twentieth via hole V20.
  • the first power supply line 71 extending along the second direction Y is connected to the first power supply connecting line 33 extending along the first direction X, so that a plurality of sub-pixels in a sub-pixel row have the same first power supply voltage, thereby increasing the power supply voltage. Show uniformity.
  • the reference signal line 72 is connected to the first region of the eighth active layer through the sixth via hole V6, and is connected to the reference signal connection line 32 through the seventeenth via hole V17.
  • the reference signal line 72 extending along the second direction Y is connected to the reference signal connecting line 32 extending along the first direction X, so that multiple sub-pixels in a sub-pixel row have the same reference voltage, which improves display uniformity.
  • the data signal line 73 is connected to the first region of the first active layer through the fourth via hole V4.
  • the first connection electrode 41 is a straight line extending along the second direction Y, one end is connected to the first electrode plate 26 of the storage capacitor through the first via hole V1, and the other end is connected to the storage capacitor first electrode plate 26 through the fifth via hole V5.
  • the second region of the first active layer (also the second region of the eighth active layer) is connected, and the middle position between the two ends is connected to the second electrode plate 37 through the third via hole V3.
  • the first connection electrode 41 simultaneously serves as the second electrode of the first transistor T1 and the second electrode of the eighth transistor T8, and has the same potential as the second end of the storage capacitor Cst (ie, the third node N3).
  • the second electrode plate 37 since the second electrode plate 37 is disposed on the node between the two gate electrodes of the second transistor T2 of the double gate structure, the second electrode plate 37 has the same potential as the third node N3 , thus an overlapping second parasitic capacitance is formed between the second active layer between the two gate electrodes and the second electrode plate 37 having the potential of the third node N3, and the second parasitic capacitance is used to stabilize the first node N1 the potential.
  • the first connection electrode 41 is configured to introduce a third parasitic capacitance at a double-gate intermediate node of the fourth transistor T4 of the double-gate structure.
  • the first connection electrode 41 extends along the second direction Y, the third region 14-3 of the fourth active layer between the two gate electrodes of the fourth transistor T4 also extends along the second direction Y, the first connection electrode 41 is located on the opposite side of the first direction X of the first power supply line 71, the fourth active layer of the fourth transistor T4 is located on the opposite side of the first direction X of the first connection electrode 41, the first connection electrode 41 Adjacent to the third region 14-3, the orthographic projection of the third region 14-3 of the fourth active layer on the first power supply line 71 and the orthographic projection of the first connection electrode 41 on the first power supply line 71 have an overlapping region, That is, the orthographic projection of the first connection electrode 41 on the first power supply line 71 along the first direction X and the fourth active layer located between the two fourth gate electrodes on the first power supply line
  • the second connection electrode 42 is a straight line extending along the second direction Y, one end is connected to the first electrode plate 27 of the threshold capacitor through the second via hole V2, and the other end is connected to the first electrode plate 27 of the threshold capacitor through the eighth via hole V8.
  • the second region of the fourth active layer is connected, and the middle position between the two ends is connected to the first region of the second active layer through the seventh via hole V7.
  • the second connection electrode 42 simultaneously serves as the first electrode of the second transistor T2 and the second electrode of the fourth transistor T4, and has the same potential as the first terminal of the threshold capacitor CVth (ie, the first node N1).
  • the first electrode plate 27 of the threshold capacitor also serves as the gate electrode of the third transistor T3
  • the second connection electrode 42 realizes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the second electrode of the fourth transistor T4.
  • the interconnection of the pole and the first plate 27 of the threshold capacitor are the first electrode plate 27 of the threshold capacitor.
  • the third connection electrode 43 is in the shape of a zigzag line extending along the second direction Y, one end is connected to the first region of the fourth active layer through the ninth via hole V9, and the other end is connected to the first region of the fourth active layer through the eleventh through hole V9.
  • the hole V11 is connected to the first region of the sixth active layer, and the middle position between the two ends is connected to the initial signal line 31 through the tenth via hole V10.
  • the third connection electrode 43 simultaneously serves as the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6, which realizes that the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6 are connected to the initial signal line 31 at the same time. Connection.
  • the fourth connection electrode 44 is block-shaped, and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the twelfth via hole V12.
  • the fourth connection electrode 44 simultaneously serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and realizes the connection between the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7.
  • the fifth connection electrode 45 is a straight line extending along the second direction Y, one end is connected to the first region of the seventh active layer through the thirteenth via hole V13, and the other end is connected to the first region of the seventh active layer through the fourteenth via hole V13.
  • the via hole V14 is connected to the second region of the second active layer (which is also the second region of the third active layer).
  • the fifth connection electrode 45 simultaneously serves as the second pole of the second transistor T2, the second pole of the third transistor T3 and the first pole of the seventh transistor T7, so that the second pole of the second transistor T2 and the first pole of the third transistor T3
  • the second electrode and the first electrode of the seventh transistor T7 have the same potential (ie, the fourth node N4).
  • the sixth connection electrode 46 is a straight line extending along the second direction Y, one end is connected to the second electrode plate 34 of the storage capacitor through the fifteenth via hole V15, and the other end is connected to the second electrode plate 34 of the storage capacitor through the sixteenth via hole V16 is connected to the second region of the fifth active layer.
  • the sixth connection electrode 46 is connected to the second electrode plate 34 of the storage capacitor, and the second electrode plate 34 of the storage capacitor and the second electrode plate 35 of the threshold capacitor are an integral structure connected to each other. It is realized that the second pole of the fifth transistor T5, the first terminal of the storage capacitor Cst and the second terminal of the threshold capacitor CVth have the same potential (ie, the second node N2).
  • the first electrode plate 36 since the first power supply line 71 is connected with the first power supply connection line 33 and the first power supply connection line 33 is connected with the first electrode plate 36 , the first electrode plate 36 has the same characteristics as the first power supply line 71 . the potential. Since the orthographic projection of the first electrode plate 36 on the substrate and the orthographic projection of the fifth active layer 15 on the substrate between the two gate electrodes of the fifth transistor T5 of the dual-gate structure have an overlapping area, there is an overlap between the two gate electrodes.
  • An overlapping first parasitic capacitance is formed between the fifth active layer between the electrodes and the first electrode plate 36 with the first power supply voltage, and the first parasitic capacitance is used to stabilize the potential of the double-gate intermediate node of the fifth transistor T5 , thereby stabilizing the potential of the second node.
  • a fifth insulating layer pattern is formed.
  • forming the fifth insulating layer pattern may include: coating a fifth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fifth insulating film by a patterning process to form a covering third conductive layer
  • the fifth insulating layer is provided with a plurality of via holes, and the plurality of via holes include at least a thirty-first via hole V31, as shown in FIG. 12 .
  • the thirty-first via hole V31 is located in the region where the fourth connection electrode 44 is located, and the fifth insulating layer in the thirty-first via hole V31 is removed to expose the surface of the fourth connection electrode 44.
  • Thirty-one via holes V31 are configured so that the anode of the light emitting device formed later is connected to the fourth connection electrode 44 through the via hole.
  • a fourth conductive layer pattern is formed.
  • forming the fourth conductive layer may include: depositing a fourth metal thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth metal thin film by a patterning process, and forming a fourth metal thin film disposed on the fifth insulating layer
  • the fourth conductive layer includes at least: anode connection electrode 51 , second power supply connection line 52 and second power supply line 74 , as shown in FIG. 13 .
  • the anode connection electrode 51 is disposed on the side of the initial signal line 31 away from the first light-emitting signal line 24 , the anode connection electrode 51 is rectangular, and is connected to the fourth connection electrode 44 through the thirty-first via V31
  • the anode connection electrode 51 is configured to be connected to the anode of the light-emitting device to be formed later. Since the fourth connection electrode 44 simultaneously serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, the anode of the light emitting device is connected to the pixel driving circuit, so that the pixel driving circuit can drive the light emitting device to emit light.
  • the second power line 74 extends along the second direction Y, corresponding to the position of the first power line 71 .
  • the second power supply connection line 52 extends along the first direction X and is disposed between the first scan signal line 21 and the second scan signal line 22 - 2 , and is connected to the second power supply line 74 . Since the second power supply connection line 52 is connected to the second power supply line 74, the second power supply connection line 52 in a sub-pixel row serves as a low-voltage signal connection line, so that each sub-pixel in a sub-pixel row has the same second power supply voltage , which improves display uniformity.
  • the second power lines 74 may be provided with equal widths, or may be provided with unequal widths, may be straight lines, or may be folded lines.
  • the subsequent preparation process may include: forming a flat layer covering the pattern of the fourth conductive layer, forming an anode of the light emitting device on the flat layer, forming a pixel definition layer covering the anode, and setting the pixel definition layer of each sub-pixel There are pixel openings that expose the anode.
  • an organic light-emitting layer is formed by an evaporation process, and a cathode is formed on the organic light-emitting layer.
  • an encapsulation layer is formed.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. , the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light-emitting device.
  • the substrate may be a flexible substrate, or it may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer and a second inorganic material layer that are stacked, the first flexible material layer and the second flexible material layer
  • the material can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, etc.
  • the material of the first inorganic material layer and the second inorganic material layer can be nitrogen Silicon oxide (SiNx) or silicon oxide (SiOx), etc., are used to improve the water and oxygen resistance of the substrate.
  • the thickness of the first flexible material layer may be about 5 ⁇ m to 15 ⁇ m, such as 10 ⁇ m; the thickness of the second flexible material layer may be about 5 ⁇ m to 15 ⁇ m, such as 10 ⁇ m; the thickness of the first inorganic material layer
  • the thickness of the second inorganic material layer may be about 0.3 ⁇ m to 0.9 ⁇ m, for example, 0.6 ⁇ m; the thickness of the second inorganic material layer may be about 0.3 ⁇ m to 0.9 ⁇ m, for example, 0.6 ⁇ m.
  • the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo Wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first conductive layer is called the first gate metal (Gate1) layer
  • the second conductive layer is called the second gate metal (Gate2) layer
  • the third conductive layer is called the first source-drain metal (SD1) layer
  • the fourth conductive layer Called the second source-drain metal (SD2) layer.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) One or more, it can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer
  • the fifth insulating layer is called the passivation (PVX) layer.
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • the first insulating layer has a thickness of 3000 angstroms to 5000 angstroms
  • the second insulating layer has a thickness of 1000 angstroms to 2000 angstroms
  • the third insulating layer has a thickness of 4500 angstroms to 7000 angstroms
  • the fourth insulating layer has a thickness of 4500 angstroms to 7000 angstroms.
  • the thickness of the fifth insulating layer is 3000 angstroms to 5000 angstroms
  • the thickness of the fifth insulating layer is 3000 angstroms to 5000 angstroms.
  • High-resolution (PPI) displays with finer picture and display quality have become a design trend. Since the pixel area of high-resolution display is small, the arrangement of the pixel driving circuit in a limited space needs to consider various interference factors, especially the influence of the data signal line on the key nodes in the pixel driving circuit. In the pixel driving circuit shown in FIG.
  • the third node N3 stabilizes the potential of the reference voltage provided by the reference signal line through the eighth transistor T8, because the second transistor T2, the fourth transistor T4 and the fifth transistor T5 is disconnected, so in the light-emitting stage, the leakage path of the second node N2 is the single leakage path of the fifth transistor T5, and the leakage path of the first node N1 is the double leakage path of the second transistor T2 and the fourth transistor T4.
  • the second transistor T2 In order to reduce the leakage of key nodes in the light-emitting stage, in a pixel driving circuit of a display substrate, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 all adopt a double-gate structure, but this solution has the first node N1 and The problem of poor potential stability of the second node N2.
  • FIG. 14 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the double-gate intermediate node N7 of the fifth transistor T5 is provided with a first parasitic capacitance C1 , which is formed by two fifth gate electrodes located at the fifth transistor T5 An overlapping capacitance is formed between the fifth active layer and the first electrode plate 36, and the first electrode plate 36 has the same potential as the first power supply line.
  • the double-gate intermediate node N5 of the second transistor T2 is provided with a second parasitic capacitance C2.
  • the second parasitic capacitance C2 is formed by the second active layer and the second electrode plate located between the two second gate electrodes of the second transistor T2.
  • the overlapped capacitance formed by 37, the second electrode plate 37 has the same potential as the third node N3.
  • the double-gate intermediate node N6 of the fourth transistor T4 is provided with a third parasitic capacitance C3, and the third parasitic capacitance C3 is formed by the fourth active layer and the first connection electrode of the fourth transistor T4 located between the two fourth gate electrodes.
  • the lateral capacitance formed by 41, the first connection electrode 41 has the same potential as the third node N3.
  • the double-gate intermediate node N6 of the fourth transistor T4 is further provided with a fourth parasitic capacitance C4, and the fourth parasitic capacitance C4 is connected by the fourth active layer of the fourth transistor T4 located between the two fourth gate electrodes and the third connection
  • the overlapping capacitance formed by the electrodes 43, the third connection electrode 43 has the same potential as the initial signal line 31.
  • the other plate is connected to the first power supply line VDD, thus avoiding the jump-up of the double-gate intermediate node N7 of the fifth transistor T5 due to the turning off of the third scanning line S3, eliminating reverse leakage, and effectively stabilizing the potential of the second node N2.
  • the second parasitic capacitance C2 for the double leakage channel of the first node N1 in the light-emitting stage, due to the second parasitic capacitance C2, one plate is connected to the double-gate intermediate node N5 of the second transistor T2, and the other plate is connected to the third node N3, one plate of the third parasitic capacitor C3 is connected to the double-gate intermediate node N6 of the fourth transistor T4, and the other plate is connected to the third node N3, so that when the data voltage Vdt is coupled to the first node N1, the second transistor T2
  • the double-gate intermediate node N5 of the fourth transistor T4 and the double-gate intermediate node N6 of the fourth transistor T4 jump synchronously.
  • the Vref-Vdt information will be superimposed on the first node N1 and the double-gate intermediate node synchronously.
  • the potentials of the double-gate intermediate node N5 and the double-gate intermediate node N6 are close to the potential of the first node N1, thereby reducing the leakage of the second transistor T2 and the fourth transistor T4, effectively stabilizing the first node.
  • the capacitance values of the first parasitic capacitance C1 , the second parasitic capacitance C2 , the third parasitic capacitance C3 and the fourth parasitic capacitance C4 can be designed according to the actual circuit, so as to stabilize the potential of the key nodes.
  • the size of the parasitic capacitance can be adjusted by adjusting the area of the overlapping region of the electrode plate and the active layer.
  • the first parasitic capacitance C1, the second parasitic capacitance C2, the third parasitic capacitance The parasitic capacitance C3 and the fourth parasitic capacitance C4 may be different.
  • the capacitance values of the first parasitic capacitance C1 , the second parasitic capacitance C2 , the third parasitic capacitance C3 and the fourth parasitic capacitance C4 may be about 0.1 fF to 6.0 fF.
  • the display substrate provided by the exemplary embodiments of the present disclosure avoids the instantaneous high voltage at the intermediate node of the dual gate by introducing parasitic capacitance at the intermediate node of the dual gate transistor. , eliminating the reverse leakage of the intermediate node of the double gate, effectively stabilizing the potential of the key node, ensuring the accuracy of the driving current, and improving the display effect.
  • the preparation process of the present disclosure can be well compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.
  • the structures and the preparation process thereof shown in the present disclosure are merely exemplary descriptions. In the exemplary embodiments, corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs.
  • the first electrode plate and the second electrode plate may be disposed on other conductive layers.
  • the first electrode plate and the second electrode plate can be arranged on the first conductive layer, and are arranged on the same layer as the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor, and are simultaneously formed by the same patterning process.
  • the shapes of the electrode plate and the second electrode plate may be the same as in the foregoing exemplary embodiment.
  • first electrode plate and the second electrode plate may be disposed on the third conductive layer, disposed on the same layer as the first connection electrode and the first power supply line, and formed simultaneously through the same patterning process, the first electrode plate and
  • the shape of the second electrode plate and the structure of the corresponding connecting electrodes can be changed according to actual needs, which are not limited in the present disclosure.
  • the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display ( QDLED), etc., the present disclosure is not limited here.
  • a pixel driving circuit such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display ( QDLED), etc.
  • Exemplary embodiments of the present disclosure provide a method for manufacturing a display substrate, so as to manufacture the display substrates of the above-mentioned exemplary embodiments.
  • the display substrate may include a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit includes a plurality of transistors, at least one The transistor includes an active layer and two gate electrodes; the preparation method includes:
  • a semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate are formed on the substrate, at least one conductive layer is provided with at least one electrode plate, the orthographic projection of the electrode plate on the substrate There is an overlapping area with the orthographic projection of the active layer between the two gate electrodes on the substrate.
  • forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate may include:
  • a first conductive layer, a second conductive layer and a third conductive layer are sequentially formed on the semiconductor layer, and the electrode plate is on the first conductive layer, the second conductive layer or the third conductive layer.
  • At least one conductive layer is provided with a first power supply line connected to the pixel driving circuit, and at least one electrode plate is connected to the first power supply line.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which is not limited in the embodiment of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其制备方法、显示装置。显示基板包括基底(101)和多个子像素(P1,P2,P3)，至少一个子像(P1,P2,P3)素包括像素驱动电路和连接像素驱动电路的发光器件(103)，像素驱动电路包括多个晶体管，至少一个晶体管包括有源层和两个栅电极；基底上设置有半导体层以及设置在半导体层远离基底一侧的多个导电层，至少一个导电层设置有至少一个电极板，电极板在基底(101)上的正投影与位于两个栅电极之间的有源层在基底(101)上的正投影存在重叠区域。

Description

显示基板及其制备方法、显示装置
本申请要求于2021年1月27日提交的、申请号为PCT/CN2021/073957、发明名称为“像素驱动电路及其驱动方法、显示基板、显示装置”的PCT申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供了一种显示基板，所述显示基板包括基底和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路包括多个晶体管，至少一个晶体管包括有源层和两个栅电极；所述基底上设置有半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有至少一个电极板，所述电极板在所述基底上的正投影与位于所述两个栅电极之间的有源层在所述基底上的正投影存在重叠区域。
在示例性实施方式中，所述多个导电层包括依次设置在所述半导体层远离所述基底一侧的第一导电层、第二导电层和第三导电层，所述电极板设置在所述第一导电层、第二导电层或第三导电层上。
在示例性实施方式中，所述显示基板还包括与所述像素驱动电路连接的第一电源线，至少一个电极板与所述第一电源线连接。
在示例性实施方式中，所述多个晶体管至少包括第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；所述第一晶体管的第一极与数据信号线连接，所述第一晶体管的第二极与第三节点连接；所述第二晶体管的第一极与第一节点连接，所述第二晶体管的第二极与第四节点连接；所述第三晶体管的栅电极与第一节点连接，所述第三晶体管的第一极与第一电源线连接，所述第三晶体管的第二极与第四节点连接；所述第四晶体管的第一极与初始信号线连接，所述第四晶体管的第二极与第一节点连接；所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与第二节点连接。
在示例性实施方式中，所述像素驱动电路还包括存储电容和阈值电容，所述存储电容包括存储电容第一极板和存储电容第二极板，所述阈值电容包括阈值电容第一极板和阈值电容第二极板；所述存储电容第一极板与所述第三节点连接，所述存储电容第二极板与所述第二节点连接；所述阈值电容第一极板与所述第一节点连接，所述阈值电容第二极板与所述第二节点连接。
在示例性实施方式中，所述存储电容第一极板和阈值电容第一极板设置在所述第一导电层上，所述存储电容第一极板和阈值电容第一极板间隔设置，所述存储电容第一极板与所述半导体层不交叠。
在示例性实施方式中，所述存储电容第二极板和阈值电容第二极板设置在所述第二导电层上，所述存储电容第二极板和阈值电容第二极板相互连接，所述存储电容第二极板在所述基底上的正投影与所述存储电容第一极板在所述基底上的正投影存在重叠区域，所述阈值电容第二极板在所述基底上的正投影与所述阈值电容第一极板在所述基底上的正投影存在重叠区域。
在示例性实施方式中，所述第五晶体管为双栅晶体管，所述第五晶体管 至少包括第五有源层和两个第五栅电极；所述电极板包括第一电极板，所述第一电极板在所述基底上的正投影与位于两个第五栅电极之间的第五有源层在所述基底上的正投影存在重叠区域。
在示例性实施方式中，所述两个第五栅电极设置在所述第一导电层，所述第一电极板设置在所述第一导电层或第二导电层，所述第一电源线设置在所述第三导电层，所述第一电源线通过过孔与所述第一电极板连接。
在示例性实施方式中，所述第二导电层还包括第一电源连接线，所述第一电极板与所述第一电源连接线连接，所述第一电源线通过过孔与所述第一电源连接线连接。
在示例性实施方式中，所述第二晶体管为双栅晶体管，所述第二晶体管至少包括第二有源层和两个第二栅电极；所述电极板包括第二电极板，所述第二电极板在所述基底上的正投影与位于两个第二栅电极之间的第二有源层在所述基底上的正投影存在重叠区域。
在示例性实施方式中，所述两个第二栅电极设置在所述第一导电层，所述第二电极板设置在所述第一导电层或第二导电层，所述第三导电层还设置有第一连接电极，所述第一连接电极通过过孔与所述第二电极板连接。
在示例性实施方式中，所述第一连接电极作为所述第一晶体管的第二极，并通过过孔与所述存储电容第一极板连接。
在示例性实施方式中，所述第四晶体管为双栅晶体管，所述第四晶体管至少包括第四有源层和两个第四栅电极；所述第一连接电极在第一电源线上的正投影与位于两个第四栅电极之间的第四有源层在第一电源线上的正投影存在重叠区域。
在示例性实施方式中，所述第三导电层还设置有第二连接电极，所述第二连接电极同时作为所述第二晶体管的第一极和所述第四晶体管的第二极，所述第二连接电极通过过孔与所述阈值电容第一极板连接。
在示例性实施方式中，所述第三导电层还设置有第二连接电极，所述第三连接电极作为所述第四晶体管的第一极，所述第三连接电极通过过孔与所述初始信号线连接，所述第三连接电极在基底上的正投影与所述第四晶体管 的两个栅电极之间的第四有源层在基底上的正投影存在重叠区域。
本公开还提供了一种显示装置，包括前述的显示基板。
本公开还提供了一种显示基板的制备方法，所述显示基板包括基底和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路包括多个晶体管，至少一个晶体管包括有源层和两个栅电极；所述制备方法包括：
在所述基底上形成半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有至少一个电极板，所述电极板在所述基底上的正投影与位于所述两个栅电极之间的有源层在所述基底上的正投影存在重叠区域。
在示例性实施方式中，在所述基底上形成半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，包括：
在所述基底上形成半导体层；
在所述半导体层上依次形成第一导电层、第二导电层和第三导电层，所述电极板在所述第一导电层、第二导电层或第三导电层上。
在示例性实施方式中，至少一个导电层上设置有与所述像素驱动电路连接的第一电源线，至少一个电极板与所述第一电源线连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为本公开示例性实施例一种显示基板的结构示意图；
图7为本公开示例性实施例一种形成半导体层图案后的示意图；
图8为本公开示例性实施例一种形成第一导电层图案后的示意图；
图9为本公开示例性实施例一种形成第二导电层图案后的示意图；
图10为本公开示例性实施例一种形成第四绝缘层图案后的示意图；
图11为本公开示例性实施例一种形成第三导电层图案后的示意图；
图12为本公开示例性实施例一种形成第五绝缘层图案后的示意图；
图13为本公开示例性实施例一种形成第四导电层图案后的示意图；
图14为本公开示例性实施例像素驱动电路的等效电路图。
附图标记说明:
11—第一有源层；        12—第二有源层；        13—第三有源层；
14—第四有源层；        15—第五有源层；        16—第六有源层；
17—第七有源层；        18—第八有源层；        21—第一扫描信号线；
22—第二扫描信号线；    23—第三扫描信号线；    24—发光控制线；
26—存储电容第一极板；  27—阈值电容第一极板；  31—初始信号线；
32—参考信号连接线；    33—第一电源连接线；    34—存储电容第二极板；
35—阈值电容第二极板；  36—第一电极板；        37—第二电极板；
41—第一连接电极；      42—第二连接电极；      43—第三连接电极；
44—第四连接电极；      45—第五连接电极；      46—第六连接电极；
51—阳极连接电极；      52—第二电源连接线；    71—第一电源线；
72—参考信号线；        73—数据信号线；        74—第二电源线；
101—基底；             102—驱动电路层；       103—发光器件；
104—封装层；           301—阳极；             302—像素定义层；
303—有机发光层；       304—阴极；             401—第一封装层；
402—第二封装层；       403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括扫描信号驱动器、数据信号驱动器、发光信号驱动器、OLED显示基板、第一电源单元、第二电源单元和初始电源单元。在示例性实施方式中，OLED显示基板至少包括多个扫描信号线(S 1到S N)、多个数据信号线(D 1到D M)和多个发光信号线(EM 1到EM N)，扫描信号驱动器被配置为依次向多个扫描信号线(S 1到S N)提供扫描信号，数据信号驱动器被配置为向多个数据信 号线(D 1到D M)提供数据信号，发光信号驱动器被配置为依次向多个发光信号线(EM 1到EM N)提供发光控制信号。在示例性实施方式中，多个扫描信号线和多个发光信号线沿着水平方向延伸，多个数据信号线沿着竖直方向延伸。显示装置包括多个子像素，至少一个子像素包括像素驱动电路和发光器件，一个子像素的像素驱动电路可以连接一条扫描信号线、一条发光控制线和一条数据信号线。第一电源单元、第二电源单元和初始电源单元分别被配置为通过第一电源线、第二电源线和初始信号线向像素驱动电路提供第一电源电压、第二电源电压和初始电源电压。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个中包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色(W)子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板了可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101 一侧的发光器件103以及设置在发光器件103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中以每个子像素中包括一个驱动晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每个子像素的驱动电路层102可以包括：设置在基底上的第一绝缘层；设置在第一绝缘层上的有源层；覆盖有源层的第二绝缘层；设置在第二绝缘层上的栅电极和第一极板；覆盖栅电极和第一极板的第三绝缘层；设置在第三绝缘层上的第二极板；覆盖第二极板的第四绝缘层，第二绝缘层、第三绝缘层和第四绝缘层上开设有过孔，过孔暴露出有源层；设置在第四绝缘层上的源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接；覆盖前述结构的平坦层，平坦层上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极组成驱动晶体管210，第一极板和第二极板组成存储电容211。
在示例性实施方式中，发光器件103可以包括阳极301、像素定义层302、有机发光层303和阴极304。阳极301设置在平坦层上，通过平坦层上开设的过孔与驱动晶体管210的漏电极连接；像素定义层302设置在阳极301和平坦层上，像素定义层302上设置有像素开口，像素开口暴露出阳极301；有机发光层303至少部分设置在像素开口内，有机发光层303与阳极301连接；阴极304设置在有机发光层303上，阴极304与有机发光层303连接；有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。
在示例性实施方式中，封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光器件103。
在示例性实施方式中，有机发光层303可以至少包括在阳极301上叠设的空穴注入层、空穴传输层、发光层和空穴阻挡层。在示例性实施方式中，所有子像素的空穴注入层是连接在一起的共通层，所有子像素的空穴传输层 是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，空穴阻挡层是连接在一起的共通层。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T2C结构。图4为一种像素驱动电路的等效电路示意图，示意了一种8T2C结构。如图4所示，像素驱动电路可以包括8个开关晶体管(第一晶体管T1到第八晶体管T8)、2个电容(存储电容Cst和阈值电容CVth)，像素驱动电路分别与9个信号线连接，9个信号线包括第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、发光信号线EM、参考信号线REF、初始信号线INIT、数据信号线DATA、第一电源线VDD和第二电源线VSS。在示例性实施方式中，第一晶体管T1的栅电极与第一扫描信号线S1连接，第一晶体管T1的第一极与数据信号线DATA连接，第一晶体管的第二极与第二节点N3连接。第二晶体管T2的栅电极与第二扫描信号线S2连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第四节点N4连接。第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第一电源线VDD连接，第三晶体管T3的第二极与第四节点N4连接。第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与初始信号线INIT连接，第四晶体管T4的第二极与第一节点N1连接。第五晶体管T5的栅电极与第三扫描信号线S3连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与第二扫描信号线S2连接，第六晶体管T6的第一极与初始信号线INIT连接，第六晶体管T6的第二极与发光器件的第一极连接。第七晶体管T7的栅电极与发光信号线EM连接，第七晶体管T7的第一极与第四节点N4连接，第七晶体管T7的第二极与发光器件的第一极连接。第八晶体管T8的栅电极与发光信号线EM连接，第八晶体管T8的第一极与参考信号线REF连接，第八晶体管T8的第二极与第三节点N3连接。阈值电容CVth的第一端与第一节点N1连接，阈值电容CVth的第二端与第二节点N2连接。存储电容Cst的第一端与第二节点N2连接，存储电容Cst的第二端与第三节点N3连接。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以是P型晶体 管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第八晶体管T8可以包括P型晶体管和N型晶体管。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
在示例性实施方式中，第二扫描信号线S2为本显示行像素驱动电路中的扫描信号线，第三扫描信号线S3为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第二扫描信号线S2为S(n)，第三扫描信号线S3为S(n-1)，本显示行的第三扫描信号线S3与上一显示行像素驱动电路中的第二扫描信号线S2可以为同一信号线，或者说，本显示行的第二扫描信号线S2与下一显示行像素驱动电路中的第三扫描信号线S3可以为同一信号线，以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、发光信号线EM和初始信号线INIT可以沿水平方向延伸，数据信号线DATA、第一电源线VDD、第二电源线VSS和参考信号线REF可以沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括8个开关晶体管(第一晶体管T1到第八晶体管T8)、2个电容(存储电容Cst和阈值电容CVth)和9个信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、发光信号线EM、参考信号线REF、初始信号线INIT、数据信号线DATA、第一电源线VDD和第二电源线VSS)，8个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位和数据刷新阶段，第一扫描信号线S1和第三扫描信号线S3的信号为低电平信号，第二扫描信号线S2和发光信号线EM的信号为高电平信号。第一扫描信号线S1的信号为低电平信号，使第一晶体管T1和第四晶体管T4导通。第一晶体管T1导通使数据信号线DATA输出的数据电压提供至第三节点N3，第三节点N3写入数据电压Vdt。第四晶体管T4导通使初始信号线INIT的初始信号提供至第一节点N1，第一节点N1复位到初始电压Vinit。第三扫描信号线S3的信号为低电平信号，使第五晶体管T5导通，第一电源线VDD输出的电源电压提供至第二节点N2，第二节点N2写入电源电压Vdd。
第二阶段A2、称为阈值获取阶段，第二扫描信号线S2和第三扫描信号线S3的信号为低电平信号，第一扫描信号线S1和发光信号线EM的信号为高电平信号。第三扫描信号线S3的信号为低电平信号，使第五晶体管T5继续导通，第一电源线VDD输出的电源电压提供至第二节点N2，第二节点N2保持电源电压Vdd。第二扫描信号线S2的信号为低电平信号，使第二晶体管T2和第六晶体管T6导通。第二晶体管T2导通使第一节点N1和第四节点N4电位相同，第三晶体管T3形成“二极管连接”结构，第一电源线VDD向第一节点N1充电，第一节点N1充电至Vdd-|Vth|电位后截至，将带有第三晶体管T3阈值电压的信息存储在阈值电容CVth中。第六晶体管T6导通使使初始信号线INIT的初始信号提供至OLED的第一极，OLED的第一极复位到初始电压Vinit。
第三阶段A3、称为发光阶段，发光信号线EM的信号为低电平信号，第一扫描信号线S1、第二扫描信号线S2和第三扫描信号线S3的信号为高电平信号。发光信号线EM的信号为低电平信号，使第七晶体管T7和第八晶体管T8导通。第七晶体管T7导通，第一节点N1的电位使第三晶体管T3导通，第一电源线VDD输出的电源电压通过导通的第三晶体管T3和第七晶体管T7向OLED的第一极提供驱动电压，驱动OLED发光。第八晶体管T8导通使参考信号线REF的参考信号提供至第三节点N3，第三节点N3的电位由数据电压Vdt变为参考电压Vref，信号叠加后，第一节点N1的电位变为：Vdd-|Vth|+(Vref-Vdt)。第一扫描信号线S1的信号为低电平信号使第一晶 体管T1导通，数据信号线DATA输出数据电压提供至第二节点N2，第二节点N2写入数据电压Vdt。第一节点N1和第二节点N2的信号叠加后，第一节点N1的电位Vdd-|Vth|+(Vref-Vdt)。之后第一节点N1悬空，靠电容保持原电位。在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定，因而根据第一节点N1的电位，流过第三晶体管T3的驱动电流为：
I＝β*(Vref-Vdt) 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，β为常数，Vdt为数据信号线DATA输出的数据电压，Vref为参考信号线REF输出的参考电压。该驱动电流公式中无第三晶体管T3的阈值电压信息，因此该像素驱动电路对第三晶体管T3的阈值电压有自补偿作用。
在像素驱动电路工作过程中，在复位阶段，第一节点N1的电位为初始电压Vinit，第二节点N2的电位为电源电压Vdd，第三节点N3的电位为数据电压Vdt。在阈值获取阶段，第一节点N1的电位为Vdd-|Vth|，第二节点N2的电位为电源电压Vdd，第三节点N3的电位为数据电压Vdt。在发光阶段，第一节点N1的电位为Vdd-|Vth|+(Vref-Vdt)，第二节点N2的电位为Vdd+Vref-Vdt，第三节点N3的电位为参考电压Vref。
图6为本公开示例性实施例一种显示基板的结构示意图，示意了三个子像素的平面结构。如图6所示，在平行于显示基板的平面内，显示基板的子像素中设置有第一扫描信号线21、两条第二扫描信号线22(第二扫描信号线22-1和第二扫描信号线22-2)、第三扫描信号线23、发光控制线24、初始信号线31、第一电源线71、参考信号线72、数据信号线73、第二电源线74、像素驱动电路和发光器件，像素驱动电路可以包括存储电容、阈值电容和多个晶体管，每个晶体管包括有源层、栅电极、第一极和第二极，存储电容包括存储电容第一极板26和存储电容第二极板34，阈值电容包括阈值电容第一极板27和阈值电容第二极板35。在示例性实施方式中，像素驱动电路与第一电源线71连接，第一电源线71向像素驱动电路提供高电平信号。在示例性实施例中，至少一个晶体管为双栅晶体管，双栅晶体管包括有源层、两个栅电极、第一极和第二极。在示例性实施方式中，显示基板还包括至少一 个电极板，至少一个电极板在基底上的正投影与位于所述两个栅电极之间的有源层在基底上的正投影存在重叠区域，至少一个电极板与第一电源线71连接。
在垂直于显示基板的平面内，显示基板可以包括在基底上依次设置的半导体层和多个导电层，至少一个导电层设置电极板。在示例性实施例中，多个导电层可以包括在半导体层上依次设置的第一导电层、第二导电层、第三导电层和第四导电层，至少一个电极板可以设置在第一导电层或第二导电层上，第一电源线71设置在第三导电层上，第一电源线71通过过孔与电极板连接。
在示例性实施例中，半导体层可以包括多个晶体管的有源层，第一导电层可以包括第一扫描信号线21、第二扫描信号线22-1、第二扫描信号线22-2、第三扫描信号线23、发光控制线、存储电容第一极板26和阈值电容第一极板27，第二导电层可以包括初始信号线31、存储电容第二极板34和阈值电容第二极板35，第三导电层可以包括第一电源线71、参考信号线72和数据信号线73，第四导电层可以包括第二电源线74。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22-1、第二扫描信号线22-2、第三扫描信号线23和发光控制线24沿第一方向X延伸，存储电容第一极板26和阈值电容第一极板27为间隔设置。初始信号线31沿第一方向X延伸，存储电容第二极板34和阈值电容第二极板35为相互连接的一体结构。第一电源线71、参考信号线72、数据信号线73和第二电源线74沿第二方向Y延伸。第一方向X可以是扫描信号线的延伸方向，第二方向Y可以是数据信号线的延伸方向。
在示例性实施例中，第二导电层可以包括参考信号连接线32和第一电源连接线33。参考信号连接线32和第一电源连接线33均沿第一方向X延伸，参考信号连接线32与参考信号线72连接，第一电源连接线33与第一电源线71，使得一子像素行中各个子像素具有相同的参考电压和电源电压，提高显示均一性。
在示例性实施例中，像素驱动电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5；第一晶体管T1的第 一极与数据信号线74连接，第一晶体管T1的第二极与存储电容第一极板26连接；第二晶体管T2的第一极与阈值电容第一极板27连接，第二晶体管T2的第二极与第三晶体管T3的第二极连接；第三晶体管T3的栅电极与阈值电容第一极板27连接，第三晶体管T3的第一极与第一电源线71连接；第四晶体管T4的第一极与初始信号线31连接，第四晶体管T4的第二极与阈值电容第一极板27连接；第五晶体管T5的第一极与第一电源线71连接，第五晶体管T5的第二极与存储电容第二极板34和阈值电容第二极板35连接。
在示例性实施例中，第二晶体管T2、第四晶体管T4和第五晶体管T5为双栅晶体管。第二导电层可以包括第一电极板36和第二电极板37。第一电极板36配置为在第五晶体管T5的双栅中间节点引入第一寄生电容，第二电极板37配置为在第二晶体管T2的双栅中间节点引入第二寄生电容。在示例性实施例中，第三导电层可以包括第一连接电极41，第一连接电极41配置为在第四晶体管T4的双栅中间节点引入第三寄生电容。
在示例性实施方式中，第一电极板36与第一电源连接线33直接连接，第二电极板37与第一连接电极41通过过孔连接。
在示例性实施例中，第三导电层可以包括第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45和第六连接电极46。第一连接电极41同时作为第一晶体管T1的第二极和第八晶体管T8的第二极，第二连接电极42同时作为第二晶体管T2的第一极和第四晶体管T4的第二极，第三连接电极43同时作为第四晶体管T4的第一极和第六晶体管T6的第一极，第四连接电极44同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第五连接电极45同时作为第二晶体管T2的第二极、第三晶体管T3的第二极和第七晶体管T7的第一极，第六连接电极46作为第五晶体管T5的第二极。
在示例性实施例中，第四导电层可以包括阳极连接电极51和第二电源连接线52，阳极连接电极51配置连接第四连接电极44和发光器件的阳极，第二电源连接线52沿着第一方向X延伸并连接第二电源线74，因而使得一子像素行中各个子像素具有相同的第二电源电压，提高了显示均一性。
在示例性实施方式中，显示基板可以包括第一绝缘层、第二绝缘层、第 三绝缘层、第四绝缘层和第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
本公开示例性实施例提供的显示基板，通过在双栅晶体管的双栅中间节点设置寄生电容，避免了双栅中间节点的瞬间高压，消除了双栅中间节点的反向漏电，有效稳定了关键节点的电位，可以保证驱动电流的准确性，提高了显示效果。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以显示基板中一子像素行中3个子像素为例，显示基板的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上 的半导体层，如图7所示。
在示例性实施例中，至少一个子像素的半导体层可以包括第一晶体管T1的第一有源层至第八晶体管T8的第八有源层，第一晶体管T1的第一有源层11和第八晶体管T8的第八有源层18为相互连接的一体结构，第二晶体管T2的第二有源层12和第三晶体管T3的第三有源层13为相互连接的一体结构，第六晶体管T6的第六有源层16和第七晶体管T7的第七有源层17为相互连接的一体结构，第四晶体管T4的第四有源层14为单独设置，第五晶体管T5的第五有源层15为单独设置。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。
在示例性实施例中，第一有源层11的第一区11-1单独设置，第一有源层11的第二区11-2同时作为第八有源层18的第二区18-2，即第一有源层11的第二区11-2和第八有源层18的第二区18-2相互连接。
在示例性实施例中，第二有源层12的第一区12-1单独设置，第二有源层12的第二区12-2同时作为第三有源层13的第二区13-2，即第二有源层12的第二区12-2和第三有源层13的第二区13-2相互连接。
在示例性实施例中，第三有源层13的第一区13-1单独设置，第三有源层13的第二区13-2同时作为第二有源层12的第二区12-2，即第三有源层13的第二区13-2和第二有源层12的第二区12-2相互连接。
在示例性实施例中，第四有源层14的第一区14-1和第四有源层14的第二区14-2均单独设置。第五有源层15的第一区15-1和第五有源层15的第二区15-2均单独设置。
在示例性实施例中，第六有源层16的第一区16-1单独设置，第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2，即第六有源层16的第二区16-2和第七有源层17的第二区17-2之间相互连接。
在示例性实施例中，第七有源层17的第一区17-1单独设置，第七有源层17的第二区17-2同时作为第六有源层16的第二区16-2，即第七有源层17的第二区17-2和第六有源层16的第二区16-2之间相互连接。
在示例性实施例中，第八有源层18的第一区18-1单独设置，第八有源层18的第二区18-2同时作为第一有源层11的第二区11-2，即第八有源层18的第二区18-2和第一有源层11的第二区11-2相互连接。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22-1、第二扫描信号线22-2、第三扫描信号线23、发光控制线24、存储电容第一极板26和阈值电容第一极板27，如图8所示。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22-1、第二扫描信号线22-2、第三扫描信号线23和发光控制线24可以沿着第一方向X延伸。存储电容第一极板26和阈值电容第一极板27间隔设置，且均设置在第二扫描信号线22-2和第三扫描信号线23之间，存储电容第一极板26靠近第三扫描信号线23，阈值电容第一极板27靠近第二扫描信号线22-2。第一扫描信号线21设置在第二扫描信号线22-2远离阈值电容第一极板27的一侧，发光控制线24设置在第一扫描信号线21远离第三扫描信号线23的一侧。在示例性实施例中，第二扫描信号线22-1和第二扫描信号线22-2与相同的信号源连接，输出相同的信号。
在示例性实施例中，存储电容第一极板26的轮廓可以为矩形状，角部可以设置倒角。阈值电容第一极板27的轮廓可以为矩形状，矩形状靠近第三有源层13第一区的角部设置凹糟，角部可以设置倒角。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22-1、第二扫描信号线22-2、第三扫描信号线23和发光控制线24可以为等宽度设置，也可以为非等宽度设置，宽度为第二方向Y的尺寸。
在示例性实施例中，第三扫描信号线23(也是上一子像素行中子像素的第二扫描信号线)上可以设置多个第一栅极块和多个第二栅极块，每个子像素内可以设置一个第一栅极块和一个第二栅极块，第一栅极块的一端与第三扫描信号线23连接，另一端沿着第二方向Y延伸，第二栅极块的一端与第 三扫描信号线23连接，另一端沿着第二方向Y的反方向延伸，第一栅极块和第二栅极块配置为形成双栅电极。
在示例性实施例中，第一扫描信号线21与第一有源层11相重叠的区域作为第一晶体管T1的栅电极，第一扫描信号线21与第四有源层14相重叠的区域作为第四晶体管T4的栅电极(双栅结构)，第二扫描信号线22-2与第二有源层12相重叠的区域作为第二晶体管T2的栅电极(双栅结构)，第二扫描信号线22-1与第六有源层16相重叠的区域作为第六晶体管T6的栅电极，第三扫描信号线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极(双栅结构)，发光控制线24与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，发光控制线24与第八有源层18相重叠的区域作为第八晶体管T8的栅电极，阈值电容第一极板27在基底上的正投影与第三有源层13在基底上的正投影存在重叠区域，阈值电容第一极板27同时作为第三晶体管T3的栅电极。
在示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为开关型晶体管，第三晶体管T3为驱动型晶体管。
在示例性实施例中，存储电容第一极板26在基底上的正投影与第三有源层13在基底上的正投影没有重叠区域。
在示例性实施例中，一子像素行中相邻子像素的存储电容第一极板26隔离设置，相邻子像素的阈值电容第一极板27隔离设置。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第八晶体管T8的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第八有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包 括：初始信号线31、参考信号连接线32、第一电源连接线33、存储电容第二极板34、阈值电容第二极板35、第一电极板36和第二电极板37，如图9所示。
在示例性实施例中，存储电容第二极板34和阈值电容第二极板35设置在第二扫描信号线22-2和第三扫描信号线23之间，存储电容第二极板34和阈值电容第二极板35可以是相互连接的一体结构。
在示例性实施例中，一体结构的存储电容第二极板34和阈值电容第二极板35可以为矩形状，矩形状的角部可以设置倒角。
在示例性实施例中，存储电容第二极板34在基底上的正投影与存储电容第一极板26在基底上的正投影存在重叠区域。存储电容第二极板34上设置有第一开口34-1，第一开口34-1可以为矩形，位于存储电容第二极板34的中部，第一开口34-1使存储电容第二极板34形成环形结构。第一开口34-1暴露出覆盖存储电容第一极板26的第三绝缘层，且存储电容第一极板26在基底上的正投影包含第一开口34-1在基底上的正投影。在示例性实施例中，第一开口34-1配置为容置后续形成的第一过孔，第一过孔位于第一开口34-1内并暴露出存储电容第一极板26，使后续形成的第一连接电极通过第一过孔与存储电容第一极板26连接。
在示例性实施例中，阈值电容第二极板35在基底上的正投影与阈值电容第一极板27在基底上的正投影存在重叠区域。阈值电容第二极板35上设置有第二开口35-1，第二开口35-1可以为矩形，位于阈值电容第二极板35的中部，第二开口35-1使阈值电容第二极板35形成环形结构。第二开口35-1暴露出覆盖阈值电容第一极板27的第三绝缘层，且阈值电容第一极板27在基底上的正投影包含第二开口35-1在基底上的正投影。在示例性实施例中，第二开口35-1配置为容置后续形成的第二过孔，第二过孔位于第二开口35-1内并暴露出阈值电容第一极板27，使后续形成的第二连接电极通过第二过孔与阈值电容第一极板27连接。
在示例性实施例中，存储电容第一极板26和存储电容第二极板34构成像素驱动电路的存储电容Cst，存储电容第一极板26作为存储电容Cst的第二端，存储电容第二极板34作为存储电容Cst的第一端。阈值电容第一极板 27和阈值电容第二极板35构成像素驱动电路的阈值电容CVth，阈值电容第一极板27作为阈值电容CVth的第一端，同时作为第三晶体管T3的栅电极，阈值电容第二极板35作为阈值电容的第二端。存储电容Cst的第一端与阈值电容CVth的第二端相互连接，存储电容Cst的第一端同时作为阈值电容CVth的第二端。
在示例性实施例中，一子像素行中相邻子像素的存储电容第二极板34间隔设置，一子像素行中相邻子像素的阈值电容第二极板35间隔设置。
在示例性实施例中，初始信号线31、参考信号连接线32和第一电源连接线33沿着第一方向X延伸，初始信号线31设置在发光控制线24远离第一扫描信号线21的一侧，参考信号连接线32和第一电源连接线33设置在第三扫描信号线23和存储电容第一极板26之间，参考信号连接线32靠近存储电容第一极板26，第一电源连接线33靠近第三扫描信号线23。
在示例性实施例中，参考信号连接线32配置为与后续形成的参考信号线连接，因而一子像素行中的参考信号连接线32作为连接线，使得一子像素行中各个子像素具有相同的参考电压，提高了显示均一性。
在示例性实施例中，第一电源连接线33配置为与后续形成的第一电源线连接，因而一子像素行中的第一电源连接线33作为连接线，使得一子像素行中各个子像素具有相同的第一电源电压，提高了显示均一性。
在示例性实施例中，初始信号线31、参考信号连接线32和第一电源连接线33可以为等宽度设置，也可以为非等宽度设置。
在示例性实施例中，第一电极板36的一端与第一电源连接线33连接，另一端沿着第二方向Y延伸，且第一电极板36在基底上的正投影与双栅结构的第五晶体管T5的两个栅电极之间的第五有源层15在基底上的正投影存在重叠区域。第一电极板36配置为在第五晶体管T5的双栅中间节点引入第一寄生电容，第一寄生电容用于稳定第五晶体管T5的双栅中间节点的电位，进而稳定第二节点的电位。在示例性实施例中，通过调节第一电极板36与第五晶体管T5的两个栅电极之间的第五有源层15的交叠区域面积，可以调节第一寄生电容的大小。
在示例性实施例中，对应出射不同颜色光线的子像素，第一电极板36第五晶体管T5的两个栅电极之间的第五有源层15的交叠区域面积可以不同。
在示例性实施例中，第二电极板37设置在第一扫描信号线21和第二扫描信号线22-2之间，第二电极板37在基底上的正投影与双栅结构的第二晶体管T2的两个栅电极之间的第二有源层12在基底上的正投影存在重叠区域。第二电极板37配置为在第二晶体管T2的双栅中间节点引入第二寄生电容，以稳定第一节点N1的电位。在示例性实施例中，通过调节第二电极板37与第二晶体管T2的两个栅电极之间的第二有源层12的交叠区域面积，可以调节第二寄生电容的大小。
在示例性实施例中，对应出射不同颜色光线的子像素，第二电极板37与第二晶体管T2的两个栅电极之间的第二有源层12的交叠区域面积可以不同。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16、第十七过孔V17、第十八过孔V18、第十九过孔V19和第二十过孔V20，如图10所示。
在示例性实施例中，第一过孔V1位于存储电容第二极板34设置的第一开口34-1所在区域，第一过孔V1在基底上的正投影位于第一开口34-1在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出存储电容第一极板26的表面，第一过孔V1配置为使后续形成的第一连接电极通过该过孔与存储电容第一极板26连接。
在示例性实施例中，第二过孔V2位于阈值电容第二极板35设置的第二开口35-1所在区域，第二过孔V2内的第四绝缘层和第三绝缘层被刻蚀掉， 暴露出阈值电容第一极板27的表面，第二过孔V2配置为使后续形成的第二连接电极通过该过孔与阈值电容第一极板27连接。
在示例性实施例中，第三过孔V3位于第二电极板37所在区域，第三过孔V3内的第四绝缘层被刻蚀掉，暴露出第二电极板37的表面，第三过孔V3配置为使后续形成的第一连接电极通过该过孔与第二电极板37连接。
在示例性实施例中，第四过孔V4位于第一有源层的第一区所在区域，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第一有源层的第一区的表面，第四过孔V4配置为使后续形成的数据信号线通过该过孔与第一有源层连接。
在示例性实施例中，第五过孔V5位于第一有源层的第二区(也是第八有源层的第二区)所在区域，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第一有源层的第二区的表面，第五过孔V5配置为使后续形成的第一连接电极通过该过孔与第一有源层连接。
在示例性实施例中，第六过孔V6位于第八有源层的第一区所在区域，第六过孔V6的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第八有源层的第一区的表面，第六过孔V6配置为使后续形成的参考信号线通过该过孔与第八有源层连接。
在示例性实施例中，第七过孔V7位于第二有源层的第一区所在区域，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第二有源层的第一区的表面，第七过孔V7配置为使后续形成的第二连接电极通过该过孔与第二有源层连接。
在示例性实施例中，第八过孔V8位于第四有源层的第二区所在区域，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第四有源层的第二区的表面，第八过孔V8配置为使后续形成的第二连接电极通过该过孔与第四有源层连接。
在示例性实施例中，第九过孔V9位于第四有源层的第一区所在区域，第九过孔V9内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第四有源层的第一区的表面，第九过孔V9配置为使后续形成的第三连接 电极通过该过孔与第四有源层连接。
在示例性实施例中，第十过孔V10位于初始信号线31所在区域，第十过孔V10内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面，第十过孔V10配置为使后续形成的第三连接电极通过该过孔与初始信号线31连接。
在示例性实施例中，第十一过孔V11位于第六有源层的第一区所在区域，第十一过孔V11内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第六有源层的第一区的表面，第十一过孔V11配置为使后续形成的第三连接电极通过该过孔与第六有源层连接。
在示例性实施例中，第十二过孔V12位于第六有源层的第二区(也是第七有源层的第二区)所在区域，第十二过孔V12内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第六有源层的第二区的表面，第十二过孔V12配置为使后续形成的第四连接电极通过该过孔与第六有源层连接。
在示例性实施例中，第十三过孔V13位于第七有源层的第一区所在区域，第十三过孔V13内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第七有源层的第一区的表面，第十三过孔V13配置为使后续形成的第五连接电极通过该过孔与第七有源层连接。
在示例性实施例中，第十四过孔V14位于第二有源层的第二区(也是第三有源层的第二区)所在区域，第十四过孔V14内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第二有源层的第二区的表面，第十四过孔V14配置为使后续形成的第五连接电极通过该过孔与第二有源层连接。
在示例性实施例中，第十五过孔V15位于存储电容第二极板34所在区域，第十五过孔V15内的第四绝缘层被刻蚀掉，暴露出存储电容第二极板34的表面，第十五过孔V15配置为使后续形成的第六连接电极通过该过孔与存储电容第二极板34连接。
在示例性实施例中，第十六过孔V16位于第五有源层的第二区所在区域，第十六过孔V16内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第五有源层的第二区的表面，第十六过孔V16配置为使后续形成的第六连接电极通过该过孔与第五有源层连接。
在示例性实施例中，第十七过孔V17位于参考信号连接线32所在区域，第十七过孔V17内的第四绝缘层被刻蚀掉，暴露出参考信号连接线32的表面，第十七过孔V17配置为使后续形成的参考信号线通过该过孔与参考信号连接线32连接。
在示例性实施例中，第十八过孔V18位于第三有源层的第一区所在区域，第十八过孔V18内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第三有源层的第一区的表面，第十八过孔V18配置为使后续形成的第一电源线通过该过孔与第三有源层连接。
在示例性实施例中，第十九过孔V19位于第五有源层的第一区所在区域，第十九过孔V19内的第四绝缘层、第三绝缘层和第二绝缘层62被刻蚀掉，暴露出第五有源层的第一区的表面，第十九过孔V19配置为使后续形成的第一电源线通过该过孔与第五有源层连接。
在示例性实施例中，第二十过孔V20位于第一电源连接线33所在区域，第二十过孔V20内的第四绝缘层被刻蚀掉，暴露出第一电源连接线33的表面，第二十过孔V20配置为使后续形成的第一电源线71通过该过孔与第一电源连接线33。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45、第六连接电极46、第一电源线71、参考信号线72和数据信号线73，如图11所示。
在示例性实施例中，第一电源线71、参考信号线72和数据信号线73沿着第二方向Y延伸，第一电源线71、参考信号线72和数据信号线73可以为等宽度设置，也可以为非等宽度设置，可以为直线，或者可以为折线。
在示例性实施例中，第一电源线71通过第十八过孔V18与第三有源层的第一区连接，通过第十九过孔V19与第五有源层的第一区连接，通过第二十过孔V20与第一电源连接线33连接。沿着第二方向Y延伸的第一电源线 71通过连接沿着第一方向X延伸的第一电源连接线33，可以使得一子像素行的多个子像素具有相同的第一电源电压，提高了显示均一性。
在示例性实施例中，参考信号线72通过第六过孔V6与第八有源层的第一区连接，通过第十七过孔V17与参考信号连接线32连接。沿着第二方向Y延伸的参考信号线72通过连接沿着第一方向X延伸的参考信号连接线32，可以使得一子像素行的多个子像素具有相同的参考电压，提高了显示均一性。
在示例性实施例中，数据信号线73通过第四过孔V4与第一有源层的第一区连接。
在示例性实施例中，第一连接电极41为沿着第二方向Y延伸的直线形，一端通过第一过孔V1与存储电容第一极板26连接，另一端通过第五过孔V5与第一有源层的第二区(也是第八有源层的第二区)连接，两端之间中部位置通过第三过孔V3与第二电极板37连接。第一连接电极41同时作为第一晶体管T1的第二极和第八晶体管T8的第二极，并与存储电容Cst的第二端具有相同的电位(即第三节点N3)。
在示例性实施例中，由于第二电极板37设置在双栅结构的第二晶体管T2的两个栅电极之间的节点上，而第二电极板37与具有与第三节点N3相同的电位，因而在两个栅电极之间的第二有源层与具有第三节点N3电位的第二电极板37之间形成交叠的第二寄生电容，第二寄生电容用于稳定第一节点N1的电位。
在示例性实施例中，第一连接电极41配置为在双栅结构的第四晶体管T4的双栅中间节点引入第三寄生电容。第一连接电极41沿着第二方向Y延伸，第四晶体管T4的两个栅电极之间的第四有源层的第三区域14-3也沿着第二方向Y延伸，第一连接电极41位于第一电源线71第一方向X的反方向的一侧，第四晶体管T4的第四有源层位于第一连接电极41第一方向X的反方向的一侧，第一连接电极41邻近第三区域14-3，第四有源层的第三区域14-3在第一电源线71上的正投影与第一连接电极41在第一电源线71上的正投影存在重叠区域，即第一连接电极41沿着第一方向X在第一电源线71上的正投影与位于两个第四栅电极之间的第四有源层沿着第一方向X在第一电源线71上的正投影存在重叠区域，因而在第一连接电极41和第四有源层 的第三区域14-3之间形成侧向的第三寄生电容，第三寄生电容用于稳定第一节点N1的电位。
在示例性实施例中，第二连接电极42为沿着第二方向Y延伸的直线形，一端通过第二过孔V2与阈值电容第一极板27连接，另一端通过第八过孔V8与第四有源层的第二区连接，两端之间中部位置通过第七过孔V7与第二有源层的第一区连接。第二连接电极42同时作为第二晶体管T2的第一极和第四晶体管T4的第二极，并与阈值电容CVth的第一端具有相同的电位(即第一节点N1)。由于阈值电容第一极板27同时作为第三晶体管T3的栅电极，因而第二连接电极42实现了第二晶体管T2的第一极、第三晶体管T3的栅电极、第四晶体管T4的第二极和阈值电容第一极板27的相互连接。
在示例性实施例中，第三连接电极43为沿着第二方向Y延伸的折线形，一端通过第九过孔V9与第四有源层的第一区连接，另一端通过第十一过孔V11与第六有源层的第一区连接，两端之间中部位置通过第十过孔V10与初始信号线31连接。第三连接电极43同时作为第四晶体管T4的第一极和第六晶体管T6的第一极，实现了第四晶体管T4的第一极和第六晶体管T6的第一极同时与初始信号线31的连接。在示例性实施例中，第三连接电极43在基底上的正投影与第四晶体管T4的两个栅电极之间的第四有源层在基底上的正投影存在重叠区域。
在示例性实施例中，第四连接电极44为块状，通过第十二过孔V12与第六有源层的第二区(也是第七有源层的第二区)连接。第四连接电极44同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，实现第六晶体管T6的第二极和第七晶体管T7的第二极的连接。
在示例性实施例中，第五连接电极45为沿着第二方向Y延伸的直线形，一端通过第十三过孔V13与第七有源层的第一区连接，另一端通过第十四过孔V14与第二有源层的第二区(也是第三有源层的第二区)连接。第五连接电极45同时作为第二晶体管T2的第二极、第三晶体管T3的第二极和第七晶体管T7的第一极，使第二晶体管T2的第二极、第三晶体管T3的第二极和第七晶体管T7的第一极具有相同的电位(即第四节点N4)。
在示例性实施例中，第六连接电极46为沿着第二方向Y延伸的直线形， 一端通过第十五过孔V15与存储电容第二极板34连接，另一端通过第十六过孔V16与第五有源层的第二区连接。第六连接电极46作为第五晶体管T5的第二极，由于与存储电容第二极板34连接，而存储电容第二极板34与阈值电容第二极板35为相互连接的一体结构，因而实现了第五晶体管T5的第二极、存储电容Cst的第一端和阈值电容CVth的第二端具有相同的电位(即第二节点N2)。
在示例性实施例中，由于第一电源线71与第一电源连接线33连接，第一电源连接线33与第一电极板36连接，因而第一电极板36具有与第一电源线71相同的电位。由于第一电极板36在基底上的正投影与双栅结构的第五晶体管T5的两个栅电极之间的第五有源层15在基底上的正投影存在重叠区域，因而在两个栅电极之间的第五有源层与具有第一电源电压的第一电极板36之间形成交叠的第一寄生电容，第一寄生电容用于稳定第五晶体管T5的双栅中间节点的电位，进而稳定第二节点的电位。
(6)形成第五绝缘层图案。在示例性实施例中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，涂覆第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，第五绝缘层上设置有多个过孔，多个过孔至少包括第三十一过孔V31，如图12所示。
在示例性实施例中，第三十一过孔V31位于第四连接电极44所在区域，第三十一过孔V31内的第五绝缘层被去掉，暴露出第四连接电极44的表面，第三十一过孔V31配置为使后续形成的发光器件的阳极通过该过孔与第四连接电极44连接。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成设置在第五绝缘层上的第四导电层，第四导电层至少包括：阳极连接电极51、第二电源连接线52和第二电源线74，如图13所示。
在示例性实施例中，阳极连接电极51设置在初始信号线31远离第一发光信号线24的一侧，阳极连接电极51为矩形状，通过第三十一过孔V31与第四连接电极44连接，阳极连接电极51配置与后续形成的发光器件的阳极 连接。由于第四连接电极44同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，因而实现了发光器件的阳极与像素驱动电路的连接，使得像素驱动电路可以驱动发光器件发光。
在示例性实施例中，第二电源线74沿着第二方向Y延伸，与第一电源线71的位置相对应。第二电源连接线52沿着第一方向X延伸，设置在第一扫描信号线21和第二扫描信号线22-2之间，第二电源连接线52与第二电源线74连接。由于第二电源连接线52连接第二电源线74，因而一子像素行中的第二电源连接线52作为低电压信号连接线，使得一子像素行中各个子像素具有相同的第二电源电压，提高了显示均一性。
在示例性实施例中，第二电源线74可以为等宽度设置，或者可以为非等宽度设置，可以为直线，或者可以为折线。
在示例性实施例中，后续制备流程可以包括：形成覆盖第四导电层图案的平坦层，在平坦层上形成发光器件的阳极，形成覆盖阳极的像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。随后，采用蒸镀工艺形成有机发光层，在有机发光层上形成阴极。随后，形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光器件。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力。在示例性实施方式中，第一柔性材料层的厚度可以约为5μm至 15μm，例如为10μm；第二柔性材料层的厚度可以约为5μm至15μm，例如为10μm；第一无机材料层的厚度可以约为0.3μm至0.9μm，例如为0.6μm；第二无机材料层的厚度可以约为0.3μm至0.9μm，例如为0.6μm。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一导电层称为第一栅金属(Gate1)层，第二导电层称为第二栅金属(Gate2)层，第三导电层称为第一源漏金属(SD1)层，第四导电层称为第二源漏金属(SD2)层。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层，第五绝缘层称为钝化(PVX)层。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施例中，第一绝缘层的厚度为3000埃到5000埃，第二绝缘层的厚度为1000埃到2000埃，第三绝缘层的厚度为4500埃到7000埃，第四绝缘层的厚度为3000埃到5000埃，第五绝缘层的厚度为3000埃到5000埃。
高分辨率(PPI)显示具有更精细的画质和显示品质，已经成为设计趋势。由于高分辨率显示的像素面积较小，因而在有限空间范围内进行像素驱动电路的排布需要考虑各种干扰因素，特别是数据信号线对像素驱动电路中关键节点的影响。如图4所示的像素驱动电路中，在发光阶段，第三节点N3通过第八晶体管T8稳定在参考信号线提供的参考电压的电位，由于第二晶体管T2、第四晶体管T4和第五晶体管T5断开，因此在发光阶段，第二节点N2的漏电通路为第五晶体管T5的单漏电通道，第一节点N1的漏电通路为 第二晶体管T2和第四晶体管T4的双漏电通道。为了减小发光阶段中关键节点的漏电，一种显示基板的像素驱动电路中，第二晶体管T2、第四晶体管T4和第五晶体管T5均采用双栅结构，但该方案存在第一节点N1和第二节点N2电位稳定性差的问题。
研究表明，双栅晶体管的双栅中间节点是悬空状态，存在栅源电容(Cgs)和栅漏电容(Cgd)，当栅极电压由低电压跳变到高电压时，中间节点被耦合到高压状态，引起晶体管反向漏电，进而影响第一节点N1和第二节点N2的电位。本公开示例性实施例提出在双栅晶体管的双栅中间节点设置寄生电容，以有效稳定第一节点N1和第二节点N2的电位。图14为本公开示例性实施例像素驱动电路的等效电路图。如图14所示，在示例性实施例中，第五晶体管T5的双栅中间节点N7设置有第一寄生电容C1，第一寄生电容C1是由位于第五晶体管T5的两个第五栅电极之间的第五有源层和第一电极板36形成的交叠的电容，第一电极板36具有与第一电源线相同的电位。第二晶体管T2的双栅中间节点N5设置有第二寄生电容C2，第二寄生电容C2是由位于第二晶体管T2的两个第二栅电极之间的第二有源层和第二电极板37形成的交叠的电容，第二电极板37具有与第三节点N3相同的电位。第四晶体管T4的双栅中间节点N6设置有第三寄生电容C3，第三寄生电容C3是由第四晶体管T4的位于两个第四栅电极之间的第四有源层和第一连接电极41形成的侧向的电容，第一连接电极41具有与第三节点N3相同的电位。第四晶体管T4的双栅中间节点N6还设置有第四寄生电容C4，第四寄生电容C4是由第四晶体管T4的位于两个第四栅电极之间的第四有源层和第三连接电极43形成的交叠的电容，第三连接电极43具有与初始信号线31相同的电位。
在示例性实施例中，对于发光阶段中第二节点N2的单漏电通道，由于第一寄生电容C1的一个极板连接第五晶体管T5的双栅中间节点N7，另一个极板连接第一电源线VDD，因而避免了第五晶体管T5的双栅中间节点N7因第三扫描线S3关断引起的上跳，消除了反向漏电，有效稳定了第二节点N2的电位。
在示例性实施例中，对于发光阶段中第一节点N1的双漏电通道，由于 第二寄生电容C2的一个极板连接第二晶体管T2的双栅中间节点N5，另一个极板连接第三节点N3，第三寄生电容C3的一个极板连接第四晶体管T4的双栅中间节点N6，另一个极板连接第三节点N3，使得在数据电压Vdt耦合至第一节点N1时，第二晶体管T2的双栅中间节点N5和第四晶体管T4的双栅中间节点N6同步跳变，在第三节点N3稳定在参考电压Vref时，Vref-Vdt信息会同步叠加到第一节点N1、双栅中间节点N5和双栅中间节点N6上，使得双栅中间节点N5和双栅中间节点N6的电位接近第一节点N1的电位，因而减少了第二晶体管T2和第四晶体管T4的漏电，有效稳定了第一节点N1的电位。
在示例性实施例中，第一寄生电容C1、第二寄生电容C2、第三寄生电容C3和第四寄生电容C4的电容值可以根据实际电路进行设计，以起到稳定关键节点电位的作用。在示例性实施例中，通过调节电极板与有源层的交叠区域面积可以调节寄生电容的大小，对应出射不同颜色光线的子像素，第一寄生电容C1、第二寄生电容C2、第三寄生电容C3和第四寄生电容C4可以不同。例如，第一寄生电容C1、第二寄生电容C2、第三寄生电容C3和第四寄生电容C4的电容值可以约为0.1fF至6.0fF。
通过以上描述的显示基板的结构以及制备过程可以看出，本公开示例性实施例所提供的显示基板，通过在双栅晶体管的双栅中间节点引入寄生电容，避免了双栅中间节点的瞬间高压，消除了双栅中间节点的反向漏电，有效稳定了关键节点的电位，可以保证驱动电流的准确性，提高了显示效果。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。在示例性实施方式中，第一电极板和第二电极板可以设置在其它导电层上。例如，第一电极板和第二电极板可以设置在第一导电层上，与存储电容第一极板和阈值电容第一极板同层设置，且通过同一次图案化工艺同时形成，第一电极板和第二电极板的形状可以与前述示例性实施例相同。又如，第一电极板和第二电极板可以设置在第三导电层上，与第一连接电极和第一电源线同层设置， 且通过同一次图案化工艺同时形成，第一电极板和第二电极板的形状以及相应连接电极的结构可以根据实际需要变更，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开示例性实施例提供一种显示基板的制备方法，以制作上述示例性实施例的显示基板。在示例性实施例中，所述显示基板可以包括基底和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路包括多个晶体管，至少一个晶体管包括有源层和两个栅电极；所述制备方法包括：
在所述基底上形成半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有至少一个电极板，所述电极板在所述基底上的正投影与位于所述两个栅电极之间的有源层在所述基底上的正投影存在重叠区域。
在示例性实施例中，在所述基底上形成半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，可以包括：
在所述基底上形成半导体层；
在所述半导体层上依次形成第一导电层、第二导电层和第三导电层，所述电极板在所述第一导电层、第二导电层或第三导电层上。
在示例性实施例中，至少一个导电层上设置有与所述像素驱动电路连接的第一电源线，至少一个电极板与所述第一电源线连接。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在 不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，所述显示基板包括基底和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路包括多个晶体管，至少一个晶体管包括有源层和两个栅电极；所述基底上设置有半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有至少一个电极板，所述电极板在所述基底上的正投影与位于所述两个栅电极之间的有源层在所述基底上的正投影存在重叠区域。
  2. 根据权利要求1所述的显示基板，其中，所述多个导电层包括依次设置在所述半导体层远离所述基底一侧的第一导电层、第二导电层和第三导电层，所述电极板设置在所述第一导电层、第二导电层或第三导电层上。
  3. 根据权利要求2所述的显示基板，其中，所述显示基板还包括与所述像素驱动电路连接的第一电源线，至少一个电极板与所述第一电源线连接。
  4. 根据权利要求1至3任一项所述的显示基板，其中，所述多个晶体管至少包括第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；
    所述第一晶体管的第一极与数据信号线连接，所述第一晶体管的第二极与第三节点连接；
    所述第二晶体管的第一极与第一节点连接，所述第二晶体管的第二极与第四节点连接；
    所述第三晶体管的栅电极与第一节点连接，所述第三晶体管的第一极与第一电源线连接，所述第三晶体管的第二极与第四节点连接；
    所述第四晶体管的第一极与初始信号线连接，所述第四晶体管的第二极与第一节点连接；
    所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与第二节点连接。
  5. 根据权利要求4所述的显示基板，其中，所述像素驱动电路还包括存储电容和阈值电容，所述存储电容包括存储电容第一极板和存储电容第二 极板，所述阈值电容包括阈值电容第一极板和阈值电容第二极板；所述存储电容第一极板与所述第三节点连接，所述存储电容第二极板与所述第二节点连接；所述阈值电容第一极板与所述第一节点连接，所述阈值电容第二极板与所述第二节点连接。
  6. 根据权利要求5所述的显示基板，其中，所述存储电容第一极板和阈值电容第一极板设置在所述第一导电层上，所述存储电容第一极板和阈值电容第一极板间隔设置，所述存储电容第一极板与所述半导体层不交叠。
  7. 根据权利要求5所述的显示基板，其中，所述存储电容第二极板和阈值电容第二极板设置在所述第二导电层上，所述存储电容第二极板和阈值电容第二极板相互连接，所述存储电容第二极板在所述基底上的正投影与所述存储电容第一极板在所述基底上的正投影存在重叠区域，所述阈值电容第二极板在所述基底上的正投影与所述阈值电容第一极板在所述基底上的正投影存在重叠区域。
  8. 根据权利要求4所述的显示基板，其中，所述第五晶体管为双栅晶体管，所述第五晶体管至少包括第五有源层和两个第五栅电极；所述电极板包括第一电极板，所述第一电极板在所述基底上的正投影与位于两个第五栅电极之间的第五有源层在所述基底上的正投影存在重叠区域。
  9. 根据权利要求8所述的显示基板，其中，所述两个第五栅电极设置在所述第一导电层，所述第一电极板设置在所述第一导电层或第二导电层，所述第一电源线设置在所述第三导电层，所述第一电源线通过过孔与所述第一电极板连接。
  10. 根据权利要求9所述的显示基板，其中，所述第二导电层还包括第一电源连接线，所述第一电极板与所述第一电源连接线连接，所述第一电源线通过过孔与所述第一电源连接线连接。
  11. 根据权利要求4所述的显示基板，其中，所述第二晶体管为双栅晶体管，所述第二晶体管至少包括第二有源层和两个第二栅电极；所述电极板包括第二电极板，所述第二电极板在所述基底上的正投影与位于两个第二栅电极之间的第二有源层在所述基底上的正投影存在重叠区域。
  12. 根据权利要求11所述的显示基板，其中，所述两个第二栅电极设置在所述第一导电层，所述第二电极板设置在所述第一导电层或第二导电层，所述第三导电层还设置有第一连接电极，所述第一连接电极通过过孔与所述第二电极板连接。
  13. 根据权利要求12所述的显示基板，其中，所述第一连接电极作为所述第一晶体管的第二极，并通过过孔与所述存储电容第一极板连接。
  14. 根据权利要求12所述的显示基板，其中，所述第四晶体管为双栅晶体管，所述第四晶体管至少包括第四有源层和两个第四栅电极；所述第一连接电极在第一电源线上的正投影与位于两个第四栅电极之间的第四有源层在第一电源线上的正投影存在重叠区域。
  15. 根据权利要求4所述的显示基板，其中，所述第三导电层还设置有第二连接电极，所述第二连接电极同时作为所述第二晶体管的第一极和所述第四晶体管的第二极，所述第二连接电极通过过孔与所述阈值电容第一极板连接。
  16. 根据权利要求4所述的显示基板，其中，所述第三导电层还设置有第二连接电极，所述第三连接电极作为所述第四晶体管的第一极，所述第三连接电极通过过孔与所述初始信号线连接，所述第三连接电极在基底上的正投影与所述第四晶体管的两个栅电极之间的第四有源层在基底上的正投影存在重叠区域。
  17. 一种显示装置，其中，包括如权利要求1～16任一项所述的显示基板。
  18. 一种显示基板的制备方法，所述显示基板包括基底和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路包括多个晶体管，至少一个晶体管包括有源层和两个栅电极；所述制备方法包括：
    在所述基底上形成半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有至少一个电极板，所述电极板在所述基底上的正投影与位于所述两个栅电极之间的有源层在所述基底上的正投影 存在重叠区域。
  19. 根据权利要求18所述的显示基板的制备方法，其中，在所述基底上形成半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，包括：
    在所述基底上形成半导体层；
    在所述半导体层上依次形成第一导电层、第二导电层和第三导电层，所述电极板在所述第一导电层、第二导电层或第三导电层上。
  20. 根据权利要求19所述的显示基板的制备方法，其中，至少一个导电层上设置有与所述像素驱动电路连接的第一电源线，至少一个电极板与所述第一电源线连接。
PCT/CN2021/096915 2021-01-27 2021-05-28 显示基板及其制备方法、显示装置 WO2022160535A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/764,993 US20230200129A1 (en) 2021-01-27 2021-05-28 Display Substrate and Preparation Method thereof, and Display Apparatus
CN202180001335.3A CN115298830A (zh) 2021-01-27 2021-05-28 显示基板及其制备方法、显示装置
DE112021001804.3T DE112021001804T5 (de) 2021-01-27 2021-05-28 Anzeigesubstrat, herstellungsverfahren dafür und anzeigevorrichtung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNPCT/CN2021/073957 2021-01-27
PCT/CN2021/073957 WO2022160125A1 (zh) 2021-01-27 2021-01-27 像素驱动电路及其驱动方法、显示基板、显示装置

Publications (1)

Publication Number Publication Date
WO2022160535A1 true WO2022160535A1 (zh) 2022-08-04

Family

ID=82652675

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2021/073957 WO2022160125A1 (zh) 2021-01-27 2021-01-27 像素驱动电路及其驱动方法、显示基板、显示装置
PCT/CN2021/096915 WO2022160535A1 (zh) 2021-01-27 2021-05-28 显示基板及其制备方法、显示装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/073957 WO2022160125A1 (zh) 2021-01-27 2021-01-27 像素驱动电路及其驱动方法、显示基板、显示装置

Country Status (4)

Country Link
US (2) US11688343B2 (zh)
CN (2) CN115398523A (zh)
DE (1) DE112021001804T5 (zh)
WO (2) WO2022160125A1 (zh)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413812A (zh) * 2013-07-24 2013-11-27 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
CN103489826A (zh) * 2013-09-26 2014-01-01 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
CN103928472A (zh) * 2014-03-26 2014-07-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
CN104576659A (zh) * 2015-02-09 2015-04-29 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN108550553A (zh) * 2018-06-06 2018-09-18 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、显示装置
CN108695394A (zh) * 2017-04-06 2018-10-23 京东方科技集团股份有限公司 薄膜晶体管、其制备方法、阵列基板及显示装置
CN108767016A (zh) * 2018-05-21 2018-11-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置
CN109300995A (zh) * 2018-09-27 2019-02-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板
CN109360828A (zh) * 2018-09-27 2019-02-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN110491881A (zh) * 2018-05-14 2019-11-22 上海和辉光电有限公司 一种阵列基板、显示面板及阵列基板的制备方法
CN110520832A (zh) * 2019-07-10 2019-11-29 京东方科技集团股份有限公司 触控微发光二极管显示装置、操作触控微发光二极管显示装置的方法，以及制造触控微发光二极管显示装置的方法
CN110767539A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN111816691A (zh) * 2020-08-28 2020-10-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560482B1 (ko) 2004-04-29 2006-03-13 삼성에스디아이 주식회사 발광표시 장치 및 그 화소회로
JP4479755B2 (ja) 2007-07-03 2010-06-09 ソニー株式会社 有機エレクトロルミネッセンス素子、及び、有機エレクトロルミネッセンス表示装置
KR100911981B1 (ko) * 2008-03-04 2009-08-13 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101040893B1 (ko) * 2009-02-27 2011-06-16 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101681097B1 (ko) * 2010-07-27 2016-12-02 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR101859474B1 (ko) * 2011-09-05 2018-05-23 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치의 화소 회로
KR101964769B1 (ko) 2012-10-26 2019-04-03 삼성디스플레이 주식회사 화소, 이를 포함하는 표시장치 및 그 구동 방법
KR102043980B1 (ko) * 2013-05-13 2019-11-14 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
CN103971640B (zh) 2014-05-07 2016-08-24 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法和显示装置
KR20150138527A (ko) * 2014-05-29 2015-12-10 삼성디스플레이 주식회사 화소 회로 및 이를 포함하는 전계발광 디스플레이 장치
CN104464616B (zh) 2014-10-28 2017-10-03 上海天马有机发光显示技术有限公司 像素电路及其驱动方法、显示面板
CN105185305A (zh) 2015-09-10 2015-12-23 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN105185306A (zh) 2015-09-18 2015-12-23 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板及显示装置
US20170186782A1 (en) 2015-12-24 2017-06-29 Innolux Corporation Pixel circuit of active-matrix light-emitting diode and display panel having the same
CN205920745U (zh) * 2016-08-22 2017-02-01 京东方科技集团股份有限公司 像素电路、显示面板及显示设备
CN107316613B (zh) 2017-07-31 2019-07-09 上海天马有机发光显示技术有限公司 像素电路、其驱动方法、有机发光显示面板及显示装置
KR102485163B1 (ko) 2018-02-12 2023-01-09 삼성디스플레이 주식회사 표시장치
KR102578210B1 (ko) 2018-03-21 2023-09-13 삼성디스플레이 주식회사 유기 발광 표시 장치
CN108806587B (zh) 2018-06-26 2020-03-24 京东方科技集团股份有限公司 像素驱动电路、内嵌式触摸屏、显示装置及驱动方法
KR102623339B1 (ko) 2018-07-17 2024-01-11 삼성디스플레이 주식회사 화소 및 그것을 포함하는 유기 발광 표시 장치
CN108665852A (zh) 2018-07-23 2018-10-16 京东方科技集团股份有限公司 像素电路、驱动方法、有机发光显示面板及显示装置
CN109064972A (zh) 2018-08-30 2018-12-21 云谷（固安）科技有限公司 像素结构、驱动方法、像素电路和显示面板
CN109192143A (zh) 2018-09-28 2019-01-11 昆山国显光电有限公司 像素电路及其驱动方法、显示面板、显示装置
KR20200073419A (ko) 2018-12-14 2020-06-24 엘지디스플레이 주식회사 게이트 드라이버와 이를 포함한 유기발광다이오드 표시장치 및 그 구동방법
KR102620074B1 (ko) 2019-03-22 2024-01-02 삼성디스플레이 주식회사 발광 표시 장치
GB2593420B (en) 2019-10-14 2023-06-14 Arne Urban Svedberg Ralf Improvements in or relating to ventilation of freight containers
CN111627387B (zh) 2020-06-24 2022-09-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN111613177A (zh) 2020-06-28 2020-09-01 上海天马有机发光显示技术有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN112234091A (zh) * 2020-10-23 2021-01-15 厦门天马微电子有限公司 显示面板和显示装置

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413812A (zh) * 2013-07-24 2013-11-27 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
CN103489826A (zh) * 2013-09-26 2014-01-01 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
CN103928472A (zh) * 2014-03-26 2014-07-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
CN104576659A (zh) * 2015-02-09 2015-04-29 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN108695394A (zh) * 2017-04-06 2018-10-23 京东方科技集团股份有限公司 薄膜晶体管、其制备方法、阵列基板及显示装置
CN110491881A (zh) * 2018-05-14 2019-11-22 上海和辉光电有限公司 一种阵列基板、显示面板及阵列基板的制备方法
CN108767016A (zh) * 2018-05-21 2018-11-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置
CN108550553A (zh) * 2018-06-06 2018-09-18 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、显示装置
US20200381524A1 (en) * 2018-06-06 2020-12-03 Boe Technology Group Co., Ltd. Thin film transistor, method of manufacturing the same and display device
CN109300995A (zh) * 2018-09-27 2019-02-01 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示面板
CN109360828A (zh) * 2018-09-27 2019-02-19 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN110520832A (zh) * 2019-07-10 2019-11-29 京东方科技集团股份有限公司 触控微发光二极管显示装置、操作触控微发光二极管显示装置的方法，以及制造触控微发光二极管显示装置的方法
CN110767539A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN111816691A (zh) * 2020-08-28 2020-10-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Also Published As

Publication number Publication date
WO2022160125A1 (zh) 2022-08-04
CN115298830A (zh) 2022-11-04
US20230200129A1 (en) 2023-06-22
CN115398523A (zh) 2022-11-25
US11688343B2 (en) 2023-06-27
US20230154402A1 (en) 2023-05-18
DE112021001804T5 (de) 2023-01-05

Similar Documents

Publication Publication Date Title
WO2022062465A1 (zh) 显示基板及其制备方法、显示装置
WO2022057491A1 (zh) 显示基板及其制备方法、显示装置
WO2022179189A1 (zh) 显示基板及其制备方法、显示装置
WO2023000125A1 (zh) 显示基板及其制备方法、显示装置
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2022227005A1 (zh) 显示基板及其制备方法、显示装置
WO2022204918A1 (zh) 显示基板及其制备方法、显示装置
WO2022160535A1 (zh) 显示基板及其制备方法、显示装置
WO2022109919A1 (zh) 显示基板及其制作方法、显示装置
WO2023016341A1 (zh) 显示基板及其制备方法、显示装置
WO2023206462A1 (zh) 显示基板及其制备方法、显示装置
WO2023221040A1 (zh) 显示基板及其制备方法、显示装置
WO2024065629A1 (zh) 显示基板及其制备方法、显示装置
WO2023178612A1 (zh) 显示基板及其制备方法、显示装置
WO2023279333A1 (zh) 显示基板及显示装置
WO2023230912A1 (zh) 显示基板及其制备方法、显示装置
WO2024031315A1 (zh) 显示基板及其制备方法、显示装置
WO2022198377A1 (zh) 显示基板及其制作方法、显示装置
WO2024092434A1 (zh) 显示基板及其制备方法、显示装置
WO2022226815A1 (zh) 显示基板及其制备方法、显示装置
WO2022227478A1 (zh) 一种显示基板及其制作方法、显示装置
WO2023039886A1 (zh) 显示基板及其制备方法、显示装置
WO2023226050A1 (zh) 显示基板及其制备方法、显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21922133

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 10/11/2023)