WO2022062465A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2022062465A1
WO2022062465A1 PCT/CN2021/097380 CN2021097380W WO2022062465A1 WO 2022062465 A1 WO2022062465 A1 WO 2022062465A1 CN 2021097380 W CN2021097380 W CN 2021097380W WO 2022062465 A1 WO2022062465 A1 WO 2022062465A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
transistor
plate
conductive layer
layer
Prior art date
Application number
PCT/CN2021/097380
Other languages
English (en)
French (fr)
Inventor
郑灿
王丽
张�浩
陈义鹏
刘珂
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/763,198 priority Critical patent/US20220376024A1/en
Priority to CN202180001397.4A priority patent/CN114730544B/zh
Priority to EP21870852.7A priority patent/EP4152307A4/en
Publication of WO2022062465A1 publication Critical patent/WO2022062465A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • This article relates to the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT Thin Film Transistor
  • the present disclosure provides a display substrate, comprising a substrate, a second power supply line, a data signal line and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuits are respectively connected with the data signal line, the light-emitting device is connected with the second power supply line;
  • the substrate is provided with a semiconductor layer and a plurality of conductive layers arranged on the side of the semiconductor layer away from the substrate, at least one The conductive layer is provided with a first electrode, the first electrode is connected to the second power supply line, and the orthographic projection of the first electrode on the substrate and the orthographic projection of the data signal line on the substrate have an overlapping area.
  • the first electrode includes a first electrode segment extending in a first direction and a second electrode segment extending in a second direction, and the orthographic projection of the second electrode segment on the substrate is the same as the The orthographic projection of the data signal line on the substrate has an overlapping area, one end of the first electrode segment is connected to the second electrode segment, and the other end is connected to the second power line; the second direction is the data The extension direction of the signal line, the first direction intersects the second direction.
  • the plurality of conductive layers include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on a side of the semiconductor layer away from the substrate, the The data signal line is arranged on the fourth conductive layer, and the first electrode is arranged on the first conductive layer, the second conductive layer or the third conductive layer.
  • the second power line is disposed on the fourth conductive layer, and the second power line is connected to the first electrode through a via hole.
  • the fourth conductive layer further includes a second power supply connection line, one end of the second power supply connection line is connected to the second power supply line, and the other end of the second power supply connection line is connected to the first electrode through a via hole connect.
  • the first electrode is provided on the first conductive layer or the second conductive layer, and an interlayer connection electrode is further provided on the third conductive layer, and the interlayer connection electrode passes through the The hole is connected to the first electrode, and the second power line is connected to the interlayer connection electrode through the via hole.
  • the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; a first electrode of the first transistor is connected to the data signal line , the second pole of the first transistor is connected to the second node; the first pole of the second transistor is connected to the first node, the second pole of the second transistor is connected to the third node; the third The gate electrode of the transistor is connected to the first node, the first electrode of the third transistor is connected to the first power supply line, the second electrode of the third transistor is connected to the third node; the first electrode of the fourth transistor is connected connected connected to the initial signal line; the first pole of the fifth transistor is connected to the reference signal line, and the second pole of the fifth transistor is connected to the second node.
  • the pixel driving circuit further includes a storage capacitor and a threshold capacitor, the storage capacitor includes a first plate of the storage capacitor and a second plate of the storage capacitor, and the threshold capacitor includes a first plate of the threshold capacitor and the second plate of the threshold capacitor; the second plate of the storage capacitor is connected to the first power supply line, the first plate of the storage capacitor is connected to the first node; the second plate of the threshold capacitor is connected to the The second node is connected, and the first plate of the threshold capacitor is connected to the first node.
  • the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are arranged on the first conductive layer, and the first electrode plate of the storage capacitor and the first electrode plate of the threshold capacitor are connected to each other
  • the integrated structure, the first plate of the threshold capacitor and the semiconductor layer do not overlap.
  • the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor are arranged on the second conductive layer, and the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor are arranged at intervals from each other , the second electrode plate of the storage capacitor of this sub-pixel and the second electrode plate of the storage capacitor of the adjacent sub-pixel are an integral structure connected to each other, and the orthographic projection of the second electrode plate of the storage capacitor on the substrate is the same as that of the storage capacitor.
  • the orthographic projection of the first pole plate on the substrate has an overlapping area, and the orthographic projection of the second pole plate of the threshold capacitor on the substrate and the orthographic projection of the first pole plate of the threshold capacitor on the substrate exist overlapping area.
  • the fourth transistor is a double-gate transistor, at least including a fourth active layer and two fourth gate electrodes disposed on the semiconductor layer; the display substrate further includes a first sub-electrode Plate, the orthographic projection of the first sub-plate on the substrate and the orthographic projection of the fourth active layer located between the two fourth gate electrodes on the substrate have an overlapping area.
  • the two fourth gate electrodes are disposed on the first conductive layer, the first sub-electrode plate is disposed on the second conductive layer, and the first sub-electrode plate and the Initial signal line connection.
  • the fifth transistor is a double-gate transistor, at least including a fifth active layer and two fifth gate electrodes disposed on the semiconductor layer; the display substrate further includes a second sub-electrode plate, the orthographic projection of the second sub-plate on the substrate and the orthographic projection of the fifth active layer located between the two fifth gate electrodes on the substrate have an overlapping area.
  • the two fifth gate electrodes are disposed on the first conductive layer, the second sub-electrode plate is disposed on the second conductive layer, and the second sub-electrode plate passes through a via hole connected to the first power cord.
  • the first transistor is a double-gate transistor, including at least a first active layer and two first gate electrodes disposed on the semiconductor layer; the display substrate further includes a third sub-electrode plate, the orthographic projection of the third sub-plate on the substrate and the orthographic projection of the first active layer located between the two first gate electrodes on the substrate have an overlapping area.
  • the two first gate electrodes are disposed on the first conductive layer
  • the third sub-electrode plate is disposed on the second conductive layer
  • the third sub-electrode plate passes through a via hole connected to the first power cord.
  • the second transistor is a double-gate transistor, at least including a second active layer and two second gate electrodes disposed on the semiconductor layer;
  • the display substrate further includes a fourth sub-electrode plate, the orthographic projection of the fourth sub-plate on the substrate and the orthographic projection of the second active layer located between the two second gate electrodes on the substrate have an overlapping area.
  • the two second gate electrodes are disposed on the first conductive layer
  • the third sub-electrode plate is disposed on the second conductive layer
  • the fourth sub-electrode plate passes through a via hole connected to the first power cord.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the present disclosure also provides a method for manufacturing a display substrate, the display substrate includes a substrate, a second power line, a data signal line, and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit device, the pixel driving circuit is respectively connected with the data signal line, and the light-emitting device is connected with the second power line;
  • the preparation method includes:
  • a semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate are formed on the substrate, at least one conductive layer is provided with a first electrode, and the first electrode is connected to the second power supply line , the orthographic projection of the first electrode on the substrate and the orthographic projection of the data signal line on the substrate have an overlapping area.
  • forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate include:
  • a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer are sequentially formed on the semiconductor layer, and the first electrode is disposed on the first conductive layer, the second conductive layer or the third conductive layer layer, the second power line and the data signal line are arranged on the fourth conductive layer, and the second power line is connected to the first electrode through a via hole.
  • 1 is a schematic structural diagram of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an exemplary embodiment of the present disclosure after a semiconductor layer pattern is formed
  • FIG. 8 is a schematic diagram after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of an exemplary embodiment of the present disclosure after a fifth insulating layer pattern is formed;
  • FIG. 13 is a schematic diagram after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure.
  • 25 the second light-emitting control line
  • 26 the first plate of the storage capacitor
  • 27 the first plate of the threshold capacitor
  • 101 substrate
  • 102 drive circuit layer
  • 103 light emitting device
  • 104 encapsulation layer
  • 301 anode
  • 302 pixel definition layer
  • 303 organic light-emitting layer
  • 304 cathode
  • 401 first encapsulation layer
  • 402 the second encapsulation layer
  • 403 the third encapsulation layer.
  • the scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited to this, for example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be carried out according to actual needs. Adjustment.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only schematic structural diagrams, and an embodiment of the present disclosure is not limited to the figures. The shape or value shown in the figure, etc.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver and a pixel array, the timing controller is respectively connected with the data driver, the scan driver and the light-emitting driver, and the data driver is respectively connected with a plurality of data signal lines (D1 to Dn) are connected, the scan drivers are connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emission drivers are connected to a plurality of light emission signal lines (E1 to Eo), respectively.
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emission signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, At least one light-emitting signal line and a pixel driving circuit.
  • the timing controller may supply grayscale values and control signals suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc.
  • the driver can supply the light-emitting driver with a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data signal lines D1 , D2 , D3 , . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in pixel row units, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1 , S2 , S3 , . . .
  • the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan driver may be constructed in the form of a shift register, and may generate the scan signal in such a manner that a scan start signal supplied in the form of an on-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal , m can be a natural number.
  • the light emission driver may generate emission signals to be supplied to the light emission signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light-emitting driver may be constructed in the form of a shift register, and may generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal, o Can be a natural number.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, and a sub-pixel P1 that emits light of a second color.
  • the second sub-pixel P2 and the third sub-pixel P3 emitting light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line and the light-emitting signal line, and the pixel driving circuit is configured to connect the scanning signal line and the light-emitting signal line Under the control of the line, the data voltage transmitted by the data signal line is received, and the corresponding current is output to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to respond to the current output by the pixel driving circuit of the sub-pixel. Brightness of light.
  • the pixel unit P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels, green sub-pixels, and blue sub-pixels and white (W) sub-pixels, which are not limited in this disclosure.
  • the shape of the sub-pixels in the pixel unit may be rectangular, diamond, pentagon or hexagonal.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a zigzag manner.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal, vertical, or square manner. The arrangement is not limited in this disclosure.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of the OLED display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101 , a light emitting device 103 disposed on the side of the driving circuit layer 102 away from the substrate 101 , and a light emitting device 103 disposed on the side of the substrate 101 .
  • the encapsulation layer 104 on the side of the device 103 away from the substrate 101 .
  • the display substrate may include other film layers, such as spacer columns, etc., which are not limited in the present disclosure.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and FIG. 3 takes the example of including one driving transistor and one storage capacitor in each sub-pixel for illustration.
  • the driving circuit layer 102 of each sub-pixel may include: a first insulating layer disposed on the substrate; an active layer disposed on the first insulating layer; and a second insulating layer covering the active layer The grid electrode and the first polar plate arranged on the second insulating layer; the third insulating layer covering the grid electrode and the first polar plate; the second polar plate arranged on the third insulating layer;
  • the fourth insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are provided with via holes, and the via holes expose the active layer; the source electrode and the drain electrode arranged on the fourth insulating layer, the source electrode and the The drain electrodes are respectively connected with the active layer through via holes; the flat layer covering the
  • the light emitting device 103 may include an anode 301 , a pixel definition layer 302 , an organic light emitting layer 303 and a cathode 304 .
  • the anode 301 is arranged on the flat layer, and is connected to the drain electrode of the driving transistor 210 through a via hole opened on the flat layer;
  • the pixel definition layer 302 is arranged on the anode 301 and the flat layer, and a pixel opening is arranged on the pixel definition layer 302, and the pixel opening
  • the anode 301 is exposed;
  • the organic light-emitting layer 303 is at least partially disposed in the pixel opening, and the organic light-emitting layer 303 is connected to the anode 301;
  • the cathode 304 is disposed on the organic light-emitting layer 303, and the cathode 304 is connected to the organic light-emitting layer 303;
  • the anode 301 and the cathode 304 are driven to emit
  • the encapsulation layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials.
  • the second encapsulation layer 402 can be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that the outside water vapor cannot enter the light emitting device 103 .
  • the organic light-emitting layer 303 may include a stacked hole injection layer (Hole Injection Layer, HIL for short), a hole transport layer (Hole Transport Layer, HTL for short), an electron blocking layer (Electron Block Layer, EBL), Emitting Layer (EML), Hole Block Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL) .
  • HIL Hole Injection Layer
  • HTL Hole Transport Layer
  • EBL Electron Block Layer
  • EML Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer and the electron injection layer of all subpixels may be a common layer connected together
  • the hole transport layer and the electron transport layer of all subpixels may be a common layer connected together
  • all The hole blocking layers of the subpixels may be a common layer connected together
  • the light emitting layers and the electron blocking layers of adjacent subpixels may overlap slightly, or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T2C structure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit, illustrating an 8T2C structure. As shown in FIG.
  • the pixel driving circuit may include 8 transistors (the first transistor T1 to the eighth transistor T8 ), 2 capacitors (the storage capacitor Cst and the threshold capacitor CVth), and the pixel driving circuit is respectively connected with 10 signal lines,
  • the 10 signal lines include a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a reference signal line REF, an initial signal line INIT, A data signal line DATA, a first power supply line VDD, and a second power supply line VSS.
  • the gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the data signal line DATA, and the second electrode of the first transistor is connected to the second node N2 connect.
  • the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first power supply line VDD, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the initial signal line INIT, and the second electrode of the fourth transistor T4 is connected to the first electrode of the eighth transistor T8.
  • the gate electrode of the fifth transistor T5 is connected to the third scan signal line S3, the first electrode of the fifth transistor T5 is connected to the reference signal line REF, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the gate electrode of the sixth transistor T6 is connected to the second scan signal line S2, the first electrode of the sixth transistor T6 is connected to the initial signal line INIT, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the gate electrode of the seventh transistor T7 is connected to the first light emitting signal line EM1, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the gate electrode of the eighth transistor T8 is connected to the second light-emitting signal line EM2, the first electrode of the eighth transistor T8 is connected to the second electrode of the fourth transistor T4, and the second electrode of the eighth transistor T8 is connected to the first node N1.
  • the first end of the storage capacitor Cst is connected to the first power line VDD, and the second end of the storage capacitor Cst is connected to the first node N1.
  • the first end of the threshold capacitor CVth is connected to the second node N2, and the second end of the threshold capacitor CVth is connected to the first node N1.
  • the first to eighth transistors T1 to T8 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to eighth transistors T1 to T8 may include P-type transistors and N-type transistors.
  • the second pole of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuous high-level signal.
  • the second scan signal line S2 is the scan signal line in the pixel driving circuit of the display row
  • the third scan signal line S3 is the scan signal line in the pixel driving circuit of the previous display row.
  • the second scanning signal line S2 is S(n)
  • the third scanning signal line S3 is S(n-1)
  • the third scanning signal line S3 of this display line is the same as the first line in the pixel driving circuit of the previous display line.
  • the two scan signal lines S2 can be the same signal line, or in other words, the second scan signal line S2 of the current display line and the third scan signal line S3 in the pixel driving circuit of the next display line can be the same signal line, so as to reduce the number of display panels
  • the signal line of the display panel can realize the narrow border of the display panel.
  • the first light-emitting signal line EM1 is the light-emitting signal line in the pixel driving circuit of the display line
  • the second light-emitting signal line EM2 is the light-emitting signal line in the pixel driving circuit of the next display line, that is, for the nth display line
  • the first light-emitting signal line EM1 is EM(n)
  • the second light-emitting signal line EM2 is EM(n+1).
  • a light-emitting signal line EM1 can be the same signal line, so as to reduce the number of signal lines of the display panel and realize a narrow frame of the display panel.
  • the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the first emission signal line EM1, the second emission signal line EM2, and the initial signal line INIT may be in a horizontal direction Extending, the data signal line DATA, the first power supply line VDD, the second power supply line VSS and the reference signal line REF may extend in a vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is a working timing diagram of a pixel driving circuit.
  • the pixel driving circuit in FIG. 4 includes 8 transistors (the first transistor T1 to the eighth transistor T8 ), 2 capacitors (the storage capacitor Cst) and threshold capacitance CVth) and 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, first light-emitting signal line EM1, second light-emitting signal line EM2, reference signal line REF , the initial signal line INIT, the data signal line DATA, the first power supply line VDD and the second power supply line VSS), the eight transistors are all P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signals of the second light-emitting signal line EM2 and the third scanning signal line S3 are low-level signals.
  • the signal of EM1 is a high level signal.
  • the signal of the third scanning signal line S3 is a low-level signal, so that the fourth transistor T4 and the fifth transistor T5 are turned on, the reference signal of the reference signal line REF is supplied to the second node N2, and the second node N2 is reset to the value of the reference signal.
  • Reference voltage Vref The signal of the second light-emitting signal line EM2 is a low-level signal, which turns on the eighth transistor T8.
  • the initial signal of the initial signal line INIT is provided to the first node N1, and the first A node N1 is reset to the initial voltage Vinit of the initial signal.
  • the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.
  • the second stage A2 is called the threshold value acquisition stage.
  • the signals of the second scan signal line S2 and the third scan signal line S3 are low-level signals.
  • the signal of the line EM2 is a high level signal.
  • the signal of the second scanning signal line S2 is a low-level signal, so that the second transistor T2 and the sixth transistor T6 are turned on.
  • the second transistor T2 is turned on so that the first node N1 and the third node N3 have the same potential, the third transistor T3 forms a "diode connection" structure, the first power line VDD charges the first node N1, and the first node N1 charges to Vdd- After the
  • Vdd is the power supply voltage of the first power supply line VDD
  • Vth is the threshold voltage of the third transistor T3.
  • the sixth transistor T6 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared.
  • the signal of the third scanning signal line S3 is a low-level signal, and the fifth transistor T5 continues to be turned on, so that the second node N2 maintains the reference voltage Vref of the reference signal.
  • the first transistor T1, the third transistor T3, the seventh transistor T7 and the eighth transistor T8 are turned off, and the OLED does not emit light in this stage.
  • the signal of the signal line EM2 is a high-level signal.
  • the signal of the first scan signal line S1 is a low-level signal, so that the first transistor T1 is turned on, the data signal line DATA outputs the data voltage to the second node N2, and the second node N2 writes the data voltage Vdt. After the signals of the first node N1 and the second node N2 are superimposed, the potential of the first node N1 becomes:
  • V N1 Vdd-
  • the fourth stage A4 called the light-emitting stage, the signal of the first light-emitting signal line EM1 is a low-level signal, the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3 and the second light-emitting signal line
  • the signal of EM2 is a high level signal.
  • the signal of the first light-emitting signal line EM1 is a low-level signal, so that the seventh transistor T7 is turned on.
  • the potential of the first node N1 turns on the third transistor T3, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on third transistor T3 and the seventh transistor T7 to drive the OLED to emit light.
  • the first node N1 and the second node N2 are floating, and the original potential is maintained by the storage capacitor Cst.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode, and thus flows through the third transistor according to the potential of the first node N1
  • the drive current of T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • ⁇ is a constant
  • Vdt is the data voltage output by the data signal line DATA
  • Vref is the reference voltage output by the reference signal line REF.
  • the potential of the first node N1 is the initial voltage Vinit
  • the potential of the second node N2 is the reference voltage Vref.
  • the potential of the first node N1 is Vdd-
  • the potential of the second node N2 is the reference voltage Vref.
  • the potential of the second node N2 is the data voltage Vdt.
  • the potential of the first node N1 is V N1
  • the potential of the second node N2 is the data voltage Vdt.
  • the characteristic of the pixel driving circuit of the exemplary embodiment of the present disclosure is that the threshold acquisition stage and the data writing stage are separated in time, and the acquisition time of the threshold voltage Vth can be increased through timing control, and the compensation capability of the threshold voltage Vth of the pixel driving circuit can be improved.
  • FIG. 6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a planar structure of three sub-pixels.
  • the pixel driving circuit may include a storage capacitor, a threshold value A capacitor and a plurality of transistors, each transistor may include an active layer, a gate electrode, a first electrode and a second electrode, the storage capacitor includes a storage capacitor first plate 26 and a storage capacitor second plate 33, and the threshold capacitor includes a threshold capacitor The first plate 27 and the second plate 34 of the threshold capacitor.
  • the pixel driving circuit is connected to the first power supply line 71 and the data signal line 74 respectively, the first power supply line 71 provides a high-level signal to the pixel driving circuit, and the data signal line 74 provides a data signal to the pixel driving circuit , the light-emitting device is connected to the second power line 73, and the second power line 73 provides a low-level signal to the light-emitting device.
  • the display substrate further includes a first electrode 28, the first electrode 28 is connected to the second power supply line 73, and the orthographic projection of the first electrode 28 on the plane of the display substrate and the data signal line 74 on the plane of the display substrate There is an area of overlap for the orthographic projections on .
  • the display substrate may include a semiconductor layer and a plurality of conductive layers arranged in sequence on the substrate, and at least one of the conductive layers is provided with the first electrode 28 .
  • the plurality of conductive layers may include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on the semiconductor layer, and the data signal line 74 may be disposed on the fourth conductive layer layer, the first electrode 28 may be disposed on the first conductive layer, or may be disposed on the second conductive layer, or may be disposed on the third conductive layer.
  • the semiconductor layer may include an active layer of a plurality of transistors
  • the first conductive layer may include a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a first light emission control line Line 24, second light-emitting control line 25, storage capacitor first plate 26 and threshold capacitor first plate 27,
  • the second conductive layer may include initial signal line 31, storage capacitor second plate 33 and threshold capacitor second plate
  • the third conductive layer may include first power lines 71 and reference signal lines 72
  • the fourth conductive layer may include second power lines 73 and data signal lines 74 .
  • the first scan signal line 21 , the second scan signal line 22 , the third scan signal line 23 , the first light emission control line 24 and the second light emission control line 25 extend along the first direction X, and the storage capacitors
  • the first electrode plate 26 and the first electrode plate 27 of the threshold capacitor are an integral structure connected to each other.
  • the initial signal line 31 extends along the first direction X, and the second electrode plate 33 of the storage capacitor and the second electrode plate 34 of the threshold capacitor are arranged at intervals.
  • the first power supply line 71 , the reference signal line 72 , the second power supply line 73 and the data signal line 74 extend along the second direction Y.
  • the first direction X may be the extension direction of the scan signal lines
  • the second direction Y may be the extension direction of the data signal lines.
  • the second electrode plates 33 of the storage capacitors of adjacent subpixels in a subpixel row are connected to each other by connecting lines, and the second electrode plates 33 of the storage capacitors connected to each other in a subpixel row simultaneously serve as the first power supply
  • the connection line enables each sub-pixel in a sub-pixel row to have the same power supply voltage, which improves display uniformity.
  • the second conductive layer may include a first connection line 32 extending along the first direction X and connected to the reference signal line 72, so that each subpixel in a subpixel row has the same Reference voltage to improve display uniformity.
  • the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5; the first electrode of the first transistor T1 and the data signal line 74 connected, the second pole of the first transistor T1 is connected to the second plate 34 of the threshold capacitor; the first pole of the second transistor T2 is connected to the first plate 26 of the storage capacitor and the first plate 27 of the threshold capacitor, and the second transistor T2
  • the second pole of the third transistor T3 is connected to the second pole of the third transistor T3; the gate electrode of the third transistor T3 is connected to the first plate 26 of the storage capacitor and the first plate 27 of the threshold capacitor, and the first pole of the third transistor T3 is connected to the A power supply line 71 is connected; the first pole of the fourth transistor T4 is connected to the initial signal line 31, and the second pole of the fourth transistor T4 is connected to the first plate 26 of the storage capacitor and the first plate 27 of the threshold capacitor; the fifth transistor The first electrode of T5 is connected to
  • the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the fifth transistor T5 are dual gate transistors.
  • the second conductive layer may include a first sub-plate 35, a second sub-plate 36, a third sub-plate 37 and a fourth sub-plate 38.
  • the first sub-plate 35 is configured to introduce parasitic capacitance at the double-gate intermediate node of the fourth transistor T4
  • the second sub-plate 36 is configured to introduce parasitic capacitance at the double-gate intermediate node of the fifth transistor T5
  • the third sub-plate 37 The fourth sub-plate 38 is configured to introduce parasitic capacitance at the double-gate intermediate node of the first transistor T1
  • the fourth sub-plate 38 is configured to introduce parasitic capacitance at the double-gate intermediate node of the second transistor T2.
  • the fourth transistor T4 includes at least a fourth active layer and two fourth gate electrodes, the orthographic projection of the first sub-plate 35 on the substrate and the fourth gate electrode located between the two fourth gate electrodes.
  • the orthographic projections of the four active layers on the substrate have overlapping regions.
  • the two fourth gate electrodes are disposed on the first conductive layer, the first sub-electrode plate 35 is disposed on the second conductive layer, and the first sub-electrode plate 35 is connected to the initial signal line 31 .
  • the fifth transistor T5 includes at least a fifth active layer and two fifth gate electrodes, the orthographic projection of the second sub-plate 36 on the substrate and the third gate electrode located between the two fifth gate electrodes.
  • the orthographic projections of the five active layers on the substrate have overlapping regions.
  • the two fifth gate electrodes are disposed on the first conductive layer, the second sub-electrode plate 36 is disposed on the second conductive layer, and the second sub-electrode plate 36 is connected to the first power line 71 through via holes.
  • the first transistor T1 includes at least a first active layer and two first gate electrodes, an orthographic projection of the third sub-plate 37 on the substrate and a third sub-plate 37 located between the two first gate electrodes.
  • the orthographic projection of an active layer on the substrate has an overlapping area.
  • the two first gate electrodes are disposed on the first conductive layer
  • the third sub-electrode plate 37 is disposed on the second conductive layer
  • the third sub-electrode plate 37 is connected to the first power line 71 through via holes.
  • the second transistor T3 includes at least a second active layer and two second gate electrodes, the orthographic projection of the fourth sub-plate 38 on the substrate and the second gate electrode located between the two second gate electrodes.
  • the orthographic projections of the two active layers on the substrate have overlapping regions.
  • the two second gate electrodes are disposed on the first conductive layer, the third sub-plate 38 is disposed on the second conductive layer, and the fourth sub-plate 38 is connected to the first power line 71 through via holes.
  • the third conductive layer may include a first connection electrode 41, a second connection electrode 42, a third connection electrode, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode The connection electrode 47 , the eighth connection electrode, and the interlayer connection electrode 49 .
  • the first connection electrode 41 serves as the first electrode of the second transistor T2
  • the second connection electrode 42 serves as the second electrode of the eighth transistor T8
  • the third connection electrode serves as the first electrode of the first transistor T1
  • the fourth connection electrode 44 simultaneously As the second electrode of the first transistor T1 and the second electrode of the fifth transistor T5
  • the fifth connection electrode 45 simultaneously serves as the first electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6,
  • the sixth connection electrode 46 simultaneously As the second electrode of the fourth transistor T4 and the first electrode of the eighth transistor T8
  • the seventh connection electrode 47 simultaneously serves as the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the seventh transistor T7.
  • One pole, the eighth connection electrode simultaneously serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7
  • the interlayer connection electrode 49 is configured to connect the first electrode 28 and the second power supply line.
  • the fourth conductive layer may include an anode connection electrode 51 configured to connect the eighth connection electrode and an anode of the light emitting device.
  • the first electrode 28 may include a first electrode segment extending along the first direction X and a second electrode segment extending along the second direction Y, and the orthographic projection of the second electrode segment on the substrate corresponds to the data signal
  • the orthographic projection of the line 74 on the substrate has an overlapping area, one end of the first electrode segment is connected to the second electrode segment, and the other end is connected to the second power line through a via hole.
  • the third conductive layer may include a second power supply connection line 75, one end of the second power supply connection line 75 is connected to the second power supply line 73, and the other end is connected to the interlayer connection electrode 49 through a via hole.
  • the intermediate connection electrode 49 is connected to the first electrode 28 through a via hole.
  • the display substrate may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer, the first insulating layer is disposed between the substrate and the semiconductor layer, and the first insulating layer is disposed between the substrate and the semiconductor layer.
  • the second insulating layer is provided between the semiconductor layer and the first conductive layer
  • the third insulating layer is provided between the first conductive layer and the second conductive layer
  • the fourth insulating layer is provided between the second conductive layer and the third conductive layer
  • the fifth insulating layer is arranged between the third conductive layer and the fourth conductive layer.
  • the orthographic projection of the first electrode on the substrate and the orthographic projection of the data signal line on the substrate have an overlapping area, and the first electrode is connected to the second power supply line , which effectively shields the influence of the data voltage jump on the key nodes, avoids the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit, and improves the display effect.
  • the following is an exemplary description through the preparation process of the display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is located within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A Overlaps the boundary of the orthographic projection of B.
  • A's orthographic projection includes B's orthographic projection means that the boundary of B's orthographic projection falls within the boundary of A's orthographic projection, or the boundary of A's orthographic projection overlaps with the boundary of B's orthographic projection.
  • the preparation process of the display substrate may include the following operations.
  • a semiconductor layer pattern is formed.
  • forming the semiconductor layer pattern may include: sequentially depositing a first insulating thin film and a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, forming a first insulating layer covering the substrate, and disposing on the substrate The semiconductor layer on the first insulating layer is shown in FIG. 7 .
  • the semiconductor layer of at least one sub-pixel may include the first active layer of the first transistor T1 to the eighth active layer of the eighth transistor T8, the first active layer 11 of the first transistor T1,
  • the third active layer 13 of the third transistor T3 and the fifth active layer 15 of the fifth transistor T5 are provided separately, the second active layer 12 of the second transistor T2 and the sixth active layer 16 of the sixth transistor T6
  • the seventh active layer 17 of the seventh transistor T7 is an integral structure connected to each other
  • the fourth active layer 14 of the fourth transistor T4 and the eighth active layer 18 of the eighth transistor T8 are an integral structure connected to each other.
  • the fourth active layer 14 of the pixel is connected to the sixth active layer 16 of the subpixels in the previous subpixel row
  • the sixth active layer 16 of this subpixel is connected to the fourth active layer of the subpixels in the next subpixel row. 14 connections.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first and second regions.
  • the shape of the first active layer 11 is a “ji” shape, and two ends of the “ji” shape are the first region 11 - 1 of the first active layer 11 and the first active layer 11 respectively
  • the second region 11-2, the first region 11-1 of the first active layer 11 and the second region 11-2 of the first active layer 11 are provided separately.
  • the shape of the second active layer 12 is a "Led-down L" shape, and two ends of the "Led-down L" shape are the first region 12 - 1 and the first region 12 - 1 of the second active layer 12 , respectively.
  • the second region 12-2 of the second active layer 12 and the first region 12-1 of the second active layer 12 are provided separately, and the second region 12-2 of the second active layer 12 simultaneously serves as the seventh active layer
  • the first region 17-1 of 17, that is, the second region 12-2 of the second active layer 12 and the first region 17-1 of the seventh active layer 17 are connected to each other.
  • the shape of the third active layer 13 is a wavy line extending along the second direction Y, and two ends of the wavy line are the first region 13 - 1 and the first region 13 - 1 of the third active layer 13 respectively.
  • the second region 13-2 of the three active layers 13, the first region 13-1 of the third active layer 13 is close to the first active layer 11, and the second region 13-2 of the third active layer 13 is close to the second Active layer 12 .
  • the shape of the fourth active layer 14 is a bifold line extending along the second direction Y, and two ends of the bifold line are respectively the first regions 14 - 1 of the fourth active layer 14 . and the second region 14 - 2 of the fourth active layer 14 .
  • the first region 14-1 of the fourth active layer 14 also serves as the first region 16-1 of the sixth active layer 16 of the subpixel in the previous subpixel row, that is, the first region 16-1 of the fourth active layer 14 of the current subpixel.
  • a region 14-1 is interconnected with the first region 16-1 of the sixth active layer 16 of the subpixels in the previous subpixel row.
  • the second region 14-2 of the fourth active layer 14 simultaneously serves as the first region 18-1 of the eighth active layer 18, that is, the second region 14-2 of the fourth active layer 14 and the eighth active layer 18
  • the first zones 18-1 are connected to each other.
  • the shape of the fifth active layer 15 is a “ji” shape, and two ends of the “ji” shape are the first region 15 - 1 of the fifth active layer 15 and the fifth active layer 15 respectively
  • the second region 15-2 of the fifth active layer 15, the first region 15-1 of the fifth active layer 15 and the second region 15-2 of the fifth active layer 15 are separately arranged.
  • the shape of the sixth active layer 16 is a "one" shape, and two ends of the "one" shape are the first region 16 - 1 of the sixth active layer 16 and the sixth active layer 16 respectively The second district 16-2.
  • the first region 16-1 of the sixth active layer 16 simultaneously serves as the first region 14-1 of the fourth active layer 14 of the subpixel in the next subpixel row, that is, the first region 16-1 of the sixth active layer 16 of the subpixel.
  • a region 16-1 is interconnected with the first region 14-1 of the fourth active layer 14 of the subpixels in the next subpixel row.
  • the second region 16-2 of the sixth active layer 16 simultaneously serves as the second region 17-2 of the seventh active layer 17, that is, the second region 16-2 of the sixth active layer 16 and the seventh active layer 17
  • the second regions 17-2 are connected to each other.
  • the shape of the seventh active layer 17 is a "1" shape, and two ends of the "1" shape are the first region 17-1 of the seventh active layer 17 and the seventh active layer T7 respectively
  • the second region 17-2 of the seventh active layer 17 simultaneously serves as the second region 12-2 of the second active layer 12, and the second region 17-2 of the seventh active layer T7 also serves as the second region 16 - 2 of the sixth active layer 16 .
  • the shape of the eighth active layer 18 is a “1” shape, and two ends of the “1” shape are the first region 18 - 1 of the eighth active layer 18 and the eighth active layer 18 respectively
  • the second region 18-2 of the eighth active layer 18 simultaneously serves as the second region 14-2 of the fourth active layer 14, and the second region 18-2 of the eighth active layer 18 Set individually.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first metal film on the substrate on which the foregoing pattern is formed, and patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a first scan signal line 21, a second scan signal line 22, a third scan signal line
  • the signal line 23 , the first light emission control line 24 , the second light emission control line 25 , the first electrode plate 26 of the storage capacitor, the first electrode plate 27 of the threshold capacitor and the first electrode 28 are shown in FIG. 8 .
  • the first scan signal line 21 , the second scan signal line 22 , the third scan signal line 23 , the first light emission control line 24 and the second light emission control line 25 extend along the first direction X.
  • the first electrode plate 26 of the storage capacitor, the first electrode plate 27 of the threshold capacitor and the first electrode 28 are disposed between the first scan signal line 21 and the second scan signal line 22, and are located in the middle of the sub-pixel in the second direction Y.
  • the first electrode plate 26 of the storage capacitor is close to the second scan signal line 22
  • the first electrode plate 27 of the threshold capacitor is close to the first scan signal line 21 .
  • the first light-emitting control line 24 is arranged on the side of the second scanning signal line 22 away from the first plate 26 of the storage capacitor, and the third scanning signal line 23 and the second light-emitting control line 25 are arranged on the first scanning signal line 21 away from the threshold capacitor.
  • the second light emission control line 25 is disposed between the first scanning signal line 21 and the third scanning signal line 23 .
  • the first electrode 28 is in the shape of a broken line, and includes a first electrode segment 28-1 extending along a first direction X and a second electrode segment 28-2 extending along a second direction Y, the first The ends of the electrode segment 28-1 and the second electrode segment 28-2 adjacent to each other are connected to each other, the first electrode segment 28-1 is configured to be connected to the second power supply line formed subsequently, and the second electrode segment 28-2 is connected to the subsequently formed second power supply line.
  • the data signal lines overlap and are configured to shield the influence of data voltage jumps on the data signal lines on key nodes, so as to prevent the data voltage jumps from affecting the potential of key nodes of the pixel driving circuit, thereby improving the display effect.
  • the outline of the first electrode plate 26 of the storage capacitor may be rectangular, and the corners may be chamfered.
  • the outline of the first electrode plate 27 of the threshold capacitor can be rectangular, the rectangular shape is provided with concave grooves near the corner of the second electrode segment 28 - 2 of the first electrode 28 , and the rectangular shape is provided with concave grooves near the corner of the third active layer 13 . Oops, the corners can be chamfered.
  • the storage capacitor first plate 26 and the threshold capacitor first plate 27 are connected to each other by connecting lines.
  • the first electrode plate 26 of the storage capacitor and the first electrode plate 27 of the threshold capacitor are an integral structure connected to each other.
  • the first scan signal line 21 , the second scan signal line 22 , the third scan signal line 23 , the first light-emitting control line 24 and the second light-emitting control line 25 may be set with the same width, or may be The width is not equal, and the width is the dimension of the second direction Y.
  • a plurality of second gate blocks may be disposed on the second scan signal line 22, each second gate block is disposed in each sub-pixel, and one end of the second gate block is connected to the second scan signal The line 22 is connected, and the other end extends along the second direction Y to form a second transistor with double gates.
  • a plurality of third gate blocks may be provided on the third scan signal line 23, each third gate block is provided in each sub-pixel, one end of the third gate block is connected to the third scan signal line 23, and the other end is along the extending in the opposite direction of the second direction Y to form a fourth transistor with double gates.
  • the region where the first scan signal line 21 and the first active layer 11 overlap serves as the gate electrode of the first transistor T1 (dual gate structure), and the second scan signal line 22 and the second active layer serve as the gate electrode (dual gate structure)
  • the overlapping area of 12 is used as the gate electrode of the second transistor T2 (dual gate structure), and the orthographic projection of the first electrode plate 26 of the storage capacitor on the substrate and the orthographic projection of the third active layer 13 on the substrate have an overlapping area.
  • the first electrode plate 26 of the capacitor also serves as the gate electrode of the third transistor T3, and the overlapping area of the third scanning signal line 23 and the fourth active layer 14 serves as the gate electrode (dual gate structure) of the fourth transistor T4.
  • the area where the signal line 23 overlaps with the fifth active layer 15 is used as the gate electrode of the fifth transistor T5 (dual gate structure), and the area where the second scanning signal line 22 overlaps with the sixth active layer 16 is used as the sixth transistor T6
  • the gate electrode of the first light-emitting control line 24 and the seventh active layer 17 is used as the gate electrode of the seventh transistor T7, and the region where the second light-emitting control line 25 and the eighth active layer 18 overlap is used as the eighth transistor T7.
  • the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all switching transistors
  • the third transistor T3 is a driving transistor.
  • the orthographic projection of the threshold capacitor first plate 27 on the substrate and the orthographic projection of the third active layer 13 on the substrate have no overlapping area.
  • the first conductive layer may be used as a shield to conduct a conductorization process on the semiconductor layer, and the semiconductor layers in the shielded regions of the first conductive layer form the first transistors T1 to T1 to eighth In the channel region of the transistor T8, the semiconductor layer in the region not shielded by the first conductive layer is conductive, that is, the first and second regions from the first active layer to the eighth active layer are all conductive.
  • a second conductive layer pattern is formed.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second metal film on the substrate on which the foregoing pattern is formed, and patterning the second metal film using a patterning process to form A third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least includes: an initial signal line 31, a first connection line 32, and a second electrode of the storage capacitor The plate 33 and the second plate 34 of the threshold capacitor are shown in FIG. 9 .
  • the initial signal line 31 and the first connection line 32 extend along the first direction X, the initial signal line 31 is disposed on the side of the third scan signal line 23 away from the second light emission control line 25, and the first connection
  • the line 32 is arranged between the second scanning signal line 22 and the first light-emitting control line 24, and the first connecting line 32 is configured to be connected to the reference signal line formed subsequently, so that each sub-pixel in a sub-pixel row has the same reference voltage , to improve display uniformity.
  • the initial signal line 31 and the first connection line 32 may be set with equal widths, or may be set with unequal widths.
  • the storage capacitor second plate 33 and the threshold capacitor second plate 34 are disposed between the first scan signal line 21 and the second scan signal line 22, the storage capacitor second plate 33 and the threshold capacitor
  • the second pole plates 34 are arranged at intervals.
  • the outline of the second electrode plate 33 of the storage capacitor may be rectangular, and the corners of the rectangle may be provided with chamfers.
  • the orthographic projection of the plate 26 on the substrate presents an area of overlap.
  • the second electrode plate 33 of the storage capacitor is provided with a first opening 33-1.
  • the first opening 33-1 can be rectangular and is located in the middle of the second electrode plate 33 of the storage capacitor.
  • the plate 33 forms an annular structure.
  • the first opening 33-1 exposes the third insulating layer covering the first electrode plate 26 of the storage capacitor, and the orthographic projection of the first electrode plate 26 of the storage capacitor on the substrate includes the orthographic projection of the first opening 33-1 on the substrate.
  • the first opening 33-1 is configured to accommodate a first via hole formed later, the first via hole is located in the first opening 33-1 and exposes the first electrode plate 26 of the storage capacitor, so that the subsequent The formed first connection electrode is connected to the first electrode plate 26 of the storage capacitor through the first via hole.
  • the shape of the second electrode plate 34 of the threshold capacitor is similar to the shape of the first electrode plate 27 of the threshold capacitor, which is a rectangle with grooves at two corners, and the second electrode plate 34 of the threshold capacitor is on the substrate.
  • the orthographic projection of , and the orthographic projection of the threshold capacitor first plate 27 on the substrate have an overlapping area.
  • the second electrode plate 34 of the threshold capacitor is provided with a second opening 34-1.
  • the second opening 34-1 can be rectangular and is located in the middle of the second electrode plate 34 of the threshold capacitor.
  • the second opening 34-1 makes the second electrode of the threshold capacitor 34-1.
  • the plate 34 forms an annular structure.
  • the second opening 34-1 exposes the third insulating layer covering the threshold capacitor first plate 27, and the orthographic projection of the threshold capacitor first plate 27 on the substrate includes the orthographic projection of the second opening 34-1 on the substrate.
  • the second opening 34-1 is configured to accommodate a second via hole formed later, the second via hole is located in the second opening 34-1 and exposes the first electrode plate 27 of the threshold capacitor, so that subsequent The formed second connection electrode is connected to the first electrode plate 27 of the threshold capacitor through the second via hole.
  • the first electrode plate 26 of the storage capacitor and the second electrode plate 33 of the storage capacitor constitute the storage capacitor Cst of the pixel driving circuit, and the first electrode plate 26 of the storage capacitor serves as the second end of the storage capacitor Cst, and also serves as the second end of the storage capacitor Cst.
  • the gate electrode of the three transistors T3 and the second electrode plate 33 of the storage capacitor serve as the first end of the storage capacitor Cst, and are connected to the first power supply line VDD formed subsequently.
  • the threshold capacitor first plate 27 and the threshold capacitor second plate 34 constitute the threshold capacitor CVth of the pixel driving circuit, and the threshold capacitor first plate 27 serves as the first end of the threshold capacitor CVth, which is formed with the subsequent formation of the threshold capacitor CVth.
  • the second electrode of the first transistor T1 is connected, and the second electrode plate 34 of the threshold capacitor serves as the second end of the threshold capacitor CVth, and is connected to the second end of the storage capacitor Cst.
  • the storage capacitor second plates 33 of adjacent sub-pixels in a sub-pixel row are connected to each other by connecting lines. Since the second electrode plate 33 of the storage capacitor is connected to the first power supply line formed subsequently, the second electrode plate 33 of the storage capacitor connected to each other in a sub-pixel row also serves as the first power supply connection line, so that each sub-pixel row in a sub-pixel row The pixels have the same supply voltage, improving display uniformity.
  • the threshold capacitor second plates 34 of adjacent subpixels in a subpixel row are arranged at intervals, so that the threshold capacitor CVth of each subpixel only reflects the threshold voltage of the driving transistor of the subpixel.
  • each sub-pixel may be provided with a first sub-plate 35 , a second sub-plate 36 , a third sub-plate 37 and a fourth sub-plate 38 .
  • the first sub-plate 35 may be in an "L" shape, one end of the first sub-plate 35 is connected to the initial signal line 31, and the orthographic projection of the other end on the substrate is located between the gate electrodes of the two fourth transistors T4.
  • the orthographic projection of the fourth active layer 14 on the substrate has an overlapping area.
  • the first sub-plate 35 is configured to introduce parasitic capacitance at the double gate intermediate node of the fourth transistor T4 to stabilize the potential of key nodes in the pixel driving circuit, thereby improving the flicker of the display substrate and adjusting the off-state leakage current of the fourth transistor T4.
  • the second sub-plate 36 may be in the shape of "1", the orthographic projection of the second sub-plate 36 on the substrate and the positive projection of the fifth active layer 15 on the substrate between the gate electrodes of the two fifth transistors T5 Projections have overlapping areas.
  • the second sub-plate 36 is configured to introduce parasitic capacitance at the double gate intermediate node of the fifth transistor T5 to adjust the off-state leakage current of the fifth transistor T5 and stabilize the potential of key nodes in the pixel driving circuit, thereby improving the flicker of the display substrate.
  • the third sub-plate 37 may be in the shape of a "one", the orthographic projection of the third sub-plate 37 on the substrate and the orthographic projection of the first active layer 11 between the gate electrodes of the two first transistors T1 on the substrate Projections have overlapping areas.
  • the third sub-plate 37 is configured to introduce parasitic capacitance at the double gate intermediate node of the first transistor T1 to adjust the off-state leakage current of the first transistor T1 and stabilize the potential of key nodes in the pixel driving circuit, thereby improving the flicker of the display substrate.
  • the fourth sub-plate 38 may be in the shape of a "one", and the orthographic projection of the fourth sub-plate 38 on the substrate and the orthographic projection of the second active layer 12 between the gate electrodes of the two second transistors T2 on the substrate. Projections have overlapping areas.
  • the fourth sub-plate 38 is configured to introduce parasitic capacitance at the double gate intermediate node of the second transistor T2 to adjust the off-state leakage current of the second transistor T2, stabilize the potential of key nodes in the pixel driving circuit, and further improve the flicker of the display substrate.
  • a fourth insulating layer pattern is formed.
  • forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fourth insulating film by a patterning process to form a pattern covering the second conductive layer.
  • the fourth insulating layer, the fourth insulating layer is provided with a plurality of vias, and the plurality of vias at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via Via V5, sixth via V6, seventh via V7, eighth via V8, ninth via V9, tenth via V10, eleventh via V11, twelfth via V12, tenth via
  • the via hole V20 and the twenty-first via hole V21 are shown in FIG. 10 .
  • the first via hole V1 is located in the region where the first opening 33-1 provided on the second electrode plate 33 of the storage capacitor is located, and the orthographic projection of the first via hole V1 on the substrate is located at the location where the first opening 33-1 is located.
  • the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away, exposing the surface of the first electrode plate 26 of the storage capacitor, and the first via hole V1 is configured as The first connection electrode formed subsequently is connected to the first electrode plate 26 of the storage capacitor through the via hole.
  • the second via hole V2 is located in the region where the second opening 34 - 1 provided in the second electrode plate 34 of the threshold capacitor is located, and the fourth insulating layer and the third insulating layer in the second via hole V2 are etched The surface of the first electrode plate 27 of the threshold capacitor is exposed, and the second via hole V2 is configured to connect the second connection electrode formed subsequently to the first electrode plate 27 of the threshold capacitor through the through hole.
  • the third via hole V3 is located in the region where the third sub-plate 37 is located, and the fourth insulating layer in the third via V3 is etched away to expose the surface of the third sub-plate 37.
  • the three via holes V3 are configured so that the first power supply line formed later is connected to the third sub-electrode plate 37 through the via holes, so as to provide a constant power supply voltage for the third sub-electrode plate 37 .
  • the fourth via hole V4 is located in the region where the first region of the first active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away , the surface of the first region of the first active layer is exposed, and the fourth via hole V4 is configured to connect the third connection electrode formed subsequently to the first active layer through the via hole.
  • the fifth via hole V5 is located in the region where the second region of the first active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away , the surface of the second region of the first active layer is exposed, and the fifth via hole V5 is configured to connect the fourth connection electrode formed subsequently to the first active layer through the via hole.
  • the sixth via hole V6 is located in the region where the second sub-plate 36 is located, the fourth insulating layer in the sixth via V6 is etched away, exposing the surface of the second sub-plate 36, and the first The six via holes V6 are configured to connect the subsequently formed first power line to the second sub-electrode plate 36 through the via hole, so as to provide a constant power supply voltage for the second sub-electrode plate 36 .
  • the seventh via hole V7 is located in the region where the first region of the fifth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away , the surface of the first region of the fifth active layer is exposed, and the seventh via hole V7 is configured to connect the reference signal line formed subsequently to the fifth active layer through the via hole.
  • the eighth via hole V8 is located in the region where the second region of the fifth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away , the surface of the second region of the fifth active layer is exposed, and the eighth via hole V8 is configured to connect the fourth connection electrode formed subsequently to the fifth active layer through the via hole.
  • the ninth via hole V9 is located in the region where the first region of the fourth active layer (also the first region of the sixth active layer) is located, and the fourth insulating layer, the first region of the fourth active layer in the ninth via hole V9
  • the third insulating layer and the second insulating layer are etched away, exposing the surface of the first region of the fourth active layer, and the ninth via hole V9 is configured so that the fifth connection electrode formed subsequently is connected to the fourth active layer through the via hole. source layer connection.
  • the tenth via hole V10 is located in the region where the second region of the fourth active layer (also the first region of the eighth active layer) is located, and the fourth insulating layer, the first region of the fourth active layer in the tenth via hole V10
  • the third insulating layer and the second insulating layer are etched away, exposing the surface of the second region of the fourth active layer, and the tenth via hole V10 is configured to allow the sixth connection electrode formed subsequently to pass through the via hole to connect with the fourth active layer. source layer connection.
  • the eleventh via hole V11 is located in the region where the second region of the eighth active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched The surface of the second region of the eighth active layer is exposed, and the eleventh via hole V11 is configured to connect the second connection electrode formed subsequently to the eighth active layer through the via hole.
  • the twelfth via hole V12 is located in the region where the first region of the third active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched etched away to expose the surface of the first region of the third active layer, and the twelfth via hole V12 is configured to connect the first power supply line formed subsequently to the third active layer through the via hole.
  • the thirteenth via hole V13 is located in the region where the second region of the third active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the thirteenth via hole V13 are etched The surface of the second region of the third active layer is exposed, and the thirteenth via hole V13 is configured to connect the seventh connection electrode formed subsequently to the third active layer through the via hole.
  • the fourteenth via hole V14 is located in the region where the first region of the second active layer is located, and the fourth insulating layer, the third insulating layer and the second insulating layer in the fourteenth via hole V14 are etched etched away to expose the surface of the first region of the second active layer, and the fourteenth via hole V14 is configured to connect the subsequently formed first connection electrode to the second active layer through the via hole.
  • the fifteenth via hole V15 is located in the region where the second region of the second active layer (also the first region of the seventh active layer) is located, and the fourth insulating layer in the fifteenth via hole V15 , the third insulating layer and the second insulating layer are etched away, exposing the surface of the second region of the second active layer, and the fifteenth via hole V15 is configured to allow the seventh connection electrode formed subsequently to pass through the via hole with the The second active layer is connected.
  • the sixteenth via hole V16 is located in the region where the fourth sub-plate 38 is located, and the fourth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the fourth sub-plate 38 , the sixteenth via hole V16 is configured to connect the subsequently formed first power line to the fourth sub-electrode plate 38 through the via hole, so as to provide a constant power supply voltage for the fourth sub-electrode plate 38 .
  • the seventeenth via hole V17 is located in the region where the first connection line 32 is located, and the fourth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the first connection line 32.
  • the seventeen via holes V17 are configured so that the reference signal line formed later is connected to the first connection line 32 through the via holes.
  • the eighteenth via hole V18 is located in the region where the initial signal line 31 is located, and the fourth insulating layer in the eighteenth via hole V18 is etched away to expose the surface of the initial signal line 31.
  • the eighteenth via hole V18 is etched away.
  • the via hole V18 is configured so that the fifth connection electrode 45 formed later is connected to the initial signal line 31 through the via hole.
  • the nineteenth via hole V19 is located in the area where the second electrode plate 33 of the storage capacitor is located, and the fourth insulating layer in the nineteenth via hole V19 is etched away, exposing the second electrode plate 33 of the storage capacitor , the nineteenth via hole V19 is configured so that the first power line formed subsequently is connected to the second electrode plate 33 of the storage capacitor through the via hole.
  • the number of the nineteenth vias V19 may be one or more, the plurality of the nineteenth vias V19 are sequentially arranged along the second direction Y, and the plurality of the nineteenth vias V19 may improve the The reliability of the connection between a power line and the second plate 33 of the storage capacitor.
  • the twentieth via hole V20 is located in the region where the second electrode segment 28-2 of the first electrode 28 is located, and the fourth insulating layer and the third insulating layer in the twentieth via hole V20 are etched away , the surface of the second electrode segment 28-2 of the first electrode 28 is exposed, and the twentieth via hole V20 is configured so that the subsequently formed interlayer connection electrode passes through the via hole and the second electrode segment 28-2 of the first electrode 28- 2 connections.
  • the twenty-first via hole V21 is located in the region where the second region of the sixth active layer (also the second region of the seventh active layer) is located, and the fourth via hole V21 in the twenty-first via hole V21 is located
  • the insulating layer, the third insulating layer and the second insulating layer are etched away, exposing the surface of the second region of the sixth active layer, and the twenty-first via hole V21 is configured to allow the ninth connection electrode formed subsequently to pass through the The via hole is connected to the second active layer.
  • a third conductive layer pattern is formed.
  • forming the third conductive layer may include: depositing a third metal thin film on the substrate on which the aforementioned patterns are formed, patterning the third metal thin film by a patterning process, and forming a third metal thin film disposed on the fourth insulating layer
  • the third conductive layer includes at least: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a Seven connection electrodes 47 , eighth connection electrodes 48 , interlayer connection electrodes 49 , first power supply lines 71 and reference signal lines 72 , as shown in FIG. 11 .
  • the first power supply line 71 and the reference signal line 72 extend along the second direction Y, and the first power supply line 71 and the reference signal line 72 may be provided with equal widths or unequal widths, and may be A straight line, or it can be a polyline.
  • the first power line 71 is connected to the third sub-plate 37 through the third via V3, is connected to the second sub-plate 36 through the sixth via V6, and is connected to the twelfth via V12.
  • the first region of the third active layer is connected to the fourth sub-plate 38 through the sixteenth via V16, and is connected to the storage capacitor second plate 33 through the nineteenth via V19.
  • the reference signal line 72 is connected to the first region of the fifth active layer through the seventh via hole V7, and is connected to the first connection line 32 through the seventeenth via hole V17.
  • the first connection electrode 41 is in the shape of a strip extending along the second direction Y, one end is connected to the first electrode plate 26 of the storage capacitor through the first via hole V1, and the other end is connected to the first electrode plate 26 of the storage capacitor through the fourteenth via hole V14.
  • the first region of the second active layer is connected, so that the first electrode of the second transistor T2 is connected to the first electrode plate 26 of the storage capacitor. Since the first electrode plate 26 of the storage capacitor serves as the gate electrode of the third transistor T3 at the same time, the first connection electrode 41 serves as the first electrode of the second transistor T2, realizing the first electrode of the second transistor T2 and the connection of the third transistor T3.
  • the gate electrode and the second terminal of the storage capacitor Cst have the same potential.
  • the second connection electrode 42 is a strip extending along the second direction Y, one end is connected to the first electrode plate 27 of the threshold capacitor through the second via hole V2, and the other end is connected to the first electrode plate 27 of the threshold capacitor through the eleventh via hole V11.
  • the second region of the eighth active layer is connected, so that the second electrode of the eighth transistor T8 is connected to the first electrode plate 27 of the threshold capacitor.
  • the second connection electrode 42 acts as the second electrode of the eighth transistor T8 to realize the first electrode of the second transistor T2
  • the gate electrode of the third transistor T3, the second electrode of the eighth transistor T8, the second terminal of the storage capacitor Cst, and the second terminal of the threshold capacitor CVth have the same potential (ie, the first node N1).
  • the third connection electrode 43 is disposed between the first power supply line 71 and the reference signal line 72, and is connected to the first region of the first active layer through the fourth via V4, and the third connection electrode 43 As the first electrode of the first transistor T1, the third connection electrode 43 is configured to be connected to a data signal line formed later.
  • the fourth connection electrode 44 is a strip extending along the second direction Y, one end is connected to the second region of the first active layer through the fifth via hole V5, and the other end is connected to the second region of the first active layer through the eighth via hole V8 Connected to the second region of the fifth active layer, the fourth connection electrode 44 simultaneously serves as the second pole of the first transistor T1 and the second pole of the fifth transistor T5, so that the second pole of the first transistor T1 and the fifth transistor The second pole of T5 has the same potential (ie, the second node N2).
  • the fifth connection electrode 45 is in the shape of a strip extending along the second direction Y, and one end passes through the ninth via V9 and the first region of the fourth active layer (also the first region of the sixth active layer). area) connection, the other end is connected to the initial signal line 31 through the eighteenth via hole V18, the fifth connection electrode 45 simultaneously serves as the first pole of the fourth transistor T4 and the first pole of the sixth transistor T6 to realize the fourth transistor T4 The first pole of and the sixth transistor T6 are connected to the initial signal line 31 at the same time.
  • the sixth connection electrode 46 has a rectangular shape, is connected to the second region of the fourth active layer (also the first region of the eighth active layer) through the tenth via hole V10, and the sixth connection electrode 46 serves as the second pole of the fourth transistor T4 and the first pole of the eighth transistor T8 at the same time, and realizes the connection between the second pole of the fourth transistor T4 and the first pole of the eighth transistor T8.
  • the seventh connection electrode 47 is a strip extending along the second direction Y, one end is connected to the second region of the third active layer through the thirteenth via V13, and the other end is connected to the second region of the third active layer through the fifteenth through hole V13.
  • the hole V15 is connected to the second region of the second active layer (also the first region of the seventh active layer), and the seventh connection electrode 47 simultaneously serves as the second pole of the second transistor T2 and the second pole of the third transistor T3 and the first electrode of the seventh transistor T7, so that the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the seventh transistor T7 have the same potential (ie, the third node N3).
  • the eighth connection electrode 48 has a rectangular shape and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the twenty-first via hole V21, and the eighth The connection electrode 48 simultaneously serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and realizes the connection between the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7.
  • the interlayer connection electrode 49 is disposed between the reference signal line 72 and the second connection electrode 42, the interlayer connection electrode 49 is connected to the first electrode 28 through the twentieth via hole V20, and the interlayer connection electrode 49 is configured to be connected to a second power supply line formed later.
  • a fifth insulating layer pattern is formed.
  • forming the fifth insulating layer pattern may include: coating a fifth insulating film on the substrate on which the foregoing pattern is formed, and patterning the fifth insulating film by a patterning process to form a covering third conductive layer
  • the fifth insulating layer, the fifth insulating layer is provided with a plurality of via holes, and the plurality of via holes at least include: the thirty-first via hole V31, the thirty-second via hole V32 and the thirty-third via hole V33, such as Figure 12.
  • the thirty-first via hole V31 is located in the region where the third connection electrode 43 is located, and the fifth insulating layer in the thirty-first via hole V31 is removed to expose the surface of the third connection electrode 43.
  • Thirty-one via holes V31 are configured so that the data signal lines formed later are connected to the third connection electrodes 43 through the via holes.
  • the thirty-second via hole V32 is located in the region where the eighth connection electrode 48 is located, and the fifth insulating layer in the thirty-second via hole V32 is removed to expose the surface of the eighth connection electrode 48.
  • the thirty-two via holes V32 are configured so that the anode connection electrode formed subsequently is connected to the eighth connection electrode 48 through the via holes.
  • the thirty-third via hole V33 is located in the region where the interlayer connection electrode 49 is located, and the fifth insulating layer in the thirty-third via hole V33 is removed to expose the surface of the interlayer connection electrode 49.
  • Thirty-three via holes V33 are configured so that the second electrode lines formed later are connected to the interlayer connection electrodes 49 through the via holes.
  • a fourth conductive layer pattern is formed.
  • forming the fourth conductive layer may include: depositing a fourth metal thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth metal thin film by a patterning process, and forming a fourth metal thin film disposed on the fifth insulating layer
  • the fourth conductive layer includes at least: anode connection electrode 51 , second power supply line 73 and data signal line 74 , as shown in FIG. 13 .
  • the anode connection electrode 51 is disposed between the third scan signal line 23 and the initial signal line 31 , the anode connection electrode 51 is rectangular, and is connected to the eighth connection electrode 48 through the thirty-second via hole V32 , the anode connection electrode 51 is configured to be connected to the anode of the light-emitting device formed subsequently. Since the eighth connection electrode 48 simultaneously serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, the anode of the light emitting device is connected to the pixel driving circuit, so that the pixel driving circuit can drive the light emitting device to emit light.
  • the data signal line 74 extends along the second direction Y and is disposed between the first power supply line 71 and the reference signal line 72 , and the data signal line 74 is connected to the third through the thirty-first via V31 Electrode 43 is connected. Since the third connection electrode 43 serves as the first electrode of the first transistor T1, the connection between the data signal line 74 and the first electrode of the first transistor T1 is realized.
  • the orthographic projection of the data signal line 74 on the substrate and the orthographic projection of the first electrode 28 on the substrate have an overlapping area.
  • the second power line 73 extends along the second direction Y, corresponding to the position of the first power line 71 , and a plurality of second power connection lines 75 are provided on the second power line 73 , each of which is
  • the second power supply connection line 75 is disposed in each sub-pixel, one end of the second power supply connection line 75 is connected to the second power supply line 73 , and the other end extends along the opposite direction of the first direction X through the thirty-third via hole V33 It is connected to the interlayer connection electrode 49 .
  • the connection between the second power line 73 and the first electrode 28 is realized, and the second power line 73 can provide a constant low-level signal for the first electrode 28, so that the first The electrode 28 can effectively shield the influence of the data voltage jump on the key nodes, avoid the data voltage jump from affecting the potential of the key nodes of the pixel driving circuit, and improve the display effect.
  • the second power line 73 and the data signal line 74 may be provided with equal widths, or may be provided with unequal widths, may be straight lines, or may be folded lines.
  • the subsequent preparation process may include: forming a flat layer covering the pattern of the fourth conductive layer, forming an anode of the light emitting device on the flat layer, forming a pixel definition layer covering the anode, and setting the pixel definition layer of each sub-pixel There are pixel openings that expose the anode.
  • an organic light-emitting layer is formed by an evaporation process, and a cathode is formed on the organic light-emitting layer.
  • an encapsulation layer is formed.
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. , the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light-emitting device.
  • the substrate may be a flexible substrate, or it may be a rigid substrate.
  • the rigid substrate can be but not limited to one or more of glass and quartz
  • the flexible substrate can be but not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone , one or more of polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer and a second inorganic material layer that are stacked, the first flexible material layer and the second flexible material layer
  • the material can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, etc.
  • the material of the first inorganic material layer and the second inorganic material layer can be nitrogen Silicon oxide (SiNx) or silicon oxide (SiOx), etc., are used to improve the water and oxygen resistance of the substrate.
  • the thickness of the first flexible material layer may be about 5 ⁇ m to 15 ⁇ m, such as 10 ⁇ m; the thickness of the second flexible material layer may be about 5 ⁇ m to 15 ⁇ m, such as 10 ⁇ m; the thickness of the first inorganic material layer
  • the thickness of the second inorganic material layer may be about 0.3 ⁇ m to 0.9 ⁇ m, for example, 0.6 ⁇ m; the thickness of the second inorganic material layer may be about 0.3 ⁇ m to 0.9 ⁇ m, for example, 0.6 ⁇ m.
  • the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may adopt metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo). ), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo Wait.
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first conductive layer is called the first gate metal (Gate1) layer
  • the second conductive layer is called the second gate metal (Gate2) layer
  • the third conductive layer is called the first source-drain metal (SD1) layer
  • the fourth conductive layer Called the second source-drain metal (SD2) layer.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) One or more, it can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called the buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the interlayer insulation ( ILD) layer
  • the fifth insulating layer is called the passivation (PVX) layer.
  • the semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • six Materials such as thiophene or polythiophene, that is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology or organic technology.
  • the first insulating layer has a thickness of 3000 angstroms to 5000 angstroms
  • the second insulating layer has a thickness of 1000 angstroms to 2000 angstroms
  • the third insulating layer has a thickness of 4500 angstroms to 7000 angstroms
  • the fourth insulating layer has a thickness of 4500 angstroms to 7000 angstroms.
  • the thickness of the fifth insulating layer is 3000 angstroms to 5000 angstroms
  • the thickness of the fifth insulating layer is 3000 angstroms to 5000 angstroms.
  • High-resolution (PPI) displays with finer picture and display quality have become a design trend. Since the pixel area of high-resolution display is small, the arrangement of the pixel driving circuit in a limited space needs to consider various interference factors, especially the influence of the data signal line on the key nodes in the pixel driving circuit.
  • the data voltage Vdt provided by the data signal line is written into the second node N2 through the first transistor T1, and is coupled to the first node N1 through the threshold capacitor CVth, thereby controlling the third transistor T3 ( The potential of the gate electrode of the driving transistor) realizes display under different data voltages Vdt.
  • FIG. 6 in conjunction with FIG. 7 to FIG.
  • the data signal lines of the three sub-pixels in a sub-pixel row will be connected to the first node N1 (the first plate of the storage capacitor and the first node of the threshold capacitor) of the sub-pixel or the adjacent sub-pixels a plate) to form parasitic capacitance. Since the data voltage Vdt is written in time-division row by row, the data signal of each sub-pixel column is refreshed row by row.
  • the n-1-th sub-pixel column or the n+1-th sub-pixel column is The jump of the data voltage Vdt in the pixel column will affect the potential of the first node N1 of the pixel driving circuit in the nth sub-pixel column through parasitic effects, thereby affecting the driving current flowing through the third transistor T3.
  • a display substrate adopts a solution of increasing the distance between the data signal line and the first node N1, but this solution is not conducive to the layout and layout. Resolution improvement.
  • Exemplary embodiments of the present disclosure provide a first electrode, the first electrode is disposed in the first conductive layer, the orthographic projection of the first electrode on the substrate and the orthographic projection of the data signal line on the substrate have an overlapping area, and the first electrode Connecting to the second power line reduces the parasitic capacitance formed between the data signal line and the first node N1 of the sub-pixel or adjacent sub-pixels, effectively shielding the impact of the jump of the data voltage Vdt on the first node N1, avoiding The jump of the data voltage Vdt affects the potential of the first node N1 of the pixel driving circuit, thereby avoiding affecting the driving current flowing through the third transistor T3 and improving the display effect.
  • the first electrode plate of the storage capacitor, the first electrode plate of the threshold capacitor (the first node N1 ) and the first electrode are all disposed on the first conductive layer, and the data signal line is disposed on the fourth conductive layer. Since the second conductive layer is disposed between the first conductive layer and the fourth conductive layer, the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor in the second conductive layer can shield the first electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor. The electric field between the surface of a polar plate facing the fourth conductive layer and the data signal line.
  • the orthographic projection of the first electrode on the substrate and the orthographic projection of the data signal line on the substrate have an overlapping area, so the first electrode can shield the first plate of the storage capacitor and the first plate of the threshold capacitor.
  • the first electrode reduces the relationship between the data signal line and the sub-pixels.
  • the parasitic capacitance formed by the first node N1 of the sub-adjacent pixels effectively shields the influence of the jump of the data voltage Vdt on the first node N1, and improves the display effect.
  • a parasitic capacitance exists between the first electrode and the data signal line, since the first electrode is connected to the second power supply line, the parasitic capacitance basically has no effect on the performance of the pixel driving circuit.
  • the first electrode provided in the exemplary embodiment of the present disclosure shields the influence of the transition of the data voltage Vdt on the first node N1, the distance between the data signal line and the storage capacitor and the threshold capacitor can be effectively reduced, which is not only beneficial to the
  • the layout of the layout can be reduced, and the pixel area can be reduced, which is beneficial to improve the resolution of the display substrate.
  • Exemplary embodiments of the present disclosure show that the preparation process of the substrate can be well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • the first electrode may be disposed on the second conductive layer or the third conductive layer.
  • the first electrode can be disposed on the second conductive layer, and the second electrode plate of the storage capacitor and the second electrode plate of the threshold capacitor can be disposed in the same layer, and formed at the same time through the same patterning process. The same is true for the sexual examples.
  • the first electrode is arranged between the first plate of the threshold capacitor and the data signal line, the first electrode is arranged between the first plate of the threshold capacitor and the data signal line, The first electrode can not only shield the electric field between the surface of the first electrode plate of the threshold capacitor facing the fourth conductive layer and the data signal line, but also shield the surface and data of the first electrode plate of the threshold capacitor away from the fourth conductive layer. Electric field between signal lines.
  • the first electrode may be disposed on the third conductive layer, disposed in the same layer as the first power supply line and the reference signal line, and formed at the same time by the same patterning process, and the shape of the first electrode may be the same as that of the foregoing exemplary embodiment.
  • the second electrode segments are the same.
  • the first electrode is arranged between the first plate of the threshold capacitor and the data signal line, the first electrode is arranged between the first plate of the threshold capacitor and the data signal line, The first electrode can not only shield the electric field between the surface of the first electrode plate of the threshold capacitor facing the fourth conductive layer and the data signal line, but also shield the surface and data of the first electrode plate of the threshold capacitor away from the fourth conductive layer. Electric field between signal lines.
  • the structure of the connecting electrode in the corresponding conductive layer can be changed according to actual needs, which is not limited in the present disclosure.
  • the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display ( QDLED), etc., the present disclosure is not limited here.
  • a pixel driving circuit such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display ( QDLED), etc.
  • Exemplary embodiments of the present disclosure provide a method for manufacturing a display substrate, so as to manufacture the display substrates of the above-mentioned exemplary embodiments.
  • the display substrate includes a substrate, a second power supply line, a data signal line and a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit The circuits are respectively connected with the data signal lines, and the light-emitting devices are connected with the second power lines; the preparation method includes:
  • a semiconductor layer and a plurality of conductive layers disposed on the side of the semiconductor layer away from the substrate are formed on the substrate, at least one conductive layer is provided with a first electrode, and the first electrode is connected to the second power supply line , the orthographic projection of the first electrode on the substrate and the orthographic projection of the data signal line on the substrate have an overlapping area.
  • forming a semiconductor layer on the substrate and a plurality of conductive layers disposed on a side of the semiconductor layer away from the substrate may include:
  • a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer are sequentially formed on the semiconductor layer, and the first electrode is disposed on the first conductive layer, the second conductive layer or the third conductive layer layer, the second power line and the data signal line are arranged on the fourth conductive layer, and the second power line is connected to the first electrode through a via hole.
  • Exemplary embodiments of the present disclosure show a method for fabricating a substrate. The fabrication process has been described in detail in the foregoing exemplary embodiments, and will not be repeated here.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which is not limited in the embodiment of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示基板及其制备方法、显示装置。所述显示基板包括基底、第二电源线、数据信号线和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路分别与所述数据信号线连接，所述发光器件与所述第二电源线连接；所述基底上设置有半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有第一电极，所述第一电极与所述第二电源线连接，所述第一电极在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域。

Description

显示基板及其制备方法、显示装置
本申请要求于2020年9月28日提交的、申请号为202011041915.9、发明名称为“像素电路、像素驱动方法、显示面板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种显示基板，包括基底、第二电源线、数据信号线和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路分别与所述数据信号线连接，所述发光器件与所述第二电源线连接；所述基底上设置有半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有第一电极，所述第一电极与所述第二电源线连接，所述第一电极在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域。
在示例性实施方式中，所述第一电极包括沿第一方向延伸的第一电极段 和沿第二方向延伸的第二电极段，所述第二电极段在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域，所述第一电极段的一端与所述第二电极段连接，另一端与所述第二电源线连接；所述第二方向为所述数据信号线的延伸方向，所述第一方向与第二方向交叉。
在示例性实施方式中，所述多个导电层包括依次设置在所述半导体层远离所述基底一侧的第一导电层、第二导电层、第三导电层和第四导电层，所述数据信号线设置在所述第四导电层上，所述第一电极设置在所述第一导电层、第二导电层或第三导电层上。
在示例性实施方式中，所述第二电源线设置在所述第四导电层上，所述第二电源线通过过孔与所述第一电极连接。
在示例性实施方式中，所述第四导电层还包括第二电源连接线，所述第二电源连接线的一端与所述第二电源线连接，另一端通过过孔与所述第一电极连接。
在示例性实施方式中，所述第一电极设置在所述第一导电层或第二导电层上，所述第三导电层上还设置有层间连接电极，所述层间连接电极通过过孔与所述第一电极连接，所述第二电源线通过过孔与所述层间连接电极连接。
在示例性实施方式中，所述像素驱动电路至少包括第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体管；所述第一晶体管的第一极与所述数据信号线连接，所述第一晶体管的第二极与第二节点连接；所述第二晶体管的第一极与第一节点连接，所述第二晶体管的第二极与第三节点连接；所述第三晶体管的栅电极与第一节点连接，所述第三晶体管的第一极与第一电源线连接，所述第三晶体管的第二极与第三节点连接；所述第四晶体管的第一极与初始信号线连接；所述第五晶体管的第一极与参考信号线连接，所述第五晶体管的第二极与第二节点连接。
在示例性实施方式中，所述像素驱动电路还包括存储电容和阈值电容，所述存储电容包括存储电容第一极板和存储电容第二极板，所述阈值电容包括阈值电容第一极板和阈值电容第二极板；所述存储电容第二极板与所述第 一电源线连接，所述存储电容第一极板与所述第一节点连接；所述阈值电容第二极板与所述第二节点连接，所述阈值电容第一极板与所述第一节点连接。
在示例性实施方式中，所述存储电容第一极板和阈值电容第一极板设置在所述第一导电层上，所述存储电容第一极板和阈值电容第一极板为相互连接的一体结构，所述阈值电容第一极板与所述半导体层不交叠。
在示例性实施方式中，所述存储电容第二极板和阈值电容第二极板设置在所述第二导电层上，所述存储电容第二极板和阈值电容第二极板相互间隔设置，本子像素的存储电容第二极板与相邻子像素的存储电容第二极板为相互连接的一体结构，所述存储电容第二极板在所述基底上的正投影与所述存储电容第一极板在所述基底上的正投影存在重叠区域，所述阈值电容第二极板在所述基底上的正投影与所述阈值电容第一极板在所述基底上的正投影存在重叠区域。
在示例性实施方式中，所述第四晶体管为双栅晶体管，至少包括设置在所述半导体层上的第四有源层和两个第四栅电极；所述显示基板还包括第一子极板，所述第一子极板在基底上的正投影与位于两个第四栅电极之间的第四有源层在基底上的正投影存在重叠区域。
在示例性实施方式中，所述两个第四栅电极设置在所述第一导电层，所述第一子极板设置在所述第二导电层，所述第一子极板与所述初始信号线连接。
在示例性实施方式中，所述第五晶体管为双栅晶体管，至少包括设置在所述半导体层上的第五有源层和两个第五栅电极；所述显示基板还包括第二子极板，所述第二子极板在基底上的正投影与位于两个第五栅电极之间的第五有源层在基底上的正投影存在重叠区域。
在示例性实施方式中，所述两个第五栅电极设置在所述第一导电层，所述第二子极板设置在所述第二导电层，所述第二子极板通过过孔与所述第一电源线连接。
在示例性实施方式中，所述第一晶体管为双栅晶体管，至少包括设置在 所述半导体层上的第一有源层和两个第一栅电极；所述显示基板还包括第三子极板，所述第三子极板在基底上的正投影与位于两个第一栅电极之间的第一有源层在基底上的正投影存在重叠区域。
在示例性实施方式中，所述两个第一栅电极设置在所述第一导电层，所述第三子极板设置在所述第二导电层，所述第三子极板通过过孔与所述第一电源线连接。
在示例性实施方式中，所述第二晶体管为双栅晶体管，至少包括设置在所述半导体层上的第二有源层和两个第二栅电极；所述显示基板还包括第四子极板，所述第四子极板在基底上的正投影与位于两个第二栅电极之间的第二有源层在基底上的正投影存在重叠区域。
在示例性实施方式中，所述两个第二栅电极设置在所述第一导电层，所述第三子极板设置在所述第二导电层，所述第四子极板通过过孔与所述第一电源线连接。
本公开还提供了一种显示装置，包括前述的显示基板。
本公开还提供了一种显示基板的制备方法，所述显示基板包括基底、第二电源线、数据信号线和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路分别与所述数据信号线连接，所述发光器件与所述第二电源线连接；所述制备方法包括：
在所述基底上形成半导体层和设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有第一电极，所述第一电极与所述第二电源线连接，所述第一电极在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域。
在示例性实施方式中，在所述基底上形成半导体层和设置在所述半导体层远离所述基底一侧的多个导电层，包括：
在所述基底上形成半导体层；
在所述半导体层上依次形成第一导电层、第二导电层、第三导电层和第四导电层，所述第一电极设置在所述第一导电层、第二导电层或第三导电层 上，所述第二电源线和数据信号线设置在所述第四导电层上，所述第二电源线通过过孔与所述第一电极连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为一种像素驱动电路的等效电路示意图；
图5为一种像素驱动电路的工作时序图；
图6为本公开示例性实施例一种显示基板的结构示意图；
图7为本公开示例性实施例一种形成半导体层图案后的示意图；
图8为本公开示例性实施例一种形成第一导电层图案后的示意图；
图9为本公开示例性实施例一种形成第二导电层图案后的示意图；
图10为本公开示例性实施例一种形成第四绝缘层图案后的示意图；
图11为本公开示例性实施例一种形成第三导电层图案后的示意图；
图12为本公开示例性实施例一种形成第五绝缘层图案后的示意图；
图13为本公开示例性实施例一种形成第四导电层图案后的示意图。
附图标记说明:
11—第一有源层；       12—第二有源层；       13—第三有源层；
14—第四有源层；       15—第五有源层；       16—第六有源层；
17—第七有源层；       18—第八有源层；       21—第一扫描信号线；
22—第二扫描信号线；   23—第三扫描信号线；   24—第一发光控制线；
25—第二发光控制线；   26—存储电容第一极板； 27—阈值电容第一极板；
28—第一电极；         31—初始信号线；       32—第一连接线；
33—存储电容第二极板； 34—阈值电容第二极板； 35—第一子极板；
36—第二子极板；       37—第三子极板；       38—第四子极板；
41—第一连接电极；     42—第二连接电极；     43—第三连接电极；
44—第四连接电极；     45—第五连接电极；     46—第六连接电极；
47—第七连接电极；     48—第八连接电极；     49—层间连接电极；
51—阳极连接电极；     71—第一电源线；       72—参考信号线；
73—第二电源线；       74—数据信号线；       75—第二电源连接线；
101—基底；            102—驱动电路层；      103—发光器件；
104—封装层；          301—阳极；            302—像素定义层；
303—有机发光层；      304—阴极；            401—第一封装层；
402—第二封装层；      403—第三封装层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的 混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下 的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据信号线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号 线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个中包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色(W)子像素，本公开在此不做限定。在示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了OLED显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板了可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光器件103以及设置在发光器件103远离基底101一侧的封装层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中以每个子像素中包括一个驱动晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每个子像素的驱动电路层102可以包括：设置在基底上的第一绝缘层；设置在第一绝缘层上的有源层；覆盖有源层的第二绝缘层；设置在第二绝缘层上的栅电极和第一极板；覆盖栅电极和第一极板的第三绝缘层；设置在第三绝缘层上的第二极板；覆盖第二极板的第四绝缘层，第二绝缘层、第三绝缘层和第四绝缘层上开设有过孔，过孔暴露出有源层；设置在第四绝缘层上的源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接；覆盖前述结构的平坦层，平坦层上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极组成驱动晶体管210，第一极板和第二极板组成存储电容211。
在示例性实施方式中，发光器件103可以包括阳极301、像素定义层302、有机发光层303和阴极304。阳极301设置在平坦层上，通过平坦层上开设的过孔与驱动晶体管210的漏电极连接；像素定义层302设置在阳极301和平坦层上，像素定义层302上设置有像素开口，像素开口暴露出阳极301；有机发光层303至少部分设置在像素开口内，有机发光层303与阳极301连接；阴极304设置在有机发光层303上，阴极304与有机发光层303连接；有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。
在示例性实施方式中，封装层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光器件103。
在示例性实施方式中，有机发光层303可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层和电子 注入层可以是连接在一起的共通层，所有子像素的空穴传输层和电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层和电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T2C结构。图4为一种像素驱动电路的等效电路示意图，示意了一种8T2C结构。如图4所示，像素驱动电路可以包括8个晶体管(第一晶体管T1到第八晶体管T8)、2个电容(存储电容Cst和阈值电容CVth)，像素驱动电路分别与10个信号线连接，10个信号线包括第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第一发光信号线EM1、第二发光信号线EM2、参考信号线REF、初始信号线INIT、数据信号线DATA、第一电源线VDD和第二电源线VSS。
在示例性实施方式中，第一晶体管T1的栅电极与第一扫描信号线S1连接，第一晶体管T1的第一极与数据信号线DATA连接，第一晶体管的第二极与第二节点N2连接。第二晶体管T2的栅电极与第二扫描信号线S2连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第一电源线VDD连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的栅电极与第三扫描信号线S3连接，第四晶体管T4的第一极与初始信号线INIT连接，第四晶体管T4的第二极与第八晶体管T8的第一极连接。第五晶体管T5的栅电极与第三扫描信号线S3连接，第五晶体管T5的第一极与参考信号线REF连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与第二扫描信号线S2连接，第六晶体管T6的第一极与初始信号线INIT连接，第六晶体管T6的第二极与发光器件的第一极连接。第七晶体管T7的栅电极与第一发光信号线EM1连接，第七晶体管T7的第一极与第三节点N3连接，第七晶体管T7的第二极与发光器件的第一极连接。第八晶体管T8的栅电极与第二发光信号线EM2连接，第八晶体管T8的第一极与第四晶体管T4的第二极连接，第八晶体管T8的第二极与第一节点N1连接。存储电容Cst的第一端与第一电源线VDD 连接，存储电容Cst的第二端与第一节点N1连接。阈值电容CVth的第一端与第二节点N2连接，阈值电容CVth的第二端与第一节点N1连接。
在示例性实施方式中，第一晶体管T1到第八晶体管T8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第八晶体管T8可以包括P型晶体管和N型晶体管。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
在示例性实施方式中，第二扫描信号线S2为本显示行像素驱动电路中的扫描信号线，第三扫描信号线S3为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第二扫描信号线S2为S(n)，第三扫描信号线S3为S(n-1)，本显示行的第三扫描信号线S3与上一显示行像素驱动电路中的第二扫描信号线S2可以为同一信号线，或者说，本显示行的第二扫描信号线S2与下一显示行像素驱动电路中的第三扫描信号线S3可以为同一信号线，以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一发光信号线EM1为本显示行像素驱动电路中的发光信号线，第二发光信号线EM2为下一显示行像素驱动电路中的发光信号线，即对于第n显示行，第一发光信号线EM1为EM(n)，第二发光信号线EM2为EM(n+1)，本显示行的第一发光信号线EM1与下一显示行像素驱动电路中的第一发光信号线EM1可以为同一信号线，以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第一发光信号线EM1、第二发光信号线EM2和初始信号线INIT可以沿水平方向延伸，数据信号线DATA、第一电源线VDD、第二电源线VSS和参考信号线REF可以沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)， 包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为一种像素驱动电路的工作时序图。下面通过图4示例的像素驱动电路的工作过程说明本公开示例性实施例，图4中的像素驱动电路包括8个晶体管(第一晶体管T1到第八晶体管T8)、2个电容(存储电容Cst和阈值电容CVth)和10个信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第一发光信号线EM1、第二发光信号线EM2、参考信号线REF、初始信号线INIT、数据信号线DATA、第一电源线VDD和第二电源线VSS)，8个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二发光信号线EM2和第三扫描信号线S3的信号为低电平信号，第一扫描信号线S1、第二扫描信号线S2和第一发光信号线EM1的信号为高电平信号。第三扫描信号线S3的信号为低电平信号，使第四晶体管T4和第五晶体管T5导通，参考信号线REF的参考信号提供至第二节点N2，第二节点N2复位到参考信号的参考电压Vref。第二发光信号线EM2的信号为低电平信号，使第八晶体管T8导通，由于第四晶体管T4和第八晶体管T8导通，初始信号线INIT的初始信号提供至第一节点N1，第一节点N1复位到初始信号的初始电压Vinit。此阶段中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为阈值获取阶段，第二扫描信号线S2和第三扫描信号线S3的信号为低电平信号，第一扫描信号线S1、第一发光信号线EM1和第二发光信号线EM2的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第二晶体管T2和第六晶体管T6导通。第二晶体管T2导通使第一节点N1和第三节点N3电位相同，第三晶体管T3形成“二极管连接”结构，第一电源线VDD向第一节点N1充电，第一节点N1充电至Vdd-|Vth|电位后截至，将带有第三晶体管T3阈值电压的信息存储在存储电容Cst中。Vdd为第一电源线VDD的电源电压，Vth为第三晶体管T3的阈值电压。第六晶体管T6导通使初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压。第三扫描信号线S3 的信号为低电平信号，第五晶体管T5继续导通，使第二节点N2保持参考信号的参考电压Vref。此阶段中，第一晶体管T1、第三晶体管T3、第七晶体管T7和第八晶体管T8断开，此阶段OLED不发光。
第三阶段A3、称为数据写入阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2、第三扫描信号线S3、第一发光信号线EM1和第二发光信号线EM2的信号为高电平信号。第一扫描信号线S1的信号为低电平信号使第一晶体管T1导通，数据信号线DATA输出数据电压提供至第二节点N2，第二节点N2写入数据电压Vdt。第一节点N1和第二节点N2的信号叠加后，第一节点N1的电位变为：
V N1＝Vdd-|Vth|+(Vdt-Vref)*Cvth/(Cvth+Cst)
第四阶段A4、称为发光阶段，第一发光信号线EM1的信号为低电平信号，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3和第二发光信号线EM2的信号为高电平信号。第一发光信号线EM1的信号为低电平信号，使第七晶体管T7导通。第一节点N1的电位使第三晶体管T3导通，第一电源线VDD输出的电源电压通过导通的第三晶体管T3和第七晶体管T7向OLED的第一极提供驱动电压，驱动OLED发光。此阶段中，第一节点N1和第二节点N2悬空，靠存储电容Cst保持原电位。在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定，因而根据第一节点N1的电位，流过第三晶体管T3的驱动电流为：
I＝β*[(Vdt-Vref)CVth/(Cvth+Cst)] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，β为常数，Vdt为数据信号线DATA输出的数据电压，Vref为参考信号线REF输出的参考电压。该驱动电流公式中无第三晶体管T3的阈值电压信息，因此该像素驱动电路对第三晶体管T3的阈值电压有自补偿作用。
在像素驱动电路工作过程中，在复位阶段，第一节点N1的电位为初始电压Vinit，第二节点N2的电位为参考电压Vref。在阈值获取阶段，第一节点N1的电位为Vdd-|Vth|，第二节点N2的电位为参考电压Vref。数据写入 阶段，第一节点N1的电位为V N1＝Vdd-|Vth|+(Vdt-Vref)*Cvth/(Cvth+Cst)，第二节点N2的电位为数据电压Vdt。在发光阶段，第一节点N1的电位为V N1，第二节点N2的电位为数据电压Vdt。本公开示例性实施例的像素驱动电路的特点是阈值获取阶段和数据写入阶段时间分开，可以通过时序控制，增加阈值电压Vth的获取时间，提高像素驱动电路阈值电压Vth的补偿能力。
图6为本公开示例性实施例一种显示基板的结构示意图，示意了三个子像素的平面结构。如图6所示，在平行于显示基板的平面内，至少一个子像素中设置有第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第一发光控制线24、第二发光控制线25、初始信号线31、第一电源线71、参考信号线72、第二电源线73、数据信号线74、像素驱动电路和发光器件，像素驱动电路可以包括存储电容、阈值电容和多个晶体管，每个晶体管可以包括有源层、栅电极、第一极和第二极，存储电容包括存储电容第一极板26和存储电容第二极板33，阈值电容包括阈值电容第一极板27和阈值电容第二极板34。在示例性实施方式中，像素驱动电路分别与第一电源线71和数据信号线74连接，第一电源线71向像素驱动电路提供高电平信号，数据信号线74向像素驱动电路提供数据信号，发光器件与第二电源线73连接，第二电源线73向发光器件提供低电平信号。在示例性实施方式中，显示基板还包括第一电极28，第一电极28与第二电源线73连接，且第一电极28在显示基板平面上的正投影与数据信号线74在显示基板平面上的正投影存在重叠区域。
在垂直于显示基板的平面内，显示基板可以包括在基底上依次设置的半导体层和多个导电层，至少一个导电层设置第一电极28。在示例性实施例中，多个导电层可以包括在半导体层上依次设置的第一导电层、第二导电层、第三导电层和第四导电层，数据信号线74可以设置在第四导电层上，第一电极28可以设置在第一导电层，或者可以设置在第二导电层上，或者可以设置在第三导电层上。
在示例性实施例中，半导体层可以包括多个晶体管的有源层，第一导电层可以包括第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第一发光控制线24、第二发光控制线25、存储电容第一极板26和阈值电容 第一极板27，第二导电层可以包括初始信号线31、存储电容第二极板33和阈值电容第二极板34，第三导电层可以包括第一电源线71和参考信号线72，第四导电层可以包括第二电源线73和数据信号线74。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第一发光控制线24和第二发光控制线25沿第一方向X延伸，存储电容第一极板26和阈值电容第一极板27为相互连接的一体结构。初始信号线31沿第一方向X延伸，存储电容第二极板33和阈值电容第二极板34间隔设置。第一电源线71、参考信号线72、第二电源线73和数据信号线74沿第二方向Y延伸。第一方向X可以是扫描信号线的延伸方向，第二方向Y可以是数据信号线的延伸方向。
在示例性实施例中，一子像素行中相邻子像素的存储电容第二极板33通过连接线相互连接，一子像素行中相互连接的存储电容第二极板33同时作为第一电源连接线，使得一子像素行中各个子像素具有相同的电源电压，提高了显示均一性。
在示例性实施例中，第二导电层可以包括第一连接线32，第一连接线32沿第一方向X延伸且与参考信号线72连接，使得一子像素行中各个子像素具有相同的参考电压，提高显示均一性。
在示例性实施例中，像素驱动电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5；第一晶体管T1的第一极与数据信号线74连接，第一晶体管T1的第二极与阈值电容第二极板34连接；第二晶体管T2的第一极与存储电容第一极板26和阈值电容第一极板27连接，第二晶体管T2的第二极与第三晶体管T3的第二极连接；第三晶体管T3的栅电极与存储电容第一极板26和阈值电容第一极板27连接，第三晶体管T3的第一极与第一电源线71连接；第四晶体管T4的第一极与初始信号线31连接，第四晶体管T4的第二极与存储电容第一极板26和阈值电容第一极板27连接；第五晶体管T5的第一极与参考信号线72连接，第五晶体管T5的第二极与阈值电容第二极板34连接。
在示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4和第五晶体管T5为双栅晶体管。第二导电层可以包括第一子极板35、第二子 极板36、第三子极板37和第四子极板38。第一子极板35配置为在第四晶体管T4的双栅中间节点引入寄生电容，第二子极板36配置为在第五晶体管T5的双栅中间节点引入寄生电容，第三子极板37配置为在第一晶体管T1的双栅中间节点引入寄生电容，第四子极板38配置为在第二晶体管T2的双栅中间节点引入寄生电容。
在示例性实施例中，第四晶体管T4至少包括第四有源层和两个第四栅电极，第一子极板35在基底上的正投影与位于两个第四栅电极之间的第四有源层在基底上的正投影存在重叠区域。两个第四栅电极设置在第一导电层，第一子极板35设置在第二导电层，第一子极板35与初始信号线31连接。
在示例性实施例中，第五晶体管T5至少包括第五有源层和两个第五栅电极，第二子极板36在基底上的正投影与位于两个第五栅电极之间的第五有源层在基底上的正投影存在重叠区域。两个第五栅电极设置在第一导电层，第二子极板36设置在第二导电层，第二子极板36通过过孔与第一电源线71连接。
在示例性实施例中，第一晶体管T1至少包括第一有源层和两个第一栅电极，第三子极板37在基底上的正投影与位于两个第一栅电极之间的第一有源层在基底上的正投影存在重叠区域。两个第一栅电极设置在第一导电层，第三子极板37设置在第二导电层，第三子极板37通过过孔与第一电源线71连接。
在示例性实施例中，第二晶体管T3至少包括第二有源层和两个第二栅电极，第四子极板38在基底上的正投影与位于两个第二栅电极之间的第二有源层在基底上的正投影存在重叠区域。两个第二栅电极设置在第一导电层，第三子极板38设置在第二导电层，第四子极板38通过过孔与第一电源线71连接。
在示例性实施例中，第三导电层可以包括第一连接电极41、第二连接电极42、第三连接电极、第四连接电极44、第五连接电极45、第六连接电极46、第七连接电极47、第八连接电极和层间连接电极49。第一连接电极41作为第二晶体管T2的第一极，第二连接电极42作为第八晶体管T8的第二极，第三连接电极作为第一晶体管T1的第一极，第四连接电极44同时作为 第一晶体管T1的第二极和第五晶体管T5的第二极，第五连接电极45同时作为第四晶体管T4的第一极和第六晶体管T6的第一极，第六连接电极46同时作为第四晶体管T4的第二极和第八晶体管T8的第一极，第七连接电极47同时作为第二晶体管T2的第二极、第三晶体管T3的第二极和第七晶体管T7的第一极，第八连接电极同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，层间连接电极49配置为连接第一电极28和第二电源线。
在示例性实施例中，第四导电层可以包括阳极连接电极51，阳极连接电极51配置连接第八连接电极和发光器件的阳极。
在示例性实施例中，第一电极28可以包括沿第一方向X延伸的第一电极段和沿第二方向Y延伸的第二电极段，第二电极段在基底上的正投影与数据信号线74在基底上的正投影存在重叠区域，第一电极段的一端与第二电极段连接，另一端通过过孔与第二电源线连接。
在示例性实施例中，第三导电层可以包括第二电源连接线75，第二电源连接线75的一端与第二电源线73连接，另一端通过过孔与层间连接电极49连接，层间连接电极49通过过孔与第一电极28连接。
在示例性实施方式中，显示基板可以包括第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层，第一绝缘层设置在基底与半导体层之间，第二绝缘层设置在半导体层和第一导电层之间，第三绝缘层设置在第一导电层与第二导电层之间，第四绝缘层设置在第二导电层与第三导电层之间，第五绝缘层设置在第三导电层与第四导电层之间。
本公开示例性实施例提供的显示基板，通过设置第一电极，第一电极在基底上的正投影与数据信号线在基底上的正投影存在重叠区域，且第一电极与第二电源线连接，有效屏蔽了数据电压跳变对关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种 或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以显示基板中一子像素行中3个子像素为例，显示基板的制备过程可以包括如下操作。
(1)形成半导体层图案。在示例性实施例中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图7所示。
在示例性实施例中，至少一个子像素的半导体层可以包括第一晶体管T1的第一有源层至第八晶体管T8的第八有源层，第一晶体管T1的第一有源层11、第三晶体管T3的第三有源层13和第五晶体管T5的第五有源层15为单独设置，第二晶体管T2的第二有源层12、第六晶体管T6的第六有源层16和第七晶体管T7的第七有源层17为相互连接的一体结构，第四晶体管T4的第四有源层14和第八晶体管T8的第八有源层18为相互连接的一体结构，本子像素的第四有源层14与上一子像素行中子像素的第六有源层16连接，本子像素的第六有源层16与下一子像素行中子像素的第四有源层14连接。
在示例性实施例中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。
在示例性实施例中，第一有源层11的形状呈“几”字形，“几”字形的两端 分别为第一有源层11的第一区11-1和第一有源层11的第二区11-2，第一有源层11的第一区11-1和第一有源层11的第二区11-2单独设置。
在示例性实施例中，第二有源层12的形状呈“躺倒的L”字形，“躺倒的L”字形的两端分别为第二有源层12的第一区12-1和第二有源层12的第二区12-2，第二有源层12的第一区12-1单独设置，第二有源层12的第二区12-2同时作为第七有源层17的第一区17-1，即第二有源层12的第二区12-2和第七有源层17的第一区17-1相互连接。
在示例性实施例中，第三有源层13的形状为沿第二方向Y延伸的波浪形线，波浪形线的两端分别为第三有源层13的第一区13-1和第三有源层13的第二区13-2，第三有源层13的第一区13-1靠近第一有源层11，第三有源层13的第二区13-2靠近第二有源层12。
在示例性实施例中，第四有源层14的形状为沿第二方向Y延伸的双折形线，双折形线的两端分别为第四有源层14的第一区14-1和第四有源层14的第二区14-2。第四有源层14的第一区14-1同时作为上一子像素行中子像素的第六有源层16的第一区16-1，即本子像素的第四有源层14的第一区14-1与上一子像素行中子像素的第六有源层16的第一区16-1相互连接。第四有源层14的第二区14-2同时作为第八有源层18的第一区18-1，即第四有源层14的第二区14-2和第八有源层18的第一区18-1相互连接。
在示例性实施例中，第五有源层15的形状呈“几”字形，“几”字形的两端分别为第五有源层15的第一区15-1和第五有源层15的第二区15-2，第五有源层15的第一区15-1和第五有源层15的第二区15-2单独设置。
在示例性实施例中，第六有源层16的形状呈“一”字形，“一”字形的两端分别为第六有源层16的第一区16-1和第六有源层16的第二区16-2。第六有源层16的第一区16-1同时作为下一子像素行中子像素的第四有源层14的第一区14-1，即本子像素的第六有源层16的第一区16-1与下一子像素行中子像素的第四有源层14的第一区14-1相互连接。第六有源层16的第二区16-2同时作为第七有源层17的第二区17-2，即第六有源层16的第二区16-2和第七有源层17的第二区17-2之间相互连接。
在示例性实施例中，第七有源层17的形状呈“1”字形，“1”字形的两端分别为第七有源层17的第一区17-1和第七有源层T7的第二区17-2，第七有源层17的第一区17-1同时作为第二有源层12的第二区12-2，第七有源层T7的第二区17-2同时作为第六有源层16的第二区16-2。
在示例性实施例中，第八有源层18的形状呈“1”字形，“1”字形的两端分别为第八有源层18的第一区18-1和第八有源层18的第二区18-2，第八有源层18的第一区18-1同时作为第四有源层14的第二区14-2，第八有源层18的第二区18-2单独设置。
(2)形成第一导电层图案。在示例性实施例中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第一发光控制线24、第二发光控制线25、存储电容第一极板26、阈值电容第一极板27和第一电极28，如图8所示。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第一发光控制线24和第二发光控制线25沿第一方向X延伸。存储电容第一极板26、阈值电容第一极板27和第一电极28设置在第一扫描信号线21和第二扫描信号线22之间，位于子像素第二方向Y的中部。存储电容第一极板26靠近第二扫描信号线22，阈值电容第一极板27靠近第一扫描信号线21。第一发光控制线24设置在第二扫描信号线22远离存储电容第一极板26的一侧，第三扫描信号线23和第二发光控制线25设置在第一扫描信号线21远离阈值电容第一极板27一侧，第二发光控制线25设置在第一扫描信号线21和第三扫描信号线23之间。
在示例性实施例中，第一电极28为折线形状，包括沿着第一方向X延伸的第一电极段28-1和沿着第二方向Y延伸的第二电极段28-2，第一电极段28-1与第二电极段28-2相互邻近的一端相互连接，第一电极段28-1配置为与后续形成的第二电源线连接，第二电极段28-2与后续形成的数据信号线重叠，配置为屏蔽数据信号线上数据电压跳变对关键节点的影响，避免数据 电压跳变影响像素驱动电路的关键节点的电位，提高显示效果。
在示例性实施例中，存储电容第一极板26的轮廓可以为矩形状，角部可以设置倒角。阈值电容第一极板27的轮廓可以为矩形状，矩形状靠近第一电极28的第二电极段28-2的角部设置凹糟，矩形状靠近第三有源层13的角部设置凹糟，角部可以设置倒角。
在示例性实施例中，存储电容第一极板26和阈值电容第一极板27通过连接线相互连接。在一种可能的示例性实施例中，存储电容第一极板26和阈值电容第一极板27为相互连接的一体结构。
在示例性实施例中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第一发光控制线24和第二发光控制线25可以为等宽度设置，也可以为非等宽度设置，宽度为第二方向Y的尺寸。
在示例性实施例中，第二扫描信号线22上可以设置多个第二栅极块，每个第二栅极块设置在每个子像素内，第二栅极块的一端与第二扫描信号线22连接，另一端沿着第二方向Y延伸，形成双栅的第二晶体管。第三扫描信号线23上可以设置多个第三栅极块，每个第三栅极块设置在每个子像素内，第三栅极块的一端与第三扫描信号线23连接，另一端沿着第二方向Y的反方向延伸，形成双栅的第四晶体管。
在示例性实施例中，第一扫描信号线21与第一有源层11相重叠的区域作为第一晶体管T1的栅电极(双栅结构)，第二扫描信号线22与第二有源层12相重叠的区域作为第二晶体管T2的栅电极(双栅结构)，存储电容第一极板26在基底上的正投影与第三有源层13在基底上的正投影存在重叠区域，存储电容第一极板26同时作为第三晶体管T3的栅电极，第三扫描信号线23与第四有源层14相重叠的区域作为第四晶体管T4的栅电极(双栅结构)，第三扫描信号线23与第五有源层15相重叠的区域作为第五晶体管T5的栅电极(双栅结构)，第二扫描信号线22与第六有源层16相重叠的区域作为第六晶体管T6的栅电极，第一发光控制线24与第七有源层17相重叠的区域作为第七晶体管T7的栅电极，第二发光控制线25与第八有源层18相重叠的区域作为第八晶体管T8的栅电极。
在示例性实施例中，第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均为开关型晶体管，第三晶体管T3为驱动型晶体管。
在示例性实施例中，阈值电容第一极板27在基底上的正投影与第三有源层13在基底上的正投影没有重叠区域。
在示例性实施例中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第八晶体管T8的沟道区，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第八有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施例中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二金属薄膜，采用图案化工艺对第二金属薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：初始信号线31、第一连接线32、存储电容第二极板33和阈值电容第二极板34，如图9所示。
在示例性实施例中，初始信号线31和第一连接线32沿第一方向X延伸，初始信号线31设置在第三扫描信号线23远离第二发光控制线25的一侧，第一连接线32设置在第二扫描信号线22和第一发光控制线24之间，第一连接线32配置为与后续形成的参考信号线连接，使得一子像素行中各个子像素具有相同的参考电压，提高显示均一性。初始信号线31和第一连接线32可以为等宽度设置，也可以为非等宽度设置。
在示例性实施例中，存储电容第二极板33和阈值电容第二极板34设置在第一扫描信号线21和第二扫描信号线22之间，存储电容第二极板33和阈值电容第二极板34间隔设置。
在示例性实施例中，存储电容第二极板33的轮廓可以为矩形状，矩形状的角部可以设置倒角，存储电容第二极板33在基底上的正投影与存储电容第一极板26在基底上的正投影存在重叠区域。存储电容第二极板33上设置有第一开口33-1，第一开口33-1可以为矩形，位于存储电容第二极板33的中 部，第一开口33-1使存储电容第二极板33形成环形结构。第一开口33-1暴露出覆盖存储电容第一极板26的第三绝缘层，且存储电容第一极板26在基底上的正投影包含第一开口33-1在基底上的正投影。在示例性实施例中，第一开口33-1配置为容置后续形成的第一过孔，第一过孔位于第一开口33-1内并暴露出存储电容第一极板26，使后续形成的第一连接电极通过第一过孔与存储电容第一极板26连接。
在示例性实施例中，阈值电容第二极板34的形状与阈值电容第一极板27的形状相近，为两个角部设置凹槽的矩形状，阈值电容第二极板34在基底上的正投影与阈值电容第一极板27在基底上的正投影存在重叠区域。阈值电容第二极板34上设置有第二开口34-1，第二开口34-1可以为矩形，位于阈值电容第二极板34的中部，第二开口34-1使阈值电容第二极板34形成环形结构。第二开口34-1暴露出覆盖阈值电容第一极板27的第三绝缘层，且阈值电容第一极板27在基底上的正投影包含第二开口34-1在基底上的正投影。在示例性实施例中，第二开口34-1配置为容置后续形成的第二过孔，第二过孔位于第二开口34-1内并暴露出阈值电容第一极板27，使后续形成的第二连接电极通过第二过孔与阈值电容第一极板27连接。
在示例性实施例中，存储电容第一极板26和存储电容第二极板33构成像素驱动电路的存储电容Cst，存储电容第一极板26作为存储电容Cst的第二端，同时作为第三晶体管T3的栅电极，存储电容第二极板33作为存储电容Cst的第一端，与后续形成的第一电源线VDD连接。
在示例性实施例中，阈值电容第一极板27和阈值电容第二极板34构成像素驱动电路的阈值电容CVth，阈值电容第一极板27作为阈值电容CVth的第一端，与后续形成的第一晶体管T1的第二极连接，阈值电容第二极板34作为阈值电容CVth的第二端，与存储电容Cst的第二端连接。
在示例性实施例中，一子像素行中相邻子像素的存储电容第二极板33通过连接线相互连接。由于存储电容第二极板33与后续形成的第一电源线连接，因而一子像素行中相互连接的存储电容第二极板33同时作为第一电源连接线，使得一子像素行中各个子像素具有相同的电源电压，提高了显示均一性。
在示例性实施例中，一子像素行中相邻子像素的的阈值电容第二极板34间隔设置，使得每个子像素阈值电容CVth仅反映本子像素驱动晶体管的阈值电压。
在示例性实施例中，每个子像素可以设置第一子极板35、第二子极板36、第三子极板37和第四子极板38。
第一子极板35可以为“L”字形，第一子极板35的一端与初始信号线31连接，另一端在基底上的正投影与位于两个第四晶体管T4的栅电极之间的第四有源层14在基底上的正投影存在重叠区域。第一子极板35配置为在第四晶体管T4的双栅中间节点引入寄生电容，稳定像素驱动电路中关键节点电位，进而改善显示基板的闪烁，以调节第四晶体管T4的关态漏电流。
第二子极板36可以为“1”字形，第二子极板36在基底上的正投影与位于两个第五晶体管T5的栅电极之间的第五有源层15在基底上的正投影存在重叠区域。第二子极板36配置为在第五晶体管T5的双栅中间节点引入寄生电容，以调节第五晶体管T5的关态漏电流，稳定像素驱动电路中关键节点电位，进而改善显示基板的闪烁。
第三子极板37可以为“一”字形，第三子极板37在基底上的正投影与位于两个第一晶体管T1的栅电极之间的第一有源层11在基底上的正投影存在重叠区域。第三子极板37配置为在第一晶体管T1的双栅中间节点引入寄生电容，以调节第一晶体管T1的关态漏电流，稳定像素驱动电路中关键节点电位，进而改善显示基板的闪烁。
第四子极板38可以为“一”字形，第四子极板38在基底上的正投影与位于两个第二晶体管T2的栅电极之间的第二有源层12在基底上的正投影存在重叠区域。第四子极板38配置为在第二晶体管T2的双栅中间节点引入寄生电容，以调节第二晶体管T2的关态漏电流，稳定像素驱动电路中关键节点电位，进而改善显示基板的闪烁。
(4)形成第四绝缘层图案。在示例性实施例中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层 上设置有多个过孔，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16、第十七过孔V17、第十八过孔V18、第十九过孔V19、第二十过孔V20和第二十一过孔V21，如图10所示。
在示例性实施例中，第一过孔V1位于存储电容第二极板33设置的第一开口33-1所在区域，第一过孔V1在基底上的正投影位于第一开口33-1在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出存储电容第一极板26的表面，第一过孔V1配置为使后续形成的第一连接电极通过该过孔与存储电容第一极板26连接。
在示例性实施例中，第二过孔V2位于阈值电容第二极板34设置的第二开口34-1所在区域，第二过孔V2内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出阈值电容第一极板27的表面，第二过孔V2配置为使后续形成的第二连接电极通过该过孔与阈值电容第一极板27连接。
在示例性实施例中，第三过孔V3位于第三子极板37所在区域，第三过孔V3内的第四绝缘层被刻蚀掉，暴露出第三子极板37的表面，第三过孔V3配置为使后续形成的第一电源线通过该过孔与第三子极板37连接，为第三子极板37提供恒定的电源电压。
在示例性实施例中，第四过孔V4位于第一有源层的第一区所在区域，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第四过孔V4配置为使后续形成的第三连接电极通过该过孔与第一有源层连接。
在示例性实施例中，第五过孔V5位于第一有源层的第二区所在区域，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第五过孔V5配置为使后续形成的第四连接电极通过该过孔与第一有源层连接。
在示例性实施例中，第六过孔V6位于第二子极板36所在区域，第六过 孔V6内的第四绝缘层被刻蚀掉，暴露出第二子极板36的表面，第六过孔V6配置为使后续形成的第一电源线通过该过孔与第二子极板36连接，为第二子极板36提供恒定的电源电压。
在示例性实施例中，第七过孔V7位于第五有源层的第一区所在区域，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第七过孔V7配置为使后续形成的参考信号线通过该过孔与第五有源层连接。
在示例性实施例中，第八过孔V8位于第五有源层的第二区所在区域，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第二区的表面，第八过孔V8配置为使后续形成的第四连接电极通过该过孔与第五有源层连接。
在示例性实施例中，第九过孔V9位于第四有源层的第一区(也是第六有源层的第一区)所在区域，第九过孔V9内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第九过孔V9配置为使后续形成的第五连接电极通过该过孔与第四有源层连接。
在示例性实施例中，第十过孔V10位于第四有源层的第二区(也是第八有源层的第一区)所在区域，第十过孔V10内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第十过孔V10配置为使后续形成的第六连接电极通过该过孔与第四有源层连接。
在示例性实施例中，第十一过孔V11位于第八有源层的第二区所在区域，第十一过孔V11内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第二区的表面，第十一过孔V11配置为使后续形成的第二连接电极通过该过孔与第八有源层连接。
在示例性实施例中，第十二过孔V12位于第三有源层的第一区所在区域，第十二过孔V12内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第一区的表面，第十二过孔V12配置为使后续形成的第一电源线通过该过孔与第三有源层连接。
在示例性实施例中，第十三过孔V13位于第三有源层的第二区所在区域， 第十三过孔V13内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区的表面，第十三过孔V13配置为使后续形成的第七连接电极通过该过孔与第三有源层连接。
在示例性实施例中，第十四过孔V14位于第二有源层的第一区所在区域，第十四过孔V14内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区的表面，第十四过孔V14配置为使后续形成的第一连接电极通过该过孔与第二有源层连接。
在示例性实施例中，第十五过孔V15位于第二有源层的第二区(也是第七有源层的第一区)所在区域，第十五过孔V15内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第十五过孔V15配置为使后续形成的第七连接电极通过该过孔与第二有源层连接。
在示例性实施例中，第十六过孔V16位于第四子极板38所在区域，第十六过孔V16内的第四绝缘层被刻蚀掉，暴露出第四子极板38的表面，第十六过孔V16配置为使后续形成的第一电源线通过该过孔与第四子极板38连接，为第四子极板38提供恒定的电源电压。
在示例性实施例中，第十七过孔V17位于第一连接线32所在区域，第十七过孔V17内的第四绝缘层被刻蚀掉，暴露出第一连接线32的表面，第十七过孔V17配置为使后续形成的参考信号线通过该过孔与第一连接线32连接。
在示例性实施例中，第十八过孔V18位于初始信号线31所在区域，第十八过孔V18内的第四绝缘层被刻蚀掉，暴露出初始信号线31的表面，第十八过孔V18配置为使后续形成的第五连接电极45通过该过孔与初始信号线31连接。
在示例性实施例中，第十九过孔V19位于存储电容第二极板33所在区域，第十九过孔V19内的第四绝缘层被刻蚀掉，暴露出存储电容第二极板33的表面，第十九过孔V19配置为使后续形成的第一电源线通过该过孔与存储电容第二极板33连接。在在示例性实施例中，第十九过孔V19可以是一个或多个，多个第十九过孔V19沿着第二方向Y依次排布，多个第十九过孔 V19可以提高第一电源线与存储电容第二极板33的连接可靠性。
在示例性实施例中，第二十过孔V20位于第一电极28的第二电极段28-2所在区域，第二十过孔V20内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一电极28的第二电极段28-2的表面，第二十过孔V20配置为使后续形成的层间连接电极通过该过孔与第一电极28的第二电极段28-2连接。
在示例性实施例中，第二十一过孔V21位于第六有源层的第二区(也是第七有源层的第二区)所在区域，第二十一过孔V21内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区的表面，第二十一过孔V21配置为使后续形成的第九连接电极通过该过孔与第二有源层连接。
(5)形成第三导电层图案。在示例性实施例中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三金属薄膜，采用图案化工艺对第三金属薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，第三导电层至少包括：第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45、第六连接电极46、第七连接电极47、第八连接电极48、层间连接电极49、第一电源线71和参考信号线72，如图11所示。
在示例性实施例中，第一电源线71和参考信号线72沿第二方向Y延伸，第一电源线71和参考信号线72可以为等宽度设置，也可以为非等宽度设置，可以为直线，或者可以为折线。
在示例性实施例中，第一电源线71通过第三过孔V3与第三子极板37连接，通过第六过孔V6与第二子极板36连接，通过第十二过孔V12与第三有源层的第一区连接，通过第十六过孔V16与第四子极板38连接，通过第十九过孔V19与存储电容第二极板33连接。
在示例性实施例中，参考信号线72通过第七过孔V7与第五有源层的第一区连接，通过第十七过孔V17与第一连接线32连接。
在示例性实施例中，第一连接电极41为沿第二方向Y延伸的条形，一端通过第一过孔V1与存储电容第一极板26连接，另一端通过第十四过孔 V14与第二有源层的第一区连接，使第二晶体管T2的第一极与存储电容第一极板26连接起来。由于存储电容第一极板26同时作为第三晶体管T3的栅电极，因而第一连接电极41作为第二晶体管T2的第一极，实现了第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容Cst的第二端具有相同的电位。
在示例性实施例中，第二连接电极42为沿第二方向Y延伸的条形，一端通过第二过孔V2与阈值电容第一极板27连接，另一端通过第十一过孔V11与第八有源层的第二区连接，使第八晶体管T8的第二极与阈值电容第一极板27连接起来。由于阈值电容第一极板27与存储电容第一极板26为相互连接的一体结构，因而第二连接电极42作为第八晶体管T8的第二极，实现了第二晶体管T2的第一极、第三晶体管T3的栅电极、第八晶体管T8的第二极、存储电容Cst的第二端和阈值电容CVth的第二端具有相同的电位(即第一节点N1)。
在示例性实施例中，第三连接电极43设置在第一电源线71和参考信号线72之间，通过第四过孔V4与第一有源层的第一区连接，第三连接电极43作为第一晶体管T1的第一极，第三连接电极43配置为与后续形成的数据信号线连接。
在示例性实施例中，第四连接电极44为沿第二方向Y延伸的条形，一端通过第五过孔V5与第一有源层的第二区连接，另一端通过第八过孔V8与第五有源层的第二区连接，第四连接电极44同时作为第一晶体管T1的第二极和第五晶体管T5的第二极，使第一晶体管T1的第二极和第五晶体管T5的第二极具有相同的电位(即第二节点N2)。
在示例性实施例中，第五连接电极45为沿第二方向Y延伸的条形，一端通过第九过孔V9与第四有源层的第一区(也是第六有源层的第一区)连接，另一端通过第十八过孔V18与初始信号线31连接，第五连接电极45同时作为第四晶体管T4的第一极和第六晶体管T6的第一极，实现第四晶体管T4的第一极和第六晶体管T6同时与初始信号线31连接。
在示例性实施例中，第六连接电极46为矩形状，通过第十过孔V10与第四有源层的第二区(也是第八有源层的第一区)连接，第六连接电极46 同时作为第四晶体管T4的第二极和第八晶体管T8的第一极，实现第四晶体管T4的第二极和第八晶体管T8的第一极的连接。
在示例性实施例中，第七连接电极47为沿第二方向Y延伸的条形，一端通过第十三过孔V13与第三有源层的第二区连接，另一端通过第十五过孔V15与第二有源层的第二区(也是第七有源层的第一区)连接，第七连接电极47同时作为第二晶体管T2的第二极、第三晶体管T3的第二极和第七晶体管T7的第一极，使第二晶体管T2的第二极、第三晶体管T3的第二极和第七晶体管T7的第一极具有相同的电位(即第三节点N3)。
在示例性实施例中，第八连接电极48为矩形状，通过第二十一过孔V21与第六有源层的第二区(也是第七有源层的第二区)连接，第八连接电极48同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，实现第六晶体管T6的第二极和第七晶体管T7的第二极的连接。
在示例性实施例中，层间连接电极49设置在参考信号线72和第二连接电极42之间，层间连接电极49通过第二十过孔V20与第一电极28连接，层间连接电极49配置为与后续形成的第二电源线连接。
(6)形成第五绝缘层图案。在示例性实施例中，形成第五绝缘层图案可以包括：在形成前述图案的基底上，涂覆第五绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第五绝缘层，第五绝缘层上设置有多个过孔，多个过孔至少包括：第三十一过孔V31、第三十二过孔V32和第三十三过孔V33，如图12所示。
在示例性实施例中，第三十一过孔V31位于第三连接电极43所在区域，第三十一过孔V31内的第五绝缘层被去掉，暴露出第三连接电极43的表面，第三十一过孔V31配置为使后续形成的数据信号线通过该过孔与第三连接电极43连接。
在示例性实施例中，第三十二过孔V32位于第八连接电极48所在区域，第三十二过孔V32内的第五绝缘层被去掉，暴露出第八连接电极48的表面，第三十二过孔V32配置为使后续形成的阳极连接电极通过该过孔与第八连接电极48连接。
在示例性实施例中，第三十三过孔V33位于层间连接电极49所在区域，第三十三过孔V33内的第五绝缘层被去掉，暴露出层间连接电极49的表面，第三十三过孔V33配置为使后续形成的第二电极线通过该过孔与层间连接电极49连接。
(7)形成第四导电层图案。在示例性实施例中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四金属薄膜，采用图案化工艺对第四金属薄膜进行图案化，形成设置在第五绝缘层上的第四导电层，第四导电层至少包括：阳极连接电极51、第二电源线73和数据信号线74，如图13所示。
在示例性实施例中，阳极连接电极51设置在第三扫描信号线23和初始信号线31之间，阳极连接电极51为矩形状，通过第三十二过孔V32与第八连接电极48连接，阳极连接电极51配置与后续形成的发光器件的阳极连接。由于第八连接电极48同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，因而实现了发光器件的阳极与像素驱动电路的连接，使得像素驱动电路可以驱动发光器件发光。
在示例性实施例中，数据信号线74沿着第二方向Y延伸，设置在第一电源线71与参考信号线72之间，数据信号线74通过第三十一过孔V31与第三连接电极43连接。由于第三连接电极43作为第一晶体管T1的第一极，因而实现了数据信号线74与第一晶体管T1的第一极的连接。数据信号线74在基底上的正投影与第一电极28在基底上的正投影存在重叠区域。
在示例性实施例中，第二电源线73沿着第二方向Y延伸，与第一电源线71的位置相对应，第二电源线73上设置有多个第二电源连接线75，每个第二电源连接线75设置在每个子像素内，第二电源连接线75的一端与第二电源线73连接，另一端沿着第一方向X的反方向延伸，通过第三十三过孔V33与层间连接电极49连接。由于层间连接电极49与第一电极28，因而实现了第二电源线73与第一电极28的连接，第二电源线73可以为第一电极28提供恒定的低电平信号，使第一电极28可以有效屏蔽数据电压跳变对关键节点的影响，避免了数据电压跳变影响像素驱动电路的关键节点的电位，提高了显示效果。
在示例性实施例中，第二电源线73和数据信号线74可以为等宽度设置， 或者可以为非等宽度设置，可以为直线，或者可以为折线。
在示例性实施例中，后续制备流程可以包括：形成覆盖第四导电层图案的平坦层，在平坦层上形成发光器件的阳极，形成覆盖阳极的像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。随后，采用蒸镀工艺形成有机发光层，在有机发光层上形成阴极。随后，形成封装层，封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光器件。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力。在示例性实施方式中，第一柔性材料层的厚度可以约为5μm至15μm，例如为10μm；第二柔性材料层的厚度可以约为5μm至15μm，例如为10μm；第一无机材料层的厚度可以约为0.3μm至0.9μm，例如为0.6μm；第二无机材料层的厚度可以约为0.3μm至0.9μm，例如为0.6μm。
在示例性实施例中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一导电层称为第一栅金属(Gate1)层，第二导电层称为第二栅金属(Gate2)层，第三导电层称为第一源漏金属(SD1)层，第四导电层称为第二源漏金属(SD2)层。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五 绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称为栅绝缘(GI)层，第四绝缘层称为层间绝缘(ILD)层，第五绝缘层称为钝化(PVX)层。半导体层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
在示例性实施例中，第一绝缘层的厚度为3000埃到5000埃，第二绝缘层的厚度为1000埃到2000埃，第三绝缘层的厚度为4500埃到7000埃，第四绝缘层的厚度为3000埃到5000埃，第五绝缘层的厚度为3000埃到5000埃。
高分辨率(PPI)显示具有更精细的画质和显示品质，已经成为设计趋势。由于高分辨率显示的像素面积较小，因而在有限空间范围内进行像素驱动电路的排布需要考虑各种干扰因素，特别是数据信号线对像素驱动电路中关键节点的影响。如图4所示的像素驱动电路中，数据信号线提供的数据电压Vdt通过第一晶体管T1写入第二节点N2，并通过阈值电容CVth耦合至第一节点N1，进而控制第三晶体管T3(驱动晶体管)的栅电极的电位，实现不同数据电压Vdt下的显示。如图6并结合图7至图13所示，一子像素行中三个子像素的数据信号线会与本子像素或者相子邻像素的第一节点N1(存储电容第一极板和阈值电容第一极板)形成寄生电容。由于数据电压Vdt是分时逐行写入，每一子像素列的数据信号逐行刷新，对于第n子像素列的像素驱动电路来说，第n-1子像素列或第n+1子像素列中数据电压Vdt的跳变会通过寄生效应影响到第n子像素列中像素驱动电路的第一节点N1的电位，进而影响流过第三晶体管T3的驱动电流。为了减少数据电压跳变对第一节点N1电位的影响，一种显示基板采用增加数据信号线与第一节点N1之间距离的解决方案，但该方案既不利于版图的排布，也不利于分辨率的提高。
本公开示例性实施例通过设置第一电极，第一电极设置在第一导电层中， 第一电极在基底上的正投影与数据信号线在基底上的正投影存在重叠区域，且第一电极与第二电源线连接，降低了数据信号线与本子像素或者相子邻像素的第一节点N1所形成的寄生电容，有效屏蔽了数据电压Vdt的跳变对第一节点N1的影响，避免了数据电压Vdt跳变影响像素驱动电路的第一节点N1的电位，进而避免了影响流过第三晶体管T3的驱动电流，提高了显示效果。
在示例性实施例中，存储电容第一极板和阈值电容第一极板(第一节点N1)以及第一电极均设置在第一导电层，数据信号线设置在第四导电层。由于第一导电层与第四导电层之间设置有第二导电层，第二导电层中的存储电容第二极板和阈值电容第二极板可以屏蔽存储电容第一极板和阈值电容第一极板朝向第四导电层一侧的表面与数据信号线之间的电场。由于第一导电层设置有第一电极，第一电极在基底上的正投影与数据信号线在基底上的正投影存在重叠区域，因此第一电极可以屏蔽存储电容第一极板和阈值电容第一极板背离第四导电层一侧的表面与数据信号线之间的电场。
通过以上描述的显示基板的结构以及制备过程可以看出，本公开示例性实施例所提供的显示基板，通过在第一导电层上设置第一电极，第一电极降低了数据信号线与本子像素或者相子邻像素的第一节点N1所形成的寄生电容，有效屏蔽了数据电压Vdt的跳变对第一节点N1的影响，提高了显示效果。虽然第一电极与数据信号线之间会存在寄生电容，但由于第一电极与第二电源线连接，因而该寄生电容对像素驱动电路性能基本上无影响。由于本公开示例性实施例设置的第一电极屏蔽了数据电压Vdt的跳变对第一节点N1的影响，因而可以有效减小数据信号线与存储电容和阈值电容之间的距离，不仅有利于版图的排布，而且可以减小像素面积，有利于提高显示基板的分辨率。本公开示例性实施例显示基板的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，第一电极可以设置在第二导电层或第三导电层。例如，第一电极可以设置在第二导电层，与存储电容第二极板和阈值电容第二极板同层设置，且 通过同一次图案化工艺同时形成，第一电极的形状可以与前述示例性实施例相同。由于存储电容第一极板和阈值电容第一极板设置在第一导电层，数据信号线设置在第四导电层，因而第一电极设置在阈值电容第一极板与数据信号线之间，第一电极不仅可以屏蔽阈值电容第一极板朝向第四导电层一侧的表面与数据信号线之间的电场，而且可以屏蔽阈值电容第一极板背离第四导电层一侧的表面与数据信号线之间的电场。又如，第一电极可以设置在第三导电层，与第一电源线和参考信号线同层设置，且通过同一次图案化工艺同时形成，第一电极的形状可以与前述示例性实施例的第二电极段相同。由于存储电容第一极板和阈值电容第一极板设置在第一导电层，数据信号线设置在第四导电层，因而第一电极设置在阈值电容第一极板与数据信号线之间，第一电极不仅可以屏蔽阈值电容第一极板朝向第四导电层一侧的表面与数据信号线之间的电场，而且可以屏蔽阈值电容第一极板背离第四导电层一侧的表面与数据信号线之间的电场。对于第一电极设置在第二导电层或第三导电层情形，相应导电层中连接电极的结构可以根据实际需要变更，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开示例性实施例提供一种显示基板的制备方法，以制作上述示例性实施例的显示基板。在示例性实施例中，所述显示基板包括基底、第二电源线、数据信号线和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路分别与所述数据信号线连接，所述发光器件与所述第二电源线连接；所述制备方法包括：
在所述基底上形成半导体层和设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有第一电极，所述第一电极与所述第二电源线连接，所述第一电极在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域。
在示例性实施例中，在所述基底上形成半导体层和设置在所述半导体层 远离所述基底一侧的多个导电层，可以包括：
在所述基底上形成半导体层；
在所述半导体层上依次形成第一导电层、第二导电层、第三导电层和第四导电层，所述第一电极设置在所述第一导电层、第二导电层或第三导电层上，所述第二电源线和数据信号线设置在所述第四导电层上，所述第二电源线通过过孔与所述第一电极连接。
本公开示例性实施例显示基板的制备方法，制备过程已在前述示例性实施例中详细说明，在此不再赘述。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (21)

  1. 一种显示基板，所述显示基板包括基底、第二电源线、数据信号线和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路分别与所述数据信号线连接，所述发光器件与所述第二电源线连接；所述基底上设置有半导体层以及设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有第一电极，所述第一电极与所述第二电源线连接，所述第一电极在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域。
  2. 根据权利要求1所述的显示基板，其中，所述第一电极包括沿第一方向延伸的第一电极段和沿第二方向延伸的第二电极段，所述第二电极段在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域，所述第一电极段的一端与所述第二电极段连接，另一端与所述第二电源线连接；所述第二方向为所述数据信号线的延伸方向，所述第一方向与第二方向交叉。
  3. 根据权利要求1所述的显示基板，其中，所述多个导电层包括依次设置在所述半导体层远离所述基底一侧的第一导电层、第二导电层、第三导电层和第四导电层，所述数据信号线设置在所述第四导电层上，所述第一电极设置在所述第一导电层、第二导电层或第三导电层上。
  4. 根据权利要求3所述的显示基板，其中，所述第二电源线设置在所述第四导电层上，所述第二电源线通过过孔与所述第一电极连接。
  5. 根据权利要求3所述的显示基板，其中，所述第四导电层还包括第二电源连接线，所述第二电源连接线的一端与所述第二电源线连接，另一端通过过孔与所述第一电极连接。
  6. 根据权利要求3所述的显示基板，其中，所述第一电极设置在所述第一导电层或第二导电层上，所述第三导电层上还设置有层间连接电极，所述层间连接电极通过过孔与所述第一电极连接，所述第二电源线通过过孔与所述层间连接电极连接。
  7. 根据权利要求1至6任一项所述的显示基板，其中，所述像素驱动电路至少包括第一晶体管、第二晶体管、第三晶体管、第四晶体管和第五晶体 管；所述第一晶体管的第一极与所述数据信号线连接，所述第一晶体管的第二极与第二节点连接；所述第二晶体管的第一极与第一节点连接，所述第二晶体管的第二极与第三节点连接；所述第三晶体管的栅电极与第一节点连接，所述第三晶体管的第一极与第一电源线连接，所述第三晶体管的第二极与第三节点连接；所述第四晶体管的第一极与初始信号线连接；所述第五晶体管的第一极与参考信号线连接，所述第五晶体管的第二极与第二节点连接。
  8. 根据权利要求7所述的显示基板，其中，所述像素驱动电路还包括存储电容和阈值电容，所述存储电容包括存储电容第一极板和存储电容第二极板，所述阈值电容包括阈值电容第一极板和阈值电容第二极板；所述存储电容第二极板与所述第一电源线连接，所述存储电容第一极板与所述第一节点连接；所述阈值电容第二极板与所述第二节点连接，所述阈值电容第一极板与所述第一节点连接。
  9. 根据权利要求8所述的显示基板，其中，所述存储电容第一极板和阈值电容第一极板设置在所述第一导电层上，所述存储电容第一极板和阈值电容第一极板为相互连接的一体结构，所述阈值电容第一极板与所述半导体层不交叠。
  10. 根据权利要求8所述的显示基板，其中，所述存储电容第二极板和阈值电容第二极板设置在所述第二导电层上，所述存储电容第二极板和阈值电容第二极板相互间隔设置，本子像素的存储电容第二极板与相邻子像素的存储电容第二极板为相互连接的一体结构，所述存储电容第二极板在所述基底上的正投影与所述存储电容第一极板在所述基底上的正投影存在重叠区域，所述阈值电容第二极板在所述基底上的正投影与所述阈值电容第一极板在所述基底上的正投影存在重叠区域。
  11. 根据权利要求7所述的显示基板，其中，所述第四晶体管为双栅晶体管，至少包括设置在所述半导体层上的第四有源层和两个第四栅电极；所述显示基板还包括第一子极板，所述第一子极板在基底上的正投影与位于两个第四栅电极之间的第四有源层在基底上的正投影存在重叠区域。
  12. 根据权利要求11所述的显示基板，其中，所述两个第四栅电极设 置在所述第一导电层，所述第一子极板设置在所述第二导电层，所述第一子极板与所述初始信号线连接。
  13. 根据权利要求7所述的显示基板，其中，所述第五晶体管为双栅晶体管，至少包括设置在所述半导体层上的第五有源层和两个第五栅电极；所述显示基板还包括第二子极板，所述第二子极板在基底上的正投影与位于两个第五栅电极之间的第五有源层在基底上的正投影存在重叠区域。
  14. 根据权利要求13所述的显示基板，其中，所述两个第五栅电极设置在所述第一导电层，所述第二子极板设置在所述第二导电层，所述第二子极板通过过孔与所述第一电源线连接。
  15. 根据权利要求7所述的显示基板，其中，所述第一晶体管为双栅晶体管，至少包括设置在所述半导体层上的第一有源层和两个第一栅电极；所述显示基板还包括第三子极板，所述第三子极板在基底上的正投影与位于两个第一栅电极之间的第一有源层在基底上的正投影存在重叠区域。
  16. 根据权利要求15所述的显示基板，其中，所述两个第一栅电极设置在所述第一导电层，所述第三子极板设置在所述第二导电层，所述第三子极板通过过孔与所述第一电源线连接。
  17. 根据权利要求7所述的显示基板，其中，所述第二晶体管为双栅晶体管，至少包括设置在所述半导体层上的第二有源层和两个第二栅电极；所述显示基板还包括第四子极板，所述第四子极板在基底上的正投影与位于两个第二栅电极之间的第二有源层在基底上的正投影存在重叠区域。
  18. 根据权利要求17所述的显示基板，其中，所述两个第二栅电极设置在所述第一导电层，所述第三子极板设置在所述第二导电层，所述第四子极板通过过孔与所述第一电源线连接。
  19. 一种显示装置，其中，包括如权利要求1～18任一项所述的显示基板。
  20. 一种显示基板的制备方法，所述显示基板包括基底、第二电源线、数据信号线和多个子像素，至少一个子像素包括像素驱动电路和连接所述像素驱动电路的发光器件，所述像素驱动电路分别与所述数据信号线连接，所 述发光器件与所述第二电源线连接；所述制备方法包括：
    在所述基底上形成半导体层和设置在所述半导体层远离所述基底一侧的多个导电层，至少一个导电层设置有第一电极，所述第一电极与所述第二电源线连接，所述第一电极在基底上的正投影与所述数据信号线在基底上的正投影存在重叠区域。
  21. 根据权利要求20所述的显示基板，其中，在所述基底上形成半导体层和设置在所述半导体层远离所述基底一侧的多个导电层，包括：
    在所述基底上形成半导体层；
    在所述半导体层上依次形成第一导电层、第二导电层、第三导电层和第四导电层，所述第一电极设置在所述第一导电层、第二导电层或第三导电层上，所述第二电源线和数据信号线设置在所述第四导电层上，所述第二电源线通过过孔与所述第一电极连接。
PCT/CN2021/097380 2020-09-28 2021-05-31 显示基板及其制备方法、显示装置 WO2022062465A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/763,198 US20220376024A1 (en) 2020-09-28 2021-05-31 Display Substrate and Manufacturing Method Therefor, and Display Apparatus
CN202180001397.4A CN114730544B (zh) 2020-09-28 2021-05-31 显示基板及其制备方法、显示装置
EP21870852.7A EP4152307A4 (en) 2020-09-28 2021-05-31 DISPLAY SUBSTRATE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011041915.9A CN112053661B (zh) 2020-09-28 2020-09-28 像素电路、像素驱动方法、显示面板和显示装置
CN202011041915.9 2020-09-28

Publications (1)

Publication Number Publication Date
WO2022062465A1 true WO2022062465A1 (zh) 2022-03-31

Family

ID=73606011

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/CN2021/097380 WO2022062465A1 (zh) 2020-09-28 2021-05-31 显示基板及其制备方法、显示装置
PCT/CN2021/112069 WO2022062747A1 (zh) 2020-09-28 2021-08-11 像素电路、像素驱动方法、显示面板和显示装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/112069 WO2022062747A1 (zh) 2020-09-28 2021-08-11 像素电路、像素驱动方法、显示面板和显示装置

Country Status (4)

Country Link
US (2) US20220376024A1 (zh)
EP (1) EP4152307A4 (zh)
CN (2) CN112053661B (zh)
WO (2) WO2022062465A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115004375A (zh) * 2022-04-25 2022-09-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112053661B (zh) * 2020-09-28 2023-04-11 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置
EP4113497A4 (en) * 2021-02-10 2023-08-16 BOE Technology Group Co., Ltd. NETWORK SUBSTRATE, AND ASSOCIATED DISPLAY PANEL AND DISPLAY APPARATUS
US11978396B2 (en) 2021-03-24 2024-05-07 Boe Technology Group Co., Ltd. Array substrate, display panel and display device thereof
CN113299230B (zh) * 2021-05-27 2023-01-10 昆山国显光电有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN113487996A (zh) * 2021-07-22 2021-10-08 上海闻泰信息技术有限公司 像素驱动电路、显示面板及显示设备
CN114514573B (zh) * 2021-07-30 2022-08-09 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN113838420B (zh) * 2021-08-05 2022-03-18 京东方科技集团股份有限公司 像素电路、显示装置和驱动方法
TWI773498B (zh) * 2021-08-25 2022-08-01 友達光電股份有限公司 像素電路
CN115346489A (zh) * 2021-09-09 2022-11-15 武汉天马微电子有限公司 显示装置及其控制方法
CN115942815A (zh) * 2021-09-30 2023-04-07 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN114005407A (zh) * 2021-11-02 2022-02-01 武汉天马微电子有限公司 显示面板和显示装置
CN114863881B (zh) * 2022-04-25 2023-05-23 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
WO2023231097A1 (zh) * 2022-05-31 2023-12-07 京东方科技集团股份有限公司 像素电路、显示面板、驱动方法和显示装置
CN115440167B (zh) * 2022-08-30 2023-11-07 惠科股份有限公司 像素电路、显示面板和显示装置
CN117079597A (zh) * 2023-08-31 2023-11-17 惠科股份有限公司 显示驱动电路、显示驱动方法及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190081228A (ko) * 2017-12-29 2019-07-09 엘지디스플레이 주식회사 표시 장치용 어레이 기판
CN110189708A (zh) * 2019-06-26 2019-08-30 云谷（固安）科技有限公司 像素驱动电路及显示装置
CN111128080A (zh) * 2020-03-30 2020-05-08 京东方科技集团股份有限公司 显示基板及显示装置
CN111653240A (zh) * 2020-06-30 2020-09-11 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
CN111696486A (zh) * 2020-07-14 2020-09-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示基板及显示装置
CN112053661A (zh) * 2020-09-28 2020-12-08 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100897172B1 (ko) * 2007-10-25 2009-05-14 삼성모바일디스플레이주식회사 화소 및 그를 이용한 유기전계발광표시장치
KR101125571B1 (ko) * 2010-02-05 2012-03-22 삼성모바일디스플레이주식회사 화소, 이를 이용한 표시 장치 및 그 구동 방법
KR101812176B1 (ko) * 2011-05-20 2017-12-27 삼성디스플레이 주식회사 유기 발광 표시 장치
KR20140022671A (ko) * 2012-08-14 2014-02-25 삼성디스플레이 주식회사 유기 발광 표시 장치
KR101980757B1 (ko) * 2012-12-13 2019-05-21 엘지디스플레이 주식회사 유기발광 표시장치
CN103077680B (zh) * 2013-01-10 2016-04-20 上海和辉光电有限公司 一种oled像素驱动电路
KR102033611B1 (ko) * 2013-02-25 2019-10-18 삼성디스플레이 주식회사 화소, 이를 포함하는 표시장치 및 그 구동 방법
EP3113226B1 (en) 2014-02-25 2019-05-08 LG Display Co., Ltd. Display backplane and method for manufacturing same
CN104064139B (zh) * 2014-06-05 2016-06-29 上海天马有机发光显示技术有限公司 一种有机发光二极管像素补偿电路、显示面板和显示装置
US11600234B2 (en) * 2015-10-15 2023-03-07 Ordos Yuansheng Optoelectronics Co., Ltd. Display substrate and driving method thereof
KR102547871B1 (ko) * 2016-12-01 2023-06-28 삼성디스플레이 주식회사 화소 및 이를 가지는 유기전계발광 표시장치
US10127859B2 (en) 2016-12-29 2018-11-13 Lg Display Co., Ltd. Electroluminescent display
KR20180088551A (ko) * 2017-01-26 2018-08-06 삼성디스플레이 주식회사 표시 장치
KR102326386B1 (ko) * 2017-05-11 2021-11-15 삼성디스플레이 주식회사 표시 장치
CN106952617B (zh) * 2017-05-18 2019-01-25 京东方科技集团股份有限公司 像素驱动电路及方法、显示装置
CN107274829B (zh) * 2017-07-10 2020-04-14 上海天马有机发光显示技术有限公司 一种有机电致发光显示面板及显示设备
CN207337880U (zh) * 2017-08-24 2018-05-08 京东方科技集团股份有限公司 一种像素补偿电路、显示面板及显示装置
CN107527894B (zh) 2017-08-31 2023-12-26 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN110010072A (zh) 2018-01-05 2019-07-12 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN108492770B (zh) * 2018-03-27 2021-01-22 京东方科技集团股份有限公司 一种像素补偿电路、其驱动方法及显示面板、显示装置
CN208173203U (zh) * 2018-05-29 2018-11-30 北京京东方技术开发有限公司 显示面板及显示装置
CN108470539B (zh) * 2018-06-13 2020-04-21 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板和显示装置
CN109036273A (zh) * 2018-08-30 2018-12-18 云谷（固安）科技有限公司 像素结构、像素电路和显示面板
KR20200028567A (ko) 2018-09-06 2020-03-17 삼성디스플레이 주식회사 표시 장치
CN110895915A (zh) 2018-09-13 2020-03-20 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109192141B (zh) 2018-10-30 2021-01-22 京东方科技集团股份有限公司 显示面板及其检测方法、显示装置
KR102530811B1 (ko) * 2018-10-31 2023-05-09 엘지디스플레이 주식회사 표시 장치
KR102617275B1 (ko) 2018-11-30 2023-12-27 삼성디스플레이 주식회사 디스플레이 장치
CN111511100B (zh) 2019-01-30 2021-09-24 京东方科技集团股份有限公司 柔性电路板及制作方法、电子装置模组及电子装置
CN111511109B (zh) 2019-01-30 2021-11-23 京东方科技集团股份有限公司 柔性电路板及制作方法、电子装置模组及电子装置
CN109584799A (zh) 2019-02-02 2019-04-05 京东方科技集团股份有限公司 一种像素驱动电路、像素电路、显示面板和显示装置
CN109686314B (zh) 2019-03-01 2021-01-29 京东方科技集团股份有限公司 像素电路、显示基板和显示装置
CN110322842B (zh) * 2019-05-21 2021-07-02 合肥维信诺科技有限公司 一种像素驱动电路及显示装置
CN110223636B (zh) 2019-06-17 2021-01-15 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示装置
CN110189706B (zh) * 2019-06-28 2021-06-29 上海天马有机发光显示技术有限公司 一种显示面板、及显示装置
CN110429116B (zh) 2019-07-24 2021-01-01 武汉华星光电半导体显示技术有限公司 一种阵列基板、显示面板及阵列基板的制造方法
KR102627150B1 (ko) * 2019-10-14 2024-01-22 삼성디스플레이 주식회사 유기 발광 표시 장치의 화소, 및 유기 발광 표시 장치
CN114203784A (zh) * 2019-11-07 2022-03-18 京东方科技集团股份有限公司 一种显示基板和显示装置
CN210516730U (zh) * 2019-11-07 2020-05-12 京东方科技集团股份有限公司 一种显示基板和显示装置
CN111341814A (zh) * 2020-03-11 2020-06-26 深圳市华星光电半导体显示技术有限公司 显示面板及显示面板的制作方法
KR20210148538A (ko) * 2020-05-29 2021-12-08 삼성디스플레이 주식회사 표시 장치
CN111627387B (zh) * 2020-06-24 2022-09-02 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN111564136B (zh) * 2020-07-16 2020-10-23 武汉华星光电半导体显示技术有限公司 像素电路及驱动方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190081228A (ko) * 2017-12-29 2019-07-09 엘지디스플레이 주식회사 표시 장치용 어레이 기판
CN110189708A (zh) * 2019-06-26 2019-08-30 云谷（固安）科技有限公司 像素驱动电路及显示装置
CN111128080A (zh) * 2020-03-30 2020-05-08 京东方科技集团股份有限公司 显示基板及显示装置
CN111653240A (zh) * 2020-06-30 2020-09-11 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及其驱动方法
CN111696486A (zh) * 2020-07-14 2020-09-22 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示基板及显示装置
CN112053661A (zh) * 2020-09-28 2020-12-08 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示面板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4152307A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115004375A (zh) * 2022-04-25 2022-09-02 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
US11997899B2 (en) 2024-05-28
EP4152307A1 (en) 2023-03-22
CN114730544A (zh) 2022-07-08
CN112053661B (zh) 2023-04-11
CN114730544B (zh) 2023-12-26
US20230052846A1 (en) 2023-02-16
US20220376024A1 (en) 2022-11-24
EP4152307A4 (en) 2023-10-25
WO2022062747A1 (zh) 2022-03-31
CN112053661A (zh) 2020-12-08

Similar Documents

Publication Publication Date Title
WO2022062465A1 (zh) 显示基板及其制备方法、显示装置
WO2023000125A1 (zh) 显示基板及其制备方法、显示装置
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2022227005A1 (zh) 显示基板及其制备方法、显示装置
WO2022241747A1 (zh) 显示基板及其制备方法、显示装置
WO2022160535A1 (zh) 显示基板及其制备方法、显示装置
WO2023016341A1 (zh) 显示基板及其制备方法、显示装置
WO2022198377A1 (zh) 显示基板及其制作方法、显示装置
WO2023178612A1 (zh) 显示基板及其制备方法、显示装置
WO2023279333A1 (zh) 显示基板及显示装置
WO2023206462A1 (zh) 显示基板及其制备方法、显示装置
WO2024031240A1 (zh) 显示基板及其制备方法、显示装置
WO2024031315A1 (zh) 显示基板及其制备方法、显示装置
WO2023221040A1 (zh) 显示基板及其制备方法、显示装置
WO2023039886A1 (zh) 显示基板及其制备方法、显示装置
WO2023184352A1 (zh) 显示基板及显示装置
WO2022226815A1 (zh) 显示基板及其制备方法、显示装置
WO2022109919A1 (zh) 显示基板及其制作方法、显示装置
WO2023051103A1 (zh) 显示基板及其制备方法、显示装置
WO2023159511A1 (zh) 显示基板及其制备方法、显示装置
WO2023230912A1 (zh) 显示基板及其制备方法、显示装置
WO2023115457A1 (zh) 显示基板及其驱动方法、显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2024065629A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21870852

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021870852

Country of ref document: EP

Effective date: 20221212

NENP Non-entry into the national phase

Ref country code: DE