WO2024065629A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2024065629A1
WO2024065629A1 PCT/CN2022/123125 CN2022123125W WO2024065629A1 WO 2024065629 A1 WO2024065629 A1 WO 2024065629A1 CN 2022123125 W CN2022123125 W CN 2022123125W WO 2024065629 A1 WO2024065629 A1 WO 2024065629A1
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Prior art keywords
transistor
electrode
signal line
layer
initial
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PCT/CN2022/123125
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English (en)
French (fr)
Inventor
黄耀
肖星亮
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/123125 priority Critical patent/WO2024065629A1/zh
Publication of WO2024065629A1 publication Critical patent/WO2024065629A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer including a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, the first direction and the second direction intersect, the circuit unit includes at least a pixel driving circuit, the pixel driving circuit includes a storage capacitor and a plurality of oxide transistors, the light-emitting structure layer includes a plurality of light-emitting devices, the first initial signal line is configured to provide an initial voltage signal to the pixel driving circuit, the low-voltage power supply line is configured to provide a low power supply voltage signal to the light-emitting device, the second initial signal line is connected to the first initial signal line, and the first
  • the first initial signal line includes a plurality of initial sub-lines spaced apart along the first direction, and in at least one circuit unit, the initial sub-lines adjacent to each other in the first direction are connected to each other via initial connection electrodes.
  • the driving circuit layer includes a plurality of conductive layers, the initial sub-line and the initial connection electrode are disposed in different conductive layers, and in at least one circuit unit, the initial connection electrode is connected to the initial sub-line through a via hole.
  • the second initial signal line is connected to the initial connection electrode.
  • the driving circuit layer includes a plurality of conductive layers, the initial connection electrode and the second initial signal line are arranged in different conductive layers, and in at least one circuit unit, the second initial signal line is connected to the initial connection electrode through a via hole.
  • the pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and in at least one circuit unit, the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the second electrode plate of the storage capacitor and the second electrode of the sixth transistor, the first electrode of the second transistor is connected to the first electrode plate of the storage capacitor, the second electrode of the second transistor is connected to the first electrode of the third transistor, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the second electrode of the third transistor, the first electrode of the fifth transistor is connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the first electrode of the sixth transistor is connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is connected to the light-emitting device.
  • the first transistor, the fourth transistor and the sixth transistor are arranged on one side of the storage capacitor in the second direction, and the second transistor and the fifth transistor are arranged on a side of the storage capacitor in the opposite direction of the second direction.
  • the fourth transistor is arranged on a side of the storage capacitor in the second direction
  • the sixth transistor is arranged on a side of the fourth transistor away from the storage capacitor
  • the first transistor is arranged on a side of the sixth transistor away from the storage capacitor
  • the second transistor is arranged on a side of the storage capacitor in the opposite direction of the second direction
  • the fifth transistor is arranged on a side of the second transistor away from the storage capacitor.
  • the first transistor includes at least a first active layer
  • the sixth transistor includes at least a sixth active layer
  • the second region of the first active layer and the first region of the sixth active layer are interconnected as an integral structure.
  • the second transistor includes at least a second active layer
  • the third transistor includes at least a third active layer
  • the fourth transistor includes at least a fourth active layer
  • the second active layer and the fourth active layer are shaped like strips extending along the first direction
  • the third active layer is shaped like a strip extending along the second direction
  • the first region of the third active layer and the second region of the second active layer are interconnected as an integrated structure
  • the second region of the third active layer and the second region of the fourth active layer are interconnected as an integrated structure.
  • the third transistor includes at least a bottom gate electrode and a top gate electrode, the bottom gate electrode is respectively connected to the second electrode of the fourth transistor and the first electrode of the sixth transistor, and the top gate electrode and the first electrode plate of the storage capacitor are an integrated structure.
  • the driving circuit layer also includes a first scan signal line, a second scan signal line, a third scan signal line, a first light-emitting control line, and a second light-emitting control line extending along the first direction, and in at least one circuit unit, the first scan signal line is connected to the top gate electrode of the first transistor, the second scan signal line is connected to the top gate electrode of the fourth transistor, the third scan signal line is connected to the top gate electrode of the second transistor, the first light-emitting control line is connected to the top gate electrode of the sixth transistor, and the second light-emitting control line is connected to the top gate electrode of the fifth transistor.
  • the second scan signal line is located on the side of the storage capacitor in the second direction
  • the first light-emitting control line is located on the side of the second scan signal line away from the storage capacitor
  • the first scan signal line is located on the side of the first light-emitting control line away from the storage capacitor
  • the third scan signal line is located on the side of the storage capacitor in the opposite direction of the second direction
  • the second light-emitting control line is located on the side of the third scan signal line away from the storage capacitor.
  • the first initial signal line is disposed on a side of the first scan signal line away from the storage capacitor.
  • the driving circuit layer includes at least a blocking conductive layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, which are arranged in sequence along a direction away from the substrate,
  • the blocking conductive layer includes at least a plurality of bottom gate electrodes of oxide transistors
  • the first conductive layer includes at least a first electrode plate of the storage capacitor and top gate electrodes of a plurality of oxide transistors
  • the second conductive layer includes at least a second electrode plate of the storage capacitor and the first initial signal line
  • the third conductive layer includes at least a first electrode and a second electrode of a plurality of oxide transistors
  • the fourth conductive layer includes at least the second initial signal line and a low-voltage power supply line.
  • the plurality of unit columns include at least a first unit column, a second unit column, and a third unit column
  • the pixel driving circuits of the plurality of circuit units in the first unit column are connected to a red light-emitting device that emits red light
  • the pixel driving circuits of the plurality of circuit units in the second unit column are connected to a green light-emitting device that emits green light
  • the pixel driving circuits of the plurality of circuit units in the third unit column are connected to a blue light-emitting device that emits blue light
  • the low-voltage power line is arranged in the first unit column and the second unit column
  • the second initial signal line is arranged in the third unit column.
  • the present disclosure further provides a display device, comprising the aforementioned display substrate.
  • the present disclosure further provides a method for preparing a display substrate, comprising:
  • a driving circuit layer is formed on a substrate, wherein the driving circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction intersects with the second direction, wherein the circuit unit includes at least a pixel driving circuit, wherein the pixel driving circuit includes a storage capacitor and a plurality of oxide transistors, wherein the first initial signal line is configured to provide an initial voltage signal to the pixel driving circuit, wherein the second initial signal line is connected to the first initial signal line, and wherein the first initial signal line and the second initial signal line form a mesh connection structure;
  • a light emitting structure layer is formed on the driving circuit layer, wherein the light emitting structure layer includes a plurality of light emitting devices, and the low voltage power line is configured to provide a low power voltage signal to the light emitting devices.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure
  • FIG6 is a schematic diagram of an embodiment of the present disclosure after forming a shielding conductive layer pattern
  • FIG. 7A and 7B are schematic diagrams of a semiconductor layer pattern formed according to an embodiment of the present disclosure.
  • FIGS. 8A and 8B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern
  • 9A and 9B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern
  • FIG10 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern
  • FIGS. 11A and 11B are schematic diagrams of an embodiment of the present disclosure after a third conductive layer pattern is formed;
  • FIG12 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern
  • FIGS. 13A and 13B are schematic diagrams of an embodiment of the present disclosure after a fourth conductive layer pattern is formed;
  • FIG14 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG15 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG16 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG17 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG18 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG19 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG20 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG21 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG22 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram of a planar structure of yet another display substrate according to an exemplary embodiment of the present disclosure.
  • 16 shielding electrode
  • 20 driving circuit layer
  • 21 first active layer
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, and may have chamfers, arc edges and deformations, etc.
  • "About" in this disclosure means that the limits are not strictly defined, and the values within the range of process and measurement errors are allowed.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • D1 to Dn data signal lines
  • S1 to Sm scan signal lines
  • E1 to Eo light emitting signal lines
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the light emitting signal line and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver.
  • the data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values and control signals received from the timing controller. For example, the data driver can sample grayscale values using a clock signal, and apply data voltages corresponding to grayscale values to data signal lines D1 to Dn in units of unit lines, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number.
  • the light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller.
  • the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each sub-pixel may include a circuit unit and a light-emitting device, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a light-emitting signal line, and a data signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels.
  • the display substrate may include a driving circuit layer 20 disposed on a substrate 10, a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate 10, and an encapsulation structure layer 40 disposed on a side of the light emitting structure layer 30 away from the substrate 10.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the driving circuit layer 20 may include a plurality of circuit units, each of which may include a pixel driving circuit, and a scanning signal line, a light emitting control line, a data signal line, and a first power supply line connected to the pixel driving circuit, etc.
  • the pixel driving circuit may include at least a plurality of transistors and a storage capacitor.
  • the driving circuit layer 20 may include a shielding conductive layer 20-1, a first insulating layer 91, a semiconductor layer 20-2, a second insulating layer 92, a first conductive layer 20-3, a third insulating layer 93, a second conductive layer 20-4, a fourth insulating layer 94, a third conductive layer 20-5, a fifth insulating layer 95, a first planar layer 96, a fourth conductive layer 20-6, and a second planar layer 97 sequentially arranged on the substrate.
  • the shielding conductive layer 20-1 may include at least a plurality of shielding lines
  • the semiconductor layer 20-2 may include at least an active layer of a plurality of transistors
  • the first conductive layer 20-3 may include at least a first electrode plate of a storage capacitor
  • the second conductive layer 20-4 may include at least a second electrode plate of a storage capacitor
  • the third conductive layer 20-5 may include at least a first electrode and a second electrode of a plurality of transistors
  • the fourth conductive layer 20-6 may include at least an anode connecting electrode.
  • the light emitting structure layer 30 may include a plurality of light emitting devices, each of which may include at least an anode, a pixel definition layer, an organic light emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the organic light emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 40 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light emitting structure layer 30.
  • the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent circuit units may have a small amount of overlap, or may be isolated from each other.
  • OLED display technology matures and its yield rate continues to increase, the cost of OLED display devices continues to decrease, allowing OLED display devices to be gradually applied to more fields, such as medium and large-sized electronic products.
  • LTPS low-temperature polysilicon
  • An exemplary embodiment of the present disclosure provides a display substrate, comprising a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, wherein the driving circuit layer comprises a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction intersects with the second direction, the circuit unit comprises at least a pixel driving circuit, wherein the pixel driving circuit comprises a storage capacitor and a plurality of oxide transistors, the light-emitting structure layer comprises a plurality of light-emitting devices, the first initial signal line is configured to provide an initial voltage signal to the pixel driving circuit, the low-voltage power supply line is configured to provide a low power supply voltage signal to the light-emitting device, the second initial signal line is connected to
  • the first initial signal line includes a plurality of initial sub-lines spaced apart along the first direction, and in at least one circuit unit, the initial sub-lines adjacent to each other in the first direction are connected to each other through initial connection electrodes.
  • the second initial signal line is connected to the initial connection electrode.
  • the plurality of unit columns include at least a first unit column, a second unit column, and a third unit column
  • the pixel driving circuits of the plurality of circuit units in the first unit column are connected to a red light-emitting device that emits red light
  • the pixel driving circuits of the plurality of circuit units in the second unit column are connected to a green light-emitting device that emits green light
  • the pixel driving circuits of the plurality of circuit units in the third unit column are connected to a blue light-emitting device that emits blue light
  • the low-voltage power line is arranged in the first unit column and the second unit column
  • the second initial signal line is arranged in the third unit column.
  • the display substrate of this embodiment is described below by means of some examples.
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit of an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit of the exemplary embodiment of the present disclosure may include 6 transistors (a first transistor T1 to a sixth transistor T6) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (a first scanning signal line S1, a second scanning signal line S2, a first light emitting signal line E1, a second light emitting signal line E2, an initial signal line INIT, a data signal line D, a first power line VDD, and a second power line VSS).
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is respectively connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode of the storage capacitor C
  • the second node N2 is respectively connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5
  • the third node N3 is respectively connected to the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6,
  • the fourth node N4 is respectively connected to the second electrode of the first transistor T1, the second electrode of the sixth transistor T6, and the second electrode of the storage capacitor C
  • the fourth node N4 is also connected to the first electrode of the light emitting device EL.
  • the first plate of the storage capacitor C is connected to the first node N1
  • the second plate of the storage capacitor C is connected to the fourth node N4, that is, the first end of the storage capacitor C is connected to the gate electrode of the third transistor T3, and the second end of the storage capacitor C is connected to the first electrode of the light emitting device EL.
  • a gate electrode of the first transistor T1 is connected to the first scan signal line S1
  • a first electrode of the first transistor T1 is connected to the initialization signal line INIT
  • a second electrode of the first transistor T1 is connected to the second plate of the storage capacitor C and the fourth node N4.
  • a gate electrode of the second transistor T2 is connected to the first scan signal line S1
  • a first electrode of the second transistor T2 is connected to the first node N1
  • a second electrode of the second transistor T2 is connected to the second node N2.
  • the second transistor T2 connects the gate electrode of the third transistor T3 to the first electrode of the third transistor T3.
  • the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first plate of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called a driving transistor, and the third transistor T3 determines the size of the driving current flowing between the first power line VDD and the light emitting device according to the potential difference between its gate electrode and the first electrode.
  • a gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the third node N3.
  • the fourth transistor T4 inputs a data voltage of the data signal line D to the third node N3.
  • a gate electrode of the fifth transistor T5 is connected to the second light emitting signal line E2, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.
  • a gate electrode of the sixth transistor T6 is connected to the first light emitting signal line E1, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the light emitting device to make the light emitting device emit light.
  • the light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).
  • the six transistors of the pixel driving circuit may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.
  • the six transistors of the pixel driving circuit may be oxide thin film transistors.
  • the active layer of the oxide thin film transistor may be oxide semiconductor (Oxide).
  • the oxide thin film transistor has the advantages of low leakage current, and the display substrate provided with the oxide thin film transistor can realize low-frequency driving, reduce power consumption, and improve display quality.
  • the second electrode of the light emitting device EL is connected to the second power line VSS
  • the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit
  • the second power line VSS can be configured to provide a constant second voltage signal to the pixel driving circuit
  • the first voltage signal is greater than the second voltage signal
  • the initial signal line INIT can be configured to provide an initial voltage signal to the pixel driving circuit.
  • the initial voltage signal can be a constant voltage signal, and its size can be between the first voltage signal provided by the first power line VDD and the second voltage signal provided by the second power line VSS, which is not limited in the present disclosure.
  • the operation process of the pixel driving circuit may include the following stages.
  • the first stage A1 is called the initialization stage.
  • the high-level signal provided by the first scanning signal line S1 turns on the first transistor T1 and the second transistor T2, and the high-level signal provided by the second light-emitting signal line E2 turns on the fifth transistor T5.
  • the first transistor T1 is turned on so that the initial voltage signal provided by the initial signal line INIT is provided to the fourth node N4 and the second electrode plate of the storage capacitor C, the storage capacitor C and the light-emitting device EL are initialized, the original data voltage in the storage capacitor C is cleared, the pre-stored voltage of the first electrode of the light-emitting device EL is cleared, the initialization is completed, and the light-emitting element EL does not emit light.
  • the second transistor T2 is turned on so that the first node N1 and the second node N2 are connected, and the fifth transistor T5 is turned on so that the first voltage signal output by the first power line VDD is charged into the first electrode plate of the storage capacitor C through the fifth transistor T5, the second node N2 and the first node N1. Since the first electrode plate of the storage capacitor C is at a high level, the third transistor T3 is turned on.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the second scanning signal line S2 provides a high level signal to turn on the fourth transistor T4.
  • the fourth transistor T4 is turned on so that the data voltage output by the data signal line D is provided to the first node N1 through the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the first plate of the storage capacitor C.
  • the third stage A3 is called the light-emitting stage.
  • the first light-emitting control line E1 and the second light-emitting signal line E2 provide a high-level signal to turn on the fifth transistor T5 and the sixth transistor T6, and the first voltage signal output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light.
  • the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3 , so the pixel driving circuit can better compensate for the threshold voltage of the third transistor T3 .
  • FIG5 is a schematic diagram of the planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuit in three circuit units in a unit row.
  • the display substrate in a direction perpendicular to the display substrate, may include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate.
  • the driving circuit layer may include circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include at least a pixel driving circuit, and at least one pixel driving circuit may include a storage capacitor and a plurality of oxide transistors.
  • the light-emitting structure layer includes a plurality of light-emitting devices, and at least one light-emitting device may include an anode, an organic light-emitting layer, and a cathode.
  • the driving circuit layer further includes a plurality of first initial signal lines 70 extending along a first direction X, a plurality of second initial signal lines 80 extending along a second direction Y, and a plurality of low-voltage power supply lines 90 extending along the second direction Y, and the first direction X intersects the second direction Y.
  • the first initial signal lines 70 are configured to provide an initial voltage signal to the pixel driving circuit
  • the low-voltage power supply lines 90 are configured to provide a low power supply voltage signal to the cathode of the light-emitting device
  • the second initial signal lines 80 are connected to the first initial signal lines 70, so that the first initial signal lines 70 extending along the first direction X and the second initial signal lines 80 extending along the second direction Y form a mesh connection structure.
  • the first initial signal line 70 may include a plurality of initial sub-lines 41 spaced apart along the first direction X. In at least one circuit unit, adjacent initial sub-lines 41 in the first direction X are connected to each other through initial connection electrodes 58 to form a first initial signal line 70 extending along the first direction X.
  • the second initial signal line 80 is connected to the initial connection electrode 58, and since the initial connection electrode 58 is connected to the initial sub-line 41, the connection between the second initial signal line 80 and the first initial signal line 70 is achieved.
  • the driving circuit layer may include multiple conductive layers, the initial sub-line 41, the initial connection electrode 58 and the second initial signal line 80 may be arranged in different conductive layers, and in at least one circuit unit, the initial connection electrode 58 is connected to the initial sub-line 41 through a via, and the second initial signal line 80 is connected to the initial connection electrode 58 through a via.
  • the storage capacitor of the pixel driving circuit may include a first electrode plate and a second electrode plate
  • the plurality of oxide transistors of the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.
  • the first electrode of the first transistor T1 is connected to the first initial signal line 70
  • the second electrode of the first transistor T1 is connected to the second electrode plate of the storage capacitor 50 and the second electrode of the sixth transistor T6.
  • the first electrode of the second transistor T2 is connected to the first electrode plate of the storage capacitor 50, the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3, the first electrode of the fourth transistor T4 is connected to the data signal line 63, the second electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the first electrode of the fifth transistor T5 is connected to the first power line 62, the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1.
  • the first transistor T1, the fourth transistor T4 and the sixth transistor T6 may be located on one side of the storage capacitor 50 in the second direction Y, and the second transistor T2 and the fifth transistor T5 may be located on the side of the storage capacitor 50 in the opposite direction of the second direction Y.
  • the fourth transistor T4 may be located on the side of the storage capacitor 50 in the second direction Y
  • the sixth transistor T6 may be located on the side of the fourth transistor T4 away from the storage capacitor 50
  • the first transistor T1 may be located on the side of the sixth transistor T6 away from the storage capacitor 50
  • the second transistor T2 may be located on the side of the storage capacitor 50 in the opposite direction of the second direction Y
  • the fifth transistor T5 may be located on the side of the second transistor T2 away from the storage capacitor 50.
  • the driving circuit layer may further include a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a first light-emitting control line 34, and a second light-emitting control line 35.
  • the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the first light-emitting control line 34, and the second light-emitting control line 35 may be straight lines or broken lines extending along the first direction X.
  • each of the first to sixth transistors T1 to T6 includes a top gate electrode and a bottom gate electrode.
  • the first scan signal line 31 may be connected to the top gate electrode of the first transistor T1, and the first scan signal line 31 is configured to control the on and off of the first transistor T1.
  • the second scan signal line 32 may be connected to the top gate electrode of the fourth transistor T4, and the second scan signal line 32 is configured to control the on and off of the fourth transistor T4.
  • the third scan signal line 33 may be connected to the top gate electrode of the second transistor T2, and the third scan signal line 33 is configured to control the on and off of the second transistor T2.
  • the first light emission control line 34 may be connected to the top gate electrode of the sixth transistor T6, and the first light emission control line 34 is configured to control the on and off of the sixth transistor T6.
  • the second light emission control line 35 may be connected to the top gate electrode of the fifth transistor T5. The second light emission control line 35 is configured to control the on and off of the fifth transistor T5.
  • the second scan signal line 32 may be located on one side of the storage capacitor 50 in the second direction Y
  • the first light emission control line 34 may be located on the side of the second scan signal line 32 away from the storage capacitor 50
  • the first scan signal line 31 may be located on the side of the first light emission control line 34 away from the storage capacitor 50
  • the third scan signal line 33 may be located on the side of the storage capacitor 50 in the opposite direction of the second direction Y
  • the second light emission control line 35 may be located on the side of the third scan signal line 33 away from the storage capacitor 50.
  • the first preliminary signal line 70 may be located on a side of the first scan signal line 31 away from the storage capacitor 50 .
  • the plurality of unit columns may include at least a first unit column, a second unit column, and a third unit column, the pixel driving circuits of the plurality of circuit units in the first unit column are connected to the red light emitting device emitting red light, the pixel driving circuits of the plurality of circuit units in the second unit column are connected to the green light emitting device emitting green light, the pixel driving circuits of the plurality of circuit units in the third unit column are connected to the blue light emitting device emitting blue light, the low voltage power line 90 may be disposed in the first unit column and the second unit column, and the second initial signal line 80 may be disposed in the third unit column.
  • the n-1th column and the nth column may be the first unit column and the second unit column, respectively, the n+1th column may be the third unit column, the low voltage power line 90 may be disposed in the circuit units of the n-1th column and the nth column, respectively, and the second initial signal line 80 may be disposed in the circuit unit of the n+1th column.
  • the driving circuit layer may include at least a blocking conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer and a fourth conductive layer, which are arranged in sequence along a direction away from the substrate.
  • the blocking conductive layer may include at least a bottom gate electrode of a plurality of oxide transistors
  • the semiconductor layer may include at least an active layer of a plurality of oxide transistors
  • the first conductive layer may include at least a first electrode plate of a storage capacitor 50 and top gate electrodes of a plurality of oxide transistors
  • the second conductive layer may include at least a second electrode plate of the storage capacitor 50 and a first initial signal line 70
  • the third conductive layer may include at least a first electrode and a second electrode of a plurality of oxide transistors
  • the fourth conductive layer may include at least a second initial signal line 80 and a low-voltage power supply line 90.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating, and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • a process of preparing a display substrate may include the following operations.
  • Forming a blocking conductive layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film by a patterning process, and forming a blocking conductive layer pattern on the substrate, as shown in FIG. 6 .
  • the shielding conductive layer pattern may include at least a first shielding line 11 , a second shielding line 12 , a third shielding line 13 , a fourth shielding line 14 , a fifth shielding line 15 , and a shielding electrode 16 .
  • the shapes of the first shielding line 11 , the second shielding line 12 , the third shielding line 13 , the fourth shielding line 14 and the fifth shielding line 15 may be straight lines extending along the first direction X or folded lines.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • “A extends along direction B” means "the main part of A extends along direction B".
  • the second direction Y may be a direction pointing from the display area to the binding area, and the opposite direction of the second direction Y may be a direction pointing from the binding area to the display area.
  • the first shielding line 11 may be located on one side of the shielding electrode 16 in the second direction Y.
  • the first shielding line 11 is configured to shield the first transistor T1 to reduce the influence of light on the electrical characteristics of the first transistor T1 and is configured as a bottom gate electrode of the first transistor T1.
  • the second shielding line 12 may be located on one side of the shielding electrode 16 in the second direction Y, and between the shielding electrode 16 and the first shielding line 11.
  • a fourth bottom gate electrode 12-1 is disposed on one side of the second shielding line 12 close to the shielding electrode 16, and the fourth bottom gate electrode 12-1 is configured to shield the fourth transistor T4, reduce the influence of light on the electrical characteristics of the fourth transistor T4, and is configured as the bottom gate electrode of the fourth transistor T4.
  • the third shielding line 13 may be located on a side opposite to the second direction Y of the shielding electrode 16, so that the shielding electrode 16 is located between the second shielding line 12 and the third shielding line 13.
  • a second bottom gate electrode 13-1 is disposed on a side of the third shielding line 13 close to the shielding electrode 16, and the second bottom gate electrode 13-1 is configured to shield the second transistor T2, reduce the influence of light on the electrical characteristics of the second transistor T2, and is configured as the bottom gate electrode of the second transistor T2.
  • the fourth shielding line 14 may be located between the first shielding line 11 and the second shielding line 12.
  • the fourth shielding line 14 is configured to shield the sixth transistor T6 to reduce the influence of light on the electrical characteristics of the sixth transistor T6, and is configured as a bottom gate electrode of the sixth transistor T6.
  • the fifth shielding line 15 may be located on a side of the third shielding line 13 away from the shielding electrode 16.
  • the fifth shielding line 15 is configured to shield the fifth transistor T5, reduce the influence of light on the electrical characteristics of the fifth transistor T5, and is configured as a bottom gate electrode of the fifth transistor T5.
  • the shielding electrode 16 may be in the shape of a strip extending along the second direction Y.
  • the shielding electrode 16 is configured to shield the third transistor T3 to reduce the influence of light on the electrical characteristics of the third transistor T3 and is configured as a bottom gate electrode of the third transistor T3.
  • a shielding connection block 16 - 1 is provided at an end of the shielding electrode 16 close to the first shielding line 11 , and the shielding connection block 16 - 1 is configured to be connected to a fifth connection electrode formed subsequently.
  • forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 7A and 7B , where FIG. 7B is a plan view schematic diagram of the semiconductor layer in FIG. 7A .
  • the semiconductor layer pattern may include a first active layer 21 of the first transistor T1 to a sixth active layer 26 of the sixth transistor T6, and the second active layer 22, the third active layer 23 and the fourth active layer 24 are an integral structure connected to each other, and the first active layer 21 and the sixth active layer 26 are an integral structure connected to each other.
  • the first active layer 21, the fourth active layer 24, and the sixth active layer 26 may be located on one side of the third active layer 23 in the second direction Y, and the second active layer 22 and the fifth active layer 25 may be located on a side of the third active layer 23 in the opposite direction of the second direction Y.
  • the first active layer 21 to the sixth active layer 26 may be in an "I" shape.
  • the second active layer 22 and the fourth active layer 24 may be in a strip shape extending along the first reverse direction X
  • the third active layer 23 may be in a strip shape extending along the second direction Y
  • the first end of the second active layer 22 is connected to one end of the third active layer 23
  • the second end of the second active layer 22 extends along the first direction X
  • the first end of the fourth active layer 24 is connected to the other end of the third active layer 23
  • the second end of the fourth active layer 24 extends along the first direction X, so that the second active layer 22, the third active layer 23 and the fourth active layer 24 of the integrated structure form a "C" shape.
  • the orthographic projection of the third active layer 23 on the substrate may be located within the range of the orthographic projection of the shielding electrode 16 on the substrate, so that the channel region of the third transistor T3 may be effectively shielded by the shielding electrode 16.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the second region 21-2 of the first active layer 21 and the second region 26-2 of the sixth active layer 26 are interconnected integral structures, that is, the second region 21-2 of the first active layer 21 can serve as the second region 26-2 of the sixth active layer 26.
  • the second region 22-2 of the second active layer 22 and the first region 23-1 of the third active layer 23 are interconnected integral structures, that is, the second region 22-2 of the second active layer 22 can serve as the first region 23-1 of the third active layer 23.
  • the second region 24-2 of the fourth active layer 24 and the second region 23-2 of the third active layer 23 are interconnected integral structures, that is, the second region 24-2 of the fourth active layer 24 can serve as the first region 23-1 of the third active layer 23.
  • the first region 21-1 of the first active layer 21, the first region 22-1 of the second active layer 22, the first region 24-1 of the fourth active layer 24, the first region 25-1 of the fifth active layer 25, the second region 25-2 of the fifth active layer 25, and the first region 26-1 of the sixth active layer 26 may be separately provided.
  • the semiconductor layer may be made of oxide, and the first transistor T1 to the sixth transistor T6 are all oxide transistors.
  • the semiconductor film may be made of indium gallium zinc oxide (IGZO) with high electron mobility.
  • the thickness of the semiconductor layer may be about 20nm to 40nm. For example, the thickness of the semiconductor layer may be about 30nm.
  • forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 8A and 8B , where FIG. 8B is a plan view schematic diagram of the first conductive layer in FIG. 8A .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern includes at least a first scan signal line 31 , a second scan signal line 32 , a third scan signal line 33 , a first light emission control line 34 , a second light emission control line 35 and a first plate 36 of a storage capacitor.
  • the shape of the first electrode plate 36 may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 36 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode plate 36 may simultaneously serve as a plate of the storage capacitor and a top gate electrode of the third transistor T3 (driving transistor), that is, the top gate electrode of the third transistor T3 and the first electrode plate 36 of the storage capacitor are an integrated structure.
  • the first scan signal line 31 , the second scan signal line 32 , the third scan signal line 33 , the first light emission control line 34 , and the second light emission control line 35 may be in the shape of a straight line extending along the first direction X or a folded line.
  • the first scan signal line 31 can be located on one side of the first electrode plate 36 in the second direction Y, and the area where the first scan signal line 31 overlaps with the first active layer serves as the top gate electrode of the first transistor T1, that is, the first scan signal line 31 and the top gate electrode of the first transistor T1 are an integrated structure connected to each other.
  • the orthographic projection of the first scan signal line 31 on the substrate may be located within the range of the orthographic projection of the first shielding line 11 on the substrate, so that the channel region of the first transistor T1 may be effectively shielded by the first shielding line 11 .
  • the second scan signal line 32 may be located at one side of the first electrode plate 36 in the second direction Y, and between the first electrode plate 36 and the first scan signal line 31.
  • a fourth top gate electrode 32-1 is connected to one side of the second scan signal line 32 close to the first electrode plate 36, and an orthographic projection of the fourth top gate electrode 32-1 on the substrate at least partially overlaps an orthographic projection of the fourth active layer on the substrate, and the fourth top gate electrode 32-1 is configured as a top gate electrode of the fourth transistor T4.
  • the orthographic projection of the second scanning signal line 32 on the substrate can be located within the range of the orthographic projection of the second shielding line 12 on the substrate, and the orthographic projection of the fourth top gate electrode 32-1 on the substrate can be located within the range of the orthographic projection of the fourth bottom gate electrode 12-1 on the substrate, so that the channel region of the fourth transistor T4 can be effectively shielded by the fourth bottom gate electrode 12-1.
  • the third scan signal line 33 may be located on a side of the first electrode plate 36 in the opposite direction of the second direction Y, so that the first electrode plate 36 is located between the second scan signal line 32 and the third scan signal line 33.
  • a second top gate electrode 33-1 is connected to a side of the third scan signal line 33 close to the first electrode plate 36, and an orthographic projection of the second top gate electrode 33-1 on the substrate at least partially overlaps with an orthographic projection of the second active layer on the substrate, and the second top gate electrode 33-1 is configured as a top gate electrode of the second transistor T2.
  • the orthographic projection of the third scanning signal line 33 on the substrate can be located within the range of the orthographic projection of the third shielding line 13 on the substrate, and the orthographic projection of the second top gate electrode 33-1 on the substrate can be located within the range of the orthographic projection of the second bottom gate electrode 13-1 on the substrate, so that the channel region of the second transistor T2 can be effectively shielded by the second bottom gate electrode 13-1.
  • the first scan signal line 31 and the third scan signal line 33 may transmit the same scan signal, and the first scan signal line 31 and the third scan signal line 33 are connected to the same scan signal source.
  • the first light-emitting control line 34 can be located on a side of the second scanning signal line 32 away from the first electrode plate 36, and can be located between the first scanning signal line 31 and the second scanning signal line 32.
  • the area where the first light-emitting control line 34 overlaps with the sixth active layer serves as the top gate electrode of the sixth transistor T6, that is, the first light-emitting control line 34 and the top gate electrode of the sixth transistor T6 are an integrated structure that is interconnected.
  • the orthographic projection of the first light emitting control line 34 on the substrate may be located within the range of the orthographic projection of the fourth shielding line 14 on the substrate, so that the channel region of the sixth transistor T6 may be effectively shielded by the fourth shielding line 14 .
  • the second light-emitting control line 35 can be located on a side of the third scanning signal line 33 away from the first electrode plate 36, and the area where the second light-emitting control line 35 overlaps with the fifth active layer serves as the top gate electrode of the fifth transistor T5, that is, the second light-emitting control line 35 and the top gate electrode of the fifth transistor T5 are an integrated structure connected to each other.
  • the orthographic projection of the second light emitting control line 35 on the substrate may be located within the range of the orthographic projection of the fifth shielding line 15 on the substrate, so that the channel region of the fifth transistor T5 may be effectively shielded by the fifth shielding line 15 .
  • the first conductive layer after forming the first conductive layer pattern, can be used as a shield to perform conductorization on the semiconductor layer.
  • the semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the sixth transistor T6, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor T1 to the sixth active layer are both conductorized.
  • forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 9A and 9B , where FIG. 9B is a plan view of the second conductive layer in FIG. 9A .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit includes at least an initial sub-line 41 and a second electrode 42 of a storage capacitor.
  • the outline of the second electrode plate 42 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second electrode plate 42 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 36 on the substrate.
  • the second electrode plate 42 can serve as another electrode plate of the storage capacitor, and the first electrode plate 36 and the second electrode plate 42 constitute the storage capacitor of the pixel driving circuit.
  • an opening 43 is provided on the second electrode plate 42.
  • the opening 43 may be rectangular and may be located in the middle of the second electrode plate 42, so that the second electrode plate 42 forms a ring structure.
  • the opening 43 exposes the third insulating layer covering the first electrode plate 36, and the orthographic projection of the first electrode plate 36 on the substrate includes the orthographic projection of the opening 43 on the substrate.
  • the opening 43 is configured to accommodate a first via hole formed subsequently. The first via hole is located in the opening 43 and exposes the first electrode plate 36, so that the second electrode of the first transistor T1 formed subsequently is connected to the first electrode plate 36.
  • the initial sub-line 41 may be in the shape of a line whose main portion extends along the first direction X. In the first direction X, the initial sub-line 41 may be disposed between first regions of first active layers of adjacent circuit units in the first direction X. In the second direction Y, the initial sub-line 41 may be located on a side of the first scan signal line 31 away from the second electrode plate 42. The initial sub-line 41 is configured to form a first initial signal line that transmits an initial voltage signal and extends along the first direction X using an initial connection electrode formed subsequently.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are disposed on the fourth insulating layer, as shown in FIG. 10 .
  • the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 43 on the substrate, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 36, and the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 36 through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the second region of the sixth active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor T1 (also the second electrode of the sixth transistor T6) to the second region of the first active layer (also the second region of the sixth active layer) through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fifth active layer, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the first region of the fifth active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the fifth active layer, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed fifth transistor T5 to the second region of the fifth active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second region of the second active layer (also the first region of the third active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second region of the second active layer, and the fifth via hole V5 is configured to connect the second electrode of the subsequently formed second transistor T2 (also the first electrode of the third transistor T3) to the second region of the second active layer (also the first region of the third active layer) through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the fourth active layer, and the sixth via hole V6 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the first region of the fourth active layer through the via hole.
  • the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the second area of the fourth active layer (also the second area of the third active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via V7 are etched away to expose the surface of the second area of the fourth active layer, and the seventh via V7 is configured to connect the second electrode of the subsequently formed fourth transistor T4 (also the second electrode of the third transistor T3) to the second area of the fourth active layer (also the second area of the third active layer) through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the sixth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first region of the sixth active layer, and the eighth via V8 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the first region of the sixth active layer through the via.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first region of the second active layer, and the ninth via hole V9 is configured to connect the first electrode of the subsequently formed second transistor T2 to the first region of the second active layer through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the blocking connection block 16-1 of the blocking electrode 16 on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the tenth via hole V10 are etched away to expose the surface of the blocking connection block 16-1, and the tenth via hole V10 is configured to connect the subsequently formed fifth connection electrode to the blocking electrode 16 through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode plate 42 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second electrode plate 42, and the eleventh via hole V11 is configured to connect the subsequently formed seventh connecting electrode to the second electrode plate 42 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the first region of the first active layer, and the twelfth via hole V12 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the first active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the end of the initial sub-line 41 close to the first region of the first active layer on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the end of the initial sub-line 41, and the thirteenth via hole V13 is configured to connect the first electrode of the subsequently formed first transistor T1 to the initial sub-line 41 through the via hole.
  • forming the third conductive layer may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 11A and 11B , where FIG. 11B is a plan view of the third conductive layer in FIG. 11A .
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer of each circuit unit includes at least first connection electrode 51 , second connection electrode 52 , third connection electrode 53 , fourth connection electrode 54 , fifth connection electrode 55 , sixth connection electrode 56 , seventh connection electrode 57 and initial connection electrode 58 .
  • the shape of the first connection electrode 51 can be a zigzag shape with the main part extending along the second direction Y.
  • the first end of the first connection electrode 51 is connected to the first electrode plate 36 through the first via hole V1
  • the second end of the first connection electrode 51 is connected to the first region of the second active layer through the ninth via hole V9, so that the first electrode plate 36 and the first electrode of the second transistor T2 have the same potential.
  • the first connection electrode 51 can serve as the first electrode of the second transistor T2 (i.e., the first node N1 of the pixel driving circuit).
  • the second connection electrode 52 may be in a polygonal shape, and the second connection electrode 52 is connected to the first region of the fifth active layer through the third via hole V3.
  • the second connection electrode 52 may serve as a first electrode of the fifth transistor T5, and the second connection electrode 52 is configured to be connected to a first power line formed subsequently.
  • the third connection electrode 53 may be in a strip shape with a main portion extending along the second direction Y, a first end of the third connection electrode 53 is connected to the second region of the fifth active layer through a fourth via hole V4, and a second end of the third connection electrode 53 is connected to the second region of the second active layer through a fifth via hole V5.
  • the third connection electrode 53 may simultaneously serve as the second electrode of the second transistor T2, the first electrode of the third transistor T3, and the second electrode of the fifth transistor T5 (i.e., the second node N2 of the pixel driving circuit).
  • the shape of the fourth connection electrode 54 may be polygonal, and the fourth connection electrode 54 is connected to the first region of the fourth active layer through the sixth via hole V6.
  • the fourth connection electrode 54 may serve as a first electrode of the fourth transistor T4, and the fourth connection electrode 54 is configured to be connected to a subsequently formed data signal line.
  • the fifth connection electrode 55 may be in an "L" shape, the first end of the fifth connection electrode 55 is connected to the first region of the sixth active layer through the eighth via hole V8, the second end of the fifth connection electrode 55 is connected to the shielding connection block 16-1 of the shielding electrode 16 through the tenth via hole V10, the third end of the fifth connection electrode 55 is connected to the second region of the fourth active layer through the seventh via hole V7, and the third end of the fifth connection electrode 55 is located between the first end and the second end.
  • the fifth connection electrode 55 may simultaneously serve as the second electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first electrode of the sixth transistor T6 (i.e., the third node N3 of the pixel driving circuit). Since the shielding electrode 16 serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4 and the first electrode of the sixth transistor T6 through the fifth connection electrode 55.
  • the shape of the sixth connection electrode 56 may be polygonal, and the sixth connection electrode 56 is connected to the second region of the first active layer (also the second region of the sixth active layer) through the second via hole V2.
  • the sixth connection electrode 56 may simultaneously serve as the second electrode of the first transistor T1 and the second electrode of the sixth transistor T6, and the sixth connection electrode 56 is configured to be connected to the anode connection electrode formed subsequently.
  • the seventh connection electrode 57 may be in a polygonal shape, and the seventh connection electrode 57 is connected to the second electrode plate 42 through the eleventh via hole V11. In an exemplary embodiment, the seventh connection electrode 57 is configured to be connected to an anode connection electrode formed subsequently.
  • the shape of the initial connection electrode 58 can be a strip shape with the main part extending along the first direction X.
  • the middle part of the initial connection electrode 58 is connected to the first area of the first active layer through the twelfth via hole V12, and the two ends of the initial connection electrode 58 are respectively connected to the ends of the adjacent initial sub-lines 41 through the thirteenth via hole V13.
  • the mutual connection between the multiple initial sub-lines 41 is realized to form the first initial signal line.
  • the connection between the first initial signal line and the first electrode of the first transistor T1 is realized, so that the initial voltage transmitted by the first initial signal line is written into the first electrode of the first transistor T1.
  • Forming a first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein a plurality of vias are disposed on the first planar layer, as shown in FIG. 12 .
  • the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , a twenty-third via V23 , and a twenty-fourth via V24 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are etched away to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect a subsequently formed first power line to the second connecting electrode 52 through the via hole.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are etched away to expose the surface of the fourth connecting electrode 54, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the fourth connecting electrode 54 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.
  • the orthographic projection of the twenty-fourth via hole V24 on the substrate is within the range of the orthographic projection of the seventh connecting electrode 57 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fourth via hole V24 are etched away to expose the surface of the seventh connecting electrode 57, and the twenty-fourth via hole V24 is configured to connect a subsequently formed anode connecting electrode to the seventh connecting electrode 57 through the via hole.
  • some circuit units also include a twenty-fifth via hole V25, the orthographic projection of the twenty-fifth via hole V25 on the substrate at least partially overlaps with the orthographic projection of the initial connection electrode 58 on the substrate, the first flat layer and the fifth insulating layer within the twenty-fifth via hole V25 are etched away to expose the surface of the initial connection electrode 58, and the twenty-fifth via hole V25 is configured to connect a subsequently formed second initial signal line to the initial connection electrode 58 through the via hole.
  • the twenty-fifth via V25 may be disposed in the circuit unit in the n+1th column, that is, the circuit unit in the n+1th column is provided with the second initial signal line, while the circuit units in the n-1th column and the nth column are not provided with the twenty-fifth via V25.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, as shown in FIGS. 13A and 13B , where FIG. 13B is a plan view of the fourth conductive layer in FIG. 13A .
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer of each circuit unit includes at least an anode connection electrode 61 , a first power line 62 , and a data signal line 63 .
  • the shape of the anode connection electrode 61 can be a zigzag shape with the main part extending along the second direction Y, the first end of the anode connection electrode 61 is connected to the sixth connection electrode 56 through the twenty-third via hole V23, and the second end of the anode connection electrode 61 is connected to the seventh connection electrode 57 through the twenty-fourth via hole V24.
  • the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the first active layer) through the via hole, and the seventh connection electrode 57 is connected to the second electrode plate 42 through the via hole, the second electrode plate 42, the second electrode of the first transistor T1, and the second electrode of the sixth transistor T6 have the same potential (i.e., the fourth node N4 of the pixel driving circuit).
  • the anode connection electrode 61 is configured to be connected to the anode formed subsequently, so that the pixel driving circuit can output a driving current to the light-emitting device.
  • the shape of the first power line 62 may be a straight line or a folded line with a main portion extending along the second direction Y, and the first power line 62 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fifth active layer through the via hole, the first power line 62 can write a constant first voltage signal to the first electrode of the fifth transistor T5.
  • the data signal line 63 may be in the shape of a straight line with a main portion extending along the second direction Y, and the data signal line 63 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. Since the fourth connection electrode 54 is connected to the first region of the fourth active layer through the via hole, the data signal line 63 can write the data signal to the first electrode of the fourth transistor T4.
  • the fourth conductive layer of a part of the circuit unit may further include a second initial signal line 80.
  • the shape of the second initial signal line 80 may be a straight line or a folded line with the main part extending along the second direction Y, and the second initial signal line 80 is connected to the initial connection electrode 58 through the twenty-fifth via hole V25.
  • the initial sub-line 41 constitutes a first initial signal line extending along the first direction X through the initial connection electrode 58
  • the second initial signal line 80 is connected to the initial connection electrode 58
  • the first initial signal line extending along the first direction X and the second initial signal line 80 extending along the second direction Y constitute an initial signal line of a network connection structure in the display area, which can minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, and effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the fourth conductive layer of the partial circuit unit may further include a low-voltage power line (second power line) 90.
  • the low-voltage power line 90 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y, and may be located between the first power line 62 and the data signal line 63.
  • the low-voltage power line 90 is configured to output a constant second voltage signal to the cathode of the light-emitting device.
  • the plurality of unit columns of the display panel may include at least a first unit column, a second unit column, and a third unit column, the pixel driving circuits of the plurality of circuit units in the first unit column are connected to the red light emitting device emitting red light, the pixel driving circuits of the plurality of circuit units in the second unit column are connected to the green light emitting device emitting green light, and the pixel driving circuits of the plurality of circuit units in the third unit column are connected to the blue light emitting device emitting blue light.
  • the n-1th column may be the first unit column
  • the nth column may be the second unit column
  • the n+1th column may be the third unit column
  • the low voltage power line 90 may be provided in the circuit units in the n-1th column and the nth column
  • the second initial signal line 80 may be provided in the circuit unit in the n+1th column.
  • the second initial signal line 80 may be disposed in the circuit units of the nth and n+1th columns, and the low voltage power line 90 may be disposed in the circuit unit of the n-1th column, which is not limited in the present disclosure.
  • a second flat film is coated on the substrate on which the aforementioned pattern is formed, and the second flat film is patterned using a patterning process to form a second flat layer covering the fourth conductive layer pattern, and an anode via is provided on the second flat layer, and the orthographic projection of the anode via on the substrate is located within the range of the orthographic projection of the anode connecting electrode on the substrate, and the anode via is configured to connect a subsequently formed anode to the anode connecting electrode through the via.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a first light-emitting control line, a second light-emitting control line, a first initial signal line, a first power line, and a data signal line connected to the pixel drive circuit.
  • the drive circuit layer may include a shielding conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer, and a second flat layer sequentially arranged on the substrate.
  • the shielding conductive layer may include at least a shielding electrode and a plurality of shielding lines
  • the semiconductor layer may include at least an active layer of the first transistor to the sixth transistor
  • the first conductive layer may include at least a first plate of a storage capacitor
  • the second conductive layer may include at least a second plate of a storage capacitor
  • the third conductive layer may include at least a first electrode and a second electrode of the first transistor to the sixth transistor
  • the fourth conductive layer may include at least an anode connection electrode.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer may be referred to as a buffer layer
  • the second insulating layer and the third insulating layer may be referred to as a gate insulating (GI) layer
  • the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer
  • the fifth insulating layer may be referred to as a passivation (PVX) layer.
  • the shielding conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), etc., or may be made of alloy materials composed of metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., and may be a single layer structure, or may be a multilayer composite structure, such as Ti/Al/Ti, etc.
  • the first planar layer and the second planar layer may be made of organic materials, such as resin or polyimide.
  • a light emitting structure layer may be prepared on the driving circuit layer, and a packaging structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.
  • the pixel driving circuit of this exemplary embodiment uses 6 oxide transistors to meet the driving requirements. Compared with the existing pixel driving circuit structure of 7 transistors, it not only reduces the number of transistors, simplifies the structure of the pixel driving circuit structure, reduces the occupied area of the pixel driving circuit, is conducive to achieving high-resolution (PPI) display, but also can ensure the yield of large-size display substrates and reduce production costs.
  • the bottom gate electrode is arranged in the shielding conductive layer, and the top gate electrode is arranged in the first conductive layer, which can ensure the shielding effect and improve the electrical performance of the transistor.
  • the present disclosure sets a first initial signal line extending along the first direction X and a second initial signal line extending along the second direction Y in the display area, and the initial signal line of the network connection structure is formed in the display area, which can minimize the resistance of the initial signal line, reduce the voltage drop of the initial voltage, and effectively improve the uniformity of the initial voltage in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the present disclosure realizes the structure of VSS in pixel by setting a low-voltage power line in the display area, which not only effectively reduces the resistance of the low-voltage power line, effectively reduces the voltage drop of the low-voltage power signal, and realizes low power consumption, but also effectively improves the uniformity of the low-voltage power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.
  • the preparation process disclosed in the present disclosure is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.
  • the display substrate may include two first initial signal lines extending along the first direction (such as the first horizontal initial line and the second horizontal initial line) and two second initial signal lines extending along the second direction (such as the first vertical initial line and the second vertical initial line).
  • first horizontal initial line and the first vertical initial line can be connected by vias
  • second horizontal initial line and the second vertical initial line can be connected by vias to form an initial signal line of a dual network connection structure in the display area.
  • the display substrate may include a first low-voltage power line extending along the first direction and a second low-voltage power line extending along the second direction.
  • the first low-voltage power line and the second low-voltage power line are connected by vias to form a low-voltage power line of a network connection structure in the display area.
  • FIG14 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a first shielding block 101 is provided on the first power line 62 in the fourth conductive layer.
  • the first blocking block 101 can be arranged on one side of the first power line 62 in the first direction X (close to the data signal line 63), which is equivalent to setting a protrusion on the first power line 62.
  • the orthographic projection of the first blocking block 101 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer of the fifth transistor T5 on the substrate.
  • the first blocking block 101 is configured to block the fifth transistor T5, reduce the influence of light on the electrical characteristics of the fifth transistor T5, and improve the working stability of the fifth transistor T5.
  • the first blocking block 101 and the first power line 62 may be an integral structure connected to each other, and an orthographic projection of the first blocking block 101 on the substrate at least partially overlaps an orthographic projection of the channel region of the fifth active layer on the substrate.
  • FIG15 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5 , except that, in at least one circuit unit, a second shielding block 102 is provided on the second initial signal line 80 and/or the low voltage power line 90 in the fourth conductive layer.
  • the second blocking block 102 can be arranged on a side of the second initial signal line 80 and/or the low-voltage power line 90 in the opposite direction of the first direction X (close to the first power line 62), which is equivalent to setting a protrusion on the second initial signal line 80 and/or the low-voltage power line 90.
  • the orthographic projection of the second blocking block 102 on the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate.
  • the second blocking block 102 is configured to block the second transistor T2, reduce the influence of light on the electrical characteristics of the second transistor T2, and improve the working stability of the second transistor T2.
  • the second blocking block 102 and the second initial signal line 80 of a partial circuit unit may be an integrated structure connected to each other
  • the second blocking block 102 and the low-voltage power line 90 of a partial circuit unit may be an integrated structure connected to each other
  • the orthographic projection of the second blocking block 102 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second active layer on the substrate.
  • FIG16 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a third shielding block 103 is provided on the second initial signal line 80 and/or the low voltage power line 90 in the fourth conductive layer.
  • the third blocking block 103 can be arranged on a side of the second initial signal line 80 and/or the low-voltage power line 90 in the opposite direction of the first direction X (close to the first power line 62), which is equivalent to providing a protrusion on the second initial signal line 80 and/or the low-voltage power line 90.
  • the orthographic projection of the third blocking block 103 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer of the fourth transistor T4 on the substrate.
  • the third blocking block 103 is configured to block the fourth transistor T4, reduce the influence of light on the electrical characteristics of the fourth transistor T4, and improve the working stability of the fourth transistor T4.
  • the third blocking block 103 and the second initial signal line 80 of a partial circuit unit may be an integrated structure connected to each other
  • the third blocking block 103 and the low-voltage power line 90 of a partial circuit unit may be an integrated structure connected to each other
  • the orthographic projection of the third blocking block 103 on the substrate at least partially overlaps with the orthographic projection of the channel region of the fourth active layer on the substrate.
  • FIG17 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a fourth shielding block 104 is provided on the second initial signal line 80 and/or the low voltage power line 90 in the fourth conductive layer.
  • the fourth blocking block 104 can be arranged on a side of the second initial signal line 80 and/or the low-voltage power line 90 in the opposite direction of the first direction X (close to the first power line 62), which is equivalent to setting a protrusion on the second initial signal line 80 and/or the low-voltage power line 90.
  • the orthographic projection of the fourth blocking block 104 on the substrate at least partially overlaps with the orthographic projection of the first active layer of the first transistor T1 on the substrate.
  • the fourth blocking block 104 is configured to block the first transistor T1, reduce the influence of light on the electrical characteristics of the first transistor T1, and improve the working stability of the first transistor T1.
  • the fourth blocking block 104 and the second initial signal line 80 of a partial circuit unit may be an integrated structure connected to each other
  • the fourth blocking block 104 and the low-voltage power line 90 of a partial circuit unit may be an integrated structure connected to each other
  • the orthographic projection of the fourth blocking block 104 on the substrate at least partially overlaps with the orthographic projection of the channel region of the first active layer on the substrate.
  • the fourth shielding block 104 may be disposed at a position of the first power line 62 close to the first transistor T1 , which is equivalent to providing a protrusion on the first power line 62 to shield the first transistor T1 .
  • the fourth blocking blocks 104 of some circuit units can be set on the first power line 62, the fourth blocking blocks 104 of some circuit units can be set on the second initial signal line 80, and the fourth blocking blocks 104 of some circuit units can be set on the low-voltage power line 90, which is not limited in the present disclosure.
  • FIG18 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a fifth shielding block 105 is provided on the anode connection electrode 61 in the fourth conductive layer.
  • the fifth blocking block 105 can be arranged on one side of the anode connecting electrode 61 in the first direction X (close to the data signal line 63), which is equivalent to increasing the size of the anode connecting electrode 61.
  • the orthographic projection of the fifth blocking block 105 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer of the sixth transistor T6 on the substrate.
  • the fifth blocking block 105 is configured to block the sixth transistor T6, reduce the influence of light on the electrical characteristics of the sixth transistor T6, and improve the working stability of the sixth transistor T6.
  • the fifth blocking block 105 and the anode connection electrode 61 may be an integral structure connected to each other, and an orthographic projection of the fifth blocking block 105 on the substrate at least partially overlaps an orthographic projection of the channel region of the sixth active layer on the substrate.
  • FIG19 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a shielding block 111 is provided on the first power line 62 in the fourth conductive layer.
  • the shielding block 111 can be disposed on one side of the first power line 62 in the first direction X (close to the data signal line 63), which is equivalent to providing a protrusion on the first power line 62.
  • the positive projection of the shielding block 111 on the substrate at least partially overlaps with the positive projection of the second plate of the storage capacitor 50 on the substrate.
  • the shielding block 111 is configured to shield the fourth node N4 of the pixel driving circuit to stabilize the anode potential.
  • the shielding block 111 and the first power line 62 may be an integral structure connected to each other.
  • FIG20 is a schematic diagram of the planar structure of another display substrate of the exemplary embodiment of the present disclosure, illustrating the planar structure of the pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, the second initial signal line 80 in the fourth conductive layer may include a first initial straight portion 80A, a second initial straight portion 80B, and an initial bending portion 80C between the first initial straight portion 80A and the second initial straight portion 80B, and/or, the low voltage power line 90 may include a first power straight portion 90A, a second power straight portion 90B, and a power bending portion 90C between the first power straight portion 90A and the second power straight portion 90B.
  • the first end of the initial bend portion 80C is connected to the first initial straight portion 80A
  • the second end of the initial bend portion 80C is connected to the second initial straight portion 80B
  • the middle portion of the initial bend portion 80C protrudes toward the direction close to the first power line 62, so that the positive projection of the second initial signal line 80 on the substrate does not overlap with the positive projection of the first connecting electrode 51 (the first node N1 of the pixel driving circuit) on the substrate
  • the initial bend portion 80C of the second initial signal line 80 is configured to avoid the first node N1 of the pixel driving circuit to reduce the voltage division of the first node N1 and improve the potential stability of the key nodes of the pixel driving circuit.
  • a first end of the power bend 90C is connected to the first power straight portion 90A
  • a second end of the power bend 90C is connected to the second power straight portion 90B
  • a middle portion of the power bend 90C protrudes toward the direction close to the first power line 62, so that the orthographic projection of the low-voltage power line 90 on the substrate does not overlap with the orthographic projection of the first connecting electrode 51 (the first node N1 of the pixel driving circuit) on the substrate
  • the power bend 90C of the low-voltage power line 90 is configured to avoid the first node N1 of the pixel driving circuit to reduce the voltage division of the first node N1 and improve the potential stability of the key nodes of the pixel driving circuit.
  • Fig. 21 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of this exemplary embodiment is substantially the same as the main structure of the display substrate shown in Fig. 5, except that a complete first initial signal line 70 is formed when the second conductive layer is formed.
  • the first preliminary signal line 70 may be shaped like a zigzag line with a main portion extending along the first direction X, and the first preliminary signal lines 70 of adjacent circuit units are connected to each other.
  • the first initial signal line 70 may include an initial straight portion 70A and an initial avoidance portion 70B.
  • the initial straight portion 70A may be in the shape of a line extending along the first direction X, and may be disposed between adjacent first active layers in the first direction X. Both ends of the initial avoidance portion 70B in the first direction X are respectively connected to the initial straight portion 70A, and the middle portion of the initial avoidance portion 70B protrudes in a direction away from the first active layer, so that the orthographic projection of the initial avoidance portion 70B on the substrate does not overlap with the orthographic projection of the first active layer on the substrate.
  • the initial straight portion 70A and the initial avoidance portion 70B may be an integrated structure connected to each other to form a complete first initial signal line 70. Since the complete first initial signal line 70 is formed when the second conductive layer is formed, the subsequent process can save the corresponding vias and initial connection electrodes, reducing the process difficulty.
  • FIG22 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a first capacitor block 121 is provided on the anode connection electrode 61 in the fourth conductive layer.
  • the first capacitor block 121 can be arranged on one side of the anode connecting electrode 61 in the first direction X (close to the data signal line 63), or, can be arranged on one side of the anode connecting electrode 61 in the opposite direction of the first direction X (close to the first power line 62), or, can be arranged on both sides of the anode connecting electrode 61 in the first direction X, and the positive projection of the first capacitor block 121 on the substrate at least partially overlaps with the positive projection of the second scanning signal line 32 on the substrate, and the first capacitor block 121 is configured to increase the parasitic capacitance between the anode connecting electrode 61 (the fourth node N4 of the pixel driving circuit) and the second scanning signal line 32.
  • the falling edge of the signal on the second scanning signal line 32 can lower the potential of the fourth node N4, thereby enhancing the black screen display effect.
  • the parasitic capacitance between the anode connection electrode 61 and the second scan signal line 32 is greater than the parasitic capacitance between the anode connection electrode 61 and the first light emission control line 34 .
  • the first capacitor block 121 and the anode connection electrode 61 may be an integral structure connected to each other.
  • FIG23 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating a planar structure of a pixel driving circuit in three circuit units in a unit row.
  • the main structure of the display substrate of the exemplary embodiment is substantially the same as the main structure of the display substrate shown in FIG5, except that, in at least one circuit unit, a second capacitor block 122 is provided on the anode connection electrode 61 in the fourth conductive layer.
  • the second capacitor block 122 can be arranged on one side of the anode connecting electrode 61 in the first direction X (close to the data signal line 63), or, can be arranged on one side of the anode connecting electrode 61 in the opposite direction of the first direction X (close to the first power line 62), or, can be arranged on both sides of the anode connecting electrode 61 in the first direction X, and the positive projection of the second capacitor block 122 on the substrate at least partially overlaps with the positive projection of the first scanning signal line 31 on the substrate, and the second capacitor block 122 is configured to increase the parasitic capacitance between the anode connecting electrode 61 (the fourth node N4 of the pixel driving circuit) and the first scanning signal line 31.
  • the potential of the fourth node N4 can be lowered to enhance the black screen display effect.
  • the parasitic capacitance between the anode connection electrode 61 and the first scan signal line 31 is greater than the parasitic capacitance between the anode connection electrode 61 and the first light emission control line 34 .
  • the second capacitor block 122 and the anode connection electrode 61 may be an integral structure connected to each other.
  • the schemes shown in FIG. 14 to FIG. 23 and the structures in the schemes may be arbitrarily combined with each other, and the present disclosure is not limited thereto.
  • the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.
  • the present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment.
  • the preparation method may include:
  • a driving circuit layer is formed on a substrate, wherein the driving circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of first initial signal lines extending along a first direction, and a plurality of second initial signal lines and a low-voltage power supply line extending along a second direction, wherein the first direction intersects with the second direction, wherein the circuit unit includes at least a pixel driving circuit, wherein the pixel driving circuit includes a storage capacitor and a plurality of oxide transistors, wherein the first initial signal line is configured to provide an initial voltage signal to the pixel driving circuit, wherein the second initial signal line is connected to the first initial signal line, and wherein the first initial signal line and the second initial signal line form a mesh connection structure;
  • a light emitting structure layer is formed on the driving circuit layer, wherein the light emitting structure layer includes a plurality of light emitting devices, and the low voltage power line is configured to provide a low power voltage signal to the light emitting devices.
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括设置在基底(10)上的驱动电路层(20)和发光结构层(30)，驱动电路层(20)包括多个电路单元、多条沿着第一方向延伸的第一初始信号线(70)、以及多条沿着第二方向延伸的第二初始信号线(80)和低压电源线(90)，电路单元至少包括像素驱动电路，发光结构层包括多个发光器件，第一初始信号线(70)被配置为向像素驱动电路提供初始电压信号，低压电源线(90)被配置为向发光器件提供低电源电压信号，第二初始信号线(80)与第一初始信号线(70)连接，第一初始信号线(70)和第二初始信号线(80)构成网状连通结构。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括构成多个单元行和多个单元列的多个电路单元、多条沿着第一方向延伸的第一初始信号线、以及多条沿着第二方向延伸的第二初始信号线和低压电源线，所述第一方向和所述第二方向交叉，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述发光结构层包括多个发光器件，所述第一初始信号线被配置为向所述像素驱动电路提供初始电压信号，所述低压电源线被配置为向所述发光器件提供低电源电压信号，所述第二初始信号线与所述第一初始信号线连接，所述第一初始信号线和所述第二初始信号线构成网状连通结构。
在示例性实施方式中，所述第一初始信号线包括沿着所述第一方向间隔 设置的多个初始子线，至少一个电路单元中，在所述第一方向相邻的所述初始子线通过初始连接电极相互连接。
在示例性实施方式中，所述驱动电路层包括多个导电层，所述初始子线和所述初始连接电极设置在不同的导电层中，至少一个电路单元中，所述初始连接电极通过过孔与所述初始子线连接。
在示例性实施方式中，至少一个电路单元中，所述第二初始信号线与所述初始连接电极连接。
在示例性实施方式中，所述驱动电路层包括多个导电层，所述初始连接电极和所述第二初始信号线设置在不同的导电层中，至少一个电路单元中，所述第二初始信号线通过过孔与所述初始连接电极连接。
在示例性实施方式中，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管，至少一个电路单元中，所述第一晶体管的第一极与所述第一初始信号线连接，所述第一晶体管的第二极与所述存储电容的第二极板和所述第六晶体管的第二极连接，所述第二晶体管的第一极与所述存储电容的第一极板连接，所述第二晶体管的第二极与所述第三晶体管的第一极连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第三晶体管的第二极连接，所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与所述第三晶体管的第一极连接，所述第六晶体管的第一极与所述第三晶体管的第二极连接，所述第六晶体管的第二极与所述发光器件连接。
在示例性实施方式中，至少一个电路单元中，所述第一晶体管、第四晶体管和第六晶体管设置在所述存储电容所述第二方向的一侧，所述第二晶体管和第五晶体管设置在所述存储电容所述第二方向的反方向的一侧。
在示例性实施方式中，至少一个电路单元中，所述第四晶体管设置在所述存储电容所述第二方向的一侧，所述第六晶体管设置在所述第四晶体管远离所述存储电容的一侧，所述第一晶体管设置在所述第六晶体管远离所述存储电容的一侧，所述第二晶体管设置在所述存储电容所述第二方向的反方向的一侧，所述第五晶体管设置在所述第二晶体管远离所述存储电容的一侧。
在示例性实施方式中，至少一个电路单元中，所述第一晶体管至少包括第一有源层，所述第六晶体管至少包括第六有源层，所述第一有源层的第二区和所述第六有源层的第一区为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元中，所述第二晶体管至少包括第二有源层，所述第三晶体管至少包括第三有源层，所述第四晶体管至少包括第四有源层，所述第二有源层和第四有源层的形状为沿着所述第一方向延伸的条形状，所述第三有源层的形状为沿着所述第二方向延伸的条形状，所述第三有源层的第一区和所述第二有源层的第二区为相互连接的一体结构，所述第三有源层的第二区和所述第四有源层的第二区为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元中，所述第三晶体管至少包括底栅电极和顶栅电极，所述底栅电极分别与所述第四晶体管的第二极和所述第六晶体管的第一极连接，所述顶栅电极和所述存储电容的第一极板为一体结构。
在示例性实施方式中，所述驱动电路层还包括沿着所述第一方向延伸的第一扫描信号线、第二扫描信号线、第三扫描信号线、第一发光控制线和第二发光控制线，至少一个电路单元中，所述第一扫描信号线与所述第一晶体管的顶栅电极连接，所述第二扫描信号线与所述第四晶体管的顶栅电极连接，所述第三扫描信号线与所述第二晶体管的顶栅电极连接，所述第一发光控制线与所述第六晶体管的顶栅电极连接，所述第二发光控制线与所述第五晶体管的顶栅电极连接。
在示例性实施方式中，至少一个电路单元中，所述第二扫描信号线位于所述存储电容所述第二方向的一侧，所述第一发光控制线位于所述第二扫描信号线远离所述存储电容的一侧，所述第一扫描信号线位于所述第一发光控制线远离所述存储电容的一侧，所述第三扫描信号线位于所述存储电容所述第二方向的反方向的一侧，所述第二发光控制线位于所述第三扫描信号线远离所述存储电容的一侧。
在示例性实施方式中，至少一个电路单元中，所述第一初始信号线设置在所述第一扫描信号线远离所述存储电容的一侧。
在示例性实施方式中，所述驱动电路层至少包括沿着远离所述基底方向依次设置的遮挡导电层、第一导电层、第二导电层、第三导电层和第四导电层，所述遮挡导电层至少包括多个氧化物晶体管的底栅电极，所述第一导电层至少包括所述存储电容的第一极板和多个氧化物晶体管的顶栅电极，所述第二导电层至少包括所述存储电容的第二极板和所述第一初始信号线，所述第三导电层至少包括多个氧化物晶体管的第一极和第二极，所述第四导电层至少包括所述第二初始信号线和低压电源线。
在示例性实施方式中，所述多个单元列至少包括第一单元列、第二单元列和第三单元列，所述第一单元列中多个电路单元的像素驱动电路与出射红色光线的红色发光器件连接，所述第二单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接，所述第三单元列中多个电路单元的像素驱动电路与出射蓝色光线的蓝色发光器件连接，所述低压电源线设置在所述第一单元列和第二单元列中，所述第二初始信号线设置在所述第三单元列中。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，包括：
在基底上形成驱动电路层，所述驱动电路层包括构成多个单元行和多个单元列的多个电路单元、多条沿着第一方向延伸的第一初始信号线、以及多条沿着第二方向延伸的第二初始信号线和低压电源线，所述第一方向和所述第二方向交叉，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述第一初始信号线被配置为向所述像素驱动电路提供初始电压信号，所述第二初始信号线与所述第一初始信号线连接，所述第一初始信号线和所述第二初始信号线构成网状连通结构；
在所述驱动电路层上形成发光结构层，所述发光结构层包括多个发光器件，所述低压电源线被配置为向所述发光器件提供低电源电压信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为本公开示例性实施例一种像素驱动电路的等效电路图；
图5为本公开示例性实施例一种显示基板的平面结构示意图；
图6为本公开实施例形成遮挡导电层图案后的示意图；
图7A和图7B为本公开实施例形成半导体层图案后的示意图；
图8A和图8B为本公开实施例形成第一导电层图案后的示意图；
图9A和图9B为本公开实施例形成第二导电层图案后的示意图；
图10为本公开实施例形成第四绝缘层图案后的示意图；
图11A和图11B为本公开实施例形成第三导电层图案后的示意图；
图12为本公开实施例形成第一平坦层图案后的示意图；
图13A和图13B为本公开实施例形成第四导电层图案后的示意图；
图14为本公开示例性实施例另一种显示基板的平面结构示意图；
图15为本公开示例性实施例又一种显示基板的平面结构示意图；
图16为本公开示例性实施例又一种显示基板的平面结构示意图；
图17为本公开示例性实施例又一种显示基板的平面结构示意图；
图18为本公开示例性实施例又一种显示基板的平面结构示意图；
图19为本公开示例性实施例又一种显示基板的平面结构示意图；
图20为本公开示例性实施例又一种显示基板的平面结构示意图；
图21为本公开示例性实施例又一种显示基板的平面结构示意图；
图22为本公开示例性实施例又一种显示基板的平面结构示意图；
图23为本公开示例性实施例又一种显示基板的平面结构示意图。
附图标记说明:
10—基底；              11—第一遮挡线；      12—第二遮挡线；
13—第三遮挡线；        14—第四遮挡线；      15—第五遮挡线；
16—遮挡电极；          20—驱动电路层；      21—第一有源层；
22—第二有源层；        23—第三有源层；      24—第四有源层；
25—第五有源层；        26—第六有源层；      27—第七有源层；
30—发光结构层；        31—第一扫描信号线；  32—第二扫描信号线；
33—第三扫描信号线；    34—第一发光控制线；  35—第二发光控制线；
36—第一极板；          40—封装结构层；      41—初始子线；
42—第二极板；          43—开口；            50—存储电容；
51—第一连接电极；      52—第二连接电极；    53—第三连接电极；
54—第四连接电极；      55—第五连接电极；    56—第六连接电极；
57—第七连接电极；      58—初始连接电极；    61—阳极连接电极；
62—第一电源线；        63—数据信号线；      70—第一初始信号线；
80—第二初始信号线；    90—低压电源线；      91—第一绝缘层；
92—第二绝缘层；        93—第三绝缘层；      94—第四绝缘层；
95—第五绝缘层；        96—第一平坦层；      97—第二平坦层；
101—第一遮挡块；       102—第二遮挡块；     103—第三遮挡块；
104—第四遮挡块；       105—第五遮挡块；     111—屏蔽块；
121—第一电容块；       122—第二电容块。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容 中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或 电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线状成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线状成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射 停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以单元行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。每个子像素可以均包括电路单元和发光器件，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。每个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子 像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底10上的驱动电路层20、设置在驱动电路层20远离基底10一侧的发光结构层30以及设置在发光结构层30远离基底10一侧的封装结构层40。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，在平行于显示基板的平面上，驱动电路层20可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的扫描信号线、发光控制线、数据信号线和第一电源线等，像素驱动电路可以至少包括多个晶体管和存储电容。在垂直于显示基板的平面内，驱动电路层20可以包括在基底上依次设置的遮挡导电层20-1、第一绝缘层91、半导体层20-2、第二绝缘层92、第一导电层20-3、第三绝缘层93、第二导电层20-4、第四绝缘层94、第三导电层20-5、第五绝缘层95、第一平坦层96、第四导电层20-6和第二平坦层97。遮挡导电层20-1可以至少包括多条遮挡线，半导体层20-2可以至少包括多个晶体管的有源层，第一导电层20-3可以至少包括存储电容的第一极板，第二导电层20-4可以至少包括存储电容的第二极板，第三导电层20-5可以至少包括多个晶体管的第一极和第二极，第四导电层20-6可以至少包括阳极连接电极。
在示例性实施方式中，发光结构层30可以包括多个发光器件，每个发光器件可以至少包括阳极、像素定义层、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层40可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界 水汽无法进入发光结构层30。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻电路单元的发光层可以有少量的交叠，或者可以是相互隔离的。
随着OLED显示技术的逐渐成熟和良率不断提高，OLED显示装置的成本不断下降，使得OLED显示装置逐渐应用于更多领域，例如中大尺寸的电子产品领域。随着显示基板的尺寸的增大，由于采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)薄膜晶体管的显示基板的良率下降，导致成本偏高，因而全部采用氧化物(Oxide)薄膜晶体管的显示基板开始被重视。
本公开示例性实施例提供了一种显示基板，包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括构成多个单元行和多个单元列的多个电路单元、多条沿着第一方向延伸的第一初始信号线、以及多条沿着第二方向延伸的第二初始信号线和低压电源线，所述第一方向和所述第二方向交叉，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述发光结构层包括多个发光器件，所述第一初始信号线被配置为向所述像素驱动电路提供初始电压信号，所述低压电源线被配置为向所述发光器件提供低电源电压信号，所述第二初始信号线与所述第一初始信号线连接，所述第一初始信号线和所述第二初始信号线构成网状连通结构。
在示例性实施方式中，所述第一初始信号线包括沿着所述第一方向间隔设置的多个初始子线，至少一个电路单元中，在所述第一方向相邻的所述初始子线通过初始连接电极相互连接。
在示例性实施方式中，至少一个电路单元中，所述第二初始信号线与所述初始连接电极连接。
在示例性实施方式中，所述多个单元列至少包括第一单元列、第二单元 列和第三单元列，所述第一单元列中多个电路单元的像素驱动电路与出射红色光线的红色发光器件连接，所述第二单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接，所述第三单元列中多个电路单元的像素驱动电路与出射蓝色光线的蓝色发光器件连接，所述低压电源线设置在所述第一单元列和第二单元列中，所述第二初始信号线设置在所述第三单元列中。
下面通过一些示例对本实施例的显示基板进行举例说明。
图4为本公开示例性实施例一种像素驱动电路的等效电路图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图4所示，本公开示例性实施例的像素驱动电路可以包括6个晶体管(第一晶体管T1至第六晶体管T6)和1个存储电容C，像素驱动电路分别与8条信号线(第一扫描信号线S1、第二扫描信号线S2、第一发光信号线E1、第二发光信号线E2、初始信号线INIT、数据信号线D、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3和第四节点N4。其中，第一节点N1分别与第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容C的第一极板连接，第二节点N2分别与第二晶体管T2的第二极、第三晶体管T3的第一极和第五晶体管T5的第二极连接，第三节点N3分别与第三晶体管T3的第二极、第四晶体管T4的第二极和第六晶体管T6的第一极连接，第四节点N4分别与第一晶体管T1的第二极、第六晶体管T6的第二极和存储电容C的第二极板连接，第四节点N4还与发光器件EL的第一极连接。
在示例性实施方式中，存储电容C的第一极板与第一节点N1连接，存储电容C的第二极板与第四节点N4连接，即存储电容C的第一端与第三晶体管T3的栅电极连接，存储电容C的第二端与发光器件EL的第一极连接。
在示例性实施方式中，第一晶体管T1的栅电极与第一扫描信号线S1连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管T1的第二极与存储电容C的第二极板和第四节点N4连接。当导通电平扫描信号施加到第一扫描信号线S1时，第一晶体管T1导通，将初始化电压分别传输到 存储电容C的第二极板和发光器件EL的第一极，实现存储电容C和发光器件EL的初始化。
在示例性实施方式中，第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第二节点N2连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的栅电极与第三晶体管T3的第一极连接。
在示例性实施方式中，第三晶体管T3的栅电极与第一节点N1连接，即第三晶体管T3的栅电极与存储电容C的第一极板连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其栅电极与第一极之间的电位差来确定在第一电源线VDD与发光器件之间流动的驱动电流的大小。
在示例性实施方式中，第四晶体管T4的栅电极与第二扫描信号线S2连接，第四晶体管T4的第一极与数据信号线D连接，第四晶体管T4的第二极与第三节点N3连接。当导通电平扫描信号施加到第二扫描信号线S2时，第四晶体管T4使数据信号线D的数据电压输入到第三节点N3。
在示例性实施方式中，第五晶体管T5的栅电极与第二发光信号线E2连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的栅电极与第一发光信号线E1连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。当导通电平发光信号施加到第一发光信号线E1和第二发光信号线E2时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与发光器件之间形成驱动电流路径而使发光器件发光。
在示例性实施方式中，发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，像素驱动电路的六个晶体管可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的 工艺难度，提高产品的良率。
在示例性实施方式中，像素驱动电路的六个晶体管可以采用氧化物薄膜晶体管。氧化物薄膜晶体管的有源层可以采用氧化物半导体(Oxide)。氧化物薄膜晶体管具有漏电流低等优点，采用设置氧化物薄膜晶体管的显示基板，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，发光器件EL的第二极与第二电源线VSS连接，第一电源线VDD可以配置为向像素驱动电路提供恒定的第一电压信号，第二电源线VSS可以配置为向像素驱动电路提供恒定的第二电压信号，并且第一电压信大于第二电压信号，初始信号线INIT可以配置为向像素驱动电路提供初始电压信号。初始电压信号可以为恒压信号，其大小可以介于第一电源线VDD提供的第一电压信号和第二电源线VSS提供的第二电压信号之间，本公开在此不做限定。
在一些示例中，以像素驱动电路包括的第一晶体管T1至第六晶体管T6均为N型晶体管为例，像素驱动电路的工作过程可以包括以下阶段。
第一阶段A1，称为初始化阶段。第一扫描信号线S1提供的高电平信号使第一晶体管T1和第二晶体管T2导通，第二发光信号线E2提供的高电平信号使第五晶体管T5导通。第一晶体管T1导通使得初始信号线INIT提供的初始电压信号被提供至第四节点N4和存储电容C的第二极板，对存储电容C和发光器件EL进行初始化，清除存储电容C中原有数据电压，清空发光器件EL的第一极的预存电压，完成初始化，发光元件EL不发光。第二晶体管T2导通使得第一节点N1和第二节点N2连接，第五晶体管T5导通使得第一电源线VDD输出的第一电压信号通过第五晶体管T5、第二节点N2和第一节点N1充入存储电容C的第一极板，由于存储电容C的第一极板为高电平，因此第三晶体管T3导通。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段。第二扫描信号线S2提供高电平信号，使第四晶体管T4导通。第四晶体管T4导通使得数据信号线D输出的数据电压经过第三节点N3、导通的第三晶体管T3、第二节点N2、导通的第二晶体管T2提供至第一节点N1，并将数据信号线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C的第一极板。
第三阶段A3，称为发光阶段。第一发光控制线E1和第二发光信号线E2提供高电平信号使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的第一电压信号通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光元件EL的第一极提供驱动电压，驱动发光元件EL发光。
在像素驱动电路的驱动过程中，流经发光元件EL的电流与第三晶体管T3的阈值电压无关，因而像素驱动电路可以较好地补偿第三晶体管T3的阈值电压。
图5为本公开示例性实施例一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。在示例性实施方式中，在垂直于显示基板的方向上，显示基板可以包括设置在基底上的驱动电路层、设置在驱动电路层远离基底一侧的发光结构层以及设置在发光结构层远离基底一侧的封装结构层。在平行于显示基板的方向上，驱动电路层可以包括构成多个单元行和多个单元列的电路单元，至少一个电路单元可以至少包括像素驱动电路，至少一个像素驱动电路可以包括存储电容和多个氧化物晶体管。发光结构层包括多个发光器件，至少一个发光器件可以包括阳极、有机发光层和阴极。
在示例性实施方式中，驱动电路层还包括多条沿着第一方向X延伸的第一初始信号线70、多条沿着第二方向Y延伸的第二初始信号线80以及多条沿着第二方向Y延伸的低压电源线90，第一方向X和第二方向Y交叉。第一初始信号线70被配置为向像素驱动电路提供初始电压信号，低压电源线90被配置为向发光器件的阴极提供低电源电压信号，第二初始信号线80与第一初始信号线70连接，使得沿着第一方向X延伸的第一初始信号线70和沿着第二方向Y延伸的第二初始信号线80构成网状连通结构。
在示例性实施方式中，第一初始信号线70可以包括沿着第一方向X间隔设置的多个初始子线41，至少一个电路单元中，第一方向X上相邻的初始子线41通过初始连接电极58相互连接，形成沿着第一方向X延伸的第一初始信号线70。
在示例性实施方式中，至少一个电路单元中，第二初始信号线80与初始连接电极58连接，由于初始连接电极58与初始子线41连接，因而实现了第 二初始信号线80与第一初始信号线70之间的连接。
在示例性实施方式中，驱动电路层可以包括多个导电层，初始子线41、初始连接电极58和第二初始信号线80可以设置在不同的导电层中，至少一个电路单元中，初始连接电极58通过过孔与初始子线41连接，第二初始信号线80通过过孔与初始连接电极58连接。
在示例性实施方式中，像素驱动电路的存储电容可以包括第一极板和第二极板，像素驱动电路的多个氧化物晶体管可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6。至少一个电路单元中，第一晶体管T1的第一极与第一初始信号线70连接，第一晶体管T1的第二极与存储电容50的第二极板和第六晶体管T6的第二极连接。第二晶体管T2的第一极与存储电容50的第一极板连接，第二晶体管T2的第二极与第三晶体管T3的第一极连接，第四晶体管T4的第一极与数据信号线63连接，第四晶体管T4的第二极与第三晶体管T3的第二极连接，第五晶体管T5的第一极与第一电源线62连接，第五晶体管T5的第二极与第三晶体管T3的第一极连接，第六晶体管T6的第一极与第三晶体管T3的第二极连接，第六晶体管T6的第二极与第一晶体管T1的第二极连接。
在示例性实施方式中，至少一个电路单元中，第一晶体管T1、第四晶体管T4和第六晶体管T6可以位于存储电容50第二方向Y的一侧，第二晶体管T2和第五晶体管T5可以位于存储电容50第二方向Y的反方向的一侧。
在示例性实施方式中，至少一个电路单元中，第四晶体管T4可以位于存储电容50第二方向Y的一侧，第六晶体管T6可以位于第四晶体管T4远离存储电容50的一侧，第一晶体管T1可以位于第六晶体管T6远离存储电容50的一侧，第二晶体管T2可以位于存储电容50第二方向Y的反方向的一侧，第五晶体管T5可以位于第二晶体管T2远离存储电容50的一侧。
在示例性实施方式中，驱动电路层还可以包括第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第一发光控制线34和第二发光控制线35，第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第一发光控制线34和第二发光控制线35的形状可以为沿着第一方向X延伸的直线状或者折线状。
在示例性实施方式中，第一晶体管T1至第六晶体管T6均包括顶栅电极和底栅电极。
在示例性实施方式中，第一扫描信号线31可以与第一晶体管T1的顶栅电极连接，第一扫描信号线31被配置为控制第一晶体管T1的导通和断开。第二扫描信号线32可以与第四晶体管T4的顶栅电极连接，第二扫描信号线32被配置为控制第四晶体管T4的导通和断开。第三扫描信号线33可以与第二晶体管T2的顶栅电极连接，第三扫描信号线33被配置为控制第二晶体管T2的导通和断开。第一发光控制线34可以与第六晶体管T6的顶栅电极连接，第一发光控制线34被配置为控制第六晶体管T6的导通和断开。第二发光控制线35可以与第五晶体管T5的顶栅电极连接。第二发光控制线35被配置为控制第五晶体管T5的导通和断开。
在示例性实施方式中，至少一个电路单元中，第二扫描信号线32可以位于存储电容50第二方向Y的一侧，第一发光控制线34可以位于第二扫描信号线32远离存储电容50的一侧，第一扫描信号线31可以位于第一发光控制线34远离存储电容50的一侧。第三扫描信号线33可以位于存储电容50第二方向Y的反方向的一侧，第二发光控制线35可以位于第三扫描信号线33远离存储电容50的一侧。
在示例性实施方式中，第一初始信号线70可以位于第一扫描信号线31远离存储电容50的一侧。
在示例性实施方式中，多个单元列可以至少包括第一单元列、第二单元列和第三单元列，第一单元列中多个电路单元的像素驱动电路与出射红色光线的红色发光器件连接，第二单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接，第三单元列中多个电路单元的像素驱动电路与出射蓝色光线的蓝色发光器件连接，低压电源线90可以设置在第一单元列和第二单元列中，第二初始信号线80可以设置在第三单元列中。例如，第n-1列和第n列可以分别为第一单元列和第二单元列，第n+1列可以为第三单元列，低压电源线90可以分别设置在第n-1列和第n列的电路单元中，第二初始信号线80可以设置在第n+1列的电路单元中。
在示例性实施方式中，驱动电路层可以至少包括沿着远离基底方向依次 设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层、第一平坦层和第四导电层，遮挡导电层可以至少包括多个氧化物晶体管的底栅电极，半导体层可以至少包括多个氧化物晶体管的有源层，第一导电层可以至少包括存储电容50的第一极板和多个氧化物晶体管的顶栅电极，第二导电层可以至少包括存储电容50的第二极板和第一初始信号线70，第三导电层可以至少包括多个氧化物晶体管的第一极和第二极，第四导电层可以至少包括第二初始信号线80和低压电源线90。
下面通过本示例性实施例显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多8种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，显示基板的制备过程可以包括如下操作。
(1)形成遮挡导电层图案。在示例性实施方式中，形成遮挡导电层图案可以包括：在基底上沉积遮挡薄膜，通过图案化工艺对遮挡薄膜进行图案化，在基底上形成遮挡导电层图案，如图6所示。
在示例性实施方式中，遮挡导电层图案可以至少包括：第一遮挡线11、第二遮挡线12、第三遮挡线13、第四遮挡线14、第五遮挡线15和遮挡电极 16。
在示例性实施方式中，第一遮挡线11、第二遮挡线12、第三遮挡线13、第四遮挡线14和第五遮挡线15的形状可以为沿着第一方向X延伸的直线状或者折线状。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。在示例性实施方式中，第二方向Y可以是从显示区域指向绑定区域的方向，第二方向Y的反方向可以是从绑定区域指向显示区域的方向。
在示例性实施方式中，第一遮挡线11可以位于遮挡电极16第二方向Y的一侧。第一遮挡线11被配置为对第一晶体管T1进行遮挡，减少光线对第一晶体管T1电学特性的影响，同时被配置作为第一晶体管T1的底栅电极。
在示例性实施方式中，第二遮挡线12可以位于遮挡电极16第二方向Y的一侧，且位于遮挡电极16与第一遮挡线11之间。第二遮挡线12靠近遮挡电极16的一侧设置有第四底栅电极12-1，第四底栅电极12-1被配置为对第四晶体管T4进行遮挡，减少光线对第四晶体管T4电学特性的影响，同时被配置作为第四晶体管T4的底栅电极。
在示例性实施方式中，第三遮挡线13可以位于遮挡电极16第二方向Y的反方向的一侧，使遮挡电极16位于第二遮挡线12和第三遮挡线13之间。第三遮挡线13靠近遮挡电极16的一侧设置有第二底栅电极13-1，第二底栅电极13-1被配置为对第二晶体管T2进行遮挡，减少光线对第二晶体管T2电学特性的影响，同时被配置作为第二晶体管T2的底栅电极。
在示例性实施方式中，第四遮挡线14可以位于第一遮挡线11与第二遮挡线12之间。第四遮挡线14被配置为对第六晶体管T6进行遮挡，减少光线对第六晶体管T6电学特性的影响，同时被配置作为第六晶体管T6的底栅电极。
在示例性实施方式中，第五遮挡线15可以位于第三遮挡线13远离遮挡 电极16的一侧。第五遮挡线15被配置为对第五晶体管T5进行遮挡，减少光线对第五晶体管T5电学特性的影响，同时被配置作为第五晶体管T5的底栅电极。
在示例性实施方式中，遮挡电极16的形状可以为沿着第二方向Y延伸的条形状。遮挡电极16被配置为对第三晶体管T3进行遮挡，减少光线对第三晶体管T3电学特性的影响，同时被配置作为第三晶体管T3的底栅电极。
在示例性实施方式中，遮挡电极16靠近第一遮挡线11的端部设置有遮挡连接块16-1，遮挡连接块16-1被配置为与后续形成的第五连接电极连接。
(2)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖遮挡导电层的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，如图7A和图7B所示，图7B为图7A中半导体层的平面示意图。
在示例性实施方式中，半导体层图案可以包括第一晶体管T1的第一有源层21至第六晶体管T6的第六有源层26，且第二有源层22、第三有源层23和第四有源层24为相互连接的一体结构，第一有源层21和第六有源层26为相互连接的一体结构。
在示例性实施方式中，在第二方向Y上，第一有源层21、第四有源层24和第六有源层26可以位于第三有源层23第二方向Y的一侧，第二有源层22和第五有源层25可以位于第三有源层23第二方向Y的反方向的一侧。
在示例性实施方式中，第一有源层21至第六有源层26的形状可以呈“I”字形状。第二有源层22和第四有源层24的形状可以为沿着第一反向X延伸的条形状，第三有源层23的形状可以为沿着第二方向Y延伸的条形状，第二有源层22的第一端与第三有源层23的一端连接，第二有源层22的第二端沿着第一方向X延伸，第四有源层24的第一端与第三有源层23的另一端连接，第四有源层24的第二端沿着第一方向X延伸，使得一体结构的第二有源层22、第三有源层23和第四有源层24构成“C”字形状。
在示例性实施方式中，第三有源层23在基底上的正投影可以位于遮挡电 极16在基底上的正投影的范围之内，使得第三晶体管T3的沟道区域可以被遮挡电极16有效遮挡。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层21的第二区21-2和第六有源层26的第二区26-2为相互连接的一体结构，即第一有源层21的第二区21-2可以作为第六有源层26的第二区26-2。第二有源层22的第二区22-2和第三有源层23的第一区23-1为相互连接的一体结构，即第二有源层22的第二区22-2可以作为第三有源层23的第一区23-1。第四有源层24的第二区24-2和第三有源层23的第二区23-2为相互连接的一体结构，即第四有源层24的第二区24-2可以作为第三有源层23的第一区23-1。第一有源层21的第一区21-1、第二有源层22的第一区22-1、第四有源层24的第一区24-1、第五有源层25的第一区25-1、第五有源层25的第二区25-2和第六有源层26的第一区26-1可以单独设置。
在示例性实施方式中，半导体层可以采用氧化物，第一晶体管T1至第六晶体管T6均为氧化物晶体管。在示例性实施方式中，半导体薄膜可以采用电子迁移率较高的氧化铟镓锌(IGZO)。半导体层的厚度可以约为20nm至40nm。例如，半导体层的厚度可以约为30nm左右。
(3)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图8A和图8B所示，图8B为图8A中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，第一导电层图案至少包括：第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第一发光控制线34、第二发光控制线35和存储电容的第一极板36。
在示例性实施方式中，第一极板36的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板36在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板36可以 同时作为存储电容的一个极板和第三晶体管T3(驱动晶体管)的顶栅电极，即第三晶体管T3的顶栅电极和存储电容的第一极板36为一体结构。
在示例性实施方式中，第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第一发光控制线34和第二发光控制线35的形状可以为沿着第一方向X延伸的直线状或者折线状。
在示例性实施方式中，第一扫描信号线31可以位于第一极板36第二方向Y的一侧，第一扫描信号线31与第一有源层相重叠的区域作为第一晶体管T1的顶栅电极，即第一扫描信号线31和第一晶体管T1的顶栅电极为相互连接的一体结构。
在示例性实施方式中，第一扫描信号线31在基底上的正投影可以位于第一遮挡线11在基底上的正投影的范围之内，使得第一晶体管T1的沟道区域可以被第一遮挡线11有效遮挡。
在示例性实施方式中，第二扫描信号线32可以位于第一极板36第二方向Y的一侧，且位于第一极板36与第一扫描信号线31之间。第二扫描信号线32靠近第一极板36的一侧连接有第四顶栅电极32-1，第四顶栅电极32-1在基底上的正投影与第四有源层在基底上的正投影至少部分交叠，第四顶栅电极32-1被配置作为第四晶体管T4的顶栅电极。
在示例性实施方式中，第二扫描信号线32在基底上的正投影可以位于第二遮挡线12在基底上的正投影的范围之内，第四顶栅电极32-1在基底上的正投影可以位于第四底栅电极12-1在基底上的正投影的范围之内，使得第四晶体管T4的沟道区域可以被第四底栅电极12-1有效遮挡。
在示例性实施方式中，第三扫描信号线33可以位于第一极板36第二方向Y的反方向的一侧，使第一极板36位于第二扫描信号线32和第三扫描信号线33之间。第三扫描信号线33靠近第一极板36的一侧连接有第二顶栅电极33-1，第二顶栅电极33-1在基底上的正投影与第二有源层在基底上的正投影至少部分交叠，第二顶栅电极33-1被配置作为第二晶体管T2的顶栅电极。
在示例性实施方式中，第三扫描信号线33在基底上的正投影可以位于第三遮挡线13在基底上的正投影的范围之内，第二顶栅电极33-1在基底上的正投影可以位于第二底栅电极13-1在基底上的正投影的范围之内，使得第二 晶体管T2的沟道区域可以被第二底栅电极13-1有效遮挡。
在示例性实施方式中，第一扫描信号线31和第三扫描信号线33可以传输相同的扫描信号，第一扫描信号线31和第三扫描信号线33连接相同的扫描信号源。
在示例性实施方式中，第一发光控制线34可以位于第二扫描信号线32远离第一极板36的一侧，可以位于第一扫描信号线31和第二扫描信号线32之间，第一发光控制线34与第六有源层相重叠的区域作为第六晶体管T6的顶栅电极，即第一发光控制线34和第六晶体管T6的顶栅电极为相互连接的一体结构。
在示例性实施方式中，第一发光控制线34在基底上的正投影可以位于第四遮挡线14在基底上的正投影的范围之内，使得第六晶体管T6的沟道区域可以被第四遮挡线14有效遮挡。
在示例性实施方式中，第二发光控制线35可以位于第三扫描信号线33远离第一极板36的一侧，第二发光控制线35与第五有源层相重叠的区域作为第五晶体管T5的顶栅电极，即第二发光控制线35和第五晶体管T5的顶栅电极为相互连接的一体结构。
在示例性实施方式中，第二发光控制线35在基底上的正投影可以位于第五遮挡线15在基底上的正投影的范围之内，使得第五晶体管T5的沟道区域可以被第五遮挡线15有效遮挡。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第六晶体管T6的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管T1至第六有源层的第一区和第二区均被导体化。
(4)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图9A和图9B所示，图9B为图9A中第二导电层的平面示意图。在示例性实施方式中，第二 导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：初始子线41和存储电容的第二极板42。
在示例性实施方式中，第二极板42的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板42在基底上的正投影与第一极板36在基底上的正投影至少部分交叠，第二极板42可以作为存储电容的另一个极板，第一极板36和第二极板42构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板42上设置有开口43，开口43的形状可以为矩形状，可以位于第二极板42的中部，使第二极板42形成环形结构。开口43暴露出覆盖第一极板36的第三绝缘层，且第一极板36在基底上的正投影包含开口43在基底上的正投影。在示例性实施方式中，开口43被配置为容置后续形成的第一过孔，第一过孔位于开口43内并暴露出第一极板36，使后续形成的第一晶体管T1的第二极与第一极板36连接。
在示例性实施方式中，初始子线41的形状可以为主体部分沿着第一方向X延伸的线形状。在第一方向X上，初始子线41可以设置在第一方向X上相邻电路单元的第一有源层的第一区之间。在第二方向Y上，初始子线41可以位于第一扫描信号线31远离第二极板42的一侧。初始子线41被配置为利用后续形成的初始连接电极构成传输初始电压信号且沿着第一方向X延伸的第一初始信号线。
(5)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔，如图10所示。
在示例性实施方式中，多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12和第十三过孔V13。
在示例性实施方式中，第一过孔V1在基底上的正投影位于开口43在基 底上的正投影的范围之内，第一过孔V1内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板36的表面，第一过孔V1配置为使后续形成的第一晶体管T1的第二极通过该过孔与第一极板36连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区(也是第六有源层的第二区)在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第二过孔V2被配置为使后续形成的第一晶体管T1的第二极(也是第六晶体管T6的第二极)通过该过孔与第一有源层的第二区(也是第六有源层的第二区)连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第三过孔V3被配置为使后续形成的第五晶体管T5的第一极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第五有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第二区的表面，第四过孔V4被配置为使后续形成的第五晶体管T5的第二极通过该过孔与第五有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第二有源层的第二区(也是第三有源层的第一区)在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第五过孔V5被配置为使后续形成的第二晶体管T2的第二极(也是第三晶体管T3的第一极)通过该过孔与第二有源层的第二区的第二区(也是第三有源层的第一区)连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第六过孔V6被配置为使后续形成的第四晶体管T4的第一极通过该过孔与第四有 源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第四有源层的第二区(也是第三有源层的第二区)在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区的表面，第七过孔V7被配置为使后续形成的第四晶体管T4的第二极(也是第三晶体管T3的第二极)通过该过孔与第四有源层的第二区(也是第三有源层的第二区)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第六有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第一区的表面，第八过孔V8被配置为使后续形成的第六晶体管T6的第一极通过该过孔与第六有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第二有源层的第一区在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第二有源层的第一区的表面，第九过孔V9被配置为使后续形成的第二晶体管T2的第一极通过该过孔与第二有源层的第一区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于遮挡电极16的遮挡连接块16-1在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层、第三绝缘层、第二绝缘层和第一绝缘层被刻蚀掉，暴露出遮挡连接块16-1的表面，第十过孔V10被配置为使后续形成的第五连接电极通过该过孔与遮挡电极16连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第二极板42在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层被刻蚀掉，暴露出第二极板42的表面，第十一过孔V11被配置为使后续形成的第七连接电极通过该过孔与第二极板42连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第十二过孔V12内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第 十二过孔V12被配置为使后续形成的第一晶体管T1的第一极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于初始子线41靠近第一有源层的第一区的端部在基底上的正投影的范围之内，第十三过孔V13内的第四绝缘层被刻蚀掉，暴露出初始子线41的端部的表面，第十三过孔V13被配置为使后续形成的第一晶体管T1的第一极通过该过孔与初始子线41连接。
(6)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图11A和图11B所示，图11B为图11A中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个电路单元的第三导电层至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第七连接电极57和初始连接电极58。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的折线状，第一连接电极51的第一端通过第一过孔V1与第一极板36连接，第一连接电极51的第二端通过第九过孔V9与第二有源层的第一区连接，使第一极板36和第二晶体管T2的第一极具有相同的电位。在示例性实施方式中，第一连接电极51可以作为第二晶体管T2的第一极(即像素驱动电路的第一节点N1)。
在示例性实施方式中，第二连接电极52的形状可以为多边形状，第二连接电极52通过第三过孔V3与第五有源层的第一区连接。在示例性实施方式中，第二连接电极52可以作为第五晶体管T5的第一极，第二连接电极52被配置为与后续形成的第一电源线连接。
在示例性实施方式中，第三连接电极53的形状可以为主体部分沿着第二方向Y延伸的条形状，第三连接电极53的第一端通过第四过孔V4与第五有源层的第二区连接，第三连接电极53的第二端通过第五过孔V5与第二有源层的第二区连接。在示例性实施方式中，第三连接电极53可以同时作为第二 晶体管T2的第二极、第三晶体管T3的第一极和第五晶体管T5的第二极(即像素驱动电路的第二节点N2)。
在示例性实施方式中，第四连接电极54的形状可以为多边形状，第四连接电极54通过第六过孔V6与第四有源层的第一区连接。在示例性实施方式中，第四连接电极54可以作为第四晶体管T4的第一极，第四连接电极54被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第五连接电极55的形状可以为“L”字形状，第五连接电极55的第一端通过第八过孔V8与第六有源层的第一区连接，第五连接电极55的第二端通过第十过孔V10与遮挡电极16的遮挡连接块16-1连接，第五连接电极55的第三端通过第七过孔V7与第四有源层的第二区连接，第五连接电极55的第三端位于第一端与第二端之间。在示例性实施方式中，第五连接电极55可以同时作为第三晶体管T3的第二极、第四晶体管T4的第二极和第六晶体管T6的第一极(即像素驱动电路的第三节点N3)。由于遮挡电极16作为第三晶体管T3的底栅电极，因而实现了第三晶体管T3的底栅电极通过第五连接电极55与第四晶体管T4的第二极和第六晶体管T6的第一极的连接。
在示例性实施方式中，第六连接电极56的形状可以为多边形状，第六连接电极56通过第二过孔V2与第一有源层的第二区(也是第六有源层的第二区)连接。在示例性实施方式中，第六连接电极56可以同时作为第一晶体管T1的第二极和第六晶体管T6的第二极，第六连接电极56被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第七连接电极57的形状可以为多边形状，第七连接电极57通过第十一过孔V11与第二极板42连接。在示例性实施方式中，第七连接电极57被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，初始连接电极58的形状可以为主体部分沿着第一方向X延伸的条形状，初始连接电极58的中部通过第十二过孔V12与第一有源层的第一区连接，初始连接电极58的两端分别通过第十三过孔V13与相邻的初始子线41的端部连接，一方面实现了多条初始子线41之间的相互连接，形成第一初始信号线，另一方面实现了第一初始信号线与第一晶体管 T1的第一极的连接，使第一初始信号线传输的初始电压写入第一晶体管T1的第一极。
(7)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，先沉积第五绝缘薄膜，然后涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜和第五绝缘薄膜进行图案化，形成覆盖第三导电层图案的第五绝缘层以及设置在第五绝缘层上的第一平坦层，第一平坦层上设置有多个过孔，如图12所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第二十一过孔V21、第二十二过孔V22、第二十三过孔V23和第二十四过孔V24。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第二连接电极52在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第二连接电极52的表面，第二十一过孔V21被配置为使后续形成的第一电源线通过该过孔与第二连接电极52连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第四连接电极54在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第四连接电极54的表面，第二十二过孔V22被配置为使后续形成的数据信号线通过该过孔与第四连接电极54连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第六连接电极56的表面，第二十三过孔V23被配置为使后续形成的阳极连接电极通过该过孔与第六连接电极56连接。
在示例性实施方式中，第二十四过孔V24在基底上的正投影位于第七连接电极57在基底上的正投影的范围之内，第二十四过孔V24内的第一平坦层和第五绝缘层被刻蚀掉，暴露出第七连接电极57的表面，第二十四过孔V24被配置为使后续形成的阳极连接电极通过该过孔与第七连接电极57连接。
在示例性实施方式中，部分电路单元还包括第二十五过孔V25，第二十五过孔V25在基底上的正投影与初始连接电极58在基底上的正投影至少部 分交叠，第二十五过孔V25内的第一平坦层和第五绝缘层被刻蚀掉，暴露出初始连接电极58的表面，第二十五过孔V25被配置为使后续形成的第二初始信号线通过该过孔与初始连接电极58连接。
在示例性实施方式中，第二十五过孔V25可以设置在第n+1列的电路单元，即第n+1列的电路单元中设置有第二初始信号线，而第n-1列和第n列中的电路单元没有设置第二十五过孔V25。
(8)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图13A和图13B所示，图13B为图13A中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，每个电路单元的第四导电层至少包括：阳极连接电极61、第一电源线62和数据信号线63。
在示例性实施方式中，阳极连接电极61的形状可以为主体部分沿着第二方向Y延伸的折线状，阳极连接电极61的第一端通过第二十三过孔V23与第六连接电极56连接，阳极连接电极61的第二端通过第二十四过孔V24与第七连接电极57连接。由于第六连接电极56通过过孔与第六有源层的第二区(也是第一有源层的第二区)连接，第七连接电极57通过过孔与第二极板42连接，因而实现了第二极板42、第一晶体管T1的第二极和第六晶体管T6的第二极具有相同的电位(即像素驱动电路的第四节点N4)。在示例性实施方式中，阳极连接电极61被配置为与后续形成的阳极连接，因而可以实现像素驱动电路向发光器件输出驱动电流。
在示例性实施方式中，第一电源线62的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一电源线62通过第二十一过孔V21与第二连接电极52连接。由于第二连接电极52通过过孔与第五有源层的第一区连接，因而实现了第一电源线62可以将恒定的第一电压信号写入第五晶体管T5的第一极。
在示例性实施方式中，数据信号线63的形状可以为主体部分沿着第二方向Y延伸的直线状，数据信号线63通过第二十二过孔V22与第四连接电极 54连接。由于第四连接电极54通过过孔与第四有源层的第一区连接，因而实现了数据信号线63可以将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，部分电路单元的第四导电层还可以包括第二初始信号线80。第二初始信号线80的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第二初始信号线80通过第二十五过孔V25与初始连接电极58连接。由于初始子线41通过初始连接电极58构成沿着第一方向X延伸的第一初始信号线，第二初始信号线80与初始连接电极58连接，使得沿着第一方向X延伸的第一初始信号线和沿着第二方向Y延伸的第二初始信号线80在显示区域构成网络连通结构的初始信号线，可以最大限度地降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，部分电路单元的第四导电层还可以包括低压电源线(第二电源线)90。低压电源线90的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，可以位于第一电源线62和数据信号线63之间，低压电源线90被配置为向发光器件的阴极输出恒定的第二电压信号。
在一些示例性实施方式中，显示面板的多个单元列可以至少包括第一单元列、第二单元列和第三单元列，第一单元列中多个电路单元的像素驱动电路与出射红色光线的红色发光器件连接，第二单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接，第三单元列中多个电路单元的像素驱动电路与出射蓝色光线的蓝色发光器件连接。例如，第n-1列可以为第一单元列，第n列可以为第二单元列，第n+1列可以为第三单元列，低压电源线90可以设置在第n-1列和第n列中的电路单元中，第二初始信号线80可以设置在第n+1列的电路单元中。
在一些可能示例性实施方式中，第二初始信号线80可以设置在第n列和第n+1列的电路单元中，低压电源线90可以设置在第n-1列中的电路单元中，本公开在此不做限定。
随后，在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第四导电层图案的第二平坦层，第二平坦层上设置有阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在 基底上的正投影的范围之内，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第一发光控制线、第二发光控制线、第一初始信号线、第一电源线和数据信号线。在垂直于显示基板的平面内，所述驱动电路层可以包括在基底上依次设置的遮挡导电层、第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第五绝缘层、第一平坦层、第四导电层和第二平坦层。遮挡导电层可以至少包括遮挡电极和多条遮挡线，半导体层可以至少包括第一晶体管至第六晶体管的有源层，第一导电层可以至少包括存储电容的第一极板，第二导电层可以至少包括存储电容的第二极板，第三导电层可以至少包括第一晶体管至第六晶体管的第一极和第二极，第四导电层可以至少包括阳极连接电极。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层，第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层和第三绝缘层可以称为栅绝缘(GI) 层，第四绝缘层可以称为层间绝缘(ILD)层，第五绝缘层可以称为钝化(PVX)层。遮挡导电层、第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)或钼(Mo)等，或者可以采用由金属组成的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，可以是单层结构，或者可以是多层复合结构，如Ti/Al/Ti等。第一平坦层和第二平坦层可以采用有机材料，如树脂或聚酰亚胺。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上制备发光结构层，在发光结构层上制备封装结构层，这里不再赘述。
从以上描述的显示基板的结构以及制备过程可以看出，本示例性实施例的像素驱动电路采用6个氧化物晶体管即可满足驱动要求，与现有7个晶体管的像素驱动电路结构相比，不仅减少了晶体管的数量，简化了像素驱动电路结构的结构，减少了像素驱动电路的占用面积，有利于实现高分辨率(PPI)显示，而且可以保证大尺寸显示基板的良率，降低生产成本。本示例性实施例底栅电极设置在遮挡导电层，顶栅电极设置在第一导电层，可以保证遮挡效果，可以提高晶体管的电学性能。本公开通过在显示区域内设置沿着第一方向X延伸的第一初始信号线和沿着第二方向Y延伸的第二初始信号线，在显示区域构成网络连通结构的初始信号线，可以最大限度地降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开通过在显示区域内设置低压电源线，实现了VSS in pixel的结构，不仅有效降低低压电源线的电阻，有效降低低压电源信号的压降，实现低功耗，而且可以有效提升显示基板中第低压电源信号的均一性，有效提升了显示均一性，提高了显示品质和显示质量。本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。例如，显示基板可以包括两条沿着第一方向延伸的第一初始信号线(如第一水平初始线和第二水平初始线)以及两条沿着第二方向延伸的第二初始信号线(如第一竖直初始线和第二竖直初始线)，至少一个电 路单元中，第一水平初始线与第一竖直初始线可以通过过孔连接，第二水平初始线与第二竖直初始线可以通过过孔连接，在显示区域构成双网络连通结构的初始信号线。又如，显示基板可以包括沿着第一方向延伸的第一低压电源线和沿着第二方向延伸的第二低压电源线，至少一个电路单元中，第一低压电源线和第二低压电源线通过过孔连接，在显示区域构成网络连通结构的低压电源线。
图14为本公开示例性实施例另一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图14所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的第一电源线62上设置有第一遮挡块101。
在示例性实施方式中，第一遮挡块101可以设置在第一电源线62第一方向X(靠近数据信号线63)的一侧，相当于在第一电源线62上设置凸起，第一遮挡块101在基底上的正投影与第五晶体管T5的第五有源层在基底上的正投影至少部分交叠，第一遮挡块101被配置为对第五晶体管T5进行遮挡，减少光线对第五晶体管T5电学特性的影响，提高第五晶体管T5的工作稳定性。
在示例性实施方式中，第一遮挡块101和第一电源线62可以为相互连接的一体结构，第一遮挡块101在基底上的正投影与第五有源层的沟道区在基底上的正投影至少部分交叠。
图15为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图15所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的第二初始信号线80和/或低压电源线90上设置有第二遮挡块102。
在示例性实施方式中，第二遮挡块102可以设置在第二初始信号线80和/或低压电源线90第一方向X的反方向(靠近第一电源线62)的一侧，相当于在第二初始信号线80和/或低压电源线90上设置凸起，第二遮挡块102在基底上的正投影与第二晶体管T2的第二有源层在基底上的正投影至少部 分交叠，第二遮挡块102被配置为对第二晶体管T2进行遮挡，减少光线对第二晶体管T2电学特性的影响，提高第二晶体管T2的工作稳定性。
在示例性实施方式中，部分电路单元的第二遮挡块102和第二初始信号线80可以为相互连接的一体结构，部分电路单元的第二遮挡块102和低压电源线90可以为相互连接的一体结构，第二遮挡块102在基底上的正投影与第二有源层的沟道区在基底上的正投影至少部分交叠。
图16为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图16所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的第二初始信号线80和/或低压电源线90上设置有第三遮挡块103。
在示例性实施方式中，第三遮挡块103可以设置在第二初始信号线80和/或低压电源线90第一方向X的反方向(靠近第一电源线62)的一侧，相当于在第二初始信号线80和/或低压电源线90上设置凸起，第三遮挡块103在基底上的正投影与第四晶体管T4的第四有源层在基底上的正投影至少部分交叠，第三遮挡块103被配置为对第四晶体管T4进行遮挡，减少光线对第四晶体管T4电学特性的影响，提高第四晶体管T4的工作稳定性。
在示例性实施方式中，部分电路单元的第三遮挡块103和第二初始信号线80可以为相互连接的一体结构，部分电路单元的第三遮挡块103和低压电源线90可以为相互连接的一体结构，第三遮挡块103在基底上的正投影与第四有源层的沟道区在基底上的正投影至少部分交叠。
图17为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图17所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的第二初始信号线80和/或低压电源线90上设置有第四遮挡块104。
在示例性实施方式中，第四遮挡块104可以设置在第二初始信号线80和/或低压电源线90第一方向X的反方向(靠近第一电源线62)的一侧，相当于在第二初始信号线80和/或低压电源线90上设置凸起，第四遮挡块104 在基底上的正投影与第一晶体管T1的第一有源层在基底上的正投影至少部分交叠，第四遮挡块104被配置为对第一晶体管T1进行遮挡，减少光线对第一晶体管T1电学特性的影响，提高第一晶体管T1的工作稳定性。
在示例性实施方式中，部分电路单元的第四遮挡块104和第二初始信号线80可以为相互连接的一体结构，部分电路单元的第四遮挡块104和低压电源线90可以为相互连接的一体结构，第四遮挡块104在基底上的正投影与第一有源层的沟道区在基底上的正投影至少部分交叠。
在一些示例性实施方式中，第四遮挡块104可以设置在第一电源线62靠近第一晶体管T1的位置，相当于在第一电源线62上设置凸起，实现对第一晶体管T1的遮挡。
在另一些示例性实施方式中，可以根据电路单元的布局情况，部分电路单元的第四遮挡块104设置在第一电源线62上，部分电路单元的第四遮挡块104设置在第二初始信号线80，部分电路单元的第四遮挡块104设置在低压电源线90，本公开在此不做限定。
图18为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图18所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的阳极连接电极61上设置有第五遮挡块105。
在示例性实施方式中，第五遮挡块105可以设置在阳极连接电极61第一方向X(靠近数据信号线63)的一侧，相当于增加阳极连接电极61的尺寸，第五遮挡块105在基底上的正投影与第六晶体管T6的第六有源层在基底上的正投影至少部分交叠，第五遮挡块105被配置为对第六晶体管T6进行遮挡，减少光线对第六晶体管T6电学特性的影响，提高第六晶体管T6的工作稳定性。
在示例性实施方式中，第五遮挡块105和阳极连接电极61可以为相互连接的一体结构，第五遮挡块105在基底上的正投影与第六有源层的沟道区在基底上的正投影至少部分交叠。
图19为本公开示例性实施例又一种显示基板的平面结构示意图，示意了 一个单元行中三个电路单元中像素驱动电路的平面结构。如图19所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的第一电源线62上设置有屏蔽块111。
在示例性实施方式中，屏蔽块111可以设置在第一电源线62第一方向X(靠近数据信号线63)的一侧，相当于在第一电源线62上设置凸起，屏蔽块111在基底上的正投影与存储电容50的第二极板在基底上的正投影至少部分交叠，屏蔽块111被配置为对像素驱动电路的第四节点N4进行屏蔽，以稳定阳极电位。
在示例性实施方式中，屏蔽块111和第一电源线62可以为相互连接的一体结构。
图20为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图20所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的第二初始信号线80可以包括第一初始直线部80A、第二初始直线部80B以及位于第一初始直线部80A和第二初始直线部80B之间的初始弯折部80C，和/或，低压电源线90可以包括第一电源直线部90A、第二电源直线部90B以及位于第一电源直线部90A和第二电源直线部90B之间的电源弯折部90C。
在示例性实施方式中，初始弯折部80C的第一端与第一初始直线部80A连接，初始弯折部80C的第二端与第二初始直线部80B连接，初始弯折部80C的中部向着靠近第一电源线62的方向凸起，使第二初始信号线80在基底上的正投影与第一连接电极51(像素驱动电路的第一节点N1)在基底上的正投影没有交叠，第二初始信号线80的初始弯折部80C被配置为避让像素驱动电路的第一节点N1，以减少第一节点N1的分压，提高像素驱动电路关键节点的电位稳定性。
在示例性实施方式中，电源弯折部90C的第一端与第一电源直线部90A连接，电源弯折部90C的第二端与第二电源直线部90B连接，电源弯折部 90C的中部向着靠近第一电源线62的方向凸起，使低压电源线90在基底上的正投影与第一连接电极51(像素驱动电路的第一节点N1)在基底上的正投影没有交叠，低压电源线90的电源弯折部90C被配置为避让像素驱动电路的第一节点N1，以减少第一节点N1的分压，提高像素驱动电路关键节点的电位稳定性。
图21为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图21所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，在形成第二导电层时形成完整的第一初始信号线70。
在示例性实施方式中，第一初始信号线70的形状可以为主体部分沿着第一方向X延伸的折线状，且相邻电路单元的第一初始信号线70相互连接。
在示例性实施方式中，第一初始信号线70可以包括初始直线部70A和初始避让部70B。初始直线部70A的形状可以为沿着第一方向X延伸的线形状，可以设置在第一方向X上相邻的第一有源层之间。初始避让部70B第一方向X的两端分别与初始直线部70A连接，初始避让部70B的中部向着远离第一有源层的方向凸起，使初始避让部70B在基底上的正投影与第一有源层在基底上的正投影没有交叠。
在示例性实施方式中，初始直线部70A和初始避让部70B可以为相互连接的一体结构，形成完整的第一初始信号线70。由于在形成第二导电层时形成了完整的第一初始信号线70，因而后续工艺可以节省相应的过孔以及初始连接电极，降低工艺难度。
图22为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图22所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的阳极连接电极61上设置有第一电容块121。
在示例性实施方式中，第一电容块121可以设置在阳极连接电极61第一方向X(靠近数据信号线63)的一侧，或者，可以设置在阳极连接电极61 第一方向X的反方向(靠近第一电源线62)的一侧，或者，可以设置在阳极连接电极61第一方向X的两侧，第一电容块121在基底上的正投影与第二扫描信号线32在基底上的正投影至少部分交叠，第一电容块121被配置为增加阳极连接电极61(像素驱动电路的第四节点N4)与第二扫描信号线32之间的寄生电容。
在示例性实施方式中，通过增加像素驱动电路的第四节点N4与第二扫描信号线32之间的寄生电容，在数据写入完成后，发光元件发光之前，使得第二扫描信号线32上信号的下降沿可以拉低第四节点N4的电位，增强黑画面显示效果。
在示例性实施方式中，通过设置有第一电容块121，使得阳极连接电极61与第二扫描信号线32之间的寄生电容，大于阳极连接电极61与第一发光控制线34之间的寄生电容。
在示例性实施方式中，第一电容块121和阳极连接电极61可以为相互连接的一体结构。
图23为本公开示例性实施例又一种显示基板的平面结构示意图，示意了一个单元行中三个电路单元中像素驱动电路的平面结构。如图23所示，在示例性实施方式中，本示例性实施例显示基板的主体结构与图5所示显示基板的主体结构基本上相同，所不同的是，至少一个电路单元中，第四导电层中的阳极连接电极61上设置有第二电容块122。
在示例性实施方式中，第二电容块122可以设置在阳极连接电极61第一方向X(靠近数据信号线63)的一侧，或者，可以设置在阳极连接电极61第一方向X的反方向(靠近第一电源线62)的一侧，或者，可以设置在阳极连接电极61第一方向X的两侧，第二电容块122在基底上的正投影与第一扫描信号线31在基底上的正投影至少部分交叠，第二电容块122被配置为增加阳极连接电极61(像素驱动电路的第四节点N4)与第一扫描信号线31之间的寄生电容。
在示例性实施方式中，通过增加像素驱动电路的第四节点N4与第一扫描信号线31之间的寄生电容，在数据写入完成后，发光元件发光之前，可以拉低第四节点N4的电位，增强黑画面显示效果。
在示例性实施方式中，通过设置有第二电容块122，使得阳极连接电极61与第一扫描信号线31之间的寄生电容，大于阳极连接电极61与第一发光控制线34之间的寄生电容。
在示例性实施方式中，第二电容块122和阳极连接电极61可以为相互连接的一体结构。
在示例性实施方式中，图14至图23所示方案及方案中的结构可以相互任意组合，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述制备方法可以包括：
在基底上形成驱动电路层，所述驱动电路层包括构成多个单元行和多个单元列的多个电路单元、多条沿着第一方向延伸的第一初始信号线、以及多条沿着第二方向延伸的第二初始信号线和低压电源线，所述第一方向和所述第二方向交叉，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述第一初始信号线被配置为向所述像素驱动电路提供初始电压信号，所述第二初始信号线与所述第一初始信号线连接，所述第一初始信号线和所述第二初始信号线构成网状连通结构；
在所述驱动电路层上形成发光结构层，所述发光结构层包括多个发光器件，所述低压电源线被配置为向所述发光器件提供低电源电压信号。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (18)

  1. 一种显示基板，包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层，所述驱动电路层包括构成多个单元行和多个单元列的多个电路单元、多条沿着第一方向延伸的第一初始信号线、以及多条沿着第二方向延伸的第二初始信号线和低压电源线，所述第一方向和所述第二方向交叉，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述发光结构层包括多个发光器件，所述第一初始信号线被配置为向所述像素驱动电路提供初始电压信号，所述低压电源线被配置为向所述发光器件提供低电源电压信号，所述第二初始信号线与所述第一初始信号线连接，所述第一初始信号线和所述第二初始信号线构成网状连通结构。
  2. 根据权利要求2所述的显示基板，其中，所述第一初始信号线包括沿着所述第一方向间隔设置的多个初始子线，至少一个电路单元中，在所述第一方向相邻的所述初始子线通过初始连接电极相互连接。
  3. 根据权利要求2所述的显示基板，其中，所述驱动电路层包括多个导电层，所述初始子线和所述初始连接电极设置在不同的导电层中，至少一个电路单元中，所述初始连接电极通过过孔与所述初始子线连接。
  4. 根据权利要求2所述的显示基板，其中，至少一个电路单元中，所述第二初始信号线与所述初始连接电极连接。
  5. 根据权利要求4所述的显示基板，其中，所述驱动电路层包括多个导电层，所述初始连接电极和所述第二初始信号线设置在不同的导电层中，至少一个电路单元中，所述第二初始信号线通过过孔与所述初始连接电极连接。
  6. 根据权利要求1所述的显示基板，其中，所述像素驱动电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管，至少一个电路单元中，所述第一晶体管的第一极与所述第一初始信号线连接，所述第一晶体管的第二极与所述存储电容的第二极板和所述第六晶体管的第二极连接，所述第二晶体管的第一极与所述存储电容的第一极板连接， 所述第二晶体管的第二极与所述第三晶体管的第一极连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第三晶体管的第二极连接，所述第五晶体管的第一极与第一电源线连接，所述第五晶体管的第二极与所述第三晶体管的第一极连接，所述第六晶体管的第一极与所述第三晶体管的第二极连接，所述第六晶体管的第二极与所述发光器件连接。
  7. 根据权利要求6所述的显示基板，其中，至少一个电路单元中，所述第一晶体管、第四晶体管和第六晶体管设置在所述存储电容所述第二方向的一侧，所述第二晶体管和第五晶体管设置在所述存储电容所述第二方向的反方向的一侧。
  8. 根据权利要求7所述的显示基板，其中，至少一个电路单元中，所述第四晶体管设置在所述存储电容所述第二方向的一侧，所述第六晶体管设置在所述第四晶体管远离所述存储电容的一侧，所述第一晶体管设置在所述第六晶体管远离所述存储电容的一侧，所述第二晶体管设置在所述存储电容所述第二方向的反方向的一侧，所述第五晶体管设置在所述第二晶体管远离所述存储电容的一侧。
  9. 根据权利要求6所述的显示基板，其中，至少一个电路单元中，所述第一晶体管至少包括第一有源层，所述第六晶体管至少包括第六有源层，所述第一有源层的第二区和所述第六有源层的第一区为相互连接的一体结构。
  10. 根据权利要求6所述的显示基板，其中，至少一个电路单元中，所述第二晶体管至少包括第二有源层，所述第三晶体管至少包括第三有源层，所述第四晶体管至少包括第四有源层，所述第二有源层和第四有源层的形状为沿着所述第一方向延伸的条形状，所述第三有源层的形状为沿着所述第二方向延伸的条形状，所述第三有源层的第一区和所述第二有源层的第二区为相互连接的一体结构，所述第三有源层的第二区和所述第四有源层的第二区为相互连接的一体结构。
  11. 根据权利要求6所述的显示基板，其中，至少一个电路单元中，所述第三晶体管至少包括底栅电极和顶栅电极，所述底栅电极分别与所述第四晶体管的第二极和所述第六晶体管的第一极连接，所述顶栅电极和所述存储电容的第一极板为一体结构。
  12. 根据权利要求6所述的显示基板，其中，所述驱动电路层还包括沿着所述第一方向延伸的第一扫描信号线、第二扫描信号线、第三扫描信号线、第一发光控制线和第二发光控制线，至少一个电路单元中，所述第一扫描信号线与所述第一晶体管的顶栅电极连接，所述第二扫描信号线与所述第四晶体管的顶栅电极连接，所述第三扫描信号线与所述第二晶体管的顶栅电极连接，所述第一发光控制线与所述第六晶体管的顶栅电极连接，所述第二发光控制线与所述第五晶体管的顶栅电极连接。
  13. 根据权利要求12所述的显示基板，其中，至少一个电路单元中，所述第二扫描信号线位于所述存储电容所述第二方向的一侧，所述第一发光控制线位于所述第二扫描信号线远离所述存储电容的一侧，所述第一扫描信号线位于所述第一发光控制线远离所述存储电容的一侧，所述第三扫描信号线位于所述存储电容所述第二方向的反方向的一侧，所述第二发光控制线位于所述第三扫描信号线远离所述存储电容的一侧。
  14. 根据权利要求13所述的显示基板，其中，至少一个电路单元中，所述第一初始信号线设置在所述第一扫描信号线远离所述存储电容的一侧。
  15. 根据权利要求1至14任一项所述的显示基板，其中，所述驱动电路层至少包括沿着远离所述基底方向依次设置的遮挡导电层、第一导电层、第二导电层、第三导电层和第四导电层，所述遮挡导电层至少包括多个氧化物晶体管的底栅电极，所述第一导电层至少包括所述存储电容的第一极板和多个氧化物晶体管的顶栅电极，所述第二导电层至少包括所述存储电容的第二极板和所述第一初始信号线，所述第三导电层至少包括多个氧化物晶体管的第一极和第二极，所述第四导电层至少包括所述第二初始信号线和低压电源线。
  16. 根据权利要求1至14任一项所述的显示基板，其中，所述多个单元列至少包括第一单元列、第二单元列和第三单元列，所述第一单元列中多个电路单元的像素驱动电路与出射红色光线的红色发光器件连接，所述第二单元列中多个电路单元的像素驱动电路与出射绿色光线的绿色发光器件连接，所述第三单元列中多个电路单元的像素驱动电路与出射蓝色光线的蓝色发光器件连接，所述低压电源线设置在所述第一单元列和第二单元列中，所述第 二初始信号线设置在所述第三单元列中。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，包括：
    在基底上形成驱动电路层，所述驱动电路层包括构成多个单元行和多个单元列的多个电路单元、多条沿着第一方向延伸的第一初始信号线、以及多条沿着第二方向延伸的第二初始信号线和低压电源线，所述第一方向和所述第二方向交叉，所述电路单元至少包括像素驱动电路，所述像素驱动电路包括存储电容和多个氧化物晶体管，所述第一初始信号线被配置为向所述像素驱动电路提供初始电压信号，所述第二初始信号线与所述第一初始信号线连接，所述第一初始信号线和所述第二初始信号线构成网状连通结构；
    在所述驱动电路层上形成发光结构层，所述发光结构层包括多个发光器件，所述低压电源线被配置为向所述发光器件提供低电源电压信号。
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