WO2022165717A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2022165717A1
WO2022165717A1 PCT/CN2021/075301 CN2021075301W WO2022165717A1 WO 2022165717 A1 WO2022165717 A1 WO 2022165717A1 CN 2021075301 W CN2021075301 W CN 2021075301W WO 2022165717 A1 WO2022165717 A1 WO 2022165717A1
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WIPO (PCT)
Prior art keywords
transistor
sub
layer
stage
line
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PCT/CN2021/075301
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English (en)
French (fr)
Inventor
韩龙
刘利宾
皇甫鲁江
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112021002459.0T priority Critical patent/DE112021002459T5/de
Priority to US17/630,211 priority patent/US20230180550A1/en
Priority to PCT/CN2021/075301 priority patent/WO2022165717A1/zh
Priority to CN202180000155.3A priority patent/CN115398631A/zh
Publication of WO2022165717A1 publication Critical patent/WO2022165717A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a display device.
  • OLED Organic Light Emitting Diode
  • Organic Light Emitting Diode Organic Light Emitting Diode
  • the purpose of the present disclosure is to provide an array substrate and a display device.
  • an array substrate wherein a plurality of pixel units are arranged in an array, the pixel units include a plurality of sub-pixels, and the array substrate includes:
  • a plurality of initialization signal lines which are arranged on the first conductive layer on the base substrate, extend along the first direction and are arranged at intervals along the second direction, and are used to provide initialization signals to each of the sub-pixels; the first direction and the second direction two directions intersect;
  • a plurality of connecting lines arranged on the second conductive layer on the base substrate, extending along the second direction and arranged at intervals along the first direction;
  • first conductive layer and the second conductive layer are the same layer or different layers;
  • the projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate are both intersected and electrically connected, so that the initialization signal lines and the connection lines are on the base substrate
  • the projections form a grid-like structure.
  • the array substrate includes a base substrate and a first source-drain layer, a second source-drain layer, and an anode layer that are sequentially stacked on the base substrate;
  • the first conductive layer and the second conductive layer at least any one is the first source and drain layer, and the other is the first source and drain layer or the anode layer;
  • the first direction is the row direction
  • the second direction is the column direction;
  • the array substrate further includes:
  • data lines disposed on the second source and drain layers, extending along the column direction and spaced along the row direction, and used for providing data signals to each of the sub-pixels;
  • the power lines are arranged on the second source and drain layers, extend along the column direction and are arranged at intervals along the row direction, and are used for supplying power signals to each of the sub-pixels.
  • the first conductive layer and the second conductive layer are both the first source and drain layers
  • the initialization signal line extends along a row direction
  • the connection line extends along a column direction extending in the direction
  • each of the initialization signal lines is connected to each of the connection lines and crossed in a grid shape.
  • the first conductive layer is a first source-drain layer
  • the second conductive layer is an anode layer
  • the initialization signal line is provided on the first source-drain layer layer, extending along the row direction and spaced along the column direction
  • the connection lines are provided on the anode layer, extending along the column direction and spaced along the row direction; each of the initialization signal lines
  • Each of the connection lines is electrically connected through a via hole, and the projections of the plurality of initialization signal lines and the plurality of connection lines on the base substrate are in a grid shape.
  • the first conductive layer is an anode layer
  • the second conductive layer is a first source-drain layer
  • the initialization signal line is provided on the anode layer, along the extending in the row direction and arranged at intervals along the column direction
  • the connection lines are arranged on the first source and drain layers, extending along the column direction and arranged at intervals along the row direction
  • each of the initialization signal lines It is electrically connected to each of the connection lines through via holes, and the projections of the plurality of initialization signal lines and the plurality of connection lines on the base substrate are in a grid shape.
  • a plurality of seventh conductive connection parts are further provided on the second source and drain layers, and the seventh conductive connection parts are arranged between the initialization signal line and the connection line The sub-pixel area where the projected intersection is located;
  • the seventh conductive connection part is connected with the initialization signal line through a via hole, and the seventh conductive connection part is connected with the connection line through another via hole, so that the initialization signal line and the connection line pass through the seventh conductive line
  • the connecting portion is electrically connected.
  • the array substrate further includes a first gate line layer and a second gate line layer disposed on the base substrate;
  • the sub-pixel further includes a sub-pixel drive circuit, the sub-pixel drive circuit includes a capacitor and a drive transistor, the capacitor includes a first electrode plate and a second electrode plate, and the first electrode plate is arranged on the first gate Line layer, the second plate is arranged on the second gate line layer; the first plate of the capacitor is multiplexed as the gate of the drive transistor, the first stage of the drive transistor and the power supply line connection;
  • a plurality of third conductive connection parts are also arranged on the first source and drain layers, and the third conductive connection parts are distributed in each sub-pixel region;
  • the third conductive connection part is connected to the first stage of the driving transistor through a via hole, and the third conductive connection part is also connected to the power supply line through a via hole, so that the power supply line passes through the third A conductive connection is electrically connected to the first stage of the drive transistor.
  • the array substrate further includes a plurality of scan lines, the scan lines are disposed in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, for providing a scan signal to each of the sub-pixels;
  • the sub-pixel driving circuit further includes a first transistor, the gate of the first transistor is connected to the scan line, the first stage of the first transistor is connected to the data line, and the first transistor of the first transistor is connected to the data line.
  • the second stage is connected to the second plate of the capacitor;
  • the first source and drain layers are further provided with a plurality of fourth conductive connection parts, and the fourth conductive connection parts are distributed in each sub-pixel region;
  • the fourth conductive connection part is connected with the first stage of the first transistor through a via hole, and the fourth conductive connection part is also connected with the data line through a via hole, so that the data line passes through all the
  • the fourth conductive connection portion is electrically connected to the first stage of the first transistor.
  • the sub-pixel includes an anode disposed on the anode layer;
  • the array substrate further includes a plurality of reset signal lines, and the reset signal lines are disposed on the first gate a line layer, extending along the row direction and being spaced apart along the column direction, for providing a reset signal to each of the sub-pixels;
  • the sub-pixel driving circuit further includes an eighth transistor, the gate of the eighth transistor is connected to the reset signal line, the first stage of the eighth transistor is electrically connected to the initialization signal line, and the eighth transistor is electrically connected to the initialization signal line.
  • the second stage of the transistor is electrically connected to the anode of the sub-pixel;
  • the first source and drain layers are also provided with a plurality of fifth conductive connecting parts
  • the second source and drain layers are also provided with a plurality of sixth conductive connecting parts
  • the fifth conductive connecting parts and the sixth The conductive connection parts are distributed in each sub-pixel region;
  • the fifth conductive connection part and the second stage of the eighth transistor are connected through a via hole
  • the fifth conductive connection part and the sixth conductive connection part are connected through a via hole
  • the sixth conductive connection part and the The anodes are connected through vias to electrically connect the second stage of the eighth transistor with the anodes of the sub-pixels.
  • the array substrate further includes a plurality of light-emitting control signal lines, the light-emitting control signal lines are provided on the first gate line layer, extend along the row direction and extend along the row direction.
  • the column directions are arranged at intervals, and are used to provide light-emitting control signals to each of the sub-pixels;
  • the sub-pixel driving circuit further includes a second transistor and a ninth transistor, the gate of the second transistor is connected to the scan line, and the first stage of the second transistor is connected to the second stage of the driving transistor , the second stage of the second transistor is connected to the first plate of the capacitor; the gate of the ninth transistor is connected to the light-emitting control signal line, and the first stage of the ninth transistor is connected to the The first plate of the capacitor is electrically connected;
  • the first source and drain layers are further provided with a plurality of first conductive connection parts, and the first conductive connection parts are distributed in each sub-pixel region;
  • the first conductive connection part is connected with the second stage of the second transistor and the first stage of the ninth transistor through via holes, and the first conductive connection part also passes through the first electrode plate of the capacitor The via holes are connected, so that the second stage of the second transistor and the first stage of the ninth transistor are electrically connected to the first electrode plate of the capacitor.
  • the sub-pixel driving circuit further includes a fifth transistor and a sixth transistor, a gate of the fifth transistor is connected to the reset signal line, and a gate of the fifth transistor is connected to the reset signal line.
  • the first stage is electrically connected to the initialization signal line
  • the second stage of the fifth transistor is electrically connected to the second plate of the capacitor
  • the gate of the sixth transistor is connected to the light-emitting control signal line
  • the first stage of the sixth transistor is electrically connected to the initialization signal line
  • the second stage of the sixth transistor is electrically connected to the second plate of the capacitor
  • the first source and drain layers are further provided with a plurality of second conductive connection parts, and the second conductive connection parts are distributed in each sub-pixel region;
  • the second conductive connection part is connected with the second stage of the first transistor, the second stage of the fifth transistor, and the second stage of the sixth transistor through a via hole, and the second conductive connection part is also connected to the second stage of the sixth transistor.
  • the second electrode plate of the capacitor is connected through a via hole, so that the second stage of the first transistor, the second stage of the fifth transistor, and the second stage of the sixth transistor are electrically connected to the second electrode plate of the capacitor .
  • the sub-pixel driving circuit further includes:
  • the gate of the fourth transistor is connected to the reset signal line, the first stage of the fourth transistor is electrically connected to the initialization signal line, and the second stage of the fourth transistor is connected to the reset signal line
  • the first plate of the capacitor is electrically connected;
  • the gate of the seventh transistor is connected to the light-emitting control signal line
  • the first stage of the seventh transistor is electrically connected to the second stage of the driving transistor
  • the second stage of the seventh transistor is The stage is electrically connected to the anode of the sub-pixel.
  • the array substrate further includes:
  • a plurality of power supply leads are arranged on the second gate line layer, extend along the row direction and are arranged at intervals along the column direction, and the power supply lines located in each of the sub-pixel regions in the same row are connected to one through a via hole the power leads.
  • the third conductive connection part is also connected with the power supply line through a via hole, so that the power supply line and the power supply lead are electrically connected.
  • the number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal lines and the connection lines are in each sub-pixel
  • the pixel areas are all electrically connected through vias;
  • the number of the connection lines is smaller than the number of sub-pixels in the row direction, and in the row direction, the initialization signal line and each of the connection lines are electrically connected through via holes in some sub-pixel regions.
  • a display device comprising the above-mentioned array substrate.
  • FIG. 1 is a schematic diagram of the positional relationship between an initialization signal line and a connection line in an embodiment
  • FIG. 2 is a schematic structural diagram of a sub-pixel circuit of a 9T1C
  • FIG. 3 is a timing diagram of the sub-pixel circuit structure shown in FIG. 2;
  • FIG. 5 is a schematic view of the stacking of the active layer and the first gate line layer in the first embodiment
  • FIG. 6 is a schematic diagram of stacking of the active layer, the first gate line layer, and the second gate line layer in the first embodiment
  • FIG. 7 is a schematic view of the stacking of the active layer, the first gate line layer, the second gate line layer, and the first source and drain layers in the first embodiment;
  • FIG. 8 is a schematic diagram of film stacking of an active layer, a first gate line layer, a second gate line layer, a first source and drain layer, and a second source and drain layer in the first embodiment;
  • FIG. 9 is a schematic structural diagram of the first gate line layer in the first embodiment.
  • FIG. 10 is a schematic structural diagram of the second gate line layer in the first embodiment
  • FIG. 11 is a schematic structural diagram of a first source and drain layer in the first embodiment
  • FIG. 12 is a schematic structural diagram of the second source and drain layers in the first embodiment
  • Fig. 13 is the sectional view of the A-A direction in Fig. 8;
  • FIG. 14 is a schematic diagram of an array structure of a plurality of sub-pixels in the first embodiment
  • FIG. 15 is a schematic diagram of film stacking of an active layer, a first gate line layer, a second gate line layer, and a first source and drain layer in the second embodiment;
  • FIG. 16 is a schematic diagram of film stacking of an active layer, a first gate line layer, a second gate line layer, a first source and drain layer, and a second source and drain layer in the second embodiment;
  • 17 is a schematic structural diagram of the first source and drain layers in the second embodiment
  • FIG. 18 is a schematic structural diagram of a second source and drain layer in the second embodiment
  • 19 is a schematic structural diagram of the anode layer in the second embodiment.
  • Figure 20 is a sectional view taken along the direction B-B in Figure 16;
  • 21 is a schematic diagram of an array structure of a plurality of sub-pixels in the second embodiment
  • 22 is a schematic view of the film stacking of the active layer, the first gate line layer, the second gate line layer, and the first source and drain layers in the third embodiment;
  • 23 is a schematic view of the film stacking of the active layer, the first gate line layer, the second gate line layer, the first source and drain layers, and the second source and drain layers in the third embodiment;
  • FIG. 24 is a schematic structural diagram of the first source and drain layers in the third embodiment.
  • 25 is a schematic structural diagram of the second source and drain layers in the third embodiment.
  • 26 is a schematic structural diagram of the anode layer in the third embodiment.
  • Figure 27 is a schematic cross-sectional view of the direction C-C in Figure 23;
  • active layer 100 active layer; 200, first gate insulating layer; 300, first gate line layer; 400, second gate insulating layer; 500, second gate line layer; 500', second gate Line layer; 600, first dielectric layer; 700, first source and drain layer; 800, first dielectric layer; 900, first source and drain layer; 1000, passivation layer; 1100, anode layer;
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • An embodiment of the present disclosure provides an array substrate.
  • the array substrate is arrayed with a plurality of pixel units along a row direction and a column direction, and the pixel unit includes a plurality of sub-pixels.
  • the array substrate includes a plurality of initialization signal lines 51 and a plurality of connection lines 10 .
  • a plurality of initialization signal lines 51 are provided on the first conductive layer, extend along the row direction and are arranged at intervals along the column direction, and each initialization signal line 51 is used to provide initialization signals to each sub-pixel in the extending direction.
  • a plurality of connecting lines 10 are disposed on the second conductive layer, extend along the column direction and are arranged at intervals along the row direction.
  • the horizontal direction is the row direction
  • the vertical direction is the column direction as an example.
  • the projections of the at least one initialization signal line 51 and the at least one connection line 10 on the base substrate are both intersected and electrically connected, so that the projections of the initialization signal line 51 and the connection line 10 on the base substrate intersect to form a grid-like structure.
  • the criss-crossed initialization signal lines 51 and the connecting lines 10 are connected into a grid-like structure, which increases the paths of the initialization signal, and the initialization signal can be transmitted to each sub-pixel through more paths, thereby reducing the IR caused by the single current transmission path. The problem of too large drop.
  • the number of connecting lines 10 may be equal to the number of sub-pixels in the row direction, or may be smaller than the number of sub-pixels in the row direction.
  • the number of connection lines 10 is smaller than the number of sub-pixels in the row direction, it means that in the row direction, the initialization signal lines 51 and the connection lines 10 are electrically connected in part of the sub-pixel area.
  • the number of connecting lines 10 is half of the number of sub-pixels in the row direction, and one is provided every other sub-pixel, then the initialization signal line 51 is electrically connected to one connecting line 10 every other sub-pixel. Therefore, one of every two adjacent sub-pixels in the row direction is provided with the connection line 10 , and the other is not provided with the connection line 10 .
  • a different number of sub-pixels may also be spaced between two adjacent connecting lines 10.
  • connection line 10 is provided in each sub-pixel in the row direction. As long as the projections of the plurality of connection lines 10 and the plurality of initialization signal lines 51 on the base substrate can form a grid-like structure.
  • the horizontal arrangement of the initialization signal line 51 means that the main structure of the initialization signal line 51 extends in the horizontal direction.
  • the longitudinal arrangement of the connecting line 10 means that the main structure of the connecting line 10 extends in the longitudinal direction, and the overall direction is the longitudinal direction.
  • each pixel unit is composed of four RGBG sub-pixels, and each sub-pixel is driven by a separate sub-pixel driving circuit.
  • the sub-pixel circuit structure includes a capacitor and nine TFT transistors T1-T9.
  • the third transistor T3 is a driving transistor, and the other transistors are switching transistors.
  • the capacitor includes a first electrode plate Cst1 and a second electrode plate Cst2 .
  • the first electrode plate Cst1 is provided on the first gate line layer 300
  • the second electrode plate Cst2 is provided on the second gate line layer 500 .
  • the first plate Cst1 is connected to the node N2, and the second plate Cst2 is connected to the node N1.
  • the gate 3g of the driving transistor T3 (third transistor) is multiplexed by the first plate Cst1 of the capacitor, and the source 3s is connected to the power supply line 72; the gate 1g of the first transistor T1 is connected to the scan line 31, and the source 1s is connected to The data line 71 is connected, and the drain 1d is connected to the node N1.
  • the gate 2g of the second transistor T2 is connected to the scan line 31, the source 2s is connected to the drain 3d of the driving transistor T3, and the drain 2d is connected to the node N2.
  • the gate 4g of the fourth transistor T4 is connected to the reset signal line 32, the source 4s is electrically connected to the initialization signal line 51, and the drain 4d is connected to the node N2.
  • the gate 5g of the fifth transistor T5 is connected to the reset signal line 32, the source 5s is electrically connected to the initialization signal line 51, and the drain 5d is connected to the node N1.
  • the gate 6g of the sixth transistor T6 is connected to the light emission control signal line 33, the source 6s is electrically connected to the initialization signal line 51, and the drain 6d is connected to the node N1.
  • the gate 7g of the seventh transistor T7 is connected to the light emission control signal line 33, the source 7s is electrically connected to the drain 3d of the driving transistor T3, and the drain 7d is electrically connected to the anode 91 of the sub-pixel.
  • the gate 8g of the eighth transistor T8 is connected to the reset signal line 32, the source 8s is electrically connected to the initialization signal line 51, and the drain 8d is electrically connected to the anode 91 of the sub-pixel.
  • the gate 9g of the ninth transistor T9 is connected to the light emission control signal line 33, and the source 9s is connected to the node N2.
  • the initialization signal provided by the initialization signal line 51 is Vint
  • the reset signal provided by the reset signal line 32 is Reset
  • the light-emitting control signal provided by the light-emitting control signal line 33 is EM
  • the scan signal provided by the scan line 31 is gate
  • the data line 71 The data signal provided is data
  • the power supply signal provided by the power line 72 is ELVDD.
  • the specific working principle of the sub-pixel compensation circuit is as follows:
  • the reset signal Reset is at a low level.
  • the fourth transistor T4 is turned on, and the initial signal Vint initializes the point N2.
  • the potential of the point N2 is the initial signal Vint.
  • the fifth transistor T5 is turned on, and the initial signal Vint is written into the N1 point.
  • the eighth transistor T8 is turned on to release the residual charge displayed in the previous frame, and the initial signal Vint is written to reduce the voltage difference between the anode and cathode of the OLED device, reduce the brightness of the OLED device at low gray levels, and improve the contrast of the pixel.
  • the signal Gate of the scan line 31 is at a low level.
  • the first transistor T1 is turned on.
  • the potential of the N1 point is Vdata, and the data signal voltage is written into the N1 point.
  • the second transistor T2 is turned on, sampling the diode connection of the driving transistor T3, the potential of the N2 point rises to ELVDD+Vth, the driving transistor T3 gradually changes from the on state to the off state, and compensates the threshold voltage Vth of the driving transistor T3.
  • the light emission control signal EM is at a low level.
  • the sixth transistor T6 is turned on, at this time, the potential of the point N1 is the initial signal Vint.
  • the ninth transistor T9 is turned on, and the leakage of the N2 point is reduced in the light-emitting stage. As the potential of the N1 point jumps, the potential of the N2 point becomes ELVDD+Vth+Vint-Vdata at this time.
  • the seventh transistor T7 is turned on, the driving current is output, and the OLED device emits light.
  • the current calculation formula of the OLED device is
  • the threshold voltage Vth of the driving transistor T3 can be compensated in the sampling stage, thereby eliminating the influence of the difference of the DTFT threshold voltage Vth of different pixels on the uniformity of display brightness.
  • Vint can be used as an initialization signal, and can also be used as a reference signal during data writing.
  • the sub-pixel driving circuits of the above-mentioned sub-pixels are fabricated on a base substrate.
  • An active layer 100 , a first gate line layer 300 , a second gate line layer 500 , a first source and drain layer 700 , a second source and drain layer 900 , and an anode layer 1100 are stacked on the base substrate.
  • These film layers are used for Various signal lines or wires are formed to provide corresponding electrical signals to each sub-pixel driving circuit.
  • the insulating layers are used for insulation between the two film layers.
  • the first gate insulating layer 200 is provided between the active layer 100 and the first gate line layer 300
  • the first gate line layer 300 and the second gate line layer 500 are provided.
  • a first dielectric layer 600 is provided between the second gate insulating layer 400 , the second gate line layer 500 and the first source and drain layers 700 , and a second dielectric layer 600 is provided between the first source and drain layers 700 and the second source and drain layers 900 .
  • a passivation layer 1000 is further provided above the dielectric layer 800 and the second source and drain layers 900 .
  • the anode layer 1100 , the organic light-emitting layer, the cathode layer and other film layers of the sub-pixels are disposed above the passivation layer 1000 to form an OLED light-emitting device, and the OLED light-emitting devices of each sub-pixel are separated by a pixel defining layer.
  • only the passivation layer 1000 is provided between the second source-drain layer 900 and the anode layer 1100 as an example for description.
  • other film layers such as a planarization layer may also be provided.
  • FIGS. 4-8 show the active layer 100 , the first gate line layer 300 , the second gate line layer 500 , the first source and drain layers 700 , and the second source and drain layers in one sub-pixel region in the first embodiment.
  • a schematic diagram of the film stack of the drain layer 900, FIG. 9-FIG. 12 show the first gate line layer 300, the second gate line layer 500, the first source and drain layers 700, and the second source and drain layers in a sub-pixel region
  • a schematic diagram of each layer structure of the layer 900 shows a schematic cross-sectional view along the A-A direction in FIG. 8 .
  • the active layer 100 is used for disposing channel regions (1g-9g), first stages (1s-9s) and second stages (1d-9d) of each TFT transistor.
  • the first gate line layer 300 is used to set the gates (eg, 1g ⁇ 9g) of the transistors in the sub-pixel driving circuit, the first electrode plate Cst1 of the capacitor, and a plurality of scan lines 31 , A plurality of reset signal lines 32, a plurality of light-emitting control signal lines 33 and other structures.
  • a plurality of scan lines 31 are arranged at intervals in the column direction and extend in the row direction, and are used for providing scan signals to each sub-pixel located in the same row in the row direction.
  • a plurality of reset signal lines 32 are arranged at intervals in the column direction and extend in the row direction, and are used for providing reset signals to sub-pixels located in the same row in the row direction.
  • the plurality of light-emitting control signal lines 33 extend in the row direction and are arranged at intervals in the column direction, and are used for providing light-emitting control signals to sub-pixels located in the same row in the row direction.
  • the reset signal line 32 is located at the top
  • the scan line 31 is located at the bottom
  • the light-emitting control signal line 33 is located between the reset signal line 32 and the scan line 31
  • the first plate Cst1 of the capacitor is located at the bottom. Between the light emission control signal line 33 and the scan line 31 .
  • the reset signal line 32 of the sub-pixel of the next level can be connected to the scan line 31 of the sub-pixel of the previous level, so that the scan signal of the sub-pixel of the previous level can be used as the reset signal of the sub-pixel of the next level, thereby Avoid introducing a separate signal line for the reset signal, effectively reducing the wiring space.
  • the second gate line layer 500 is used to set structures such as a second electrode plate Cst2 forming a capacitor, and the second electrode plate Cst2 of the capacitor corresponds to the first electrode plate Cst1 in the thickness direction of the array substrate.
  • the second gate line layer 500 further includes a plurality of power supply leads 52.
  • the plurality of power supply leads 52 extend along the row direction and are arranged at intervals along the column direction.
  • the power supply leads 52 are used to connect the The power lines 72 are connected through via holes, so that the projections of the power leads 52 and the power lines 72 also form a grid-like structure, which can reduce the voltage drop of the power supply voltage.
  • the first conductive layer and the second conductive layer are both the first source-drain layer 700 , that is, the initialization signal line 51 and the connection line 10 are both disposed on the first source-drain layer
  • the initialization signal lines 51 extend in the row direction
  • the connection lines 10 extend in the column direction
  • each initialization signal line 51 is connected with each connection line 10 and crosses in a grid shape. That is to say, in this embodiment, each sub-pixel region has the initialization signal line 51 and the connection line 10 .
  • the initialization signal line 51 is often disposed on the gate layer, and the initialization signal is easily affected by the gate driving signal.
  • the initialization signal line 51 and the connection line 10 of the present disclosure are in the first source-drain layer 700 , which can reduce the parasitic capacitance between the initialization signal and the gate driving signal, enhance the anti-interference ability, and improve the product display uniformity.
  • the initialization signal line 51 is also connected to the source electrode 5s of the fifth transistor T5 and the source electrode 6s of the sixth transistor T6 through via holes penetrating the first gate insulating layer 200 , the second gate insulating layer 400 and the first dielectric layer 600 , It is further connected to the source 4s of the fourth transistor T4 and the source 8s of the eighth transistor T8.
  • the connecting wire 10 shown in the figure is designed to be bent in order to avoid other structures, but it does not affect the overall extending direction of the connecting wire 10 being the longitudinal direction.
  • the power lines 72 and the data lines 71 are both disposed on the second source and drain layers 900 .
  • the power lines 72 extend in the column direction and are arranged at intervals in the row direction, and are used to provide power signals to sub-pixels in the same column.
  • the data lines 71 extend along the column direction and are arranged at intervals along the row direction, and are used for providing data signals to each sub-pixel located in the same column. Wherein, the projections of the power lines 72 and the data lines 71 on the array substrate do not overlap with the first electrode plate Cst1 and the second electrode plate Cst2 of the capacitor.
  • the power supply line 72 and the data line 71 are arranged in the second source-drain layer 900, and are arranged in layers with the initialization signal line 51 and the connection line 10, which can reduce the parasitic capacitance of the power supply line 72, the data line 71 and other nodes, and enhance the The stability of power signal and data signal is more suitable for display products driven by high frequency.
  • the first source-drain layer 700 is further provided with a plurality of first conductive connection parts 75 , and each first conductive connection part 75 is disposed on the source-drain layer 700 and distributed in each sub-pixel region .
  • the projection of the first conductive connection portion 75 on the base substrate overlaps with the projection of the second transistor T2 2d and the projection of the first stage 9s of the ninth transistor T9
  • the gate insulating layer 200 , the second gate insulating layer 400 , and the via holes of the first dielectric layer 600 are connected to each other, and the projection of the first conductive connection portion 75 on the base substrate also overlaps with the projection of the first electrode plate Cst1 of the capacitor, and is passed through.
  • the via holes penetrating the second gate insulating layer 400 and the first dielectric layer 600 are connected, that is to say, both 2d and 9s are electrically connected to the first electrode plate Cst1 of the capacitor through the first conductive connection portion 75 .
  • the first conductive connection portion 75 is located on the right side of the connection line 10,
  • the first source-drain layer 700 is further provided with a plurality of second conductive connecting parts 74 , and each second conductive connecting part 74 is disposed on the source-drain layer 700 and distributed in each sub-pixel region.
  • the projection of the second conductive connection portion 74 on the base substrate is the same as the projection of the drain 1d of the first transistor T1, the drain 5d of the fifth transistor T5, and the drain 6d of the sixth transistor T6
  • the projections overlap and are connected through the vias penetrating the first gate insulating layer 200 , the second gate insulating layer 400 and the first dielectric layer 600 , and the projection of the second conductive connection portion 74 on the substrate is also connected to the second pole of the capacitor.
  • the second conductive connection portion 74 is located on the right side of the first conductive connection portion 75 .
  • a plurality of third conductive connecting portions 73 are further disposed on the first source and drain layers 700 , and each third conductive connecting portion 73 is distributed in each sub-pixel region. As shown in the figure, in each sub-pixel area, the projection of the third conductive connection portion 73 on the base substrate overlaps with the projection of the source electrode 3s of the driving transistor T3 The layer 400 and the via holes of the first dielectric layer 600 are connected, and the projection of the third conductive connection portion 73 on the base substrate also overlaps with the projection of the power line 72 and is connected through the via hole penetrating the second dielectric layer 800 . That is, the third conductive connection portion 73 is used to connect the source electrode 3s of the driving transistor T3 and the power supply line 72 .
  • the projection of the third conductive connection portion 73 on the base substrate also overlaps with the projection of the power lead 52 , and is connected through a via hole passing through the first dielectric layer 600 to connect the power lead 72 to the power lead 52 . It should be noted that, in each sub-pixel region, the third conductive connection portion 73 is located on the right side of the second conductive connection portion 74 .
  • the first source-drain layer 700 is further provided with a plurality of fourth conductive connecting portions 76 , and each fourth conductive connecting portion 76 is disposed on the first source-drain layer 700 and distributed in each sub-pixel region.
  • the projection of the fourth conductive connection portion 76 on the base substrate overlaps with the projection of the source electrode 1s of the first transistor T1, and passes through the first gate insulating layer 200 and the second gate
  • the insulating layer 400 and the via holes of the first dielectric layer 600 are connected, and the projection of the fourth conductive connection portion 76 on the base substrate also overlaps the projection of the data line 71 and is connected through the via hole penetrating the second dielectric layer 800 .
  • the fourth conductive connection portion 76 is used to connect the source electrode 1s of the first transistor T1 and the data line 71 . In each sub-pixel region, the fourth conductive connection portion 76 is located on the right side of the third conductive connection portion 73 .
  • a plurality of fifth conductive connecting portions 77 are further disposed on the first source and drain layer 700 , and each fifth conductive connecting portion 77 is disposed on the first source and drain layer 700 and distributed in each sub-pixel region. As shown in the figure, in each sub-pixel region, the projection of the fifth conductive connection portion 77 on the base substrate overlaps with the projection of the drain 8d of the eighth transistor T8, and passes through the first gate insulating layer 200 and the second gate The insulating layer 400 and the via holes of the first dielectric layer 600 are connected to each other.
  • the projection of the fifth conductive connection portion 77 on the base substrate also overlaps with the projection of the sixth conductive connection portion 78 provided on the second source-drain layer 900 , and is connected to the sixth conductive connection portion 78 through the via hole passing through the second dielectric layer 800 .
  • the conductive connections 78 are connected.
  • the projection of the sixth conductive connection portion 78 on the base substrate also overlaps with the projection of the anode of the sub-pixel, and is connected through the via hole provided on the passivation layer 1000 . That is to say, the drain electrode 8d of the eighth transistor T8 is connected to the anode through the fifth conductive connection part 77 and the sixth conductive connection part 78 in sequence, so that the pixel anode can be driven.
  • the fifth conductive connection portion 77 is located on the right side of the connection line 10 and the first conductive connection portion 75 .
  • the circular structure at the lower left corner of the first source-drain layer 700 in the sub-pixel region in FIG. 11 is the right half of the fourth conductive connecting portion 76 of the adjacent sub-pixel on the left, and the The right half of the four conductive connections 76 is located at the lower left corner of the right adjacent sub-pixel.
  • the vertical wiring on the left side of the second source-drain layer 900 in the sub-pixel region is the data line 71 of the adjacent sub-pixel on the left, and the data line 71 in the sub-pixel region can also be regarded as the adjacent sub-pixel on the right. within the pixel.
  • FIG. 14 shows a schematic structural diagram of the arrangement of eight sub-pixel arrays, in which only the initialization signal line 51 and the connection line 10 in the first source and drain layer 700 are shown, and other conductive connection parts are not shown.
  • the number of connecting lines 10 is the same as the number of sub-pixels in the row direction, that is, one vertical connecting line 10 is provided for each column of sub-pixels.
  • the initialization signal line 51 and the connection line 10 are disposed on the first source-drain layer 700 , which can improve the etching yield. Moreover, the material resistance of the first source-drain layer 700 is low, which is beneficial to improve the IR drop.
  • FIGS. 15-16 show schematic diagrams of film stacking of the first source-drain layer 700 and the second source-drain layer 900 in a sub-pixel region in the second embodiment
  • FIGS. 17-19 show a A schematic diagram of the structure of each layer of the first source-drain layer 700 , the second source-drain layer 900 , and the anode layer 1100 in the sub-pixel region.
  • the active layer 100 , the first gate line layer 300 , and the second gate line layer 500 are the same as those in FIG. 4 , FIG. 9 , and FIG. 10 , so the related drawings and descriptions are omitted here.
  • FIG. 20 shows a schematic cross-sectional view along the line B-B in FIG. 16 .
  • the first conductive layer is the first source-drain layer 700 , that is, the initialization signal lines 51 are provided on the first source-drain layer 700 , extending in the row direction and arranged at intervals in the column direction.
  • the initialization signal line 51 is located above the sub-pixel region, and the projection on the base substrate overlaps with the reset signal line 32. Since the reset signal line 32 is located in the first gate line layer 300, the initialization signal line 51 is located in The first source-drain layer 700 has many film layers between the reset signal line 32 and the initialization signal line 51 , so even if there is overlap, parasitic capacitance is not easily generated, which can ensure the stability of the signal.
  • the first source-drain layer 700 is also provided with the same first to fifth conductive connection parts as in FIG. 11 , and the structures and functions thereof are the same as those in FIG. 11 , and are not repeated here.
  • the anode layer 1100 is used for disposing the anode 91 of the OLED light emitting device, and is located in the opening of the pixel defining layer.
  • An organic light-emitting layer and a cathode layer are also arranged in the opening.
  • the film layer structure of the OLED light-emitting device may adopt a conventional structure, which will not be repeated here.
  • the figure is a schematic structural diagram of the anode layer 1100 of an RGBG pixel structure.
  • the second conductive layer is the anode layer 1100 , that is, the connecting wire 10 is provided on the anode layer 1100 , passes through the gap between the two anodes 91 in the longitudinal direction, and is insulated from any anode 91 .
  • the connection line 10 is covered by the pixel definition layer to avoid contact with other film layers above.
  • a seventh conductive connection part 79 is provided on the second source and drain layer 900 , and a plurality of seventh conductive connection parts 79 are distributed on the Initialize the sub-pixel area where the projection of the signal line 51 and the connection line 10 intersect, in other words, not necessarily all the second source and drain layers 900 of the sub-pixels are provided with the seventh conductive connection portion 79, but the initialization signal line 51 is connected to the sub-pixel where the connection line 10 is connected, and the sub-pixel is set in that sub-pixel.
  • 900 represents the first source-drain layer structure provided with the seventh conductive connection portion 79
  • 900 ′ represents the first source-drain layer structure without the seventh conductive connection portion 79
  • the projection of the seventh conductive connection portion 79 on the base substrate and the projection of the initialization signal line 51 have an overlapping area, and are connected through the vias provided on the second dielectric layer 800
  • the projection of the seventh conductive connection portion 79 on the base substrate and the projection of the connection line 10 have an overlapping area, and are connected through the vias provided on the passivation layer 1000, so that the initialization signal line 51 and the connection line 10 pass through the seventh
  • the conductive connections 79 form electrical connections.
  • the second source-drain layer 900 is also provided with the same power lines 72 , data lines 71 and sixth conductive connecting portions 78 as in FIG. 12 , whose structures and functions are the same as those in FIG. 12 , and will not be repeated here.
  • FIG. 21 shows a schematic structural diagram of the arrangement of eight sub-pixel arrays shown in FIG. 16 , in which only the initialization signal lines 51 in the first source and drain layers 700 and the second source and drain layers 900 are shown.
  • the seventh conductive connection portion 79, and the connection line 10 of the anode layer 1100, do not show other circuit structures.
  • the number of connecting lines 10 is half of the number of sub-pixels in the row direction, that is, one of every two adjacent sub-pixels in the row direction is provided with a connecting line 10, while the other is not provided with a connection. Line 10.
  • each connection line 10 is not arranged through the same column of sub-pixels, but is arranged in a bend in two adjacent columns of sub-pixels. Specifically, in the sub-pixels in the upper row, the connection line 10 is connected to the initialization signal line 51 in the left sub-pixel correspondingly, and in the sub-pixel in the next row, the connection line 10 is bent to correspond to the initialization signal line 51 in the right sub-pixel connection, this is to avoid the pixels on the anode layer 1100. It should be noted that, although the connecting wire 10 is bent and arranged in the longitudinal direction, since its overall direction is still in the longitudinal direction, it is regarded as extending in the longitudinal direction.
  • FIGS. 22-23 show schematic diagrams of film stacking of the first source-drain layer 700 and the second source-drain layer 900 in a sub-pixel region in the third embodiment
  • FIGS. 24-26 show a A schematic diagram of the structure of each layer of the first source-drain layer 700 , the second source-drain layer 900 , and the anode layer 1100 in the sub-pixel region.
  • the active layer 100 , the first gate line layer 300 , and the second gate line layer 500 are the same as those in FIG. 4 , FIG. 9 , and FIG. 10 , so the related drawings and descriptions are omitted here.
  • FIG. 27 shows a schematic cross-sectional view along the C-C direction in FIG. 23 .
  • the second conductive layer is the first source-drain layer 700 , that is, the connection lines 10 are provided on the first source-drain layer 700 , extending in the column direction and arranged at intervals in the row direction.
  • the connecting line 10 is located on the left side of the sub-pixel area.
  • the number of connecting lines is half of the number of sub-pixels in the row direction, that is, one of every two adjacent sub-pixels in the row direction is provided with a connecting line 10 while the other is not provided with a connecting line 10 . Therefore, 700 in FIG.
  • connection line 24 represents a schematic structural diagram of the first source-drain layer provided with the connection line 10
  • 700' represents a schematic structural diagram of the first source-drain layer without the connection line 10 provided.
  • the first source-drain layer 700 is also provided with the same first to fifth conductive connection parts as in FIG. 11 , all of which are located on the right side of the connection line 10 .
  • the first conductive layer is the anode layer 1100 , that is, the initialization signal line 51 is provided on the anode layer 1100 and passes through two rows of sub-layers in the lateral direction.
  • the space between the pixels is insulated from any anode 91 .
  • the initialization signal line 51 is covered by the pixel definition layer to avoid contact with other film layers above. In order to avoid the pixel opening area, the initialization signal line 51 is bent, but its overall extension direction is still horizontal.
  • a seventh conductive connection part 79 is provided on the second source and drain layer 900, and a plurality of seventh conductive connection parts 79 are distributed on the Initialize the sub-pixel area where the projection of the signal line 51 and the connection line 10 intersect, in other words, not necessarily all the second source and drain layers 900 of the sub-pixels are provided with the seventh conductive connection portion 79, but the initialization signal line 51 is connected to the sub-pixel where the connection line 10 is connected, and the sub-pixel is set in that sub-pixel.
  • 900 represents the second source-drain layer structure provided with the seventh conductive connection portion 79
  • 900' represents the second source-drain layer structure without the seventh conductive connection portion 79 provided.
  • the projection of the seventh conductive connection portion 79 on the base substrate and the projection of the connection line 10 have an overlapping area, and are connected through the vias provided on the second dielectric layer 800 .
  • the projection of the seventh conductive connection portion 79 on the base substrate also has an overlapping area with the projection of the initialization signal line 51, and is connected through the via hole provided on the passivation layer 1000, so that the initialization signal line 51 and the connection line 10 pass through the first Seven conductive connections 79 form electrical connections.
  • the initialization signal line 51 also needs to be connected to the source electrode 5s of the fifth transistor T5, in the sub-pixel region where the connection line 10 is provided, the projection of the connection line 10 on the substrate is also connected with the fifth transistor T5.
  • the projection of the source electrode 5s has an overlapping area, and the connection line 10 is connected to the source electrode 5s of the fifth transistor T5 through a via hole penetrating the first gate insulating layer 200 , the second gate insulating layer 400 and the first dielectric layer 600 . Since the initialization signal line 51 and the connection line 10 are electrically connected, the initialization signal line 51 is sequentially connected to the source electrode 5s of the fifth transistor T5 through the seventh conductive connection portion 79 and the connection line.
  • the wiring arrangement of other lines of the second source-drain layer 900 is also the same as that in the previous embodiment.
  • the second source-drain layer 900 is also provided with the same power lines 72 , data lines 71 and sixth conductive connecting portions 78 as in FIG. 12 , whose structures and functions are the same as those in FIG. 12 , and will not be repeated here.
  • FIG. 28 shows a schematic structural diagram of the arrangement of eight sub-pixel arrays, in which only the connection lines 10 in the first source and drain layers 700 , the seventh conductive connection parts 79 in the second source and drain layers 700 are shown, As well as the initialization signal line 51 in the anode layer 1100, other line structures are not shown.
  • the number of connecting lines 10 is the same as the number of sub-pixels in the row direction, that is, one vertical connecting line 10 and one seventh conductive connecting portion 79 are provided for each column of sub-pixels.
  • the above embodiments provide various setting positions and connection modes of the initialization signal lines and connection lines of the present disclosure, and various structures of the present disclosure can take into account the requirements of PPI and performance of different products while making reasonable wiring. It can be understood that the setting positions and connection manners of the initialization signal lines and the connection lines can be combined arbitrarily, so as to meet the requirements of the PPI of the display panel, process practicability and display performance.
  • the above embodiments are described by taking the 9T1C pixel circuit structure as an example.
  • the initialization signal lines and connection lines can also be set in the form of the dual source and drain layers of the present disclosure, so that the It forms a grid shape, which can also reduce the IR drop and relieve the wiring pressure.
  • each of the above pixel units is composed of four sub-pixels of RGBG, and only one algorithm is used as an example for the description.
  • the structure of the layered connection of the initialization signal lines and the connection lines of the present disclosure in a grid shape can also be applied to other Algorithm to arrange the RGBG pixel structure.
  • the initialization signal line and the connection line can also be connected in a grid shape through the double source and drain layers, which can also reduce the IR drop and relieve the wiring pressure. .
  • Embodiments of the present disclosure further provide a display device including the array substrate of the above-mentioned embodiments. Since the display device includes the above-mentioned array substrate, it has the same beneficial effects, and details are not described herein again in this disclosure.
  • the present disclosure does not specifically limit the application of display devices, which can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or components.
  • display devices can be TVs, notebook computers, tablet computers, wearable display devices, mobile phones, in-vehicle displays, navigation, e-books, digital photo frames, advertising light boxes, etc. products or components.

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Abstract

本公开提供一种阵列基板和显示装置。阵列基板包括多条初始化信号线（51）和多条连接线（10），初始化信号线（51）设于第一导电层，沿第一方向延伸且沿第二方向间隔排列；连接线（10）设于第二导电层，沿第二方向延伸且沿第一方向间隔排列；第一导电层和第二导电层为相同层或不同层；至少一条初始化信号线（51）与至少一条连接线（10）在衬底基板上的投影均相交且电连接，以使初始化信号线（51）和连接线（10）在衬底基板上的投影形成网格状结构。本公开可以改善IR drop过大的问题，还能减少布线空间压力。

Description

阵列基板和显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板和显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示技术，以其轻薄、自发光、视角广、响应速度快、亮度低、功耗低等优点，被业界公认为第三代显示技术，已广泛地被应用于高性能显示领域中。
随着对显示面板PPI(像素密度)的要求越来越高，面板上的布线压力也越来越大，既需要考虑各种线路能够紧密排布，又要尽量降低各种线路之间的互相影响，因此对布线设计提出了更高的要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种阵列基板和显示装置。
根据本公开的一个方面，提供一种阵列基板，阵列排布有多个像素单元，所述像素单元包括多个子像素，所述阵列基板包括：
多条初始化信号线，设于衬底基板上的第一导电层，沿第一方向延伸且沿第二方向间隔排列，用于向各所述子像素提供初始化信号；所述第一方向和第二方向相交；
多条连接线，设于所述衬底基板上的第二导电层，沿所述第二方向延伸且沿所述第一方向间隔排列；
其中，所述第一导电层和第二导电层为相同层或不同层；
其中，至少一条所述初始化信号线与至少一条所述连接线在所述衬底基板上的投影均相交且电连接，以使所述初始化信号线和所述连接线在所述衬底基板上的投影形成网格状结构。
在本公开的一种示例性实施方式中，所述阵列基板包括衬底基板和依次层叠设置于所述衬底基板上的第一源漏极层、第二源漏极层、阳极层；所述第一导电层和第二导电层中，至少任意一者为所述第一源漏极层，另一者为所述第一源漏极层或阳极层；所述第一方向为行方向，所述第二方向为列方向；
所述阵列基板还包括：
数据线，设于所述第二源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供数据信号；
电源线，设于所述第二源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供电源信号。
在本公开的一种示例性实施方式中，所述第一导电层和第二导电层均为所述第一源漏极层，所述初始化信号线沿行方向延伸，所述连接线沿列方向延伸，每一条所述初始化信号线与每一条所述连接线均连接且交叉呈网格状。
在本公开的一种示例性实施方式中，所述第一导电层为第一源漏极层，所述第二导电层为阳极层；所述初始化信号线设于所述第一源漏极层，沿所述行方向延伸且沿所述列方向间隔排列；所述连接线设于所述阳极层，沿所述列方向延伸且沿所述行方向间隔排列；每一条所述初始化信号线与每一条所述连接线均通过过孔电连接，所述多条初始化信号线和所述多条连接线在所述衬底基板上的投影交叉呈网格状。
在本公开的一种示例性实施方式中，所述第一导电层为阳极层，所述第二导电层为第一源漏极层；所述初始化信号线设于所述阳极层，沿所述行方向延伸且沿所述列方向间隔排列；所述连接线设于所述第一源漏极层，沿所述列方向延伸且沿所述行方向间隔排列；每一条所述初始化信号线与每一条所述连接线均通过过孔电连接，且所述多条初始化信号线和所述多条连接线在所述衬底基板上的投影交叉呈网格状。
在本公开的一种示例性实施方式中，所述第二源漏极层上还设置有多个第七导电连接部，所述第七导电连接部分布于所述初始化信号线与连接线的投影相交处所在的子像素区域；
其中，所述第七导电连接部与所述初始化信号线通过一过孔连接，第七导电连接部与连接线通过另一过孔连接，以使初始化信号线和连接线通过所述第七导电连接部电连接。
在本公开的一种示例性实施方式中，所述阵列基板还包括设置于所述衬底基板上的第一栅线层和第二栅线层；
所述子像素还包括子像素驱动电路，所述子像素驱动电路包括电容和驱动晶体管，所述电容包括第一极板和第二极板，所述第一极板设于所述第一栅线层，所述第二极板设于所述第二栅线层；所述电容的第一极板复用为所述驱动晶体管的栅极，所述驱动晶体管的第一级与所述电源线连接；
所述第一源漏极层上还设置有多个第三导电连接部，所述第三导电连接部分布于各子像素区域内；
其中，所述第三导电连接部与驱动晶体管的第一级通过过孔相连，所述第三导电连接部还与所述电源线通过过孔相连，以使所述电源线通过所述第三导电连接部与所述驱动晶体管的第一级电连接。
在本公开的一种示例性实施方式中，所述阵列基板还包括多条扫描线，所述扫描线设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供扫描信号；
所述子像素驱动电路还包括第一晶体管，所述第一晶体管的栅极与所述扫描线连接，所述第一晶体管的第一级与所述数据线连接，所述第一晶体管的第二级与所述电容的第二极板连接；
所述第一源漏极层上还设置有多个第四导电连接部，所述第四导电连接部分布于各子像素区域内；
其中，所述第四导电连接部与所述第一晶体管的第一级通过过孔相连，所述第四导电连接部还与所述数据线通过过孔相连，以使所述数据线通过所述第四导电连接部与所述第一晶体管的第一级电连接。
在本公开的一种示例性实施方式中，所述子像素包括设于所述阳极层的阳极；所述阵列基板还包括多条复位信号线，所述复位信号线设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供复位信号；
所述子像素驱动电路还包括第八晶体管，所述第八晶体管的栅极与所述复位信号线连接，所述第八晶体管的第一级与所述初始化信号线电连接，所述第八晶体管的第二级与所述子像素的阳极电连接；
所述第一源漏极层上还设置有多个第五导电连接部，所述第二源漏极层上还设置有多个第六导电连接部，所述第五导电连接部和第六导电连接部均分布于各子像素区域内；
其中，所述第五导电连接部和第八晶体管的第二级通过过孔连接，所述第五导电连接部和第六导电连接部通过过孔连接，所述第六导电连接部和所述阳极通过过孔连接，以使所述第八晶体管的第二级与所述子像素的阳极电连接。
在本公开的一种示例性实施方式中，所述阵列基板还包括多条发光控制信号线，所述发光控制信号线设于所述第一栅线层，沿所述行方向延伸且沿所述列方向间隔排列，用于向各所述子像素提供发光控制信号；
所述子像素驱动电路还包括第二晶体管和第九晶体管，所述第二晶体管的栅极与所述扫描线连接，所述第二晶体管的第一级与所述驱动晶体管的第二级连接，所述第二晶体管的第二级与所述电容的第一极板连接；所述第九晶体管的栅极与所述发光控制信号线连接，所述第九晶体管的第一级与所述电容的第一极板电连接；
所述第一源漏极层上还设置有多个第一导电连接部，所述第一导电连接部分布于各子像素区域内；
其中，所述第一导电连接部和所述第二晶体管的第二级、第九晶体管的第一级通过过孔连接，所述第一导电连接部还和所述电容的第一极板通过过孔连接，以使所述第二晶体管的第二级、第九晶体管的第一级与所述电容的第一极板电连接。
在本公开的一种示例性实施方式中，所述子像素驱动电路还包括第五晶体管和第六晶体管，所述第五晶体管的栅极与所述复位信号线连接，所述第五晶体管的第一级与所述初始化信号线电连接，所述第五晶体管的第二级与所述电容的第二极板电连接；所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一级与所述初始化信号线电连接，所述第六晶体管的第二级与所述电容的第二极板电连接；
所述第一源漏极层上还设置有多个第二导电连接部，所述第二导电连接部分布于各子像素区域内；
其中，所述第二导电连接部和所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级通过过孔连接，所述第二导电连接部还和所述电容的第二极板通过过孔连接，以使所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级与所述电容的第二极板电连接。
在本公开的一种示例性实施方式中，所述子像素驱动电路还包括：
第四晶体管，所述第四晶体管的栅极与所述复位信号线连接，所述第四晶体管的第一级与所述初始化信号线电连接，所述第四晶体管的第二级与所述电容的第一极板电连接；
第七晶体管，所述第七晶体管的栅极与所述发光控制信号线连接，所述第七晶体管的第一级与所述驱动晶体管的第二级电连接，所述第七晶体管的第二级与所述子像素的阳极电连接。
在本公开的一种示例性实施方式中，所述阵列基板还包括：
多条电源引线，设于所述第二栅线层，沿所述行方向延伸且沿所述列方向间隔排列，位于同一行的各所述子像素区域内的电源线通过过孔连接于一条所述电源引线。
其中，所述第三导电连接部还与所述电源线通过过孔连接，以使所述电源线与电源引线电连接。
在本公开的一种示例性实施方式中，所述连接线的数量与所述行方向上子像素的数量相等，在所述行方向上，所述初始化信号线与各所述连接线在每一子像素区域都通过过孔电连接；
或，所述连接线的数量小于所述行方向上子像素的数量，在所述行方向上，所述初始化信号线与各所述连接线在部分子像素区域通过过孔电连接。
根据本公开的另一个方面，提供一种显示装置，其中，包括以上所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种实施方式中初始化信号线和连接线的位置关系示意图；
图2为一种9T1C的子像素电路结构示意图；
图3为图2所示的子像素电路结构的时序图；
图4为第一种实施方式中有源层的结构示意图；
图5为第一种实施方式中有源层和第一栅线层膜层堆叠示意图；
图6为第一种实施方式中有源层、第一栅线层、第二栅线层膜层堆叠示意图；
图7为第一种实施方式中有源层、第一栅线层、第二栅线层、第一源漏极层膜层堆叠示意图；
图8为第一种实施方式中有源层、第一栅线层、第二栅线层、第一源漏极层、第二源漏极层的膜层堆叠示意图；
图9为第一种实施方式中第一栅线层的结构示意图；
图10为第一种实施方式中第二栅线层的结构示意图；
图11为第一种实施方式中第一源漏极层的结构示意图；
图12为第一种实施方式中第二源漏极层的结构示意图；
图13为图8中A-A向的截面图；
图14为第一种实施方式中多个子像素的阵列结构示意图；
图15为第二种实施方式中有源层、第一栅线层、第二栅线层、第一源漏极层的膜层堆叠示意图；
图16为第二种实施方式中有源层、第一栅线层、第二栅线层、第一源漏极层、第二源漏极层的膜层堆叠示意图；
图17为第二种实施方式中第一源漏极层的结构示意图；
图18为第二种实施方式中第二源漏极层的结构示意图；
图19为第二种实施方式中阳极层的结构示意图；
图20为图16中B-B向的截面图；
图21为第二种实施方式中多个子像素的阵列结构示意图；
图22为第三种实施方式中有源层、第一栅线层、第二栅线层、第一源漏极层的膜层堆叠示意图；
图23为第三种实施方式中有源层、第一栅线层、第二栅线层、第一源漏极层、第二源漏极层的膜层堆叠示意图；
图24为第三种实施方式中第一源漏极层的结构示意图；
图25为第三种实施方式中第二源漏极层的结构示意图；
图26为第三种实施方式中阳极层的结构示意图；
图27为图23中C-C向的截面示意图；
图28为第三种实施方式中多个子像素的阵列结构示意图；
图中：有源层100、有源层；200、第一栅绝缘层；300、第一栅线层；400、第二栅绝缘层；500、第二栅线层；500’、第二栅线层；600、第一介质层；700、第一源漏极层；800、第一介质层；900、第一源漏极层；1000、钝化层；1100、阳极层；
31、扫描线；32、复位信号线；33、发光控制信号线；51、初始化信号线；510、信号段；511、主体段；512、延伸段；52、电源引线；71、数据线；72、电源线；73、第三导电连接部；74、第二导电连接部；75、第一导电连接部；76、第四导电连接部；77、第五导电连接部；78、第六导电连接部；79、第七导电连接部；80、过孔；91、阳极；10、连接线。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本 公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式中提供了一种阵列基板，参考图1，该阵列基板沿行方向、列方向阵列排布有多个像素单元，像素单元包括多个子像素。阵列基板包括多条初始化信号线51和多条连接线10。多条初始化信号线51设于第一导电层，沿行方向延伸且沿列方向间隔排列，每一条初始化信号线51用于向其延伸方向上的各子像素提供初始化信号。多条连接线10设于第二导电层，沿列方向延伸且沿行方向间隔排列。图中横向方向为行方向，纵向方向为列方向为例。至少一条初始化信号线51与至少一条连接线10在衬底基板上的投影均相交且电连接，以使初始化信号线51和连接线10在衬底基板上的投影相交形成网格状结构。
将横纵交错的初始化信号线51连接线10连接成网格状结构，增多了初始化信号的路径，初始化信号可以通过更多路径传递至每一子像素，进而降低因电流传递路径单一导致的IR drop过大的问题。
本公开实施方式中，连接线10的数量可以等于行方向上子像素的数量，也可以小于行方向上子像素的数量。
具体来说，当连接线10的数量小于行方向上子像素的数量时，意味着，在行方向上，初始化信号线51与各连接线10在部分子像素区域内电连接。参考图1，连接线10的数量为行方向上子像素数量的一半，且每间隔一个子像素设置一条，那么每间隔一个子像素，初始化信号线51就和一条连接线10电连接。因此，行方向上每相邻两个子像素中有一个设置有连接线10，而另一个不设置连接线10。在其他实施方式中，连接线10的数量小于行方向上子像素的数量时，相邻两条连接线10之间也可以间隔不同数量 的子像素。
当连接线10的数量与行方向上子像素的数量相等时，意味着，在行方向上，初始化信号线51与各连接线10在每一子像素区域都电连接。因此，行方向上每个子像素中都设置有连接线10。只要多条连接线10和多条初始化信号线51在衬底基板上的投影能形成网格状结构即可。
可以理解的是，连接线10的数量越多，网格越密，初始化信号的传递路径越多，越能够降低IR drop，但布线的空间压力也会越大，制备工艺难度也越大。因此具体数量可根据实际情况进行设置。
需要说明的是，以初始化信号线51沿行方向延伸，连接线沿列方向延伸为例，初始化信号线51横向设置是指初始化信号线51主体结构沿横向延伸，实际产品中，可能会有局部并非完全横向设置，例如会拐弯以避开其他电路结构，或向其他方向延伸以便于与其他线路连接，等等，只要初始化信号线51的整体走向是横向方向即可。同理，连接线10纵向设置是指连接线10主体结构沿纵向延伸，整体走向是纵向方向。
以下对本实施方式的阵列基板进行详细说明：
本实施方式中，每个像素单元由RGBG四个子像素组成，各子像素都通过单独的子像素驱动电路进行驱动。
图2示出了一种9T1C的子像素电路结构，子像素电路结构包括一个电容和九个TFT晶体管T1～T9，本实施例中，第三晶体管T3为驱动晶体管，其他晶体管为开关晶体管。
参考图2，电容包括第一极板Cst1和第二极板Cst2，第一极板Cst1设于第一栅线层300，第二极板Cst2设于第二栅线层500。第一极板Cst1连于节点N2，第二极板Cst2连于节点N1。驱动晶体管T3(第三晶体管)的栅极3g由电容的第一极板Cst1复用，源极3s与电源线72连接；第一晶体管T1的栅极1g与扫描线31连接，源极1s与数据线71连接，漏极1d连于节点N1。第二晶体管T2的栅极2g与扫描线31连接，源极2s与驱动晶体管T3的漏极3d连接，漏极2d连于节点N2。第四晶体管T4的栅极4g与复位信号线32连接，源极4s与初始化信号线51电连接，漏极4d连于节点N2。第五晶体管T5的栅极5g与复位信号线32连接，源极5s与初始化信号线51电连接，漏极5d连于节点N1。第六晶体管T6的栅极6g与发光控制信号线33连接，源极6s与初始化信号线51电连接，漏极6d连于节点N1。第七晶体管T7的栅极7g与发光控制信号线33连接，源极7s与驱动晶体管T3的漏极3d电连接，漏极7d与子像素的阳极91电连接。第八晶体管T8的栅极8g与复位信号线32连接，源极8s与初始化信号线51 电连接，漏极8d与子像素的阳极91电连接。第九晶体管T9的栅极9g与发光控制信号线33连接，源极9s连于节点N2。
其中，初始化信号线51提供的初始化信号为Vint，复位信号线32提供的复位信号为Reset，发光控制信号线33提供的发光控制信号为EM，扫描线31提供的扫描信号为gate，数据线71提供的数据信号为data，电源线72提供的电源信号为ELVDD。
参考图3所示的时序图，该子像素补偿电路具体工作原理如下：
第1阶段，复位信号Reset为低电平。第四晶体管T4打开，初始信号Vint对N2点进行初始化，此时N2点电位为初始信号Vint。第五晶体管T5打开，初始信号Vint写入N1点。第八晶体管T8打开，释放上一帧显示残留电荷，初始信号Vint写入降低OLED器件阳极和阴极之间的电压差，在低灰阶时降低OLED器件的亮度，提高像素的对比度。
第2阶段，扫描线31信号Gate为低电平。第一晶体管T1打开，此时N1点电位为Vdata，数据信号电压写入N1点。第二晶体管T2打开，对驱动晶体管T3二极管连接进行采样，N2点电位升高至ELVDD+Vth，驱动晶体管T3逐渐由打开状态变为关闭状态，对驱动晶体管T3的阈值电压Vth进行补偿。
第3阶段，发光控制信号EM为低电平。第六晶体管T6打开，此时N1点电位为初始信号Vint。第九晶体管T9打开，发光阶段降低N2点漏电。随着N1点电位跳变，此时N2点电位变为ELVDD+Vth+Vint-Vdata。第七晶体管T7打开，驱动电流输出，OLED器件发光。OLED器件的电流计算公式为
Figure PCTCN2021075301-appb-000001
通过上述电路，可在采样阶段对驱动晶体管T3的阈值电压Vth进行补偿，进而消除不同像素的DTFT阈值电压Vth差异对显示亮度均一性的影响。
本实施例中，Vint可以作为初始化信号，也可以作为数据写入时的参考信号。
在本实施方式中，上述各子像素的子像素驱动电路制备于一衬底基板。衬底基板上层叠设置有源层100、第一栅线层300、第二栅线层500、第一源漏极层700、第二源漏极层900、阳极层1100，这些膜层用于形成各种信号线或导线，向各子像素驱动电路提供相应的电信号。两膜层之间均通过绝缘层进行绝缘，例如有源层100和第一栅线层300之间设置第一栅绝缘层200，第一栅线层300和第二栅线层500之间设置第二栅绝缘层400，第二栅线层500和第一源漏极层700之间设置第一介质层600，第一源漏极层700和第二源漏极层900之间设置第二介质层800，第二源漏极层900上方还进一步设置钝 化层1000。钝化层1000上方设置子像素的阳极层1100、有机发光层、阴极层等膜层，以形成OLED发光器件，各子像素的OLED发光器件通过像素界定层进行间隔。本实施方式中，第二源漏极层900和阳极层1100之间以仅设置钝化层1000为例进行说明，在其他实施方式中，还可以设置平坦化层等其他膜层。
图4-图8示出了第一种实施方式中，一个子像素区域内有源层100、第一栅线层300、第二栅线层500、第一源漏极层700、第二源漏极层900的膜层堆叠示意图，图9-图12示出了一个子像素区域内第一栅线层300、第二栅线层500、第一源漏极层700、第二源漏极层900的各层结构示意图。图13示出了图8中A-A向的截面示意图。
参考图4，有源层100用于设置各TFT晶体管的沟道区(1g-9g)、第一级(1s-9s)和第二级(1d-9d)。
参考图5和图9，第一栅线层300用于设置形成子像素驱动电路中各晶体管的栅极(如：1g～9g)、电容的第一极板Cst1、以及多条扫描线31、多条复位信号线32、多条发光控制信号线33等结构。多条扫描线31沿列方向间隔排列且沿行方向延伸，用于向行方向上位于同一行的各子像素提供扫描信号。多条复位信号线32沿列方向间隔排列且沿行方向延伸，用于向行方向上位于同一行的各子像素提供复位信号。多条发光控制信号线33沿行方向延伸且沿列方向间隔排列，用于向行方向上位于同一行的各子像素提供发光控制信号。其中，在每一个子像素区域内，复位信号线32位于最上方，扫描线31位于最下方，发光控制信号线33位于复位信号线32和扫描线31之间，电容的第一极板Cst1位于发光控制信号线33和扫描线31之间。在列方向上，下一级子像素的复位信号线32可以与上一级子像素的扫描线31相连，以使上一级子像素的扫描信号能够作为下一级子像素的复位信号，从而避免为复位信号单独引入专门的信号线，有效减少布线空间。
参考图6和图10，第二栅线层500用于设置形成电容的第二极板Cst2等结构，电容的第二极板Cst2在阵列基板厚度方向上与第一极板Cst1对应。本实施方式中，第二栅线层500还包括多条电源引线52，多条电源引线52沿行方向延伸且沿列方向间隔排列，电源引线52用于将同一行的各子像素区域内的电源线72通过过孔连接起来，由此使得电源引线52与电源线72的投影也形成了网格状结构，能够降低电源电压的压降。
参考图7、图11和图13，本实施方式中，第一导电层和第二导电层均为第一源漏极层700，即初始化信号线51和连接线10均设置于第一源漏极层700，初始化信号线51沿行方向延伸，连接线10沿列方向延伸，每一条初始化信号线51与每一条连接线 10均连接且交叉呈网格状。也就是说，在本实施方式中，每个子像素区域内都有初始化信号线51和连接线10。现有技术中往往将初始化信号线51设置在栅极层，初始化信号容易受到栅极驱动信号的影响。本公开初始化信号线51和连接线10在第一源漏极层700，可以降低初始化信号与栅极驱动信号之间的寄生电容，增强抗干扰能力，提升产品显示均一性。初始化信号线51还通过贯穿于第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔与第五晶体管T5的源极5s、第六晶体管T6的源极6s相连，进而与第四晶体管T4的源极4s、第八晶体管T8的源极8s相连。需要说明的是，图中所示的连接线10为了避开其他结构进行了弯曲设计，但不影响其整体延伸方向为纵向。
参考图8和图12，电源线72和数据线71均设于第二源漏极层900。电源线72沿列方向延伸且沿行方向间隔排列，用于向位于同一列的各子像素提供电源信号，电源线72通过过孔与电源引线52连接，以实现电源线网格化。数据线71沿列方向延伸且沿行方向间隔排列，用于向位于同一列的各子像素提供数据信号。其中，电源线72和数据线71在阵列基板上的投影均与电容的第一极板Cst1、第二极板Cst2无重叠。本公开将电源线72、数据线71设置于第二源漏极层900，与初始化信号线51和连接线10分层设置，可以降低电源线72、数据线71与其他节点的寄生电容，增强电源信号、数据信号的稳定性，更适合用于高频驱动的显示产品。
继续参考图7和图11，第一源漏极层700上还设置有多个第一导电连接部75，各第一导电连接部75设于源漏极层700且分布于各子像素区域内。如图所示，每个子像素区域内，第一导电连接部75在衬底基板上的投影与第二晶体管T2的2d、第九晶体管T9的第一级9s的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔相连，第一导电连接部75在衬底基板上的投影还与电容的第一极板Cst1的投影重叠，且通过贯穿第二栅绝缘层400、第一介质层600的过孔相连，也就是说，2d、9s均通过第一导电连接部75与电容的第一极板Cst1电连接。各子像素区域内，第一导电连接部75位于连接线10的右侧，
第一源漏极层700上还设置有多个第二导电连接部74，各第二导电连接部74设于源漏极层700且分布于各子像素区域内。如图所示，每个子像素区域内，第二导电连接部74在衬底基板上的投影与第一晶体管T1的漏极1d、第五晶体管T5的漏极5d、第六晶体管T6的6d的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔相连，第二导电连接部74在衬底基板上的投影还与电容的第二极板Cst2的投影重叠，且通过贯穿第一介质层600的过孔相连，也就是说，1d、5d、6d均 通过第二导电连接部74与电容的第二极板Cst2电连接。各子像素区域内，第二导电连接部74位于第一导电连接部75的右侧。
第一源漏极层700上还设置有多个第三导电连接部73，各第三导电连接部73分布于各子像素区域内。如图所示，每个子像素区域内，第三导电连接部73在衬底基板上的投影与驱动晶体管T3的源极3s的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔相连，第三导电连接部73在衬底基板上的投影还与电源线72的投影重叠，且通过贯穿第二介质层800的过孔相连。也就是说，第三导电连接部73用于将驱动晶体管T3的源极3s和电源线72连接。第三导电连接部73在衬底基板上的投影还与电源引线52的投影重叠，且通过贯穿第一介质层600的过孔相连，以将电源线72与电源引线52连接。需要说明的是，各子像素区域内，第三导电连接部73位于第二导电连接部74的右侧。
第一源漏极层700上还设置有多个第四导电连接部76，各第四导电连接部76设于第一源漏极层700且分布于各子像素区域内。如图所示，每个子像素区域内，第四导电连接部76在衬底基板上的投影与第一晶体管T1的源极1s的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔相连，第四导电连接部76在衬底基板上的投影还与数据线71的投影重叠，且通过贯穿第二介质层800的过孔相连。也就是说，第四导电连接部76用于将第一晶体管T1的源极1s和数据线71连接。各子像素区域内，第四导电连接部76位于第三导电连接部73的右侧。
第一源漏极层700上还设置有多个第五导电连接部77，各第五导电连接部77设于第一源漏极层700且分布于各子像素区域内。如图所示，每个子像素区域内，第五导电连接部77在衬底基板上的投影与第八晶体管T8的漏极8d的投影重叠，且通过贯穿第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔相连。第五导电连接部77在衬底基板上的投影还与设于第二源漏极层900上的第六导电连接部78的投影重叠，且通过贯穿第二介质层800的过孔与第六导电连接部78相连。第六导电连接部78在衬底基板上的投影还与子像素的阳极的投影重叠，且通过设于钝化层1000上的过孔相连。也就是说，第八晶体管T8的漏极8d依次通过第五导电连接部77、第六导电连接部78与阳极连接，由此可对像素阳极进行驱动。各子像素区域内，第五导电连接部77位于连接线10和第一导电连接部75的右侧。
需要说明的是，图11中位于子像素区域内第一源漏极层700左下角的圆形结构为左侧相邻子像素的第四导电连接部76的右半部分，本子像素区域的第四导电连接部76 的右半部分位于右侧相邻子像素的左下角。图12中位于子像素区域内第二源漏极层900左侧的纵向走线为左侧相邻子像素的数据线71，本子像素区域的数据线71也可以看做位于右侧相邻子像素内。
图14示出了八个子像素阵列排布的结构示意图，图中仅示出了第一源漏极层700中的初始化信号线51和连接线10，未示出其他导电连接部。本实施方式中，连接线10的数量与行方向上子像素数量相同，即每列子像素都设置一条纵向连接线10。
本实施方式中，由于第一源漏极层700采用干法刻蚀，将初始化信号线51和连接线10设置于第一源漏极层700，可提高刻蚀良品率。而且第一源漏极层700材料电阻较低，有利于改善IR drop。
图15-图16示出了第二种实施方式中，一个子像素区域内第一源漏极层700、第二源漏极层900的膜层堆叠示意图，图17-图19示出了一个子像素区域内第一源漏极层700、第二源漏极层900、阳极层1100的各层结构示意图。有源层100、第一栅线层300、第二栅线层500与图4、图9、图10相同，故此处省略相关附图及说明。图20示出了图16中B-B向的截面示意图。
参考图15和图17，第一导电层为第一源漏极层700，即初始化信号线51设于第一源漏极层700，沿行方向延伸且沿列方向间隔排列。本实施方式中，初始化信号线51位于子像素区域的上方，在衬底基板上的投影与复位信号线32有交叠，由于复位信号线32位于第一栅线层300，初始化信号线51位于第一源漏极层700，复位信号线32和初始化信号线51之间具有较多的膜层，即使有交叠也不易产生寄生电容，能保证信号的稳定。第一源漏极层700上还设置有与图11相同的第一～第五导电连接部，其结构和作用与图11中相同，此处不再赘述。
参考图19，阳极层1100用于设置OLED发光器件的阳极91，位于像素界定层的开口内。开口内还设置有有机发光层、阴极层。OLED发光器件的膜层结构可采用常规结构，此处不再赘述。图中所示为一种RGBG像素结构的阳极层1100结构示意图。
本实施方式中，第二导电层为阳极层1100，即连接线10设于阳极层1100，在纵向方向上穿过两个阳极91之间的空隙，且与任意阳极91都绝缘。连接线10被像素界定层覆盖，以避免与上方其他膜层接触。
为了实现初始化信号线51和连接线10的连接，参考图15、图17和图20，第二源漏极层900上设置有第七导电连接部79，多个第七导电连接部79分布于初始化信号线51与连接线10的投影相交处所在的子像素区域，换句话说，不一定所有子像素的第二 源漏极层900都设置有第七导电连接部79，而是初始化信号线51与连接线10在哪个子像素连接，就在哪个子像素设置。图17中900表示设置有第七导电连接部79的第一源漏极层结构，900’表示未设置第七导电连接部79的第一源漏极层结构。设置有第七导电连接部79的子像素区域内，第七导电连接部79在衬底基板的投影与初始化信号线51的投影具有重叠区域，通过设置于第二介质层800上的过孔连接，第七导电连接部79在衬底基板的投影与连接线10的投影具有重叠区域，通过设置于钝化层1000上的过孔连接，由此使得初始化信号线51和连接线10通过第七导电连接部79形成电连接。
第二源漏极层900上还设置有与图12相同的电源线72、数据线71和第六导电连接部78，其结构和作用与图12中相同，此处不再赘述。
图21示出了图16所示的八个子像素阵列排布的结构示意图，图中仅示出了第一源漏极层700中的初始化信号线51，以及第二源漏极层900中的第七导电连接部79，以及阳极层1100的连接线10，未示出其他线路结构。从图中可看出，本实施方式中，连接线10的数量为行方向上子像素数量的一半，即行方向上每相邻两个子像素中有一个设置有连接线10，而另一个不设置连接线10。另外，本实施方式中，每一条连接线10并非穿过同一列子像素设置，而是在相邻的两列子像素中拐弯设置。具体而言，上一行子像素中，连接线10与左侧子像素内的初始化信号线51对应连接，下一行子像素中，连接线10弯曲至与右侧子像素内的初始化信号线51对应连接，这是为了避开阳极层1100上的像素。需要说明的是，虽然连接线10沿纵向弯曲设置，但由于其整体走向仍是纵向，因此视为沿纵向延伸。
图22-图23示出了第三种实施方式中，一个子像素区域内第一源漏极层700、第二源漏极层900的膜层堆叠示意图，图24-图26示出了一个子像素区域内第一源漏极层700、第二源漏极层900、阳极层1100的各层结构示意图。有源层100、第一栅线层300、第二栅线层500与图4、图9、图10相同，故此处省略相关附图及说明。图27示出了图23中C-C向的截面示意图。
参考图22和图24，本实施方式中，第二导电层为第一源漏极层700，即连接线10设于第一源漏极层700，沿列方向延伸且沿行方向间隔排列。连接线10位于子像素区域的左侧。参考图26，本实施方式中，连接线的数量为行方向上子像素数量的一半，即行方向上每相邻两个子像素中有一个设置有连接线10，而另一个不设置连接线10。因此，图24中700表示设置有连接线10的第一源漏极层的结构示意图，700’表示未设置连接线10的第一源漏极层的结构示意图。第一源漏极层700上还设置有与图11相同的第一 ～第五导电连接部，均位于连接线10的右侧，其结构和作用与前述相同，此处不再赘述。
参考图26所示的RGBG像素结构的阳极层1100结构示意图，本实施方式中，第一导电层为阳极层1100，即初始化信号线51设于阳极层1100，在横向方向上穿过两行子像素之间的空隙，且与任意阳极91都绝缘。初始化信号线51被像素界定层覆盖，以避免与上方其他膜层接触。为了避开像素开口区，初始化信号线51弯曲设置，但其整体延伸方向仍为横向。
为了实现初始化信号线51和连接线10的连接，参考图23、图25和图27，第二源漏极层900上设置有第七导电连接部79，多个第七导电连接部79分布于初始化信号线51与连接线10的投影相交处所在的子像素区域，换句话说，不一定所有子像素的第二源漏极层900都设置有第七导电连接部79，而是初始化信号线51与连接线10在哪个子像素连接，就在哪个子像素设置。图25中900表示设置有第七导电连接部79的第二源漏极层结构，900’表示未设置第七导电连接部79的第二源漏极层结构。设置有第七导电连接部79的子像素区域内，第七导电连接部79在衬底基板的投影与连接线10的投影具有重叠区域，通过设置于第二介质层800上的过孔连接。第七导电连接部79在衬底基板的投影还与初始化信号线51的投影具有重叠区域，通过设置于钝化层1000上的过孔连接，由此使得初始化信号线51和连接线10通过第七导电连接部79形成电连接。
另外，由于初始化信号线51还需与第五晶体管T5的源极5s相连，因此，在设置有连接线10的子像素区域内，连接线10在衬底基板的投影还与第五晶体管T5的源极5s的投影具有重叠区域，连接线10通过贯穿第一栅绝缘层200、第二栅绝缘层400、第一介质层600的过孔与第五晶体管T5的源极5s连接。由于初始化信号线51和连接线10电连接，因此使得初始化信号线51依次通过第七导电连接部79、连接线和第五晶体管T5的源极5s相连。本实施方式中，第二源漏极层900其他线路的走线布置也与上一实施方式相同。
第二源漏极层900上还设置有与图12相同的电源线72、数据线71和第六导电连接部78，其结构和作用与图12中相同，此处不再赘述。
图28示出了八个子像素阵列排布的结构示意图，图中仅示出了第一源漏极层700中的连接线10、第二源漏极层700中的第七导电连接部79、以及阳极层1100中的初始化信号线51，未示出其他线路结构。本实施方式中，连接线10的数量与行方向上子像素数量相同，即每列子像素都设置一条纵向连接线10以及一个第七导电连接部79。
以上实施方式给出了本公开初始化信号线和连接线的多种设置位置和连接方式，本 公开的各种结构均可以在合理布线的同时兼顾不同产品PPI的要求、性能的要求。可以理解的是，初始化信号线和连接线的设置位置、连接方式可以任意组合，以便适应显示面板PPI、工艺可实施性和显示性能的需求。另外，以上实施方式是以9T1C的像素电路结构为例进行说明，当阵列基板采用其他像素电路结构时，也可以采用本公开的双源漏极层的形式设置初始化信号线和连接线，以使其形成网格状，同样能够降低IR drop同时缓解布线压力。另外，上述每个像素单元由RGBG四个子像素组成，且仅以一种算法进行排列为例进行了说明，本公开初始化信号线和连接线分层连接呈网格状的结构也能够适用于其他算法进行排列的RGBG像素结构。进一步地，当像素单元采用其他设置方式时，例如RGB、RGBW等时，也可以将初始化信号线和连接线通过双源漏极层设置连接呈网格状，同样能够降低IR drop同时缓解布线压力。
本公开实施方式还提供一种显示装置，该显示装置包括上述实施方式的阵列基板。由于该显示装置包括上述阵列基板，因此具有相同的有益效果，本公开在此不再赘述。
本公开对于显示装置的适用不做具体限制，其可以是电视机、笔记本电脑、平板电脑、可穿戴显示设备、手机、车载显示、导航、电子书、数码相框、广告灯箱等任何具有柔性显示功能的产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种阵列基板，阵列排布有多个像素单元，所述像素单元包括多个子像素，其中，所述阵列基板包括：
    多条初始化信号线，设于衬底基板上的第一导电层，沿第一方向延伸且沿第二方向间隔排列，用于向各所述子像素提供初始化信号；所述第一方向和第二方向相交；
    多条连接线，设于所述衬底基板上的第二导电层，沿所述第二方向延伸且沿所述第一方向间隔排列；
    其中，所述第一导电层和第二导电层为相同层或不同层；
    其中，至少一条所述初始化信号线与至少一条所述连接线在所述衬底基板上的投影均相交且电连接，以使所述初始化信号线和所述连接线在所述衬底基板上的投影形成网格状结构。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括衬底基板和依次层叠设置于所述衬底基板上的第一源漏极层、第二源漏极层、阳极层；所述第一导电层和第二导电层中，至少任意一者为所述第一源漏极层，另一者为所述第一源漏极层或阳极层；所述第一方向为行方向，所述第二方向为列方向；
    所述阵列基板还包括：
    数据线，设于所述第二源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供数据信号；
    电源线，设于所述第二源漏极层，沿列方向延伸且沿所述行方向间隔排列，用于向各所述子像素提供电源信号。
  3. 根据权利要求2所述的阵列基板，其中，所述第一导电层和第二导电层均为所述第一源漏极层，所述初始化信号线沿行方向延伸，所述连接线沿列方向延伸，每一条所述初始化信号线与每一条所述连接线均连接且交叉呈网格状。
  4. 根据权利要求2所述的阵列基板，其中，所述第一导电层为第一源漏极层，所述第二导电层为阳极层；所述初始化信号线设于所述第一源漏极层，沿所述行方向延伸且沿所述列方向间隔排列；所述连接线设于所述阳极层，沿所述列方向延伸且沿所述行方向间隔排列；每一条所述初始化信号线与每一条所述连接线均通过过孔电连接，所述多条初始化信号线和所述多条连接线在所述衬底基板上的投影交叉呈网格状。
  5. 根据权利要求2所述的阵列基板，其中，所述第一导电层为阳极层，所述第二导电层为第一源漏极层；所述初始化信号线设于所述阳极层，沿所述行方向延伸且沿所 述列方向间隔排列；所述连接线设于所述第一源漏极层，沿所述列方向延伸且沿所述行方向间隔排列；每一条所述初始化信号线与每一条所述连接线均通过过孔电连接，且所述多条初始化信号线和所述多条连接线在所述衬底基板上的投影交叉呈网格状。
  6. 根据权利要求4或5所述的阵列基板，其中，所述第二源漏极层上还设置有多个第七导电连接部，所述第七导电连接部分布于所述初始化信号线与连接线的投影相交处所在的子像素区域；
    其中，所述第七导电连接部与所述初始化信号线通过一过孔连接，第七导电连接部与连接线通过另一过孔连接，以使初始化信号线和连接线通过所述第七导电连接部电连接。
  7. 根据权利要求3-6中任一项所述的阵列基板，其中，所述阵列基板还包括设置于所述衬底基板上的第一栅线层和第二栅线层；
    所述子像素还包括子像素驱动电路，所述子像素驱动电路包括电容和驱动晶体管，所述电容包括第一极板和第二级板，所述第一极板设于所述第一栅线层，所述第二极板设于所述第二栅线层；所述电容的第一极板复用为所述驱动晶体管的栅极，所述驱动晶体管的第一级与所述电源线连接；
    所述第一源漏极层上还设置有多个第三导电连接部，所述第三导电连接部分布于各子像素区域内；
    其中，所述第三导电连接部与驱动晶体管的第一级通过过孔相连，所述第三导电连接部还与所述电源线通过过孔相连，以使所述电源线通过所述第三导电连接部与所述驱动晶体管的第一级电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括多条扫描线，所述扫描线设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供扫描信号；
    所述子像素驱动电路还包括第一晶体管，所述第一晶体管的栅极与所述扫描线连接，所述第一晶体管的第一级与所述数据线连接，所述第一晶体管的第二级与所述电容的第二极板连接；
    所述第一源漏极层上还设置有多个第四导电连接部，所述第四导电连接部分布于各子像素区域内；
    其中，所述第四导电连接部与所述第一晶体管的第一级通过过孔相连，所述第四导电连接部还与所述数据线通过过孔相连，以使所述数据线通过所述第四导电连接部与所 述第一晶体管的第一级电连接。
  9. 根据权利要求8所述的阵列基板，其中，所述子像素包括设于所述阳极层的阳极；所述阵列基板还包括多条复位信号线，所述复位信号线设于所述第一栅线层，沿所述行方向延伸且沿列方向间隔排列，用于向各所述子像素提供复位信号；
    所述子像素驱动电路还包括第八晶体管，所述第八晶体管的栅极与所述复位信号线连接，所述第八晶体管的第一级与所述初始化信号线电连接，所述第八晶体管的第二级与所述子像素的阳极电连接；
    所述第一源漏极层上还设置有多个第五导电连接部，所述第二源漏极层上还设置有多个第六导电连接部，所述第五导电连接部和第六导电连接部均分布于各子像素区域内；
    其中，所述第五导电连接部和第八晶体管的第二级通过过孔连接，所述第五导电连接部和第六导电连接部通过过孔连接，所述第六导电连接部和所述阳极通过过孔连接，以使所述第八晶体管的第二级与所述子像素的阳极电连接。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括多条发光控制信号线，所述发光控制信号线设于所述第一栅线层，沿所述行方向延伸且沿所述列方向间隔排列，用于向各所述子像素提供发光控制信号；
    所述子像素驱动电路还包括第二晶体管和第九晶体管，所述第二晶体管的栅极与所述扫描线连接，所述第二晶体管的第一级与所述驱动晶体管的第二级连接，所述第二晶体管的第二级与所述电容的第一极板连接；所述第九晶体管的栅极与所述发光控制信号线连接，所述第九晶体管的第一级与所述电容的第一极板电连接；
    所述第一源漏极层上还设置有多个第一导电连接部，所述第一导电连接部分布于各子像素区域内；
    其中，所述第一导电连接部和所述第二晶体管的第二级、第九晶体管的第一级通过过孔连接，所述第一导电连接部还和所述电容的第一极板通过过孔连接，以使所述第二晶体管的第二级、第九晶体管的第一级与所述电容的第一极板电连接。
  11. 根据权利要求10所述的阵列基板，其中，所述子像素驱动电路还包括第五晶体管和第六晶体管，所述第五晶体管的栅极与所述复位信号线连接，所述第五晶体管的第一级与所述初始化信号线电连接，所述第五晶体管的第二级与所述电容的第二极板电连接；所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一级与所述初始化信号线电连接，所述第六晶体管的第二级与所述电容的第二极板电连接；
    所述第一源漏极层上还设置有多个第二导电连接部，所述第二导电连接部分布于各 子像素区域内；
    其中，所述第二导电连接部和所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级通过过孔连接，所述第二导电连接部还和所述电容的第二极板通过过孔连接，以使所述第一晶体管的第二级、第五晶体管的第二级、第六晶体管的第二级与所述电容的第二极板电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述子像素驱动电路还包括：
    第四晶体管，所述第四晶体管的栅极与所述复位信号线连接，所述第四晶体管的第一级与所述初始化信号线电连接，所述第四晶体管的第二级与所述电容的第一极板电连接；
    第七晶体管，所述第七晶体管的栅极与所述发光控制信号线连接，所述第七晶体管的第一级与所述驱动晶体管的第二级电连接，所述第七晶体管的第二级与所述子像素的阳极电连接。
  13. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括：
    多条电源引线，设于所述第二栅线层，沿所述行方向延伸且沿所述列方向间隔排列，位于同一行的各所述子像素区域内的电源线通过过孔连接于一条所述电源引线。
    其中，所述第三导电连接部还与所述电源线通过过孔连接，以使所述电源线与电源引线电连接。
  14. 根据权利要求1所述的阵列基板，其中，所述连接线的数量与所述行方向上子像素的数量相等，在所述行方向上，所述初始化信号线与各所述连接线在每一子像素区域都通过过孔电连接；
    或，所述连接线的数量小于所述行方向上子像素的数量，在所述行方向上，所述初始化信号线与各所述连接线在部分子像素区域通过过孔电连接。
  15. 一种显示装置，其中，包括权利要求1-14中任一项所述的阵列基板。
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CN108878488A (zh) * 2018-06-26 2018-11-23 上海天马有机发光显示技术有限公司 一种显示面板和显示装置及显示面板的制作方法
CN112117284A (zh) * 2019-06-21 2020-12-22 三星显示有限公司 显示装置
CN111584599A (zh) * 2020-05-27 2020-08-25 京东方科技集团股份有限公司 一种显示面板及其制作方法、显示装置
CN111584610A (zh) * 2020-06-10 2020-08-25 京东方科技集团股份有限公司 一种显示面板及显示装置
CN111682054A (zh) * 2020-06-24 2020-09-18 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置

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WO2024065629A1 (zh) * 2022-09-30 2024-04-04 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
WO2024065624A1 (en) * 2022-09-30 2024-04-04 Boe Technology Group Co., Ltd. Array substrate and display apparatus

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