WO2021097754A9 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2021097754A9
WO2021097754A9 PCT/CN2019/119953 CN2019119953W WO2021097754A9 WO 2021097754 A9 WO2021097754 A9 WO 2021097754A9 CN 2019119953 W CN2019119953 W CN 2019119953W WO 2021097754 A9 WO2021097754 A9 WO 2021097754A9
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
orthographic projection
signal line
sub
pattern
Prior art date
Application number
PCT/CN2019/119953
Other languages
English (en)
French (fr)
Other versions
WO2021097754A1 (zh
Inventor
刘庭良
杨慧娟
张毅
李瀚�
王予
皇甫鲁江
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980002526.4A priority Critical patent/CN113348558A/zh
Priority to US17/255,884 priority patent/US12035581B2/en
Priority to EP19945471.1A priority patent/EP4064357A4/en
Priority to PCT/CN2019/119953 priority patent/WO2021097754A1/zh
Priority to JP2021572448A priority patent/JP7401064B2/ja
Publication of WO2021097754A1 publication Critical patent/WO2021097754A1/zh
Priority to JP2023199938A priority patent/JP2024028766A/ja
Publication of WO2021097754A9 publication Critical patent/WO2021097754A9/zh
Priority to US18/734,462 priority patent/US20240324370A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • Active matrix organic light-emitting diode (English: Active-matrix organic light-emitting diode, abbreviation: AMOLED) display products are widely used for their advantages such as high brightness, low power consumption, fast response, high definition, good flexibility, and high luminous efficiency. applications in various fields.
  • the purpose of this disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display panel, including: a substrate, a functional film layer disposed on the substrate, and a plurality of first light-emitting elements disposed on a side of the functional film layer facing away from the substrate. ; Also includes multiple sub-pixel areas arranged in an array;
  • the functional film layer includes: a power signal line layer, a data line layer and a compensation function layer;
  • the power signal line layer includes a power signal line pattern provided in each of the sub-pixel areas, and the data line layer includes a power signal line pattern provided in each of the sub-pixel areas.
  • the data line pattern in each of the sub-pixel areas, the power signal line pattern includes a first part extending along the first direction, the data line pattern extends along the first direction;
  • the compensation function layer includes at least a compensation function graphic in the sub-pixel area;
  • Each of the first light-emitting elements includes: a first anode, a first light-emitting pattern and a first cathode that are stacked in sequence in a direction away from the substrate; an orthographic projection of the first anode on the substrate , there is a first overlapping area with the orthographic projection of the corresponding power signal line pattern on the substrate, there is a second overlapping area with the orthographic projection of the corresponding data line pattern on the substrate, and there is a second overlapping area with the corresponding orthographic projection of the data line pattern on the substrate There is a third overlapping area in the orthographic projection of the compensation function pattern on the substrate, and the second overlapping area is located between the first overlapping area and the third overlapping area.
  • the first anode includes a first edge portion and a second edge portion oppositely arranged along the second direction, and a first middle portion located between the first edge portion and the second edge portion;
  • the second direction intersects the first direction;
  • the orthographic projection of the first edge portion on the substrate includes the first overlapping area; the orthographic projection of the second edge portion on the substrate includes the third overlapping area; the first overlapping area An orthographic projection of the middle portion on the substrate includes the second overlapping area.
  • the orthographic projection of the first edge portion on the substrate does not overlap with the orthographic projection of the first luminous pattern on the substrate
  • the orthographic projection of the second edge portion on the substrate is The projection does not overlap with the orthographic projection of the first luminous pattern on the substrate; the orthographic projection of the first middle portion on the substrate intersects with the orthographic projection of the first luminous pattern on the substrate.
  • the functional film layer also includes: a gate scanning line layer, an initialization signal line layer, a reset signal line layer and a light emission control signal line layer;
  • the gate scan line layer includes a gate scan line pattern provided in each of the sub-pixel areas
  • the initialization signal line layer includes an initialization signal line pattern provided in each of the sub-pixel areas
  • the reset signal includes a reset signal line pattern provided in each of the sub-pixel areas
  • the light-emitting control signal line layer includes a light-emitting control signal line pattern provided in each of the sub-pixel areas; the gate scanning line pattern, The initialization signal line pattern, the reset signal line pattern and the light emitting control signal line pattern all extend along a second direction, and the second direction intersects the first direction.
  • the first anode further includes a third edge portion and a fourth edge portion oppositely arranged along the first direction, and the first middle portion is located between the third edge portion and the fourth edge portion. ;
  • the third edge portion is coupled to the first edge portion and the second edge portion respectively, and the fourth edge portion is coupled to the first edge portion and the second edge portion respectively;
  • the orthographic projection of the first middle portion on the substrate, the corresponding orthographic projection of the gate scan line pattern on the substrate, and the corresponding orthographic projection of the reset signal line pattern on the substrate Includes the sixth overlapping area.
  • the first anode includes a main body part and a via connecting part, and the main body part includes the first edge part, the second edge part, the third edge part, and the fourth edge part. and the first middle part; the main part is a centrally symmetrical figure.
  • the first middle part is a centrally symmetrical figure, and the orthographic projection of the first middle part on the substrate coincides with the orthographic projection of the first luminous pattern on the substrate.
  • the display panel includes a first metal layer, a second metal layer and a third metal layer;
  • the gate scanning line layer, the reset signal line layer and the light emission control signal line layer are located in the first metal layer;
  • the initialization signal line layer is located in the second metal layer
  • the data line layer, the power signal line layer and the compensation function layer are located in the third metal layer;
  • the functional film layer also includes a first insulating layer and a second insulating layer.
  • the first insulating layer is located between the first metal layer and the second metal layer.
  • the second insulating layer is located between the first metal layer and the second metal layer. between the second metal layer and the third metal layer.
  • the compensation function pattern is made of conductive material and coupled with the initialization signal line pattern.
  • the compensation function graphics and the data line graphics are arranged on the same layer.
  • the display panel further includes: a plurality of sub-pixel driving circuits, a first part of the sub-pixel driving circuits in the plurality of sub-pixel driving circuits corresponding to the first light-emitting element, the first part of the sub-pixel driving circuit The circuit is used to drive the corresponding first light-emitting element to emit light;
  • the sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor;
  • the gate electrode of the first transistor is coupled to the corresponding gate scan line pattern, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the corresponding gate scan line pattern.
  • the electrode is coupled to the gate of the driving transistor;
  • the gate of the second transistor is coupled to the corresponding reset signal line pattern, the first electrode of the second transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the second transistor coupled to the gate of the drive transistor;
  • the gate of the fourth transistor is coupled to the corresponding gate scan line pattern, the first electrode of the fourth transistor is coupled to the corresponding data line pattern, and the second electrode of the fourth transistor coupled to the first electrode of the drive transistor;
  • the first electrode of the driving transistor is coupled to the corresponding power signal line pattern, and the second electrode of the driving transistor is coupled to the corresponding first light-emitting element;
  • the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power signal line pattern.
  • the sub-pixel driving circuit further includes a first conductive connection part, and the second electrode of the first transistor is coupled to the gate of the driving transistor through the first conductive connection part;
  • the display panel further includes a third metal layer, the first conductive connection portion is located on the third metal layer, and the orthographic projection of the first conductive connection portion included in the first partial sub-pixel driving circuit on the substrate , the orthographic projections of the corresponding first anode on the substrate do not overlap.
  • the display panel further includes a plurality of second light-emitting elements and a plurality of third light-emitting elements; each of the second light-emitting elements includes a second anode, a second light-emitting pattern and a second cathode; each of the third light-emitting elements includes two sub-light-emitting elements arranged oppositely along the first direction, and each of the sub-light-emitting elements includes a light-emitting element along a direction away from the substrate.
  • the third anode, the third luminous pattern and the third cathode are stacked in sequence;
  • the plurality of sub-pixel driving circuits also include a second part of a sub-pixel driving circuit and a third part of a sub-pixel driving circuit.
  • the second part of the sub-pixel driving circuit corresponds to the second light-emitting element in a one-to-one manner.
  • the second part of the sub-pixel driving circuit corresponds to the second light-emitting element.
  • the sub-pixel driving circuit is used to drive the corresponding second light-emitting element to emit light.
  • the third part of the sub-pixel driving circuit is in one-to-one correspondence with the sub-light-emitting element.
  • the third part of the sub-pixel driving circuit is used to drive the corresponding The sub-light-emitting element emits light;
  • the orthographic projection of the first conductive connection part included in the second part of the sub-pixel driving circuit on the substrate overlaps with the orthographic projection of its corresponding second anode on the electrode; the third part of the sub-pixel
  • the orthographic projection of the first conductive connection portion included in the driving circuit on the substrate overlaps the orthographic projection of its corresponding third anode on the substrate.
  • the gate of the first transistor is in direct contact with the corresponding gate scanning line pattern.
  • the orthographic projection of the first electrode of the first transistor on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.
  • the orthographic projection of the second electrode of the first transistor on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.
  • the sub-pixel driving circuit further includes a seventh transistor, the gate of the seventh transistor is graphically coupled to the reset signal line, and the second electrode of the seventh transistor in the first part of the sub-pixel driving circuit is connected to the third transistor.
  • An anode coupling, a seventh overlapping area exists between the orthographic projection of the first electrode of the seventh transistor on the substrate and the orthographic projection of the corresponding compensation function pattern on the substrate, and the third The first electrodes of the seven transistors are coupled to the corresponding compensation function pattern through via holes provided in the seventh overlapping area, so as to be indirectly coupled to the corresponding initialization signal line pattern through the compensation function pattern.
  • the orthographic projection of the gate of the driving transistor on the substrate at least partially overlaps the orthographic projection of the corresponding compensation function pattern on the substrate.
  • the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the corresponding compensation function pattern on the substrate include a first overlapping portion of overlap
  • the orthographic projection of the first overlapping portion on the substrate at least partially overlaps the orthographic projection of the corresponding first anode on the substrate.
  • the first plate of the storage capacitor is made of the same material as the gate scanning line pattern and the reset signal line pattern, and the second plate of the storage capacitor is made of the same material as the initialization signal line pattern. set up;
  • the orthographic projection of the first plate of the storage capacitor on the substrate and the orthographic projection of the second plate of the storage capacitor on the substrate are located where the corresponding gate scanning line pattern is. between the orthographic projection on the substrate and the corresponding orthographic projection of the light-emitting control signal line pattern on the substrate.
  • the functional film layer further includes a gate insulating layer, and a first insulating layer located on a side of the gate insulating layer facing away from the substrate; the first plate of the storage capacitor, the The gate scanning line pattern and the reset signal line pattern are both located on the surface of the gate insulating layer facing away from the substrate; the second plate of the storage capacitor and the initialization signal line pattern are both located on the first The insulating layer faces away from the surface of the substrate.
  • the orthographic projection of the first plate of the storage capacitor on the substrate and the orthographic projection of the second plate of the storage capacitor on the substrate are both aligned with the corresponding first anode.
  • the orthographic projections on the substrate partially overlap.
  • the orthographic projection of the first plate of the storage capacitor on the substrate and the orthographic projection of the second plate of the storage capacitor on the substrate are both consistent with the corresponding compensation function graphics.
  • the orthographic projections on the substrate partially overlap.
  • the central area of the second plate of the storage capacitor includes an opening, and the orthographic projection of the opening on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.
  • the thickness difference between the compensation function layer and the power signal line layer is within a threshold range; or, the thickness difference between the compensation function layer and the data line layer The thickness difference between them is within the threshold range.
  • the display panel further includes a plurality of second light-emitting elements
  • Each of the second light-emitting elements includes a second anode, a second light-emitting pattern and a second cathode that are stacked in sequence in a direction away from the substrate;
  • the second anode includes an oppositely arranged second cathode along the second direction.
  • a fifth edge portion and a sixth edge portion, and a second middle portion located between the fifth edge portion and the sixth edge portion, the orthographic projection of the second middle portion on the substrate being the same as the The orthographic projection of the second luminous pattern on the substrate coincides;
  • the orthographic projection of the second middle portion on the substrate at least partially overlaps the orthographic projection of the corresponding power signal line pattern on the substrate, and the orthographic projection of the second middle portion on the substrate overlaps with that of the corresponding power signal line pattern.
  • the orthographic projections of the corresponding data line patterns on the substrate at least partially overlap.
  • the second luminous pattern is symmetrical about a second axis of symmetry, the second axis of symmetry extends along the first direction, and the orthographic projection of the second axis of symmetry on the substrate is located at the corresponding The power signal line pattern is inside the orthographic projection on the substrate.
  • the display panel further includes a plurality of third light-emitting elements
  • Each of the third light-emitting elements includes two sub-light-emitting elements arranged oppositely along the first direction, and each of the sub-light-emitting elements includes a third anode and a third anode, which are stacked in sequence in a direction away from the substrate.
  • a third light-emitting pattern and a third cathode the third anode includes a seventh edge portion and an eighth edge portion oppositely arranged along the second direction, and is located between the seventh edge portion and the eighth edge portion.
  • the orthographic projection of the third intermediate portion on the substrate coincides with the orthographic projection of the third luminous pattern on the substrate;
  • the orthographic projection of the third middle portion on the substrate at least partially overlaps the orthographic projection of the corresponding data line pattern on the substrate;
  • the orthographic projection of the seventh edge portion on the substrate at least partially overlaps the orthographic projection of the corresponding power signal line pattern on the substrate.
  • the first light-emitting element includes a red sub-pixel
  • the second light-emitting element includes a blue sub-pixel
  • the third light-emitting element includes a green sub-pixel
  • a second aspect of the present invention provides a display device, including the above display panel.
  • a third aspect of the present invention provides a manufacturing method of a display panel.
  • the display panel includes a plurality of sub-pixel areas arranged in an array.
  • the manufacturing method includes:
  • the functional film layer includes: a power signal line layer, a data line layer and a compensation function layer;
  • the power signal line layer includes a power signal line pattern provided in each of the sub-pixel areas,
  • the data line layer includes a data line pattern disposed in each of the sub-pixel areas, the power signal line pattern includes a first portion extending along a first direction, and the data line pattern extends along the first direction;
  • the compensation function layer includes a compensation function pattern provided in at least one of the sub-pixel areas;
  • a plurality of first light-emitting elements are fabricated on the side of the functional film layer facing away from the substrate.
  • Each of the first light-emitting elements includes: a first anode, a first anode, and a first anode, which are stacked in sequence in a direction away from the substrate.
  • the first light-emitting pattern and the first cathode; the orthographic projection of the first anode on the substrate has a first overlapping area with the corresponding orthographic projection of the power signal line pattern on the substrate.
  • the second overlapping area Located between the first overlapping area and the third overlapping area.
  • Figure 1 is a schematic layout diagram of a sub-pixel driving circuit in the related art
  • FIGS 2 to 5 are schematic structural diagrams of each film layer of the sub-pixel driving circuit described in the related art
  • Figure 6 is a first structural schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a second structural schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a corresponding working timing diagram of the sub-pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a first layout schematic diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic cross-sectional view along the A1A2 direction in Figure 9;
  • Figure 11 is a schematic layout diagram of an active layer provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic layout diagram of the first gate metal layer provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic layout diagram of the second gate metal layer provided by an embodiment of the present disclosure.
  • Figure 14 is a first layout schematic diagram of the source and drain metal layers provided by an embodiment of the present disclosure.
  • Figure 15 is a second layout schematic diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure
  • Figure 16 is a schematic layout diagram of the source and drain metal layers in Figure 15;
  • Figure 17 is a schematic cross-sectional view along the B1B2 direction in Figure 15;
  • Figure 18 is a schematic cross-sectional view along the C1C2 direction in Figure 15;
  • Figure 19 is a third layout schematic diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure.
  • Figure 20 is a fourth layout schematic diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure.
  • Figure 21 is a fifth layout schematic diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure.
  • Figure 22 is a schematic cross-sectional view along the D1D2 direction in Figure 21;
  • Figure 23 is a schematic cross-sectional view along the E1E2 direction in Figure 21;
  • Figure 24 is a schematic layout diagram of a sub-pixel driving circuit corresponding to a pixel unit provided by an embodiment of the present disclosure
  • Figure 25 is a schematic structural diagram of the first anode provided by an embodiment of the present disclosure.
  • Figure 26 is a schematic structural diagram of a second anode provided by an embodiment of the present disclosure.
  • Figure 27 is a schematic structural diagram of a third anode provided by an embodiment of the present disclosure.
  • the structure of the AMOLED display panel includes: a substrate, a plurality of sub-pixel drive circuits provided on the substrate, and a plurality of light-emitting elements provided on a side of the sub-pixel drive circuit facing away from the substrate, the light-emitting elements being connected to the
  • the sub-pixel driving circuits are in one-to-one correspondence, and the sub-pixel driving circuits are used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the display panel.
  • the sub-pixel driving circuit generally includes a plurality of thin film transistors, as shown in Figure 1.
  • Figure 1 shows that when the sub-pixel driving circuit includes seven thin film transistors M1 to M7, the seven thin film transistors The specific layout method.
  • the sub-pixel driving circuit includes an active layer as shown in Figure 2, a first metal layer as shown in Figure 3, and a second metal layer as shown in Figure 4.
  • the active layer includes an active pattern for forming the channel region of each thin film transistor (the part within the dotted box in Figure 2), and the Active pattern coupling, a doped active pattern with conductive properties (the part outside the dotted line frame in Figure 2);
  • the first metal layer includes the gate of each thin film transistor, and the scanning of the gate coupling The signal line pattern GATE, a plate CE1 of the storage capacitor in the sub-pixel driving circuit, the reset signal line pattern RST, and the light-emitting control signal line pattern EM;
  • the second metal layer includes the initialization signal line pattern VINT, and the Another electrode plate CE2 of the storage capacitor in the sub-pixel driving circuit;
  • the third metal layer includes a data line pattern DATA, a power signal line pattern VDD, and some conductive connections (such as marks 341 to 343).
  • each sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor; the display panel It also includes an initialization signal line graphic VINT, a gate scanning line graphic GATE, a light-emitting control signal line graphic EM, a reset control signal line graphic RST, a data line graphic DATA and a power supply signal line graphic VDD.
  • VINT initialization signal line graphic
  • GATE gate scanning line graphic
  • EM light-emitting control signal line graphic
  • RST reset control signal line graphic
  • VDD power supply signal line graphic
  • the plurality of sub-pixel driving circuits are distributed in an array, and are located in a one-to-one correspondence in the sub-pixel area of the display panel.
  • the plurality of sub-pixel driving circuits can be divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits, located in
  • the initialization signal line patterns VINT corresponding to the sub-pixel driving circuits in the same row are electrically connected in sequence to form an integrated structure;
  • the gate scanning line patterns GATE corresponding to the sub-pixel driving circuits in the same row are electrically connected in sequence to form an integrated structure.
  • the light-emitting control signal line patterns EM corresponding to the sub-pixel driving circuits located in the same row are electrically connected in sequence to form an integrated structure;
  • the reset control signal line patterns RST corresponding to the sub-pixel driving circuits located in the same row are electrically connected in sequence , formed into an integrated structure;
  • the data line patterns DATA corresponding to the sub-pixel driving circuits located in the same column are electrically connected in sequence to form an integrated structure;
  • the power signal line patterns VDD corresponding to the sub-pixel driving circuits located in the same column are electrically connected in sequence connected to form an integrated structure.
  • each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged sequentially along the The graphics RST all extend along the X direction, and the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits can respectively communicate with the corresponding initialization signal line pattern VINT, gate scanning line pattern GATE, luminescence control signal line pattern EM, The reset control signal line pattern RST is coupled; each column of sub-pixel drive circuits includes a plurality of sub-pixel drive circuits arranged sequentially along the Y direction.
  • the data line pattern DATA and the power signal line pattern VDD both extend along the Y direction.
  • Each column of sub-pixel drive circuits Each of the plurality of sub-pixel driving circuits included in the pixel driving circuit can be coupled to the corresponding data line pattern DATA and the power signal line pattern VDD respectively.
  • each sub-pixel driving circuit included in the display panel may include: a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , and a sixth transistor T6 .
  • the seventh transistor T7 and the storage capacitor Cst; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors.
  • the first transistor T1 has a double-gate structure.
  • the gate electrode 201g of the first transistor T1 is coupled to the corresponding gate scanning line pattern GATE.
  • the source electrode S1 of the first transistor T1 is coupled to the drain electrode D3 of the third transistor T3.
  • the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double-gate structure.
  • the gate electrode 202g of the second transistor T2 is coupled to the corresponding first reset signal line pattern RST1.
  • the source electrode S2 of the second transistor T2 is coupled to the corresponding first initialization signal line pattern VINT1.
  • the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the gate electrode 204g of the fourth transistor T4 is coupled to the corresponding gate scanning line pattern GATE, the source electrode S4 of the fourth transistor T4 is coupled to the corresponding data line pattern DATA, and the drain electrode D4 of the fourth transistor T4 is coupled to the corresponding gate scanning line pattern DATA.
  • the source S3 of the three transistors T3 is coupled.
  • the gate electrode 205g of the fifth transistor T5 is coupled to the corresponding first light-emitting control signal line pattern EM1
  • the source electrode S5 of the fifth transistor T5 is coupled to the corresponding power supply signal line pattern VDD
  • the drain electrode D5 of the fifth transistor T5 is coupled to the corresponding first light-emitting control signal line pattern EM1.
  • the source S3 of the third transistor T3 is coupled.
  • the gate electrode 206g of the sixth transistor T6 is coupled to the corresponding second light emitting control signal line pattern EM2, the source electrode S6 of the sixth transistor T6 is coupled to the drain electrode D3 of the third transistor T3, and the drain electrode D6 of the sixth transistor T6 It is coupled to the first anode 501 of the light-emitting element OLED.
  • the gate electrode 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain electrode D7 of the seventh transistor T7 is coupled to the first anode 501 of the light-emitting element OLED, and the source electrode S7 of the seventh transistor T7 is coupled to the second reset signal line pattern RST2.
  • the corresponding second initialization signal line pattern VINT2 is coupled.
  • the first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3. Therefore, the gate 203g of the third transistor T3 can be directly multiplexed as the first plate Cst1 of the storage capacitor Cst.
  • the storage capacitor Cst The second plate Cst2 is coupled with the corresponding power signal line pattern VDD.
  • the first light-emitting control signal line pattern EM1 and the second light-emitting control signal line pattern EM2 can reuse the same light-emitting control signal line pattern EM, so that they can be controlled simultaneously by the light-emitting control signal line pattern.
  • each working cycle includes a first reset period P1 , a write compensation period P2 , a second reset period P3 and a light-emitting period P4 .
  • the first reset signal input by the first reset signal line pattern RST1 is at an effective level
  • the second transistor T2 is turned on
  • the initialization signal transmitted by the first initialization signal line pattern VINT1 is input to the third
  • the gate electrode 203g of the transistor T3 causes the gate-source voltage Vgs held on the third transistor T3 in the previous frame to be cleared, thereby resetting the gate electrode 203g of the third transistor T3.
  • the first reset signal is at an inactive level
  • the second transistor T2 is turned off
  • the gate scan signal input by the gate scan line pattern GATE is at an active level
  • the first transistor T1 and the fourth transistor T2 are controlled.
  • the transistor T4 is turned on, the data line pattern DATA writes the data signal, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4.
  • the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 is turned on.
  • the transistor T3 is formed into a diode structure. Therefore, the first transistor T1, the third transistor T3, and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the third transistor can be controlled.
  • the potential of the gate 203g of T3 finally reaches Vdata+Vth
  • Vdata represents the data signal
  • Vth represents the threshold voltage of the third transistor T3.
  • the gate scanning signal is at an inactive level
  • the first transistor T1 and the fourth transistor T4 are both turned off
  • the second reset signal input by the second reset signal line pattern RST2 is at an active level
  • the control The seventh transistor T7 is turned on, and the first initialization signal transmitted by the first initialization signal line pattern VINT1 is input to the anode of the light-emitting element OLED, and the light-emitting element OLED is controlled not to emit light.
  • the light-emitting control signal written in the light-emitting control signal line pattern EM is at an effective level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line pattern VDD is input to the third
  • the source S3 of the transistor T3 and the gate 203g of the third transistor T3 are maintained at Vdata+Vth, so that the third transistor T3 is turned on.
  • the corresponding gate-source voltage of the third transistor T3 is Vdata+Vth-Vdd, and Vdd is the power supply.
  • the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element OLED, driving the corresponding light-emitting element OLED to emit light.
  • Figure 9 shows a schematic layout diagram of three adjacent sub-pixel driving circuits.
  • the layout of each film layer corresponding to the sub-pixel driving circuit is as follows:
  • An active layer (generally a low-temperature polysilicon layer), a gate insulating layer GI1, a first gate metal layer, a first interlayer insulating layer GI2, a second gate metal layer, and a second interlayer insulating layer are sequentially stacked in a direction away from the substrate 70 interlayer insulating layer ILD, first source-drain metal layer and planar layer PLN.
  • the active layer is used to form the channel area (such as: 101pg ⁇ 107pg), the source electrode formation area (such as: 101ps ⁇ 107ps) and the drain electrode formation area (such as: 101pd ⁇ 107pd), due to the doping effect, the conductivity of the active layer corresponding to the source electrode formation area and the drain electrode formation area will be better than that of the active layer corresponding to the channel area.
  • the active layer corresponding to the source electrode formation area can be used as The source electrode of each transistor (for example: S1 ⁇ S7), and the active layer corresponding to the drain formation region can be used as the drain electrode of each transistor (for example: D1 ⁇ D7).
  • the first gate metal layer is used to form the gates of each transistor in the sub-pixel driving circuit (such as: 201g ⁇ 207g), as well as the gate scanning signal line pattern GATE and the light-emitting control signal line pattern included in the display panel.
  • the second gate metal layer is used to form the second plate Cst2 of the storage capacitor Cst, the shielding pattern 301 (used to block the active layer between the two channel regions corresponding to the first transistor T1), and
  • the display panel includes a first initialization signal line pattern VINT1 and a second initialization signal line pattern VINT2.
  • the first source-drain metal layer is used to form data line patterns (eg: DATA1, DATA2, DATA3) and power signal line patterns (eg: VDD1, VDD2, VDD3) included in the display panel.
  • data line patterns eg: DATA1, DATA2, DATA3
  • power signal line patterns eg: VDD1, VDD2, VDD3
  • the gate electrode 201g of the first transistor T1 covers the first channel region 101pg, and the source electrode S1 of the first transistor T1 is located in the first source electrode formation region 101ps.
  • the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.
  • the gate electrode 202g of the second transistor T2 covers the second channel region 102pg, the source electrode S2 of the second transistor T2 is located in the second source electrode formation region 102ps, and the drain electrode D2 of the second transistor T2 is located in the second drain electrode formation region 102pd.
  • the gate electrode 203g of the third transistor T3 covers the third channel region 103pg, the source electrode S3 of the third transistor T3 is located in the third source electrode formation region 103ps, and the drain electrode D3 of the third transistor T3 is located in the third drain electrode formation region 103pd.
  • the gate electrode 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source electrode S4 of the fourth transistor T4 is located in the fourth source electrode formation region 104ps, and the drain electrode D4 of the fourth transistor T4 is located in the fourth drain electrode formation region 104pd.
  • the gate electrode 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source electrode S5 of the fifth transistor T5 is located in the fifth source electrode formation region 105ps, and the drain electrode D5 of the fifth transistor T5 is located in the fifth drain electrode formation region 105pd.
  • the gate electrode 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source electrode S6 of the sixth transistor T6 is located in the sixth source electrode formation region 106ps, and the drain electrode D6 of the sixth transistor T6 is located in the sixth drain electrode formation region 106pd.
  • the gate electrode 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source electrode S7 of the seventh transistor T7 is located in the seventh source electrode formation region 107ps, and the drain electrode D7 of the seventh transistor T7 is located in the seventh drain electrode formation region 107pd.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line VDD.
  • Figure 9 illustrates a red light-emitting element and a blue light-emitting element. At least one of the red light-emitting element and the blue light-emitting element includes an anode that can cover the power signal line pattern and the data line at the same time.
  • the anode pattern 901 included in the blue light-emitting element simultaneously covers the power signal line pattern VDD1 and the data line pattern DATA
  • the anode pattern 902 included in the red light-emitting element simultaneously covers the power signal line pattern VDD2 and data line pattern DATA2
  • the above layout method makes the anode pattern have a small step difference in the longitudinal extending direction, which is beneficial to Improve the color cast caused by light-emitting components.
  • the above-mentioned display panel has improved the color shift phenomenon caused by the light-emitting elements
  • the power signal line pattern VDD and the data line pattern DATA can produce step differences in the lateral extension direction (such as the X direction), thus
  • the subsequently formed anode pattern 902 is tilted in the lateral extension direction, and the organic light-emitting material layer 802 formed on the anode pattern 902 is also tilted, so that the display panel still has a color shift phenomenon during display.
  • embodiments of the present disclosure provide a display panel, including: a substrate 50, a functional film layer provided on the substrate 50, and a functional film layer provided on the substrate 50.
  • a plurality of first light-emitting elements on the side facing away from the substrate 50 also includes a plurality of sub-pixel regions arranged in an array;
  • the functional film layer includes: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer includes a power signal line pattern (VDD1 and VDD2 in Figure 15) provided in each of the sub-pixel areas. ), the data line layer includes a data line pattern (DATA1 and DATA2 in Figure 15) provided in each of the sub-pixel areas, the power signal line pattern includes a first portion extending along the first direction, the The data line pattern extends along the first direction; the compensation function layer includes a compensation function pattern 401 disposed in at least one of the sub-pixel areas;
  • Each of the first light-emitting elements includes: a first anode 501, a first light-emitting pattern 601 and a first cathode that are stacked in sequence in a direction away from the substrate 50; the first anode 501 is on the substrate.
  • the orthographic projection on 50 has a first overlapping area F1 with the orthographic projection of the corresponding power signal line pattern on the substrate 50 , and there is a first overlapping area F1 with the orthographic projection of the corresponding data line pattern on the substrate 50
  • the second overlapping area F2 has a third overlapping area F3 with the corresponding orthographic projection of the compensation function graphic 401 on the substrate 50.
  • the second overlapping area F2 is located in the first overlapping area F1. and the third overlapping area F3.
  • a plurality of sub-pixel areas arranged in an array can be divided into sub-pixel area columns extending along a first direction, and sub-pixel area rows extending along a second direction.
  • the sub-pixel area columns include sub-pixel areas along the first direction.
  • a plurality of sub-pixel areas arranged, the sub-pixel area row includes a plurality of sub-pixel areas arranged along the second direction; the first direction intersects the second direction, and for example, the first direction includes Y direction, the second direction includes the X direction.
  • the power signal line layer includes a power signal line pattern arranged in each of the sub-pixel areas.
  • the power signal line pattern can be selected as a grid.
  • the grid-shaped power signal line pattern includes lines along the first The first part of the direction extension.
  • the power supply signal line pattern corresponds to the sub-pixel area one-to-one, the power supply signal line pattern is located in the corresponding sub-pixel area, and the power supply signal line pattern VDD corresponding to the sub-pixel area located in the same column is in sequence. electrically connected to form an integrated structure.
  • the data line layer includes a data line pattern disposed in each of the sub-pixel areas, the data line pattern extends along the first direction, and the data line pattern corresponds to the sub-pixel area in a one-to-one manner.
  • the data line patterns are located in the corresponding sub-pixel areas, and the data line patterns DATA corresponding to the sub-pixel areas located in the same column are electrically connected in sequence to form an integrated structure.
  • the display panel also includes a plurality of first light-emitting elements located on a side of the functional film layer facing away from the substrate 50.
  • the first light-emitting elements include: stacked in sequence in a direction away from the substrate 50.
  • the first anode 501, the first light-emitting pattern 601 and the first cathode when the display panel is working, a driving signal is provided to the first anode 501 and a common signal is provided to the first cathode, so that when the first anode 501 An electric field is generated between the first cathode and the first cathode, thereby controlling the first light-emitting pattern 601 to emit light of a corresponding color; for example, the first light-emitting element includes a red light-emitting element capable of emitting red light.
  • the compensation function layer includes a compensation function pattern 401 provided in at least one of the sub-pixel areas.
  • the compensation function pattern 401 corresponds to the first light-emitting element in a one-to-one manner;
  • the The power signal line pattern and the data line pattern may be arranged alternately along the second direction, and the compensation function pattern 401 may be disposed near the corresponding first light-emitting element.
  • the first light-emitting element There is a first overlapping area F1 between the orthographic projection of the first anode 501 on the substrate 50 and the orthographic projection of the corresponding power signal line pattern on the substrate 50, and the orthographic projection of the corresponding data line pattern on the substrate 50.
  • the second overlapping area F2 is located between the first overlapping area F1 and the third overlapping area F3.
  • the compensation function pattern 401 can compensate for the step difference between the power signal line pattern and the data line pattern generated below the first anode 501 , so that in the display panel, the first anode 501 included in the first light-emitting element simultaneously covers part of the corresponding power signal line pattern, part of the corresponding data line pattern, and at least part of the corresponding compensation function pattern 401 , the first anode 501 can have a high flatness, thereby effectively reducing the color shift phenomenon produced by the display panel during display.
  • the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are oppositely arranged along the second direction, and are located between the first edge portion 501a1 and the the first middle portion 501a5 between the second edge portions 501a2; the second direction intersects the first direction; the orthographic projection of the first edge portion 501a1 on the substrate 50 includes the first overlap Region F1; the orthographic projection of the second edge portion 501a2 on the substrate 50 includes the third overlapping region F3; the orthographic projection of the first middle portion 501a5 on the substrate 50 includes the second Overlap area F2.
  • the specific structures of the first anode 501 are various.
  • the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 that are oppositely arranged along the second direction, and located on the A first middle portion 501a5 between the first edge portion 501a1 and the second edge portion 501a2.
  • the first edge portion 501a1, the second edge portion 501a2 and the middle portion may all be along the first direction. extend.
  • the orthographic projection of the first edge portion 501a1 on the substrate 50 can form the first overlapping area F1 with the orthographic projection of the corresponding power signal line pattern on the substrate 50.
  • the first overlapping region F1 The orthographic projection of the middle portion 501a5 on the substrate 50 can form the second overlapping area F2 with the orthographic projection of the corresponding data line pattern on the substrate 50, where the second edge portion 501a2 is
  • the orthographic projection on the base 50 can form the third overlapping area F3 with the corresponding orthographic projection of the compensation function pattern 401 on the base 50 .
  • the first edge portion 501a1 and the second edge portion 501a2 of the first anode 501 that are oppositely arranged along the second direction can respectively cover the corresponding power signal line pattern and the corresponding compensation function pattern.
  • the middle part of the first anode 501 between the first edge part 501a1 and the second edge part 501a2 can cover the corresponding data line pattern, so that the power signal covered by the first anode 501
  • the line patterns, data signal line patterns and compensation function patterns 401 can be evenly distributed in the area covered by the first anode 501, thereby better ensuring the flatness of the first anode 501.
  • the orthographic projection of the first edge portion 501a1 on the substrate 50 does not intersect with the orthographic projection of the first luminous pattern 601 on the substrate 50. Overlapping, the orthographic projection of the second edge portion 501a2 on the substrate 50 does not overlap with the orthographic projection of the first luminous pattern 601 on the substrate 50; the first middle portion 501a5 is on the substrate. The orthographic projection on 50 overlaps with the orthographic projection of the first luminous pattern 601 on the substrate 50 .
  • the specific layout of the first light-emitting pattern 601 can be varied.
  • the first light-emitting pattern 601 can be laid out in various ways.
  • the orthographic projection of a luminous pattern 601 on the substrate 50 is located between the orthographic projection of the first edge pattern on the substrate 50 and the orthographic projection of the second edge pattern on the substrate 50, and Overlap with the orthographic projection of the first middle portion 501a5 on the substrate 50; when the first luminous pattern 601 is laid out in this way, the first luminous pattern 601 can be located on the first anode 501
  • the surface of the middle part of the first anode 501 has a higher flatness, which is more conducive to improving the flatness of the first light-emitting pattern 601.
  • the first middle portion 501a5 is a centrally symmetrical figure, and the orthographic projection of the first middle portion 501a5 on the substrate 50 is in the same position as the first luminous pattern 601. The orthographic projections on the substrate 50 coincide with each other.
  • the first middle portion 501a5 of the first anode 501 can be selected as a centrally symmetrical figure.
  • the orthographic projection of the first middle portion 501a5 on the substrate 50 is a hexagon; in this case
  • the first luminous pattern 601 is also The centrally symmetrical pattern, such a structure of the first middle portion 501a5 and the first luminous pattern 601 is more conducive to the flatness of the first luminous pattern 601 and the uniformity of light emission.
  • the ratio between the sum of the area of the first overlapping area F1 and the area of the second overlapping area F2 and the area of the third overlapping area F3 is close to 2:1.
  • the first anode 501 when laying out the first anode 501, the power signal line pattern, the data line pattern and the compensation function pattern 401, the first anode 501, the data line pattern and the compensation function pattern 401 can be controlled in a direction perpendicular to the substrate 50.
  • the degree of overlap of an anode 501 with the power signal line pattern, the data line pattern and the compensation function pattern 401 is adjusted to adjust the flatness of the first anode 501; for example, the first anode 501 can be set
  • the ratio between the sum of the area of the overlapping region F1 and the second overlapping region F2 and the area of the third overlapping region F3 is close to 2:1; this arrangement makes the first intersection
  • the overlapping area, the second overlapping area and the third overlapping area are close to each other, that is, the power signal line pattern, the data line pattern and the compensation function pattern 401 covered by the first anode 501
  • the areas are close, which is more conducive to improving the flatness of the first anode 501 .
  • the functional film layer also includes: a gate scanning line layer, an initialization signal line layer, a reset signal line layer and a light emission control signal line layer;
  • the gate scanning line layer includes a gate scanning line pattern GATE provided in each of the sub-pixel areas, and the initialization signal line layer includes an initialization signal line pattern VINT provided in each of the sub-pixel areas.
  • the reset signal line layer includes a reset signal line pattern RST provided in each of the sub-pixel areas, and the light-emitting control signal line layer includes a light-emitting control signal line pattern EM provided in each of the sub-pixel areas; the gate electrode
  • the scanning line pattern GATE, the initialization signal line pattern VINT, the reset signal line pattern RST and the light-emitting control signal line pattern EM all extend along a second direction, and the second direction intersects the first direction.
  • the gate scanning line layer includes a gate scanning line pattern GATE disposed in each of the sub-pixel regions.
  • the gate scanning line pattern GATE extends along the second direction and is located in each sub-pixel area of the same row.
  • the gate scanning line patterns GATE corresponding to the pixel area are electrically connected in sequence to form an integrated structure.
  • the initialization signal line layer includes an initialization signal line pattern VINT provided in each of the sub-pixel areas.
  • the initialization signal line layer extends along the second direction, and the initialization signal line patterns corresponding to each sub-pixel area located in the same row
  • the signal line patterns VINT are electrically connected in sequence to form an integrated structure.
  • the reset signal line layer includes a reset signal line pattern RST disposed in each of the sub-pixel areas.
  • the reset signal line pattern RST extends along the second direction, and is located in the same row of corresponding sub-pixel areas.
  • the reset signal line patterns RST are electrically connected in sequence to form an integrated structure.
  • the light-emitting control signal line layer includes a light-emitting control signal line pattern EM arranged in each of the sub-pixel areas.
  • the light-emitting control signal line pattern EM extends along the second direction, and each sub-pixel area located in the same row corresponds to
  • the light-emitting control signal line patterns EM are electrically connected in sequence to form an integrated structure.
  • the first anode 501 further includes a third edge portion 501a3 and a fourth edge portion 501a4 arranged oppositely along the first direction, and the first middle portion 501a5 is located between the third edge portion 501a3 and the fourth edge portion 501a4; the third edge portion 501a3 is coupled to the first edge portion 501a1 and the second edge portion 501a2 respectively, and the fourth edge portion The portion 501a4 is coupled to the first edge portion 501a1 and the second edge portion 501a2 respectively; the orthographic projection of the first middle portion 501a5 on the substrate 50 corresponds to the corresponding gate scan line pattern.
  • the orthographic projection on the substrate 50 and the corresponding orthographic projection of the reset signal line pattern on the substrate 50 include a sixth overlapping area.
  • the first anode 501 further includes a third edge portion 501a3 and a fourth edge portion 501a4 that are oppositely arranged along the first direction, and the first middle portion 501a5 is located between the third edge portion 501a3 and the fourth edge portion 501a4 .
  • the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3 and the fourth edge portion 501a4 collectively surround the middle portion.
  • the orthographic projection of the third edge portion 501a3 on the substrate 50 and the corresponding initialization signal line pattern VINT can be set (the first initialization signal line pattern in Figure 15
  • the orthographic projection of VINT1) on the substrate 50 forms a fourth overlapping area; the orthographic projection of the fourth edge portion 501a4 on the substrate 50 and the corresponding light-emitting control signal line pattern EM are on the substrate 50
  • the orthographic projection on the substrate 50 forms a fifth overlapping area; the orthographic projection of the first middle portion 501a5 on the substrate 50 and the corresponding orthographic projection of the gate scan line pattern GATE on the substrate 50, and the corresponding
  • the orthographic projection of the reset signal line pattern RST (the first reset signal line pattern RST1 in Figure 15) on the substrate 50 forms a sixth overlapping area; this layout method makes it possible to The fourth overlapping area and the fifth overlapping area are arranged oppositely, and the sixth overlapping area is located between the fourth overlapping area and the fifth overlapping area, so that the sixth
  • the first anode 501 includes a main body part 501a and a via connection part 501b.
  • the main body part 501a includes the first edge part 501a1 and the second edge part 501a2. , the third edge portion 501a3, the fourth edge portion 501a4 and the first middle portion 501a5; the main body portion 501a is a centrally symmetrical figure.
  • the first anode 501 may include a coupled main body part 501a and a via connection part 501b, and the surface of the main body part 501a facing away from the substrate 50 is used to form the first light-emitting pattern 601, so
  • the via hole connection part 501b is used to couple with the sub-pixel driving circuit in the display panel through the via hole, and receive the driving signal provided by the sub-pixel driving circuit.
  • the above arrangement of the first anode 501 including the main body part 501a and the via hole connection part 501b avoids making via holes in the part of the first anode 501 used to form the first light emitting pattern 601, This ensures the luminous effect of the first light-emitting element.
  • the main body portion 501a is provided to include the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3, the fourth edge portion 501a4 and the first middle portion 501a5, and
  • the main body part 501a is set as a centrally symmetrical pattern, so that the power signal line pattern VDD (VDD1 in Figure 15), the data line pattern DATA (DATA1 in Figure 15), the gate scanning line pattern GATE, the reset signal The line pattern RST (the first reset signal line pattern RST1 in Figure 15), the lighting control signal line pattern EM, and the initialization signal line pattern VINT (the first initialization signal line pattern VINT1 in Figure 15) are the first
  • the portion covered by the anode 501 can be evenly distributed under the first anode 501, which is more conducive to improving the flatness of the first anode 501.
  • the display panel includes a first metal layer, a second metal layer and a third metal layer; the gate scanning line layer, the reset signal line layer and the light-emitting control signal line layer are located in the first metal layer; the initialization signal line layer is located in the second metal layer; the data line layer, the power signal The line layer and the compensation functional layer are located in the third metal layer; the functional film layer also includes a first insulating layer (GI2 in Figure 17) and a second insulating layer (ILD in Figure 17), The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer.
  • GI2 first insulating layer
  • ILD second insulating layer
  • the gate scanning line layer, the reset signal line layer and the The light-emitting control signal line layer is arranged on the same layer and is jointly formed into a first metal layer;
  • the data line layer, the power signal line layer and the compensation function layer are arranged on the same layer and is jointly formed into a third metal layer.
  • the initialization signal line layer is formed as a second metal layer, and the second metal layer and the first metal layer are arranged in different layers.
  • an insulating layer can be formed between adjacent metal layers.
  • the functional film layer further includes a first insulating layer and a second insulating layer, the first insulating layer is located between the first metal layer and the second metal layer, the second insulating layer is located between the second metal layer and the third metal layer .
  • the layout space in the display panel is utilized to the maximum extent, which is more conducive to the development of thinner display panels.
  • the compensation function pattern 401 is made of conductive material and coupled with the initialization signal line pattern VINT (the first initialization signal line pattern VINT1 in Figure 15).
  • the material of the compensation function graphic 401 can be set according to actual needs.
  • it includes conductive materials or insulating materials.
  • the compensation function graphic 401 is made of conductive materials, the compensation function and the fixed signal can be combined.
  • the output terminal is coupled so that the compensation function pattern 401 has a fixed potential, thereby preventing the compensation function pattern 401 from being in a floating state and affecting the stability of the display panel.
  • the initialization signal line pattern VINT can be multiplexed as a fixed potential output terminal. Since the initialization signal line pattern VINT is used to transmit an initialization signal with a fixed potential, the compensation function pattern 401 and the initialization signal The line pattern VINT coupling enables the compensation function pattern 401 to have the same fixed potential as the initialization signal.
  • the above-mentioned multiplexing of the initialization signal line pattern VINT as the fixed potential output terminal not only avoids the need to make an additional fixed potential output terminal in the display substrate specifically used to provide a fixed potential for the compensation function graphic 401, but is also effective
  • the layout space of the functional film layer is improved; moreover, the voltage of the initialization signal line is strengthened, making the voltage of the initialization signal transmitted on the initialization signal line more stable, which is more conducive to the stable operation of the sub-pixel drive circuit. performance.
  • the orthographic projection of the compensation function pattern 401 on the substrate 50 can be set to be the same as the initialization signal line pattern VINT.
  • the orthographic projection of the signal line pattern VINT on the substrate 50 has an overlapping area. In this way, by arranging via holes in the overlapping area, the compensation function pattern 401 and the initialization signal line pattern VINT can be coupled. .
  • the compensation function graphic 401 is arranged on the same layer as the data line graphic DATA.
  • the compensation function graphics 401 and the data line graphics DATA can be arranged on the same layer.
  • This layout method avoids the compensation function graphics 401 occupying a separate layer, thereby This is more conducive to thinning the display panel.
  • the compensation function pattern 401 and the data line pattern DATA can be made of the same material. This arrangement allows the compensation function pattern 401 and the data line pattern DATA to be formed in the same patterning process, thereby The production process of the display panel is effectively simplified and the production cost of the display panel is saved.
  • the display panel further includes: a plurality of sub-pixel driving circuits, a first part of the sub-pixel driving circuits in the plurality of sub-pixel driving circuits corresponding to the first light-emitting element, and the first part of the sub-pixel driving circuit is in a one-to-one correspondence with the first light-emitting element.
  • a sub-pixel driving circuit is used to drive the corresponding first light-emitting element to emit light; the sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor.
  • the gate electrode of the first transistor is coupled to the corresponding gate scanning line pattern GATE, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the third electrode of the first transistor is coupled to the corresponding gate scanning line pattern GATE.
  • Two electrodes are coupled to the gate of the driving transistor; the gate of the second transistor is coupled to the corresponding reset signal line pattern RST, and the first electrode of the second transistor is coupled to the corresponding initialization signal.
  • the line pattern VINT is coupled, the second electrode of the second transistor is coupled with the gate of the driving transistor; the gate of the fourth transistor is coupled with the corresponding gate scanning line pattern GATE, the The first electrode of the fourth transistor is coupled to the corresponding data line pattern DATA, the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; the first electrode of the driving transistor is coupled to the corresponding data line pattern DATA.
  • the power signal line pattern VDD is coupled, the second electrode of the driving transistor is coupled to the corresponding first light-emitting element; the first plate of the storage capacitor is coupled to the gate of the driving transistor , the second plate of the storage capacitor is coupled to the corresponding power signal line pattern VDD.
  • the functional film layer includes n+1 power signal line patterns VDD, n+1 data line patterns DATA, n+1 gate scan line patterns GATE, and n+1 initialization signal line patterns VINT. , n+1 reset signal line patterns RST and n+1 light-emitting control signal line patterns EM, the display panel includes a plurality of sub-pixel driving circuits corresponding to the sub-pixel areas one-to-one, the plurality of sub-pixel driving circuits It can be divided into n+1 row sub-pixel driving circuits, and can be divided into n+1 column sub-pixel driving circuits; the n+1 power supply signal line pattern VDD corresponds to the n+1 column sub-pixel driving circuit, and the n The +1 data line pattern DATA corresponds to the n+1 column sub-pixel driving circuit in a one-to-one correspondence.
  • the n+1 gate scanning line pattern GATE corresponds to the n+1 row sub-pixel driving circuit in a one-to-one correspondence.
  • the n+1 The initialization signal line pattern VINT has a one-to-one correspondence with the n+1 rows of sub-pixel drive circuits
  • the n+1 reset signal line patterns RST have a one-to-one correspondence with the n+1 rows of sub-pixel drive circuits
  • the n+1 light emission control circuits have a one-to-one correspondence.
  • the signal line pattern EM has a one-to-one correspondence with the n+1 row sub-pixel driving circuit.
  • the following takes the sub-pixel driving circuit located in the nth row and nth column as an example to describe in detail its specific structure and connection methods with various signal line patterns.
  • the sub-pixel driving circuit includes: a driving transistor (ie, a third transistor T3, described as the third transistor T3 below), a first transistor T1, a second transistor T2, a fourth transistor T4, and Storage capacitor Cst; the first transistor T1, the second transistor T2 and the fourth transistor T4 are P-type transistors.
  • a driving transistor ie, a third transistor T3, described as the third transistor T3 below
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are P-type transistors.
  • the gate electrode 201g of the first transistor T1 is coupled to the gate scanning line pattern GATE, and the first electrode (ie, the source electrode S1) of the first transistor T1 is connected to the second electrode (ie, the source electrode S1) of the third transistor T3. That is, the drain electrode D3) is coupled, and the second electrode (ie, the drain electrode D1) of the first transistor T1 is coupled with the gate electrode 203g of the third transistor T3.
  • the gate electrode 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, and the first electrode (ie, source S2) of the second transistor T2 is coupled to the first initialization signal line pattern VINT1.
  • the second electrode (ie, the drain D2) of the second transistor T2 is coupled with the gate electrode 203g of the third transistor T3.
  • the gate electrode 204g of the fourth transistor T4 is coupled to the gate scanning line pattern GATE, and the first electrode (ie, the source electrode S4) of the fourth transistor T4 is coupled to the data line pattern DATA.
  • the second electrode (ie, the drain D4) of the fourth transistor T4 is coupled to the first electrode (ie, the source S3) of the third transistor T3.
  • the first electrode (i.e., source S3) of the third transistor T3 is coupled to the power signal line pattern VDD, and the second electrode (i.e., the drain D3) of the third transistor T3 is coupled to the corresponding light-emitting element OLED. catch.
  • the first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.
  • the functional film layer further includes: a light emission control signal line pattern and a second reset signal line pattern RST2;
  • the sub-pixel driving circuit further includes: a fifth transistor, a sixth transistor and a seventh transistor; wherein , the gate of the fifth transistor is coupled to the light-emitting control signal line pattern, the first electrode of the fifth transistor is coupled to the power signal line pattern VDD, and the second electrode of the fifth transistor is coupled to The first electrode of the driving transistor is coupled; the gate electrode of the sixth transistor is graphically coupled to the light-emitting control signal line, and the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor.
  • the second electrode of the sixth transistor is coupled to the corresponding light-emitting element; the gate electrode of the seventh transistor is graphically coupled to the second reset signal line, and the first electrode of the seventh transistor is coupled to the The initialization signal line is coupled, and the second electrode of the seventh transistor is coupled with the second electrode of the sixth transistor.
  • the gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM
  • the first electrode (i.e., source S5) of the fifth transistor T5 is coupled to the power signal line pattern VDD
  • the second electrode (i.e., the drain D5) of the fifth transistor T5 is coupled to the driving transistor.
  • the first electrode (ie, the source S3) of the third transistor T3) is coupled.
  • the gate electrode 206g of the sixth transistor T6 is coupled to the light-emitting control signal line pattern EM, and the first electrode (ie, source S6) of the sixth transistor T6 is connected to the driving transistor (ie, the third transistor T3).
  • the second electrode (i.e., the drain D3) of the sixth transistor T6 is coupled, and the second electrode (i.e., the drain D6) of the sixth transistor T6 is coupled with the corresponding light-emitting element OLED;
  • the gate 207g of the seventh transistor T7 is connected to the second reset signal line pattern RST2 (for example, the second reset signal line pattern RST2 may be the reset signal line corresponding to the n+1th row sub-pixel driving circuit).
  • pattern RST the first electrode (ie, the source S7) of the seventh transistor T7 is coupled with the second initialization signal line pattern VINT2 (for example, the second initialization signal line pattern VINT2 may be the nth
  • the initialization signal line pattern VINT corresponding to the +1 row sub-pixel driving circuit is coupled, and the second electrode (ie, the drain D7) of the seventh transistor T7 is connected to the second electrode (ie, the drain D6) of the sixth transistor T6. ) coupling.
  • the above embodiment provides a display panel in which the sub-pixel driving circuit further includes the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, so that the sub-pixel driving circuit can only drive the corresponding light-emitting element OLED during the light-emitting phase.
  • Emitting light avoids the phenomenon of abnormal light emission of the light-emitting element OLED, thereby better improving the display quality of the display panel.
  • the sub-pixel driving circuit further includes a first conductive connection portion 701, and the second electrode (ie, the drain D1) of the first transistor T1 passes through the first conductive connection portion 701.
  • a conductive connection part 701 is coupled to the gate electrode of the driving transistor (ie, the gate electrode 203g of the third transistor T3); the display panel also includes a third metal layer, and the first conductive connection part 701 is located on the third metal layer.
  • the orthographic projection of the first conductive connection part included in the first partial sub-pixel driving circuit on the substrate does not overlap with the orthographic projection of the corresponding first anode 501 on the substrate.
  • the compensation function pattern 401 may be disposed between the data line pattern (such as DATA1) and the first conductive connection part included in the first part of the sub-pixel driving circuit, the data line pattern is located in the first part of the sub-pixel driving circuit Just below the first anode; in the display panel with the above structure, the gate of the driving transistor (ie, the gate 203g of the third transistor T3) can be separated from the data line pattern (such as DATA1) through the compensation function pattern 401. This can better avoid signal changes on the data line pattern and crosstalk on the gate potential of the driving transistor. Moreover, the display panel with the above structure also avoids short circuit between the first conductive connection part 701 and the compensation function pattern 401 .
  • the compensation function pattern 401 can be coupled with the initialization signal line pattern (such as VINT1), so that the compensation function pattern 401 has a fixed potential, thereby further avoiding The signal changes produce crosstalk on the gate potential of the driving transistor.
  • VINT1 initialization signal line pattern
  • the first conductive connection portion 701 is located on the third metal layer, so that the first conductive connection portion 701 can be formed with other patterns included in the third metal layer in one patterning process, thereby It greatly simplifies the manufacturing process of the display substrate.
  • the display panel further includes a plurality of second light-emitting elements and a plurality of third light-emitting elements; each of the second light-emitting elements includes, in a direction away from the substrate, The second anode 502, the second light-emitting pattern 602 and the second cathode are stacked in sequence; each third light-emitting element includes two sub-light-emitting elements arranged oppositely along the first direction, each of the sub-light-emitting elements Both include a third anode 503, a third light-emitting pattern 603 and a third cathode that are stacked in sequence in a direction away from the substrate;
  • the plurality of sub-pixel driving circuits also include a second part of a sub-pixel driving circuit and a third part of a sub-pixel driving circuit.
  • the second part of the sub-pixel driving circuit corresponds to the second light-emitting element in a one-to-one manner.
  • the second part of the sub-pixel driving circuit corresponds to the second light-emitting element.
  • the sub-pixel driving circuit is used to drive the corresponding second light-emitting element to emit light.
  • the third part of the sub-pixel driving circuit is in one-to-one correspondence with the sub-light-emitting element.
  • the third part of the sub-pixel driving circuit is used to drive the corresponding The sub-light-emitting element emits light;
  • the orthographic projection of the first conductive connection part included in the second part of the sub-pixel driving circuit on the substrate overlaps with the orthographic projection of its corresponding second anode 502 on the electrode; the third part of the sub-pixel The orthographic projection of the first conductive connection portion included in the pixel driving circuit on the substrate overlaps with the orthographic projection of its corresponding third anode 503 on the substrate.
  • the above arrangement is to set the orthographic projection of the first conductive connection part included in the second part of the sub-pixel driving circuit on the substrate to overlap with the orthographic projection of the corresponding second anode 502 on the electrode; and the third The orthographic projection of the first conductive connection part included in the three-part sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the corresponding third anode 503 on the substrate, so that the second anode 502 and the The third anode 503 has higher flatness.
  • the gate electrode 201g of the first transistor T1 is in direct contact with the corresponding gate scanning line pattern GATE.
  • the gate electrode 201g of the first transistor T1 and the corresponding gate scan line pattern GATE can be made in the same layer and formed into an integrated structure. This not only makes the gate electrode 201g of the first transistor T1 and the corresponding gate scan line pattern GATE
  • the corresponding gate scanning line pattern GATE can be formed in the same patterning process, and the gate of the formed first transistor can be in direct contact with the corresponding gate scanning line pattern GATE, without the need to set additional A conductive connection portion used to connect the gate of the first transistor and the corresponding gate scan line pattern GATE.
  • the gate electrode of the second transistor and the gate electrode of the seventh transistor may be integrated with the corresponding gate scan line pattern GATE, or the gate electrode of the second transistor,
  • the gate electrode of the seventh transistor may be in direct contact with the corresponding gate scanning line pattern GATE, or the gate electrode of the second transistor and the gate electrode of the seventh transistor may be used as the corresponding gate electrode.
  • the orthographic projection of the first electrode of the first transistor on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50; and/ Or, the orthographic projection of the second electrode of the first transistor on the substrate 50 at least partially overlaps with the corresponding orthographic projection of the compensation function pattern 401 on the substrate 50 .
  • the orthographic projection of the compensation function pattern 401 on the substrate 50 can be set to be in contact with the second electrode of the first transistor T1 (ie, as shown in FIG. 15 ).
  • the orthographic projection of the N1 node in 15) on the substrate 50 at least partially overlaps; and/or the orthographic projection of the compensation function pattern 401 on the substrate 50 can be set to overlap with the orthographic projection of the first transistor T1 Orthographic projections of the first electrode (formed at 101 ps in FIG. 15 ) on the substrate 50 at least partially overlap.
  • the above arrangement enables the compensation function pattern 401 to cover the second electrode of the first transistor T1 and/or the first electrode of the first transistor T1 in a direction perpendicular to the substrate 50, so that The second electrode of the first transistor T1 and/or the first electrode of the first transistor T1 acts as a shield to avoid data transmitted on the data line pattern DATA adjacent to the first transistor T1
  • crosstalk occurs to the first transistor T1; at the same time, because the second electrode of the first transistor T1 is coupled to the gate electrode 203g of the third transistor T3, the first electrode of the first transistor T1 is coupled to the gate electrode 203g of the third transistor T3.
  • the second electrode of the third transistor T3 is coupled, thereby further avoiding crosstalk on the third transistor T3 when the data signal transmitted on the data line pattern DATA adjacent to the first transistor T1 changes.
  • the orthographic projection of the first electrode of the first transistor T1 on the substrate does not intersect with the orthographic projection of the corresponding compensation function pattern 401 on the substrate. overlap; and/or, the orthographic projection of the second electrode of the first transistor T1 on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.
  • the above arrangement not only allows a wider distance between the compensation function pattern 401 and the first conductive connection part 701, but also avoids short circuit failure between the compensation function pattern 401 and the first conductive connection part 701; Moreover, while ensuring the flatness of the first anode 501, the formation of parasitic capacitance between the compensation function pattern 401 and the shielding pattern 301 is avoided.
  • the sub-pixel driving circuit further includes a seventh transistor T7.
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (RST2 in Figure 15).
  • the first sub-pixel The second electrode of the seventh transistor T7 in the pixel driving circuit is coupled to the first anode 501, and the first electrode of the seventh transistor in the first sub-pixel driving circuit is on the positive side of the substrate 50.
  • the hole is coupled to the corresponding compensation function pattern 401, so as to be indirectly coupled to the corresponding initialization signal line pattern VINT through the compensation function pattern 401.
  • a via hole can be made in the seventh overlapping area, so that the first electrode of the seventh transistor can be coupled to the compensation function pattern 401 through the via hole, and at the same time, since the compensation function pattern 401 and the initialization The signal line is coupled. Therefore, the first electrode of the seventh transistor can be indirectly coupled to the initialization signal line through the compensation function pattern 401 .
  • the first electrode of the seventh transistor is indirectly coupled to the initialization signal line through the compensation function pattern 401, which avoids the need to make a special first electrode for coupling the seventh transistor and the initialization signal line.
  • the conductive connection portion of the initialization signal line simplifies the manufacturing process of the display panel and saves production costs.
  • the orthographic projection of the compensation function pattern 401 on the substrate 50 may overlap with the orthographic projection of the second pole of the seventh transistor on the substrate 50; or, As shown in FIG. 19 , the orthographic projection of the compensation function pattern 401 on the substrate 50 may not overlap with the orthographic projection of the second electrode of the seventh transistor on the substrate 50 .
  • the orthographic projection of the gate of the driving transistor on the substrate 50 at least partially intersects with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50 .
  • the orthographic projection of the gate of the driving transistor ie, the gate 203g of the third transistor T3
  • the orthographic projections on the substrate 50 at least partially overlap, so that the compensation function pattern 401 can cover at least part of the gate of the driving transistor, thereby shielding the gate of the driving transistor to avoid contact with the driving transistor.
  • the orthographic projection of the gate of the driving transistor on the substrate 50 and the corresponding orthographic projection of the compensation function pattern 401 on the substrate 50 include overlapping The first overlapping portion; the orthographic projection of the first overlapping portion on the substrate 50 at least partially overlaps with the corresponding orthographic projection of the first anode 501 on the substrate 50 .
  • the above arrangement is such that in the direction perpendicular to the substrate 50 , the gate electrode of the driving transistor, the compensation function pattern 401 and the first anode 501 have a common overlapping area, so that the compensation
  • the functional pattern 401 can not only avoid crosstalk on the driving transistor when the data signal transmitted on the data line pattern DATA adjacent to the driving transistor changes, but can also avoid crosstalk on the driving transistor when the driving signal transmitted on the first anode 501 changes. , causing crosstalk to the drive transistor.
  • the compensation function pattern 401 can be disposed between the gate of the driving transistor and the first anode 501 , so that the compensation function pattern 401 can better avoid transmission on the first anode 501 When the drive signal changes, crosstalk will occur to the drive transistor.
  • the first plate Cst1 of the storage capacitor Cst is made of the same material as the gate scanning line pattern GATE and the reset signal line pattern RST.
  • the second plate Cst2 is made of the same material as the initialization signal line pattern VINT; the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50, and the second plate Cst2 of the storage capacitor Cst.
  • the orthographic projections on the substrate 50 are located at the corresponding orthographic projections of the gate scanning line pattern GATE on the substrate 50 and the corresponding luminescence control signal line patterns EM on the substrate 50 between orthographic projections.
  • some of the functional graphics in the display panel can be made of the same material.
  • some of the functional graphics in the display panel can be made with conductive properties.
  • the graphics are made of the same material with conductive properties, and some of the functional graphics with insulating properties in the display panel are made of the same material with insulating properties.
  • the first plate Cst1 of the storage capacitor Cst can be made of the same material as the gate scanning line pattern GATE and the reset signal line pattern RST, and the second plate Cst2 of the storage capacitor Cst can be made of the same material.
  • the same material is used as the initialization signal line pattern VINT; this arrangement enables the first plate Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE and the reset signal line pattern RST to be made.
  • the same process equipment is used to form in the same manufacturing environment; similarly, the same process equipment can also be used to manufacture the second plate Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT in the same manufacturing environment. formed; therefore, this arrangement method can effectively simplify the manufacturing process of the display panel and save the manufacturing cost of the display panel.
  • an orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50 can be set, as well as the storage
  • the orthographic projection of the second plate Cst2 of the capacitor Cst on the substrate 50 is located at the corresponding orthographic projection of the gate scanning line pattern GATE on the substrate 50 and the corresponding light-emitting control signal line pattern. Between the orthographic projections on the substrate 50; this arrangement not only ensures that the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst can have a certain positive direction in the direction perpendicular to the substrate 50.
  • the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst are in contact with the gate scanning line pattern GATE and the light emission control signal in the direction perpendicular to the substrate 50 Line patterns overlap, so that the storage capacitor Cst does not form other parasitic capacitances with the gate scanning line pattern GATE and the light-emitting control signal line pattern EM, ensuring that the sub-pixel driving circuit Stable working performance.
  • the functional film layer also includes a gate insulating layer (GI1 in Figure 17), and a first insulating layer (such as GI1) located on a side of the gate insulating layer facing away from the substrate 50.
  • GI2 in Figure 17 the first plate Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE and the reset signal line pattern RST are all located on the side of the gate insulating layer facing away from the substrate 50 Surface; the second plate Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT are both located on the surface of the first insulating layer facing away from the substrate 50 .
  • the functional film layer also includes the gate insulating layer and the first insulating layer.
  • the gate insulating layer is used to insulate between the gate electrode and the active layer in the thin film transistor.
  • the third insulating layer An insulating layer is used to insulate conductive functional graphics arranged in different layers in the display substrate.
  • the first plate Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE and the reset signal line pattern RST can be arranged on the The gate insulating layer faces away from the surface of the substrate 50; in this way, when the same material is used to make the first plate Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE and the reset signal line pattern RST , the first plate Cst1 of the storage capacitor Cst, the gate scanning line pattern GATE and the reset signal line pattern RST can be formed simultaneously in the same patterning process.
  • the second plate Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT can be disposed on the surface of the first insulating layer facing away from the substrate 50; in this way, the same material is used to make the device.
  • the second plate Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT are formed, the second plate Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT can be formed simultaneously in the same patterning process.
  • the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 overlap with the corresponding orthographic projections of the first anode 501 on the substrate 50 .
  • the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50 can be set , and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 overlaps with the intersection of the corresponding orthographic projection of the first anode 501 on the substrate 50; because the third An anode 501 and the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst are arranged in different layers. Therefore, this layout method avoids the first connection between the first anode 501 and the storage capacitor Cst. When a short circuit occurs between the electrode plate Cst1 and the second electrode plate Cst2, the layout space of the display panel is utilized to a greater extent.
  • the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 overlap with the corresponding orthographic projections of the compensation function graphics 401 on the substrate 50 .
  • the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst are on the substrate 50
  • the functional pattern 401 can not only avoid crosstalk on the storage capacitor Cst when the data signal transmitted on the data line pattern DATA adjacent to the storage capacitor Cst changes, but can also prevent the driving signal transmitted on the first anode 501 from occurring. When changing, crosstalk occurs to the storage capacitor Cst, thereby better ensuring the stability of the operation of the sub-pixel driving circuit in the display panel.
  • the central area of the second plate Cst2 of the storage capacitor Cst includes an opening 302 , and the orthographic projection of the opening 302 on the substrate 50 corresponds to The orthographic projections of the compensation function graphics 401 on the substrate 50 do not overlap.
  • the area where the opening 302 on the second plate Cst2 of the storage capacitor Cst is generally used to form a via hole and a conductive part passing through the via hole, and the via hole and the conductive part are used to connect the via hole and the conductive part.
  • the functional graphics on the upper and lower sides of the diode plate are coupled together.
  • the orthographic projection of the opening 302 on the substrate 50 to not overlap with the orthographic projection of the corresponding compensation function graphic 401 on the substrate 50 , it can be better. This prevents the compensation function pattern 401 from being short-circuited with the conductive portion at the opening 302, thereby better ensuring the stability of the operation of the sub-pixel driving circuit in the display panel.
  • the orthographic projection of the opening 302 on the base 50 can also be set to partially overlap with the corresponding orthographic projection of the compensation function graphic 401 on the base 50 , it is only necessary to ensure that the compensation function pattern 401 and the conductive part at the opening 302 will not be short-circuited.
  • the orthographic projection of the compensation function graphic 401 on the substrate 50 can be set to partially overlap with the orthographic projection of the shielding graphic 301 on the substrate. ; Or, as shown in Figure 20, in some embodiments, the orthographic projection of the compensation function graphic 401 on the substrate 50 can be set not to overlap with the orthographic projection of the shielding graphic 301 on the substrate. .
  • the thickness difference between the compensation function layer and the power signal line layer is within a threshold range; or, the thickness difference between the compensation function layer and the data The thickness difference between line layers is within the threshold range.
  • the thickness of the compensation function pattern 401 in the direction perpendicular to the base 50 can be set according to actual needs. For example, in the direction perpendicular to the base 50 , set the thickness difference between the compensation function layer and the power signal line layer to be within the threshold range; or, set the thickness difference between the compensation function layer and the data line layer to be within the threshold range; this setting The method enables the compensation function layer to well compensate for the step difference produced by the power signal line layer and the data line layer.
  • the threshold range can be set to less than or equal to 0.1 ⁇ m, so that in the direction perpendicular to the substrate 50, the thickness of the compensation function layer, the power signal line layer and the data line layer Close to each other, thereby better ensuring the compensation effect for step differences.
  • the display panel further includes a plurality of second light-emitting elements; each of the second light-emitting elements includes a plurality of second light-emitting elements that are stacked in sequence in a direction away from the substrate 50 .
  • the orthographic projection of the second middle portion 502a3 on the substrate 50 at least partially overlaps the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50, and the second middle portion 502a3 is on the substrate.
  • the orthographic projection on 50 at least partially overlaps with the orthographic projection of the corresponding data line pattern DATA on the substrate 50 .
  • the display panel may further include a second light-emitting element, the second light-emitting element has a different light-emitting color from the first light-emitting element, and the second light-emitting element may include a light emitting element extending in a direction away from the substrate 50 .
  • the second anode 502, the second light-emitting pattern 602 and the second cathode are stacked in sequence.
  • the second anode 502 is coupled to the corresponding second sub-pixel driving circuit in the display panel, and receives the input signal from the second sub-pixel driving circuit.
  • the driving signal is provided, the second cathode receives the common signal, and under the joint action of the second anode 502 and the second cathode, the second light-emitting pattern 602 emits light of a corresponding color.
  • the structure of the second anode 502 is various.
  • the second anode 502 includes a fifth edge portion 502a1 and a sixth edge portion 502a2 that are oppositely arranged along the second direction, and are located on the fifth edge portion 502a1 and a sixth edge portion 502a2 .
  • the orthographic projection of the second middle portion 502a3 on the substrate 50 can be set to coincide with the orthographic projection of the second light-emitting pattern 602 on the substrate 50.
  • the orthographic projection of the two middle portions 502a3 on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50.
  • the second middle portion 502a3 is on the substrate 50.
  • the orthographic projection at least partially overlaps the orthographic projection of the corresponding data line pattern DATA on the substrate 50; this layout allows the middle part of the second anode 502 to evenly cover the power signal line pattern VDD and
  • the data line pattern DATA allows the middle portion of the second anode 502 to have a higher flatness, so that the second light-emitting pattern 602 is formed on the second middle portion 502a3 of the second anode 502 At this time, it can be ensured that the second light-emitting pattern 602 has a high flatness, thereby ensuring the light-emitting effect of the second light-emitting element and weakening the color shift phenomenon that occurs when the display panel displays.
  • the second luminous pattern 602 is symmetrical about a second axis of symmetry, the second axis of symmetry extends along the first direction, and the second axis of symmetry is on the substrate.
  • the orthographic projection on 50 is located inside the corresponding orthographic projection of the power signal line pattern VDD on the substrate 50 .
  • the structure of the second light-emitting pattern 602 can be set according to actual needs.
  • the second light-emitting pattern 602 is set to be an axially symmetrical pattern, which is more conducive to improving the uniformity of the light emitted by the second light-emitting element. .
  • the second luminous pattern 602 can be set to be symmetrical about a second axis of symmetry, the second axis of symmetry extends along the first direction, and the orthographic projection of the second axis of symmetry on the substrate 50 is located at The corresponding power supply signal line pattern VDD is inside the orthographic projection on the substrate 50.
  • This layout allows the central part of the second light emitting pattern 602 to cover the power supply signal line pattern VDD, and due to the The power signal line pattern VDD extends along the first direction and has a wider width perpendicular to the first direction. Therefore, most of the second light emitting pattern 602 is formed on the power signal line pattern. VDD, thereby better ensuring the flatness of the second light-emitting pattern 602 and weakening the color shift phenomenon that occurs when the display panel displays.
  • the display panel further includes a plurality of third light-emitting elements; each of the third light-emitting elements includes two sub-light emitting elements arranged oppositely along the first direction.
  • Each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603 and a third cathode that are stacked in sequence in a direction away from the substrate 50;
  • the third anode 503 includes a third anode 503 along the The seventh edge portion 503a1 and the eighth edge portion 503a2 are oppositely arranged in the second direction, and the third middle portion is located between the seventh edge portion 503a1 and the eighth edge portion 503a2.
  • the third middle portion is at The orthographic projection on the base 50 coincides with the orthographic projection of the third luminous pattern 603 on the base 50;
  • the orthographic projection of the third middle portion on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding data line pattern DATA on the substrate 50 ; the seventh edge portion 503a1 is on the substrate 50 The orthographic projection of the corresponding power signal line pattern VDD on the substrate 50 at least partially overlaps.
  • the display panel may further include a plurality of third light-emitting elements, each of the third light-emitting elements including two sub-light-emitting elements arranged oppositely along the first direction, each of the sub-light-emitting elements being in contact with the The first light-emitting element and the second light-emitting element emit light in different colors.
  • the sub-light-emitting element may include a third anode 503, a third light-emitting pattern 603 and a third anode 503, a third light-emitting pattern 603 and a third light-emitting pattern 603, which are stacked sequentially in a direction away from the substrate 50.
  • the third cathode may include a third anode 503, a third light-emitting pattern 603 and a third anode 503, a third light-emitting pattern 603 and a third light-emitting pattern 603, which are stacked sequentially in a direction away from the substrate 50.
  • the third cathode may include
  • the third anode 503 is coupled to the corresponding third sub-pixel driving circuit in the display panel and receives the driving signal provided by the third sub-pixel driving circuit.
  • the third cathode receives the common signal. Under the joint action of the third anode 503 and the third cathode, the third light-emitting pattern 603 emits light of a corresponding color.
  • the third anode 503 has various structures.
  • the third anode 503 includes a seventh edge portion and an eighth edge portion that are oppositely arranged along the second direction, and are located on the seventh edge portion. and a third middle portion between said eighth edge portion.
  • the orthographic projection of the third middle portion on the substrate 50 can be set to coincide with the orthographic projection of the third light-emitting pattern 603 on the substrate 50; the third The orthographic projection of the middle part on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding data line pattern DATA on the substrate 50; the orthographic projection of the seventh edge part on the substrate 50 corresponds to The orthographic projection of the power signal line pattern VDD on the substrate 50 at least partially overlaps; this layout makes the overlap area of the third anode 503 with the corresponding power signal line pattern VDD and data line pattern DATA smaller, It can ensure that the third light-emitting pattern 603 has a high flatness, thus ensuring the light-emitting effect of the third light-emitting element and weakening the color shift phenomenon that occurs when the display panel displays.
  • the first light-emitting element includes a red sub-pixel
  • the second light-emitting element includes a blue sub-pixel
  • the third light-emitting element includes a green sub-pixel
  • the light-emitting colors of the first light-emitting element, the second light-emitting element and the third light-emitting element can be set according to actual needs.
  • the first light-emitting element includes a red sub-pixel
  • the third light-emitting element includes a red sub-pixel.
  • the two light-emitting elements include blue sub-pixels
  • the third light-emitting element includes green sub-pixels.
  • An embodiment of the present disclosure also provides a display device, including the display panel provided in the above embodiment.
  • the compensation function pattern 401 can compensate for the step difference between the power signal line pattern VDD and the data line pattern DATA generated below the first anode 501, so that in the display panel,
  • the first anode 501 included in the first light-emitting element simultaneously covers part of the corresponding power signal line pattern VDD, part of the corresponding part of the data line pattern DATA, and at least part of the corresponding compensation function pattern 401, the first anode 501 It can have a higher flatness, thereby effectively reducing the color shift phenomenon caused by the display panel during display; therefore, the display device provided by the embodiment of the present disclosure also has the above beneficial effects when including the display panel provided by the above embodiment. .
  • the display device may be any product or component with a display function such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • Embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the display panel includes a plurality of sub-pixel areas arranged in an array.
  • the manufacturing method includes:
  • a functional film layer is made on the substrate 50; the functional film layer includes: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer includes a power signal line pattern provided in each of the sub-pixel areas.
  • VDD the data line layer includes a data line pattern DATA disposed in each of the sub-pixel areas, the power signal line pattern VDD includes a first portion extending along the first direction, and the data line pattern DATA extends along the first direction.
  • the compensation function layer includes a compensation function pattern 401 provided in at least one of the sub-pixel areas;
  • a plurality of first light-emitting elements are fabricated on the side of the functional film layer facing away from the substrate 50 .
  • Each of the first light-emitting elements includes: first light-emitting elements that are stacked sequentially in a direction away from the substrate 50 .
  • the anode 501, the first light-emitting pattern 601 and the first cathode; the orthographic projection of the first anode 501 on the substrate 50 and the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50 exist.
  • a plurality of sub-pixel areas arranged in an array can be divided into sub-pixel area columns extending along a first direction, and sub-pixel area rows extending along a second direction.
  • the sub-pixel area columns include sub-pixel areas along the first direction.
  • a plurality of sub-pixel areas arranged, the sub-pixel area row includes a plurality of sub-pixel areas arranged along the second direction; the first direction intersects the second direction, and for example, the first direction includes Y direction, the second direction includes the X direction.
  • the power signal line layer includes a power signal line pattern VDD arranged in each of the sub-pixel areas.
  • the power signal line pattern VDD can be selected as a grid.
  • the grid-shaped power signal line pattern VDD includes edges along all the first part extending in the first direction.
  • the power supply signal line pattern VDD corresponds to the sub-pixel area column one-to-one, and the power supply signal line pattern VDD is located in each sub-pixel area included in the corresponding sub-pixel area column.
  • the data line layer includes a data line pattern DATA disposed in each of the sub-pixel areas, the data line pattern DATA extends along the first direction, and the data line pattern DATA is aligned with the sub-pixel area rows one by one.
  • the data line pattern DATA is located in each sub-pixel area included in the corresponding sub-pixel area column.
  • the display panel also includes a plurality of first light-emitting elements located on a side of the functional film layer facing away from the substrate 50.
  • the first light-emitting elements include: stacked in sequence in a direction away from the substrate 50.
  • the first anode 501, the first light-emitting pattern 601 and the first cathode when the display panel is working, a driving signal is provided to the first anode 501 and a common signal is provided to the first cathode, so that when the first anode 501 An electric field is generated between the first cathode and the first cathode, thereby controlling the first light-emitting pattern 601 to emit light of a corresponding color; for example, the first light-emitting element includes a red light-emitting element capable of emitting red light.
  • the compensation function layer includes a compensation function pattern 401 provided in at least one of the sub-pixel areas.
  • the compensation function pattern 401 corresponds to the first light-emitting element in a one-to-one manner;
  • the display panel When making the display panel, first form a functional film layer on the substrate 50, and then make a first light-emitting element on the side of the functional film layer facing away from the substrate 50.
  • the The power signal line pattern VDD and the data line pattern DATA may be alternately arranged along the second direction, and the compensation function pattern 401 may be disposed near the corresponding first light-emitting element.
  • the first light-emitting element There is a first overlapping region F1 between the orthographic projection of the first anode 501 on the substrate 50 and the corresponding orthographic projection of the power signal line pattern VDD on the substrate 50 , and the corresponding orthographic projection of the power signal line pattern VDD on the substrate 50 .
  • the orthographic projection of the data line pattern DATA on the substrate 50 has a second overlapping area F2, and the orthographic projection of the corresponding compensation function graphic 401 on the substrate 50 has a third overlapping area F3.
  • the second overlapping area F2 is located between the first overlapping area F1 and the third overlapping area F3.
  • the compensation function pattern 401 can compensate for the step difference between the power signal line pattern VDD and the data line pattern DATA generated below the first anode 501, so that the In the display panel, when the first anode 501 included in the first light-emitting element simultaneously covers part of the corresponding power signal line pattern VDD, part of the corresponding part of the data line pattern DATA, and at least part of the corresponding compensation function pattern 401, The first anode 501 can have a high flatness, thereby effectively reducing the color shift phenomenon produced by the display panel during display.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示面板及其制作方法、显示装置，显示面板包括：基底（50）、功能膜层和多个第一发光元件；功能膜层包括电源信号线层、数据线层和补偿功能层；电源信号线层包括设置于各子像素区中的电源信号线图形（VDD，VDD1，VDD2），数据线层包括设置于各子像素区中的数据线图形（DATA，DATA1，DATA2），补偿功能层包括设置于至少一个子像素区中的补偿功能图形（401）；第一发光元件包括：层叠设置的第一阳极（501）、第一发光图形（601）和第一阴极；第一阳极（501）在基底（50）上的正投影，与对应的电源信号线图形（VDD，VDD1，VDD2）在基底（50）上的正投影存在第一交叠区域（F1），与对应的数据线图形（DATA，DATA1，DATA2）在基底（50）上的正投影存在第二交叠区域（F2），与对应的补偿功能图形（401）在基底（50）上的正投影存在第三交叠区域（F3），第二交叠区域（F2）位于第一交叠区域（F1）和第三交叠区域（F3）之间。

Description

显示面板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
有源矩阵有机发光二极管(英文：Active-matrix organic light-emitting diode，简称：AMOLED)显示产品，以其亮度高、功耗低、响应快、清晰度高、柔性好、发光效率高等优点被广泛的应用在各个领域。
而随着AMOLED显示产品的应用范围越来越广泛，对AMOLED显示产品的显示质量要求也越来越高，其中显示产品在进行显示时容易产生的色片现象受到了人们的广泛关注。
发明内容
本公开的目的在于提供一种显示面板及其制作方法、显示装置。
本公开的第一方面提供一种显示面板，包括：基底、设置在所述基底上的功能膜层、以及设置在所述功能膜层背向所述基底的一侧的多个第一发光元件；还包括阵列排布的多个子像素区；
所述功能膜层包括：电源信号线层、数据线层和补偿功能层；所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述数据线层包括设置于各所述子像素区中的数据线图形，所述电源信号线图形包括沿第一方向延伸的第一部分，所述数据线图形沿所述第一方向延伸；所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形；
每个所述第一发光元件均包括：沿远离所述基底的方向上，依次层叠设置的第一阳极、第一发光图形和第一阴极；所述第一阳极在所述基底上的正投影，与对应的所述电源信号线图形在所述基底上的正投影存在第一交叠区域，与对应的所述数据线图形在所述基底上的正投影存在第二交叠区域，与对应的所述补偿功能图形在所述基底上的正投影存在第三交叠区域，所述第 二交叠区域位于所述第一交叠区域和所述第三交叠区域之间。
可选的，所述第一阳极包括沿第二方向相对设置的第一边缘部分和第二边缘部分，以及位于所述第一边缘部分和所述第二边缘部分之间的第一中间部分；所述第二方向与所述第一方向相交；
所述第一边缘部分在所述基底上的正投影包括所述第一交叠区域；所述第二边缘部分在所述基底上的正投影包括所述第三交叠区域；所述第一中间部分在所述基底上的正投影包括所述第二交叠区域。
可选的，所述第一边缘部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影不交叠，所述第二边缘部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影不交叠；所述第一中间部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影交叠。
可选的，所述功能膜层还包括：栅极扫描线层、初始化信号线层、复位信号线层和发光控制信号线层；
所述栅极扫描线层包括设置于各所述子像素区中的栅极扫描线图形，所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形，所述复位信号线层包括设置于各所述子像素区中的复位信号线图形，所述发光控制信号线层包括设置于各所述子像素区中的发光控制信号线图形；所述栅极扫描线图形、所述初始化信号线图形、所述复位信号线图形和所述发光控制信号线图形均沿第二方向延伸，所述第二方向与所述第一方向相交。
可选的，所述第一阳极还包括沿所述第一方向相对设置的第三边缘部分和第四边缘部分，所述第一中间部分位于所述第三边缘部分和第四边缘部分之间；所述第三边缘部分分别与所述第一边缘部分和所述第二边缘部分耦接，所述第四边缘部分分别与所述第一边缘部分和所述第二边缘部分耦接；
所述第一中间部分在所述基底上的正投影与对应的所述栅极扫描线图形在所述基底上的正投影，以及对应的所述复位信号线图形在所述基底上的正投影包括第六交叠区域。
可选的，所述第一阳极包括主体部分和过孔连接部分，所述主体部分包括所述第一边缘部分、所述第二边缘部分、所述第三边缘部分、所述第四边缘部分和所述第一中间部分；所述主体部分为中心对称图形。
可选的，所述第一中间部分为中心对称图形，所述第一中间部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影重合。
可选的，所述显示面板包括第一金属层、第二金属层和第三金属层；
所述栅极扫描线层、所述复位信号线层和所述发光控制信号线层位于所述第一金属层中；
所述初始化信号线层位于所述第二金属层中；
所述数据线层、所述电源信号线层和所述补偿功能层位于所述第三金属层中；
所述功能膜层还包括第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一金属层和所述第二金属层之间，所述第二绝缘层位于所述第二金属层和所述第三金属层之间。
可选的，所述补偿功能图形采用导电材料制作，且与所述初始化信号线图形耦接。
可选的，所述补偿功能图形与所述数据线图形同层设置。
可选的，所述显示面板还包括：多个子像素驱动电路，所述多个子像素驱动电路中的第一部分子像素驱动电路与所述第一发光元件一一对应，所述第一部分子像素驱动电路用于驱动对应的所述第一发光元件发光；所述子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管和存储电容；
所述第一晶体管的栅极与对应的所述栅极扫描线图形耦接，所述第一晶体管的第一电极与所述驱动晶体管的第二电极耦接，所述第一晶体管的第二电极与所述驱动晶体管的栅极耦接；
所述第二晶体管的栅极与对应的所述复位信号线图形耦接，所述第二晶体管的第一电极与对应的所述初始化信号线图形耦接，所述第二晶体管的第二电极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与对应的所述栅极扫描线图形耦接，所述第四晶体管的第一电极与对应的所述数据线图形耦接，所述第四晶体管的第二电极与所述驱动晶体管的第一电极耦接；
所述驱动晶体管的第一电极与对应的所述电源信号线图形耦接，所述驱 动晶体管的第二电极与对应的所述第一发光元件耦接；
所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与对应的所述电源信号线图形耦接。
可选的，所述子像素驱动电路还包括第一导电连接部，所述第一晶体管的第二电极通过所述第一导电连接部与所述驱动晶体管的栅极耦接；
所述显示面板还包括第三金属层，所述第一导电连接部位于所述第三金属层，所述第一部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第一阳极在所述基底上的正投影不交叠。
可选的，所述显示面板还包括多个第二发光元件和多个第三发光元件；每个所述第二发光元件包括沿远离所述基底的方向上，依次层叠设置的第二阳极、第二发光图形和第二阴极；每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件均包括沿远离所述基底的方向上，依次层叠设置的第三阳极、第三发光图形和第三阴极；
所述多个子像素驱动电路还包括第二部分子像素驱动电路和第三部分子像素驱动电路，所述第二部分子像素驱动电路与所述第二发光元件一一对应，所述第二部分子像素驱动电路用于驱动对应的所述第二发光元件发光，所述第三部分子像素驱动电路与所述子发光元件一一对应，所述第三部分子像素驱动电路用于驱动对应的子发光元件发光；
所述第二部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第二阳极在所述电极上的正投影交叠；所述第三部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第三阳极在所述基底上的正投影交叠。
可选的，所述第一晶体管的栅极与对应的所述栅极扫描线图形直接接触。
可选的，所述第一晶体管的第一电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
可选的，所述第一晶体管的第二电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
可选的，所述子像素驱动电路还包括第七晶体管，所述第七晶体管的栅极与复位信号线图形耦接，第一部分子像素驱动电路中第七晶体管的第二电 极与所述第一阳极耦接，该第七晶体管的第一电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影之间存在第七交叠区域，所述第七晶体管的第一电极通过设置在所述第七交叠区域的过孔与对应的所述补偿功能图形耦接，以通过该补偿功能图形与对应的所述初始化信号线图形间接耦接。
可选的，所述驱动晶体管的栅极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影至少部分交叠。
可选的，所述驱动晶体管的栅极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影包括交叠的第一交叠部分；
所述第一交叠部分在所述基底上的正投影，与对应的所述第一阳极在所述基底上的正投影至少部分交叠。
可选的，所述存储电容的第一极板与所述栅极扫描线图形和所述复位信号线图形同材料设置，所述存储电容的第二极板与所述初始化信号线图形同材料设置；
所述存储电容的第一极板在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影，均位于对应的所述栅极扫描线图形在所述基底上的正投影，与对应的所述发光控制信号线图形在所述基底上的正投影之间。
可选的，所述功能膜层还包括栅极绝缘层，以及位于所述栅极绝缘层背向所述基底的一侧的第一绝缘层；所述存储电容的第一极板、所述栅极扫描线图形和所述复位信号线图形均位于所述栅极绝缘层背向所述基底的表面；所述存储电容的第二极板与所述初始化信号线图形均位于所述第一绝缘层背向所述基底的表面。
可选的，所述存储电容的第一极板在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影，均与对应的所述第一阳极在所述基底上的正投影部分交叠。
可选的，所述存储电容的第一极板在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影，均与对应的所述补偿功能图形在所述基底上的正投影部分交叠。
可选的，所述存储电容的第二极板的中心区域包括开口，所述开口在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
可选的，在垂直于所述基底的方向上，所述补偿功能层与所述电源信号线层之间的厚度差在阈值范围内；或者，所述补偿功能层与所述数据线层之间的厚度差在阈值范围内。
可选的，所述显示面板还包括多个第二发光元件；
每个所述第二发光元件包括沿远离所述基底的方向上，依次层叠设置的第二阳极、第二发光图形和第二阴极；所述第二阳极包括沿所述第二方向相对设置的第五边缘部分和第六边缘部分，以及位于所述第五边缘部分和所述第六边缘部分之间的第二中间部分，所述第二中间部分在所述基底上的正投影与所述第二发光图形在所述基底上的正投影重合；
所述第二中间部分在所述基底上的正投影与对应的所述电源信号线图形在所述基底上的正投影至少部分重叠，所述第二中间部分在所述基底上的正投影与对应的所述数据线图形在所述基底上的正投影至少部分重叠。
可选的，所述第二发光图形关于第二对称轴对称，所述第二对称轴沿所述第一方向延伸，所述第二对称轴在所述基底上的正投影，位于对应的所述电源信号线图形在所述基底上的正投影的内部。
可选的，所述显示面板还包括多个第三发光元件；
每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件均包括沿远离所述基底的方向上，依次层叠设置的第三阳极、第三发光图形和第三阴极；所述第三阳极包括沿所述第二方向相对设置的第七边缘部分和第八边缘部分，以及位于所述第七边缘部分和所述第八边缘部分之间的第三中间部分，所述第三中间部分在所述基底上的正投影与所述第三发光图形在所述基底上的正投影重合；
所述第三中间部分在所述基底上的正投影与对应的所述数据线图形在所述基底上的正投影至少部分重叠；
所述第七边缘部分在所述基底上的正投影与对应的电源信号线图形在所述基底上的正投影至少部分重叠。
可选的，所述第一发光元件包括红色子像素，所述第二发光元件包括蓝色子像素，所述第三发光元件包括绿色子像素。
基于上述显示面板的技术方案，本发明的第二方面提供一种显示装置，包括上述显示面板。
基于上述显示面板的技术方案，本发明的第三方面提供一种显示面板的制作方法，所述显示面板包括阵列排布的多个子像素区，所述制作方法包括：
在基底上制作功能膜层；所述功能膜层包括：电源信号线层、数据线层和补偿功能层；所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述数据线层包括设置于各所述子像素区中的数据线图形，所述电源信号线图形包括沿第一方向延伸的第一部分，所述数据线图形沿所述第一方向延伸；所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形；
在所述功能膜层背向所述基底的一侧制作多个第一发光元件，每个所述第一发光元件均包括：沿远离所述基底的方向上，依次层叠设置的第一阳极、第一发光图形和第一阴极；所述第一阳极在所述基底上的正投影，与对应的所述电源信号线图形在所述基底上的正投影存在第一交叠区域，与对应的所述数据线图形在所述基底上的正投影存在第二交叠区域，与对应的所述补偿功能图形在所述基底上的正投影存在第三交叠区域，所述第二交叠区域位于所述第一交叠区域和所述第三交叠区域之间。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为相关技术中子像素驱动电路的布局示意图；
图2～5为相关技术中所述子像素驱动电路的各膜层结构示意图；
图6为本公开实施例提供的子像素驱动电路的第一结构示意图；
图7为本公开实施例提供的子像素驱动电路的第二结构示意图；
图8为本公开实施例提供的子像素驱动电路对应的工作时序图；
图9为本公开实施例提供的显示面板中子像素驱动电路的第一布局示意图；
图10为图9中沿A1A2方向的截面示意图；
图11为本公开实施例提供的有源层的布局示意图；
图12为本公开实施例提供的第一栅金属层的布局示意图；
图13为本公开实施例提供的第二栅金属层的布局示意图；
图14为本公开实施例提供的源漏金属层的第一布局示意图；
图15为本公开实施例提供的显示面板中子像素驱动电路的第二布局示意图；
图16为图15中的源漏金属层的布局示意图；
图17为图15中沿B1B2方向的截面示意图；
图18为图15中沿C1C2方向的截面示意图；
图19为本公开实施例提供的显示面板中子像素驱动电路的第三布局示意图；
图20为本公开实施例提供的显示面板中子像素驱动电路的第四布局示意图；
图21为本公开实施例提供的显示面板中子像素驱动电路的第五布局示意图；
图22为图21中沿D1D2方向的截面示意图；
图23为图21中沿E1E2方向的截面示意图；
图24为本公开实施例提供的一个像素单元对应的子像素驱动电路的布局示意图；
图25为本公开实施例提供的第一阳极的结构示意图；
图26为本公开实施例提供的第二阳极的结构示意图；
图27为本公开实施例提供的第三阳极的结构示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示面板及其制作方法、显示装置， 下面结合说明书附图进行详细描述。
AMOLED显示面板的结构包括：基底，设置在基底上的多个子像素驱动电路，以及设置在所述子像素驱动电路背向所述基底的一侧的多个发光元件，所述发光元件与所述子像素驱动电路一一对应，所述子像素驱动电路用于驱动对应的发光元件发光，从而实现显示面板的显示功能。
相关技术中，所述子像素驱动电路一般包括多个薄膜晶体管，如图1所示，图1中示出了所述子像素驱动电路包括7个薄膜晶体管M1～M7时，该7个薄膜晶体管的具体布局方式，按照这种方式布局时，所述子像素驱动电路包括如图2所示的有源层，如图3所示的第一金属层，如图4所示的第二金属层，以及如图5所示的第三金属层；所述有源层包括用于形成各薄膜晶体管的沟道区的有源图形(如图2中的虚线框内的部分)，以及与所述有源图形耦接，具有导电性能的掺杂有源图形(如图2中的虚线框外的部分)；所述第一金属层包括各薄膜晶体管的栅极，所述栅极耦接的扫描信号线图形GATE，所述子像素驱动电路中存储电容的一个极板CE1，复位信号线图形RST，以及发光控制信号线图形EM；所述第二金属层包括初始化信号线图形VINT，以及所述子像素驱动电路中存储电容的另一个电极板CE2；所述第三金属层包括数据线图形DATA，电源信号线图形VDD，以及一些导电连接部(如标记341～343)。
值得注意，如图1所示，在布局子像素驱动电路时，为了实现异层设置的功能图形之间的耦接，还可设置一些过孔(如标记：381～388)
如图6和图7所示，本公开提供一种显示面板，该显示面板包括多个子像素驱动电路，示例性的，每个子像素驱动电路包括7个薄膜晶体管和1个电容；所述显示面板还包括初始化信号线图形VINT，栅极扫描线图形GATE，发光控制信号线图形EM，复位控制信号线图形RST，数据线图形DATA和电源信号线图形VDD，各图形均一一对应位于所述显示面板的子像素区中。
所述多个子像素驱动电路呈阵列分布，且一一对应位于所述显示面板的子像素区中，所述多个子像素驱动电路能够划分为多行子像素驱动电路和多列子像素驱动电路，位于同一行的子像素驱动电路对应的所述初始化信号线图形VINT依次电连接，形成为一体结构；位于同一行的子像素驱动电路对 应的所述栅极扫描线图形GATE依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述发光控制信号线图形EM依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述复位控制信号线图形RST依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述数据线图形DATA依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述电源信号线图形VDD依次电连接，形成为一体结构。
示例性的，每行子像素驱动电路均包括沿X方向依次排列的多个子像素驱动电路，所述初始化信号线图形VINT、栅极扫描线图形GATE、发光控制信号线图形EM和复位控制信号线图形RST均沿所述X方向延伸，每行子像素驱动电路中包括的多个子像素驱动电路均能够分别与对应的初始化信号线图形VINT，栅极扫描线图形GATE，发光控制信号线图形EM，复位控制信号线图形RST耦接；每列子像素驱动电路均包括沿Y方向依次排列的多个子像素驱动电路，所述数据线图形DATA和电源信号线图形VDD均沿所述Y方向延伸，每列子像素驱动电路中包括的多个子像素驱动电路均能够分别与对应的数据线图形DATA和电源信号线图形VDD耦接。
如图6所示，显示面板中包括的各子像素驱动电路可均包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容Cst；第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7均可采用P型晶体管。
所述第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与对应的栅极扫描线图形GATE耦接，第一晶体管T1的源极S1与第三晶体管T3的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与对应的第一复位信号线图形RST1耦接，第二晶体管T2的源极S2与对应的第一初始化信号线图形VINT1耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与对应的所述栅极扫描线图形GATE耦接，第四晶体管T4的源极S4与对应的数据线图形DATA耦接，第四晶体管T4 的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与对应的第一发光控制信号线图形EM1耦接，第五晶体管T5的源极S5与对应的电源信号线图形VDD耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与对应的第二发光控制信号线图形EM2耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与发光元件OLED的第一阳极501耦接。
第七晶体管T7的栅极207g与第二复位信号线图形RST2耦接，第七晶体管T7的漏极D7与所述发光元件OLED的第一阳极501耦接，第七晶体管T7的源极S7与对应的第二初始化信号线图形VINT2耦接。
存储电容Cst的第一极板Cst1与第三晶体管T3的栅极203g耦接，因此，可直接将第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储电容Cst的第二极板Cst2与对应的电源信号线图形VDD耦接。
如图7所示，所述第一发光控制信号线图形EM1与所述第二发光控制信号线图形EM2可复用同一个发光控制信号线图形EM，这样可通过该发光控制信号线图形同时控制第五晶体管T5和第六晶体管T6的通断情况。
如图8所示，图7结构的子像素驱动电路在工作时，每个工作周期均包括第一复位时段P1、写入补偿时段P2、第二复位时段P3和发光时段P4。
在所述第一复位时段P1，第一复位信号线图形RST1输入的第一复位信号处于有效电平，第二晶体管T2导通，由第一初始化信号线图形VINT1传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述第一复位信号处于非有效电平，第二晶体管T2截止，栅极扫描线图形GATE输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，数据线图形DATA写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管 T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，Vdata代表数据信号，Vth代表第三晶体管T3的阈值电压。
在第二复位时段P3，所述栅极扫描信号处于非有效电平，第一晶体管T1和第四晶体管T4均截止，第二复位信号线图形RST2输入的第二复位信号处于有效电平，控制第七晶体管T7导通，由第一初始化信号线图形VINT1传输的第一初始化信号输入至发光元件OLED的阳极，控制发光元件OLED不发光。
在发光时段P4，发光控制信号线图形EM写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形VDD传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-Vdd，Vdd为电源信号对应的电位，基于该栅源电压产生的漏电流流向对应的发光元件OLED的阳极，驱动对应的发光元件OLED发光。
如图9和图10所示，图9中示出了三个相邻的子像素驱动电路的布局示意图，在制作上述子像素驱动电路时，子像素驱动电路对应的各膜层的布局如下：
沿远离基底70的方向上依次层叠设置的有源层(一般为低温多晶硅层)、栅极绝缘层GI1、第一栅金属层、第一层间绝缘层GI2、第二栅金属层、第二层间绝缘层ILD、第一源漏金属层和平坦层PLN。
如图11所示，有源层用于形成子像素驱动电路中各晶体管的沟道区(如：101pg～107pg)，源极形成区(如：101ps～107ps)和漏极形成区(如：101pd～107pd)，源极形成区和漏极形成区对应的有源层由于掺杂作用，导电性能会优于沟道区对应的有源层，该源极形成区对应的有源层可作为个各晶体管的源极(如：S1～S7)，该漏极形成区对应的有源层可作为个各晶体管的漏极(如：D1～D7)。
如图12所示，第一栅金属层用于形成子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及显示面板包括的栅极扫描信号线图形GATE、发光 控制信号线图形EM、第一复位信号线图形RST1和第二复位信号线图形RST2等结构，其中每个子像素驱动电路中的第三晶体管T3的栅极203g均复用为该子像素驱动电路中的存储电容Cst的第一极板Cst1。
如图13所示，第二栅金属层用于形成存储电容Cst的第二极板Cst2，屏蔽图形301(用于遮挡第一晶体管T1对应的两沟道区之间的有源层)，以及显示面板包括的第一初始化信号线图形VINT1和第二初始化信号线图形VINT2.
如图9和图14所示，第一源漏金属层用于形成显示面板包括的数据线图形(如：DATA1、DATA2、DATA3)和电源信号线图形(如：VDD1、VDD2、VDD3)。
更详细地说，请继续参阅图9、图11和图12，第一晶体管T1的栅极201g覆盖第一沟道区101pg，第一晶体管T1的源极S1位于第一源极形成区101ps，第一晶体管T1的漏极D1位于第一漏极形成区101pd。
第二晶体管T2的栅极202g覆盖第二沟道区102pg，第二晶体管T2的源极S2位于第二源极形成区102ps，第二晶体管T2的漏极D2位于第二漏极形成区102pd。
第三晶体管T3的栅极203g覆盖第三沟道区103pg，第三晶体管T3的源极S3位于第三源极形成区103ps，第三晶体管T3的漏极D3位于第三漏极形成区103pd。
第四晶体管T4的栅极204g覆盖第四沟道区104pg，第四晶体管T4的源极S4位于第四源极形成区104ps，第四晶体管T4的漏极D4位于第四漏极形成区104pd。
第五晶体管T5的栅极205g覆盖第五沟道区105pg，第五晶体管T5的源极S5位于第五源极形成区105ps，第五晶体管T5的漏极D5位于第五漏极形成区105pd。
第六晶体管T6的栅极206g覆盖第六沟道区106pg，第六晶体管T6的源极S6位于第六源极形成区106ps，第六晶体管T6的漏极D6位于第六漏极形成区106pd。
第七晶体管T7的栅极207g覆盖第七沟道区107pg，第七晶体管T7的源 极S7位于第七源极形成区107ps，第七晶体管T7的漏极D7位于第七漏极形成区107pd。
第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储电容Cst的第二极板Cst2与电源信号线VDD耦接。
请继续参阅图9，图9中示意了红色发光元件和蓝色发光元件，所述红色发光元件和所述蓝色发光元件中的至少一个包括的阳极，能够同时覆盖电源信号线图形和数据线图形，示例性的，所述蓝色发光元件中包括的阳极图形901同时覆盖了电源信号线图形VDD1和数据线图形DATA1，所述红色发光元件中包括的阳极图形902同时覆盖了电源信号线图形VDD2和数据线图形DATA2，由于电源信号线图形和数据线图形均为纵向延伸(如Y方向)的整条图形，因此，上述布局方式使得阳极图形在纵向延伸方向上产生段差较小，有利于改善发光元件产生的色偏现象。
上述显示面板虽然对发光元件产生的色偏现象有所改善，但是从图10中能够看出，电源信号线图形VDD和数据线图形DATA能够在横向延伸方向(如X方向)上产生段差，从而导致后续形成的阳极图形902在横向延伸方向上发生倾斜，进而导致形成在阳极图形902上的有机发光材料层802也发生倾斜，使得显示面板在显示时，仍然存在色偏现象。
基于上述问题的存在，如图15和图17所示，本公开实施例提供了一种显示面板，包括：基底50、设置在所述基底50上的功能膜层、以及设置在所述功能膜层背向所述基底50的一侧的多个第一发光元件；还包括阵列排布的多个子像素区；
所述功能膜层包括：电源信号线层、数据线层和补偿功能层；所述电源信号线层包括设置于各所述子像素区中的电源信号线图形(如图15中的VDD1和VDD2)，所述数据线层包括设置于各所述子像素区中的数据线图形(如图15中的DATA1和DATA2)，所述电源信号线图形包括沿第一方向延伸的第一部分，所述数据线图形沿所述第一方向延伸；所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形401；
每个所述第一发光元件均包括：沿远离所述基底50的方向上，依次层叠设置的第一阳极501、第一发光图形601和第一阴极；所述第一阳极501在 所述基底50上的正投影，与对应的所述电源信号线图形在所述基底50上的正投影存在第一交叠区域F1，与对应的所述数据线图形在所述基底50上的正投影存在第二交叠区域F2，与对应的所述补偿功能图形401在所述基底50上的正投影存在第三交叠区域F3，所述第二交叠区域F2位于所述第一交叠区域F1和所述第三交叠区域F3之间。
具体地，阵列排布的多个子像素区能够划分为沿第一方向延伸的子像素区列，以及沿第二方向延伸的子像素区行，所述子像素区列包括沿所述第一方向排列的多个子像素区，所述子像素区行包括沿所述第二方向排列的多个子像素区；所述第一方向与所述第二方向相交，示例性的，所述第一方向包括Y方向，所述第二方向包括X方向。
所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形可选为网格状，该网格状的电源信号线图形包括沿所述第一方向延伸的第一部分。所述电源信号线图形与所述子像素区一一对应，所述电源信号线图形位于对应的所述子像素区中，位于同一列的子像素区对应的各所述电源信号线图形VDD依次电连接，形成为一体结构。
所述数据线层包括设置于各所述子像素区中的数据线图形，所述数据线图形沿所述第一方向延伸，所述数据线图形与所述子像素区一一对应，所述数据线图形位于对应的所述子像素区中，位于同一列的子像素区对应的各所述数据线图形DATA依次电连接，形成为一体结构。
所述显示面板还包括位于所述功能膜层背向所述基底50的一侧的多个第一发光元件，所述第一发光元件包括：沿远离所述基底50的方向上，依次层叠设置的第一阳极501、第一发光图形601和第一阴极；显示面板工作时，向所述第一阳极501提供驱动信号，向所述第一阴极提供公共信号，使得在所述第一阳极501和所述第一阴极之间产生电场，从而控制所述第一发光图形601发出对应颜色的光；示例性的，所述第一发光元件包括红色发光元件，能够发出红光。
所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形401，示例性的，所述补偿功能图形401与所述第一发光元件一一对应；
在布局所述显示面板时，先在基底50上形成功能膜层，然后在该功能膜 层背向所述基底50的一侧制作第一发光元件，在布局所述功能膜层时，所述电源信号线图形与所述数据线图形可沿所述第二方向交替排列，所述补偿功能图形401可设置在对应的第一发光元件的附近，示例性的，所述第一发光元件中的所述第一阳极501在所述基底50上的正投影，与对应的所述电源信号线图形在所述基底50上的正投影存在第一交叠区域F1，与对应的所述数据线图形在所述基底50上的正投影存在第二交叠区域F2，与对应的所述补偿功能图形401在所述基底50上的正投影存在第三交叠区域F3，所述第二交叠区域F2位于所述第一交叠区域F1和所述第三交叠区域F3之间。
根据上述显示面板的具体结构可知，本公开实施例提供的显示面板中，所述补偿功能图形401能够补偿所述电源信号线图形和所述数据线图形在所述第一阳极501下方产生的段差，使得所述显示面板中，第一发光元件包括的第一阳极501在同时覆盖部分对应的所述电源信号线图形，部分对应的所述数据线图形，以及至少部分对应的补偿功能图形401时，该第一阳极501能够具有较高的平坦度，从而有效减小了显示面板在显示时产生的色偏现象。
如图25所示，在一些实施例中，所述第一阳极501包括沿第二方向相对设置的第一边缘部分501a1和第二边缘部分501a2，以及位于所述第一边缘部分501a1和所述第二边缘部分501a2之间的第一中间部分501a5；所述第二方向与所述第一方向相交；所述第一边缘部分501a1在所述基底50上的正投影包括所述第一交叠区域F1；所述第二边缘部分501a2在所述基底50上的正投影包括所述第三交叠区域F3；所述第一中间部分501a5在所述基底50上的正投影包括所述第二交叠区域F2。
具体地，所述第一阳极501的具体结构多种多样，示例性的，所述第一阳极501包括沿第二方向相对设置的第一边缘部分501a1和第二边缘部分501a2，以及位于所述第一边缘部分501a1和所述第二边缘部分501a2之间的第一中间部分501a5，所述第一边缘部分501a1、所述第二边缘部分501a2和所述中间部分可均沿所述第一方向延伸。
所述第一边缘部分501a1在所述基底50上的正投影，能够与对应的所述电源信号线图形在所述基底50上的正投影形成所述第一交叠区域F1，所述第一中间部分501a5在所述基底50上的正投影，能够与对应的所述数据线图 形在所述基底50上的正投影形成所述第二交叠区域F2，所述第二边缘部分501a2在所述基底50上的正投影，能够与对应的所述补偿功能图形401在所述基底50上的正投影形成所述第三交叠区域F3。
上述实施例提供的显示面板中，所述第一阳极501中沿第二方向相对设置的第一边缘部分501a1和第二边缘部分501a2，能够分别覆盖对应的电源信号线图形和对应的补偿功能图形401，同时所述第一阳极501中位于第一边缘部分501a1和第二边缘部分501a2之间的中间部分能够覆盖对应的数据线图形，从而使得被所述第一阳极501覆盖的所述电源信号线图形、数据信号线图形和补偿功能图形401能够均匀的分布在所述第一阳极501覆盖的区域中，从而更好的保证了所述第一阳极501的平坦度。
如图15和图25所示，在一些实施例中，所述第一边缘部分501a1在所述基底50上的正投影与所述第一发光图形601在所述基底50上的正投影不交叠，所述第二边缘部分501a2在所述基底50上的正投影与所述第一发光图形601在所述基底50上的正投影不交叠；所述第一中间部分501a5在所述基底50上的正投影与所述第一发光图形601在所述基底50上的正投影交叠。
具体地，在所述第一阳极501背向所述基底50的表面形成所述第一发光图形601时，所述第一发光图形601的具体布局方式多种多样，示例性的，所述第一发光图形601在所述基底50上的正投影，位于所述第一边缘图形在所述基底50上的正投影与所述第二边缘图形在所述基底50上的正投影之间，且与所述第一中间部分501a5在所述基底50上的正投影交叠；按照这种方式布局所述第一发光图形601时，使得所述第一发光图形601能够位于所述第一阳极501的中间部位的表面，而所述第一阳极501的中间部位的表面具有更高的平坦度，从而更有利于提升所述第一发光图形601的平坦度。
如图25所示，在一些实施例中，所述第一中间部分501a5为中心对称图形，所述第一中间部分501a5在所述基底50上的正投影与所述第一发光图形601在所述基底50上的正投影重合。
具体地，所述第一阳极501的第一中间部分501a5可选为中心对称图形，示例性的，所述第一中间部分501a5在所述基底50上的正投影为六边形；在这种情况下，当设置所述第一发光图形601在所述基底50上的正投影与所述 第一中间部分501a5在所述基底50上的正投影重合时，所述第一发光图形601也为中心对称图形，这种结构的所述第一中间部分501a5和所述第一发光图形601，更有利于所述第一发光图形601的平坦度和出光的均匀性。
在一些实施例中，所述第一交叠区域F1的面积与所述第二交叠区域F2的面积之和，与所述第三交叠区域F3的面积之间的比值接近2:1。
具体地，在布局所述第一阳极501，所述电源信号线图形、所述数据线图形和所述补偿功能图形401时，可通过控制在垂直于所述基底50的方向上，所述第一阳极501分别与所述电源信号线图形、所述数据线图形和所述补偿功能图形401的交叠程度来调整所述第一阳极501的平整程度；示例性的，可设置所述第一交叠区域F1的面积与所述第二交叠区域F2的面积之和，与所述第三交叠区域F3的面积之间的比值接近2:1；这种设置方式使得所述第一交叠面积、所述第二交叠面积和所述第三交叠面积相接近，即所述第一阳极501覆盖的所述电源信号线图形、所述数据线图形和所述补偿功能图形401的面积相接近，从而更有利于提升所述第一阳极501的平坦度。
如图15所示，在一些实施例中，所述功能膜层还包括：栅极扫描线层、初始化信号线层、复位信号线层和发光控制信号线层；
所述栅极扫描线层包括设置于各所述子像素区中的栅极扫描线图形GATE，所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形VINT，所述复位信号线层包括设置于各所述子像素区中的复位信号线图形RST，所述发光控制信号线层包括设置于各所述子像素区中的发光控制信号线图形EM；所述栅极扫描线图形GATE、所述初始化信号线图形VINT、所述复位信号线图形RST和所述发光控制信号线图形EM均沿第二方向延伸，所述第二方向与所述第一方向相交。
具体地，所述栅极扫描线层包括设置于各所述子像素区中的栅极扫描线图形GATE，所述栅极扫描线图形GATE沿所述第二方向延伸，位于同一行的各子像素区对应的所述栅极扫描线图形GATE依次电连接，形成为一体结构。
所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形VINT，所述初始化信号线层沿所述第二方向延伸，位于同一行的各子像素区 对应的所述初始化信号线图形VINT依次电连接，形成为一体结构。
所述复位信号线层包括设置于各所述子像素区中的复位信号线图形RST，所述复位信号线图形RST沿所述第二方向延伸，位于同一行的各子像素区对应的所述复位信号线图形RST依次电连接，形成为一体结构。
所述发光控制信号线层包括设置于各所述子像素区中的发光控制信号线图形EM，所述发光控制信号线图形EM沿所述第二方向延伸，位于同一行的各子像素区对应的所述发光控制信号线图形EM依次电连接，形成为一体结构。
如图15和图25所示，在一些实施例中，所述第一阳极501还包括沿所述第一方向相对设置的第三边缘部分501a3和第四边缘部分501a4，所述第一中间部分501a5位于所述第三边缘部分501a3和第四边缘部分501a4之间；所述第三边缘部分501a3分别与所述第一边缘部分501a1和所述第二边缘部分501a2耦接，所述第四边缘部分501a4分别与所述第一边缘部分501a1和所述第二边缘部分501a2耦接；所述第一中间部分501a5在所述基底50上的正投影与对应的所述栅极扫描线图形在所述基底50上的正投影，以及对应的所述复位信号线图形在所述基底50上的正投影包括第六交叠区域。
具体地，所述第一阳极501还包括沿所述第一方向相对设置的第三边缘部分501a3和第四边缘部分501a4，所述第一中间部分501a5位于所述第三边缘部分501a3和第四边缘部分501a4之间，所述第一边缘部分501a1、所述第二边缘部分501a2、所述第三边缘部分501a3和所述第四边缘部分501a4共同包围所述中间部分。
在布局所述第一阳极501时，可设置所述第三边缘部分501a3在所述基底50上的正投影与对应的所述初始化信号线图形VINT(如图15中的第一初始化信号线图形VINT1)在所述基底50上的正投影形成第四交叠区域；所述第四边缘部分501a4在所述基底50上的正投影与对应的所述发光控制信号线图形EM在所述基底50上的正投影形成第五交叠区域；所述第一中间部分501a5在所述基底50上的正投影与对应的所述栅极扫描线图形GATE在所述基底50上的正投影，以及对应的所述复位信号线图形RST(如图15中的第一复位信号线图形RST1)在所述基底50上的正投影形成第六交叠区域；这 种布局方式使得沿所述第一方向，所述第四交叠区域和所述第五交叠区域相对设置，所述第六交叠区域位于所述第四交叠区域和所述第五交叠区域之间，从而使得被所述第一阳极501覆盖的所述初始化信号线图形VINT、所述发光控制信号线图形EM、所述栅极扫描线图形GATE和所述复位信号线图形RST能够均匀的分布在所述第一阳极501覆盖的区域中，从而更好的保证了所述第一阳极501的平坦度。
如图25所示，在一些实施例中，所述第一阳极501包括主体部分501a和过孔连接部分501b，所述主体部分501a包括所述第一边缘部分501a1、所述第二边缘部分501a2、所述第三边缘部分501a3、所述第四边缘部分501a4和所述第一中间部分501a5；所述主体部分501a为中心对称图形。
具体地，所述第一阳极501可包括相耦接的主体部分501a和过孔连接部分501b，所述主体部分501a背向所述基底50的表面用于形成所述第一发光图形601，所述过孔连接部分501b用于通过过孔与所述显示面板中的子像素驱动电路耦接，接收由所述子像素驱动电路提供的驱动信号。
上述设置所述第一阳极501包括所述主体部分501a和所述过孔连接部分501b，避免了在所述第一阳极501中用于形成所述第一发光图形601的部分上制作过孔，从而保证了所述第一发光元件的发光效果。另外，设置所述主体部分501a包括所述第一边缘部分501a1、所述第二边缘部分501a2、所述第三边缘部分501a3、所述第四边缘部分501a4和所述第一中间部分501a5，并设置所述主体部分501a为中心对称图形，使得所述电源信号线图形VDD(如图15中的VDD1)、数据线图形DATA(如图15中的DATA1)、栅极扫描线图形GATE、复位信号线图形RST(如图15中的第一复位信号线图形RST1)、发光控制信号线图形EM，初始化信号线图形VINT(如图15中的第一初始化信号线图形VINT1)中被所述第一阳极501覆盖的部分，能够均匀的分布在所述第一阳极501的下方，从而更有利于提升所述第一阳极501的平坦度。
如图12、图13、图16、图17和图18所示，在一些实施例中，所述显示面板包括第一金属层、第二金属层和第三金属层；所述栅极扫描线层、所述复位信号线层和所述发光控制信号线层位于所述第一金属层中；所述初始 化信号线层位于所述第二金属层中；所述数据线层、所述电源信号线层和所述补偿功能层位于所述第三金属层中；所述功能膜层还包括第一绝缘层(如图17中的GI2)和第二绝缘层(如图17中的ILD)，所述第一绝缘层位于所述第一金属层和所述第二金属层之间，所述第二绝缘层位于所述第二金属层和所述第三金属层之间。
具体地，在对所述显示面板进行布局时，可将沿同一方向延伸的功能层图形布局在同一层，示例性的，将所述栅极扫描线层、所述复位信号线层和所述发光控制信号线层同层设置，且共同形成为第一金属层；将所述数据线层、所述电源信号线层和所述补偿功能层同层设置，且共同形成为第三金属层。
由于显示面板的尺寸固定，使得在同一层的布局空间有限，当沿同一方向延伸的功能层图形无法布局在同一层时，可将部分功能层图形布局在其它膜层，示例性的，所述初始化信号线层形成为第二金属层，所述第二金属层与所述第一金属层异层设置。
值得注意，在制作各金属层时，为了避免相邻金属层之间发生短路，可在相邻金属层之间形成绝缘层，示例性的，设置所述功能膜层还包括第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一金属层和所述第二金属层之间，所述第二绝缘层位于所述第二金属层和所述第三金属层之间。
上述实施例提供的显示面板中，通过将沿同一方向延伸的功能层图形布局在同一层，并在相邻的导电膜层之间布局绝缘层的方式，使得在避免显示面板中包括各功能图形之间发生短路的情况下，最大限度的利用了显示面板中的布局空间，更有利于显示面板的薄型化发展。
如图15所示，在一些实施例中，所述补偿功能图形401采用导电材料制作，且与所述初始化信号线图形VINT(如图15中的第一初始化信号线图形VINT1)耦接。
具体地，所述补偿功能图形401的材质可根据实际需要设置，示例性的，包括导电材料或绝缘材料，当采用导电材料制作所述补偿功能图形401时，可将所述补偿功能与固定信号输出端耦接，使所述补偿功能图形401具有固定电位，从而避免了所述补偿功能图形401处于浮接的状态，影响所述显示 面板工作的稳定性。
进一步地，可将所述初始化信号线图形VINT复用为固定电位输出端，由于所述初始化信号线图形VINT用于传输具有固定电位的初始化信号，将所述补偿功能图形401与所述初始化信号线图形VINT耦接，能够使得所述补偿功能图形401具有与所述初始化信号相同的固定电位。
上述将所述初始化信号线图形VINT复用为所述固定电位输出端，不仅避免了在显示基板中制作额外的、专门用于为所述补偿功能图形401提供固定电位的固定电位输出端，有效提升了所述功能膜层的布局空间；而且，还实现了加强了初始化信号线的电压，使得初始化信号线上传输的初始化信号的电压更稳定，从而更有利于子像素驱动电路实现稳定的工作性能。
值得注意，请继续参阅图5在将所述初始化信号线图形VINT复用为所述固定电位输出端时，可设置所述补偿功能图形401在所述基底50上的正投影，与所述初始化信号线图形VINT在所述基底50上的正投影存在交叠区域，这样通过在所述交叠区域设置过孔，即可实现将所述补偿功能图形401与所述初始化信号线图形VINT耦接。
在一些实施例中，所述补偿功能图形401与所述数据线图形DATA同层设置。
具体地，在布局所述补偿功能图形401时，可将所述补偿功能图形401与所述数据线图形DATA同层设置，这种布局方式避免了所述补偿功能图形401单独占用一层，从而更有利于所述显示面板的薄型化。
进一步地，可将所述补偿功能图形401与所述数据线图形DATA同材料设置，这种设置方式使得所述补偿功能图形401能够与所述数据线图形DATA在同一次构图工艺中形成，从而有效简化了显示面板的制作流程，节约了显示面板的制作成本。
在一些实施例中，所述显示面板还包括：多个子像素驱动电路，所述多个子像素驱动电路中的第一部分子像素驱动电路与所述第一发光元件一一对应，所述第一部分第一子像素驱动电路用于驱动对应的所述第一发光元件发光；所述子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管和存储电容。
所述第一晶体管的栅极与对应的所述栅极扫描线图形GATE耦接，所述第一晶体管的第一电极与所述驱动晶体管的第二电极耦接，所述第一晶体管的第二电极与所述驱动晶体管的栅极耦接；所述第二晶体管的栅极与对应的所述复位信号线图形RST耦接，所述第二晶体管的第一电极与对应的所述初始化信号线图形VINT耦接，所述第二晶体管的第二电极与所述驱动晶体管的栅极耦接；所述第四晶体管的栅极与对应的所述栅极扫描线图形GATE耦接，所述第四晶体管的第一电极与对应的所述数据线图形DATA耦接，所述第四晶体管的第二电极与所述驱动晶体管的第一电极耦接；所述驱动晶体管的第一电极与对应的所述电源信号线图形VDD耦接，所述驱动晶体管的第二电极与对应的所述第一发光元件耦接；所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与对应的所述电源信号线图形VDD耦接。
示例性的，所述功能膜层中包括n+1条电源信号线图形VDD、n+1条数据线图形DATA、n+1条栅极扫描线图形GATE、n+1条初始化信号线图形VINT、n+1条复位信号线图形RST和n+1条发光控制信号线图形EM，所述显示面板包括与所述子像素区一一对应的多个子像素驱动电路，所述多个子像素驱动电路可划分为n+1行子像素驱动电路，且可划分为n+1列子像素驱动电路；所述n+1条电源信号线图形VDD与n+1列子像素驱动电路一一对应，所述n+1条数据线图形DATA与n+1列子像素驱动电路一一对应，所述n+1条栅极扫描线图形GATE与n+1行子像素驱动电路一一对应，所述n+1条初始化信号线图形VINT与n+1行子像素驱动电路一一对应，所述n+1条复位信号线图形RST与n+1行子像素驱动电路一一对应，所述n+1条发光控制信号线图形EM与n+1行子像素驱动电路一一对应。
基于上述示例性结构，下面以位于第n行、第n列的子像素驱动电路为例，对其具体结构和与各种信号线图形的连接方式进行详细说明。
如图7和图15所示，所述子像素驱动电路包括：驱动晶体管(即第三晶体管T3，下面描述为第三晶体管T3)、第一晶体管T1、第二晶体管T2、第四晶体管T4和存储电容Cst；所述第一晶体管T1、所述第二晶体管T2和所述第四晶体管T4选用P型晶体管。
所述第一晶体管T1的栅极201g与所述栅极扫描线图形GATE耦接，所述第一晶体管T1的第一电极(即源极S1)与所述第三晶体管T3的第二电极(即漏极D3)耦接，所述第一晶体管T1的第二电极(即漏极D1)与所述第三晶体管T3的栅极203g耦接。
所述第二晶体管T2的栅极202g与所述第一复位信号线图形RST1耦接，所述第二晶体管T2的第一电极(即源极S2)与所述第一初始化信号线图形VINT1耦接，所述第二晶体管T2的第二电极(即漏极D2)与所述第三晶体管T3的栅极203g耦接。
所述第四晶体管T4的栅极204g与所述栅极扫描线图形GATE耦接，所述第四晶体管T4的第一电极(即源极S4)与所述数据线图形DATA耦接，所述第四晶体管T4的第二电极(即漏极D4)与所述第三晶体管T3的第一电极(即源极S3)耦接。
所述第三晶体管T3的第一电极(即源极S3)与所述电源信号线图形VDD耦接，所述第三晶体管T3的第二电极(即漏极D3)与对应的发光元件OLED耦接。
所述存储电容Cst的第一极板Cst1与所述第三晶体管T3的栅极203g耦接，所述存储电容Cst的第二极板Cst2与所述电源信号线图形VDD耦接。
在一些实施例中，所述功能膜层还包括：发光控制信号线图形和第二复位信号线图形RST2；所述子像素驱动电路还包括：第五晶体管、第六晶体管和第七晶体管；其中，所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一电极与所述电源信号线图形VDD耦接，所述第五晶体管的第二电极与所述驱动晶体管的第一电极耦接；所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一电极与所述驱动晶体管的第二电极耦接，所述第六晶体管的第二电极与对应的发光元件耦接；所述第七晶体管的栅极与所述第二复位信号线图形耦接，所述第七晶体管的第一电极与所述初始化信号线耦接，所述第七晶体管的第二电极与所述第六晶体管的第二电极耦接。
具体地，如图7和图15所示，继续以位于第n行、第n列的子像素驱动电路为例，所述第五晶体管T5的栅极205g与所述发光控制信号线图形EM 耦接，所述第五晶体管T5的第一电极(即源极S5)与所述电源信号线图形VDD耦接，所述第五晶体管T5的第二电极(即漏极D5)与所述驱动晶体管(即第三晶体管T3)的第一电极(即源极S3)耦接。
所述第六晶体管T6的栅极206g与所述发光控制信号线图形EM耦接，所述第六晶体管T6的第一电极(即源极S6)与所述驱动晶体管(即第三晶体管T3)的第二电极(即漏极D3)耦接，所述第六晶体管T6的第二电极(即漏极D6)与对应的发光元件OLED耦接；
所述第七晶体管T7的栅极207g与所述第二复位信号线图形RST2(示例性的，所述第二复位信号线图形RST2可为第n+1行子像素驱动电路对应的复位信号线图形RST)耦接，所述第七晶体管T7的第一电极(即源极S7)与所述第二初始化信号线图形VINT2(示例性的，所述第二初始化信号线图形VINT2可为第n+1行子像素驱动电路对应的初始化信号线图形VINT)耦接，所述第七晶体管T7的第二电极(即漏极D7)与所述第六晶体管T6的第二电极(即漏极D6)耦接。
上述实施例提供显示面板中，设置所述子像素驱动电路还包括所述第五晶体管T5、第六晶体管T6和第七晶体管T7，使得子像素驱动电路仅能够在发光阶段驱动对应的发光元件OLED发光，避免了发光元件OLED出现异常发光的现象，从而更好的提升了显示面板的显示质量。
如图21和图22所示，在一些实施例中，所述子像素驱动电路还包括第一导电连接部701，所述第一晶体管T1的第二电极(即漏极D1)通过所述第一导电连接部701与所述驱动晶体管的栅极(即第三晶体管T3的栅极203g)耦接；所述显示面板还包括第三金属层，所述第一导电连接部701位于所述第三金属层，所述第一部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第一阳极501在所述基底上的正投影不交叠。
具体地，可将补偿功能图形401设置在数据线图形(如DATA1)和所述第一部分子像素驱动电路中包括的第一导电连接部之间，该数据线图形位于该第一部分子像素驱动电路中第一阳极的正下方；上述结构的显示面板中，能够通过补偿功能图形401，将驱动晶体管的栅极(即第三晶体管T3的栅极 203g)与数据线图形(如DATA1)隔开，从而更好的避免数据线图形上的信号变化，对所述驱动晶体管的栅极电位产生串扰。而且，上述结构的显示面板还避免了第一导电连接部701与所述补偿功能图形401之间发生短路。
进一步地，如图21和图23所示，所述补偿功能图形401能够与初始化信号线图形(如VINT1)耦接，使得所述补偿功能图形401具有固定电位，从而进一步避免了数据线图形上的信号变化，对所述驱动晶体管的栅极电位产生串扰。
另外，上述将所述第一导电连接部701位于所述第三金属层，使得所述第一导电连接部701能够与所述第三金属层中包括的其它图形在一次构图工艺中形成，从而很好的简化了显示基板的制作工艺流程。
如图24所示，在一些实施例中，所述显示面板还包括多个第二发光元件和多个第三发光元件；每个所述第二发光元件包括沿远离所述基底的方向上，依次层叠设置的第二阳极502、第二发光图形602和第二阴极；每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件均包括沿远离所述基底的方向上，依次层叠设置的第三阳极503、第三发光图形603和第三阴极；
所述多个子像素驱动电路还包括第二部分子像素驱动电路和第三部分子像素驱动电路，所述第二部分子像素驱动电路与所述第二发光元件一一对应，所述第二部分子像素驱动电路用于驱动对应的所述第二发光元件发光，所述第三部分子像素驱动电路与所述子发光元件一一对应，所述第三部分子像素驱动电路用于驱动对应的子发光元件发光；
所述第二部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第二阳极502在所述电极上的正投影交叠；所述第三部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第三阳极503在所述基底上的正投影交叠。
上述设置所述第二部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第二阳极502在所述电极上的正投影交叠；以及所述第三部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第三阳极503在所述基底上的正投影交叠，使得所述第二 阳极502和所述第三阳极503具有更高的平坦度。
如图15所示，在一些实施例中，所述第一晶体管T1的栅极201g与对应的所述栅极扫描线图形GATE直接接触。
具体地，可将所述第一晶体管T1的栅极201g与对应的所述栅极扫描线图形GATE同层制作，且形成为一体结构，这样不仅使得所述第一晶体管T1的栅极201g与对应的所述栅极扫描线图形GATE能够在同一次构图工艺中形成，而且形成的所述第一晶体管的栅极与对应的所述栅极扫描线图形GATE能够直接接触，不需要设置额外的用于连接所述第一晶体管的栅极和对应的所述栅极扫描线图形GATE的导电连接部。
在一些实施例中，所述第二晶体管的栅极、所述第七晶体管的栅极均可与对应的所述栅极扫描线图形GATE为一体结构，或者所述第二晶体管的栅极、所述第七晶体管的栅极均可与对应的所述栅极扫描线图形GATE直接接触，或者所述第二晶体管的栅极、所述第七晶体管的栅极均可作为对应的所述栅极扫描线图形GATE的一部分。
在一些实施例中，所述第一晶体管的第一电极在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影至少部分交叠；和/或，所述第一晶体管的第二电极在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影至少部分交叠。
具体地，如图15所示，上述结构的子像素驱动电路中，可设置所述补偿功能图形401在所述基底50上的正投影，与所述第一晶体管T1的第二电极(即图15中的N1节点)在所述基底50上的正投影至少部分交叠；和/或，可设置所述补偿功能图形401在所述基底50上的正投影，与所述第一晶体管T1的第一电极(形成在图15中的101ps处)在所述基底50上的正投影至少部分交叠。
上述设置方式使得在垂直于所述基底50的方向上，所述补偿功能图形401能够覆盖所述第一晶体管T1的第二电极，和/或，所述第一晶体管T1的第一电极，从而对所述第一晶体管T1的第二电极，和/或，所述第一晶体管T1的第一电极起到屏蔽作用，避免与所述第一晶体管T1相邻的数据线图形DATA上传输的数据信号发生变化时，对第一晶体管T1产生串扰；同时由于 所述第一晶体管T1的第二电极与所述第三晶体管T3的栅极203g耦接，所述第一晶体管T1的第一电极与所述第三晶体管T3的第二电极耦接，从而进一步避免了与所述第一晶体管T1相邻的数据线图形DATA上传输的数据信号发生变化时，对第三晶体管T3产生串扰。
如图21所示，在一些实施例中，所述第一晶体管T1的第一电极在所述基底上的正投影，与对应的所述补偿功能图形401在所述基底上的正投影不交叠；和/或，所述第一晶体管T1的第二电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
上述设置方式，不仅使得所述补偿功能图形401与所述第一导电连接部701之间具有较宽的距离，避免了所述补偿功能图形401与所述第一导电连接部701发生短路不良；而且，在保证了所述第一阳极501的平坦度的同时，避免了所述补偿功能图形401与所述屏蔽图形301之间形成寄生电容。
在一些实施例中，所述子像素驱动电路还包括第七晶体管T7，所述第七晶体管T7的栅极207g与复位信号线图形(如图15中的RST2)耦接，所述第一部分子像素驱动电路中的第七晶体管T7的第二电极与所述第一阳极501耦接，所述第一部分子像素驱动电路中的所述第七晶体管的第一电极在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影之间存在第七交叠区域，所述第七晶体管的第一电极通过设置在所述第七交叠区域的过孔与对应的所述补偿功能图形401耦接，以通过该补偿功能图形401与对应的所述初始化信号线图形VINT间接耦接。
具体地，当所述第七晶体管的第一电极在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影之间存在第七交叠区域时，可在该第七交叠区域制作过孔，使得所述第七晶体管的第一电极能够通过该过孔与所述补偿功能图形401耦接，同时由于所述补偿功能图形401与所述初始化信号线耦接，因此，可实现所述第七晶体管的第一电极通过所述补偿功能图形401与所述初始化信号线间接耦接。
上述实施例中，所述第七晶体管的第一电极通过所述补偿功能图形401与所述初始化信号线间接耦接，避免了制作专门的用于耦接所述第七晶体管的第一电极与所述初始化信号线的导电连接部，简化了显示面板的制作流程， 节约了生产成本。
值得注意，如图15所示，所述补偿功能图形401在所述基底50上的正投影，可与所述第七晶体管的第二极在所述基底50上的正投影交叠；或者，如图19所示，所述补偿功能图形401在所述基底50上的正投影，可与所述第七晶体管的第二极在所述基底50上的正投影不交叠。
如图15所示，在一些实施例中，所述驱动晶体管的栅极在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影至少部分交叠。
具体地，请继续参阅图15，通过设置所述驱动晶体管的栅极(即所述第三晶体管T3的栅极203g)在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影至少部分交叠，使得所述补偿功能图形401能够覆盖至少部分所述驱动晶体管的栅极，从而对所述驱动晶体管的栅极起到屏蔽作用，避免与所述驱动晶体管相邻的数据线图形DATA上传输的数据信号发生变化时，对驱动晶体管产生串扰，从而很好的保证了所述驱动晶体管具有稳定工作性能。
继续参阅图15，在一些实施例中，所述驱动晶体管的栅极在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影包括交叠的第一交叠部分；所述第一交叠部分在所述基底50上的正投影，与对应的所述第一阳极501在所述基底50上的正投影至少部分交叠。
具体地，上述设置方式使得在垂直于所述基底50的方向上，所述驱动晶体管的栅极、所述补偿功能图形401和所述第一阳极501存在公共的交叠区域，这样所述补偿功能图形401不仅能够避免与所述驱动晶体管相邻的数据线图形DATA上传输的数据信号发生变化时，对驱动晶体管产生串扰，还能够避免所述第一阳极501上传输的驱动信号发生变化时，对驱动晶体管产生串扰。
进一步地，可将所述补偿功能图形401设置在所述驱动晶体管的栅极与所述第一阳极501之间，这样所述补偿功能图形401能够更好的避免所述第一阳极501上传输的驱动信号发生变化时，对驱动晶体管产生串扰。
如图15所示，在一些实施例中，所述存储电容Cst的第一极板Cst1与所 述栅极扫描线图形GATE和所述复位信号线图形RST同材料设置，所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT同材料设置；所述存储电容Cst的第一极板Cst1在所述基底50上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影，均位于对应的所述栅极扫描线图形GATE在所述基底50上的正投影，与对应的所述发光控制信号线图形EM在所述基底50上的正投影之间。
具体地，在制作所述显示面板中的各功能图形时，可将所述显示面板中的部分功能图形采用相同的材料制作，示例性的，将所述显示面板中的部分具有导电性能的功能图形采用同种具有导电性能的材料制作，将所述显示面板中的部分具有绝缘性能的功能图形采用同种具有绝缘性能的材料制作。
更详细地说，可将所述存储电容Cst的第一极板Cst1与所述栅极扫描线图形GATE和所述复位信号线图形RST同材料设置，所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT同材料设置；这种设置方式使得在制作所述存储电容Cst的第一极板Cst1、所述栅极扫描线图形GATE和所述复位信号线图形RST时，能够采用相同的工艺设备在相同的制作环境中形成；同样的，在制作所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT，也能够采用相同的工艺设备在相同的制作环境中形成；因此，这种设置方式能够有效简化显示面板的制作工艺流程，节约显示面板的制作成本。
另外，在布局所述存储电容Cst的第一极板Cst1和第二极板Cst2时，可设置所述存储电容Cst的第一极板Cst1在所述基底50上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影，均位于对应的所述栅极扫描线图形GATE在所述基底50上的正投影，与对应的所述发光控制信号线图形在所述基底50上的正投影之间；这种设置方式不仅保证所述存储电容Cst的第一极板Cst1和第二极板Cst2在垂直于所述基底50的方向上能够具有一定的正对面积，还避免了在垂直于所述基底50的方向上，所述存储电容Cst的第一极板Cst1和第二极板Cst2，与所述栅极扫描线图形GATE和所述发光控制信号线图形之间产生交叠，从而使得所述存储电容Cst不会与所述栅极扫描线图形GATE和所述发光控制信号线图形EM之间形成其它寄生 电容，保证了所述子像素驱动电路稳定的工作性能。
在一些实施例中，所述功能膜层还包括栅极绝缘层(如图17中的GI1)，以及位于所述栅极绝缘层背向所述基底50的一侧的第一绝缘层(如图17中的GI2)；所述存储电容Cst的第一极板Cst1、所述栅极扫描线图形GATE和所述复位信号线图形RST均位于所述栅极绝缘层背向所述基底50的表面；所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT均位于所述第一绝缘层背向所述基底50的表面。
具体地，所述功能膜层还包括所述栅极绝缘层和所述第一绝缘层，所述栅极绝缘层用于将薄膜晶体管中的栅极与有源层之间绝缘，所述第一绝缘层用于将显示基板中异层设置的导电功能图形之间绝缘。
在布局所述显示基板的功能膜层时，示例性的，可将所述存储电容Cst的第一极板Cst1、所述栅极扫描线图形GATE和所述复位信号线图形RST均设置于所述栅极绝缘层背向所述基底50的表面；这样在采用同种材料制作所述存储电容Cst的第一极板Cst1、所述栅极扫描线图形GATE和所述复位信号线图形RST时，所述存储电容Cst的第一极板Cst1、所述栅极扫描线图形GATE和所述复位信号线图形RST能够在同一次构图工艺中同时形成。
同样的，可将所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT均设置于所述第一绝缘层背向所述基底50的表面；这样在采用同种材料制作所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT时，所述存储电容Cst的第二极板Cst2与所述初始化信号线图形VINT能够在同一次构图工艺中同时形成。
按照上述方式布局所述显示面板中的功能膜层时，不仅能够有效节省布局空间，有利于所述显示面板的薄型化，而且，能够有效简化所述显示面板的制作工艺流程，节约显示面板的制作成本。
如图15所示，在一些实施例中，所述存储电容Cst的第一极板Cst1在所述基底50上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影，均与对应的所述第一阳极501在所述基底50上的正投影部分交叠。
具体地，在布局所述存储电容Cst的第一极板Cst1和第二极板Cst2时， 示例性的，可设置所述存储电容Cst的第一极板Cst1在所述基底50上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影，均与对应的所述第一阳极501在所述基底50上的正投影交部分叠；由于所述第一阳极501与所述存储电容Cst的第一极板Cst1和第二极板Cst2均异层设置，因此，这种布局方式在避免了所述第一阳极501与所述存储电容Cst的第一极板Cst1和第二极板Cst2之间发生短路的同时，更大程度的利用了显示面板的布局空间。
如图15所示，在一些实施例中，所述存储电容Cst的第一极板Cst1在所述基底50上的正投影，以及所述存储电容Cst的第二极板Cst2在所述基底50上的正投影，均与对应的所述补偿功能图形401在所述基底50上的正投影部分交叠。
具体地，请继续参阅图15，通过设置所述补偿功能图形401在所述基底50上的正投影，与所述存储电容Cst的第一极板Cst1和第二极板Cst2在所述基底50上的正投影均至少部分交叠，使得所述补偿功能图形401能够覆盖所述存储电容Cst的第一极板Cst1的至少部分，以及所述第二极板Cst2的至少部分，这样所述补偿功能图形401不仅能够避免与所述存储电容Cst相邻的数据线图形DATA上传输的数据信号发生变化时，对存储电容Cst产生串扰，还能够避免所述第一阳极501上传输的驱动信号发生变化时，对存储电容Cst产生串扰，从而更好的保证了所述显示面板中子像素驱动电路工作的稳定性。
如图13和图15所示，在一些实施例中，所述存储电容Cst的第二极板Cst2的中心区域包括开口302，所述开口302在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影不交叠。
具体地，所述存储电容Cst的第二极板Cst2上的开口302所在的区域一般用于形成过孔和穿过该过孔的导电部，该过孔和导电部用于将位于所述第二极板上下两侧的功能图形耦接在一起。
上述实施例提供的显示面板中，通过设置所述开口302在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影不交叠，能够更好的避免所述补偿功能图形401与所述开口302处的导电部发生短路， 从而更好的保证了所述显示面板中子像素驱动电路工作的稳定性。
值得注意，在布局空间受限的情况下，也可以设置所述开口302在所述基底50上的正投影，与对应的所述补偿功能图形401在所述基底50上的正投影部分交叠，只需保证所述补偿功能图形401与所述开口302处的导电部不会发生短路即可。
如图15和图18所示，在一些实施例中，可设置所述补偿功能图形401在所述基底50上的正投影，与所述屏蔽图形301在所述基底上的正投影部分交叠；或者，如图20所示，在一些实施例中，可设置所述补偿功能图形401在所述基底50上的正投影，与所述屏蔽图形301在所述基底上的正投影不交叠。
在一些实施例中，在垂直于所述基底50的方向上，所述补偿功能层与所述电源信号线层之间的厚度差在阈值范围内；或者，所述补偿功能层与所述数据线层之间的厚度差在阈值范围内。
具体地，在制作所述补偿功能图形401时，所述补偿功能图形401在垂直所述基底50的方向上的厚度可根据实际需要设置，示例性的，在垂直于所述基底50的方向上，设置所述补偿功能层与所述电源信号线层之间的厚度差在阈值范围内；或者，所述补偿功能层与所述数据线层之间的厚度差在阈值范围内；这种设置方式使得所述补偿功能层能够很好的补偿所述电源信号线层和所述数据线层产生的段差。
值得注意，所述阈值范围可设置为小于或等于0.1μm，这样就使得在垂直于所述基底50的方向上，所述补偿功能层、所述电源信号线层和所述数据线层的厚度相接近，从而更好的保证了对段差的补偿效果。
如图24和图26所示，在一些实施例中，所述显示面板还包括多个第二发光元件；每个所述第二发光元件包括沿远离所述基底50的方向上，依次层叠设置的第二阳极502、第二发光图形602和第二阴极；所述第二阳极502包括沿所述第二方向相对设置的第五边缘部分502a1和第六边缘部分502a2，以及位于所述第五边缘部分502a1和所述第六边缘部分502a2之间的第二中间部分502a3，所述第二中间部分502a3在所述基底50上的正投影与所述第二发光图形602在所述基底50上的正投影重合；
所述第二中间部分502a3在所述基底50上的正投影与对应的所述电源信号线图形VDD在所述基底50上的正投影至少部分重叠，所述第二中间部分502a3在所述基底50上的正投影与对应的所述数据线图形DATA在所述基底50上的正投影至少部分重叠。
具体地，所述显示面板还可以包括第二发光元件，所述第二发光元件与所述第一发光元件的发光颜色不同，所述第二发光元件可包括沿远离所述基底50的方向上，依次层叠设置的第二阳极502、第二发光图形602和第二阴极，所述第二阳极502与显示面板中对应的第二子像素驱动电路耦接，接收由该第二子像素驱动电路提供的驱动信号，所述第二阴极接收公共信号，在所述第二阳极502和所述第二阴极的共同作用下，所述第二发光图形602发出对应颜色的光。
所述第二阳极502的结构多种多样，示例性的，所述第二阳极502包括沿所述第二方向相对设置的第五边缘部分502a1和第六边缘部分502a2，以及位于所述第五边缘部分502a1和所述第六边缘部分502a2之间的第二中间部分502a3。
在布局所述第二发光元件时，可设置所述第二中间部分502a3在所述基底50上的正投影与所述第二发光图形602在所述基底50上的正投影重合，所述第二中间部分502a3在所述基底50上的正投影与对应的所述电源信号线图形VDD在所述基底50上的正投影至少部分重叠，所述第二中间部分502a3在所述基底50上的正投影与对应的所述数据线图形DATA在所述基底50上的正投影至少部分重叠；这种布局方式使得所述第二阳极502的中间部分能够均匀的覆盖所述电源信号线图形VDD和所述数据线图形DATA，从而使得所述第二阳极502的中间部分具有较高的平坦度，这样在将所述第二发光图形602形成在所述第二阳极502的第二中间部分502a3上时，能够保证所述第二发光图形602具有较高的平坦度，从而保证了第二发光元件的发光效果，弱化了所述显示面板显示时出现的色偏现象。
如图26所示，在一些实施例中，所述第二发光图形602关于第二对称轴对称，所述第二对称轴沿所述第一方向延伸，所述第二对称轴在所述基底50上的正投影，位于对应的所述电源信号线图形VDD在所述基底50上的正投 影的内部。
具体地，所述第二发光图形602的结构可根据实际需要设置，示例性的，设置所述第二发光图形602为轴对称图形，这样更有利于提升所述第二发光元件出光的均匀性。
进一步地，可设置所述第二发光图形602关于第二对称轴对称，该第二对称轴沿所述第一方向延伸，且所述第二对称轴在所述基底50上的正投影，位于对应的所述电源信号线图形VDD在所述基底50上的正投影的内部，这种布局方式使得所述第二发光图形602的中心部分能够覆盖所述电源信号线图形VDD，而由于所述电源信号线图形VDD沿所述第一方向延伸，且在垂直于所述第一方向上的宽度较宽，因此，使得所述第二发光图形602的大部分均形成在所述电源信号线图形VDD上，从而更好的保证了所述第二发光图形602的平坦度，弱化了所述显示面板显示时出现的色偏现象。
如图24和图27所示，在一些实施例中，所述显示面板还包括多个第三发光元件；每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件均包括沿远离所述基底50的方向上，依次层叠设置的第三阳极503、第三发光图形603和第三阴极；所述第三阳极503包括沿所述第二方向相对设置的第七边缘部分503a1和第八边缘部分503a2，以及位于所述第七边缘部分503a1和所述第八边缘部分503a2之间的第三中间部分，所述第三中间部分在所述基底50上的正投影与所述第三发光图形603在所述基底50上的正投影重合；
所述第三中间部分在所述基底50上的正投影与对应的所述数据线图形DATA在所述基底50上的正投影至少部分重叠；所述第七边缘部分503a1在所述基底50上的正投影与对应的电源信号线图形VDD在所述基底50上的正投影至少部分重叠。
具体地，所述显示面板还可以包括多个第三发光元件，每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件与所述第一发光元件和所述第二发光元件的发光颜色均不同，所述子发光元件可包括沿远离所述基底50的方向上，依次层叠设置的第三阳极503、第三发光图形603和第三阴极，所述第三阳极503与显示面板中对应的第三 子像素驱动电路耦接，接收由该第三子像素驱动电路提供的驱动信号，所述第三阴极接收公共信号，在所述第三阳极503和所述第三阴极的共同作用下，所述第三发光图形603发出对应颜色的光。
所述第三阳极503的结构多种多样，示例性的，所述第三阳极503包括沿所述第二方向相对设置的第七边缘部分和第八边缘部分，以及位于所述第七边缘部分和所述第八边缘部分之间的第三中间部分。
在布局所述第三发光元件时，可设置所述第三中间部分在所述基底50上的正投影与所述第三发光图形603在所述基底50上的正投影重合；所述第三中间部分在所述基底50上的正投影与对应的所述数据线图形DATA在所述基底50上的正投影至少部分重叠；所述第七边缘部分在所述基底50上的正投影与对应的电源信号线图形VDD在所述基底50上的正投影至少部分重叠；这种布局方式使得所述第三阳极503与对应的电源信号线图形VDD和数据线图形DATA交叠的面积较小，能够保证所述第三发光图形603具有较高的平坦度，从而保证了第三发光元件的发光效果，弱化了所述显示面板显示时出现的色偏现象。
在一些实施例中，所述第一发光元件包括红色子像素，所述第二发光元件包括蓝色子像素，所述第三发光元件包括绿色子像素。
具体地，所述第一发光元件、所述第二发光元件和所述第三发光元件的发光颜色可根据实际需要设置，示例性的，所述第一发光元件包括红色子像素，所述第二发光元件包括蓝色子像素，所述第三发光元件包括绿色子像素。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示面板。
上述实施例提供的显示面板中，所述补偿功能图形401能够补偿所述电源信号线图形VDD和所述数据线图形DATA在所述第一阳极501下方产生的段差，使得所述显示面板中，第一发光元件包括的第一阳极501在同时覆盖部分对应的所述电源信号线图形VDD，部分对应的所述数据线图形DATA，以及至少部分对应的补偿功能图形401时，该第一阳极501能够具有较高的平坦度，从而有效减小了显示面板在显示时产生的色偏现象；因此，本公开实施例提供的显示装置在包括上述实施例提供的显示面板时，同样具有上述有益效果。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示面板的制作方法，所述显示面板包括阵列排布的多个子像素区，所述制作方法包括：
在基底50上制作功能膜层；所述功能膜层包括：电源信号线层、数据线层和补偿功能层；所述电源信号线层包括设置于各所述子像素区中的电源信号线图形VDD，所述数据线层包括设置于各所述子像素区中的数据线图形DATA，所述电源信号线图形VDD包括沿第一方向延伸的第一部分，所述数据线图形DATA沿所述第一方向延伸；所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形401；
在所述功能膜层背向所述基底50的一侧制作多个第一发光元件，每个所述第一发光元件均包括：沿远离所述基底50的方向上，依次层叠设置的第一阳极501、第一发光图形601和第一阴极；所述第一阳极501在所述基底50上的正投影，与对应的所述电源信号线图形VDD在所述基底50上的正投影存在第一交叠区域F1，与对应的所述数据线图形DATA在所述基底50上的正投影存在第二交叠区域F2，与对应的所述补偿功能图形401在所述基底50上的正投影存在第三交叠区域F3，所述第二交叠区域F2位于所述第一交叠区域F1和所述第三交叠区域F3之间。
具体地，阵列排布的多个子像素区能够划分为沿第一方向延伸的子像素区列，以及沿第二方向延伸的子像素区行，所述子像素区列包括沿所述第一方向排列的多个子像素区，所述子像素区行包括沿所述第二方向排列的多个子像素区；所述第一方向与所述第二方向相交，示例性的，所述第一方向包括Y方向，所述第二方向包括X方向。
所述电源信号线层包括设置于各所述子像素区中的电源信号线图形VDD，所述电源信号线图形VDD可选为网格状，该网格状的电源信号线图形VDD包括沿所述第一方向延伸的第一部分。所述电源信号线图形VDD与所述子像素区列一一对应，所述电源信号线图形VDD位于对应的所述子像素区列中包括的各子像素区中。
所述数据线层包括设置于各所述子像素区中的数据线图形DATA，所述 数据线图形DATA沿所述第一方向延伸，所述数据线图形DATA与所述子像素区列一一对应，所述数据线图形DATA位于对应的所述子像素区列中包括的各子像素区中。
所述显示面板还包括位于所述功能膜层背向所述基底50的一侧的多个第一发光元件，所述第一发光元件包括：沿远离所述基底50的方向上，依次层叠设置的第一阳极501、第一发光图形601和第一阴极；显示面板工作时，向所述第一阳极501提供驱动信号，向所述第一阴极提供公共信号，使得在所述第一阳极501和所述第一阴极之间产生电场，从而控制所述第一发光图形601发出对应颜色的光；示例性的，所述第一发光元件包括红色发光元件，能够发出红光。
所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形401，示例性的，所述补偿功能图形401与所述第一发光元件一一对应；
在制作所述显示面板时，先在基底50上形成功能膜层，然后在该功能膜层背向所述基底50的一侧制作第一发光元件，在制作所述功能膜层时，所述电源信号线图形VDD与所述数据线图形DATA可沿所述第二方向交替排列，所述补偿功能图形401可设置在对应的第一发光元件的附近，示例性的，所述第一发光元件中的所述第一阳极501在所述基底50上的正投影，与对应的所述电源信号线图形VDD在所述基底50上的正投影存在第一交叠区域F1，与对应的所述数据线图形DATA在所述基底50上的正投影存在第二交叠区域F2，与对应的所述补偿功能图形401在所述基底50上的正投影存在第三交叠区域F3，所述第二交叠区域F2位于所述第一交叠区域F1和所述第三交叠区域F3之间。
采用本公开实施例提供的制作方法制作显示面板中，所述补偿功能图形401能够补偿所述电源信号线图形VDD和所述数据线图形DATA在所述第一阳极501下方产生的段差，使得所述显示面板中，第一发光元件包括的第一阳极501在同时覆盖部分对应的所述电源信号线图形VDD，部分对应的所述数据线图形DATA，以及至少部分对应的补偿功能图形401时，该第一阳极501能够具有较高的平坦度，从而有效减小了显示面板在显示时产生的色偏现象。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“耦接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种显示面板，包括：基底、设置在所述基底上的功能膜层、以及设置在所述功能膜层背向所述基底的一侧的多个第一发光元件；还包括阵列排布的多个子像素区；
    所述功能膜层包括：电源信号线层、数据线层和补偿功能层；所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述数据线层包括设置于各所述子像素区中的数据线图形，所述电源信号线图形包括沿第一方向延伸的第一部分，所述数据线图形沿所述第一方向延伸；所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形；
    每个所述第一发光元件均包括：沿远离所述基底的方向上，依次层叠设置的第一阳极、第一发光图形和第一阴极；所述第一阳极在所述基底上的正投影，与对应的所述电源信号线图形在所述基底上的正投影存在第一交叠区域，与对应的所述数据线图形在所述基底上的正投影存在第二交叠区域，与对应的所述补偿功能图形在所述基底上的正投影存在第三交叠区域，所述第二交叠区域位于所述第一交叠区域和所述第三交叠区域之间。
  2. 根据权利要求1所述的显示面板，其中，所述第一阳极包括沿第二方向相对设置的第一边缘部分和第二边缘部分，以及位于所述第一边缘部分和所述第二边缘部分之间的第一中间部分；所述第二方向与所述第一方向相交；
    所述第一边缘部分在所述基底上的正投影包括所述第一交叠区域；所述第二边缘部分在所述基底上的正投影包括所述第三交叠区域；所述第一中间部分在所述基底上的正投影包括所述第二交叠区域。
  3. 根据权利要求2所述的显示面板，其中，所述第一边缘部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影不交叠，所述第二边缘部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影不交叠；所述第一中间部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影交叠。
  4. 根据权利要求2所述的显示面板，其中，所述功能膜层还包括：栅极扫描线层、初始化信号线层、复位信号线层和发光控制信号线层；
    所述栅极扫描线层包括设置于各所述子像素区中的栅极扫描线图形，所述初始化信号线层包括设置于各所述子像素区中的初始化信号线图形，所述复位信号线层包括设置于各所述子像素区中的复位信号线图形，所述发光控制信号线层包括设置于各所述子像素区中的发光控制信号线图形；所述栅极扫描线图形、所述初始化信号线图形、所述复位信号线图形和所述发光控制信号线图形均沿第二方向延伸，所述第二方向与所述第一方向相交。
  5. 根据权利要求4所述的显示面板，其中，
    所述第一阳极还包括沿所述第一方向相对设置的第三边缘部分和第四边缘部分，所述第一中间部分位于所述第三边缘部分和第四边缘部分之间；所述第三边缘部分分别与所述第一边缘部分和所述第二边缘部分耦接，所述第四边缘部分分别与所述第一边缘部分和所述第二边缘部分耦接；
    所述第一中间部分在所述基底上的正投影与对应的所述栅极扫描线图形在所述基底上的正投影，以及对应的所述复位信号线图形在所述基底上的正投影包括第六交叠区域。
  6. 根据权利要求5所述的显示面板，其中，所述第一阳极包括主体部分和过孔连接部分，所述主体部分包括所述第一边缘部分、所述第二边缘部分、所述第三边缘部分、所述第四边缘部分和所述第一中间部分；所述主体部分为中心对称图形。
  7. 根据权利要求2所述的显示面板，其中，所述第一中间部分为中心对称图形，所述第一中间部分在所述基底上的正投影与所述第一发光图形在所述基底上的正投影重合。
  8. 根据权利要求4所述的显示面板，其中，所述显示面板包括第一金属层、第二金属层和第三金属层；
    所述栅极扫描线层、所述复位信号线层和所述发光控制信号线层位于所述第一金属层中；
    所述初始化信号线层位于所述第二金属层中；
    所述数据线层、所述电源信号线层和所述补偿功能层位于所述第三金属层中；
    所述功能膜层还包括第一绝缘层和第二绝缘层，所述第一绝缘层位于所 述第一金属层和所述第二金属层之间，所述第二绝缘层位于所述第二金属层和所述第三金属层之间。
  9. 根据权利要求4所述的显示面板，其中，所述补偿功能图形采用导电材料制作，且与所述初始化信号线图形耦接。
  10. 根据权利要求9所述的显示面板，其中，所述补偿功能图形与所述数据线图形同层设置。
  11. 根据权利要求4所述的显示面板，其中，所述显示面板还包括：多个子像素驱动电路，所述多个子像素驱动电路中的第一部分子像素驱动电路与所述第一发光元件一一对应，所述第一部分子像素驱动电路用于驱动对应的所述第一发光元件发光；所述子像素驱动电路包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管和存储电容；
    所述第一晶体管的栅极与对应的所述栅极扫描线图形耦接，所述第一晶体管的第一电极与所述驱动晶体管的第二电极耦接，所述第一晶体管的第二电极与所述驱动晶体管的栅极耦接；
    所述第二晶体管的栅极与对应的所述复位信号线图形耦接，所述第二晶体管的第一电极与对应的所述初始化信号线图形耦接，所述第二晶体管的第二电极与所述驱动晶体管的栅极耦接；
    所述第四晶体管的栅极与对应的所述栅极扫描线图形耦接，所述第四晶体管的第一电极与对应的所述数据线图形耦接，所述第四晶体管的第二电极与所述驱动晶体管的第一电极耦接；
    所述驱动晶体管的第一电极与对应的所述电源信号线图形耦接，所述驱动晶体管的第二电极与对应的所述第一发光元件耦接；
    所述存储电容的第一极板与所述驱动晶体管的栅极耦接，所述存储电容的第二极板与对应的所述电源信号线图形耦接。
  12. 根据权利要求11所述的显示面板，其中，所述子像素驱动电路还包括第一导电连接部，所述第一晶体管的第二电极通过所述第一导电连接部与所述驱动晶体管的栅极耦接；
    所述显示面板还包括第三金属层，所述第一导电连接部位于所述第三金属层，所述第一部分子像素驱动电路中包括的第一导电连接部在所述基底上 的正投影，与其对应的第一阳极在所述基底上的正投影不交叠。
  13. 根据权利要求12所述的显示面板，其中，所述显示面板还包括多个第二发光元件和多个第三发光元件；每个所述第二发光元件包括沿远离所述基底的方向上，依次层叠设置的第二阳极、第二发光图形和第二阴极；每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件均包括沿远离所述基底的方向上，依次层叠设置的第三阳极、第三发光图形和第三阴极；
    所述多个子像素驱动电路还包括第二部分子像素驱动电路和第三部分子像素驱动电路，所述第二部分子像素驱动电路与所述第二发光元件一一对应，所述第二部分子像素驱动电路用于驱动对应的所述第二发光元件发光，所述第三部分子像素驱动电路与所述子发光元件一一对应，所述第三部分子像素驱动电路用于驱动对应的子发光元件发光；
    所述第二部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第二阳极在所述电极上的正投影交叠；所述第三部分子像素驱动电路中包括的第一导电连接部在所述基底上的正投影，与其对应的第三阳极在所述基底上的正投影交叠。
  14. 根据权利要求11所述的显示面板，其中，所述第一晶体管的栅极与对应的所述栅极扫描线图形直接接触。
  15. 根据权利要求11所述的显示面板，其中，所述第一晶体管的第一电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
  16. 根据权利要求11所述的显示面板，其中，所述第一晶体管的第二电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
  17. 根据权利要求11所述的显示面板，其中，所述子像素驱动电路还包括第七晶体管，所述第七晶体管的栅极与复位信号线图形耦接，第一部分子像素驱动电路中第七晶体管的第二电极与所述第一阳极耦接，该第七晶体管的第一电极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影之间存在第七交叠区域，所述第七晶体管的第一电极通过设置在 所述第七交叠区域的过孔与对应的所述补偿功能图形耦接，以通过该补偿功能图形与对应的所述初始化信号线图形间接耦接。
  18. 根据权利要求11所述的显示面板，其中，所述驱动晶体管的栅极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影至少部分交叠。
  19. 根据权利要求18所述的显示面板，其中，所述驱动晶体管的栅极在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影包括交叠的第一交叠部分；
    所述第一交叠部分在所述基底上的正投影，与对应的所述第一阳极在所述基底上的正投影至少部分交叠。
  20. 根据权利要求11所述的显示面板，其中，所述存储电容的第一极板与所述栅极扫描线图形和所述复位信号线图形同材料设置，所述存储电容的第二极板与所述初始化信号线图形同材料设置；
    所述存储电容的第一极板在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影，均位于对应的所述栅极扫描线图形在所述基底上的正投影，与对应的所述发光控制信号线图形在所述基底上的正投影之间。
  21. 根据权利要求11所述的显示面板，其中，所述功能膜层还包括栅极绝缘层，以及位于所述栅极绝缘层背向所述基底的一侧的第一绝缘层；所述存储电容的第一极板、所述栅极扫描线图形和所述复位信号线图形均位于所述栅极绝缘层背向所述基底的表面；所述存储电容的第二极板与所述初始化信号线图形均位于所述第一绝缘层背向所述基底的表面。
  22. 根据权利要求11所述的显示面板，其中，所述存储电容的第一极板在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影，均与对应的所述第一阳极在所述基底上的正投影部分交叠。
  23. 根据权利要求11所述的显示面板，其中，所述存储电容的第一极板在所述基底上的正投影，以及所述存储电容的第二极板在所述基底上的正投影，均与对应的所述补偿功能图形在所述基底上的正投影部分交叠。
  24. 根据权利要求11所述的显示面板，其中，所述存储电容的第二极板 的中心区域包括开口，所述开口在所述基底上的正投影，与对应的所述补偿功能图形在所述基底上的正投影不交叠。
  25. 根据权利要求1所述的显示面板，其中，在垂直于所述基底的方向上，所述补偿功能层与所述电源信号线层之间的厚度差在阈值范围内；或者，所述补偿功能层与所述数据线层之间的厚度差在阈值范围内。
  26. 根据权利要求1所述的显示面板，其中，所述显示面板还包括多个第二发光元件；
    每个所述第二发光元件包括沿远离所述基底的方向上，依次层叠设置的第二阳极、第二发光图形和第二阴极；所述第二阳极包括沿所述第二方向相对设置的第五边缘部分和第六边缘部分，以及位于所述第五边缘部分和所述第六边缘部分之间的第二中间部分，所述第二中间部分在所述基底上的正投影与所述第二发光图形在所述基底上的正投影重合；
    所述第二中间部分在所述基底上的正投影与对应的所述电源信号线图形在所述基底上的正投影至少部分重叠，所述第二中间部分在所述基底上的正投影与对应的所述数据线图形在所述基底上的正投影至少部分重叠。
  27. 根据权利要求26所述的显示面板，其中，所述第二发光图形关于第二对称轴对称，所述第二对称轴沿所述第一方向延伸，所述第二对称轴在所述基底上的正投影，位于对应的所述电源信号线图形在所述基底上的正投影的内部。
  28. 根据权利要求26所述的显示面板，其中，所述显示面板还包括多个第三发光元件；
    每个所述第三发光元件均包括沿所述第一方向相对设置的两个子发光元件，每个所述子发光元件均包括沿远离所述基底的方向上，依次层叠设置的第三阳极、第三发光图形和第三阴极；所述第三阳极包括沿所述第二方向相对设置的第七边缘部分和第八边缘部分，以及位于所述第七边缘部分和所述第八边缘部分之间的第三中间部分，所述第三中间部分在所述基底上的正投影与所述第三发光图形在所述基底上的正投影重合；
    所述第三中间部分在所述基底上的正投影与对应的所述数据线图形在所述基底上的正投影至少部分重叠；
    所述第七边缘部分在所述基底上的正投影与对应的电源信号线图形在所述基底上的正投影至少部分重叠。
  29. 根据权利要求28所述的显示面板，其中，所述第一发光元件包括红色子像素，所述第二发光元件包括蓝色子像素，所述第三发光元件包括绿色子像素。
  30. 一种显示装置，包括如权利要求1～29中任一项所述的显示面板。
  31. 一种显示面板的制作方法，所述显示面板包括阵列排布的多个子像素区，所述制作方法包括：
    在基底上制作功能膜层；所述功能膜层包括：电源信号线层、数据线层和补偿功能层；所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述数据线层包括设置于各所述子像素区中的数据线图形，所述电源信号线图形包括沿第一方向延伸的第一部分，所述数据线图形沿所述第一方向延伸；所述补偿功能层包括设置于至少一个所述子像素区中的补偿功能图形；
    在所述功能膜层背向所述基底的一侧制作多个第一发光元件，每个所述第一发光元件均包括：沿远离所述基底的方向上，依次层叠设置的第一阳极、第一发光图形和第一阴极；所述第一阳极在所述基底上的正投影，与对应的所述电源信号线图形在所述基底上的正投影存在第一交叠区域，与对应的所述数据线图形在所述基底上的正投影存在第二交叠区域，与对应的所述补偿功能图形在所述基底上的正投影存在第三交叠区域，所述第二交叠区域位于所述第一交叠区域和所述第三交叠区域之间。
PCT/CN2019/119953 2019-11-21 2019-11-21 显示面板及其制作方法、显示装置 WO2021097754A1 (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
CN201980002526.4A CN113348558A (zh) 2019-11-21 2019-11-21 显示面板及其制作方法、显示装置
US17/255,884 US12035581B2 (en) 2019-11-21 2019-11-21 Display panel, method for manufacturing display panel, and display device
EP19945471.1A EP4064357A4 (en) 2019-11-21 2019-11-21 DISPLAY PANEL AND METHOD OF MANUFACTURE THEREOF, AND DISPLAY DEVICE
PCT/CN2019/119953 WO2021097754A1 (zh) 2019-11-21 2019-11-21 显示面板及其制作方法、显示装置
JP2021572448A JP7401064B2 (ja) 2019-11-21 2019-11-21 表示パネル及びその製作方法、表示装置
JP2023199938A JP2024028766A (ja) 2019-11-21 2023-11-27 表示パネル及びその製作方法、表示装置
US18/734,462 US20240324370A1 (en) 2019-11-21 2024-06-05 Display panel, method for manufacturing display panel, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/119953 WO2021097754A1 (zh) 2019-11-21 2019-11-21 显示面板及其制作方法、显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/255,884 A-371-Of-International US12035581B2 (en) 2019-11-21 2019-11-21 Display panel, method for manufacturing display panel, and display device
US18/734,462 Continuation US20240324370A1 (en) 2019-11-21 2024-06-05 Display panel, method for manufacturing display panel, and display device

Publications (2)

Publication Number Publication Date
WO2021097754A1 WO2021097754A1 (zh) 2021-05-27
WO2021097754A9 true WO2021097754A9 (zh) 2023-12-21

Family

ID=75980318

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/119953 WO2021097754A1 (zh) 2019-11-21 2019-11-21 显示面板及其制作方法、显示装置

Country Status (5)

Country Link
US (2) US12035581B2 (zh)
EP (1) EP4064357A4 (zh)
JP (2) JP7401064B2 (zh)
CN (1) CN113348558A (zh)
WO (1) WO2021097754A1 (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113345923B (zh) * 2021-06-01 2024-04-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN113823639B (zh) * 2021-09-09 2024-02-27 武汉天马微电子有限公司 显示面板及显示装置
CN116918489A (zh) * 2021-09-18 2023-10-20 京东方科技集团股份有限公司 显示基板及显示装置
CN113936600A (zh) * 2021-11-10 2022-01-14 云谷（固安）科技有限公司 像素电路及显示面板
CN116601768A (zh) * 2021-11-29 2023-08-15 京东方科技集团股份有限公司 显示基板和显示装置
WO2023130439A1 (zh) * 2022-01-10 2023-07-13 京东方科技集团股份有限公司 显示基板和显示装置
WO2023225889A1 (zh) * 2022-05-25 2023-11-30 京东方科技集团股份有限公司 显示基板及显示装置
WO2024186022A1 (ko) * 2023-03-03 2024-09-12 삼성디스플레이주식회사 표시장치
WO2024187307A1 (zh) * 2023-03-10 2024-09-19 京东方科技集团股份有限公司 显示基板和显示装置
CN116312372A (zh) * 2023-03-29 2023-06-23 武汉天马微电子有限公司 一种显示面板及其驱动方法、显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101666947B (zh) * 2008-09-03 2011-04-13 北京京东方光电科技有限公司 像素单元结构
CN101770108B (zh) * 2008-12-26 2012-11-21 北京京东方光电科技有限公司 彩膜基板及制造方法和液晶显示面板
CN102222780A (zh) * 2011-06-01 2011-10-19 友达光电股份有限公司 一种有源矩阵型有机发光二极管器件的制造方法
CN103985671B (zh) * 2014-04-30 2016-06-15 京东方科技集团股份有限公司 阵列基板制备方法和阵列基板、显示装置
CN104078470B (zh) * 2014-06-18 2017-02-15 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
KR102210587B1 (ko) * 2014-12-30 2021-02-02 엘지디스플레이 주식회사 액정표시장치
CN105182625A (zh) * 2015-09-28 2015-12-23 京东方科技集团股份有限公司 一种显示基板及其制作方法和显示装置
CN105552102B (zh) 2015-12-23 2019-07-02 昆山国显光电有限公司 像素排布结构及其制造方法，显示器
KR101937768B1 (ko) * 2016-12-01 2019-01-11 엘지디스플레이 주식회사 유기 발광 표시 장치
CN108376528B (zh) * 2017-02-01 2022-12-27 精工爱普生株式会社 电光装置、电子设备及头戴显示器
KR20180093188A (ko) 2017-02-10 2018-08-21 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102519065B1 (ko) * 2017-03-02 2023-04-07 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102391918B1 (ko) 2017-05-23 2022-04-29 삼성디스플레이 주식회사 유기발광표시장치
CN109388269B (zh) * 2017-08-11 2021-11-05 京东方科技集团股份有限公司 触摸显示面板及其驱动方法、触摸显示装置
KR102404266B1 (ko) * 2017-08-31 2022-05-30 엘지디스플레이 주식회사 전계발광 표시장치
CN110137212B (zh) 2018-02-09 2022-05-27 京东方科技集团股份有限公司 像素排列结构、显示基板以及显示装置
CN108597374B (zh) * 2018-04-20 2021-02-02 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN114843313A (zh) 2019-03-28 2022-08-02 京东方科技集团股份有限公司 阵列基板、显示面板
CN110021654B (zh) * 2019-04-24 2021-11-09 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Also Published As

Publication number Publication date
JP7401064B2 (ja) 2023-12-19
WO2021097754A1 (zh) 2021-05-27
US20240324370A1 (en) 2024-09-26
JP2024028766A (ja) 2024-03-05
EP4064357A1 (en) 2022-09-28
CN113348558A (zh) 2021-09-03
JP2023510991A (ja) 2023-03-16
EP4064357A4 (en) 2022-11-30
US20210359075A1 (en) 2021-11-18
US12035581B2 (en) 2024-07-09

Similar Documents

Publication Publication Date Title
WO2021097754A9 (zh) 显示面板及其制作方法、显示装置
WO2021104481A9 (zh) 显示基板、显示装置
WO2021227758A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021227760A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021227759A1 (zh) 一种显示面板及其制作方法、显示装置
WO2021227761A1 (zh) 一种显示面板及其制作方法、显示装置
CN113853643B (zh) 显示基板及其制作方法、显示装置
JP7566796B2 (ja) 表示パネル及びその製作方法、表示装置
US11877482B2 (en) Display substrate and method for manufacturing the same, driving method and display device
WO2021258318A1 (zh) 显示基板及其制作方法、显示装置
WO2022160125A1 (zh) 像素驱动电路及其驱动方法、显示基板、显示装置
CN114616616B (zh) 一种显示基板及其制作方法、显示装置
WO2022041237A1 (zh) 一种显示基板及其制作方法、显示装置
CN114450797B (zh) 一种显示基板及其制作方法、显示装置
WO2021227023A1 (zh) 显示面板及其制作方法、显示装置
WO2022041246A9 (zh) 一种显示基板及其制作方法、显示装置
WO2023130439A1 (zh) 显示基板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19945471

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021572448

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019945471

Country of ref document: EP

Effective date: 20220621