WO2021227023A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021227023A1
WO2021227023A1 PCT/CN2020/090539 CN2020090539W WO2021227023A1 WO 2021227023 A1 WO2021227023 A1 WO 2021227023A1 CN 2020090539 W CN2020090539 W CN 2020090539W WO 2021227023 A1 WO2021227023 A1 WO 2021227023A1
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WIPO (PCT)
Prior art keywords
conductive connection
signal line
pixel
line pattern
sub
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Application number
PCT/CN2020/090539
Other languages
English (en)
French (fr)
Inventor
孙开鹏
黄炜赟
王彬艳
吴超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP23157305.6A priority Critical patent/EP4213605A1/en
Priority to CN202080000747.0A priority patent/CN114207696B/zh
Priority to CN202210405819.0A priority patent/CN114743484A/zh
Priority to EP20897678.7A priority patent/EP3996072B1/en
Priority to PCT/CN2020/090539 priority patent/WO2021227023A1/zh
Priority to US17/280,364 priority patent/US11968864B2/en
Publication of WO2021227023A1 publication Critical patent/WO2021227023A1/zh
Priority to US17/851,653 priority patent/US20220328607A1/en
Priority to US18/396,485 priority patent/US20240130183A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • This kind of under-screen camera technology is mainly to set the camera in the display area of the display, and set the camera under the pixel unit. By reducing the pixel density of the area where the camera is located, it is compatible with the display function of the display panel and the camera's camera. Function.
  • the purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display panel including a first pixel area and a second pixel area, the pixel density of the second pixel area is lower than the pixel density of the first pixel area; the second pixel area It includes a plurality of pixel units distributed in an array, and the plurality of pixel units form a plurality of rows of pixel unit rows, and each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes A plurality of sub-pixels arranged in a direction, in the same row of pixel units, the closest two sub-pixels in two adjacent pixel units form a sub-pixel group; the sub-pixels include: a sub-pixel drive circuit, and the sub-pixel The first signal line pattern to the fifth signal line pattern coupled to the pixel driving circuit;
  • the display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel group one-to-one, the conductive connection structure is located between two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structure includes: The first conductive connection layer, the second conductive connection layer and the third conductive connection layer arranged in layers;
  • the first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the corresponding A first signal line pattern included in each sub-pixel in the sub-pixel group, and the second conductive connection portion is respectively coupled to a second signal line pattern included in each sub-pixel in the corresponding sub-pixel group;
  • the second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between the adjacent third conductive connection portion and the fourth conductive connection portion;
  • the three conductive connection portions are respectively coupled to the third signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and the at least one fourth conductive connection portion is connected to the first signal line pattern included in each sub-pixel in the corresponding sub-pixel group.
  • the four signal line patterns are in one-to-one correspondence, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns;
  • the third conductive connection layer is respectively coupled to a fifth signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and the fifth signal line pattern is used to transmit a fifth signal with a fixed potential.
  • the orthographic projection of the three conductive connection layers on the substrate of the display panel covering at least part of the orthographic projection of the first gap on the substrate and at least part of the orthographic projection of the second gap on the substrate .
  • the first signal line pattern includes a first reset signal line pattern, and at least a part of the first reset signal line pattern extends along the first direction;
  • the second signal line pattern includes a light emission control signal line A pattern, at least a part of the light-emitting control signal line pattern extends along the first direction.
  • the third signal line pattern includes a gate line pattern and a second reset signal line pattern arranged in a second direction, and at least part of the gate line pattern and at least part of the second reset signal line pattern are both Extending along the first direction, the gate line pattern and the second reset signal line pattern are used to transmit the same third signal;
  • the third conductive connection portion includes a first portion, a second portion, and a third portion.
  • the first portion and the second portion extend along the second direction, the third portion extends along the first direction, and the second portion extends along the first direction.
  • the fourth signal line pattern includes two initialization signal line patterns arranged along a second direction, the second direction intersects the first direction, and the second conductive connection layer includes two fourth signal line patterns.
  • Conductive connection portion, the two fourth conductive connection portions are in one-to-one correspondence with the initialization signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and each fourth conductive connection portion corresponds to the The fourth signal line patterns are respectively coupled;
  • At least part of the orthographic projection of the third conductive connecting portion on the substrate is located between the orthographic projections of the two fourth conductive connecting portions on the substrate.
  • the sub-pixel driving circuit includes a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate that are arranged oppositely, and the first electrode plate is located between the substrate and the second electrode plate. between;
  • the fifth signal line pattern includes a power signal line pattern, at least part of the power signal line pattern extends in a second direction, and the second plate is coupled to the power signal line pattern in the same sub-pixel;
  • the third conductive connection layer is respectively coupled to the second electrode plate included in each sub-pixel in the corresponding sub-pixel group.
  • the orthographic projection of the first conductive connection portion on the substrate is respectively aligned with the orthographic projection of the third conductive connection portion on the substrate, and an orthographic projection of the two fourth conductive connection portions An orthographic projection on the substrate overlaps; and/or,
  • the orthographic projection of the second conductive connecting portion on the substrate is respectively aligned with the orthographic projection of the third conductive connecting portion on the substrate, and the other of the two fourth conductive connecting portions is located on the substrate.
  • the orthographic projections on the base overlap.
  • the first conductive connection portion, the second conductive connection portion, and the fourth conductive connection portion all include a first side portion and a second side portion, and are located at the first side portion and the second side portion.
  • An orthographic projection of a middle portion included in one of the two fourth conductive connection portions on the substrate, an orthographic projection of a middle portion included in the first conductive connection portion on the substrate, and the third conductive connection portion The orthographic projection of the third part of the connecting portion on the substrate, the orthographic projection of the middle portion of the second conductive connecting portion on the substrate, and the other of the two fourth conductive connecting portions.
  • the orthographic projection of the middle portion of the slab on the substrate is arranged in sequence along the second direction.
  • the sub-pixel driving circuit includes a storage capacitor
  • the storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other in a direction perpendicular to the substrate, and the first electrode plate is located at the Between the base and the second plate;
  • the fourth signal line pattern includes a power signal line pattern, at least part of the power signal line pattern extends in a second direction, and the second plate is coupled to the power signal line pattern;
  • the second conductive connection layer includes a fourth conductive connection portion, and the fourth conductive connection portion is respectively coupled to the second electrode plate included in each sub-pixel in the corresponding sub-pixel group.
  • the fifth signal line pattern includes two initialization signal line patterns arranged along the second direction, and the third conductive connection layer is respectively coupled to the corresponding sub-pixels in the sub-pixel group.
  • the initialization signal line pattern is not limited to two initialization signal line patterns arranged along the second direction, and the third conductive connection layer is respectively coupled to the corresponding sub-pixels in the sub-pixel group.
  • the orthographic projection of the fourth conductive connection portion on the substrate, the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate overlaps the orthographic projection of the second conductive connection portion on the substrate.
  • the orthographic projection of the fourth conductive connection portion on the substrate is respectively the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second conductive connection portion on the substrate The orthographic projections overlap.
  • the orthographic projection of the fourth conductive connection portion on the substrate overlaps the orthographic projection of the first conductive connection portion on the substrate; the third conductive connection portion is on the substrate The orthographic projection of the upper portion overlaps the orthographic projection of the second conductive connection portion on the substrate.
  • the first conductive connection portion, the second conductive connection portion, and the fourth conductive connection portion all include a first side portion and a second side portion, and are located at the first side portion and the second side portion.
  • the first gap is the minimum width that satisfies the insulation condition of the middle part of the first conductive connection part and the middle part of the second conductive connection part;
  • the second gap is the minimum width that satisfies the insulation condition of the middle part of the third conductive connection part and the middle part of the fourth conductive connection part.
  • the orthographic projection of the third conductive connecting layer on the substrate and the orthographic projection of the first conductive connecting portion on the substrate, and the orthographic projection of the second conductive connecting portion on the substrate overlap.
  • the first conductive connection portion, the second conductive connection portion, and the fourth conductive connection portion all include a first side portion and a second side portion, and are located at the first side portion and the second side portion.
  • the orthographic projection of the intermediate portion of the fourth conductive connecting portion on the substrate, the orthographic projection of the intermediate portion of the first conductive connecting portion on the substrate, and the third of the third conductive connecting portion Part of the orthographic projection on the substrate, and the orthographic projection of the intermediate portion included in the second conductive connection portion on the substrate are all located inside the orthographic projection of the third conductive connection layer on the substrate.
  • the sub-pixel further includes a data line pattern extending in a second direction;
  • the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, the storage capacitor including first poles arranged oppositely Plate and second plate;
  • the first conductive connection layer and the gate electrode of the transistor structure are arranged in the same layer and the same material;
  • the second conductive connection layer and the data line pattern are provided in the same layer and the same material;
  • the third conductive connection layer and the second electrode plate are provided with the same layer and the same material.
  • the sub-pixel further includes a data line pattern extending in a second direction;
  • the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, the storage capacitor including first poles arranged oppositely Plate and second plate;
  • the first conductive connection layer and the second electrode plate are arranged in the same layer and the same material;
  • the second conductive connection layer and the data line pattern are provided in the same layer and the same material;
  • the third conductive connection layer and the gate electrode of the transistor structure are arranged in the same layer and the same material.
  • the first signal line pattern includes a first reset signal line pattern
  • the second signal line pattern includes a light emission control signal line pattern
  • the third signal line pattern includes a gate line pattern and a second reset signal line Graphics
  • the sub-pixels also include power signal line graphics, data line graphics, first initialization signal line graphics and second initialization signal line graphics
  • the sub-pixel driving circuits all include: a storage capacitor, a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to The first pole of the first transistor is coupled;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the first reset signal line pattern, the first electrode of the second transistor is coupled to the first initialization signal line pattern, and the second electrode of the second transistor is coupled to the first reset signal line pattern. Coupled to the gate of the driving transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The corresponding light-emitting element in the display panel is coupled;
  • the second electrode of the seventh transistor is coupled to the corresponding light emitting element, the gate of the seventh transistor is coupled to the second reset signal line pattern, and the first electrode of the seventh transistor is coupled to the corresponding light emitting element.
  • the second initialization signal line pattern is coupled.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display panel.
  • a third aspect of the present disclosure provides a method for manufacturing a display panel.
  • the display panel includes a first pixel area and a second pixel area.
  • the pixel density of the second pixel area is lower than that of the second pixel area.
  • the pixel density of the first pixel area; the manufacturing method includes:
  • the plurality of pixel units form a plurality of rows of pixel unit rows, each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes a plurality of sub-pixels arranged along the first direction, in the same In a row of pixel units, the two closest sub-pixels among two adjacent pixel units form a sub-pixel group; the sub-pixels include: a sub-pixel drive circuit, and a first signal coupled to the sub-pixel drive circuit, respectively Line pattern to the fifth signal line pattern;
  • the plurality of conductive connection structures correspond to the sub-pixel groups one-to-one, the conductive connection structure is located between two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structure includes: first conductive connections arranged in different layers A connection layer, a second conductive connection layer and a third conductive connection layer;
  • the first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the corresponding A first signal line pattern included in each sub-pixel in the sub-pixel group, and the second conductive connection portion is respectively coupled to a second signal line pattern included in each sub-pixel in the corresponding sub-pixel group;
  • the second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between the adjacent third conductive connection portion and the fourth conductive connection portion;
  • the three conductive connection portions are respectively coupled to the third signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and the at least one fourth conductive connection portion is connected to the first signal line pattern included in each sub-pixel in the corresponding sub-pixel group.
  • the four signal line patterns are in one-to-one correspondence, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns;
  • the third conductive connection layer is respectively coupled to a fifth signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and the fifth signal line pattern is used to transmit a fifth signal with a fixed potential.
  • the orthographic projection of the three conductive connection layers on the substrate of the display panel covering at least part of the orthographic projection of the first gap on the substrate and at least part of the orthographic projection of the second gap on the substrate .
  • FIG. 1 is a schematic diagram of a first layout of a sub-pixel group provided by an embodiment of the disclosure
  • FIG. 2 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a timing diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of a second layout of a sub-pixel group provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of the layout of the active layer in FIG. 4;
  • FIG. 6 is a schematic diagram of the layout of the first gate metal layer in FIG. 4;
  • FIG. 7 is a schematic diagram of the layout of the second gate metal layer in FIG. 4;
  • FIG. 8 is a first schematic diagram of the first source and drain metal layer in FIG. 4;
  • FIG. 9 is a second schematic diagram of the first source and drain metal layer in FIG. 4;
  • FIG. 10 is a schematic diagram of a third layout of a sub-pixel group provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the layout of the second gate metal layer in FIG. 10;
  • FIG. 12 is a schematic diagram of the layout of the first source and drain metal layer in FIG. 10.
  • the present disclosure provides a display panel including a first pixel area and a second pixel area, the pixel density of the second pixel area is lower than the pixel density of the first pixel area;
  • the second pixel area includes a plurality of pixel units distributed in an array, the plurality of pixel units form a plurality of rows of pixel units, and each row of pixel units includes a plurality of pixel units arranged along a first direction; each pixel Each unit includes a plurality of sub-pixels arranged along a first direction.
  • the closest two sub-pixels in two adjacent pixel units form a sub-pixel group;
  • the sub-pixels include: a sub-pixel drive circuit ,
  • the signal line patterns respectively coupled to the sub-pixel driving circuit may specifically include: power signal line patterns 901, data line patterns 908, gate line patterns 902, light emission control signal line patterns 903, and A reset signal line pattern 905, a first initialization signal line pattern 904, a second reset signal line pattern 905', and a second initialization signal line pattern 904'.
  • the pixel density indicates the number of pixels per inch.
  • the first pixel area is also provided with a plurality of pixel units distributed in an array, and the specific structure of the sub-pixels included in each pixel unit is the same as that of the second pixel area. Since an under-screen camera is provided in the second pixel area, the pixel density in the second pixel area is low, and the pixel units in the first pixel area and the pixels in the second pixel area are laid out. The layout of the pixel unit in the first pixel area is compact, and the layout of the pixel unit in the second pixel area is loose. In the second pixel area, in the same row of pixel units, the distance between two adjacent pixel units is relatively large, and conductive connection structures need to be arranged between the sub-pixel groups to realize the connection of the sub-pixel groups. The same signal line patterns included in each sub-pixel in the pixel group are coupled together.
  • the conductive connection structure between the two sub-pixels includes seven conductive connection portions, and the seven conductive connection portions are used to connect the first sub-pixel included in the sub-pixel group.
  • the initialization signal line pattern 904 is coupled to couple the first reset signal line pattern 905 included in each sub-pixel in the sub-pixel group, and is used to couple the gate line pattern 902 included in each sub-pixel in the sub-pixel group.
  • the second reset signal line pattern 905 ′ included in each sub-pixel is coupled to couple the power signal line pattern 901 included in each sub-pixel in the sub-image group.
  • the display panel provided by the above embodiment is compatible with the display function of the display panel and the camera function of the camera by reducing the pixel density of the second pixel area where the camera is located, there is a gap between the adjacent conductive connecting parts, through which the gap penetrates The light will form diffraction and glare, which will affect the image quality of the camera when taking pictures.
  • a large layout space area is occupied, so that in the second pixel area, the transmittance of the screen is low, thereby affecting the imaging quality of the camera when taking pictures.
  • an embodiment of the present disclosure provides a display panel, including a first pixel area and a second pixel area, the pixel density of the second pixel area is lower than the pixel density of the first pixel area
  • the second pixel area includes a plurality of pixel units distributed in an array, the plurality of pixel units form a plurality of rows of pixel unit rows, and each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each Each pixel unit includes a plurality of sub-pixels arranged along a first direction.
  • the closest two sub-pixels in two adjacent pixel units form a sub-pixel group;
  • the sub-pixels include: sub-pixel driving A circuit, and the first signal line pattern 81 to the fifth signal line pattern 85 respectively coupled with the sub-pixel driving circuit;
  • the display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel group one-to-one, the conductive connection structure is located between two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structure includes: The first conductive connection layer, the second conductive connection layer and the third conductive connection layer 75 are arranged in layers;
  • the first conductive connection layer includes a first conductive connection portion 71 and a second conductive connection portion 72, and there is a first gap between the first conductive connection portion 71 and the second conductive connection portion 72; the first conductive connection portion 71
  • the first signal line pattern 81 included in each sub-pixel in the corresponding sub-pixel group is respectively coupled, and the second conductive connection portion 72 is respectively coupled to the second signal included in each sub-pixel in the corresponding sub-pixel group Line pattern 82;
  • the second conductive connection layer includes a third conductive connection portion 73 and at least one fourth conductive connection portion 74, and there is a second gap between the adjacent third conductive connection portion 73 and the fourth conductive connection portion 74
  • the third conductive connection portion 73 is respectively coupled to the third signal line pattern 83 included in each sub-pixel in the corresponding sub-pixel group, the at least one fourth conductive connection portion 74 and the corresponding sub-pixel group
  • the fourth signal line patterns 84 included in each sub-pixel are in a one-to-one correspondence, and the fourth conductive connecting portions 74 are respectively coupled to the corresponding fourth signal line patterns 84;
  • the third conductive connection layer 75 is respectively coupled to a fifth signal line pattern 85 included in each sub-pixel in the corresponding sub-pixel group, and the fifth signal line pattern 85 is used to transmit a fifth signal with a fixed potential,
  • the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel covers at least part of the orthographic projection of the first gap on the substrate and the orthographic projection of the second gap on the substrate. At least part of the projection.
  • the display panel includes a first pixel area and a second pixel area, and both the first pixel area and the second pixel area can realize a display function.
  • the pixel density of the second pixel area is lower than that of the first pixel area.
  • a camera is arranged between the substrate and the sub-pixel driving circuit.
  • the specific layout modes of the pixel units in the first pixel area and the second pixel area are various.
  • the pixel units in the first pixel area and the pixel units in the second pixel area are both Distributed in an array.
  • the signal line pattern located in the first pixel area is electrically connected to the signal line pattern located in the second pixel area for transmitting the same signal. connect.
  • a plurality of pixel units distributed in an array can form a plurality of rows of pixel unit rows sequentially arranged along the second direction, and each row of pixel unit rows includes a plurality of pixel units sequentially arranged along the first direction .
  • the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • each pixel unit includes a plurality of sub-pixels arranged in a first direction.
  • each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel arranged in the first direction.
  • a plurality of sub-pixels included in each pixel unit are compactly arranged, and the signal line patterns included in each sub-pixel for transmitting the same signal in a pixel unit are directly coupled.
  • each sub-pixel in a pixel unit includes The signal line pattern used to transmit the same signal can be formed into a single structure.
  • each pixel unit includes first sub-pixels
  • the second sub-pixel and the third sub-pixel, the sub-pixels include two adjacent pixel units, the third sub-pixel of the previous pixel unit and the first sub-pixel of the next pixel unit.
  • each sub-pixel included in the pixel unit in the first pixel area and the second pixel area is the same, each sub-pixel includes a sub-pixel drive circuit, and the sub-pixel drive circuit is respectively coupled to Multiple signal line graphics.
  • the multiple signal line patterns include a first signal line pattern 81, a second signal line pattern 82, a third signal line pattern 83, a fourth signal line pattern 84, and a fifth signal line pattern 85; each signal Line patterns are used to transmit corresponding signals.
  • the pixel units located in the same row have a compact layout.
  • the second pixel area, along the first direction there is a certain interval between adjacent pixel units in the same row, and the interval is located between two sub-pixels in the sub-pixel group for transmitting light to The camera located in the second pixel area can realize the camera function.
  • the pixel density or pixel size of the second pixel area should be reduced as much as possible (the existing manufacturing process needs to be met), and the area of the conductive connection between the sub-pixels should be reduced, thereby Better improve the light transmittance of the second pixel area.
  • the display panel further includes: a plurality of conductive connection structures corresponding to the sub-pixel groups one-to-one, each of the conductive connection structures is located between two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structure
  • the conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer 75; a first conductive connection layer, a second conductive connection layer, and a third conductive connection layer.
  • any two layers are arranged in different layers.
  • first conductive connection layer the second conductive connection layer and the third conductive connection layer 75 are various, which will be exemplified below.
  • the first conductive connection layer includes a first conductive connection portion 71 and a second conductive connection portion 72. At least a portion of the first conductive connection portion 71 extends along a first direction, and at least a portion of the second conductive connection portion 72 Extending in the first direction, there is a first gap between the first conductive connection portion 71 and the second conductive connection portion 72.
  • the first conductive connection portion 71 is respectively coupled to the first signal line pattern 81 included in each sub-pixel in the corresponding sub-pixel group.
  • the first conductive connection portion 71 is coupled to the first signal
  • the line pattern 81 is formed as an integral structure.
  • the second conductive connection portion 72 is respectively coupled to the second signal line pattern 82 included in each sub-pixel in the corresponding sub-pixel group.
  • the second conductive connection portion 72 is coupled to the second signal The line pattern 82 is formed as an integral structure.
  • the second conductive connection layer includes a third conductive connection portion 73 and at least one fourth conductive connection portion 74. At least part of the third conductive connection portion 73 extends along the first direction. At least partly extending along the first direction, there is a second gap between the adjacent third conductive connection portion 73 and the fourth conductive connection portion 74.
  • the third conductive connection portion 73 is respectively coupled to the third signal line pattern 83 included in each sub-pixel in the corresponding sub-pixel group.
  • the third conductive connection portion 73 is located on the substrate. Projection, the orthographic projection of the third signal line pattern 83 coupled therewith on the substrate forms an overlapping area where the third conductive connection portion 73 is connected to the third signal line pattern through a via hole 83 Coupled.
  • the first gap and the second gap are generally small-sized gaps, and the first gap and the second gap may be set to satisfy the minimum gap under the condition that the two conductive connection parts are insulated from each other.
  • the at least one fourth conductive connection portion 74 corresponds to the fourth signal line pattern 84 included in each sub-pixel in the corresponding sub-pixel group uniformly, and the fourth conductive connection portion 74 corresponds to the corresponding fourth signal line pattern 84 respectively.
  • the line pattern 84 is coupled; for example, as shown in FIG. 4, the orthographic projection of the fourth conductive connecting portion 74 on the substrate, and the fourth signal line pattern 84 coupled with it on the substrate is positive
  • the projection forms an overlapping area where the fourth conductive connection portion 74 is coupled to the fourth signal line pattern 84 through a via hole.
  • the third conductive connection layer 75 is respectively coupled to a fifth signal line pattern 85 included in each sub-pixel in the corresponding sub-pixel group, and the fifth signal line pattern 85 is used to transmit a fifth signal with a fixed potential.
  • the third conductive connection layer 75 and the fifth signal line pattern 85 to which it is coupled are formed as an integral structure.
  • the fifth signal line pattern 85 is coupled to the target pattern in the display panel, and the orthographic projection of the third conductive connection layer 75 on the substrate is the same as the orthographic projection of the target pattern on the substrate. Projection forms an overlapping area. In the overlapping area, the third conductive connection layer 75 is coupled to the target pattern through a via hole, so that the third conductive connection layer 75 is connected to the first pattern through the target pattern.
  • the five-signal line pattern 85 is coupled.
  • At least part of the third conductive connection layer 75 extends along the first direction.
  • the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel covers at least part of the first gap.
  • the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel completely covers at least part of the orthographic projection of the first gap on the substrate and the second gap in the At least part of the orthographic projection on the substrate.
  • a conductive connection structure is provided between two sub-pixels included in the sub-pixel group, and the conductive connection structure includes: The connection layer, the second conductive connection layer and the third conductive connection layer 75; the first conductive connection layer and the second conductive connection layer are used to transmit the same signal signal included in each sub-pixel in the sub-pixel group
  • the line patterns are coupled together; the third conductive connection layer 75 is used to couple together the fifth signal line pattern 85 included in each sub-pixel in the sub-pixel group for transmitting the fifth signal with a fixed potential; therefore,
  • the signal line patterns included in each sub-pixel in the sub-pixel group for transmitting the same signal are correspondingly coupled together.
  • the display panel provided by the embodiment of the present disclosure, by providing the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel, at least the orthographic projection of the first gap on the substrate is covered. Part and at least part of the orthographic projection of the second gap on the substrate, so that the third conductive connection layer 75 can cover the sub-pixel group between the adjacent conductive connection parts between the two sub-pixels.
  • the gap reduces the light leakage phenomenon generated at the gap, thereby avoiding the interference diffraction and glare caused by the light passing through the gap, and better guarantees the imaging quality of the camera in the display panel when taking pictures.
  • the third conductive connection layer 75 is coupled to the fifth signal line pattern 85 for transmitting the fifth signal with a fixed potential, so that the third conductive connection layer 75 has a stable electric potential, and will not greatly affect the RC (resistance-capacitance) loading of the fifth signal line pattern 85.
  • the first signal line pattern 81 includes a first reset signal line pattern 905, and at least part of the first reset signal line pattern 905 is along the first direction Extension;
  • the second signal line pattern 82 includes a light-emitting control signal line pattern 903, at least part of the light-emitting control signal line pattern 903 extends along the first direction.
  • the first conductive connection portion 71 is respectively coupled to the first reset signal line pattern 905 included in each sub-pixel in the corresponding sub-pixel group.
  • the first conductive connection portion 71 and each of the first reset signal line patterns 905 coupled to it are formed as an integral structure.
  • the second conductive connection portion 72 is respectively coupled to the light emission control signal line pattern 903 included in each sub-pixel in the corresponding sub-pixel group.
  • the second conductive connection portion 72 and each of the light-emitting control signal line patterns 903 coupled to it are formed as an integral structure.
  • the first reset signal line pattern 905 and the light emission control signal line pattern 903 are arranged along a second direction, and the second direction intersects the first direction.
  • the first signal line pattern 81 includes a first reset signal line pattern 905, and each of the first reset signal line patterns 905 to which the first conductive connection portion 71 is coupled Formed as an integral structure, so that the first conductive connection portion 71 and the first reset signal line pattern 905 can be simultaneously formed in the same patterning process, and the formed first conductive connection portion 71 and the first A reset signal line pattern 905 can be directly coupled.
  • the second signal line pattern 82 to include a light-emitting control signal line pattern 903
  • the second conductive connecting portion 72 and each of the light-emitting control signal line patterns 903 coupled to it are formed into an integrated structure, so that the The second conductive connection portion 72 and the light emission control signal line pattern 903 can be formed at the same time in the same patterning process, and the formed second conductive connection portion 72 and the light emission control signal line pattern 903 can be directly coupled . Therefore, the display panel provided by the above embodiment effectively simplifies the manufacturing process and saves the manufacturing cost.
  • the third signal line pattern 83 includes a gate line pattern 902 and a second reset signal line pattern 905' arranged in a second direction, At least part of the gate line pattern 902 and at least part of the second reset signal line pattern 905' extend along the first direction, and the gate line pattern 902 and the second reset signal line pattern 905' are used for transmission The same third signal;
  • the third conductive connecting portion 73 includes a first portion 731, a second portion 732, and a third portion 733.
  • the first portion 731 and the second portion 732 extend along the second direction, and the third portion 733 extends along the first portion.
  • Direction extending, the second direction intersects the first direction;
  • the first portion 731 is respectively coupled to the gate line pattern 902 and the second reset signal line pattern included in one sub-pixel in the sub-pixel group 905'
  • the second part 732 is respectively coupled to the gate line pattern 902 and the second reset signal line pattern 905' included in another sub-pixel in the sub-pixel group
  • the third part 733 is respectively connected to the gate line pattern 902 and the second reset signal line pattern 905'
  • the first part 731 and the second part 732 are coupled.
  • the third signal line pattern 83 includes a gate line pattern 902 and a second reset signal line pattern 905' arranged in a second direction.
  • the gate line pattern 902 and the second reset signal line pattern 905' The reset signal line pattern 905' is used to transmit the same third signal.
  • the third conductive connection portion 73 includes the first portion 731, the second portion 732, and the third portion 733.
  • the first part 731 and the second part 732 extend in the second direction
  • the third part 733 extends in the first direction.
  • the first part 731, the second part 732, and the third part 733 are formed as an integral structure.
  • the first part 731 is used to respectively couple the gate line pattern 902 and the second reset signal line pattern 905' included in the first sub-pixel in the sub-pixel group.
  • the first part 731 is The orthographic projection on the substrate forms an overlap area with the orthographic projection of the grid line pattern 902 on the substrate and the orthographic projection of the second reset signal line pattern 905' on the substrate, respectively, and the first part 731 can be separately coupled to the gate line pattern 902 and the second reset signal line pattern 905' through the via holes formed in the overlapping area.
  • the second part 732 is used to respectively couple the gate line pattern 902 and the second reset signal line pattern 905' included in the second sub-pixel in the sub-pixel group.
  • the second part The orthographic projection of 732 on the substrate forms an overlap area with the orthographic projection of the grid line pattern 902 on the substrate and the orthographic projection of the second reset signal line pattern 905' on the substrate, respectively.
  • the second portion 732 can be separately coupled to the gate line pattern 902 and the second reset signal line pattern 905' through the via hole formed in the overlap area.
  • the third conductive connection portion 73 is provided to remove the gate line pattern 902 and the second reset signal line included in each sub-pixel group for transmitting the same third signal in the corresponding sub-pixel group.
  • the patterns 905' are coupled together, which effectively reduces the layout space occupied by the conductive connection structure, thereby better improving the light transmittance of the second pixel area.
  • the first portion 731, the second portion 732, and the third portion 733 are formed into an integrated structure, so that the third conductive connection portion 73 can be patterned at one time. It is formed in the process, thereby effectively simplifying the manufacturing process of the display panel and saving the manufacturing cost.
  • the fourth signal line pattern 84 includes two initialization signal line patterns arranged along a second direction.
  • the second conductive connection layer includes two fourth conductive connection portions 74, and the two fourth conductive connection portions 74 correspond to the initialization signal line pattern included in each sub-pixel in the corresponding sub-pixel group
  • each of the fourth conductive connecting portions 74 is respectively coupled to the corresponding fourth signal line pattern 84;
  • the orthographic projection of at least part of the third conductive connecting portion 73 on the substrate is located between the orthographic projections of the two fourth conductive connecting portions 74 on the substrate.
  • the fourth signal line pattern 84 includes a first initialization signal line pattern 904 and a second initialization signal line pattern 904' arranged along the second direction, at least a part of the first initialization signal line pattern 904 and the second initialization signal At least part of the line pattern 904' extends along the first direction.
  • the second conductive connection layer includes two fourth conductive connection portions 74, of which one fourth conductive connection portion 74 is respectively coupled to the first initialization signal line pattern 904 included in each sub-pixel in the corresponding sub-pixel group;
  • the fourth conductive connection portion 74 is respectively coupled to the second initialization signal line pattern 904' included in each sub-pixel in the corresponding sub-pixel group.
  • the layout modes between the third conductive connection portion 73 and the two fourth conductive connection portions 74 are various, exemplary .
  • the orthographic projection of at least part of the third conductive connecting portion 73 on the substrate is provided between the orthographic projections of the two fourth conductive connecting portions 74 on the substrate.
  • the orthographic projection of the third portion 733 of the third conductive connecting portion 73 on the substrate is located between the orthographic projections of the two fourth conductive connecting portions 74 on the substrate.
  • the first initialization signal line pattern 904, the gate line pattern 902, the second initialization signal line pattern 904', and the second reset signal line pattern 905' included in each sub-pixel are sequentially arranged along the second direction.
  • the above-mentioned arrangement of the orthographic projection of the third conductive connection portion 73 on the substrate is located between the orthographic projections of the two fourth conductive connection portions 74 on the substrate, so that the third conductive connection is ensured In the case of insulation between the portion 73 and the fourth conductive connection portion 74, it is more beneficial to reduce the difficulty of layout of the third conductive connection portion 73 and the two fourth conductive connection portions 74.
  • the sub-pixel drive circuit includes a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely, and the first The electrode plate is located between the substrate and the second electrode plate; the fifth signal line pattern 85 includes a power signal line pattern 901, and at least a part of the power signal line pattern 901 extends along the second direction and is in the same sub- The second electrode plate in the pixel is coupled to the power signal line pattern 901; the third conductive connection layer 75 is respectively coupled to the second electrode plate included in each sub-pixel in the corresponding sub-pixel group.
  • the sub-pixel driving circuit includes a driving transistor and a storage capacitor
  • the storage capacitor includes a first electrode plate and a second electrode plate disposed oppositely, and the first electrode plate is located between the substrate and the second electrode. Between the plates, for example, the first plate is multiplexed as the gate of the driving transistor.
  • the first electrode plate is made of a first gate metal layer in the display panel
  • the second electrode plate is made of a second gate metal layer in the display panel.
  • the fifth signal line pattern 85 includes a power signal line pattern 901. At least part of the power signal line pattern 901 extends along the second direction. The projection and the orthographic projection of the power signal line pattern 901 on the substrate form an overlapping area. In the overlapping area, the power signal line pattern 901 is coupled to the second plate through a via hole.
  • the power signal line pattern 901 may be made of the first source and drain metal layer in the display panel.
  • the power signal line patterns 901 located in the same column of sub-pixels along the second direction are sequentially coupled to form an integrated structure.
  • the third conductive connection layer 75 may be made of the second gate metal layer in the display panel, that is, the third conductive connection layer 75 and the second electrode plate are made of the same layer and the same material. In this way, the third conductive connection layer 75 can be formed in the same patterning process as the second electrode plate, and can be directly coupled, which greatly simplifies the manufacturing process of the display panel and reduces the manufacturing cost.
  • the power signal line pattern 901 is coupled to the second electrode plate, and the third conductive connection layer 75 is respectively coupled to each sub-pixel group in the corresponding sub-pixel group.
  • the second plate included in the pixel realizes that the third conductive connection layer 75 is coupled to the power signal line pattern 901 included in each sub-pixel in the corresponding sub-pixel group, so that the third conductive connection layer 75 has the same stable potential as the power signal line pattern 901, so when the large-area third conductive connection layer 75 is used to block the gap between adjacent conductive connections, the stability of the display panel can be better ensured. sex.
  • the orthographic projection of the first conductive connecting portion 71 on the substrate is respectively aligned with the orthographic projection of the third conductive connecting portion 73 on the substrate, and the two fourth conductive
  • the orthographic projection of one of the connecting portions 74 on the substrate overlaps; and/or, the orthographic projection of the second conductive connecting portion 72 on the substrate is at the same position as the third conductive connecting portion 73.
  • the orthographic projection on the substrate and the orthographic projection of the other of the two fourth conductive connecting portions 74 on the substrate overlap.
  • the first conductive connection portion 71 and the second conductive connection portion 72 are both arranged in different layers from the third conductive connection portion 73 and the fourth conductive connection portion 74, even if it is perpendicular to In the direction of the substrate, the first conductive connection portion 71 overlaps the third conductive connection portion 73 and the fourth conductive connection portion 74, and the first conductive connection portion 71 will not be connected to the third conductive connection.
  • the portion 73 and the fourth conductive connecting portion 74 are short-circuited.
  • the second conductive connection portion 72 overlaps the third conductive connection portion 73 and the fourth conductive connection portion 74, the second conductive connection portion 72 will not A short circuit occurs with the third conductive connection portion 73 and the fourth conductive connection portion 74.
  • the orthographic projection of the other one of the 74 overlaps on the substrate, which can effectively reduce the overall layout space occupied by the second conductive connection portion 72, the third conductive connection portion 73 and the fourth conductive connection portion 74 . Therefore, the above arrangement can minimize the layout space occupied by the conductive connection structure, and effectively improve the light transmittance of the display panel in the second pixel area.
  • the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 each include a first side portion and a second side portion, And an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends in a first direction, and the first side portion includes a portion extending in the first direction and an intermediate portion extending in the second direction.
  • the second side part includes a part extending in a first direction and a part extending in a second direction;
  • an orthographic projection of a middle part 743 included in one of the two fourth conductive connecting parts 74 on the substrate, and the middle part included in the first conductive connecting part 71 is in the The orthographic projection on the substrate, the orthographic projection of the third portion 733 of the third conductive connecting portion 73 on the substrate, the orthographic projection of the middle portion of the second conductive connecting portion 72 on the substrate, And the orthographic projection of the middle portion included in the other of the two fourth conductive connecting portions 74 on the substrate is sequentially arranged along the second direction.
  • first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 are various.
  • the first conductive connection portion 71, the The second conductive connection portion 72 and the fourth conductive connection portion 74 each include a first side portion and a second side portion, and an intermediate portion located between the first side portion and the second side portion.
  • the middle portion 713 of the first conductive connection portion 71, the middle portion 723 of the second conductive connection portion 72, and the middle portion 743 of the fourth conductive connection portion 74 all extend along the first direction.
  • the first side portion 711 and the second side portion 712 of the first conductive connecting portion 71 each include a portion extending in the first direction and a portion extending in the second direction; the first conductive connecting portion 72
  • the side portion 721 and the second side portion 722 each include a portion extending in the first direction and a portion extending in the second direction; one of the two fourth conductive connecting portions 74 (marked 741 in FIG.
  • the first side portion 744 and the second side portion 745 each include a portion extending in the first direction and a portion extending in the second direction; the other of the two fourth conductive connecting portions 74 (as shown in FIG. 9
  • the first side portion 744 and the second side portion 745 included in the mark 742) each include a portion extending in the second direction.
  • an orthographic projection of a middle portion included in one of the two fourth conductive connecting portions 74 on the substrate, and an orthographic projection of a middle portion included in the first conductive connecting portion 71 on the substrate The orthographic projection of the third portion 733 of the third conductive connecting portion 73 on the substrate, the orthographic projection of the middle portion of the second conductive connecting portion 72 on the substrate, and the two second The orthographic projection of the middle part included in the other of the four conductive connecting parts 74 on the substrate is compactly close together, so as to reduce the layout space occupied by the conductive connecting structure.
  • the first conductive connecting portion 71, the second conductive connecting portion 72, and the fourth conductive connecting portion 74 including a first side portion and a second side portion, all extend in a direction away from the middle portion.
  • the orthographic projection of the intermediate portion included in one of the two fourth conductive connecting portions 74 on the substrate is provided, and the orthographic projection of the intermediate portion included in the first conductive connecting portion 71 on the substrate is provided, so
  • the other of the connecting parts 74 includes an orthographic projection of the middle part on the substrate, compactly close together, and arranged in sequence along the second direction, which can effectively reduce the conductive connection while meeting the connection requirements.
  • the sub-pixel driving circuit includes a storage capacitor, and the storage capacitor includes a first electrode plate and a first electrode plate and a second electrode plate arranged opposite to each other in a direction perpendicular to the substrate.
  • a two-electrode plate, the first electrode plate is located between the base and the second electrode plate;
  • the fourth signal line pattern 84 includes a power signal line pattern 901, at least part of the power signal line pattern 901 extends in a second direction, and the second plate is coupled to the power signal line pattern 901;
  • the second conductive connection layer includes a fourth conductive connection portion 74, and the fourth conductive connection portion 74 is respectively coupled to the second electrode plate included in each sub-pixel in the corresponding sub-pixel group.
  • the sub-pixel driving circuit includes a driving transistor and a storage capacitor
  • the storage capacitor includes a first electrode plate and a second electrode plate disposed oppositely, and the first electrode plate is located between the substrate and the second electrode. Between the plates, for example, the first plate is multiplexed as the gate of the driving transistor.
  • the first electrode plate is made of a first gate metal layer in the display panel
  • the second electrode plate is made of a second gate metal layer in the display panel.
  • the fourth signal line pattern 84 includes a power signal line pattern 901. At least part of the power signal line pattern 901 extends along the second direction. The projection and the orthographic projection of the power signal line pattern 901 on the substrate form an overlapping area. In the overlapping area, the power signal line pattern 901 is coupled to the second plate through a via hole.
  • the power signal line pattern 901 may be made of the first source and drain metal layer in the display panel.
  • the power signal line patterns 901 located in the same column of sub-pixels along the second direction are sequentially coupled to form an integrated structure.
  • the second conductive connection layer may include a fourth conductive connection portion 74.
  • the fourth conductive connection portion 74 is made of a first source/drain metal layer in the display panel.
  • the orthographic projection of the fourth conductive connecting portion 74 on the substrate and the corresponding orthographic projection of the second electrode plate on the substrate have an overlapping area, and the fourth conductive connecting portion 74 is disposed on the The via hole in the overlapping area is coupled to the corresponding second electrode plate.
  • the second electrode plate is provided to be coupled to the power signal line pattern 901, and the fourth conductive connection portion 74 is respectively coupled to each sub-pixel group in the corresponding sub-pixel group.
  • the second electrode plate included in the pixel realizes that the fourth conductive connecting portion 74 is coupled to the power signal line pattern 901 included in each sub-pixel in the corresponding sub-pixel group.
  • the fifth signal line pattern 85 includes two initialization signal line patterns arranged along the second direction, and the third conductive connection layer 75 is respectively coupled to The initialization signal line pattern included in each sub-pixel in the corresponding sub-pixel group.
  • the initialization signal line pattern extends along the first direction, and the initialization signal line pattern is used to transmit an initialization signal, and the initialization signal is a direct current signal with a stable potential.
  • the third conductive connection layer 75 and the initialization signal line pattern are formed as an integral structure. This arrangement enables the third conductive connection layer 75 and the initialization signal line pattern to be simultaneously formed in a sequential patterning process, and direct coupling can be achieved.
  • the third conductive connection layer 75 is respectively coupled to the initialization signal line pattern included in each sub-pixel in the corresponding sub-pixel group, so that the third conductive connection layer 75 can be coupled to the corresponding sub-pixels at the same time
  • the four initialization signal line patterns included in the group This arrangement makes the third conductive connection layer 75 have the same stable potential as the initialization signal line pattern.
  • the large-area third conductive connection layer 75 is used to block the gap between adjacent conductive connections, It can better ensure the stability of the display panel.
  • an orthographic projection of the fourth conductive connecting portion 74 on the substrate may be provided, and an orthographic projection of the first conductive connecting portion 71 on the substrate may be located at The second conductive connection portion 72 is between the orthographic projections on the substrate; the orthographic projection of the third conductive connection portion 73 on the substrate and the orthographic projection of the second conductive connection portion 72 on the substrate The projections overlap.
  • the line pattern 903 is between the orthographic projections on the substrate, and the orthographic projection of the fourth conductive connecting portion 74 on the substrate is set above, and the orthographic projection of the first conductive connecting portion 71 on the substrate is located
  • the orthographic projection of the second conductive connection portion 72 on the substrate which is more conducive to lowering the first conductive connection portion 71, the second conductive connection portion 72 and the fourth conductive connection portion 74 Difficulty of layout.
  • an orthographic projection of the fourth conductive connection portion 74 on the substrate may be provided, which is respectively connected to the orthographic projection of the first conductive connection portion 71 on the substrate and the second conductive connection.
  • the orthographic projections of the portion 72 on the substrate overlap.
  • the above-mentioned arrangement of the orthographic projection of the fourth conductive connecting portion 74 on the substrate is respectively corresponding to the orthographic projection of the first conductive connecting portion 71 on the substrate and the second conductive connecting portion 72 on the substrate.
  • the orthogonal projections on the upper part overlap, so that the layout space occupied by the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive portion is reduced, thereby better improving the display panel
  • the light transmittance of the second pixel area is respectively corresponding to the orthographic projection of the first conductive connecting portion 71 on the substrate and the second conductive connecting portion 72 on the substrate.
  • the orthographic projection of the fourth conductive connection portion 74 on the substrate overlaps with the orthographic projection of the first conductive connection portion 71 on the substrate; the third conductive connection portion The orthographic projection of 73 on the substrate overlaps the orthographic projection of the second conductive connection portion 72 on the substrate.
  • the layout space occupied by the fourth conductive portion is reduced, thereby better improving the light transmittance of the display panel in the second pixel area.
  • the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 all include a first side portion and a second side portion. Side portion, and a middle portion located between the first side portion and the second side portion; the middle portion extends along a first direction, and the first side portion includes a portion extending along the first direction and a portion extending along the second A portion extending in a direction, the second side portion includes a portion extending in a first direction and a portion extending in a second direction;
  • the first gap between the middle portion 713 of the first conductive connection portion 71 and the middle portion 723 of the second conductive connection portion 72, and the first gap is in a direction perpendicular to the first direction. Having a first width, the first width being the minimum width that satisfies the insulation condition of the middle portion 713 of the first conductive connection portion 71 and the middle portion 723 of the second conductive connection portion 72;
  • the second gap is the minimum width that satisfies the insulation condition of the middle portion of the third conductive connection portion 73 and the middle portion 743 of the fourth conductive connection portion 74.
  • the first conductive connection portion 71 and the second conductive connection portion 72 are provided on the same layer, and are correspondingly connected to signal line patterns for transmitting different signals, the first conductive connection portion 71 and The second conductive connection portions 72 need to be arranged at intervals to avoid a short circuit between the first conductive connection portion 71 and the second conductive connection portion 72.
  • the third conductive connection portion 73 and the fourth conductive connection portion 74 are provided on the same layer and are correspondingly connected to signal line patterns for transmitting different signals, the third conductive connection portion 73 and The fourth conductive connecting portions 74 need to be arranged at intervals to avoid a short circuit between the third conductive connecting portion 73 and the fourth conductive connecting portion 74.
  • the middle portion 743 of the fourth conductive connection portion 74 has the second gap, so that the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73 and the fourth conductive connection portion
  • the conductive connecting portion 74 can be arranged compactly, thereby better improving the light transmittance of the display panel in the second pixel area.
  • an orthographic projection of the third conductive connection layer 75 on the substrate and an orthographic projection of the first conductive connection portion 71 on the substrate may be provided, and the second conductive connection portion 72
  • the orthographic projection on the substrate, the orthographic projection of the third conductive connecting portion 73 on the substrate, and the orthographic projection of the fourth conductive connecting portion 74 on the substrate all overlap.
  • the above arrangement enables the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, the fourth conductive connection portion 74 and the third conductive connection layer 75 to be compactly arranged, thereby making it more compact. It improves the light transmittance of the display panel in the second pixel area.
  • the first conductive connection portion 71, the second conductive connection portion 72, and the fourth conductive connection portion 74 each include a first side portion and a second side portion, And an intermediate portion located between the first side portion and the second side portion; the intermediate portion extends in a first direction, and the first side portion includes a portion extending in the first direction and an intermediate portion extending in the second direction.
  • the second side part includes a part extending in a first direction and a part extending in a second direction;
  • the orthographic projection of the middle portion of the fourth conductive connecting portion 74 on the substrate, the orthographic projection of the middle portion of the first conductive connecting portion 71 on the substrate, and the third conductive connecting portion 73 The orthographic projection of the third portion 733 of the second conductive connecting portion 72 on the substrate, and the orthographic projection of the middle portion of the second conductive connecting portion 72 on the substrate, all located on the third conductive connecting layer 75 on the substrate The interior of the orthographic projection.
  • the above arrangement enables the first conductive connection portion 71, the second conductive connection portion 72, the third conductive connection portion 73, the fourth conductive connection portion 74 and the third conductive connection layer 75 to be compactly arranged, thereby making it more compact. It improves the light transmittance of the display panel in the second pixel area.
  • the first conductive connection part 71 can also be used to meet the functional requirements.
  • the line width of the second conductive connection portion 72, the third conductive connection portion 73, the fourth conductive connection portion 74, and the area of the third conductive connection layer 75 are as small as possible, thereby better improving the The light transmittance of the display panel in the second pixel area.
  • the sub-pixel may be configured to further include a data line pattern 908 extending along the second direction;
  • the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, the storage capacitor including The first electrode plate and the second electrode plate are arranged oppositely; the first conductive connection layer and the gate electrode of the transistor structure are arranged in the same layer and the same material; the second conductive connection layer is the same layer as the data line pattern 908 The same material is set; the third conductive connection layer 75 and the second electrode plate are set in the same layer and the same material.
  • the first conductive connection layer and the gate of the transistor structure are arranged in the same layer and the same material, so that the first conductive connection layer and the gate of the transistor structure can be formed in the same patterning process;
  • the second conductive connection layer and the data line pattern 908 are arranged in the same layer and the same material, so that the second conductive connection layer and the data line pattern 908 can be formed in the same patterning process;
  • the third conductive connection The layer 75 and the second electrode plate are arranged in the same layer and the same material, so that the third conductive connection layer 75 and the second electrode plate can be formed in the same patterning process; thus, the production of the display panel is better simplified The process flow saves the production cost.
  • the sub-pixel may be configured to further include a data line pattern 908 extending along the second direction;
  • the sub-pixel driving circuit includes: a transistor structure and a storage capacitor, the storage capacitor including The first electrode plate and the second electrode plate are arranged oppositely; the first conductive connection layer and the second electrode plate are arranged in the same layer and the same material; the second conductive connection layer is in the same layer and the same layer as the data line pattern 908 Material arrangement;
  • the third conductive connection layer 75 and the gate electrode of the transistor structure are arranged in the same layer and the same material.
  • the first conductive connection layer and the second electrode plate are arranged in the same layer and the same material, so that the first conductive connection layer and the second electrode plate can be formed in the same patterning process;
  • the two conductive connection layers are arranged in the same layer and the same material as the data line pattern 908, so that the second conductive connection layer and the data line pattern 908 can be formed in the same patterning process;
  • the third conductive connection layer 75 The same layer and the same material as the gate of the transistor structure are arranged, so that the third conductive connection layer 75 and the gate of the transistor structure can be formed in the same patterning process; thus, the production of the display panel is better simplified The process flow saves the production cost.
  • the first signal line pattern includes a first reset signal line pattern
  • the second signal line pattern includes a light emission control signal line pattern
  • the third signal line pattern includes a gate line pattern and a second reset signal line pattern.
  • Signal line pattern; the sub-pixels also include a power signal line pattern, a data line pattern, a first initialization signal line pattern and a second initialization signal line pattern;
  • the sub-pixel driving circuits all include: a storage capacitor, a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to The first pole of the first transistor is coupled;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the first reset signal line pattern, the first electrode of the second transistor is coupled to the first initialization signal line pattern, and the second electrode of the second transistor is coupled to the first reset signal line pattern. Coupled to the gate of the driving transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The corresponding light-emitting element in the display panel is coupled;
  • the second electrode of the seventh transistor is coupled to the corresponding light emitting element, the gate of the seventh transistor is coupled to the second reset signal line pattern, and the first electrode of the seventh transistor is coupled to the corresponding light emitting element.
  • the second initialization signal line pattern is coupled.
  • the plurality of sub-pixel driving circuits included in the display panel can be divided into rows of sub-pixel driving circuits arranged in sequence along the second direction, and The multiple columns of sub-pixel drive circuits arranged sequentially in the first direction, and the first initialization signal line patterns 904 corresponding to the sub-pixel drive circuits belonging to the same pixel unit are sequentially electrically connected to form an integrated structure; sub-pixels belonging to the same pixel unit The second initialization signal line patterns 904' corresponding to the driving circuit are electrically connected in order to form an integrated structure; the gate line patterns 902 corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in order to form an integrated structure; The light emission control signal line patterns 903 corresponding to the sub-pixel driving circuits belonging to the same pixel unit are electrically connected in sequence to form an integrated structure; the first reset signal line patterns 905 corresponding to the sub-pixel driving circuits belonging to the same pixel unit The second reset signal line patterns 905'
  • the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor.
  • Each transistor included in the sub-pixel driving circuit adopts a P-type transistor, wherein the first transistor T1 has a double-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, and the source S1 of the first transistor T1 It is coupled to the drain D3 of the third transistor T3 (ie, the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double gate structure, the gate 202g of the second transistor T2 is coupled to the first reset signal line pattern 905, and the source S2 of the second transistor T2 is coupled to the first initialization signal line pattern 904 , The drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source of the third transistor T3. S3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 ⁇ S3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the display panel The corresponding light-emitting element is coupled.
  • the gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern 905', the drain D7 of the seventh transistor T7 is coupled to the light-emitting element, and the source S7 of the seventh transistor T7 is coupled to the second initialization
  • the signal line pattern 904' is coupled.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • each work cycle includes a reset period P1, a write compensation period P2, and a light emitting period P3.
  • E1 represents the light emission control signal transmitted on the light emission control signal line pattern 903 in the current sub-pixel
  • R1 represents the reset signal transmitted on the first reset signal line pattern 905 in the current sub-pixel
  • D1 represents the current sub-pixel.
  • the data signal transmitted on the data line pattern 908, G1 represents the gate scan signal transmitted on the gate line pattern 902 in the current sub-pixel
  • R1' represents the reset transmitted on the second reset signal line pattern 905' in the current sub-pixel Signal.
  • the reset signal input by the first reset signal line pattern 905 is at an active level
  • the second transistor T2 is turned on
  • the initialization signal output by the first initialization signal line pattern 904' is input To the gate 203g of the third transistor T3, the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared to reset the gate 203g of the third transistor T3.
  • the reset signal input from the first reset signal line pattern 905 is at an inactive level
  • the second transistor T2 is turned off
  • the gate scanning signal input from the gate line pattern 902 is at an active level, controlling the first
  • the transistor T1 and the fourth transistor T4 are turned on
  • the data line pattern 908 writes a data signal, which is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4.
  • the first transistor T1 and the fourth transistor T4 are turned on.
  • the third transistor T3 is turned on, so that the third transistor T3 is formed as a diode structure. Therefore, the first transistor T1, the third transistor T3, and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the potential of the gate 203g of the third transistor T3 can be controlled to finally reach Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the reset signal input by the second reset signal line pattern 905' is at an active level
  • the seventh transistor T7 is controlled to be turned on
  • the initialization signal transmitted by the second initialization signal line pattern 904' is input To the anode of the light emitting element EL, the light emitting element EL is controlled not to emit light.
  • the light emission control signal written in the light emission control signal line pattern 903 is at an effective level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line pattern 901 is input to the third The source S3 of the transistor T3, and the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on.
  • the corresponding gate-source voltage of the third transistor T3 is Vdata+Vth-VDD, where VDD is According to the voltage value corresponding to the power signal, the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light.
  • each film layer corresponding to the display sub-pixel drive circuit is as follows:
  • the active film layer, the gate insulating layer, the first gate metal layer, the first interlayer insulating layer, the second gate metal layer, the second interlayer insulating layer, the first source and drain are stacked in sequence in the direction away from the substrate The metal layer and the third interlayer insulating layer.
  • the active film layer is used to form the channel region (such as 101pg ⁇ 107pg) of each transistor in the display sub-pixel driving circuit, the source formation region and the drain formation region, the source formation region and the drain Due to the doping effect, the active film layer corresponding to the formation area has better conductivity than the active film layer corresponding to the channel area; the active film layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the source formation region and the drain formation region can directly serve as the corresponding source (such as S1 to S7) and drain (such as D1 to D7), or also
  • the source electrode contacting the source electrode formation region can be made of a metal material, and the drain electrode contacting the drain electrode formation region can be made of a metal material.
  • the first gate metal layer is used to form the gates of the transistors in the sub-pixel driving circuit (e.g., 201g ⁇ 207g), and the gate line pattern 902, the light emission control signal line pattern 903, and the reset
  • the signal line pattern 905 and other structures, the gate 203g of the third transistor T3 in each sub-pixel driving circuit is multiplexed as the first plate Cst1 of the second storage capacitor Cst in the sub-pixel driving circuit.
  • the second gate metal layer is used to form the second plate Cst2 of the second storage capacitor Cst, and the first initialization signal line pattern 904 and the second initialization signal line pattern 904' included in the display substrate.
  • the first source/drain metal layer is used to form a data line pattern 908, a power signal line pattern 901 and some conductive connections included in the display panel.
  • the gate 201g of the first transistor T1 covers the first channel region 101pg
  • the gate 202g of the second transistor T2 covers the second channel region 102pg
  • the gate of the third transistor T3 The gate 203g covers the third channel region 103pg
  • the gate 204g of the fourth transistor T4 covers the fourth channel region 104pg
  • the gate 205g of the fifth transistor T5 covers the fifth channel region 105pg
  • the gate of the sixth transistor T6 206g covers the sixth channel region 106pg
  • the gate 207g of the seventh transistor T7 covers the seventh channel region 107pg.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • the gate 204g of the fourth transistor T4 in the second direction (such as the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate of the second transistor T2
  • the gate 202g is located on the first side of the gate of the driving transistor (that is, the gate 203g of the third transistor T3), the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 They are all located on the second side of the gate of the driving transistor.
  • the first side and the second side of the gate of the driving transistor are two opposite sides along the second direction. Further, the first side of the gate of the driving transistor may be the bottom of the gate of the driving transistor.
  • the second side of the gate of the driving transistor may be the upper side of the gate of the driving transistor.
  • the lower side for example, the side of the display panel for bonding the IC is the lower side of the display panel, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC.
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor further away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the second transistor T1
  • the gates 206g of the six transistors T6 are all located on the fourth side of the gate of the driving transistor.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor may be the right side of the gate of the driving transistor, The fourth side of the gate of the driving transistor may be the left side of the gate of the driving transistor.
  • the data line pattern 908 is located on the right side of the power signal line pattern 901
  • the power signal line pattern 901 is located on the left side of the data line pattern 908.
  • An embodiment of the present disclosure also provides a display device, which includes the display panel provided in the foregoing embodiment.
  • a conductive connection structure is provided between two sub-pixels included in the sub-pixel group, and the conductive connection structure includes: a first conductive connection layer, a second conductive connection layer, and a second conductive connection layer arranged in different layers.
  • the conductive connection structure realizes that the signal line patterns used for transmitting the same signal included in each sub-pixel in the sub-pixel group are correspondingly coupled together.
  • the orthographic projection of the third conductive connection layer 75 on the substrate of the display panel is provided to cover the orthographic projection of the first gap on the substrate and the The orthographic projection of the second gap on the substrate enables the third conductive connection layer 75 to cover the gap between the adjacent conductive connections between the two sub-pixels in the sub-pixel group, thereby reducing the occurrence of gaps.
  • the third conductive connection layer 75 is coupled to the fifth signal line pattern 85 for transmitting the fifth signal with a fixed potential, so that the third conductive connection layer 75 It has a stable potential and will not greatly affect the RC (resistance-capacitance) loading of the fifth signal line pattern 85.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel, it also has the above-mentioned intentional effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel for manufacturing the display panel provided by the above-mentioned embodiments.
  • the display panel includes a first pixel area and a second pixel area.
  • the pixel density of the second pixel area is Lower than the pixel density of the first pixel area; the manufacturing method includes:
  • the plurality of pixel units form a plurality of rows of pixel unit rows, each row of pixel unit rows includes a plurality of pixel units arranged along a first direction; each pixel unit includes a plurality of sub-pixels arranged along the first direction, in the same In a row of pixel units, the two closest sub-pixels among two adjacent pixel units form a sub-pixel group; the sub-pixels include: a sub-pixel drive circuit, and a first signal coupled to the sub-pixel drive circuit, respectively Line pattern to the fifth signal line pattern;
  • the plurality of conductive connection structures correspond to the sub-pixel groups one-to-one, the conductive connection structure is located between two sub-pixels included in the corresponding sub-pixel group, and the conductive connection structure includes: first conductive connections arranged in different layers A connection layer, a second conductive connection layer and a third conductive connection layer;
  • the first conductive connection layer includes a first conductive connection portion and a second conductive connection portion, and there is a first gap between the first conductive connection portion and the second conductive connection portion; the first conductive connection portion is respectively coupled to the corresponding A first signal line pattern included in each sub-pixel in the sub-pixel group, and the second conductive connection portion is respectively coupled to a second signal line pattern included in each sub-pixel in the corresponding sub-pixel group;
  • the second conductive connection layer includes a third conductive connection portion and at least one fourth conductive connection portion, and there is a second gap between the adjacent third conductive connection portion and the fourth conductive connection portion;
  • the three conductive connection portions are respectively coupled to the third signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and the at least one fourth conductive connection portion is connected to the first signal line pattern included in each sub-pixel in the corresponding sub-pixel group.
  • the four signal line patterns are in one-to-one correspondence, and the fourth conductive connection portions are respectively coupled to the corresponding fourth signal line patterns;
  • the third conductive connection layer is respectively coupled to a fifth signal line pattern included in each sub-pixel in the corresponding sub-pixel group, and the fifth signal line pattern is used to transmit a fifth signal with a fixed potential.
  • the orthographic projection of the three conductive connection layers on the substrate of the display panel covering at least part of the orthographic projection of the first gap on the substrate and at least part of the orthographic projection of the second gap on the substrate .
  • a conductive connection structure is provided between two sub-pixels included in the sub-pixel group, and the conductive connection structure includes: a first conductive connection layer arranged in different layers, and a second conductive connection layer.
  • the display panel manufactured by the manufacturing method provided in the embodiment realizes the corresponding coupling of the signal line patterns included in each sub-pixel in the sub-pixel group for transmitting the same signal by providing the conductive connection structure.
  • the first gap is covered on the substrate. At least part of the orthographic projection of the second gap and at least part of the orthographic projection of the second gap on the substrate, so that the third conductive connection layer 75 can cover the adjacent conductive connections between two sub-pixels in the sub-pixel group.
  • the gap between the connecting parts reduces the light leakage phenomenon at the gap, thereby avoiding the interference diffraction and glare caused by the light passing through the gap, and better ensuring the imaging quality of the camera in the display panel when taking pictures. .
  • the third conductive connection layer 75 is coupled to the fifth signal line pattern 85 for transmitting the fifth signal with a fixed potential, so that the The third conductive connection layer 75 has a stable potential, and will not greatly affect the RC (resistance-capacitance) loading of the fifth signal line pattern 85.

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Abstract

一种显示面板及其制作方法、显示装置，所述显示面板的第二像素区中，第一导电连接层中的第一导电连接部（71）和第二导电连接部（72）之间具有第一间隙；第二导电连接层中的第三导电连接部（73）和第四导电连接部（74）之间具有第二间隙；第三导电连接层（75）分别耦接对应的子像素组中各子像素包括的第五信号线图形（85），第五信号线图形（85）用于传输具有固定电位的第五信号，第三导电连接层（75）在显示面板的基底上的正投影，覆盖第一间隙在基底上的正投影的至少部分和第二间隙在基底上的正投影的至少部分。

Description

显示面板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
随着消费者对屏幕完整性要求的提高，在显示屏下设置摄像头的技术益发流行。这种屏下摄像的技术主要是将摄像头设置于显示屏的显示区域内，并将摄像头设置于像素单元的下方，通过降低摄像头所在区域的像素密度，来兼容显示面板的显示功能和摄像头的摄像功能。
发明内容
本公开的目的在于提供一种显示面板及其制作方法、显示装置。
本公开的第一方面提供一种显示面板，包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述第二像素区包括阵列分布的多个像素单元，所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及分别与该子像素驱动电路耦接的第一信号线图形至第五信号线图形；
所述显示面板还包括：与所述子像素组一一对应的多个导电连接结构，所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接 层；
所述第一导电连接层包括第一导电连接部和第二导电连接部，第一导电连接部和第二导电连接部之间具有第一间隙；所述第一导电连接部分别耦接对应的所述子像素组中各子像素包括的第一信号线图形，所述第二导电连接部分别耦接对应的所述子像素组中各子像素包括的第二信号线图形；
所述第二导电连接层包括第三导电连接部和至少一个第四导电连接部，相邻的所述第三导电连接部和所述第四导电连接部之间具有第二间隙；所述第三导电连接部分别耦接对应的所述子像素组中各子像素包括的第三信号线图形，所述至少一个第四导电连接部与对应的所述子像素组中每个子像素包括的第四信号线图形均一一对应，所述第四导电连接部分别与对应的第四信号线图形耦接；
所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的第五信号线图形，所述第五信号线图形用于传输具有固定电位的第五信号，所述第三导电连接层在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
可选的，所述第一信号线图形包括第一复位信号线图形，所述第一复位信号线图形的至少部分沿所述第一方向延伸；所述第二信号线图形包括发光控制信号线图形，所述发光控制信号线图形的至少部分沿所述第一方向延伸。
可选的，所述第三信号线图形包括沿第二方向排列的栅线图形和第二复位信号线图形，所述栅线图形的至少部分和所述第二复位信号线图形的至少部分均沿第一方向延伸，所述栅线图形和所述第二复位信号线图形用于传输相同的第三信号；
所述第三导电连接部包括第一部分、第二部分和第三部分，所述第一部分和所述第二部分沿第二方向延伸，所述第三部分沿第一方向延伸，所述第二方向与所述第一方向相交；所述第一部分分别耦接所述子像素组中一个子像素包括的所述栅线图形和所述第二复位信号线图形，所述第二部分分别耦接所述子像素组中另一个子像素包括的所述栅线图形和所述第二复位信号线 图形，所述第三部分分别与所述第一部分和所述第二部分耦接。
可选的，所述第四信号线图形包括沿第二方向排列的两个初始化信号线图形，所述第二方向与所述第一方向相交，所述第二导电连接层包括两个第四导电连接部，所述两个第四导电连接部与对应的所述子像素组中每个子像素包括的所述初始化信号线图形均一一对应，每个所述第四导电连接部与对应的第四信号线图形分别耦接；
所述第三导电连接部在所述基底上的正投影的至少部分，位于所述两个第四导电连接部在所述基底上的正投影之间。
可选的，所述子像素驱动电路包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间；
所述第五信号线图形包括电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，在同一子像素中所述第二极板与所述电源信号线图形耦接；
所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的所述第二极板。
可选的，所述第一导电连接部在所述基底上的正投影，分别与所述第三导电连接部在所述基底上的正投影，以及所述两个第四导电连接部中的一个在所述基底上的正投影交叠；和/或，
所述第二导电连接部在所述基底上的正投影，分别与所述第三导电连接部在所述基底上的正投影，以及所述两个第四导电连接部中的另一个在所述基底上的正投影交叠。
可选的，所述第一导电连接部、所述第二导电连接部、所述第四导电连接部均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
所述两个第四导电连接部中的一个包括的中间部在所述基底上的正投影，所述第一导电连接部包括的中间部在所述基底上的正投影，所述第三导 电连接部的第三部分在所述基底上的正投影，所述第二导电连接部包括的中间部在所述基底上的正投影，以及所述两个第四导电连接部中的另一个包括的中间部在所述基底上的正投影，沿所述第二方向依次排列。
可选的，其中，所述子像素驱动电路包括存储电容，所述存储电容包括沿垂直于所述基底的方向相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间；
所述第四信号线图形包括电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二极板与所述电源信号线图形耦接；
所述第二导电连接层包括一个第四导电连接部，所述第四导电连接部分别耦接对应的所述子像素组中各子像素包括的所述第二极板。
可选的，所述第五信号线图形包括沿所述第二方向排列的两个初始化信号线图形，所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的所述初始化信号线图形。
可选的，所述第四导电连接部在所述基底上的正投影，位于所述第一导电连接部在所述基底上的正投影与所述第二导电连接部在所述基底上的正投影之间；所述第三导电连接部在所述基底上的正投影与所述第二导电连接部在所述基底上的正投影交叠。
可选的，所述第四导电连接部在所述基底上的正投影，分别与所述第一导电连接部在所述基底上的正投影和所述第二导电连接部在所述基底上的正投影交叠。
可选的，所述第四导电连接部在所述基底上的正投影，与所述第一导电连接部在所述基底上的正投影交叠；所述第三导电连接部在所述基底上的正投影与所述第二导电连接部在所述基底上的正投影交叠。
可选的，所述第一导电连接部、所述第二导电连接部、所述第四导电连接部均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
所述第一导电连接部的中间部与所述第二导电连接部的中间部之间具有所述第一间隙，所述第一间隙沿垂直于所述第一方向的方向上具有第一宽度，所述第一宽度为满足所述第一导电连接部的中间部与所述第二导电连接部的中间部绝缘条件的最小宽度；
所述第三导电连接部的中间部与所述第四导电连接部的中间部之间具有所述第二间隙，所述第二间隙沿垂直于所述第一方向的方向上具有第二宽度，所述第二宽度为满足所述第三导电连接部的中间部与所述第四导电连接部的中间部绝缘条件的最小宽度。
可选的，所述第三导电连接层在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影，所述第二导电连接部在所述基底上的正投影，所述第三导电连接部在所述基底上的正投影，以及所述第四导电连接部在所述基底上的正投影均交叠。
可选的，所述第一导电连接部、所述第二导电连接部、所述第四导电连接部均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
所述第四导电连接部包括的中间部在所述基底上的正投影，所述第一导电连接部包括的中间部在所述基底上的正投影，所述第三导电连接部的第三部分在所述基底上的正投影，所述第二导电连接部包括的中间部在所述基底上的正投影，均位于所述第三导电连接层在所述基底上的正投影的内部。
可选的，所述子像素还包括数据线图形，所述数据线图形沿第二方向延伸；所述子像素驱动电路包括：晶体管结构和存储电容，所述存储电容包括相对设置的第一极板和第二极板；
所述第一导电连接层与所述晶体管结构的栅极同层同材料设置；
所述第二导电连接层与所述数据线图形同层同材料设置；
所述第三导电连接层与所述第二极板同层同材料设置。
可选的，所述子像素还包括数据线图形，所述数据线图形沿第二方向延 伸；所述子像素驱动电路包括：晶体管结构和存储电容，所述存储电容包括相对设置的第一极板和第二极板；
所述第一导电连接层与所述第二极板同层同材料设置；
所述第二导电连接层与所述数据线图形同层同材料设置；
所述第三导电连接层与所述晶体管结构的栅极同层同材料设置。
可选的，所述第一信号线图形包括第一复位信号线图形，所述第二信号线图形包括发光控制信号线图形，所述第三信号线图形包括栅线图形和第二复位信号线图形；所述子像素还包括电源信号线图形，数据线图形，第一初始化信号线图形和第二初始化信号线图形；
所述子像素驱动电路均包括：存储电容，驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与所述第一复位信号线图形耦接，所述第二晶体管的第一极与所述第一初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与显示面板中对应的所述发光元件耦接；
所述第七晶体管的第二极与对应的所述发光元件耦接，所述第七晶体管的栅极与所述第二复位信号线图形耦接，所述第七晶体管的第一极与所述第 二初始化信号线图形耦接。
基于上述显示面板的技术方案，本公开的第二方面提供一种显示装置，所述显示装置包括上述显示面板。
基于上述显示面板的技术方案，本公开的第三方面提供一种显示面板的制作方法，所述显示面板包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述制作方法包括：
在所述第二像素区制作阵列分布的多个像素单元和多个导电连接结构；
所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及分别与该子像素驱动电路耦接的第一信号线图形至第五信号线图形；
所述多个导电连接结构与所述子像素组一一对应，所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层；
所述第一导电连接层包括第一导电连接部和第二导电连接部，第一导电连接部和第二导电连接部之间具有第一间隙；所述第一导电连接部分别耦接对应的所述子像素组中各子像素包括的第一信号线图形，所述第二导电连接部分别耦接对应的所述子像素组中各子像素包括的第二信号线图形；
所述第二导电连接层包括第三导电连接部和至少一个第四导电连接部，相邻的所述第三导电连接部和所述第四导电连接部之间具有第二间隙；所述第三导电连接部分别耦接对应的所述子像素组中各子像素包括的第三信号线图形，所述至少一个第四导电连接部与对应的所述子像素组中每个子像素包括的第四信号线图形均一一对应，所述第四导电连接部分别与对应的第四信号线图形耦接；
所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的第五信号线图形，所述第五信号线图形用于传输具有固定电位的第五信号，所述第三导电连接层在所述显示面板的基底上的正投影，覆盖所述第一间隙在 所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的子像素组的第一布局示意图；
图2为本公开实施例提供的子像素驱动电路的电路图；
图3为本公开实施例提供的子像素驱动电路的时序图；
图4为本公开实施例提供的子像素组的第二布局示意图；
图5为图4中有源层的布局示意图；
图6为图4中第一栅金属层的布局示意图；
图7为图4中第二栅金属层的布局示意图；
图8为图4中第一源漏金属层的第一示意图；
图9为图4中第一源漏金属层的第二示意图；
图10为本公开实施例提供的子像素组的第三布局示意图；
图11为图10中第二栅金属层的布局示意图；
图12为图10中第一源漏金属层的布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示面板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
如图1所示，本公开提供一种显示面板，所述显示面板包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述第二像素区包括阵列分布的多个像素单元，所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中， 相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及与所述子像素驱动电路分别耦接的信号线图形，所述信号线图形可具体包括：电源信号线图形901、数据线图形908、栅线图形902、发光控制信号线图形903、第一复位信号线图形905、第一初始化信号线图形904、第二复位信号线图形905'和第二初始化信号线图形904'。需要说明，所述像素密度表示每英寸所拥有的像素数量。
所述第一像素区中同样设置有阵列分布的多个像素单元，每个像素单元中包括的子像素的具体结构与第二像素区相同。由于在所述第二像素区中设置有屏下摄像头，因此所述第二像素区中的像素密度较低，在布局所述第一像素区中的像素单元和所述第二像素区的像素单元时，第一像素区的像素单元布局紧凑，而第二像素区的像素单元布局宽松。在所述第二像素区中，在同一行像素单元行中，相邻的两个像素单元之间间距较大，所述子像素组之间需要通过设置导电连接结构，来实现将所述子像素组中各子像素包括的相同信号线图形耦接在一起。
请继续参阅图1，在所述子像素组中，两个子像素之间的导电连接结构包括七个导电连接部，该七个导电连接部用于将子像素组中各子像素包括的第一初始化信号线图形904耦接，用于将子像素组中各子像素包括的第一复位信号线图形905耦接，用于将子像素组中各子像素包括的栅线图形902耦接，用于将子像素组中各子像素包括的发光控制信号线图形903耦接，用于将子像素组中各子像素包括的第二初始化信号线图形904'耦接，用于将子像素组中各子像素包括的第二复位信号线图形905'耦接，用于将子像组中各子像素包括的电源信号线图形901耦接。
上述实施例提供的显示面板虽然通过降低摄像头所在第二像素区域的像素密度，来兼容显示面板的显示功能和摄像头的摄像功能，但是相邻的导电连接部之间存在缝隙，从该缝隙透过的光会形成衍射、眩光，从而影响摄像头在拍照时的成像质量。另外，由于形成的导电连接部的数量较多，占用的布局空间面积较大，使得在所述第二像素区，屏幕的透过率低，从而影响摄像头在拍照时的成像质量。
请参阅图4和图10，本公开实施例提供了一种显示面板，包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述第二像素区包括阵列分布的多个像素单元，所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及分别与该子像素驱动电路耦接的第一信号线图形81至第五信号线图形85；
所述显示面板还包括：与所述子像素组一一对应的多个导电连接结构，所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层75；
所述第一导电连接层包括第一导电连接部71和第二导电连接部72，第一导电连接部71和第二导电连接部72之间具有第一间隙；所述第一导电连接部71分别耦接对应的所述子像素组中各子像素包括的第一信号线图形81，所述第二导电连接部72分别耦接对应的所述子像素组中各子像素包括的第二信号线图形82；
所述第二导电连接层包括第三导电连接部73和至少一个第四导电连接部74，相邻的所述第三导电连接部73和所述第四导电连接部74之间具有第二间隙；所述第三导电连接部73分别耦接对应的所述子像素组中各子像素包括的第三信号线图形83，所述至少一个第四导电连接部74与对应的所述子像素组中每个子像素包括的第四信号线图形84均一一对应，所述第四导电连接部74分别与对应的第四信号线图形84耦接；
所述第三导电连接层75分别耦接对应的所述子像素组中各子像素包括的第五信号线图形85，所述第五信号线图形85用于传输具有固定电位的第五信号，所述第三导电连接层75在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
具体的，所述显示面板包括第一像素区和第二像素区，所述第一像素区和第二像素区均能够实现显示功能。所述第二像素区的像素像素密度低于所述第一像素区的像素像素密度，在所述第二像素区中，在所述基底与子像素驱动电路之间设置有摄像头。
所述第一像素区和所述第二像素区中像素单元的具体布局方式多种多样，示例性的，所述第一像素区中的像素单元和所述第二像素区中的像素单元均呈阵列分布。示例性的，沿所述第一方向，在显示面板的同一行像素单元中，位于第一像素区中的信号线图形与位于第二像素区中用于传输相同信号的信号线图形之间电连接。
在所述第二像素区中，阵列分布的多个像素单元能够形成沿第二方向依次排列的多行像素单元行，每一行像素单元行均包括沿第一方向依次排布的多个像素单元。所述第一方向与所述第二方向相交，示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
在所述第二像素区中，每个像素单元均包括沿第一方向排列的多个子像素，示例性的，每个像素单元均包括沿第一方向排列的红色子像素、绿色子像素和蓝色子像素。每个像素单元包括的多个子像素之间紧凑排列，在一个像素单元中各子像素包括的用于传输相同信号的信号线图形直接耦接，示例性的，在一个像素单元中各子像素包括的用于传输相同信号的信号线图形可形成为一体结构。
在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；示例性的，每个像素单元中均包括沿第一方向依次排列的第一子像素、第二子像素和第三子像素，所述子像素包括相邻的两个像素单元中，前一个像素单元的第三子像素与后一个像素单元的第一子像素。
示例性的，所述第一像素区和所述第二像素区中像素单元包括的各子像素的具体结构相同，每个子像素均包括子像素驱动电路，以及该子像素驱动电路分别耦接的多个信号线图形。示例性的，所述多个信号线图形包括第一信号线图形81、第二信号线图形82、第三信号线图形83、第四信号线图形84和第五信号线图形85；每个信号线图形均用于传输对应的信号。
在所述第一像素区中，沿第一方向，位于同一行的像素单元布局紧凑。在所述第二像素区中，沿第一方向，位于同一行的相邻像素单元之间具有一定的间距，该间距位于所述子像素组中两个子像素之间，用于透过光线以使位于第二像素区的摄像头能够实现摄像功能。
值得注意，在满足屏幕显示所必需的像素密度的前提下，应尽量减少第二像素区的像素密度或者像素尺寸(需满足现有制作工艺)，减少子像素之间导电连接部的面积，从而更好的提升第二像素区的透光率。
所述显示面板还包括：与所述子像素组一一对应的多个导电连接结构，每个所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构的具体结构多种多样，示例性的，所述导电连接结构包括：第一导电连接层、第二导电连接层和第三导电连接层75；第一导电连接层、第二导电连接层和第三导电连接层75中，任意两层均异层设置。
所述第一导电连接层、所述第二导电连接层和所述第三导电连接层75的具体结构和连接关系均多种多样，下面进行示例性说明。
所述第一导电连接层包括第一导电连接部71和第二导电连接部72，所述第一导电连接部71的至少部分沿第一方向延伸，所述第二导电连接部72的至少部分沿第一方向延伸，所述第一导电连接部71和所述第二导电连接部72之间具有第一间隙。所述第一导电连接部71分别耦接对应的所述子像素组中各子像素包括的第一信号线图形81，示例性的，所述第一导电连接部71与其耦接的第一信号线图形81形成为一体结构。所述第二导电连接部72分别耦接对应的所述子像素组中各子像素包括的第二信号线图形82，示例性的，所述第二导电连接部72与其耦接的第二信号线图形82形成为一体结构。
所述第二导电连接层包括第三导电连接部73和至少一个第四导电连接部74，所述第三导电连接部73的至少部分沿第一方向延伸，所述第四导电连接部74的至少部分沿第一方向延伸，相邻的所述第三导电连接部73和所述第四导电连接部74之间具有第二间隙。所述第三导电连接部73分别耦接对应的所述子像素组中各子像素包括的第三信号线图形83，示例性的，所述第三导电连接部73在所述基底上的正投影，与其耦接的第三信号线图形83 在所述基底上的正投影形成交叠区域，在该交叠区域，所述第三导电连接部73通过过孔与所述第三信号线图形83耦接。值得注意，所述第一间隙和所述第二间隙一般为小尺寸间隙，所述第一间隙和所述第二间隙可以设置为满足两个导电连接部之间彼此绝缘条件下的最小间隙。
所述至少一个第四导电连接部74与对应的所述子像素组中每个子像素包括的第四信号线图形84均一一对应，所述第四导电连接部74分别与对应的第四信号线图形84耦接；示例性的，如图4所示，所述第四导电连接部74在所述基底上的正投影，与其耦接的第四信号线图形84在所述基底上的正投影形成交叠区域，在该交叠区域，所述第四导电连接部74通过过孔与所述第四信号线图形84耦接。
所述第三导电连接层75分别耦接对应的所述子像素组中各子像素包括的第五信号线图形85，所述第五信号线图形85用于传输具有固定电位的第五信号。示例性的，所述第三导电连接层75与其耦接的第五信号线图形85形成为一体结构。示例性的，所第五信号线图形85与显示面板中的目标图形耦接，所述第三导电连接层75在所述基底上的正投影，与所述目标图形在所述基底上的正投影形成交叠区域，在该交叠区域，所述第三导电连接层75通过过孔与所述目标图形耦接，从而实现所述第三导电连接层75通过所述目标图形与所述第五信号线图形85耦接。
所述第三导电连接层75的至少部分沿第一方向延伸，示例性的，所述第三导电连接层75在所述显示面板的基底上的正投影，覆盖至少部分所述第一间隙在所述基底上的正投影和至少部分所述第二间隙在所述基底上的正投影。示例性的，所述第三导电连接层75在所述显示面板的基底上的正投影，完全覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
根据上述显示面板的具体结构可知，本公开实施例提供的显示面板中，在子像素组包括的两个子像素之间设置了导电连接结构，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层75；所述第一导电连接层和所述第二导电连接层用于将子像素组中各子像素包括 的用于传输相同信号的信号线图形耦接在一起；所述第三导电连接层75用于将子像素组中各子像素包括的用于传输具有固定电位的第五信号的第五信号线图形85耦接在一起；因此，本公开实施例提供的显示面板通过设置所述导电连接结构，实现了将所述子像素组中各子像素包括的用于传输相同信号的信号线图形对应耦接在一起。
另外，本公开实施例提供的显示面板中，通过设置所述第三导电连接层75在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分，使得所述第三导电连接层75能够覆盖所述子像素组中位于两个子像素之间相邻导电连接部之间的缝隙，减少了缝隙处产生的漏光现象，从而避免了光线透过该缝隙时产生的干扰性衍射、眩光等问题，更好的保证了显示面板中摄像头在拍照时的成像质量。
此外，本公开实施例提供的显示面板中，将所述第三导电连接层75与用于传输具有固定电位的第五信号的第五信号线图形85耦接，使得所述第三导电连接层75具有稳定的电位，不会对所述第五信号线图形85的RC(阻容)loading(负载)产生太大影响。
如图4和图6所示，在一些实施例中，所述第一信号线图形81包括第一复位信号线图形905，所述第一复位信号线图形905的至少部分沿所述第一方向延伸；所述第二信号线图形82包括发光控制信号线图形903，所述发光控制信号线图形903的至少部分沿所述第一方向延伸。
具体的，所述第一导电连接部71分别耦接对应的所述子像素组中各子像素包括的第一复位信号线图形905。示例性的，所述第一导电连接部71与其耦接的各所述第一复位信号线图形905形成为一体结构。
所述第二导电连接部72分别耦接对应的所述子像素组中各子像素包括的发光控制信号线图形903。示例性的，所述第二导电连接部72与其耦接的各所述发光控制信号线图形903形成为一体结构。
示例性的，在同一个子像素中，所述第一复位信号线图形905与所述发光控制信号线图形903沿第二方向排列，所述第二方向与所述第一方向相交。
上述实施例提供的显示面板中，通过设置所述第一信号线图形81包括第一复位信号线图形905，所述第一导电连接部71与其耦接的各所述第一复位信号线图形905形成为一体结构，使得所述第一导电连接部71与所述第一复位信号线图形905能够在同一次构图工艺中同时形成，且所形成的所述第一导电连接部71与所述第一复位信号线图形905能够直接耦接。同样的，通过设置所述第二信号线图形82包括发光控制信号线图形903，所述第二导电连接部72与其耦接的各所述发光控制信号线图形903形成为一体结构，使得所述第二导电连接部72与所述发光控制信号线图形903能够在同一次构图工艺中同时形成，且所形成的所述第二导电连接部72与所述发光控制信号线图形903能够直接耦接。因此，上述实施例提供的显示面板有效简化了制作工艺流程，节约了制作成本。
如图4、图8、图10和图12所示，在一些实施例中，所述第三信号线图形83包括沿第二方向排列的栅线图形902和第二复位信号线图形905’，所述栅线图形902的至少部分和所述第二复位信号线图形905’的至少部分均沿第一方向延伸，所述栅线图形902和所述第二复位信号线图形905’用于传输相同的第三信号；
所述第三导电连接部73包括第一部分731、第二部分732和第三部分733，所述第一部分731和所述第二部分732沿第二方向延伸，所述第三部分733沿第一方向延伸，所述第二方向与所述第一方向相交；所述第一部分731分别耦接所述子像素组中一个子像素包括的所述栅线图形902和所述第二复位信号线图形905’，所述第二部分732分别耦接所述子像素组中另一个子像素包括的所述栅线图形902和所述第二复位信号线图形905’，所述第三部分733分别与所述第一部分731和所述第二部分732耦接。
具体的，在每个子像素中，所述第三信号线图形83均包括沿第二方向排列的栅线图形902和第二复位信号线图形905’，所述栅线图形902和所述第二复位信号线图形905’用于传输相同的第三信号。
所述第三导电连接部73的具体结构多种多样，示例性的，所述第三导电连接部73包括所述第一部分731、所述第二部分732和所述第三部分733， 所述第一部分731和所述第二部分732沿第二方向延伸，所述第三部分733沿第一方向延伸。示例性的，所述第一部分731、所述第二部分732和所述第三部分733形成为一体结构。
所述第一部分731用于分别耦接所述子像素组中第一子像素包括的所述栅线图形902和所述第二复位信号线图形905’，示例性的，所述第一部分731在所述基底上的正投影，分别与该栅线图形902在所述基底上的正投影和该第二复位信号线图形905’在所述基底上的正投影形成交叠区域，所述第一部分731能够通过形成在所述交叠区域的过孔，实现与所述栅线图形902和所述第二复位信号线图形905’分别耦接。
所述第二部分732用于分别耦接所述子像素组中第二子像素包括的所述栅线图形902和所述第二复位信号线图形905’，示例性的，所述第二部分732在所述基底上的正投影，分别与该栅线图形902在所述基底上的正投影和该第二复位信号线图形905’在所述基底上的正投影形成交叠区域，所述第二部分732能够通过形成在所述交叠区域的过孔，实现与所述栅线图形902和所述第二复位信号线图形905’分别耦接。
上述实施例提供的显示面板中，通过设置所述第三导电连接部73将对应的子像素组中，各子像素包括的用于传输相同第三信号的栅线图形902和第二复位信号线图形905’耦接在一起，有效缩小了所述导电连接结构占用的布局空间，从而更好的提升了第二像素区的透光率。
另外，上述实施例提供的显示面板中，通过设置所述第一部分731、所述第二部分732和所述第三部分733形成为一体结构，使得所述第三导电连接部73能够在一次构图工艺中形成，从而有效简化了显示面板的制作流程，节约了制作成本。
如图4、图7和图9所示，在一些实施例中，所述第四信号线图形84包括沿第二方向排列的两个初始化信号线图形，所述第二方向与所述第一方向相交，所述第二导电连接层包括两个第四导电连接部74，所述两个第四导电连接部74与对应的所述子像素组中每个子像素包括的所述初始化信号线图形均一一对应，每个所述第四导电连接部74与对应的第四信号线图形84分 别耦接；
所述第三导电连接部73的至少部分在所述基底上的正投影，位于所述两个第四导电连接部74在所述基底上的正投影之间。
具体的，所述第四信号线图形84包括沿第二方向排列的第一初始化信号线图形904和第二初始化信号线图形904’，第一初始化信号线图形904的至少部分和第二初始化信号线图形904’的至少部分均沿第一方向延伸。
所述第二导电连接层包括两个第四导电连接部74，其中一个第四导电连接部74与其对应的子像素组中各子像素包括的第一初始化信号线图形904分别耦接；另一个第四导电连接部74与其对应的子像素组中各子像素包括的第二初始化信号线图形904’分别耦接。
当设置所述第二导电连接层包括两个第四导电连接部74时，所述第三导电连接部73和所述两个第四导电连接部74之间的布局方式多种多样，示例性的，设置所述第三导电连接部73的至少部分在所述基底上的正投影，位于所述两个第四导电连接部74在所述基底上的正投影之间。示例性的，所述第三导电连接部73的第三部分733在所述基底上的正投影，位于所述两个第四导电连接部74在所述基底上的正投影之间。
在所述显示面板中，由于各子像素包括的第一初始化信号线图形904、栅线图形902、第二初始化信号线图形904’和第二复位信号线图形905’沿第二方向依次排列，上述设置所述第三导电连接部73在所述基底上的正投影，位于所述两个第四导电连接部74在所述基底上的正投影之间，使得在保证所述第三导电连接部73与所述第四导电连接部74之间绝缘的情况下，更有利于降低所述第三导电连接部73和所述两个第四导电连接部74的布局难度。
如图4、图7和图8所示，在一些实施例中，所述子像素驱动电路包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间；所述第五信号线图形85包括电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，在同一子像素中所述第二极板与所述电源信号线图形901耦接；所述第三导电连接层75分别耦接对应的所述子像素组中各子像素包括的所述第二极板。
具体的，所述子像素驱动电路包括驱动晶体管和存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间，示例性的，所述第一极板复用为所述驱动晶体管的栅极。示例性的，所述第一极板采用所述显示面板中的第一栅金属层制作，所述第二极板采用所述显示面板中的第二栅金属层制作。
所述第五信号线图形85包括电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，在同一子像素中，所述第二极板在所述基底上的正投影与所述电源信号线图形901在所述基底上的正投影形成交叠区域，在该交叠区域，所述电源信号线图形901通过过孔与所述第二极板耦接。示例性的，所述电源信号线图形901可采用显示面板中的第一源漏金属层制作。示例性的，沿第二方向位于同一列子像素中的各电源信号线图形901依次耦接，可形成为一体结构。
示例性的，所述第三导电连接层75可采用显示面板中的第二栅金属层制作，即将所述第三导电连接层75与所述第二极板同层同材料设置。这样所述第三导电连接层75能够与所述第二极板在同一次构图工艺中形成，且能够实现直接耦接，从而很好的简化了显示面板的制作工艺流程，降低了制作成本。
上述实施例提供的显示面板中，通过设置所述电源信号线图形901与所述第二极板耦接，以及所述第三导电连接层75分别耦接对应的所述子像素组中各子像素包括的所述第二极板，实现了所述第三导电连接层75与对应的所述子像素组中各子像素包括的电源信号线图形901耦接，使得所述第三导电连接层75具有与所述电源信号线图形901相同的稳定电位，这样在利用大面积的第三导电连接层75来遮挡相邻导电连接部之间的间隙时，能够更好的保证显示面板工作的稳定性。
在一些实施例中，所述第一导电连接部71在所述基底上的正投影，分别与所述第三导电连接部73在所述基底上的正投影，以及所述两个第四导电连接部74中的一个在所述基底上的正投影交叠；和/或，所述第二导电连接部72在所述基底上的正投影，分别与所述第三导电连接部73在所述基底上的正投影，以及所述两个第四导电连接部74中的另一个在所述基底上的正投影 交叠。
具体的，由于所述第一导电连接部71和所述第二导电连接部72均与所述第三导电连接部73、所述第四导电连接部74异层设置，因此，即使在垂直于所述基底的方向上，第一导电连接部71与所述第三导电连接部73、所述第四导电连接部74交叠，第一导电连接部71也不会与所述第三导电连接部73和所述第四导电连接部74发生短路。同样的，即使在垂直于所述基底的方向上，第二导电连接部72与所述第三导电连接部73、所述第四导电连接部74交叠，第二导电连接部72也不会与所述第三导电连接部73和所述第四导电连接部74发生短路。
上述设置所述第一导电连接部71在所述基底上的正投影，分别与所述第三导电连接部73在所述基底上的正投影，以及所述两个第四导电连接部74中的一个在所述基底上的正投影交叠，能够有效缩小所述第一导电连接部71、所述第三导电连接部73和所述第四导电连接部74整体占用的布局空间。同样的，设置所述第二导电连接部72在所述基底上的正投影，分别与所述第三导电连接部73在所述基底上的正投影，以及所述两个第四导电连接部74中的另一个在所述基底上的正投影交叠，能够有效缩小所述第二导电连接部72、所述第三导电连接部73和所述第四导电连接部74整体占用的布局空间。因此，上述设置方式能够最大限度的减小所述导电连接结构占用的布局空间，有效提升显示面板在第二像素区的透光率。
如图4所示，在一些实施例中，所述第一导电连接部71、所述第二导电连接部72、所述第四导电连接部74均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
如图6和图9所示，所述两个第四导电连接部74中的一个包括的中间部743在所述基底上的正投影，所述第一导电连接部71包括的中间部在所述基底上的正投影，所述第三导电连接部73的第三部分733在所述基底上的正投影，所述第二导电连接部72包括的中间部在所述基底上的正投影，以及所述 两个第四导电连接部74中的另一个包括的中间部在所述基底上的正投影，沿所述第二方向依次排列。
具体的，所述第一导电连接部71、所述第二导电连接部72、所述第四导电连接部74的具体结构多种多样，示例性的，所述第一导电连接部71、所述第二导电连接部72、所述第四导电连接部74均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部。
示例性的，可设置所述第一导电连接部71的中间部713、所述第二导电连接部72的中间部723、所述第四导电连接部74的中间部743均沿第一方向延伸；所述第一导电连接部71的第一边部711和第二边部712均包括沿第一方向延伸的部分和沿第二方向延伸的部分；所述第二导电连接部72的第一边部721和第二边部722均包括沿第一方向延伸的部分和沿第二方向延伸的部分；所述两个第四导电连接部74中的一个(如图9中的标记741)包括的第一边部744和第二边部745均包括沿第一方向延伸的部分和沿第二方向延伸的部分；所述两个第四导电连接部74中的另一个(如图9中的标记742)包括的第一边部744和第二边部745均包括沿第二方向延伸的部分。
示例性的，所述两个第四导电连接部74中的一个包括的中间部在所述基底上的正投影，所述第一导电连接部71包括的中间部在所述基底上的正投影，所述第三导电连接部73的第三部分733在所述基底上的正投影，所述第二导电连接部72包括的中间部在所述基底上的正投影，以及所述两个第四导电连接部74中的另一个包括的中间部在所述基底上的正投影紧凑的靠在一起，以缩小所述导电连接结构占用的布局空间。
示例性的，所述第一导电连接部71、所述第二导电连接部72、所述第四导电连接部74中包括第一边部和第二边部均向着远离中间部的方向延伸。
上述设置所述两个第四导电连接部74中的一个包括的中间部在所述基底上的正投影，所述第一导电连接部71包括的中间部在所述基底上的正投影，所述第三导电连接部73的第三部分733在所述基底上的正投影，所述第二导电连接部72包括的中间部在所述基底上的正投影，以及所述两个第四导电连接部74中的另一个包括的中间部在所述基底上的正投影，紧凑的靠在一 起，并沿所述第二方向依次排列，能够在满足连接需求的同时，有效缩小所述导电连接结构占用的布局空间。
如图10、图11和图12所示，在一些实施例中，所述子像素驱动电路包括存储电容，所述存储电容包括沿垂直于所述基底的方向相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间；
所述第四信号线图形84包括电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，所述第二极板与所述电源信号线图形901耦接；
所述第二导电连接层包括一个第四导电连接部74，所述第四导电连接部74分别耦接对应的所述子像素组中各子像素包括的所述第二极板。
具体的，所述子像素驱动电路包括驱动晶体管和存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间，示例性的，所述第一极板复用为所述驱动晶体管的栅极。示例性的，所述第一极板采用所述显示面板中的第一栅金属层制作，所述第二极板采用所述显示面板中的第二栅金属层制作。
所述第四信号线图形84包括电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，在同一子像素中，所述第二极板在所述基底上的正投影与所述电源信号线图形901在所述基底上的正投影形成交叠区域，在该交叠区域，所述电源信号线图形901通过过孔与所述第二极板耦接。示例性的，所述电源信号线图形901可采用显示面板中的第一源漏金属层制作。示例性的，沿第二方向位于同一列子像素中的各电源信号线图形901依次耦接，可形成为一体结构。
所述第二导电连接层可包括一个第四导电连接部74，示例性的，所述第四导电连接部74采用显示面板中的第一源漏金属层制作。所述第四导电连接部74在所述基底上的正投影与对应的所述第二极板在所述基底上的正投影具有交叠区域，所述第四导电连接部74通过设置在该交叠区域的过孔与对应的所述第二极板耦接。
上述实施例提供的显示面板中，通过设置所述第二极板与所述电源信号 线图形901耦接，以及所述第四导电连接部74分别耦接对应的所述子像素组中各子像素包括的所述第二极板；实现了所述第四导电连接部74与对应的所述子像素组中各子像素包括的电源信号线图形901耦接。
如图10和图11所示，在一些实施例中，所述第五信号线图形85包括沿所述第二方向排列的两个初始化信号线图形，所述第三导电连接层75分别耦接对应的所述子像素组中各子像素包括的所述初始化信号线图形。
具体的，所述初始化信号线图形的至少部分沿第一方向延伸，所述初始化信号线图形用于传输初始化信号，该初始化信号为具有稳定电位的直流信号。
示例性的，所述第三导电连接层75与所述初始化信号线图形形成为一体结构。这种设置方式使得所述第三导电连接层75与所述初始化信号线图形能够在依次构图工艺中同时形成，且能够实现直接耦接。
上述设置所述第三导电连接层75分别耦接对应的所述子像素组中各子像素包括的所述初始化信号线图形，使得所述第三导电连接层75能够同时耦接对应的子像素组中包括的四个初始化信号线图形。这种设置方式使得所述第三导电连接层75具有与所述初始化信号线图形相同的稳定电位，在利用大面积的第三导电连接层75来遮挡相邻导电连接部之间的间隙时，能够更好的保证显示面板工作的稳定性。
如图10所示，在一些实施例中，可设置所述第四导电连接部74在所述基底上的正投影，位于所述第一导电连接部71在所述基底上的正投影与所述第二导电连接部72在所述基底上的正投影之间；所述第三导电连接部73在所述基底上的正投影与所述第二导电连接部72在所述基底上的正投影交叠。
具体的，在所述子像素中，所述第二极板在所述基底上的正投影，位于所述第一复位信号线图形905在所述基底上的正投影，与所述发光控制信号线图形903在所述基底上的正投影之间，上述设置所述第四导电连接部74在所述基底上的正投影，位于所述第一导电连接部71在所述基底上的正投影与所述第二导电连接部72在所述基底上的正投影之间，更有利于降低所述第一导电连接部71、所述第二导电连接部72和所述第四导电连接部74的布局难 度。
上述设置所述第三导电连接部73在所述基底上的正投影与所述第二导电连接部72在所述基底上的正投影交叠，使得所述第二导电连接部72与所述第三导电部共同占用的布局空间缩小，从而更好的提升了所述显示面板在所述第二像素区的透光率。
在一些实施例中，可设置所述第四导电连接部74在所述基底上的正投影，分别与所述第一导电连接部71在所述基底上的正投影和所述第二导电连接部72在所述基底上的正投影交叠。
上述设置所述第四导电连接部74在所述基底上的正投影，分别与所述第一导电连接部71在所述基底上的正投影和所述第二导电连接部72在所述基底上的正投影交叠，使得所述第一导电连接部71、所述第二导电连接部72和所述第四导电部共同占用的布局空间缩小，从而更好的提升了所述显示面板在所述第二像素区的透光率。
在一些实施例中，所述第四导电连接部74在所述基底上的正投影，与所述第一导电连接部71在所述基底上的正投影交叠；所述第三导电连接部73在所述基底上的正投影与所述第二导电连接部72在所述基底上的正投影交叠。
上述设置所述第四导电连接部74在所述基底上的正投影，与所述第一导电连接部71在所述基底上的正投影交叠，所述第三导电连接部73在所述基底上的正投影与所述第二导电连接部72在所述基底上的正投影交叠，使得所述第一导电连接部71、所述第二导电连接部72、第三导电连接部73和所述第四导电部共同占用的布局空间缩小，从而更好的提升了所述显示面板在所述第二像素区的透光率。
如图6和图9所示，在一些实施例中，所述第一导电连接部71、所述第二导电连接部72、所述第四导电连接部74均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
所述第一导电连接部71的中间部713与所述第二导电连接部72的中间部723之间具有所述第一间隙，所述第一间隙沿垂直于所述第一方向的方向上具有第一宽度，所述第一宽度为满足所述第一导电连接部71的中间部713与所述第二导电连接部72的中间部723绝缘条件的最小宽度；
所述第三导电连接部73的中间部与所述第四导电连接部74的中间部743之间具有所述第二间隙，所述第二间隙沿垂直于所述第一方向的方向上具有第二宽度，所述第二宽度为满足所述第三导电连接部73的中间部与所述第四导电连接部74的中间部743绝缘条件的最小宽度。
具体的，由于所述第一导电连接部71与所述第二导电连接部72同层设置，且对应连接了用于传输不同信号的信号线图形，因此，所述第一导电连接部71与所述第二导电连接部72之间需要间隔设置，以避免所述第一导电连接部71与所述第二导电连接部72之间发生短路。
同样的，由于所述第三导电连接部73与所述第四导电连接部74同层设置，且对应连接了用于传输不同信号的信号线图形，因此，所述第三导电连接部73与所述第四导电连接部74之间需要间隔设置，以避免所述第三导电连接部73与所述第四导电连接部74之间发生短路。
上述设置所述第一导电连接部71的中间部713与所述第二导电连接部72的中间部723之间具有所述第一间隙，以及所述第三导电连接部73的中间部与所述第四导电连接部74的中间部743之间具有所述第二间隙，使得所述第一导电连接部71、所述第二导电连接部72、第三导电连接部73和所述第四导电连接部74能够紧凑布局，从而更好的提升了所述显示面板在所述第二像素区的透光率。
在一些实施例中，可设置所述第三导电连接层75在所述基底上的正投影与所述第一导电连接部71在所述基底上的正投影，所述第二导电连接部72在所述基底上的正投影，所述第三导电连接部73在所述基底上的正投影，以及所述第四导电连接部74在所述基底上的正投影均交叠。
上述设置方式使得所述第一导电连接部71、所述第二导电连接部72、第三导电连接部73、所述第四导电连接部74和第三导电连接层75能够紧凑布 局，从而更好的提升了所述显示面板在所述第二像素区的透光率。
如图4所示，在一些实施例中，所述第一导电连接部71、所述第二导电连接部72、所述第四导电连接部74均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
所述第四导电连接部74包括的中间部在所述基底上的正投影，所述第一导电连接部71包括的中间部在所述基底上的正投影，所述第三导电连接部73的第三部分733在所述基底上的正投影，所述第二导电连接部72包括的中间部在所述基底上的正投影，均位于所述第三导电连接层75在所述基底上的正投影的内部。
上述设置方式使得所述第一导电连接部71、所述第二导电连接部72、第三导电连接部73、所述第四导电连接部74和第三导电连接层75能够紧凑布局，从而更好的提升了所述显示面板在所述第二像素区的透光率。
值得注意，除了通过设置间隙宽度，以及不同导电连接部之间的交叠关系来缩小所述导电连接结构的布局空间，也可以在满足功能需求的情况下，将所述第一导电连接部71、所述第二导电连接部72、所述第三导电连接部73、所述第四导电连接部74的线宽，以及第三导电连接层75的面积尽量缩小，从而更好的提升了所述显示面板在所述第二像素区的透光率。
在一些实施例中，可设置所述子像素还包括数据线图形908，所述数据线图形908沿第二方向延伸；所述子像素驱动电路包括：晶体管结构和存储电容，所述存储电容包括相对设置的第一极板和第二极板；所述第一导电连接层与所述晶体管结构的栅极同层同材料设置；所述第二导电连接层与所述数据线图形908同层同材料设置；所述第三导电连接层75与所述第二极板同层同材料设置。
上述将所述第一导电连接层与所述晶体管结构的栅极同层同材料设置，使得所述第一导电连接层与所述晶体管结构的栅极能够在同一次构图工艺中形成；将所述第二导电连接层与所述数据线图形908同层同材料设置，使得 所述第二导电连接层与所述数据线图形908能够在同一次构图工艺中形成；将所述第三导电连接层75与所述第二极板同层同材料设置，使得所述第三导电连接层75与所述第二极板能够在同一次构图工艺中形成；从而更好的简化了显示面板的制作工艺流程，节约了制作成本。
在一些实施例中，可设置所述子像素还包括数据线图形908，所述数据线图形908沿第二方向延伸；所述子像素驱动电路包括：晶体管结构和存储电容，所述存储电容包括相对设置的第一极板和第二极板；所述第一导电连接层与所述第二极板同层同材料设置；所述第二导电连接层与所述数据线图形908同层同材料设置；所述第三导电连接层75与所述晶体管结构的栅极同层同材料设置。
上述将所述第一导电连接层与所述第二极板同层同材料设置，使得所述第一导电连接层与所述第二极板能够在同一次构图工艺中形成；将所述第二导电连接层与所述数据线图形908同层同材料设置，使得所述第二导电连接层与所述数据线图形908能够在同一次构图工艺中形成；将所述第三导电连接层75与所述晶体管结构的栅极同层同材料设置，使得所述第三导电连接层75与所述晶体管结构的栅极能够在同一次构图工艺中形成；从而更好的简化了显示面板的制作工艺流程，节约了制作成本。
在一些实施例中，所述第一信号线图形包括第一复位信号线图形，所述第二信号线图形包括发光控制信号线图形，所述第三信号线图形包括栅线图形和第二复位信号线图形；所述子像素还包括电源信号线图形，数据线图形，第一初始化信号线图形和第二初始化信号线图形；
所述子像素驱动电路均包括：存储电容，驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与所述第一复位信号线图形耦接，所述第二晶体 管的第一极与所述第一初始化信号线图形耦接，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与显示面板中对应的所述发光元件耦接；
所述第七晶体管的第二极与对应的所述发光元件耦接，所述第七晶体管的栅极与所述第二复位信号线图形耦接，所述第七晶体管的第一极与所述第二初始化信号线图形耦接。
具体的，如图1、图4和图10所示，所述显示面板中包括的多个子像素驱动电路能够划分为沿所述第二方向依次排列的多行子像素驱动电路，以及沿所述第一方向依次排列的多列子像素驱动电路，属于同一个像素单元的子像素驱动电路对应的所述第一初始化信号线图形904依次电连接，形成为一体结构；属于同一个像素单元的子像素驱动电路对应的所述第二初始化信号线图形904'依次电连接，形成为一体结构；属于同一个像素单元的子像素驱动电路对应的所述栅线图形902依次电连接，形成为一体结构；属于同一个像素单元的子像素驱动电路对应的所述发光控制信号线图形903依次电连接，形成为一体结构；属于同一个像素单元的子像素驱动电路对应的所述第一复位信号线图形905依次电连接，形成为一体结构；属于同一个像素单元的子像素驱动电路对应的所述第二复位信号线图形905'依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述数据线图形908依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述电源信号线图形901依次电连接，形成为一体结构。
如图1、图4和图10所示，以一个子像素驱动电路为例，该子像素驱动 电路包括7个薄膜晶体管和1个电容。该子像素驱动电路包括的各晶体管均采用P型晶体管，其中，第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形902耦接，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与所述第一复位信号线图形905耦接，第二晶体管T2的源极S2与所述第一初始化信号线图形904耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述栅线图形902耦接，第四晶体管T4的源极S4与数据线图形908耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与发光控制信号线图形903耦接，第五晶体管T5的源极S5与电源信号线图形901耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形903耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与显示面板中对应的发光元件耦接。
第七晶体管T7的栅极207g与所述第二复位信号线图形905'耦接，第七晶体管T7的漏极D7与发光元件耦接，第七晶体管T7的源极S7与所述第二初始化信号线图形904'耦接。
存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2与所述电源信号线图形901耦接。
如图2和图3所示，上述结构的显示子像素驱动电路在工作时，每个工作周期均包括复位时段P1、写入补偿时段P2和发光时段P3。图3中，E1代表当前子像素中的发光控制信号线图形903上传输的发光控制信号，R1代表当前子像素中的第一复位信号线图形905上传输的复位信号，D1代表当前子像素中的数据线图形908上传输的数据信号，G1代表当前子像素中的栅线图形902上传输的栅极扫描信号，R1'代表当前子像素中的第二复位信号线图形 905'上传输的复位信号。显示面板功能工作时，按照自下向上的方向逐行扫描。
在所述第一复位时段P1，所述第一复位信号线图形905输入的复位信号处于有效电平，第二晶体管T2导通，将由所述第一初始化信号线图形904’输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述第一复位信号线图形905输入的复位信号处于非有效电平，第二晶体管T2截止，栅线图形902输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，数据线图形908写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在写入补偿时段P2，所述第二复位信号线图形905'输入的复位信号处于有效电平，控制第七晶体管T7导通，由所述第二初始化信号线图形904'传输的初始化信号输入至发光元件EL的阳极，控制发光元件EL不发光。
在发光时段P3，发光控制信号线图形903写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形901传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
如图4～7所示，在制作上述显示子像素驱动电路时，显示子像素驱动电路对应的各膜层的布局如下：
沿远离基底的方向上依次层叠设置的有源膜层、栅极绝缘层、第一栅金 属层、第一层间绝缘层、第二栅金属层、第二层间绝缘层、第一源漏金属层和第三层间绝缘层。
如图5所示，有源膜层用于形成显示子像素驱动电路中各晶体管的沟道区(如：101pg～107pg)，源极形成区和漏极形成区，源极形成区和漏极形成区对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
另外，值得注意，所述源极形成区和漏极形成区对应的有源膜层可直接作为对应的源极(如：S1～S7)和漏极(如：D1～D7)，或者，也可以采用金属材料制作与所述源极形成区接触的源极，采用金属材料制作与所述漏极形成区接触的漏极。
如图6所示，第一栅金属层用于形成子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及显示面板包括的栅线图形902、发光控制信号线图形903、复位信号线图形905等结构，每个子像素驱动电路中的第三晶体管T3的栅极203g均复用为该子像素驱动电路中的第二存储电容Cst的第一极板Cst1。
如图7所示，第二栅金属层用于形成第二存储电容Cst的第二极板Cst2，以及显示基板包括的第一初始化信号线图形904和第二初始化信号线图形904'。
如图8所示，第一源漏金属层用于形成显示面板包括的数据线图形908、电源信号线图形901和一些导电连接部。
更详细地说，请继续参阅图4～5，第一晶体管T1的栅极201g覆盖第一沟道区101pg，第二晶体管T2的栅极202g覆盖第二沟道区102pg，第三晶体管T3的栅极203g覆盖第三沟道区103pg，第四晶体管T4的栅极204g覆盖第四沟道区104pg，第五晶体管T5的栅极205g覆盖第五沟道区105pg，第六晶体管T6的栅极206g覆盖第六沟道区106pg，第七晶体管T7的栅极207g覆盖第七沟道区107pg。第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储电容Cst的第二极板Cst2与电源信号线图形901耦接。
另外，如图4所示，本公开提供的显示面板中，在第二方向(如Y方向)上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g)的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为沿第二方向相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的下侧，驱动晶体管的栅极的第二侧可以为驱动晶体管的栅极的上侧。所述下侧，例如显示面板的用于绑定IC的一侧为显示面板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在第一方向(如X方向)上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第一晶体管T1的栅极201g和第六晶体管T6的栅极206g均位于驱动晶体管的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为沿第一方向相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的右侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的左侧。所述左侧和右侧，例如在同一子像素中，数据线图形908位于电源信号线图形901右侧，电源信号线图形901位于数据线图形908左侧。
本公开实施例还提供了一种显示装置，所述显示装置包括上述实施例提供的显示面板。
上述实施例提供的显示面板中，在子像素组包括的两个子像素之间设置了导电连接结构，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层75；所述第一导电连接层和所述第二导电连接层用于将子像素组中各子像素包括的用于传输相同信号的信号线图形耦接在一起；所述第三导电连接层75用于将子像素组中各子像素包括的用于传输具有固定电位的第五信号的第五信号线图形85耦接在一起；因此，上述实施例提供的显示面板通过设置所述导电连接结构，实现了将所述子像素组中各 子像素包括的用于传输相同信号的信号线图形对应耦接在一起。
另外，上述实施例提供的显示面板中，通过设置所述第三导电连接层75在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影和所述第二间隙在所述基底上的正投影，使得所述第三导电连接层75能够覆盖所述子像素组中位于两个子像素之间相邻导电连接部之间的缝隙，减少了缝隙处产生的漏光现象，从而避免了光线透过该缝隙时产生的干扰性衍射、眩光等问题，更好的保证了显示面板中摄像头在拍照时的成像质量。
此外，上述实施例提供的显示面板中，将所述第三导电连接层75与用于传输具有固定电位的第五信号的第五信号线图形85耦接，使得所述第三导电连接层75具有稳定的电位，不会对所述第五信号线图形85的RC(阻容)loading(负载)产生太大影响。
因此，本公开实施例提供的显示装置在包括上述显示面板时，同样具有上述有意效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件等。
本公开实施例还提供了一种显示面板的制作方法，用于制作上述实施例提供的显示面板，所述显示面板包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述制作方法包括：
在所述第二像素区制作阵列分布的多个像素单元和多个导电连接结构；
所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及分别与该子像素驱动电路耦接的第一信号线图形至第五信号线图形；
所述多个导电连接结构与所述子像素组一一对应，所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层；
所述第一导电连接层包括第一导电连接部和第二导电连接部，第一导电 连接部和第二导电连接部之间具有第一间隙；所述第一导电连接部分别耦接对应的所述子像素组中各子像素包括的第一信号线图形，所述第二导电连接部分别耦接对应的所述子像素组中各子像素包括的第二信号线图形；
所述第二导电连接层包括第三导电连接部和至少一个第四导电连接部，相邻的所述第三导电连接部和所述第四导电连接部之间具有第二间隙；所述第三导电连接部分别耦接对应的所述子像素组中各子像素包括的第三信号线图形，所述至少一个第四导电连接部与对应的所述子像素组中每个子像素包括的第四信号线图形均一一对应，所述第四导电连接部分别与对应的第四信号线图形耦接；
所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的第五信号线图形，所述第五信号线图形用于传输具有固定电位的第五信号，所述第三导电连接层在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
采用本公开实施例提供的制作方法制作的显示面板中，在子像素组包括的两个子像素之间设置了导电连接结构，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层75；所述第一导电连接层和所述第二导电连接层用于将子像素组中各子像素包括的用于传输相同信号的信号线图形耦接在一起；所述第三导电连接层75用于将子像素组中各子像素包括的用于传输具有固定电位的第五信号的第五信号线图形85耦接在一起；因此，采用本公开实施例提供的制作方法制作的显示面板通过设置所述导电连接结构，实现了将所述子像素组中各子像素包括的用于传输相同信号的信号线图形对应耦接在一起。
另外，采用本公开实施例提供的制作方法制作的显示面板中，通过设置所述第三导电连接层75在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分，使得所述第三导电连接层75能够覆盖所述子像素组中位于两个子像素之间相邻导电连接部之间的缝隙，减少了缝隙处产生的漏光现象，从 而避免了光线透过该缝隙时产生的干扰性衍射、眩光等问题，更好的保证了显示面板中摄像头在拍照时的成像质量。
此外，采用本公开实施例提供的制作方法制作的显示面板中，将所述第三导电连接层75与用于传输具有固定电位的第五信号的第五信号线图形85耦接，使得所述第三导电连接层75具有稳定的电位，不会对所述第五信号线图形85的RC(阻容)loading(负载)产生太大影响。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示面板，包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述第二像素区包括阵列分布的多个像素单元，所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及分别与该子像素驱动电路耦接的第一信号线图形至第五信号线图形；
    所述显示面板还包括：与所述子像素组一一对应的多个导电连接结构，所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层；
    所述第一导电连接层包括第一导电连接部和第二导电连接部，第一导电连接部和第二导电连接部之间具有第一间隙；所述第一导电连接部分别耦接对应的所述子像素组中各子像素包括的第一信号线图形，所述第二导电连接部分别耦接对应的所述子像素组中各子像素包括的第二信号线图形；
    所述第二导电连接层包括第三导电连接部和至少一个第四导电连接部，相邻的所述第三导电连接部和所述第四导电连接部之间具有第二间隙；所述第三导电连接部分别耦接对应的所述子像素组中各子像素包括的第三信号线图形，所述至少一个第四导电连接部与对应的所述子像素组中每个子像素包括的第四信号线图形均一一对应，所述第四导电连接部分别与对应的第四信号线图形耦接；
    所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的第五信号线图形，所述第五信号线图形用于传输具有固定电位的第五信号，所述第三导电连接层在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
  2. 根据权利要求1所述的显示面板，其中，所述第一信号线图形包括第一复位信号线图形，所述第一复位信号线图形的至少部分沿所述第一方向延伸；所述第二信号线图形包括发光控制信号线图形，所述发光控制信号线图形的至少部分沿所述第一方向延伸。
  3. 根据权利要求1所述的显示面板，其中，所述第三信号线图形包括沿第二方向排列的栅线图形和第二复位信号线图形，所述栅线图形的至少部分和所述第二复位信号线图形的至少部分均沿第一方向延伸，所述栅线图形和所述第二复位信号线图形用于传输相同的第三信号；
    所述第三导电连接部包括第一部分、第二部分和第三部分，所述第一部分和所述第二部分沿第二方向延伸，所述第三部分沿第一方向延伸，所述第二方向与所述第一方向相交；所述第一部分分别耦接所述子像素组中一个子像素包括的所述栅线图形和所述第二复位信号线图形，所述第二部分分别耦接所述子像素组中另一个子像素包括的所述栅线图形和所述第二复位信号线图形，所述第三部分分别与所述第一部分和所述第二部分耦接。
  4. 根据权利要求1所述的显示面板，其中，所述第四信号线图形包括沿第二方向排列的两个初始化信号线图形，所述第二方向与所述第一方向相交，所述第二导电连接层包括两个第四导电连接部，所述两个第四导电连接部与对应的所述子像素组中每个子像素包括的所述初始化信号线图形均一一对应，每个所述第四导电连接部与对应的第四信号线图形分别耦接；
    所述第三导电连接部在所述基底上的正投影的至少部分，位于所述两个第四导电连接部在所述基底上的正投影之间。
  5. 根据权利要求4所述的显示面板，其中，所述子像素驱动电路包括存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间；
    所述第五信号线图形包括电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，在同一子像素中所述第二极板与所述电源信号线图形耦接；
    所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的所 述第二极板。
  6. 根据权利要求4所述的显示面板，其中，所述第一导电连接部在所述基底上的正投影，分别与所述第三导电连接部在所述基底上的正投影，以及所述两个第四导电连接部中的一个在所述基底上的正投影交叠；和/或，
    所述第二导电连接部在所述基底上的正投影，分别与所述第三导电连接部在所述基底上的正投影，以及所述两个第四导电连接部中的另一个在所述基底上的正投影交叠。
  7. 根据权利要求4所述的显示面板，其中，所述第一导电连接部、所述第二导电连接部、所述第四导电连接部均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
    所述两个第四导电连接部中的一个包括的中间部在所述基底上的正投影，所述第一导电连接部包括的中间部在所述基底上的正投影，所述第三导电连接部的第三部分在所述基底上的正投影，所述第二导电连接部包括的中间部在所述基底上的正投影，以及所述两个第四导电连接部中的另一个包括的中间部在所述基底上的正投影，沿所述第二方向依次排列。
  8. 根据权利要求1所述的显示面板，其中，所述子像素驱动电路包括存储电容，所述存储电容包括沿垂直于所述基底的方向相对设置的第一极板和第二极板，所述第一极板位于所述基底与所述第二极板之间；
    所述第四信号线图形包括电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述第二极板与所述电源信号线图形耦接；
    所述第二导电连接层包括一个第四导电连接部，所述第四导电连接部分别耦接对应的所述子像素组中各子像素包括的所述第二极板。
  9. 根据权利要求8所述的显示面板，其中，所述第五信号线图形包括沿所述第二方向排列的两个初始化信号线图形，所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的所述初始化信号线图形。
  10. 根据权利要求8所述的显示面板，其中，所述第四导电连接部在所 述基底上的正投影，位于所述第一导电连接部在所述基底上的正投影与所述第二导电连接部在所述基底上的正投影之间；所述第三导电连接部在所述基底上的正投影与所述第二导电连接部在所述基底上的正投影交叠。
  11. 根据权利要求8所述的显示面板，其中，所述第四导电连接部在所述基底上的正投影，分别与所述第一导电连接部在所述基底上的正投影和所述第二导电连接部在所述基底上的正投影交叠。
  12. 根据权利要求8所述的显示面板，其中，所述第四导电连接部在所述基底上的正投影，与所述第一导电连接部在所述基底上的正投影交叠；所述第三导电连接部在所述基底上的正投影与所述第二导电连接部在所述基底上的正投影交叠。
  13. 根据权利要求1所述的显示面板，其中，所述第一导电连接部、所述第二导电连接部、所述第四导电连接部均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
    所述第一导电连接部的中间部与所述第二导电连接部的中间部之间具有所述第一间隙，所述第一间隙沿垂直于所述第一方向的方向上具有第一宽度，所述第一宽度为满足所述第一导电连接部的中间部与所述第二导电连接部的中间部绝缘条件的最小宽度；
    所述第三导电连接部的中间部与所述第四导电连接部的中间部之间具有所述第二间隙，所述第二间隙沿垂直于所述第一方向的方向上具有第二宽度，所述第二宽度为满足所述第三导电连接部的中间部与所述第四导电连接部的中间部绝缘条件的最小宽度。
  14. 根据权利要求1所述的显示面板，其中，
    所述第三导电连接层在所述基底上的正投影与所述第一导电连接部在所述基底上的正投影，所述第二导电连接部在所述基底上的正投影，所述第三导电连接部在所述基底上的正投影，以及所述第四导电连接部在所述基底上的正投影均交叠。
  15. 根据权利要求14所述的显示面板，其中，所述第一导电连接部、所述第二导电连接部、所述第四导电连接部均包括第一边部和第二边部，以及位于所述第一边部和第二边部之间的中间部；所述中间部沿第一方向延伸，所述第一边部包括沿第一方向延伸的部分和沿第二方向延伸的部分，所述第二边部包括沿第一方向延伸的部分和沿第二方向延伸的部分；
    所述第四导电连接部包括的中间部在所述基底上的正投影，所述第一导电连接部包括的中间部在所述基底上的正投影，所述第三导电连接部的第三部分在所述基底上的正投影，所述第二导电连接部包括的中间部在所述基底上的正投影，均位于所述第三导电连接层在所述基底上的正投影的内部。
  16. 根据权利要求1所述的显示面板，其中，所述子像素还包括数据线图形，所述数据线图形沿第二方向延伸；所述子像素驱动电路包括：晶体管结构和存储电容，所述存储电容包括相对设置的第一极板和第二极板；
    所述第一导电连接层与所述晶体管结构的栅极同层同材料设置；
    所述第二导电连接层与所述数据线图形同层同材料设置；
    所述第三导电连接层与所述第二极板同层同材料设置。
  17. 根据权利要求1所述的显示面板，其中，所述第一信号线图形包括第一复位信号线图形，所述第二信号线图形包括发光控制信号线图形，所述第三信号线图形包括栅线图形和第二复位信号线图形；所述子像素还包括电源信号线图形，数据线图形，第一初始化信号线图形和第二初始化信号线图形；
    所述子像素驱动电路均包括：存储电容，驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
    所述第一晶体管的栅极与所述栅线图形耦接；
    所述第二晶体管的栅极与所述第一复位信号线图形耦接，所述第二晶体管的第一极与所述第一初始化信号线图形耦接，所述第二晶体管的第二极与 所述驱动晶体管的栅极耦接；
    所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
    所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与显示面板中对应的所述发光元件耦接；
    所述第七晶体管的第二极与对应的所述发光元件耦接，所述第七晶体管的栅极与所述第二复位信号线图形耦接，所述第七晶体管的第一极与所述第二初始化信号线图形耦接。
  18. 一种显示装置，所述显示装置包括如权利要求1～17中任一项所述的显示面板。
  19. 一种显示面板的制作方法，所述显示面板包括第一像素区和第二像素区，所述第二像素区的像素密度低于所述第一像素区的像素密度；所述制作方法包括：
    在所述第二像素区制作阵列分布的多个像素单元和多个导电连接结构；
    所述多个像素单元形成多行像素单元行，每一行像素单元行均包括沿第一方向排布的多个像素单元；每个像素单元均包括沿第一方向排列的多个子像素，在同一行像素单元行中，相邻的两个像素单元中最靠近的两个子像素形成子像素组；所述子像素包括：子像素驱动电路，以及分别与该子像素驱动电路耦接的第一信号线图形至第五信号线图形；
    所述多个导电连接结构与所述子像素组一一对应，所述导电连接结构位于对应的子像素组包括的两个子像素之间，所述导电连接结构包括：异层设置的第一导电连接层、第二导电连接层和第三导电连接层；
    所述第一导电连接层包括第一导电连接部和第二导电连接部，第一导电连接部和第二导电连接部之间具有第一间隙；所述第一导电连接部分别耦接 对应的所述子像素组中各子像素包括的第一信号线图形，所述第二导电连接部分别耦接对应的所述子像素组中各子像素包括的第二信号线图形；
    所述第二导电连接层包括第三导电连接部和至少一个第四导电连接部，相邻的所述第三导电连接部和所述第四导电连接部之间具有第二间隙；所述第三导电连接部分别耦接对应的所述子像素组中各子像素包括的第三信号线图形，所述至少一个第四导电连接部与对应的所述子像素组中每个子像素包括的第四信号线图形均一一对应，所述第四导电连接部分别与对应的第四信号线图形耦接；
    所述第三导电连接层分别耦接对应的所述子像素组中各子像素包括的第五信号线图形，所述第五信号线图形用于传输具有固定电位的第五信号，所述第三导电连接层在所述显示面板的基底上的正投影，覆盖所述第一间隙在所述基底上的正投影的至少部分和所述第二间隙在所述基底上的正投影的至少部分。
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