WO2021078104A1 - 透明oled显示面板、显示装置和制备方法 - Google Patents

透明oled显示面板、显示装置和制备方法 Download PDF

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Publication number
WO2021078104A1
WO2021078104A1 PCT/CN2020/121945 CN2020121945W WO2021078104A1 WO 2021078104 A1 WO2021078104 A1 WO 2021078104A1 CN 2020121945 W CN2020121945 W CN 2020121945W WO 2021078104 A1 WO2021078104 A1 WO 2021078104A1
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Prior art keywords
sub
pixels
pixel
display panel
thin film
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PCT/CN2020/121945
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English (en)
French (fr)
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李蒙
李永谦
孟松
袁粲
袁志东
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/416,498 priority Critical patent/US12075666B2/en
Publication of WO2021078104A1 publication Critical patent/WO2021078104A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a transparent OLED display panel, a display device and a manufacturing method.
  • Transparent organic light-emitting diode Organic Light-Emitting Diode, OLED
  • OLED Organic Light-Emitting Diode
  • the embodiments of the present disclosure provide a transparent OLED display panel, a display device, and a manufacturing method.
  • embodiments of the present disclosure provide a transparent OLED display panel having a plurality of transparent areas and a plurality of display areas, the plurality of transparent areas and the plurality of display areas are alternately arranged in a first direction;
  • the transparent OLED display panel includes a plurality of pixels and a plurality of data lines, the plurality of pixels are located in the display area, a plurality of pixels located in the same display area are arranged in a second direction, and the data lines are arranged along the The first direction extends, and the first direction intersects the second direction;
  • Each of the pixels includes a plurality of sub-pixels, the sub-pixels located in the same display area include a row of first sub-pixels and a row of second sub-pixels, and the row of first sub-pixels includes A plurality of first sub-pixels arranged in a second direction, the row of second sub-pixels includes a plurality of second sub-pixels arranged in the second direction, and the pixels at least include adjacent ones in the first direction.
  • one of the first sub-pixels and one of the second sub-pixels that are adjacent in the first direction is connected to the same data line, and the first sub-pixels that are different The connected data lines are different.
  • each of the display areas includes a plurality of sub-pixel groups arranged along the second direction, each of the sub-pixel groups includes two pairs of sub-pixels adjacent in the second direction, and each sub-pixel The pair includes a first sub-pixel and a second sub-pixel that are adjacent in the first direction, and in each of the sub-pixel groups, the two data lines connected by the two sub-pixel pairs are located in the Between the two sub-pixel pairs.
  • the pixel includes four of the sub-pixels, and the sub-pixels in each of the sub-pixel groups are from the same pixel.
  • the pixel includes three of the sub-pixels, and the sub-pixels in each of the sub-pixel groups come from two adjacent pixels.
  • the transparent OLED display panel further includes a plurality of gate lines extending along the second direction, and each row of the first sub-pixel and each row of the second sub-pixel is connected to at least one The gate line connection.
  • the first sub-pixels in the row of first sub-pixels are respectively connected to two gate lines of the plurality of gate lines, and the first sub-pixels in the row of first sub-pixels are located at the two connected gate lines.
  • the second sub-pixels of the row of second sub-pixels are respectively connected to the other two of the plurality of gate lines, and the row of second sub-pixels are located in the two connected gates Between the lines.
  • the transparent OLED display panel further includes a plurality of power lines extending along the first direction, and the first sub-pixel and the second sub-pixel in each sub-pixel group are the same The power cord is connected.
  • the power line connected to the first sub-pixel group is located between the two data lines connected to the first sub-pixel group, and the first sub-pixel group is any of the plurality of sub-pixel groups One.
  • the transparent OLED display panel further includes a plurality of sensing lines extending along the first direction, and the first sub-pixel and the second sub-pixel in each sub-pixel group Connect with the same sensing line.
  • the sensing line connected to the second sub-pixel group is located between the two data lines connected to the second sub-pixel group, and the second sub-pixel group is among the plurality of sub-pixel groups Any one of.
  • the sub-pixel includes a first thin film transistor, a second thin film transistor, a capacitor, and an organic light emitting diode, wherein the gate of the first thin film transistor is electrically connected to the corresponding gate line, and the first The source of the thin film transistor is electrically connected to the corresponding data line, the drain of the first thin film transistor is electrically connected to the gate of the second thin film transistor and one end of the capacitor; The drain is electrically connected to the corresponding power line, the source of the second thin film transistor is electrically connected to the anode of the organic light emitting diode; the anode of the organic light emitting diode is electrically connected to the other end of the capacitor.
  • each of the sub-pixels further includes a third thin film transistor, and the gates of the third thin film transistors of the sub-pixels in the same row are connected to the same gate line, and for any row of sub-pixels, the third thin film transistor The transistor and the first thin film transistor are connected to different gate lines; the drain of the third thin film transistor is electrically connected to the other end of the capacitor and the source of the second thin film transistor, and the third thin film transistor The source of is electrically connected to the sensing line.
  • the sub-pixel includes an active layer, a gate insulating layer, a first electrode layer, an interlayer insulating layer, a second electrode layer, a passivation layer, and an anode metal layer that are sequentially stacked on a base substrate.
  • the anode metal layer and the second electrode layer are connected by a via hole, and the first electrode layer is isolated from the active layer by the gate insulating layer.
  • the source of the second thin film transistor is located in the active layer
  • the drain of the third thin film transistor is located in the active layer
  • each of the sub-pixels further includes at least one of a planarization layer and a buffer layer, the planarization layer is located between the passivation layer and the anode metal layer, and the buffer layer is located on the Between the substrate and the active layer.
  • the display panel in the transparent area includes a base substrate, a gate insulating layer, an interlayer insulating layer, and a passivation layer that are sequentially stacked.
  • embodiments of the present disclosure provide a display device including the transparent OLED display panel as described in the foregoing first aspect.
  • embodiments of the present disclosure provide a method for manufacturing a transparent OLED display panel, including:
  • a plurality of pixels and a plurality of data lines are formed on the base substrate to obtain a transparent OLED display panel having a plurality of transparent areas and a plurality of display areas, and the plurality of transparent areas and the plurality of display areas are in a first direction Alternate arrangement
  • the multiple pixels are located in the display area, multiple pixels located in the same display area are arranged along a second direction, the data line extends along the first direction, and the first direction is aligned with the second direction.
  • the pixel includes a plurality of sub-pixels, the sub-pixels located in the same display area include a row of first sub-pixels and a row of second sub-pixels, and the row of first sub-pixels includes a row along the second direction A plurality of first sub-pixels arranged in a row, the row of second sub-pixels includes a plurality of second sub-pixels arranged along the second direction, and the pixel includes at least one adjacent pixel in the first direction The first sub-pixel and one of the second sub-pixels;
  • one of the first sub-pixels and one of the second sub-pixels that are adjacent in the first direction is connected to the same data line, and the first sub-pixels that are different The connected data lines are different.
  • FIG. 1 is a schematic structural diagram of a transparent OLED display panel in the related art
  • FIG. 2 is a schematic structural diagram of a transparent OLED display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a partially enlarged structure of a transparent OLED display panel provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of an arrangement of pixels of a transparent OLED display panel provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of the arrangement of pixels of another OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a circuit structure of a group of sub-pixels of a transparent OLED display panel provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a circuit structure of a sub-pixel of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a partial enlarged schematic diagram of a sub-pixel of a transparent OLED display panel provided by an embodiment of the present disclosure
  • Fig. 9 is a schematic cross-sectional structure view taken along line A-A in Fig. 3;
  • FIG. 10 is a schematic diagram of the structure of an active layer in an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the structure of the first electrode layer in an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the structure of the second electrode layer in an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the structure of an anode metal layer in an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a black matrix layer of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic flowchart of a method for manufacturing a transparent OLED display panel provided by an embodiment of the present disclosure
  • FIG. 16 is a driving timing diagram of a display stage provided by an embodiment of the present disclosure.
  • FIG. 17 is a driving timing diagram of a sensing phase provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the structure of a transparent OLED display panel in the related art.
  • a transparent OLED display panel includes a plurality of transparent areas a0 and a plurality of display areas b0 alternately arranged in a first direction, and one adjacent transparent area a0 and one display area b0 constitute one Repeat cycle.
  • one repetition period is shown in FIG. 1.
  • the transparent area a0 and the display area b0 may have multiple repetition periods.
  • the transparent OLED display panel includes a plurality of sub-pixels c0 arranged in an array, each row of sub-pixels c0 is located in a display area b0, and a plurality of consecutive sub-pixels c0 of different colors in each row constitute a pixel d0.
  • Each row of sub-pixels c0 is electrically connected to a gate line e0, and each column of sub-pixels c0 is electrically connected to a data line f0.
  • Each sub-pixel c0 obtains a scan signal through the electrically connected gate line e0, and obtains a data signal through the electrically connected data line f0.
  • the OLED in each sub-pixel c0 is driven to emit light, thereby displaying an image in the display area b0 of the transparent OLED display panel.
  • the scene behind the transparent OLED display panel can be seen through the transparent area a0.
  • the data lines f0 extend along the first direction, and these data lines f0 pass through the transparent area a0 and the display area b0, and need to be shielded by a black matrix (not shown in the figure).
  • the data line f0 and the black matrix located in the transparent area a0 make the light transmission area of the transparent area a0 smaller; at the same time, each data line f0 occupies a certain area of the display area b0, so that the sub-pixel c0 in the display area b0 is arranged The space is reduced, resulting in lower resolution.
  • FIG. 2 is a schematic structural diagram of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • the transparent OLED display panel has a plurality of transparent regions a and a plurality of display regions b, and the plurality of transparent regions a and the plurality of display regions b are alternately arranged in the first direction.
  • the user can see the scene behind the transparent OLED display panel through the transparent area a, and at the same time, can watch the image displayed by the transparent OLED display panel in the display area b.
  • the transparent OLED display panel includes a plurality of pixels 1, and the plurality of pixels 1 are located in a display area b.
  • the plurality of pixels 1 in the same display area b are arranged along a second direction, and the first direction intersects the second direction, such as perpendicular.
  • the first direction is the direction indicated by arrow x in FIG. 2
  • the second direction is the direction indicated by arrow y in FIG. 2.
  • the first direction will be the column direction and the second direction will be the row direction for description.
  • the transparent OLED display panel further includes a plurality of gate lines 2 and a plurality of data lines 3.
  • the plurality of gate lines 2 are parallel to each other and extend in the second direction
  • the plurality of data lines 3 are parallel to each other and extend in the first direction. extend.
  • FIG. 3 is a schematic diagram of a partially enlarged structure of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • each pixel 1 includes a plurality of sub-pixels 11, and the sub-pixels 11 in each display area b are divided into two rows of sub-pixels 11, and the sub-pixels 11 in each row are arranged along the second direction.
  • One of the two rows of sub-pixels 11 is the first sub-pixel 111, and the other row of the two rows of sub-pixels 11 is the second sub-pixel 112.
  • Each pixel 1 includes at least one first sub-pixel 111 and at least one second sub-pixel 112, that is, the sub-pixels 11 included in each pixel 1 are divided into two rows, and the first sub-pixels included in each pixel 1 Among the one sub-pixel 111 and the second sub-pixel 112, at least one first sub-pixel 111 and at least one second sub-pixel 112 are adjacent in the first direction.
  • one first sub-pixel 111 and one second sub-pixel 112 that are adjacent in the first direction are connected to the same data line 3, and different first sub-pixels 111 are connected to different data lines 3 That is, the sub-pixels 11 in the same column are connected to one data line 3, and the sub-pixels 11 in different columns are connected to different data lines 3.
  • the first sub-pixel 111 and the second sub-pixel 112 on the left are connected to the data line 31
  • the first sub-pixel 111 and the second sub-pixel 112 on the right are connected to the data line 32.
  • the number of columns of sub-pixels corresponding to one pixel is reduced. Since the sub-pixels in the same column share one data line, when the number of sub-pixel columns is reduced, the number of data lines used by a pixel is less than the number of sub-pixels it contains. Compared with the number of sub-pixels included in the pixel, the number of data lines used reduces the number of data lines. On the one hand, because the data lines pass through the transparent area and occupy the area of the transparent area, the number of data lines is reduced, which can increase the area of the transparent area, thereby increasing the area ratio of the transparent area in the transparent OLED display panel. On the one hand, the reduction in the number of data lines reduces the area of the display area occupied by the data lines, so that more sub-pixels can be arranged in the same area and the resolution of the transparent OLED display panel is improved.
  • each row of the first sub-pixel 111 and each row of the second sub-pixel 112 are respectively connected to at least one gate line 2, and the first sub-pixel 111 and the second sub-pixel 112 are connected
  • the gate line 2 is different.
  • a row of first sub-pixels 111 is connected to one gate line 2
  • a row of second sub-pixels 112 is connected to another gate line 2.
  • each row of sub-pixels corresponds to two gate lines, and each sub-pixel in each row of sub-pixels is connected to the corresponding two gate lines.
  • the first sub-pixels 111 in a row of first sub-pixels 111 are respectively connected to two gate lines 2 (the first gate line 21 and the second gate line 22), and the first sub-pixels in the row are located at the two connected gate lines 2.
  • the second sub-pixel 112 of the second sub-pixel 112 of the row is connected to the other two gate lines 2 respectively, and the second sub-pixel 112 of the row is located in the two connected gate lines 2 ( Between the third gate line 23 and the fourth gate line 24).
  • FIG. 3 only shows one pixel 1 in each display area b, and the structure of the transparent area a adjacent to the display area b to which the pixel 1 belongs in the first direction. Since the structure shown in FIG. 3 is a repeating unit of the transparent OLED display panel provided by the embodiment of the present disclosure, that is, in the second direction, the transparent OLED display panel includes a plurality of structures shown in FIG. In the direction, the transparent OLED display panel also includes a plurality of structures as shown in FIG. 3, so the embodiment of the present disclosure uses the partial structure of the transparent OLED display panel as shown in FIG. 3 for exemplification.
  • each display area b includes a row of pixels 1.
  • each display area may also include multiple rows of pixels 1 (for example, including There are two rows of pixels 1), and the sub-pixels 11 of each row of pixels 1 are equally divided into two rows.
  • the pixel 1 includes four sub-pixels 11 arranged in a square form, and the four sub-pixels 11 include two first sub-pixels 111 and two second sub-pixels 112 arranged in a second direction.
  • the first first sub-pixel 111 in the first row is adjacent to the first second sub-pixel 112 in the second row and connected to the same first data line 31; the second first sub-pixel in the first row is The sub-pixel 111 is adjacent to the second second sub-pixel 112 in the second row, and is connected to the second data line 32.
  • the multiple transparent areas a and multiple display areas b are alternately arranged in the first direction, so in the first direction, each column of pixels 1 is connected to two data lines 3.
  • each sub-pixel c0 of a different color in a pixel d0 is respectively connected to a data line f0. If a pixel d0 includes four sub-pixels c0, then a pixel d0 needs to be connected to four data lines f0. Since multiple pixels in a column of pixels are connected to the same data line, in the related art, each column of pixels needs to be connected to four data lines. line.
  • the embodiments of the present disclosure reduce the number of data lines. Since the data lines pass through the transparent area in the first direction, the number of data lines is reduced. , The area of the occupied transparent area is also reduced, thereby increasing the area ratio of the transparent area. At the same time, the data lines also pass through the display area, the number of data lines is reduced, and the area occupied by the display area is also reduced. Therefore, more sub-pixels can be arranged on the display panel and the resolution can be improved.
  • each display area b includes a plurality of sub-pixel groups arranged along the second direction
  • each dashed box in FIG. 2 represents a sub-pixel group
  • FIG. 3 shows a sub-pixel group.
  • Each of the sub-pixel groups includes two sub-pixel pairs that are adjacent in the second direction y, and each sub-pixel pair includes a first sub-pixel 111 and a second sub-pixel that are adjacent in the first direction x.
  • each sub-pixel group includes two first sub-pixels 111 adjacent in the second direction y and two second sub-pixels 112 adjacent in the second direction y, each sub-pixel
  • the two data lines 3 connected by the two sub-pixel pairs in the group are located between the two sub-pixel pairs, that is, between two adjacent first sub-pixels 111 and two adjacent second sub-pixels 112 .
  • each display area b in the second direction, the two data lines 3 connected to the two sub-pixel pairs in each sub-pixel group are arranged between the two sub-pixel pairs, so between two adjacent sub-pixel groups There is no data cable.
  • a data line 3 passing through the transparent area a and the display area b between each column of sub-pixels 11 in the embodiment of the present disclosure, there is no data between the transparent areas a corresponding to two adjacent sub-pixel groups.
  • the line passing through increases the area of the entire transparent area a, which is convenient for the user to watch the scene behind the transparent OLED display panel through the transparent area a.
  • FIG. 4 is a schematic diagram of a pixel arrangement of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 4 shows a unit composed of a pixel 1 in a display area b and an adjacent transparent area a in a transparent OLED display panel, which corresponds to the sub-pixel 11 and the transparent area a in FIG. 3.
  • each pixel 1 includes four sub-pixels 11, and the four sub-pixels 11 in each pixel 1 correspond to a sub-pixel group in FIG. 3, that is, each sub-pixel The four sub-pixels 11 in the group belong to the same pixel 1.
  • the four sub-pixels 11 are red (red, R), blue (blue, B), green (green, G), and white (white, W) sub-pixels, respectively.
  • the two first sub-pixels 111 are red and blue sub-pixels, respectively
  • the two second sub-pixels 112 are green and white sub-pixels, respectively.
  • FIG. 5 is a schematic diagram of a pixel arrangement of another OLED display panel provided by an embodiment of the present disclosure.
  • each pixel 1 includes three sub-pixels 11, and the three sub-pixels 11 are arranged in a magenta shape.
  • the four sub-pixels in each group of sub-pixels 11 may include three sub-pixels in one pixel 1 plus one sub-pixel 11 in another pixel 11, that is, four sub-pixels in the group of sub-pixels.
  • the pixel 11 comes from two adjacent pixels 1.
  • the three sub-pixels 11 in one pixel 1 are respectively a blue sub-pixel, a red sub-pixel, and a green sub-pixel.
  • the first row of sub-pixels 11 in red is The sub-pixel 113 and the blue second sub-pixel 114 in the second row of sub-pixels share the first data line 31; the green second sub-pixel 114 in the second row of sub-pixels 11 is the same as the blue sub-pixel in the first row of sub-pixels.
  • the first sub-pixel 113 shares the second data line 32.
  • a pixel d0 in a display area b0 in the related art includes three sub-pixels c0 arranged in sequence, and the three sub-pixels c0 respectively correspond to A data line f0 is used for control. That is, every third of the pixels is controlled by a data line.
  • the number of data lines in the embodiment shown in FIG. 5 is still less than the number of data lines in the related art, so that the transparent area can be increased. a occupies the area of the display panel, and more sub-pixels 11 can be arranged in the display area b to improve the resolution.
  • the pixel 1 includes a red first sub-pixel 113 and a blue and green second sub-pixel 114, or the pixel 1 includes a blue and green first sub-pixel 113 and a red sub-pixel.
  • the second sub-pixel 114 is
  • the transparent OLED display panel further includes a plurality of power lines 4.
  • the power line 4 extends along the first direction and passes through the transparent area a and the display area b.
  • the first sub-pixel 111 and the second sub-pixel 112 in each group of sub-pixels 11 are connected to the same power line 4.
  • the power cord 4 is used to provide power to the OLED in the transparent OLED display panel.
  • Each group of sub-pixels 11 includes two adjacent first sub-pixels 111 and two adjacent second sub-pixels 112, that is, four sub-pixels 11 share one power supply line 4. That is, in each display area b, every two columns of sub-pixels 11 in each pixel 1 are connected to the same power supply line 4.
  • each column of sub-pixels 11 is connected to one power line 4 respectively. Therefore, compared with the related art, the number of power lines 4 in the embodiment of the present disclosure is reduced, which can increase the area ratio of the transparent area a in the display panel. In addition, the number of power lines 4 is reduced, so that the display area occupied by the power lines 4 is reduced. The area of b is reduced, so that more sub-pixels 11 can be arranged in the display area b, and the resolution of the display panel is further improved.
  • the power line 4 is located between two data lines 3 connected to a group of sub-pixels 11.
  • the power line 4 and the two data lines 3 are located in the gap between the two columns of sub-pixels 11. Since the number of data lines 3 is more than the power line 4, the power lines 4 are arranged in the two data lines. Between the lines 3, the two columns of sub-pixels 11 are made close to the two corresponding data lines 3, and there is no need to use jumpers across the power line 4 to connect the data lines 3 to the corresponding sub-pixels 11, which facilitates wiring and improves production efficiency.
  • the transparent OLED display panel further includes a plurality of sensing lines 5 extending along the first direction, and the first sub-pixel 111 and the second sub-pixel 112 in each sub-pixel group are the same as those described above.
  • the sensing line 5 is connected.
  • the sensing line 5 is used for sensing the electrical signal in the connected sub-pixel 11 and transmitting the compensation voltage signal of the external compensation circuit.
  • Each sub-pixel group includes two adjacent first sub-pixels 111 and two adjacent second sub-pixels 112, that is, four sub-pixels 11 share one sensing line 5. It can also be regarded that in each display area b, two adjacent columns of sub-pixels 11 are connected to the same sensing line 5.
  • each group of sub-pixels 11 only needs to pass one
  • the sensing line 5 is connected to all the sub-pixels to meet the requirement, and there is no need to arrange multiple sensing lines 5.
  • the number of sensing lines 5 passing through the transparent area a is reduced, and the area ratio of the transparent area a in the display panel can be increased.
  • the area of the display area b occupied by the sensing lines 5 is reduced. Therefore, more sub-pixels 11 can be arranged in the display area b, and the resolution can be improved.
  • the sensing line 5 is located between the first data line 31 and the second data line 32 connected to the corresponding sub-pixel group.
  • the sensing line 5, the first data line 31, and the second data line 32 are located between the two columns of sub-pixels 11. Since the number of the data lines 3 is more than the number of the sensing lines 5, the sensing lines 5 are arranged in the two second columns. Between a data line 31 and a second data line 32, the two columns of sub-pixels 11 are close to the corresponding first data line 31 and the second data line 32, and there is no need to use a jumper across the sensing line 5 to connect the data line 3 Connect with the corresponding sub-pixel 11 to facilitate wiring and improve production efficiency.
  • the sub-pixel 11 includes a pixel circuit and a light-emitting element, the pixel circuit is located between the base substrate and the light-emitting element; the light-emitting element, or OLED, includes a first electrode, an organic light-emitting layer, and a second electrode that are stacked in sequence, The second electrode is located on the side of the organic light-emitting layer facing the base substrate. Among them, the second electrode is an anode, and the first electrode is a cathode.
  • the pixel circuit includes at least two thin film transistors.
  • the thin film transistor includes an active layer on a base substrate, a gate layer on the side of the active layer away from the base substrate, and a gate layer The source and drain layers on the side away from the base substrate, etc.
  • top-gate thin film transistors are used as examples.
  • the thin film transistors may also be bottom-gate thin film transistors or double-gate thin film transistors, which are not limited in the present disclosure.
  • the pixel circuit includes 2T1C circuit, 3T1C circuit, 7T1C circuit, etc.
  • the 2T1C circuit usually can only achieve a relatively simple light emission control function.
  • the 3T1C circuit can also use external compensation technology to control the thin film in the pixel circuit.
  • the transistor compensates and improves the display quality. Due to the complex structure of the 7T1C circuit, when used in a transparent OLED display, the area of the transparent area will be too small, and the resolution will be lower at the same time.
  • a 3T1C circuit is selected as the pixel circuit in the transparent OLED.
  • T is a transistor and C is a capacitor.
  • a pixel circuit using a 3T1C circuit will be taken as an example to describe the structure of the sub-pixel.
  • FIG. 6 is a schematic diagram of a circuit structure of a group of sub-pixels of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a circuit structure of one sub-pixel of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a partial enlarged schematic diagram of a sub-pixel of a transparent OLED display panel provided by an embodiment of the present disclosure. As shown in FIGS.
  • each sub-pixel 11 includes a first thin film transistor T1, a second thin film transistor T2, a capacitor c, and an organic light emitting diode d, wherein the gate G1 of the first thin film transistor T1 is connected to the The first gate line 21 is connected, the source S1 of the first thin film transistor T1 is connected to the first data line 31 corresponding to the sub-pixel 11, the drain D1 of the first thin film transistor T1 and the gate G2 of the second thin film transistor T2 and One end of the capacitor c is connected; the drain D2 of the second thin film transistor T2 is connected to the power line 4, and the source S2 of the second thin film transistor T2 is connected to the anode of the OLED d and the other end of the capacitor c.
  • FIG. 7 is a schematic structural diagram of the circuit of the sub-pixel in the upper left corner of FIG. 3.
  • the gate G1 of the first thin film transistor T1 obtains a scan signal from the first gate line 21, and the first thin film transistor T1
  • the source S1 of the second thin film transistor T2 receives the data signal from the first data line 31
  • the gate G2 of the second thin film transistor T2 receives the data signal output from the drain D1 of the first thin film transistor T1
  • the drain D2 of the second thin film transistor T2 receives the data signal from the A power signal is obtained from the power line 4 to drive the OLED d connected to the source S2 of the second thin film transistor T2 to emit light.
  • the driving mode of the other sub-pixels 11 in each pixel 1 is consistent with the driving mode of the sub-pixel.
  • each sub-pixel 11 further includes a third thin film transistor T3.
  • the gate G3 of the third thin film transistor T3 is electrically connected to the gate line 2 connected to the third thin film transistor T3 of the sub-pixel 11 adjacent in the second direction. Connected, and the third thin film transistor T3 and the first thin film transistor T1 in the same sub-pixel 11 are connected to different gate lines 2. That is, the gate G3 of the third thin film transistor T3 of a row of sub-pixels 11 is connected to the same gate line 2, and the gate line connected to the gate G3 of the third thin film transistor T3 of the row of sub-pixels 11 and the row The gate lines connected to the gate G1 of the first thin film transistor T1 of the sub-pixel 11 are different.
  • the first thin film transistor T1 of the first sub-pixel 111 in the first row and the first thin film transistor T1 of the second sub-pixel 111 in the first row are connected to the first gate line 11, and the first sub-pixel in the first row
  • the third thin film transistor T3 of 111 and the third thin film transistor T3 of the second sub-pixel 111 in the first row are connected to the second gate line 22;
  • the first thin film transistor T1 of the first sub-pixel 112 in the second row is connected to the first row
  • the first thin film transistor T1 of the second subpixel 112 is connected to the fourth gate line 24,
  • the third thin film transistor T3 of the first subpixel 112 in the second row and the third thin film transistor T3 of the second subpixel 112 in the first row T3 is connected to the third gate line 23.
  • the drain D3 of the third thin film transistor T3 is connected to the other end of the capacitor c and the source S2 of the second thin film transistor T2, and the source S3 of the third thin film transistor T3 is connected to the
  • the voltage difference between the anode and the cathode of the OLED should maintain the theoretical voltage difference.
  • the compensation voltage of the voltage difference can be calculated by setting an external compensation circuit driven by the third thin film transistor T3.
  • the first gate line 21 and the second gate line 22 simultaneously control the first thin film transistor T1 and the third thin film transistor T3 to be turned on.
  • a data line 31 and a second data line 32 provide a low-level signal for the first sub-pixel 111 (the low-level signal is lower than the turn-on voltage of the second thin-film crystal T2 of the first sub-pixel 111, and may be, for example, 2V) , So that the first sub-pixel 111 charges the sensing line 5, and then the compensation voltage of the first sub-pixel 111 can be calculated.
  • the source of the first thin film transistor T1 is obtained through the second data line 32.
  • Fig. 9 is a schematic cross-sectional structure view taken along the line A-A in Fig. 3.
  • each sub-pixel 11 includes an active layer 1102, a gate insulating layer 1103, a first electrode layer 1104, an interlayer insulating layer 1105, a second electrode layer 1106,
  • the passivation layer 1107 and the anode metal layer 1108, the anode metal layer 1108 and the second electrode layer 1106 are connected by a via 12
  • the second electrode layer 1106 and the active layer 1102 are connected by a via 13
  • the first electrode layer 1104 is isolated from the active layer 1102 by the gate insulating layer 1103.
  • the anode metal layer 1108 and the active layer 1102 are connected through the via hole 12, the second electrode layer 1106, and the via hole 13.
  • the anode metal layer 1108 and the active layer The layers 1102 can also be directly connected through a via hole.
  • the display panel provided by the embodiments of the present disclosure may further include a pixel definition layer, a light-emitting layer, and a cathode layer. The structure of these layers can be referred to related technologies, and detailed descriptions are omitted here.
  • FIG. 10 is a schematic diagram of the structure of an active layer in an embodiment of the present disclosure.
  • the source S2 of the second thin film transistor T2 is located in the active layer 1102, and the drain D3 of the third thin film transistor T3 is located in the active layer 1102.
  • a part of the active layer 1102 is metalized to form a conductor, which serves as a plate of the capacitor c, the source S2 of the second thin film transistor T2 and the drain D3 of the third thin film transistor T3.
  • FIG. 11 is a schematic diagram of the structure of the first electrode layer in an embodiment of the present disclosure.
  • the first electrode layer 1104 may be a gate layer, and the first electrode layer 1104 may include a plurality of gate lines 2, such as a first gate line 21, a second gate line 22, and a third gate line.
  • Line 23 and the fourth gate line 24, and the gates of the thin film transistors in each sub-pixel for example, the gate G1 of the first thin film transistor T1, the gate G2 of the second thin film transistor T2, and the gate of the third thin film transistor T3 Extremely G3.
  • the first electrode layer 1104 may further include a connection line 41 connecting the drain electrode D2 of the second thin film transistor T2 and the power supply line 4, and a source electrode S3 connected to the third thin film transistor T3 and the sensor.
  • FIG. 12 is a schematic diagram of the structure of the second electrode layer in an embodiment of the present disclosure.
  • the second electrode layer 1106 is a source and drain layer, and the second electrode layer 1106 includes a plurality of data lines 3 (for example, a first data line 31 and a second data line 32), The power line 4, the sensing line 5, a plate of the capacitor c, and at least one of the source and drain of each thin film transistor, such as the source S1 and the drain D1 of the first thin film transistor T1, and the second thin film transistor The drain electrode D2 of the transistor T2 and the source electrode S3 of the third thin film transistor T3.
  • FIG. 13 is a schematic diagram of the structure of an anode metal layer in an embodiment of the present disclosure. As shown in FIG. 13, the position of the gap on the anode metal layer 1108 is the via hole 12 communicating with the second electrode layer 1106.
  • the transparent OLED display panel provided by the embodiment of the present disclosure may further include a black matrix layer.
  • FIG. 14 is a schematic structural diagram of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • the black matrix layer 1111 shields the portion of the pixel 1 with metal traces other than the portion shielded by the corresponding metal anode 1108 to prevent light leakage.
  • the transparent region a includes a base substrate 1101, a gate insulating layer 1103, an interlayer insulating layer 1105 and a passivation layer 1107 that are sequentially stacked.
  • the base substrate 1101, the gate insulating layer 1103, the interlayer insulating layer 1105, and the passivation layer 1107 in the transparent area a and the corresponding film layers in the display area b can be made at the same time and arranged in the same layer. The difference may be that there are some The thickness of the film layer is different. For example, the thickness of the gate insulating layer 1103 and the interlayer insulating layer 1105 in the transparent area a are larger than the same film layer in the display area b.
  • each sub-pixel 11 further includes at least one of a planarization layer 1109 and a buffer layer 1110.
  • the planarization layer 1109 is located between the passivation layer 1107 and the anode metal layer 1108, and the buffer layer 1110 is located between the base substrate 1101 and the base substrate 1101.
  • the buffer layer 1110 is usually a SiO2 and SiNx layer, which can prevent the metal ions in the glass substrate from entering the polysilicon and affecting the performance of the thin film transistor.
  • the planarization layer 1109 is usually a resin layer to ensure the flatness between the metal anode of the OLED and the passivation layer 1107.
  • the base substrate 1101 is a transparent substrate, such as a glass substrate.
  • the active layer 1102 is made of at least one material selected from InGaZnO, InGaO, ITZO, and AlZnO.
  • the gate insulating layer 1103 can be made of insulating materials such as silicon nitride and silicon oxide.
  • the interlayer insulating layer 1105 can be made of insulating materials such as silicon nitride and silicon oxide.
  • the passivation layer 1107 may be a composite layer structure formed by any combination of two or more of silicon oxide, silicon nitride, and silicon nitride compound.
  • the embodiment of the present disclosure also provides a method for preparing a transparent OLED display panel, the method includes: forming a plurality of pixels and a plurality of data lines on a base substrate to obtain a transparent OLED with a plurality of transparent areas and a plurality of display areas In the display panel, the plurality of transparent areas and the plurality of display areas are alternately arranged in the first direction.
  • the multiple pixels are located in the display area, multiple pixels located in the same display area are arranged along a second direction, the data line extends along the first direction, and the first direction is aligned with the second direction.
  • the directions intersect.
  • the pixel includes a plurality of sub-pixels, the sub-pixels located in the same display area include a row of first sub-pixels and a row of second sub-pixels, and the row of first sub-pixels includes a row along the second direction A plurality of first sub-pixels arranged in a row, the row of second sub-pixels includes a plurality of second sub-pixels arranged along the second direction, and the pixel includes at least one adjacent pixel in the first direction The first sub-pixel and one of the second sub-pixels.
  • one of the first sub-pixels and one of the second sub-pixels that are adjacent in the first direction is connected to the same data line, and the first sub-pixels that are different The connected data lines are different.
  • FIG. 15 is a schematic flowchart of a method for manufacturing a transparent OLED display panel provided by an embodiment of the present disclosure. As shown in FIG. 15, the manufacturing method of the transparent OLED display panel may include the following steps.
  • a base substrate is provided.
  • the base substrate is a transparent substrate, such as a glass substrate.
  • an active layer is formed on the base substrate.
  • a thin film of active material may be formed on the base substrate first.
  • a deposition method can be used to form a thin film of active material on the base substrate.
  • the material of the active material film may be at least one of InGaZnO, InGaO, ITZO, and AlZnO.
  • the active material film is processed through a patterning process to obtain a pattern of the active layer 1102, as shown in FIG. 10.
  • a part of the area in the active layer 1102 can be metalized, so that the metalized area forms a conductor, which can be used as a plate of the capacitor c and the second thin film transistor
  • the metallization treatment can adopt the following method: treating in a reducing atmosphere at 100°C to 300°C for 30min to 120min, and the reducing atmosphere includes hydrogen gas or hydrogen-containing plasma.
  • the reduction reaction occurs in a reducing atmosphere of 100°C ⁇ 300°C for 30min ⁇ 120min, which can ensure to the greatest extent that the area not covered by the etching barrier layer in the active material film is fully and effectively reduced to a metal oxide conductor . If the temperature is too low, the reduction effect of the reduction reaction will be affected, and the reaction time will be prolonged, and the production efficiency will be reduced; if the temperature is too high, it will easily lead to the need for metallization of the active material film covered by the etching barrier layer.
  • the treated area produces a chemical effect, which affects the structural performance; similarly, if the reaction time is too short, the reduction reaction will not proceed sufficiently, and if the reaction time is too long, the production efficiency will be reduced.
  • the gate insulating layer 1103 may be formed by vapor deposition.
  • the gate insulating layer 1103 can be made of insulating materials such as silicon nitride and silicon oxide.
  • the structure of the first electrode layer is shown in FIG. 12, and will not be repeated here.
  • S105 forming an interlayer insulating layer on the first electrode layer.
  • the interlayer insulating layer 1105 can be formed in the same manner as the gate insulating layer 1103.
  • the interlayer insulating layer 1105 can be made of insulating materials such as silicon nitride and silicon oxide.
  • the structure of the second electrode layer is shown in FIG. 12, and will not be repeated here.
  • the passivation layer 1107 is a composite layer structure formed by any combination of two or more of silicon oxide, silicon nitride, and silicon nitride compound.
  • the structure of the anode metal layer is shown in FIG. 13, and will not be repeated here.
  • steps S102, S105, and S107 via holes may also be formed on the formed interlayer insulating layer 1105 and the passivation layer 1107.
  • An embodiment of the present disclosure provides a display device, including a transparent OLED display panel as described in FIGS. 2 to 9.
  • the transparent OLED display panel in the display device divides the sub-pixels of one pixel into two rows, and the sub-pixels in the same column share one data line. In this way, the number of data lines used by a pixel is less than the number of sub-pixels it contains. Compared with the prior art, the number of data lines is reduced. On the one hand, the number of data lines passing through the transparent area is reduced. The ratio of the transparent area in the display panel can be increased. On the other hand, the area of the display area occupied by the data line is reduced, more sub-pixels can be arranged on the display panel, and the resolution can be improved.
  • the display device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, and the like.
  • the embodiment of the present disclosure also provides a driving method of the transparent OLED display panel as shown in FIG. 2 to FIG. 9.
  • the transparent OLED display panel displays the picture frame by frame when it is working. During the display of each frame, it is displayed in a progressive scan method.
  • the driving method may include:
  • the thin film transistors used for display of each row of sub-pixels are controlled row by row to turn on.
  • the thin film transistor used for display is the aforementioned first thin film transistor T1.
  • FIG. 16 is a driving timing diagram of a display stage provided by an embodiment of the present disclosure. As shown in FIG. 16, in combination with FIG. 2, FIG. 3, and FIG. 4, in the embodiment of the present disclosure, the pixel 1 shown in FIG.
  • a scan signal is provided for the first gate line 21, and a data signal is provided for the first data line 31 and the second data line 32.
  • the gates of the two first thin film transistors T1 in the red and blue first sub-pixels 111 located in the second direction obtain scan signals from the first gate line 21, and the sources S1 of the two first thin film transistors T1 respectively Data signals are obtained at the first data line 31 and the second data line 32.
  • the gate G2 of the second thin film transistor T2 obtains the data signal from the drain D1 of the first thin film transistor T1, and the drain D2 of the second thin film transistor T2 obtains the power signal from the power supply line 4, thereby driving the connection with the second thin film transistor T2.
  • the organic light emitting diode d connected to the source S2 emits light, and the two first sub-pixels 111 respectively display corresponding red and blue colors.
  • a scan signal is provided for the fourth gate line 24
  • a data signal is provided for the first data line 31 and the second data line 32
  • the green and white second sub-pixels 112 located in the second direction are driven
  • the circuit controls the light-emitting diode d to emit light through the same process, so that the two second sub-pixels 112 respectively display corresponding green and white colors.
  • the third thin film transistor T3 is turned on, due to the signal control of the sensing line 5, the sub-pixels will not charge the sensing line at this stage to ensure normal display.
  • a sensing stage is further provided after the display stage, and the sensing stage is used to sense the voltage values of the sub-pixels for compensation.
  • the driving method may also include:
  • the thin film transistors for sensing of each row of sub-pixels are controlled row by row to turn on.
  • the thin film transistor used for sensing is the third thin film transistor T3.
  • the external integrated circuit can calculate the compensation value to compensate the voltage of the sub-pixel.
  • FIG. 17 is a driving timing diagram of a sensing phase provided by an embodiment of the present disclosure. As shown in FIG. 17, in conjunction with FIG. 2, FIG. 3, and FIG. 4, take the red first sub-pixel 111 as the target sub-pixel 111 as an example:
  • the first data line 31 provides a first low-level signal for the red first sub-pixel 111.
  • the low-level signal is lower than the turn-on voltage of the second thin-film crystal T2 of the first sub-pixel 111, and may be, for example, 2V.
  • the second thin film transistor T2 is not conducting.
  • the low-level signal provided by the first data line 31 enters the sensing line 5 through the capacitor c and the third thin film transistor T3. At this time, the red first sub-pixel 111 charges the sensing line 5, and then the first sub-pixel can be calculated.
  • the compensation voltage of the pixel 111 is not conducting.
  • the second data line 32 will provide a second low-level signal to the blue first sub-pixel 111, so that the blue first sub-pixel 111 can charge the corresponding sensing line 5.

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Abstract

一种透明OLED显示面板、显示装置和制备方法。该透明OLED显示面板具有在第一方向上交替布置的多个透明区域（a）以及多个显示区域（b），透明OLED显示面板包括沿第二方向排列的多个像素（1）和沿第一方向延伸的多根数据线（31,32）；每个像素（1）均包括多个子像素（11），每个显示区域（b）中的子像素（11）分为沿第二方向排列一排第一子像素（111）和一排第二子像素（112），该像素至少包括在所述第一方向上相邻的一个第一子像素（111）和一个第二子像素（112）。同一显示区域（b）中，在第一方向上相邻的一个第一子像素（111）和一个第二子像素（112）与同一根数据线（31,32）相连。该透明OLED显示面板减少了数据线（31,32）占用显示区域（b）的面积，可以排布更多的子像素（11），提高分辨率。

Description

透明OLED显示面板、显示装置和制备方法
本申请要求于2019年10月22日提交的申请号为201911008550.7、发明名称为“透明OLED显示面板、显示装置和驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种透明OLED显示面板、显示装置和制备方法。
背景技术
透明有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板是指使用有机发光材料实现显示功能，且具有透视效果的显示面板，使用者可以同时看到透明OLED显示面板中显示的影像及透明OLED显示面板背后的景象。
发明内容
本公开实施例提供了一种透明OLED显示面板、显示装置和制备方法。
第一方面，本公开实施例提供了一种透明OLED显示面板，具有多个透明区域以及多个显示区域，所述多个透明区域和所述多个显示区域在第一方向上交替布置；
所述透明OLED显示面板包括：多个像素和多根数据线，所述多个像素位于所述显示区域，位于同一所述显示区域中的多个像素沿第二方向排列，所述数据线沿所述第一方向延伸，所述第一方向与所述第二方向相交；
每个所述像素均包括多个子像素，位于同一所述显示区域中的所述子像素包括一排第一子像素和一排第二子像素，所述一排第一子像素包括沿所述第二方向排列的多个第一子像素，所述一排第二子像素包括沿所述第二方向排列的多个第二子像素，所述像素至少包括在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素；
同一所述显示区域中，在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素与同一根所述数据线相连，且不同的所述第一子像素所连接 的所述数据线不同。
可选地，每个所述显示区域包括沿所述第二方向排列的多个子像素组，每个所述子像素组包括在所述第二方向上相邻的两个子像素对，每个子像素对包括在所述第一方向上相邻的一个第一子像素和一个第二子像素，每个所述子像素组中，所述两个子像素对所连接的两根所述数据线位于所述两个子像素对之间。
可选地，所述像素包括四个所述子像素，每个所述子像素组中的子像素来自同一所述像素。
可选地，所述像素包括三个所述子像素，每个所述子像素组中的子像素来自相邻的两个所述像素。
可选地，透明OLED显示面板还包括多根栅线，所述栅线沿所述第二方向延伸，各排所述第一子像素和各排所述第二子像素分别与至少一根所述栅线连接。
可选地，所述一排第一子像素中的第一子像素分别与所述多根栅线中的两根栅线连接，且所述一排第一子像素位于所连接的两根栅线之间；所述一排第二子像素的第二子像素分别与所述多根栅线中的另两根栅线连接，且所述一排第二子像素位于所连接的两根栅线之间。
可选地，所述透明OLED显示面板还包括多根电源线，所述电源线沿所述第一方向延伸，每个子像素组中的所述第一子像素和所述第二子像素与同一根所述电源线连接。
可选地，第一子像素组所连接的电源线，位于所述第一子像素组所连接的两根数据线之间，所述第一子像素组为所述多个子像素组中的任意一个。
可选地，所述透明OLED显示面板还包括多根感测线，所述感测线沿所述第一方向延伸，每个子像素组中的所述第一子像素和所述第二子像素与同一根所述感测线连接。
可选地，第二子像素组所连接的感测线位于所述第二子像素组所连接的两根所述数据线之间，所述第二子像素组为所述多个子像素组中的任意一个。
可选地，所述子像素包括第一薄膜晶体管、第二薄膜晶体管、电容和有机发光二极管，其中，所述第一薄膜晶体管的栅极与对应的所述栅线电连接，所述第一薄膜晶体管的源极与对应的所述数据线电连接，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的栅极以及所述电容的一端电连接；所述第二薄膜 晶体管的漏极与对应的所述电源线电连接，所述第二薄膜晶体管的源极与所述有机发光二极管的阳极电连接；所述有机发光二极管的阳极与所述电容的另一端电连接。
可选地，每个所述子像素还包括第三薄膜晶体管，位于同一排的子像素的第三薄膜晶体管的栅极连接同一根栅线，且对于任意一排子像素，所述第三薄膜晶体管和所述第一薄膜晶体管所连接的栅线不同；所述第三薄膜晶体管的漏极与所述电容的另一端、所述第二薄膜晶体管的源极电连接，所述第三薄膜晶体管的源极与所述感测线电连接。
可选地，所述子像素包括依次层叠在衬底基板上的有源层、栅极绝缘层、第一电极层、层间绝缘层、第二电极层、钝化层和阳极金属层，所述阳极金属层和所述第二电极层之间通过过孔连接，所述第一电极层通过所述栅极绝缘层与所述有源层隔离。
可选地，所述第二薄膜晶体管的源极位于所述有源层，所述第三薄膜晶体管的漏极位于所述有源层。
可选地，每个所述子像素还包括平坦化层、缓冲层中的至少一种，所述平坦化层位于所述钝化层和所述阳极金属层之间，所述缓冲层位于所述基板和所述有源层之间。
可选地，所述透明区域的显示面板包括依次层叠的衬底基板、栅极绝缘层、层间绝缘层和钝化层。
第二方面，本公开实施例提供了一种显示装置，包括如前述第一方面所述的透明OLED显示面板。
第三方面，本公开实施例提供了一种透明OLED显示面板的制备方法，包括：
在衬底基板上形成多个像素和多根数据线，得到具有多个透明区域以及多个显示区域的透明OLED显示面板，所述多个透明区域和所述多个显示区域在第一方向上交替布置；
所述多个像素位于所述显示区域，位于同一所述显示区域中的多个像素沿第二方向排列，所述数据线沿所述第一方向延伸，所述第一方向与所述第二方向相交；
所述像素包括多个子像素，位于同一所述显示区域中的所述子像素包括一 排第一子像素和一排第二子像素，所述一排第一子像素包括沿所述第二方向排列的多个第一子像素，所述一排第二子像素包括沿所述第二方向排列的多个第二子像素，所述像素至少包括在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素；
同一所述显示区域中，在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素与同一根所述数据线相连，且不同的所述第一子像素所连接的所述数据线不同。
附图说明
图1是相关技术中的一种透明OLED显示面板的结构示意图；
图2是本公开实施例提供的一种透明OLED显示面板的结构示意图；
图3是本公开实施例提供的一种透明OLED显示面板的局部放大结构示意图；
图4是本公开实施例提供的一种透明OLED显示面板的像素的排列示意图；
图5是本公开实施例提供的另一种OLED显示面板的像素的排列示意图；
图6是本公开实施例提供的一种透明OLED显示面板的一组子像素的电路结构示意图；
图7是本公开实施例提供的一种透明OLED显示面板的一个子像素的电路结构示意图；
图8是本公开实施例提供的一种透明OLED显示面板的一个子像素的局部放大结构示意图；
图9是沿图3中A-A线的剖面结构示意图；
图10是本公开实施例中的有源层的结构示意图；
图11是本公开实施例中第一电极层的结构示意图；
图12是本公开实施例中第二电极层的结构示意图；
图13是本公开实施例中阳极金属层的结构示意图；
图14是本公开实施例提供的一种透明OLED显示面板的黑矩阵层的结构示意图；
图15是本公开实施例提供的一种透明OLED显示面板的制备方法的流程示意图；
图16是本公开实施例提供的一种显示阶段的驱动时序图；
图17是本公开实施例提供的一种感测阶段的驱动时序图。
具体实施方式
为使本公开的原理、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是相关技术中的一种透明OLED显示面板的结构示意图。如图1所示，相关技术中，透明OLED显示面板包括在第一方向上交替布置的多个透明区域a0和多个显示区域b0，相邻的一个透明区域a0和一个显示区域b0构成1个重复周期。为便于说明，图1中仅示出了1个重复周期，实际上透明区域a0和显示区域b0可以有多个重复周期。
该透明OLED显示面板包括阵列布置的多个子像素c0，每行子像素c0位于一个显示区域b0中，每一行中连续的多个不同颜色的子像素c0构成一个像素d0。
每行子像素c0与一根栅线e0电连接，每列子像素c0与一根数据线f0电连接。每个子像素c0均通过电连接的栅线e0获得扫描信号，通过电连接的数据线f0获得数据信号。在扫描信号和数据信号的作用下，驱动各个子像素c0中的OLED发光，从而在该透明OLED显示面板的显示区域b0中显示图像。并且，通过透明区域a0可以看到透明OLED显示面板后面的景象。
如图1所示，数据线f0沿着该第一方向延伸，这些数据线f0穿过透明区域a0和显示区域b0，并且需要采用黑矩阵(图中未示出)进行遮挡。位于透明区域a0中的数据线f0和黑矩阵使得透明区域a0的透光面积较小；同时每根数据线f0均会占据显示区域b0的一定面积，使得显示区域b0中子像素c0的排布空间减小，导致分辨率较低。
图2是本公开实施例提供的一种透明OLED显示面板的结构示意图。如图2所示，该透明OLED显示面板具有多个透明区域a以及多个显示区域b，多个透明区域a和多个显示区域b在第一方向上交替布置。用户可以透过透明区域a看到透明OLED显示面板背后的景象，同时，可以观看到透明OLED显示面板在显示区域b显示的图像。
透明OLED显示面板包括多个像素1，多个像素1位于显示区域b中，同一显示区域b中的多个像素1沿第二方向排列，第一方向与第二方向相交，例如 垂直。示例性地，第一方向即如图2中箭头x所指的方向，第二方向即如图2中箭头y所指的方向。
在本公开实施例中，将以第一方向为列方向，第二方向为行方向进行说明。
如图2所示，透明OLED显示面板还包括多根栅线2和多根数据线3，多根栅线2相互平行且沿第二方向延伸，多根数据线3相互平行且沿第一方向延伸。
图3是本公开实施例提供的一种透明OLED显示面板的局部放大结构示意图。如图3所示，每个像素1均包括多个子像素11，每个显示区域b中的子像素11分为两排子像素11，每排子像素11的均沿第二方向排列。两排子像素11中的一排为第一子像素111，两排子像素11中的另一排为第二子像素112。每个像素1均包括至少一个第一子像素111和至少一个第二子像素112，也即是每个像素1所包含的子像素11均分为两排，且每个像素1所包含的第一子像素111和第二子像素112中，至少一个第一子像素111和至少一个第二子像素112在第一方向上相邻。
同一显示区域b中，在第一方向上相邻的一个第一子像素111和一个第二子像素112与同一根数据线3相连，且不同的第一子像素111所连接的数据线3不同，也即是，同一列的子像素11与一根数据线3连接，不同列的子像素11与不同的数据线3连接。例如，在图3中，左边的第一子像素111和第二子像素112连接数据线31，右边的第一子像素111和第二子像素112连接数据线32。
在本公开实施例中，通过将一个像素的子像素分为两行，使得一个像素对应的子像素的列数变少。由于同一列的子像素共用一根数据线，在子像素的列数变少的情况下，一个像素所用的数据线的数量少于其所包含的子像素的数量，与相关技术中每个像素所用的数据线的数量与该像素包含的子像素的数量相比，减少了数据线的数量。一方面，由于数据线穿过透明区域，占用透明区域的面积，所以数据线的数量减小，可以增大透明区域的面积，进而提高透明区域在透明OLED显示面板中的面积占比，另一方面，数据线的数量减小，使得数据线所占用的显示区域的面积减小，从而可以相同的面积中排布更多的子像素，提高透明OLED显示面板的分辨率。
可选地，在本公开实施例中，每排第一子像素111和每排第二子像素112分别与至少一根栅线2连接，且第一子像素111和第二子像素112所连接的栅线2不同。例如，一排第一子像素111连接一根栅线2，一排第二子像素112连接另一根栅线2。
示例性地，每排子像素对应两根栅线，且每排子像素中的每个子像素均与对应的两根栅线连接。例如，一排第一子像素111中的第一子像素111分别与两根栅线2(第一栅线21和第二栅线22)连接，且该排第一子像素位于所连接的两根栅线2之间；所述一排第二子像素112的第二子像素112分别与另两根栅线2连接，且该排第二子像素112位于所连接的两根栅线2(第三栅线23和第四栅线24)之间。
需要说明的是，图3中仅示出了每个显示区域b中的一个像素1，以及在第一方向上与该像素1所属的显示区域b相邻的透明区域a的结构。由于图3所示的结构为本公开实施例提供的透明OLED显示面板的一个重复单元，也即是，在第二方向上，透明OLED显示面板包括多个图3所示的结构，在第一方向上，透明OLED显示面板也包括多个图3所示的结构，故本公开实施例以如图3所示的透明OLED显示面板的局部结构进行示例性说明。
此外，还需要说明的是，在图3所示实施例中，每个显示区域b中包括一排像素1，在其他实施例中，每个显示区域中也可以包括多排像素1(例如包括2排像素1)，每排像素1的子像素11均分为两排。
如图3所示，该像素1包括采用正方形(square)形式排列的四个子像素11，四个子像素11包括沿第二方向排列的两个第一子像素111和两个第二子像素112。第一排中的第一个第一子像素111和第二排中的第一个第二子像素112相邻，与同一条第一数据线31连接；第一排中的第二个第一子像素111和第二排中的第二个第二子像素112相邻，与第二数据线32连接。可见，该像素1与两根数据线3连接。而多个透明区域a和多个显示区域b在第一方向上交替布置，故在第一方向上，每列像素1与两根数据线3连接。
在相关技术中，再次参照图1，一个像素d0中每个不同颜色的子像素c0分别与一根数据线f0连接。如果一个像素d0包括四个子像素c0，那么一个像素d0就需要连接四根数据线f0，由于一列像素中的多个像素连接同一根数据线，所以相关技术中，每列像素需要连接四根数据线。
在像素数量相同，且子像素面积相等的情况下，本公开实施例与相关技术相比，减少了数据线的数量，由于数据线是沿第一方向穿过透明区域的，所以数据线数量减少，占用的透明区域的面积也减小，从而提高了透明区域的面积占比。同时，数据线也穿过显示区域，数据线数量减小，占用显示区域的面积也减小，所以可以让显示面板上排列更多的子像素，提高分辨率。
可选地，再次参见图2和图3，每个显示区域b包括沿第二方向排列的多个子像素组，图2中的每个虚线框表示一个子像素组，图3中显示了一个子像素组的结构。每个所述子像素组包括在所述第二方向y上相邻的两个子像素对，每个子像素对包括在所述第一方向x上相邻的一个第一子像素111和一个第二子像素112，也即是，每个子像素组包括在第二方向y上相邻的两个第一子像素111和在第二方向y上相邻的两个第二子像素112，每个子像素组中的两个子像素对所连接的两根数据线3位于两个子像素对之间，也即是位于相邻的两个第一子像素111以及相邻的两个第二子像素112之间。
每个显示区域中b中，在第二方向上，每个子像素组中的两个子像素对所连接的两根数据线3排列在两个子像素对之间，因此相邻两个子像素组之间没有数据线。相比每列子像素11之间都排列有一根穿过透明区域a和显示区域b的数据线3的排列方式，本公开实施例中，相邻两个子像素组对应的透明区域a之间没有数据线穿过，增大了整块透明区域a的面积，方便用户透过透明区域a观看透明OLED显示面板背后的景象。
图4是本公开实施例提供的一种透明OLED显示面板的像素排列示意图。图4所示的是透明OLED显示面板中由一个显示区域b中的一个像素1和相邻的透明区域a所组成的单元，与图3中的子像素11和透明区域a对应。
在图3和图4所示的实施例中，每个像素1包括四个子像素11，每个像素1中的四个子像素11对应图3中的一个子像素组，也即是，每个子像素组中的四个子像素11属于同一像素1。示例性的，如图4所示，四个子像素11分别为红色(red，R)、蓝色(blue，B)、绿色(green，G)和白色(white，W)子像素。示例性地，两个第一子像素111分别为红色和蓝色子像素，两个第二子像素112分别为绿色和白色子像素。
图5是本公开实施例提供的另一种OLED显示面板的像素排列示意图。如图5所示，每个像素1包括三个子像素11，三个子像素11呈品字型排布。在这种情况下，每组子像素11中的4个子像素可以包括一个像素1中的三个子像素加上另一个像素11中的一个子像素11，也即该一组子像素中的四个子像素11来自相邻的两个像素1。
示例性地，一个像素1中的三个子像素11分别为蓝色子像素、红色子像素和绿色子像素。参考图3所示的OLED显示面板中子像素11和数据线3的连接方式可知，在图5所示的实施例中，在一个显示区域b中，第一排子像素11中 红色的第一子像素113和第二排子像素中蓝色的第二子像素114共用第一数据线31；第二排子像素11中绿色的第二子像素114则跟第一排子像素中蓝色的第一子像素113共用第二数据线32。即每三分之二个像素通过一根数据线控制；而如图1所示，相关技术中的一个显示区域b0中的像素d0中包括依次排列的三个子像素c0，三个子像素c0分别对应一根数据线f0进行控制。即每三分之一个像素通过一根数据线控制。综上，在像素数量相同，且子像素的数量和结构也相同的情况下，图5所示的实施例中数据线的数量依旧比相关技术中数据线的数量要少，从而可以提高透明区域a在显示面板中的面积占比，并且可以在显示区域b中排布更多的子像素11，提高分辨率。
示例性的，如图5所示，像素1包括红色的第一子像素113以及蓝色和绿色的第二子像素114，或者，像素1包括蓝色和绿色的第一子像素113以及红色的第二子像素114。
可选地，再次参见图3，该透明OLED显示面板还包括多根电源线4。参见图3，电源线4沿第一方向延伸且穿过透明区域a和显示区域b，每组子像素11中的第一子像素111和第二子像素112与同一根电源线4连接。电源线4用于为透明OLED显示面板中的OLED提供电能。每组子像素11中包括相邻的两个第一子像素111和相邻的两个第二子像素112，即4个子像素11共用一根电源线4。也即是，在每个显示区域b中，每个像素1中的每两列子像素11与同一根电源线4连接。而相关技术中，通常每列子像素11分别连接一根电源线4。因此，与相关技术相比，本公开实施例中电源线4数量减少，可以提高透明区域a在显示面板中的面积占比，另外，电源线4数量减少，使得电源线4所占用的显示区域b的面积减小，从而可以在显示区域b中排布更多的子像素11，进一步提高显示面板的分辨率。
可选地，电源线4位于一组子像素11所连接的两根数据线3之间。每组子像素11中，电源线4和两根数据线3均位于两列子像素11之间的间隙中，由于数据线3的数量多于电源线4，通过将电源线4排列在两根数据线3之间，使两列子像素11靠近与之对应的两根数据线3，无需使用跨过电源线4的跨接线将数据线3与对应的子像素11连接，方便布线，提高生产效率。
可选地，再次参见图3，透明OLED显示面板还包括多根沿第一方向延伸的感测线5，每个子像素组中的第一子像素111和第二子像素112与同一根所述感测线5连接。感测线5用于感测所连接的子像素11中的电信号，以及传递外部 补偿电路的补偿电压信号。每个子像素组中包括相邻的两个第一子像素111和相邻的两个第二子像素112，即4个子像素11共用一根感测线5。也可以视为，在每个显示区域b中，相邻的两列子像素11与同一根感测线5连接。由于通过调节第一数据线31和第二数据线32的电平信号的电压大小，可以实现单独对任一子像素11中的补偿电压的计算，因此每组子像素11中只需通过一根感测线5与所有子像素连接即可满足要求，无需排列多根感测线5。一方面，减少了穿过透明区域a的感测线5的数量，可以提高透明区域a在显示面板中的面积占比，另一方面减少了感测线5所占用的显示区域b的面积，从而可以在显示区域b中排布更多的子像素11，提高分辨率。
可选地，感测线5位于对应的子像素组所连接的第一数据线31和第二数据线32之间。感测线5、第一数据线31和第二数据线32位于两列子像素11之间，由于数据线3的数量多于感测线5的数量，通过将感测线5排列在两根第一数据线31和第二数据线32之间，使两列子像素11靠近与之对应的第一数据线31和第二数据线32，无需使用跨过感测线5的跨接线将数据线3与对应的子像素11连接，方便布线，提高生产效率。
在OLED显示面板中，子像素11包括像素电路和发光元件，像素电路位于衬底基板和发光元件之间；发光元件即OLED，包括依次层叠设置的第一电极、有机发光层以及第二电极，第二电极位于有机发光层面向衬底基板的一侧。其中，第二电极为阳极，第一电极为阴极。像素电路包括至少两个薄膜晶体管，以顶栅型薄膜晶体管为例，薄膜晶体管包括位于衬底基板上的有源层、位于有源层远离衬底基板一侧的栅极层以及位于栅极层远离衬底基板一侧的源漏极层等。在后续描述中均以顶栅型薄膜晶体管为例进行说明，在其他实现方式中，薄膜晶体管也可以为底栅型薄膜晶体管或双栅型薄膜晶体管，本公开对此不做限制。
示例性地，像素电路包括2T1C电路、3T1C电路、7T1C电路等，2T1C电路通常仅能实现较为简单的发光控制功能，3T1C电路除了能够实现发光控制，还可以通过外部补偿技术，对像素电路中薄膜晶体管进行补偿，提高显示质量。7T1C电路由于结构复杂，使用在透明OLED显示中，会造成透明区域面积过小，同时导致分辨率较低。在本公开实施例中，选用3T1C电路作为透明OLED中的像素电路。其中，T为晶体管，C为电容。
下文中将以采用3T1C电路的像素电路为例，对子像素的结构进行说明。
图6是本公开实施例提供的一种透明OLED显示面板的一组子像素的电路结构示意图。图7是本公开实施例提供的一种透明OLED显示面板的一个子像素的电路结构示意图。图8是本公开实施例提供的一种透明OLED显示面板的一个子像素的局部放大结构示意图。如图6、图7和图8所示，每个子像素11均包括第一薄膜晶体管T1、第二薄膜晶体管T2、电容c和有机发光二极管d，其中，第一薄膜晶体管T1的栅极G1与第一栅线21连接，第一薄膜晶体管T1的源极S1连接至该子像素11对应的第一数据线31，第一薄膜晶体管T1的漏极D1与第二薄膜晶体管T2的栅极G2以及电容c的一端连接；第二薄膜晶体管T2的漏极D2与电源线4连接，第二薄膜晶体管T2的源极S2与OLED d的阳极以及电容c的另一端连接。
图7为图3左上角的子像素的电路的结构示意图，在图7所示的电路中，第一薄膜晶体管T1的栅极G1从第一栅线21处获得扫描信号，第一薄膜晶体管T1的源极S1从第一数据线31处获得数据信号，第二薄膜晶体管T2的栅极G2接收从第一薄膜晶体管T1的漏极D1输出的数据信号，第二薄膜晶体管T2的漏极D2从电源线4处获得电源信号，从而驱动与第二薄膜晶体管T2的源极S2连接的OLEDd发光。
需要说明的是，每个像素1中的其他子像素11的驱动方式均与该子像素的驱动方式一致。
可选地，每个子像素11还包括第三薄膜晶体管T3，第三薄膜晶体管T3的栅极G3与在第二方向上相邻的子像素11的第三薄膜晶体管T3所连接的栅线2电连接，且同一子像素11中第三薄膜晶体管T3和第一薄膜晶体管T1连接不同的栅线2。也即是，一排子像素11的第三薄膜晶体管T3的栅极G3连接同一根栅线2，且该排子像素11的第三薄膜晶体管T3的栅极G3所连接的栅线与该排子像素11的第一薄膜晶体管T1的栅极G1所连接的栅线不同。例如，第一排的第一个子像素111的第一薄膜晶体管T1与第一排的第二个子像素111的第一薄膜晶体管T1连接第一栅线11，第一排的第一个子像素111的第三薄膜晶体管T3与第一排的第二个子像素111的第三薄膜晶体管T3连接第二栅线22；第二排的第一个子像素112的第一薄膜晶体管T1与第一排的第二个子像素112的第一薄膜晶体管T1连接第四栅线24，第二排的第一个子像素112的第三薄膜晶体管T3与第一排的第二个子像素112的第三薄膜晶体管T3连接第三栅线23。第三薄膜晶体管T3的漏极D3与电容c的另一端、以及第二薄膜晶体管T2的源极 S2连接，第三薄膜晶体管T3的源极S3与感测线5连接。
需要说明的是，透明OLED显示面板工作时，OLED的阳极和阴极之间的电压差值应当保持理论电压差值，然而，在OLED的使用过程中，由于工艺条件、外界环境和使用时间等因素，导致电源电压产生压降，从而实际施加到OLED两端的电压差值与理论电压差值存在差异，进而影响透明OLED显示面板的显示效果。通过设置由第三薄膜晶体管T3驱动的外部补偿电路可以对该电压差值的补偿电压进行计算。
再次以图5中的左上角的子像素的驱动电路为例，在感测阶段，第一栅线21和第二栅线22同时控制第一薄膜晶体管T1和第三薄膜晶体管T3导通，第一数据线31、第二数据线32为第一子像素111提供低电平信号(该低电平信号低于第一子像素111的第二薄膜晶体T2的导通电压，例如可以为2V)，使得第一子像素111为感测线5充电，进而可以计算该第一子像素111的补偿电压。而与之在第二方向上相邻的第一子像素111中，虽然第一薄膜晶体管T1和第三薄膜晶体管T3均导通，但其中第一薄膜晶体管T1源极通过第二数据线32得到的为低电平信号，其电压通常为0V或为负，因此其对感测线5的影响可忽略不计，实现单独对左上角的第一子像素111的补偿电压的计算。
图9是沿图3中A-A线的剖面结构示意图。如图9所示，每个子像素11包括依次层叠设置在衬底基板1101上的有源层1102、栅极绝缘层1103、第一电极层1104、层间绝缘层1105、第二电极层1106、钝化层1107和阳极金属层1108，阳极金属层1108和第二电极层1106之间通过过孔12连接，第二电极层1106和有源层1102之间通过过孔13连接，第一电极层1104通过栅极绝缘层1103与有源层1102隔离。
需要说明的是，在本实施例中，阳极金属层1108和有源层1102通过过孔12、第二电极层1106和过孔13连接，而在其他实施例中，阳极金属层1108和有源层1102之间也可以通过一个过孔直接连接。此外，本公开实施例提供的显示面板还可以包括像素定义层、发光层、阴极层，这些层的结构可以参见相关技术，在此省略详细描述。
图10是本公开实施例中的有源层的结构示意图。如图10所示，第二薄膜晶体管T2的源极S2位于有源层1102，第三薄膜晶体管T3的漏极D3位于有源层1102。有源层1102的部分区域通过金属化形成导体，作为电容c的一个极板、第二薄膜晶体管T2的源极S2和第三薄膜晶体管T3的漏极D3。
图11是本公开实施例中第一电极层的结构示意图。如图12所示，示例性地，第一电极层1104可以为栅极层，第一电极层1104可以包括多根栅线2，例如第一栅线21、第二栅线22、第三栅线23和第四栅线24，以及各个子像素中的薄膜晶体管的栅极，例如，第一薄膜晶体管T1的栅极G1、第二薄膜晶体管T2的栅极G2和第三薄膜晶体管T3的栅极G3。
可选地，如图11所示，第一电极层1104还可以包括连接第二薄膜晶体管T2的漏极D2和电源线4的连接线41、以及连接第三薄膜晶体管T3的源极S3和感测线5的连接线51。
图12是本公开实施例中第二电极层的结构示意图。如图12所示，示例性的，第二电极层1106为源极和漏极层，第二电极层1106包括多条数据线3，(例如第一数据线31和第二数据线32)、电源线4、感测线5、电容c的一个极板、以及各个薄膜晶体管中的源极和漏极中的至少一个，例如第一薄膜晶体管T1的源极S1和漏极D1，第二薄膜晶体管T2的漏极D2以及第三薄膜晶体管T3的源极S3。
图13是本公开实施例中阳极金属层的结构示意图。如图13所示，阳极金属层1108上的缺口位置为与第二电极层1106连通的过孔12。
可选地，本公开实施例提供的透明OLED显示面板还可以包括黑矩阵层。图14是本公开实施例提供的一种透明OLED显示面板的结构示意图。结合图3、图13和图14，示例性的，黑矩阵层1111对像素1中被相应的金属阳极1108所遮挡的部分之外具有金属走线的部分进行遮挡，防止漏光。
再次参见图9，在本公开实施例中，透明区域a包括依次层叠的衬底基板1101、栅极绝缘层1103、层间绝缘层1105和钝化层1107。透明区域a中的衬底基板1101、栅极绝缘层1103、层间绝缘层1105和钝化层1107与显示区域b中对应的各个膜层可以同时制作，且同层布置，区别可能在于存在部分膜层的厚度不同，例如透明区域a中的栅极绝缘层1103、层间绝缘层1105的厚度均大于显示区域b中的同样膜层。
可选地，每个子像素11还包括平坦化层1109、缓冲层1110中的至少一种，平坦化层1109位于钝化层1107和阳极金属层1108之间，缓冲层1110位于衬底基板1101和有源层1102之间。缓冲层1110通常为SiO2和SiNx层，可以防止玻璃基板中的金属离子进入到多晶硅中，影响薄膜晶体管的性能。而平坦化层1109通常为树脂层，保证OLED的金属阳极和钝化层1107之间的平坦度。
可选地，该衬底基板1101为透明基板，例如玻璃基板等。有源层1102采用InGaZnO、InGaO、ITZO、AlZnO中的至少一种材料制成。栅极绝缘层1103可以采用氮化硅、氧化硅等绝缘材料制作。层间绝缘层1105可以采用氮化硅、氧化硅等绝缘材料制作。钝化层1107可以为氧化硅、氮化硅、氮硅化合物中的两种或多种的任意组合所构成的复合层结构。
本公开实施例还提供了一种透明OLED显示面板的制备方法，该方法包括：在衬底基板上形成多个像素和多根数据线，得到具有多个透明区域以及多个显示区域的透明OLED显示面板，所述多个透明区域和所述多个显示区域在第一方向上交替布置。所述多个像素位于所述显示区域，位于同一所述显示区域中的多个像素沿第二方向排列，所述数据线沿所述第一方向延伸，所述第一方向与所述第二方向相交。所述像素包括多个子像素，位于同一所述显示区域中的所述子像素包括一排第一子像素和一排第二子像素，所述一排第一子像素包括沿所述第二方向排列的多个第一子像素，所述一排第二子像素包括沿所述第二方向排列的多个第二子像素，所述像素至少包括在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素。同一所述显示区域中，在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素与同一根所述数据线相连，且不同的所述第一子像素所连接的所述数据线不同。
图15是本公开实施例提供的一种透明OLED显示面板的制备方法的流程示意图。如图15所示，该透明OLED显示面板的制备方法可以包括以下步骤。
在S101中，提供一衬底基板。
该衬底基板为透明基板，例如玻璃基板等。
在S102中，在衬底基板上形成有源层。
在步骤S102中，可以先在衬底基板上形成有源材料薄膜。例如可以采用沉积的方式在衬底基板上形成有源材料薄膜。有源材料薄膜的材料可以是InGaZnO、InGaO、ITZO、AlZnO中的至少一种。
然后，通过构图工艺对有源材料薄膜进行处理，得到有源层1102的图案，如图10所示。在得到有源层1102的图案后，可以对有源层1102中的部分区域进行金属化处理，这样经过金属化处理的区域就形成了导体，可以作为电容c的一个极板、第二薄膜晶体管T2的源极S2和第三薄膜晶体管T3的漏极D3。
金属化处理可以采用以下方式：在100℃～300℃的还原性气氛中处理30min～120min，还原性气氛包括氢气或含氢等离子体。采用在100℃～300℃的还原性气氛中发生还原反应30min～120min，可最大程度地确保有源材料薄膜中未被刻蚀阻挡层覆盖的区域充分地、有效地被还原成金属氧化物导体。若该温度过低，将影响还原反应的还原效果，并且会延长该反应时间，降低生产效率；若该温度过高，容易导致有源材料薄膜中被刻蚀阻挡层覆盖的不需要进行金属化处理的区域产生化学作用，进而影响该结构性能；同样，若反应时间过短，将导致还原反应进行地不充分，若反应时间过长，将会降低生产效率。
S103：在有源层上形成栅极绝缘层。
示例性地，再次参见图9，可以通过气相沉积的方式形成栅极绝缘层1103。栅极绝缘层1103可以采用氮化硅、氧化硅等绝缘材料制作。
S104：在栅极绝缘层上形成第一电极层。
第一电极层的结构如图12所示，在此不再赘述。
S105：在第一电极层上形成层间绝缘层。
层间绝缘层1105的形成方式可以与栅极绝缘层1103相同。层间绝缘层1105可以采用氮化硅、氧化硅等绝缘材料制作。
S106：在层间绝缘层上形成第二电极层。
第二电极层的结构如图12所示，在此不再赘述。
S107：在第二电极层上形成钝化层。
示例性的，钝化层1107为氧化硅、氮化硅、氮硅化合物中的两种或多种的任意组合所构成的复合层结构。
S108：在钝化层上形成阳极金属层。
阳极金属层的结构如图13所示，在此不再赘述。
需要说明的是，不同的图案层之间需要连接的区域可以通过过孔连接。因此在步骤S102、S105、S107中，还可以在所形成的层间绝缘层1105和钝化层1107上形成过孔。
本公开实施例提供了一种显示装置，包括如图2至图9所述的透明OLED显示面板。
该显示装置中的透明OLED显示面板通过将一个像素的子像素分为两行，同一列的子像素共用一根数据线。这样，一个像素所用的数据线的数量少于其 所包含的子像素的数量，与现有技术相比，减少了数据线的数量，一方面，穿过透明区域的数据线的数量减小，可以提高透明区域在显示面板中的比例，另一方面，减少了数据线所占用显示区域的面积，可以在显示面板上排布更多的子像素，提高分辨率。
本公开实施例中，显示装置包括但不限于手机、平板电脑、笔记本电脑等。
本公开实施例还提供了一种如图2至图9所示的透明OLED显示面板的驱动方法。透明OLED显示面板工作时逐帧显示画面，在每帧画面的显示过程中，是按照逐行扫描的方式进行显示的。该驱动方法可以包括：
在显示阶段，逐行控制各行子像素的用于显示的薄膜晶体管导通。
在一行子像素的用于显示的薄膜晶体管导通时，向该行子像素的各个子像素分别写入数据信号，以控制各个子像素的发光亮度。
这里，用于显示的薄膜晶体管即前述第一薄膜晶体管T1。
图16是本公开实施例提供的一种显示阶段的驱动时序图。如图16所示，结合图2、图3和图4，在本公开实施例中，以图4所示的像素1为目标像素1为例：
以XHz的频率，在第一时间段t1，为第一栅线21提供扫描信号，为第一数据线31和第二数据线32提供数据信号。
位于第二方向上的红色和蓝色第一子像素111中的两个第一薄膜晶体管T1的栅极从第一栅线21获得扫描信号，两个第一薄膜晶体管T1的源极S1分别从第一数据线31和第二数据线32处获得数据信号。第二薄膜晶体管T2的栅极G2从第一薄膜晶体管T1的漏极D1获取数据信号，第二薄膜晶体管T2的漏极D2从电源线4处获得电源信号，从而驱动与第二薄膜晶体管T2的源极S2连接的有机发光二极管d发光，两个第一子像素111分别显示相应的红色和蓝色。
在第二时间段t2，为第四栅线24提供扫描信号，为第一数据线31和第二数据线32提供数据信号，位于第二方向上的绿色和白色第二子像素112中的驱动电路通过相同的过程控制发光二极管d发光，使两个第二子像素112分别显示相应的绿色和白色。
在显示阶段，虽然第三薄膜晶体管T3导通，但由于感测线5的信号控制，使得子像素不会在此阶段对感测线进行充电，保证正常显示。
可选地，在一帧画面的显示时间中，显示阶段后还设置有感测阶段，感测 阶段用于感测子像素的电压值以用来进行补偿。该驱动方法还可以包括：
在感测阶段，逐行控制各行子像素的用于感测的薄膜晶体管导通。这里，用于感测的薄膜晶体管为第三薄膜晶体管T3。
在一行子像素的用于感测的薄膜晶体管导通时，通过感测线感测子像素的电信号。基于该电信号，外部的集成电路可以计算出补偿值对子像素进行电压补偿。
图17是本公开实施例提供的一种感测阶段的驱动时序图。如图17所示，结合图2、图3和图4，以红色第一子像素111为目标子像素111为例：
在第三时间段t3，为第一栅线21和第二栅线22提供扫描信号，第一薄膜晶体管T1和第三薄膜晶体管T3导通。
第一数据线31为红色第一子像素111提供第一低电平信号，该低电平信号低于第一子像素111的第二薄膜晶体T2的导通电压，例如可以为2V，因此第二薄膜晶体管T2不导通。第一数据线31所提供的低电平信号通过电容c和第三薄膜晶体管T3进入感测线5，此时该红色第一子像素111为感测线5充电，进而可以计算该第一子像素111的补偿电压。
类似第一数据线31，第二数据线32会给蓝色第一子像素111提供第二低电平信号，从而实现蓝色第一子像素111为对应的感测线5充电。
需要说明的是，上述过程仅为感测阶段中对于一行子像素的感测过程，其他行的感测方式与之相同，本公开在此不作赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (18)

  1. 一种透明OLED显示面板，具有多个透明区域(a)以及多个显示区域(b)，所述多个透明区域(a)和所述多个显示区域(b)在第一方向(x)上交替布置；
    所述透明OLED显示面板包括：
    多个像素(1)和多根数据线(3)，所述多个像素(1)位于所述显示区域(b)，位于同一所述显示区域(b)中的多个像素(1)沿第二方向(y)排列，所述数据线(3)沿所述第一方向(x)延伸，所述第一方向(x)与所述第二方向(y)相交；
    所述像素(1)包括多个子像素(11)，位于同一所述显示区域(b)中的所述子像素(11)包括一排第一子像素(111)和一排第二子像素(112)，所述一排第一子像素(111)包括沿所述第二方向(y)排列的多个第一子像素(111)，所述一排第二子像素(112)包括沿所述第二方向(y)排列的多个第二子像素(112)，所述像素(1)至少包括在所述第一方向(x)上相邻的一个所述第一子像素(111)和一个所述第二子像素(112)；
    同一所述显示区域(b)中，在所述第一方向(x)上相邻的一个所述第一子像素(111)和一个所述第二子像素(112)与同一根所述数据线(3)相连，且不同的所述第一子像素(111)所连接的所述数据线(3)不同。
  2. 根据权利要求1所述的透明OLED显示面板，其中，所述显示区域(b)包括沿所述第二方向(y)排列的多个子像素组，每个所述子像素组包括在所述第二方向(y)上相邻的两个子像素对，每个子像素对包括在所述第一方向(x)上相邻的一个第一子像素(111)和一个第二子像素(112)，每个所述子像素组中，所述两个子像素对所连接的两根所述数据线(3)位于所述两个子像素对之间。
  3. 根据权利要求2所述的透明OLED显示面板，其中，所述像素(1)包括四个所述子像素(11)，每个所述子像素组中的子像素(11)来自同一所述像素(1)。
  4. 根据权利要求2所述的透明OLED显示面板，其中，所述像素(1)包括三个所述子像素(11)，每个所述子像素组中的子像素(11)来自相邻的两个所述像素(1)。
  5. 根据权利要求2至4任一项所述的透明OLED显示面板，还包括多根栅线(2)，所述栅线(2)沿所述第二方向(y)延伸，各排所述第一子像素(111)和各排所述第二子像素(112)分别与至少一根所述栅线(2)连接。
  6. 根据权利要求5所述的透明OLED显示面板，其中，所述一排第一子像素(111)中的第一子像素(111)分别与所述多根栅线(2)中的两根栅线(2)连接，且所述一排第一子像素(111)位于所连接的两根栅线(2)之间；
    所述一排第二子像素(112)的第二子像素(112)分别与所述多根栅线(2)中的另两根栅线(2)连接，且所述一排第二子像素(112)位于所连接的两根栅线(2)之间。
  7. 根据权利要求2至6任一项所述的透明OLED显示面板，还包括多根电源线(4)，所述电源线沿所述第一方向(x)延伸，每个子像素组中的所述第一子像素(111)和所述第二子像素(112)与同一根所述电源线(4)连接。
  8. 根据权利要求7所述的透明OLED显示面板，其中，第一子像素组所连接的电源线(4)，位于所述第一子像素组所连接的两根数据线(3)之间，所述第一子像素组为所述多个子像素组中的任意一个。
  9. 根据权利要求2至8任一项所述的透明OLED显示面板，还包括多根感测线(5)，所述感测线(5)沿所述第一方向(x)延伸，每个子像素组中的所述第一子像素(111)和所述第二子像素(112)与同一根所述感测线(5)连接。
  10. 根据权利要求9所述的透明OLED显示面板，其中，第二子像素组所连接的感测线(5)位于所述第二子像素组所连接的两根所述数据线(3)之间，所述第二子像素组为所述多个子像素组中的任意一个。
  11. 根据权利要求2至10任一项所述的透明OLED显示面板，其中，所述子像素(1)包括第一薄膜晶体管(T1)、第二薄膜晶体管(T2)、电容(c)和OLED(d)，
    所述第一薄膜晶体管(T1)的栅极与对应的所述栅线(2)电连接，所述第一薄膜晶体管(T1)的源极与对应的所述数据线(3)电连接，所述第一薄膜晶体管(T1)的漏极与所述第二薄膜晶体管(T2)的栅极以及所述电容(c)的一端电连接；
    所述第二薄膜晶体管(T2)的漏极与对应的所述电源线(4)电连接，所述第二薄膜晶体管(T2)的源极与所述OLED(d)的阳极电连接；所述OLED(d)的阳极与所述电容(c)的另一端电连接。
  12. 根据权利要求11所述的透明OLED显示面板，其中，所述子像素(11)还包括第三薄膜晶体管(T3)，位于同一排的子像素(11)的第三薄膜晶体管(T3)的栅极连接同一根栅线(2)，且对于任意一排子像素(11)，所述第三薄膜晶体管(T3)和所述第一薄膜晶体管(T1)所连接的栅线(2)不同；
    所述第三薄膜晶体管(T3)的漏极与所述电容(c)的另一端、所述第二薄膜晶体管(T2)的源极电连接，所述第三薄膜晶体管(T3)的源极与感测线(5)电连接。
  13. 根据权利要求12所述的透明OLED显示面板，其中，所述子像素(11)包括依次层叠在衬底基板(1101)上的有源层(1102)、栅极绝缘层(1103)、第一电极层(1104)、层间绝缘层(1105)、第二电极层(1106)、钝化层(1107)和阳极金属层(1108)，所述阳极金属层(1108)和所述第二电极层(1106)之间通过过孔(12)连接。
  14. 根据权利要求13所述的透明OLED显示面板，其中，所述第二薄膜晶体管(T2)的源极位于所述有源层(1102)，所述第三薄膜晶体管(T3)的漏极位于所述有源层(1102)。
  15. 根据权利要求13或14所述的透明OLED显示面板，其中，每个所述子像素(11)还包括平坦化层(1109)、缓冲层(1110)中的至少一种，所述平坦化层(1109)位于所述钝化层(1107)和所述阳极金属层(1108)之间，所述缓冲层(1110)位于所述基板(1101)和所述有源层(1102)之间。
  16. 根据权利要求11至15任一项所述的透明OLED显示面板，其中，所述透明区域(a)的显示面板包括衬底基板(1101)、以及依次层叠在衬底基板(1101)上的栅极绝缘层(1103)、层间绝缘层(1105)和钝化层(1107)。
  17. 一种显示装置，包括如权利要求1至16任一项所述的透明OLED显示面板。
  18. 一种透明OLED显示面板的制备方法，包括：
    在衬底基板上形成多个像素和多根数据线，得到具有多个透明区域以及多个显示区域的透明OLED显示面板，所述多个透明区域和所述多个显示区域在第一方向上交替布置；
    所述多个像素位于所述显示区域，位于同一所述显示区域中的多个像素沿第二方向排列，所述数据线沿所述第一方向延伸，所述第一方向与所述第二方向相交；
    所述像素包括多个子像素，位于同一所述显示区域中的所述子像素包括一排第一子像素和一排第二子像素，所述一排第一子像素包括沿所述第二方向排列的多个第一子像素，所述一排第二子像素包括沿所述第二方向排列的多个第二子像素，所述像素至少包括在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素；
    同一所述显示区域中，在所述第一方向上相邻的一个所述第一子像素和一个所述第二子像素与同一根所述数据线相连，且不同的所述第一子像素所连接的所述数据线不同。
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CN110718575A (zh) * 2019-10-22 2020-01-21 京东方科技集团股份有限公司 透明oled显示面板、显示装置和驱动方法

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