WO2021249105A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021249105A1
WO2021249105A1 PCT/CN2021/093629 CN2021093629W WO2021249105A1 WO 2021249105 A1 WO2021249105 A1 WO 2021249105A1 CN 2021093629 W CN2021093629 W CN 2021093629W WO 2021249105 A1 WO2021249105 A1 WO 2021249105A1
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WIPO (PCT)
Prior art keywords
sub
pixels
pixel
line
transistor
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PCT/CN2021/093629
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English (en)
French (fr)
Inventor
李蒙
李永谦
许晨
王景泉
张大成
王玉
袁志东
邱振华
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/772,955 priority Critical patent/US20240161687A1/en
Publication of WO2021249105A1 publication Critical patent/WO2021249105A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • a transparent organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel refers to a display panel that uses organic light-emitting materials to achieve display functions and has a see-through effect. Users can see the image displayed in the transparent OLED display panel and the transparent OLED at the same time The scene behind the display panel.
  • OLED Organic Light-Emitting Diode
  • the embodiments of the present disclosure provide a display substrate and a display device.
  • a display substrate is provided, and the display substrate includes:
  • the base substrate has a plurality of transparent areas and display areas alternately arranged at intervals along the first direction;
  • a plurality of pixels are on the base substrate and located in the display area, the pixels in the display area are arranged along a second direction, the pixels include a plurality of sub-pixels, and the sub-pixels in the pixels are divided into 2 rows of the sub-pixels, each row of the sub-pixels are arranged along the first direction, and the first direction and the second direction intersect;
  • a plurality of gate lines and a plurality of data lines are located on the base substrate, the plurality of gate lines extend in a first direction, and the plurality of data lines extend in a second direction;
  • the plurality of sub-pixels of the first pixel are connected to the same gate line, and the gate line connected to the plurality of sub-pixels of the first pixel is located in the two rows of the sub-pixels of the first pixel In between, the first pixel is any one of the plurality of pixels.
  • the gate line corresponding to the first pixel includes a first gate line and a second gate line, a plurality of the sub-pixels of the first pixel are respectively connected to the first gate line, and the second gate line A plurality of the sub-pixels of a pixel are respectively connected to the second gate line;
  • the first gate line and the second gate line are both located between the two rows of the sub-pixels of the first pixel.
  • the sub-pixels in the pixels are divided into two groups of the sub-pixels;
  • the first pixel corresponds to a plurality of the data lines, and the plurality of sub-pixels of the first pixel are respectively connected to different data lines;
  • the plurality of data lines are located between the two groups of the sub-pixels of the first pixel, and each group of the sub-pixels are arranged along the second direction.
  • the display substrate further includes:
  • a plurality of power signal lines extending along the second direction
  • the multiple sub-pixels of the first pixel are connected to the same power signal line, and the power signal line connected to the multiple sub-pixels of the first pixel is located between the two groups of the sub-pixels of the first pixel .
  • two data lines connected to a group of sub-pixels of the first pixel are respectively arranged.
  • the data lines on the first side of the power signal line are respectively connected to a group of sub-pixels on the first side of the power signal line, and the first side of the power signal line is the power signal Either side of the line.
  • the sub-pixel includes an active layer, a first electrode layer, and a second electrode layer that are sequentially stacked and insulated from each other, and the first electrode layer and the second electrode layer are a gate layer, a source and drain layer, respectively.
  • the first electrode layer and the second electrode layer are a gate layer, a source and drain layer, respectively.
  • the power signal line includes two sub-layers, and the two sub-layers are respectively the same layer as the first electrode layer and the second electrode layer.
  • the display substrate further includes:
  • a plurality of sensing lines extending along the second direction
  • the plurality of sub-pixels of the first pixel are connected to the same sensing line, and the sensing line connected to the plurality of sub-pixels of the first pixel is located between the first pixel and the adjacent Between pixels.
  • the display substrate further includes:
  • a plurality of sensing wires, and the plurality of sub-pixels of the first pixel are respectively connected to the sensing wires through the sensing wires.
  • the display substrate further includes:
  • the light-shielding pattern is located on the base substrate;
  • the sensing lead and the light shielding pattern are in the same layer.
  • the sub-pixel includes a 3T1C pixel circuit and a light-emitting unit;
  • the 3T1C pixel circuit includes a first transistor, a second transistor, a third transistor and a capacitor;
  • the control electrode of the first transistor is electrically connected to the first gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second electrode.
  • the control electrode of the transistor is electrically connected to one end of the capacitor, the first electrode of the second transistor is electrically connected to the power signal line, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor.
  • the other end of the capacitor is electrically connected to the light emitting unit, the control electrode of the third transistor is electrically connected to the second gate line, and the first electrode of the third transistor is electrically connected to the sensing line.
  • the plurality of sub-pixels included in the pixel are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.
  • a display device in another aspect, includes the display substrate as described in any one of the preceding items.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a partial enlarged structure of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a circuit diagram of a sub-pixel provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a partial enlarged structure of a display substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a cross-sectional view of a sub-pixel provided by an embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of a part of the film structure in a sub-pixel
  • FIG. 7 is a schematic diagram of the structure of the first electrode layer in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of the structure of a second electrode layer in an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the structure of an active layer in an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the structure of a light shielding layer in an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a manufacturing process of a transparent OLED display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a driving timing diagram of a display stage provided by an embodiment of the present disclosure.
  • FIG. 13 is a driving timing diagram of a sensing phase provided by an embodiment of the present disclosure.
  • OLED display panels can be divided into passive matrix driving organic light-emitting diodes (English: Passive Matrix Driving OLED, abbreviated as: PMOLED) and AMOLED according to driving methods.
  • PMOLED Passive Matrix Driving OLED
  • AMOLED AMOLED according to driving methods.
  • the solution provided in this application is mainly applied to AMOLED display panels.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes: a base substrate 10, a plurality of pixels 1, a plurality of gate lines 2 and a plurality of data lines 3.
  • the base substrate 10 has a plurality of transparent regions a and display regions b alternately arranged at intervals along the first direction A;
  • a plurality of gate lines 2 and a plurality of data lines 3 are located on the base substrate 10, the plurality of gate lines 2 extend in a first direction A, and the plurality of data lines 3 extend in a second direction B;
  • the plurality of sub-pixels 11 of the first pixel 1a are connected to the same gate line 2, and the gate line 2 connected to the plurality of sub-pixels 11 of the first pixel 1a is located in the first pixel 1a Between the two rows of the sub-pixels 11, the first pixel 1a is any one of the plurality of pixels 1.
  • the scene behind the display panel can be seen through the transparent area a, and the display area b displays images by controlling the OLED to emit light.
  • each sub-pixel When the display panel is working, each sub-pixel obtains a scan signal through the connected gate line, and obtains a data signal through the connected data line. Under the action of the scan signal and the data signal, the corresponding OLED is driven to emit light.
  • different rows of sub-pixels are respectively configured with gate lines, and each row of sub-pixels is connected to different gate lines.
  • this method leads to a larger area of the display area occupied by the gate line, resulting in a small number of sub-pixels that can be set, and low resolution.
  • the gate line occupies a larger area of the transparent area when the gate line passes through the transparent area, resulting in a transparent area.
  • the ratio in the display panel is not high.
  • four sub-pixels of a pixel are connected to the same gate line, which reduces the number of gate lines, reduces the area of the transparent area occupied by the gate lines, and can increase the ratio of the transparent area in the display panel; at the same time,
  • the gate line is designed between the 2 rows of sub-pixels, which is convenient for routing and can also ensure the uniformity of the signal provided by the gate line to each sub-pixel; in addition, the area of the display area occupied by the gate line is reduced, and the display panel can be arranged on the display panel. Deploy more sub-pixels to improve resolution.
  • the plurality of gate lines 2 are parallel to each other, and the plurality of data lines 3 are parallel to each other.
  • the first direction A is horizontal
  • the second direction B is vertical
  • a row of sub-pixels are arranged in the horizontal direction, that is, a row of sub-pixels, and a group of sub-pixels are arranged in the vertical direction.
  • a column of sub-pixels which is a column of sub-pixels.
  • a plurality of pixels are arranged along the column direction to form a column of pixels.
  • the horizontal direction is the first direction
  • the vertical direction is the second direction for exemplary description.
  • the first direction A may be vertical and the second direction B may be horizontal. Accordingly, a row of sub-pixels are arranged in the vertical direction, and a group of sub-pixels are arranged in the horizontal direction.
  • the sub-pixels 11 in the pixel 1 are divided into two groups of the sub-pixels 11.
  • the sub-pixels in each pixel 1 can be divided into 2 rows and 2 groups, that is, the pixel 1 includes 4 sub-pixels 11 arranged in a square shape, as shown in FIG. 1.
  • the sub-pixels 11 in the pixel 1 can also be divided into three or more groups of sub-pixels 11, or any two rows of sub-pixels 11 are staggered with each other, so that the sub-pixels 11 in the pixel 1 are not arranged in groups. .
  • FIG. 2 is a schematic diagram of a partial enlarged structure of a display substrate provided by an embodiment of the present disclosure.
  • each pixel 1 includes a plurality of sub-pixels 11, and the sub-pixels 11 in each pixel 1 are divided into two rows of sub-pixels 11, and the arrangement direction of each row of sub-pixels 11 is along the first direction A, 2
  • One of the rows of sub-pixels 11 is the first sub-pixel 111, and the other row of the two-rows of sub-pixels 11 is the second sub-pixel 112, and each pixel 1 includes at least one first sub-pixel 111 and at least one second sub-pixel 111.
  • the sub-pixels 112, that is, the sub-pixels included in each pixel 1 are equally divided into two rows.
  • the multiple sub-pixels 11 included in the pixel 1 are red (red, R), green (green, G), blue (blue, B), and white (white, W) sub-pixels, respectively.
  • the multiple sub-pixels are arranged in a Tian shape, that is, a square arrangement.
  • the two first sub-pixels 111 are blue and red sub-pixels, respectively, and the two second sub-pixels 112 are white and green sub-pixels, respectively.
  • the display substrate provided by the embodiment of the present disclosure is an OLED display substrate.
  • the sub-pixel includes a pixel circuit and a light-emitting element, the pixel circuit is located between the base substrate and the light-emitting element; the light-emitting element includes a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence, and the second electrode is located
  • the organic light-emitting layer faces the side of the base substrate.
  • the second electrode is an anode
  • the first electrode is a cathode.
  • the pixel circuit includes at least two thin film transistors.
  • the thin film transistor includes an active layer on a base substrate, a gate layer on the side of the active layer away from the base substrate, and a gate layer The source and drain layer on the side away from the base substrate, etc.
  • top-gate thin film transistors are used as examples.
  • the thin film transistors can also be bottom-gate thin film transistors or double-gate thin film transistors, which are not limited in the present disclosure.
  • the pixel circuit includes 2T1C circuit, 3T1C circuit, 7T1C circuit, etc.
  • the 2T1C circuit usually can only achieve a relatively simple light emission control function.
  • the 3T1C circuit can also use external compensation technology to control the thin film in the pixel circuit.
  • the transistor compensates and improves the display quality. Due to the complex structure of the 7T1C circuit, when used in a transparent OLED display, the area of the transparent area will be too small and the resolution will be lower at the same time.
  • the 3T1C circuit is selected as the pixel circuit in the transparent OLED.
  • T is a transistor and C is a capacitor.
  • FIG. 3 is a circuit diagram of a sub-pixel provided by an embodiment of the present disclosure.
  • the sub-pixel 11 includes a 3T1C pixel circuit 113 and a light emitting unit 114.
  • the 3T1C pixel circuit 113 includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C.
  • the control electrode of the first transistor T1 is electrically connected to the first gate line 21, the first electrode of the first transistor T1 is electrically connected to the data line 3, and the second electrode of the first transistor T1 is respectively Is electrically connected to the control electrode of the second transistor T2 and one end of the capacitor C, the first electrode of the second transistor T2 is electrically connected to the power supply signal line (VDD line) 4, and the first electrode of the second transistor T2
  • the two poles are respectively electrically connected to the second pole of the third transistor T3, the other end of the capacitor C, and the light emitting unit 114, and the control electrode of the third transistor T3 is electrically connected to the second gate line 22 ,
  • the first pole of the third transistor T3 is electrically connected to the sensing line (SENSE line) 5.
  • the transistor is a thin film transistor
  • the control electrode of the thin film transistor is a gate electrode
  • the first electrode and the second electrode may be one of the source electrode and the drain electrode, respectively.
  • the light-emitting unit 114 is an organic light-emitting diode, the anode of the organic light-emitting diode is connected to the other end of the capacitor c, and the cathode of the organic light-emitting diode is connected to the common power line (VSS line) 6.
  • VSS line common power line
  • the control electrode of the first transistor T1 obtains the scan signal from the first gate line 21
  • the first electrode of the first transistor T1 obtains the data signal from the data line 3
  • the data is transmitted through the second electrode of the first transistor T1.
  • the signal is output to the control electrode of the second transistor T2, and the first electrode of the second transistor T2 obtains a power signal from the power signal line 4 to drive the organic light emitting diode connected to the second electrode of the second transistor T2 to emit light.
  • the voltage difference between the anode and the cathode of the light-emitting diode should maintain the theoretical voltage difference.
  • the power supply The voltage generates a voltage drop, so that the voltage difference actually applied to the two ends of the light-emitting diode is different from the theoretical voltage difference between the two ends, which affects the display effect of the transparent OLED display panel.
  • the compensation voltage of the voltage difference can be calculated by setting an external compensation circuit controlled by the third transistor T3.
  • the first gate line 21 and the second gate line 22 simultaneously control the first transistor T1 and the third transistor T3 to turn on, and the data line 3 provides a low-level signal for the sub-pixels (the low-level signal is lower than the first The turn-on voltage of the second thin film crystal T2, for example, 2V).
  • the second thin film transistor T2 is not turned on, and the data line 3 charges the sensing line 5 through the capacitor C and the third transistor T3, thereby causing the external integrated circuit (Integrated Circuit (IC) can calculate the compensation voltage of the sub-pixel based on the electrical signal obtained by the sensing line 5.
  • IC Integrated Circuit
  • FIG. 4 is a schematic diagram of a partial enlarged structure of a display substrate provided by an embodiment of the present disclosure.
  • the gate line 2 corresponding to the first pixel 1a includes a first gate line 21 and a second gate line 22, and the first transistors T1 in the plurality of sub-pixels 11 of the first pixel 1a are respectively connected
  • the first gate line 21, the third transistors T3 in the plurality of sub-pixels 11 of the first pixel 1a are respectively connected to the second gate line 22; the first gate line 21 and the second gate line 21
  • the gate lines 22 are all located between the two rows of the sub-pixels 11 of the first pixel 1a.
  • the two gate lines are both arranged between the two rows of sub-pixels 11, and there is no need to configure gate lines for the two rows of sub-pixels (if gate lines are respectively configured for the two rows of sub-pixels, a total of 4
  • the number of gate lines is reduced, and the area of the transparent area and the display area occupied by the gate lines is reduced.
  • the first pixel 1a corresponds to a plurality of the data lines 3, and the plurality of sub-pixels 11 of the first pixel 1a are respectively connected to different data lines 3, that is, a plurality of sub-pixels 11 Connect with multiple data lines 3 in one-to-one correspondence.
  • a plurality of the data lines 3 are located between the two groups of the sub-pixels 11 of the first pixel 1 a, and each group of the sub-pixels 11 are arranged along the second direction B.
  • each sub-pixel in the same pixel is driven by a data line.
  • a square-shaped arrangement it can be ensured that the four sub-pixels in a pixel can emit light at the same time without time-sharing driving. Ensure that the scanning time of a row of pixels is short, so that the solution can be applied to large-size, high-resolution display screens.
  • the display substrate may further include: multiple power signal lines 4 (only one is shown in the figure).
  • the power signal line 4 extends along the second direction B; the multiple sub-pixels 11 of the first pixel 1a are connected to the same power signal line 4, and the multiple sub-pixels 11 of the first pixel 1a are connected to the The power signal line 4 is located between the two groups of the sub-pixels 11 of the first pixel 1a.
  • four sub-pixels of one pixel together with one power signal line 4 can greatly reduce the number of power signal lines and the area of the display area occupied by the power signal lines, so that they can be arranged on the display panel. Deploy more sub-pixels to improve resolution.
  • arranging the power signal line 4 between the two groups of the sub-pixels 11, on the one hand facilitates the connection of multiple sub-pixels with the power signal line 4, and on the other hand, it can also ensure that the power signal line provides signals to the multiple sub-pixels. Uniformity.
  • the power signal line 4 is used to provide power to the OLED in the transparent OLED display panel.
  • two data lines 3 connected to the two sub-pixels 11 of the first pixel 1a are respectively arranged.
  • This design method ensures that the power signal line is in the middle of the two groups of sub-pixels 11, and further ensures the uniformity of the signal provided by the power signal line to multiple sub-pixels.
  • the data line 3 located on the first side of the power signal line 4 is respectively connected to a group of sub-pixels 11 located on the first side of the power signal line 4, and the power signal line 4 The first side is either side of the power signal line 4.
  • the sub-pixel 11 located in the upper left corner is connected to the leftmost data line among the four data lines
  • the sub-pixel 11 located in the lower left corner is connected to the second data line from left to right among the four data lines.
  • the sub-pixel 11 located in the lower right corner is connected to the third data line from left to right from the four data lines
  • the sub-pixel 11 located in the upper right corner is connected to the rightmost data line among the four data lines. That is, the four sub-pixels 11 are respectively connected to the four data lines from left to right in a counterclockwise order.
  • This kind of wiring arrangement scheme can reduce the perforation and winding design between metal wires, thereby improving the production yield of products.
  • the two groups of sub-pixels 11 are brought close to the two corresponding data lines 3 to avoid data
  • the line 3 is connected to the sub-pixel 11 across the power signal line 4, which facilitates wiring and improves production efficiency.
  • the display substrate may further include: a plurality of sensing lines 5 (only one is shown in the figure).
  • the sensing line 5 extends along the second direction B; the plurality of sub-pixels 11 of the first pixel 1a are connected to the same sensing line 5, and are connected to the plurality of sub-pixels of the first pixel 1a.
  • the sensing line 5 connected to the pixel 11 is located between the first pixel 1 a and the adjacent pixel 1. That is, the sensing line 5 is located on one side of the first pixel 1a.
  • multiple sub-pixels 11 in each pixel are connected to the same sensing line 5, and multiple sub-pixels 11 share one sensing line 5.
  • the sensing line 5 is used to sense electrical signals in the sub-pixels.
  • the sensing line 5 may also be used to transmit a compensation voltage signal of an external compensation circuit. It can also be considered that, in each display area b, two adjacent groups of sub-pixels 11 are commonly connected to one sensing line 5. Since the compensation voltage of any sub-pixel 11 can be calculated separately by adjusting the voltage of the level signal of each data line 3, each group of pixels 1 only needs to pass through one sensing line 5 to communicate with all sub-pixels. Pixel connection can meet the requirements, and there is no need to arrange multiple sensing lines 5. The area of the display area b occupied by the sensing line 5 is reduced, and more sub-pixels 11 can be arranged in the display area b to improve the resolution.
  • the display substrate may further include: a plurality of common power lines 6 (only one is shown in the figure).
  • the common power line 6 extends along the second direction B; the plurality of sub-pixels 11 of the first pixel 1a are connected to the same common power line 6, and are connected to the plurality of sub-pixels of the first pixel 1a.
  • the common power line 6 to which the pixel 11 is connected is located between the first pixel 1 a and another adjacent pixel 1. That is, the sensing line 5 and the common power line 6 are respectively located on both sides of the first pixel 1a.
  • a common power line 6 is used to connect multiple sub-pixels in a group of pixels, which reduces the area of the display area b occupied by the common power line 6, and can arrange more sub-pixels 11 in the display area b to improve the resolution.
  • the common power line 6 is located on the side of the display area b close to the transparent area a.
  • each sub-pixel 11 includes a base substrate 10, a light-shielding layer 1101, an active layer 1102, a gate insulating layer 1103, a first electrode layer 1104, an interlayer insulating layer 1105, and a second electrode layered in sequence.
  • the layer 1106 and the passivation layer 1107, the source S3 of the third thin film transistor T3 in the second electrode layer 1106 and the active layer 1102 are connected by the via hole 12, which is located in the part of the common power line 6 of the second electrode layer 1106
  • the portion of the common power line 6 located on the first electrode layer 1104 is connected through the via 13 to form the double-layer common power line 6 in FIG. 4.
  • the first electrode layer 1104 is isolated from the active layer 1102 by the gate insulating layer 1103.
  • the base substrate is a transparent substrate, such as a glass substrate or the like.
  • the material of the active layer 1102 may be at least one of InGaZnO, InGaO, ITZO, and AlZnO.
  • the gate insulating layer 1103 and the interlayer insulating layer 1105 can be made of insulating materials such as silicon nitride and silicon oxide.
  • the material of the passivation layer 1107 is a composite layer structure composed of any combination of two or more of silicon oxide, silicon nitride, and silicon nitride compound.
  • the light-shielding layer 1101, the first electrode layer 1104, and the second electrode layer 1106 are metal layers, such as Al (aluminum), Cu (copper), Mo (molybdenum), Cr (chromium), Ti (titanium), etc., or alloys Electrode layer.
  • an anode layer (not shown in the figure) is further provided on the passivation layer 1107, the anode layer is connected to the source S3 of the third thin film transistor T3 through a via hole, and the anode layer is a metal layer or a conductive thin film layer.
  • each sub-pixel 11 further includes at least one of a planarization layer 1109 and a buffer layer 1110.
  • the planarization layer 1109 is located between the passivation layer 1107 and the anode layer, and the buffer layer 1110 is located between the base substrate 10 and the active layer.
  • the buffer layer 1110 is usually a layer of SiO 2 and SiN x , which can prevent metal ions in the glass substrate from entering the polysilicon and affecting the performance of the thin film transistor.
  • the planarization layer 1109 is usually a resin layer to ensure the flatness between the metal anode of the light emitting diode and the passivation layer 1107.
  • the anode layer and the active layer 1102 may also be directly connected through a via hole.
  • the sub-pixels provided by the embodiments of the present disclosure further include a pixel definition layer, a light-emitting layer, and a cathode layer. The structure of these layers can be referred to related technologies, and detailed descriptions are omitted here.
  • the first electrode layer 1104 is a gate layer
  • the second electrode layer 1106 is a source and drain layer.
  • the transparent region a includes a base substrate 10, a gate insulating layer 1103, an interlayer insulating layer 1105, and a passivation layer 1107 that are sequentially stacked.
  • the base substrate 10, the gate insulating layer 1103, the interlayer insulating layer 1105, and the passivation layer 1107 in the transparent area a and the corresponding film layers in the display area b can be fabricated at the same time and arranged in the same layer. The difference may be that there are some The thickness of the film layer is different.
  • the thickness of the gate insulating layer 1103 and the interlayer insulating layer 1105 in the transparent area a are greater than the same film layer in the display area b.
  • the thickness of the gate insulating layer 1103 in the transparent area a is greater than The thickness of the gate insulating layer 1103 in the display area b.
  • FIG. 6 shows a schematic diagram of a part of the film structure in the sub-pixel.
  • the structures of the light shielding layer 1101, the active layer 1102, the first electrode layer 1104, and the second electrode layer 1106 are mainly shown.
  • G1 is the gate of the first transistor T1
  • D1 is the drain of the first transistor T1
  • S1 is the source of the first transistor T1
  • G2 is the gate of the second transistor T2
  • D2 is the gate of the second transistor T2
  • G3 is the gate of the third transistor T3, D3 is the drain of the third transistor T3, and S3 is the source of the third transistor T3.
  • the small squares in the figure indicate connections through vias.
  • the power signal line 4 of the second electrode layer is connected to the first electrode layer through the via hole, thereby forming a power signal line 4 of double-layer wiring.
  • FIG. 6 only shows the vias of the sub-pixels located in the upper left corner, and the vias of other sub-pixels are similar.
  • FIG. 7 is a schematic diagram of the structure of the first electrode layer in an embodiment of the present disclosure.
  • the first electrode layer 1104 is a gate layer, and the first electrode layer 1104 may include gate lines 2, for example, including the aforementioned first gate line 21 and second gate line 22, and thin film transistors in each sub-pixel.
  • the first electrode layer 1104 may further include a connection line 41 connecting the drain D2 of the second transistor T2 and the power signal line 4.
  • FIG. 8 is a schematic diagram of the structure of the second electrode layer in an embodiment of the present disclosure.
  • the second electrode layer 1106 is a source and drain layer, and the second electrode layer 1106 includes multiple data lines 3, power signal lines 4, sensing lines 5, common power lines 6, and a plate of capacitor C. C1, and the source and drain of each thin film transistor, such as the source S1 and drain D1 of the first thin film transistor T1, the source S2 and drain D2 of the second thin film transistor T2, and the source of the third thin film transistor T3 Pole S3 and drain D3.
  • FIG. 9 is a schematic diagram of the structure of an active layer in an embodiment of the present disclosure.
  • the active layer includes a part of the transistors through metallization to form conductors, which are connected to the second electrode layer to become the source S1 of the first transistor T1, the source S2 of the second transistor T2, and the third Part of the source S3 of the transistor T3.
  • another plate C2 of the capacitor C is formed.
  • FIG. 10 is a schematic diagram of the structure of a light shielding layer in an embodiment of the present disclosure.
  • the light shielding layer 1101 includes a light shielding pattern 7 and a sensing lead 50.
  • the plurality of sub-pixels 11 of the first pixel 1 a are respectively connected to the sensing line 5 through the sensing lead 50.
  • the light shielding pattern 7 is electrically connected to the source S2 of the second transistor T2 through a via hole, so as to prevent the metal light shielding pattern 7 from being in a floating state.
  • the connection point 70 of the light shielding pattern 7 is electrically connected to the source S2 of the second transistor T2 through a via hole.
  • the first gate line 21 is directly connected to the gate G1 of the first thin film transistor T1; as shown in FIG. 8, the data line 3 is directly connected to the drain D1 of the first thin film transistor T1; As shown in FIG. 9, the connection point 11 a on the source S1 of the first thin film transistor T1 in the second electrode layer 1106 is connected to a plate C2 of the capacitor C in the active layer 1102 through a via.
  • connection point 11b on the gate G2 of the second thin film transistor T2 is connected to a plate C2 of the capacitor C located in the active layer 1102 through a via; as shown in FIGS. 7 and 8
  • the power signal line 4 in the first electrode layer 1104 is connected to the connection line 41
  • the connection point 11c of the connection line 41 is connected to the drain D2 of the second thin film transistor T2 in the second electrode layer 1106 through a via hole.
  • the part of the power signal line 4 in the first electrode layer 1104 is connected to the part of the power signal line 4 in the second electrode layer 1106 through a plurality of via holes to form a double-layer power signal line 4; as shown in FIG.
  • the source S2 of the two thin film transistors T2 is connected to a plate C1 of the capacitor C.
  • the second gate line 22 has a connection point 11d, and the connection point 11d is connected to one end of the first wiring 11e in the second electrode layer 1106 through a via, and then the first wiring 11e The other end is connected to the gate G3 of the third thin film transistor T3 through a via; as shown in FIGS. 8 and 10, the connection point 11f of the drain D3 of the third thin film transistor T3 in the second electrode layer 1106 passes through the via Connected to the sensing lead 50 located in the light shielding layer 1101, the connection point 11g of the sensing lead 50 is connected to the sensing line 5 located in the second electrode layer 1106 through a via; as shown in FIG. 8, the third thin film transistor T3 The source S3 is connected to a plate C1 of the capacitor C.
  • the first gate line 21 provides a scan signal to the gate G1 of the first thin film transistor T1 to control the drain D1 and source S1 of the first thin film transistor T1 to conduct; the data line 3 passes through The turned-on first thin film transistor T1 writes a data signal to a plate C2 of the capacitor C.
  • One plate C2 of the capacitor C is connected to the gate G2 of the second thin film transistor T2.
  • the first thin film transistor T1 is controlled to be turned on by the scan signal, and the third thin film transistor T3 is controlled to be turned on by the scan signal provided by the second gate line 22; then the capacitor C is charged, but the gate G2 is charged. If the potential is lower than the turn-on voltage, the second thin film transistor T2 is not turned on. At this time, the capacitor C can charge the sensing line 5 through the third thin film transistor T3, so that the sensing line senses the potential of the anode of the OLED, thereby achieving subsequent External compensation.
  • the difference from the sub-pixel 11 in the upper left corner is that the second gate line 22 is directly connected to the gate G3, and the connection point 11h of the second gate line 21 is connected to the second trace 11i of the second electrode layer 1106 through a via hole.
  • the connection point 11j of the second trace 11i is connected to the gate G1 through a via hole.
  • the sub-pixel in the lower left corner corresponds to the second data line 3 from left to right.
  • the data line 3 Since there is a data line 3 between the data line 3 and the corresponding drain D1 (the first data line 3 from left to right) The data line 3), therefore, the data line 3 cannot be directly connected to the drain D1 in the corresponding sub-pixel, and needs to be connected to the drain D1 through the third wiring 11k in the first electrode layer 1104.
  • FIG. 11 is a schematic diagram of a manufacturing process of a transparent OLED display panel provided by an embodiment of the present disclosure. As shown in FIG. 11, illustratively, the preparation method of the transparent OLED display panel includes:
  • the base substrate is a transparent substrate, such as a glass substrate.
  • the light-shielding layer can be made of a metal material. On the one hand, it can play a role of light-shielding.
  • the light-shielding pattern shields the part of the pixel with metal traces other than the part shielded by the corresponding metal anode to prevent light leakage; On the other hand, it can be multiplexed as metal traces, such as the aforementioned sensing leads.
  • the structure of the light-shielding layer refer to the previous description of FIG. 10.
  • an active material film may be formed on the light shielding layer first.
  • a deposition method can be used to form a thin film of active material on the base substrate.
  • the active material film may be at least one of InGaZnO, InGaO, ITZO, and AlZnO.
  • the active material film is processed through a patterning process to obtain a pattern of the active layer 1102.
  • a part of the area in the active layer 1102 can be metalized, so that the metalized area forms the source of the transistor.
  • the metallization treatment can adopt the following methods: treating in a reducing atmosphere at 100°C to 300°C for 30 minutes to 120 minutes, and the reducing atmosphere includes hydrogen gas or hydrogen-containing plasma.
  • the reduction reaction occurs in a reducing atmosphere of 100°C ⁇ 300°C for 30min ⁇ 120min, which can ensure to the greatest extent that the area of the active material film that is not covered by the etching barrier layer can be fully and effectively reduced to metal oxide conductor.
  • the temperature is too low, the reduction effect of the reduction reaction will be affected, and the reaction time will be prolonged, reducing production efficiency; if the temperature is too high, it is easy to remove the raw material film covered by the etching barrier layer without metallization The treated area is chemically affected, thereby affecting the structural properties; similarly, if the time is too short, the reduction reaction will not proceed sufficiently, if the time is too long, the reaction time will be prolonged and the production efficiency will be reduced.
  • the gate insulating layer 1103 may be formed by vapor deposition.
  • the gate insulating layer 1103 can be made of insulating materials such as silicon nitride and silicon oxide.
  • S105 forming an interlayer insulating layer on the first electrode layer.
  • the formation method of the interlayer insulating layer 1105 may be the same as that of the gate insulating layer 1103.
  • the material of the passivation layer 1107 is a composite layer structure formed by any combination of two or more of silicon oxide, silicon nitride, and silicon nitride compound.
  • S108 An anode layer is formed on the passivation layer.
  • the anode layer communicates with the second electrode layer 1106 through the via hole 12.
  • via holes may also be formed on the formed interlayer insulating layer 1105 and the passivation layer 1107.
  • each sub-pixel 11 further includes at least one of a planarization layer 1109 and a buffer layer 1110.
  • the planarization layer 1109 is located between the passivation layer 1107 and the anode layer, and the buffer layer 1110 is located between the base substrate 10 and the active layer.
  • the buffer layer 1110 is usually a layer of SiO 2 and SiN x , which can prevent metal ions in the glass substrate from entering the polysilicon and affecting the performance of the thin film transistor.
  • the planarization layer 1109 is usually a resin layer to ensure the flatness between the metal anode of the light emitting diode and the passivation layer 1107.
  • An embodiment of the present disclosure provides a display device, including a transparent OLED display panel as described in FIGS. 1 to 10.
  • the gate lines are designed Between the two rows of sub-pixels, it is convenient for wiring, and can also ensure the uniformity of the signal provided by the gate line to each sub-pixel; in addition, the area of the display area occupied by the gate line is reduced, and more arrangements can be made on the display panel The sub-pixels to improve the resolution.
  • the display device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, and the like.
  • the embodiment of the present disclosure also provides a driving method of the OLED display panel as shown in FIGS. 1 to 10. Taking a row of sub-pixels arranged in the row direction and a group of sub-pixels arranged in the column direction as an example, the OLED display panel displays pictures frame by frame during operation. During the display of each frame, the display is performed in a line-by-line scanning manner. That is, the method can include:
  • the thin film transistors used for display of each row of pixels are controlled row by row to turn on.
  • FIG. 12 is a driving timing diagram of a display stage provided by an embodiment of the present disclosure. As shown in FIG. 12, in conjunction with FIG. 1, FIG. 2 and FIG. 3, in the embodiment of the present disclosure, the pixel shown in FIG. 3 is taken as an example of the target pixel:
  • a scan signal is provided for the first gate line 21 and a data signal is provided for the data line 3.
  • a plurality of sub-pixels in the pixel all obtain scan signals, and the plurality of sub-pixels obtain data signals through respective corresponding data lines 3, thereby realizing simultaneous display of the plurality of sub-pixels.
  • the thin film transistors used for sensing of each row of pixels are controlled row by row to turn on.
  • the external integrated circuit can calculate the compensation value to compensate the voltage of the sub-pixel.
  • FIG. 13 is a driving timing diagram of a sensing phase provided by an embodiment of the present disclosure. As shown in Fig. 13, combining Fig. 1, Fig. 2 and Fig. 3, taking the red first sub-pixel as the target sub-pixel as an example:
  • a scan signal is provided for the first gate line 21 and the second gate line 22, and the first transistor T1 and the third transistor T3 are turned on.
  • the data line 3 provides a first low-level signal for the red first sub-pixel.
  • the low-level signal is lower than the turn-on voltage of the second thin film crystal T2 of the first sub-pixel, for example, 2V, so the second transistor T2 is not turned on. .
  • the low-level signal provided by the data line 3 enters the sensing line 5 through the capacitor C and the third transistor T3.
  • the red first sub-pixel charges the sensing line 5, so that the sensing line senses the potential of the OLED anode , And then the compensation voltage of the first sub-pixel can be calculated.
  • the data line 3 corresponding to the blue first sub-pixel will provide the second low-level signal to the blue first sub-pixel, so that the blue first sub-pixel is corresponding The sensing line 5 is charged.

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Abstract

本公开提供了一种显示基板及显示装置，属于显示技术领域。显示基板包括：衬底基板，具有多个沿第一方向间隔交替设置的透明区域和显示区域；多个像素，在衬底基板上且位于显示区域，显示区域中的像素沿第二方向排列，像素包括多个子像素，像素中的子像素分为2排子像素，每排子像素均沿着第一方向排列，第一方向和第二方向相交；多根栅线和多根数据线，位于衬底基板上，多根栅线沿第一方向延伸，多根数据线沿第二方向延伸；第一像素的多个子像素连接相同的栅线，与第一像素的多个子像素连接的栅线位于第一像素的2排子像素之间，第一像素为多个像素中的任一个。

Description

显示基板及显示装置
本公开要求于2020年6月9日提交的申请号为202010520235.9、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及显示装置。
背景技术
透明有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板是指使用有机发光材料实现显示功能，且具有透视效果的显示面板，使用者可以同时看到透明OLED显示面板中显示的影像及透明OLED显示面板背后的景象。
发明内容
本公开实施例提供了一种显示基板及显示装置。
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板，具有多个沿第一方向间隔交替设置的透明区域和显示区域；
多个像素，在所述衬底基板上且位于所述显示区域，所述显示区域中的像素沿第二方向排列，所述像素包括多个子像素，所述像素中的所述子像素分为2排所述子像素，每排所述子像素均沿着所述第一方向排列，所述第一方向和所述第二方向相交；
多根栅线和多根数据线，位于所述衬底基板上，所述多根栅线沿第一方向延伸，所述多根数据线沿第二方向延伸；
第一像素的多个所述子像素连接相同的所述栅线，与所述第一像素的多个所述子像素连接的所述栅线位于所述第一像素的2排所述子像素之间，所述第一像素为所述多个像素中的任一个。
可选地，所述第一像素对应的所述栅线包括第一栅线和第二栅线，所述第一像素的多个所述子像素分别连接所述第一栅线，所述第一像素的多个所述子像素分别连接所述第二栅线；
所述第一栅线和所述第二栅线均位于所述第一像素的2排所述子像素之间。
可选地，所述像素中的所述子像素分为2组所述子像素；
所述第一像素对应多根所述数据线，所述第一像素的多个所述子像素分别连接不同的所述数据线；
多根所述数据线位于所述第一像素的2组所述子像素之间，每组所述子像素均沿着所述第二方向排列。
可选地，所述显示基板还包括：
多根电源信号线，沿所述第二方向延伸；
所述第一像素的多个子像素连接同一根所述电源信号线，与所述第一像素的多个子像素连接的所述电源信号线位于所述第一像素的2组所述子像素之间。
可选地，与所述第一像素的多个子像素连接的所述电源信号线的每一侧，分别布置有与所述第一像素的1组子像素连接的2根数据线。
可选地，位于所述电源信号线的第一侧的数据线，分别连接位于所述电源信号线的第一侧的1组子像素，所述电源信号线的第一侧为所述电源信号线的任一侧。
可选地，所述子像素包括依次层叠且相互绝缘的有源层、第一电极层和第二电极层，所述第一电极层和第二电极层分别为栅极层、源漏极层中的一个；
所述电源信号线包括两个子层，所述两个子层分别与所述第一电极层和所述第二电极层同层。
可选地，所述显示基板还包括：
多根感测线，沿所述第二方向延伸；
所述第一像素的多个所述子像素连接同一根所述感测线，与所述第一像素的多个所述子像素连接的所述感测线位于所述第一像素与相邻像素之间。
可选地，所述显示基板还包括：
多根感测引线，所述第一像素的多个所述子像素分别通过所述感测引线连接所述感测线。
可选地，所述显示基板还包括：
遮光图案，位于所述衬底基板上；
所述感测引线与所述遮光图案同层。
可选地，所述子像素包括3T1C像素电路和发光单元；
所述3T1C像素电路包括第一晶体管、第二晶体管、第三晶体管和电容；
所述第一晶体管的控制极与所述第一栅线电连接，所述第一晶体管的第一极与所述数据线电连接，所述第一晶体管的第二极分别与所述第二晶体管的控制极和所述电容的一端电连接，所述第二晶体管的第一极与电源信号线电连接，所述第二晶体管的第二极分别与所述第三晶体管的第二极、所述电容的另一端以及所述发光单元电连接，所述第三晶体管的控制极与所述第二栅线电连接，所述第三晶体管的第一极与感测线电连接。
可选地，所述像素包括的多个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
另一方面，提供了一种显示装置，所述显示装置包括如前任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示基板的结构示意图；
图2是本公开实施例提供的一种显示基板的局部放大结构示意图；
图3是本公开实施例提供的子像素的电路图；
图4是本公开实施例提供的一种显示基板的局部放大结构示意图；
图5是本公开实施例提供的一种子像素的剖面图；
图6示出了子像素中的部分膜层结构示意图；
图7是本公开实施例中的第一电极层的结构示意图；
图8是本公开实施例中的第二电极层的结构示意图；
图9是本公开实施例中的有源层的结构示意图；
图10是本公开实施例中的遮光层的结构示意图；
图11是本公开实施例提供的一种透明OLED显示面板的制备流程示意图；
图12是本公开实施例提供的一种显示阶段的驱动时序图；
图13是本公开实施例提供的一种感测阶段的驱动时序图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
OLED显示面板按驱动方式可分为无源矩阵驱动有机发光二极管(英文：Passive Matrix Driving OLED，简称：PMOLED)和AMOLED两种，本申请提供的方案主要应用于AMOLED显示面板。
图1是本公开实施例提供的一种显示基板的结构示意图。参见图1，所述显示基板包括：衬底基板10、多个像素1、多根栅线2和多根数据线3。
衬底基板10，具有多个沿第一方向A间隔交替设置的透明区域a和显示区域b；
多个像素1，在衬底基板10上且位于所述显示区域b，显示区域b中的像素1沿第二方向B排列，像素1包括多个子像素11，像素1中的子像素11分为2排子像素11，每排子像素11均沿着第一方向A排列，第一方向A和第二方向B相交；
多根栅线2和多根数据线3，位于衬底基板10上，所述多根栅线2沿第一方向A延伸，所述多根数据线3沿第二方向B延伸；
第一像素1a的多个所述子像素11连接相同的所述栅线2，与所述第一像素1a的多个所述子像素11连接的所述栅线2位于所述第一像素1a的2排所述子像素11之间，所述第一像素1a为所述多个像素1中的任一个。
在采用该显示基板制成的显示面板中，通过透明区域a可以看到显示面板后面的景象，而显示区域b则通过控制OLED发光来显示图像。
在显示面板工作时，每个子像素均通过相连的栅线获得扫描信号，通过相连的数据线获得数据信号，在扫描信号和数据信号的作用下，驱动对应的OLED发光。在相关技术中，不同排子像素会分别配置栅线，各排子像素连接到不同的栅线上。这种方式一方面导致栅线占用的显示区域的面积较大，导致可以设置的子像素数量少，分辨率低，同时栅线穿过透明区域时占用的透明区域的面积较多，导致透明区域在显示面板中的比例不高。而在本公开实施例中，一个像素的四个子像素连相同的栅线，减少栅线数量，减少了栅线所占用透明区域的面积，可以提高透明区域在显示面板中的比例；同时，将栅线设计在2排子像素之间，方便走线，也可以保证栅线提供给各个子像素的信号的均一性；另 外，减少了栅线所占用显示区域的面积，可以在显示面板上排布更多的子像素，提高分辨率。
示例性地，所述多根栅线2相互平行，所述多根数据线3相互平行。
示例性地，如图1所示，第一方向A为横向，第二方向B为竖向，相应地一排子像素沿横向排列，也即是一行子像素，一组子像素沿竖向排列，也即是一列子像素。在每个显示区域b中，多个像素沿列方向排布，构成一列像素。在本公开实施例中，将以横向为第一方向，竖向为第二方向进行示例性地说明。
在其他实现方式中，也可以第一方向A为竖向，第二方向B为横向，相应地一排子像素沿竖向排列，一组子像素沿横向排列。
示例性地，像素1中的子像素11分为2组所述子像素11。例如，每个像素1中的子像素可以分为2排2组，即像素1包括4个呈田字型布置的子像素11，如图1所示。
在其他实现方式中，像素1中的子像素11也可以分为3组或更多组子像素11，或者任意两排子像素11相互错开，使得像素1中的子像素11不按组排布。
图2是本公开实施例提供的一种显示基板的局部放大结构示意图。如图2所示，每个像素1均包括多个子像素11，每个像素1中的子像素11分为2排子像素11，每排子像素11的排列方向均沿第一方向A，2排子像素11中的一排为第一子像素111，2排子像素11中的另一排为第二子像素112，每个像素1均包括至少一个第一子像素111和至少一个第二子像素112，也即是每个像素1所包含的子像素均分为2排。
再次参见图2，所述像素1包括的多个子像素11分别为红色(red，R)、绿色(green，G)、蓝色(blue，B)和白色(white，W)子像素。多个子像素呈田字型排布，也即square排列。
在本公开实施例中，两个第一子像素111分别为蓝色和红色子像素，两个第二子像素112分别为白色和绿色子像素。
示例性地，本公开实施例提供的显示基板为OLED显示基板。在OLED显示基板中，子像素包括像素电路和发光元件，像素电路位于衬底基板和发光元件之间；发光元件包括依次层叠设置的第一电极、有机发光层以及第二电极，第二电极位于有机发光层面向衬底基板的一侧。其中，第二电极为阳极，第一电极为阴极。像素电路包括至少两个薄膜晶体管，以顶栅型薄膜晶体管为例，薄膜晶体管包括位于衬底基板上的有源层、位于有源层远离衬底基板一侧的栅 极层以及位于栅极层远离衬底基板一侧的源漏极层等。在后续描述中均以顶栅型薄膜晶体管为例进行说明，在其他实现方式中，薄膜晶体管也可以为底栅型薄膜晶体管或双栅型薄膜晶体管，本公开对此不做限制。
示例性地，像素电路包括2T1C电路、3T1C电路、7T1C电路等，2T1C电路通常仅能实现较为简单的发光控制功能，3T1C电路除了能够实现发光控制，还可以通过外部补偿技术，对像素电路中薄膜晶体管进行补偿，提高显示质量。7T1C电路由于结构复杂，使用在透明OLED显示中，会造成透明区域面积过小，同时导致分辨率较低。在本公开实施例中，选用3T1C电路作为透明OLED中的像素电路。其中，T为晶体管，C为电容。
下面先结合图3对本公开实施例提供的子像素的结构进行说明：
图3是本公开实施例提供的子像素的电路图。参见图3，子像素11包括3T1C像素电路113和发光单元114。
所述3T1C像素电路113包括第一晶体管T1、第二晶体管T2、第三晶体管T3和电容C。
所述第一晶体管T1的控制极与所述第一栅线21电连接，所述第一晶体管T1的第一极与所述数据线3电连接，所述第一晶体管T1的第二极分别与所述第二晶体管T2的控制极和所述电容C的一端电连接，所述第二晶体管T2的第一极与电源信号线(VDD线)4电连接，所述第二晶体管T2的第二极分别与所述第三晶体管T3的第二极、所述电容C的另一端以及所述发光单元114电连接，所述第三晶体管T3的控制极与所述第二栅线22电连接，所述第三晶体管T3的第一极与感测线(SENSE线)5电连接。
示例性地，晶体管为薄膜晶体管，薄膜晶体管的控制极为栅极，第一极和第二极可以分别为源极和漏极中的一个。
示例性地，发光单元114为有机发光二极管，有机发光二极管的阳极与电容c的另一端连接，有机发光二极管的阴极接公共电源线(VSS线)6。
在该电路中，第一晶体管T1的控制极从第一栅线21获得扫描信号，第一晶体管T1的第一极从数据线3获得数据信号，并通过第一晶体管T1的第二极将数据信号输出给第二晶体管T2的控制极，第二晶体管T2的第一极从电源信号线4获得电源信号，从而驱动与第二晶体管T2的第二极连接的有机发光二极管发光。
在OLED显示面板工作时，发光二极管的阳极和阴极之间的电压差值应当 保持理论电压差值，然而，在发光二极管的使用过程中，由于工艺条件、外界环境和使用时间等因素，导致电源电压产生压降，从而实际施加到发光二极管两端的电压差值与其两端的理论电压差值存在差异，进而影响透明OLED显示面板的显示效果。通过设置由第三晶体管T3控制的外部补偿电路可以实现对该电压差值的补偿电压进行计算。在感测阶段，第一栅线21和第二栅线22同时控制第一晶体管T1和第三晶体管T3导通，数据线3为子像素提供低电平信号(该低电平信号低于第二薄膜晶体T2的导通电压，例如2V)，此时，第二薄膜晶体管T2不导通，数据线3通过电容C和第三晶体管T3向感测线5充电，进而使得外部的集成电路(Integrated Circuit，IC)可以基于感测线5获得的电信号计算该子像素的补偿电压。
图4是本公开实施例提供的一种显示基板的局部放大结构示意图。参见图4，第一像素1a对应的所述栅线2包括第一栅线21和第二栅线22，所述第一像素1a的多个所述子像素11中的第一晶体管T1分别连接所述第一栅线21，所述第一像素1a的多个所述子像素11中的第三晶体管T3分别连接所述第二栅线22；所述第一栅线21和所述第二栅线22均位于所述第一像素1a的2排所述子像素11之间。
在该实现方式中，将两根栅线均布置在2排所述子像素11之间，无需为2排子像素分别配置栅线(如果分别为2排子像素配置栅线，则共需4条栅线)，减少了栅线数量，降低了栅线占用的透明区域及显示区域的面积。
再次参见图4，所述第一像素1a对应多根所述数据线3，所述第一像素1a的多个所述子像素11分别连接不同的所述数据线3，也即多个子像素11与多根数据线3一一对应连接。
多根所述数据线3位于所述第一像素1a的2组所述子像素11之间，每组所述子像素11均沿着所述第二方向B排列。
在该实现方式中，同一个像素中的每个子像素分别采用一根数据线驱动，在采用田字形的排布方式时，可以保证一个像素内的四个子像素可以同时发光，无需分时驱动，保证一排像素的扫描时间短，从而使得该方案可应用在大尺寸、高分辨率显示屏中。
另外，将多根数据线3均设置在2组所述子像素11之间，一方面不会影响到显示基板的透明区域，另外，可以保证多个子像素到四根数据线的走线设计简单，便于生产。
再次参见图4，所述显示基板还可以包括：多根电源信号线4(图中仅示出一根)。
电源信号线4沿所述第二方向B延伸；所述第一像素1a的多个子像素11连接同一根所述电源信号线4，与所述第一像素1a的多个子像素11连接的所述电源信号线4位于所述第一像素1a的2组所述子像素11之间。
在本公开实施例中，一个像素的四个子像素连同一根电源信号线4，可以大大减少电源信号线的数量，减少了电源信号线所占用的显示区域的面积，从而可以在显示面板上排布更多的子像素，提高分辨率。另外，将电源信号线4布置在2组所述子像素11之间，一方面便于多个子像素与该电源信号线4的相连，另一方面还能够保证电源信号线提供给多个子像素的信号均一性。
其中，电源信号线4用于为透明OLED显示面板中的OLED提供电能。
再次参见图4，与所述第一像素1a的多个子像素11连接的所述电源信号线4的每一侧，分别布置有与所述第一像素1a的1组子像素11连接的数据线3。
例如，与所述第一像素1a的4个子像素11连接的所述电源信号线4的每一侧，分别布置有与所述第一像素1a的2个子像素11连接的2根数据线3。
这种设计方式，保证了电源信号线处在2组子像素11的中间，进一步保证了电源信号线提供给多个子像素的信号均一性。
在本公开实施例中，位于所述电源信号线4的第一侧的数据线3，分别连接位于所述电源信号线4的第一侧的1组子像素11，所述电源信号线4的第一侧为所述电源信号线4的任一侧。
示例性地，在图4中，位于左上角的子像素11连接4个数据线中最左边的数据线，位于左下角的子像素11连接4个数据线中从左向右第二根数据线，位于右下角的子像素11连接4个数据线从左向右第三根数据线，位于右上角的子像素11连接4个数据线中最右边的数据线。也即是，4个子像素11按照逆时针的顺序，依次与从左到右的四根数据线分别连接。这种走线排布方案可以减少金属走线之间的打孔和绕线设计，以此提高产品制作良率。
由于数据线3的数量多于电源信号线4，通过将电源信号线4排列在多根数据线3的最中间，使两组子像素11靠近与之对应的两根数据线3，避免将数据线3跨过电源信号线4与子像素11连接，方便布线，提高生产效率。
再次参见图4，所述显示基板还可以包括：多根感测线5(图中仅示出一根)。
感测线5沿所述第二方向B延伸；所述第一像素1a的多个所述子像素11 连接同一根所述感测线5，与所述第一像素1a的多个所述子像素11连接的所述感测线5位于所述第一像素1a与相邻像素1之间。也即是，感测线5位于第一像素1a的一侧。
在本公开实施例中，每个像素中的多个子像素11与同一根所述感测线5连接，多个子像素11共用一根感测线5。感测线5用于感测子像素中的电信号，在一些实施例中，感测线5还可以用于传递外部补偿电路的补偿电压信号。也可以视为，在每个显示区域b中，相邻的2组子像素11共同与一根感测线5连接。由于通过调节各根数据线3的电平信号的电压大小，可以实现单独对任一子像素11中的补偿电压的计算，因此每组像素1中只需通过一根感测线5与所有子像素连接即可满足要求，无需排列多根感测线5。减少了感测线5所占用显示区域b的面积，可以在显示区域b中排布更多的子像素11，提高分辨率。
再次参见图4，所述显示基板还可以包括：多根公共电源线6(图中仅示出一根)。
公共电源线6沿所述第二方向B延伸；所述第一像素1a的多个所述子像素11连接同一根所述公共电源线6，与所述第一像素1a的多个所述子像素11连接的所述公共电源线6位于所述第一像素1a与相邻的另一像素1之间。也即是，感测线5和公共电源线6分别位于第一像素1a的两侧。
通过一根公共电源线6连接一组像素中的多个子像素，减少了公共电源线6所占用显示区域b的面积，可以在显示区域b中排布更多的子像素11，提高分辨率。
示例性地，如图4所示，公共电源线6位于显示区域b靠近透明区域a的一侧。
图5是图4中P-P的剖面示意图，为了便于理解同时也在图6示出了剖面位置线P-P，该剖面经过公共电源线6(双层公共电源线6的连接处)和源极S3。如图5所示，每个子像素11包括依次层叠设置的衬底基板10、遮光层1101、有源层1102、栅极绝缘层1103、第一电极层1104、层间绝缘层1105、第二电极层1106和钝化层1107，第二电极层1106中的第三薄膜晶体管T3的源极S3和有源层1102之间通过过孔12连接，位于第二电极层1106的公共电源线6的部分和位于第一电极层1104的公共电源线6的部分通过过孔13连接，形成图4中的双层公共电源线6，第一电极层1104通过栅极绝缘层1103与有源层1102隔离。
示例性地，衬底基板为透明基板，例如玻璃基板等。有源层1102材料可以为InGaZnO、InGaO、ITZO、AlZnO中的至少一种。栅极绝缘层1103、层间绝缘层1105可以采用氮化硅、氧化硅等绝缘材料制作。钝化层1107的材料为氧化硅、氮化硅、氮硅化合物中的两种或多种的任意组合所构成的复合层结构。遮光层1101、第一电极层1104、第二电极层1106为金属层，例如Al(铝)、Cu(铜)、Mo(钼)、Cr(铬)、Ti(钛)等，也可以为合金电极层。
示例性地，钝化层1107上还设置有阳极层(图中未示出)，阳极层通过过孔与第三薄膜晶体管T3的源极S3连接，阳极层为金属层或者导电薄膜层。
可选地，每个子像素11还包括平坦化层1109、缓冲层1110中的至少一种，平坦化层1109位于钝化层1107和阳极层之间，缓冲层1110位于衬底基板10和有源层1102之间。缓冲层1110通常为SiO 2和SiN x层，可以防止玻璃基板中的金属离子进入到多晶硅中，影响薄膜晶体管的性能。而平坦化层1109通常为树脂层，保证发光二极管的金属阳极和钝化层1107之间的平坦度。
需要说明的是，在其他实施例中，阳极层和有源层1102之间也可以通过一个过孔直接连接。示例性地，本公开实施例提供的子像素还包括像素定义层、发光层、阴极层，这些层的结构可以参见相关技术，在此省略详细描述。
示例性地，第一电极层1104为栅极层，第二电极层1106为源漏极层。
在本公开实施例中，透明区域a包括依次层叠的衬底基板10、栅极绝缘层1103、层间绝缘层1105和钝化层1107。透明区域a中的衬底基板10、栅极绝缘层1103、层间绝缘层1105和钝化层1107与显示区域b中对应的各个膜层可以同时制作，且同层布置，区别可能在于存在部分膜层的厚度不同，例如透明区域a中的栅极绝缘层1103、层间绝缘层1105的厚度均大于显示区域b中的同一膜层，例如透明区域a中的栅极绝缘层1103的厚度大于显示区域b中的栅极绝缘层1103的厚度。
下面结合图6～图10对子像素中的电路结构进行详细说明：
图6示出了子像素中的部分膜层结构示意图。参见图6，其中主要示出了遮光层1101、有源层1102、第一电极层1104和第二电极层1106的结构。图6中G1为第一晶体管T1的栅极，D1为第一晶体管T1的漏极，S1为第一晶体管T1的源极；G2为第二晶体管T2的栅极，D2为第二晶体管T2的漏极，S2为第二晶体管T2的源极；G3为第三晶体管T3的栅极，D3为第三晶体管T3的漏极，S3为第三晶体管T3的源极。图中小方块表示通过过孔连接，例如第二电极层的 电源信号线4通过过孔连接到第一电极层，从而形成双层走线的电源信号线4。图6仅示出了位于左上角的子像素的过孔，其他子像素的过孔与之类似。
图7是本公开实施例中的第一电极层的结构示意图。如图7所示，第一电极层1104为栅极层，第一电极层1104可以包括栅线2，例如包括前述第一栅线21和第二栅线22，以及各个子像素中的薄膜晶体管的栅极，例如，第一薄膜晶体管T1的栅极G1、第二薄膜晶体管T2的栅极G2、第三薄膜晶体管T3的栅极G3，以及电源信号线4和公共电源线6的部分(与第二电极层形成双层走线)。
可选地，如图7所示，第一电极层1104还可以包括连接第二晶体管T2的漏极D2和电源信号线4的连接线41。
图8是本公开实施例中的第二电极层的结构示意图。如图8所示，第二电极层1106为源漏极层，第二电极层1106包括多条数据线3、电源信号线4、感测线5、公共电源线6、电容C的一个极板C1、以及各个薄膜晶体管中的源极和漏极，例如第一薄膜晶体管T1的源极S1和漏极D1，第二薄膜晶体管T2的源极S2和漏极D2以及第三薄膜晶体管T3的源极S3和漏极D3。
图9是本公开实施例中的有源层的结构示意图。如图9所示，有源层包括各个晶体管的部分区域通过金属化形成导体，从而与第二电极层连接，成为第一晶体管T1的源极S1、第二晶体管T2的源极S2和第三晶体管T3的源极S3的一部分。同时，形成电容C的另一个极板C2。
图10是本公开实施例中的遮光层的结构示意图。如图10所示，遮光层1101包括遮光图案7和感测引线50。其中，第一像素1a的多个所述子像素11分别通过所述感测引线50连接所述感测线5。示例性地，遮光图案7通过过孔和第二晶体管T2的源极S2电连接，避免金属的遮光图案7处于浮接(floating)状态。示例性地，遮光图案7的连接点70通过过孔和第二晶体管T2的源极S2电连接。
以图6中电源信号线4左侧的两个子像素11的结构为例(右侧两个子像素11与左侧是近似对称设置的)，对各个膜层的连接关系进行说明。
在左上角的子像素11中：
如图7所示，第一栅线21直接与第一薄膜晶体管T1的栅极G1连接；如图8所示，数据线3直接与第一薄膜晶体管T1的漏极D1连接；如图8和图9所示，位于第二电极层1106中的第一薄膜晶体管T1的源极S1上的连接点11a通过过孔与位于有源层1102中的电容C的一个极板C2连接。
如图7和图9所示，第二薄膜晶体管T2的栅极G2上的连接点11b通过过孔与位于有源层1102中的电容C的一个极板C2连接；如图7和图8所示，位于第一电极层1104中的电源信号线4与连接线41相连，连接线41的连接点11c通过过孔与位于第二电极层1106中的第二薄膜晶体管T2的漏极D2连接，同时第一电极层1104中的电源信号线4的部分通过多个过孔与第二电极层1106中的电源信号线4的部分连接，形成双层电源信号线4；如图8所示，第二薄膜晶体管T2的源极S2与电容C的一个极板C1连接。
如图7和图8所示，第二栅线22上具有连接点11d，连接点11d通过过孔连接到第二电极层1106中第一走线11e的一端，然后由第一走线11e的另一端通过过孔连接到第三薄膜晶体管T3的栅极G3；如图8和图10所示，位于第二电极层1106中的第三薄膜晶体管T3的漏极D3的连接点11f通过过孔与位于遮光层1101的感测引线50连接，感测引线50的连接点11g通过过孔与位于第二电极层1106中的感测线5连接；如图8所示，第三薄膜晶体管T3的源极S3与电容C的一个极板C1连接。
该子像素工作时，在显示阶段，第一栅线21向第一薄膜晶体管T1的栅极G1提供扫描信号，控制第一薄膜晶体管T1的漏极D1和源极S1导通；数据线3通过导通的第一薄膜晶体管T1向电容C的一个极板C2写入数据信号。电容C的一个极板C2与第二薄膜晶体管T2的栅极G2连接，当第二薄膜晶体管T2的栅极G2电位高于导通电压时，第二薄膜晶体管T2的漏极D2和源极S2导通，电源信号线4通过第二薄膜晶体管T2向OLED输出驱动信号，驱动OLED发光。在感测阶段，先通过扫描信号控制第一薄膜晶体管T1导通，同时通过第二栅线22提供的扫描信号控制第三薄膜晶体管T3导通；然后向电容C充电，但充电后栅极G2电位低于导通电压，第二薄膜晶体管T2不导通，此时电容C可以通过第三薄膜晶体管T3给感测线5充电，使得感测线感测到OLED阳极的电位，进而实现后续的外部补偿。
在左下角的子像素11中：
与左上角的子像素11的区别是，第二栅线22是直接连接到栅极G3，第二栅线21的连接点11h通过过孔与第二电极层1106的第二走线11i连接，第二走线11i的连接点11j通过过孔与栅极G1连接。另外，参见图8，左下角的子像素对应从左往右第二根数据线3，由于该数据线3和对应的漏极D1之间存在一根数据线3(从左往右第一根数据线3)，故该数据线3无法直接与对应的子像 素中的漏极D1连接，需要通过第一电极层1104中的第三走线11k连接到漏极D1。
图11是本公开实施例提供的一种透明OLED显示面板的制备流程示意图。如图11所示，示例性的，该透明OLED显示面板的制备方法包括：
S100：提供一衬底基板。
该衬底基板为透明基板，例如玻璃基板等。
S101：在衬底基板上形成遮光层。
在步骤S101中，遮光层可以采用金属材料制成，一方面可以起到遮光作用，遮光图案对像素中被相应的金属阳极所遮挡的部分之外具有金属走线的部分进行遮挡，防止漏光；另一方面可以复用为金属走线，例如前述感测引线。遮光层的结构可以参见前文关于图10的描述。
S102：在遮光层上形成有源层。
在步骤S102中，可以先在遮光层上形成有源材料薄膜。例如可以采用沉积的方式在衬底基板上形成有源材料薄膜。有源材料薄膜可以是InGaZnO、InGaO、ITZO、AlZnO中的至少一种。
然后，通过构图工艺对有源材料薄膜进行处理，得到有源层1102的图案。在得到有源层1102的图案后，可以对有源层1102中的部分区域进行金属化处理，这样经过金属化处理的区域就形成了晶体管的源极。有源层的结构可以参见前文关于图9的描述。
金属化处理可以采用以下方式：在100℃～300℃的还原性气氛中处理30min～120min，还原性气氛包括氢气或含氢等离子体。采用在100℃～300℃的还原性气氛中发生还原反应30min～120min，可最大程度的确保有源材料薄膜中未被刻蚀阻挡层覆盖的区域可以充分地、有效地被还原成金属氧化物导体。若该温度过低，将影响还原反应的还原效果，并且会延长该反应时间，降低了生产效率；若该温度过高，容易将有原材料薄膜中被刻蚀阻挡层覆盖的不需要进行金属化处理的区域受到化学作用，进而影响该结构性能；同样，若时间过短，将导致还原反应进行地不充分，若时间过长，将延长反应时间，降低生产效率。
S103：在有源层上形成栅极绝缘层。
示例性地，可以通过气相沉积的方式形成栅极绝缘层1103。栅极绝缘层1103可以采用氮化硅、氧化硅等绝缘材料制作。
S104：在栅极绝缘层上形成第一电极层。
第一电极层的结构可以参见前文关于图7的描述。
S105：在第一电极层上形成层间绝缘层。
层间绝缘层1105的形成方式可以与栅极绝缘层1103相同。
S106：在层间绝缘层上形成第二电极层。
第一电极层的结构可以参见前文关于图8的描述。
S107：在第二电极层上形成钝化层。
示例性的，钝化层1107的材料为氧化硅、氮化硅、氮硅化合物中的两种或多种的任意组合所构成的复合层结构。
S108：在钝化层上形成阳极层。
如图5所示，阳极层通过过孔12与第二电极层1106连通。
需要说明的是，不同的图案层之间需要连接的区域可以通过过孔连接。因此在步骤S102、S105、S107中，还可以在所形成的层间绝缘层1105和钝化层1107上形成过孔。
可选地，每个子像素11还包括平坦化层1109、缓冲层1110中的至少一种，平坦化层1109位于钝化层1107和阳极层之间，缓冲层1110位于衬底基板10和有源层1102之间。缓冲层1110通常为SiO 2和SiN x层，可以防止玻璃基板中的金属离子进入到多晶硅中，影响薄膜晶体管的性能。而平坦化层1109通常为树脂层，保证发光二极管的金属阳极和钝化层1107之间的平坦度。
本公开实施例提供了一种显示装置，包括如图1至图10所述的透明OLED显示面板。
该显示装置中，一个像素的四个子像素连相同的栅线，减少栅线数量，减少了栅线所占用透明区域的面积，可以提高透明区域在显示面板中的比例；同时，将栅线设计在2排子像素之间，方便走线，也可以保证栅线提供给各个子像素的信号的均一性；另外，减少了栅线所占用显示区域的面积，可以在显示面板上排布更多的子像素，提高分辨率。
本公开实施例中，显示装置包括但不限于手机、平板电脑、笔记本电脑等。
本公开实施例还提供了一种如图1至图10所示的OLED显示面板的驱动方法。以一排子像素沿行方向布置、一组子像素沿列方向布置为例，OLED显示面板工作时逐帧显示画面，在每帧显示的过程中，是按照逐行扫描的方式进行显 示的。也即该方法可以包括：
在显示阶段，逐行控制各行像素的用于显示的薄膜晶体管导通。
在一行像素的用于显示的薄膜晶体管导通时，向该行像素的各个子像素分别写入数据信号，以控制各个子像素的发光亮度。
图12是本公开实施例提供的一种显示阶段的驱动时序图。如图12所示，结合图1、图2和图3，在本公开实施例中，以图3所示的像素为目标像素为例：
在第一时间段t1，为第一栅线21提供扫描信号，为数据线3提供数据信号。
该像素中的多个子像素均获得扫描信号，多个子像素分别通过各自对应的数据线3获取数据信号，从而实现多个子像素同时显示。
在感测阶段，逐行控制各行像素的用于感测的薄膜晶体管导通。
在一行像素的用于感测的薄膜晶体管导通时，通过感测线感测子像素的电信号，感测线感测的是OLED阳极的电位。基于该电信号，外部的集成电路可以计算出补偿值对子像素进行电压补偿。
图13是本公开实施例提供的一种感测阶段的驱动时序图。如图13所示，结合图1、图2和图3，以红色第一子像素为目标子像素为例：
在时间段t2，为第一栅线21和第二栅线22提供扫描信号，第一晶体管T1和第三晶体管T3导通。
数据线3为红色第一子像素提供第一低电平信号，该低电平信号低于第一子像素的第二薄膜晶体T2的导通电压，例如2V，因此第二晶体管T2不导通。数据线3所提供的低电平信号通过电容C和第三晶体管T3进入感测线5，此时该红色第一子像素为感测线5充电，使得感测线感测到OLED阳极的电位，进而可以计算该第一子像素的补偿电压。
类似红色第一子像素对应的数据线3，蓝色第一子像素对应的数据线3会给蓝色第一子像素提供第二低电平信号，从而实现蓝色第一子像素为对应的感测线5充电。
需要说明的是，上述过程仅为感测阶段中对于一行子像素的感测过程，其他行的感测方式与之相同，本公开在此不作赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (13)

  1. 一种显示基板，其特征在于，所述显示基板包括：
    衬底基板(10)，具有沿第一方向(A)间隔交替设置的多个透明区域(a)和多个显示区域(b)；
    多个像素(1)，在所述衬底基板(10)上且位于所述显示区域(b)，所述显示区域(b)中的像素(1)沿第二方向(B)排列，所述像素(1)包括多个子像素(11)，所述像素(1)中的所述子像素(11)分为2排所述子像素(11)，每排所述子像素(11)均沿着所述第一方向(A)排列，所述第一方向(A)和所述第二方向(B)相交；
    多根栅线(2)和多根数据线(3)，在所述衬底基板(10)上，所述多根栅线(2)沿第一方向(A)延伸，所述多根数据线(3)沿第二方向(B)延伸；
    第一像素(1a)的多个所述子像素(11)连接相同的所述栅线(2)，与所述第一像素(1a)的多个所述子像素(11)连接的所述栅线(2)位于所述第一像素(1a)的2排所述子像素(11)之间，所述第一像素(1a)为所述多个像素(1)中的任一个。
  2. 根据权利要求1所述的显示基板，其特征在于，所述第一像素(1a)对应的所述栅线(2)包括第一栅线(21)和第二栅线(22)，所述第一像素(1a)的多个所述子像素(11)分别连接所述第一栅线(21)，所述第一像素(1a)的多个所述子像素(11)分别连接所述第二栅线(22)；
    所述第一栅线(21)和所述第二栅线(22)均位于所述第一像素(1a)的2排所述子像素(11)之间。
  3. 根据权利要求1或2所述的显示基板，其特征在于，所述像素(1)中的所述子像素(11)分为2组所述子像素(11)；
    所述第一像素(1a)对应多根所述数据线(3)，所述第一像素(1a)的多根所述子像素(11)分别连接不同的所述数据线(3)；
    多根所述数据线(3)位于所述第一像素(1a)的2组所述子像素(11)之间，每组所述子像素(11)均沿着所述第二方向(B)排列。
  4. 根据权利要求3所述的显示基板，其特征在于，所述显示基板还包括：
    多根电源信号线(4)，沿所述第二方向(B)延伸；
    所述第一像素(1a)的多个子像素(11)连接同一根所述电源信号线(4)， 与所述第一像素(1a)的多个子像素(11)连接的所述电源信号线(4)位于所述第一像素(1a)的2组所述子像素(11)之间。
  5. 根据权利要求4所述的显示基板，其特征在于，与所述第一像素(1a)的多个子像素(11)连接的所述电源信号线(4)的每一侧，分别布置有与所述第一像素(1a)的1组子像素(11)连接的数据线(3)。
  6. 根据权利要求5所述的显示基板，其特征在于，位于所述电源信号线(4)的第一侧的数据线(3)，分别连接位于所述电源信号线(4)的第一侧的1组子像素(11)，所述电源信号线(4)的第一侧为所述电源信号线(4)的任一侧。
  7. 根据权利要求4所述的显示基板，其特征在于，所述子像素(11)包括依次层叠且相互绝缘的有源层(1102)、第一电极层(1104)和第二电极层(1106)，所述第一电极层(1104)和第二电极层(1106)分别为栅极层、源漏极层中的一个；
    所述电源信号线(4)包括两个子层，所述两个子层分别与所述第一电极层(1104)和所述第二电极层(1106)同层。
  8. 根据权利要求1或2所述的显示基板，其特征在于，所述显示基板还包括：
    多根感测线(5)，沿所述第二方向(B)延伸；
    所述第一像素(1a)的多个所述子像素(11)连接同一根所述感测线(5)，与所述第一像素(1a)的多个所述子像素(11)连接的所述感测线(5)位于所述第一像素(1a)与相邻像素(1)之间。
  9. 根据权利要求8所述的显示基板，其特征在于，所述显示基板还包括：
    多根感测引线(50)，所述第一像素(1a)的多个所述子像素(11)分别通过所述感测引线(50)连接所述感测线(5)。
  10. 根据权利要求9所述的显示基板，其特征在于，所述显示基板还包括：
    遮光图案(6)，位于所述衬底基板(10)上；
    所述感测引线(50)与所述遮光图案(6)同层。
  11. 根据权利要求2所述的显示基板，其特征在于，所述子像素(11)包括3T1C像素电路(113)和发光单元(114)；
    所述3T1C像素电路(113)包括第一晶体管(T1)、第二晶体管(T2)、第三晶体管(T3)和电容(C)；
    所述第一晶体管(T1)的控制极与所述第一栅线(21)电连接，所述第一 晶体管(T1)的第一极与所述数据线(3)电连接，所述第一晶体管(T1)的第二极分别与所述第二晶体管(T2)的控制极和所述电容(C)的一端电连接，所述第二晶体管(T2)的第一极与电源信号线(4)电连接，所述第二晶体管(T2)的第二极分别与所述第三晶体管(T3)的第二极、所述电容(C)的另一端以及所述发光单元(114)电连接，所述第三晶体管(T3)的控制极与所述第二栅线(22)电连接，所述第三晶体管(T3)的第一极与感测线(5)电连接。
  12. 根据权利要求1或2所述的显示基板，其特征在于，所述像素(1)包括的多个子像素(11)分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
  13. 一种显示装置，其特征在于，所述显示装置包括如权利要求1至12任一项所述的显示基板。
PCT/CN2021/093629 2020-06-09 2021-05-13 显示基板及显示装置 WO2021249105A1 (zh)

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