JP7053858B2 - 表示パネル、ディスプレイ及び表示端末 - Google Patents
表示パネル、ディスプレイ及び表示端末 Download PDFInfo
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- JP7053858B2 JP7053858B2 JP2020541558A JP2020541558A JP7053858B2 JP 7053858 B2 JP7053858 B2 JP 7053858B2 JP 2020541558 A JP2020541558 A JP 2020541558A JP 2020541558 A JP2020541558 A JP 2020541558A JP 7053858 B2 JP7053858 B2 JP 7053858B2
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description
2 画素回路
2a 第1端
2b 第2端
2c 制御端
3 第1の電極
4 画素定義層
5 発光構造層
6 第2の電極
7 走査線
8 データ線
21 ソース
22 ドレイン
23 ゲート
24 ゲート絶縁層
25 アクティブ層
26 層間絶縁層
27 平坦化層
28 シールド層
31 第1の開口
32 第2の開口
41 第1の発光層
42 第2の発光層
161 第1の表示領域
162 第2の表示領域
810 機器本体
812 デバイス領域
820 ディスプレイ
930 カメラ
D1 第1の領域
D2 第2の領域
P1(P2/P7) 第1の画素ユニット
P3(P4) 第3の画素ユニット
P8 第2の画素ユニット
Claims (8)
- 表示パネルであって、
画素回路が設けられた基板と、
複数の第1の開口を有する画素定義層と、
前記複数のサブ画素は複数のサブ画素行及び複数のサブ画素列を形成し、隣接するサブ画素行における各サブ画素がずれて配列し、及び/又は、隣接するサブ画素列における各サブ画素がずれて配列し、複数のサブ画素を形成するために複数の第1の開口内に設けられた発光構造層と、
前記画素回路上に設けられ、複数の第1の電極を含み、前記画素回路が前記第1の電極と一対一対応し、前記サブ画素が前記第1の電極と一対一対応する第1の電極層と、
前記発光構造層の上方に設けられ、表面電極である第2の電極と、
走査線が前記画素回路に電圧を提供して前記画素回路の開閉を制御し、前記画素回路がオンになる時に、前記サブ画素の発光を制御するよう、データ線からの駆動電流が前記第1の電極に直接提供されて、前記画素回路にいずれも接続された走査線及びデータ線と、を備え、
複数の前記走査線は第1の方向に沿って延び、複数の前記データ線は第2の方向に沿って延び、前記第1の方向と第2の方向は交差し、
前記延伸方向での各前記走査線の2つの縁はいずれも波状であり、各走査線は2つの縁に、対向して配置されたピークと対向して配置されたトラフを有し、各隣り合う2つの走査線間の第1の間隔が連続的又は断続的に変化するように、各隣り合う2つの走査線の隣接する2つの縁は、対向して配置されたピークと対向して配置されたトラフを有し、
及び/又は、前記延伸方向での各前記データ線の2つの縁はいずれも波状であり、各データ線は2つの縁に、対向して配置されたピークと対向して配置されたトラフを有し、各隣り合う2つのデータ線間の第2の間隔が連続的又は断続的に変化するように、各隣り合う2つのデータ線の隣接する2つの縁は、対向して配置されたピークと対向して配置されたトラフを有することを特徴とする表示パネル。 - 前記サブ画素の第1の電極は前記データ線と同じ層に設けられ、前記第1の電極と前記データ線は同じプロセスステップで形成され、前記データ線は対応する第1の電極の間に巻設され、且つ前記データ線の辺は前記第1の電極の辺と平行ではなく、又は
前記データ線は前記第1の電極の下方に設けられ、前記基板上の前記データ線の投影は第1の投影であり、前記基板上の前記サブ画素の発光構造層の投影は第2の投影であり、各前記第1の投影はいずれも複数の前記第2の投影を通過することを特徴とする請求項1に記載の表示パネル。 - 前記画素回路は、一つのスイッチングデバイスのみを含み、前記スイッチングデバイスは第1端、第2端、及び制御端を含み、前記走査線は前記スイッチングデバイスの制御端に接続され、前記データ線は前記スイッチングデバイスの第1端に接続され、前記第1の電極は前記スイッチングデバイスの第2端に接続されることを特徴とする請求項1に記載の表示パネル。
- 前記第1の電極は陽極で、前記第2の電極は陰極であり、前記スイッチングデバイスは駆動薄膜トランジスタであり、前記第1端は前記駆動薄膜トランジスタのソース又はドレインで、前記第2端は前記駆動薄膜トランジスタのドレイン又はソースであり、前記制御端は前記駆動薄膜トランジスタのゲートであり、前記駆動薄膜トランジスタはトップゲート構造又はボトムゲート構造であり、
ここで、前記第1の電極、第2の電極、データ線、及び走査線のうちの1つまたは複数は、透明な導電性材料で製造され、
前記ゲート材料が透明な導電性材料である場合、前記走査線と前記ゲートは同じプロセスステップで形成され、又は、
前記ゲート材料が金属材料である場合、前記走査線は前記ゲートの上方又は下方に設けられることを特徴とする請求項3に記載の表示パネル。 - 前記走査線の幅は連続的又は断続的に変化し、
及び/又は、前記データ線の幅は連続的又は断続的に変化することを特徴とする請求項1に記載の表示パネル。 - 前記走査線のトラフの対向位置に第1の接続部が形成され、前記第1の接続部は短冊状であり、前記第1の接続部は、前記走査線と前記スイッチングデバイスとの電気的接続領域であり、及び/又は、
前記データ線のトラフの対向位置に第2の接続部が形成され、前記第2の接続部は短冊状であり、前記第2の接続部は、前記データ線と前記スイッチングデバイスとの電気的接続領域であることを特徴とする請求項4に記載の表示パネル。 - 少なくとも第1の表示領域と第2の表示領域を含み、各表示領域はいずれも動的又は静的画像を表示することに用いられ、前記第1の表示領域の下方に感光性デバイスを設けることができるディスプレイであって、
前記第1の表示領域に請求項1-6のいずれか一項に記載の表示パネルが設けられ、前記第2の表示領域に設けられた表示パネルはパッシブマトリクス有機発光ダイオード表示パネル又はアクティブマトリクス有機発光ダイオード表示パネルであることを特徴とするディスプレイ。 - 第1の表示領域の解像度は前記第2の表示領域よりも低く、
前記画素定義層は、前記第1の表示領域内に前記複数の第1の開口を定義し、前記第2の表示領域内に複数の第2の開口を定義し、前記第2の開口の面積は前記第1の開口の面積よりも小さく、
前記第1の表示領域内に、数及び位置が前記第1の開口と対応する第1のサブ画素が形成され、前記第2の表示領域内に、数及び位置が前記第2の開口と対応する第2のサブ画素が形成され、前記第1のサブ画素の発光構造層及び前記第2のサブ画素の発光構造層は、同じマスクプレートを採用し、同じプロセスステップで形成されることを特徴とする請求項7に記載のディスプレイ。
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JP2021513106A (ja) | 2021-05-20 |
KR20200100181A (ko) | 2020-08-25 |
US11263964B2 (en) | 2022-03-01 |
US20200273400A1 (en) | 2020-08-27 |
EP3734663A1 (en) | 2020-11-04 |
CN110767106B (zh) | 2020-09-08 |
WO2020062735A1 (zh) | 2020-04-02 |
TW201937724A (zh) | 2019-09-16 |
EP3734663A4 (en) | 2021-04-07 |
TWI683436B (zh) | 2020-01-21 |
CN110767106A (zh) | 2020-02-07 |
KR102373243B1 (ko) | 2022-03-11 |
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