WO2023020326A1 - 显示面板及其制作方法和显示装置 - Google Patents

显示面板及其制作方法和显示装置 Download PDF

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Publication number
WO2023020326A1
WO2023020326A1 PCT/CN2022/111019 CN2022111019W WO2023020326A1 WO 2023020326 A1 WO2023020326 A1 WO 2023020326A1 CN 2022111019 W CN2022111019 W CN 2022111019W WO 2023020326 A1 WO2023020326 A1 WO 2023020326A1
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WIPO (PCT)
Prior art keywords
display area
signal line
layer
signal lines
display
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PCT/CN2022/111019
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English (en)
French (fr)
Inventor
方飞
刘珂
石领
李若湘
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/275,807 priority Critical patent/US20240119914A1/en
Publication of WO2023020326A1 publication Critical patent/WO2023020326A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/0208—Simultaneous scanning of several lines in flat panels using active addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • the screen-to-body ratio of the full-screen display device is relatively high, which has a good visual effect.
  • the technology of an under-screen camera has been gradually developed in mobile phones and other display devices.
  • the full-screen display device includes a display panel and a full display camera (Full Display Camera, FDC).
  • the display panel has a camera display area, and pixel units are arranged in the camera display area so that the camera display area can display images.
  • the FDC is arranged under the display panel and is opposite to the display area of the camera.
  • Embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device, which can improve display uniformity of the display device. Described technical scheme is as follows:
  • the present disclosure provides a display panel, the display panel comprising: a base substrate having a display area and a peripheral area at least partially surrounding the display area, the display area including a first display area and at least one of the The second display area on one side of the first display area, the light transmittance of the first display area is greater than the light transmittance of the second display area; a plurality of first pixel units are located on the base substrate and Located in the first display area; a plurality of signal lines, at least located in the first display area and electrically connected to the plurality of first pixel units; wherein the plurality of signal lines include a plurality of first signal lines and A plurality of second signal lines, the first part of each first signal line in the plurality of first signal lines is a metal signal line, and the first part of the first signal line is at least located in the first display area; The first part of each of the plurality of second signal lines is a metal oxide signal line, and the first part of the second signal line is at least located in the first display area.
  • the first signal line includes at least one of the following signal lines: a gate signal line, a data signal line, a reset signal line, a light emission control signal line, and an initial voltage signal line and power signal lines.
  • the first signal lines include gate signal lines and data signal lines.
  • the first signal line further includes a second portion located in the second display area
  • the second signal line further includes a second portion located in the second display area. part, the second part of the first signal line and the second part of the second signal line are metal signal lines.
  • the display panel further includes a first metal layer, a first insulating layer, and a metal oxide layer sequentially located on the base substrate along a direction away from the base substrate. ; the first signal line is located in the first metal layer; the first part of at least one second signal line in the plurality of second signal lines in the first display area is located in the metal oxide layer , the second part of the second display area is located on the first metal layer, the first part and the second part of the second signal line are connected through a first via hole penetrating through the first insulating layer, the The first via hole is at the junction of the first display area and the second display area.
  • the first metal layer includes a first gate metal layer and a first source-drain metal layer
  • the first insulating layer includes a first passivation layer and an interlayer dielectric layer; along the direction away from the base substrate, the first gate metal layer, the interlayer dielectric layer, the first source-drain metal layer and the first passivation layer are stacked in sequence.
  • the display panel further includes a second insulating layer and a second metal layer, and along a direction away from the base substrate, the second metal layer, the second insulating layer layer, the first metal layer, the first insulating layer and the metal oxide layer are sequentially stacked; another part of the plurality of second signal lines in the first part of the second signal line in the first display area Located in the metal oxide layer, the second part of the second display area is located in the second metal layer, the first part and the second part of the second signal line pass through the first insulating layer and The second via hole of the second insulating layer is connected, and the second via hole is at the junction of the first display area and the second display area.
  • the second metal layer includes a second gate metal layer
  • the second insulating layer includes a first gate insulating layer
  • the first signal line is a gate signal line
  • the first size of the first display area is the size of the first display area in the extending direction of the gate signal line
  • the second size of the first display area is the size of the first display area in the The dimension in the extending direction of the data signal line.
  • the first signal line is a data signal line
  • the first size of the first display area is the first size of the first display area in the extending direction of the gate signal line
  • the second size of the first display area is the first size of the first display area in the The dimension in the extending direction of the data signal line.
  • the first signal line includes The gate signal line and the data signal line
  • the first size of the first display area is the size of the first display area in the extending direction of the gate signal line
  • the second size of the first display area is the The size of the first display area in the extending direction of the data signal lines.
  • the display panel further includes a plurality of second pixel units, the plurality of second pixel units are located in the second display area, and the plurality of first pixel units and The plurality of second pixel units are arranged into multiple rows of pixel units, and in the arrangement direction of the pixel units of one row, the pixel units in two adjacent rows of pixel units are staggered from each other; the pixel units in two adjacent rows of pixel units pass through a The gate signal line is connected.
  • the gate signal line is in a wavy shape, and the crests and troughs of the gate signal line are respectively connected to pixel units in two adjacent rows of pixel units.
  • the data signal line is in a wavy shape, and the crest and trough of the data signal line are respectively connected to two adjacent pixel units in the same row of pixel units.
  • the metal signal lines include molybdenum signal lines or titanium signal lines.
  • the metal oxide signal line is a transparent metal oxide signal line.
  • the metal oxide signal line is an indium tin oxide signal line.
  • the present disclosure provides a manufacturing method of a display panel, the manufacturing method comprising:
  • a base substrate has a display area and a peripheral area at least partially surrounding the display area, the display area includes a first display area and a second display area at least on one side of the first display area area, the light transmittance of the first display area is greater than the light transmittance of the second display area; a plurality of first pixel units and a plurality of signal lines are formed on the base substrate, and the plurality of first The pixel unit is located in the first display area; a plurality of signal lines are at least located in the first display area and electrically connected to the plurality of first pixel units, and the plurality of signal lines include a plurality of first signal lines and a plurality of a second signal line, the first part of each first signal line in the plurality of first signal lines is a metal signal line, and the first part of the first signal line is at least located in the first display area; the The first part of each second signal line in the plurality of second signal lines is a metal oxide signal line, and the first part of the second signal line is
  • the present disclosure provides a display device, the display device includes a power supply component, and the display panel according to any one of the above aspects, the power supply component is used for supplying power to the display panel.
  • the display device further includes a light sensor, the light sensor is located on a side of the display panel away from the plurality of first pixel units, and the light sensor The orthographic projection of the sensor on the base substrate at least partially overlaps with the first display area.
  • the light transmittance of the first display area is relatively high, and the photosensitive sensor (for example: a full-screen camera) can be arranged in the area corresponding to the first display area, so that light can transmit through the first display area to the light sensor.
  • the first part of the first signal line in the first display area is a metal signal line, and the resistance of metal is smaller than that of metal oxide, which can reduce the resistance of the first signal line and reduce the load of the first signal line , so that the voltage received by the pixel units in the first display area increases, and the voltage received by the pixel units in the first display area is less different from the voltage received by the pixel units in other areas, which improves the phenomenon of uneven display .
  • the first part of the second signal line is a metal oxide signal line, so as to ensure the light transmittance of the first display area.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Fig. 4 is the sectional view of A-A plane in Fig. 2;
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a film layer of a pixel provided by an embodiment of the present disclosure.
  • Fig. 11 is a top view of a first display area provided by an embodiment of the present disclosure.
  • Fig. 12 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 13 is a pixel arrangement diagram of a first display area provided by an embodiment of the present disclosure.
  • Fig. 14 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 15 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 16 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 17 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 18 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure.
  • Fig. 19 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 20 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 21 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 22 is a top view of another first display area provided by an embodiment of the present disclosure.
  • Fig. 23 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure.
  • Fig. 24 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Fig. 25 is a circuit diagram of a 7T1C pixel provided by an embodiment of the present disclosure.
  • FIG. 26 is a flow chart of a method for manufacturing a display panel provided by the implementation of the present disclosure.
  • FIG. 27 is a flow chart of a method for manufacturing a display panel provided by the implementation of the present disclosure.
  • Fig. 28 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • Fig. 29 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • Fig. 30 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • Fig. 31 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • Fig. 32 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • Fig. 33 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • Fig. 34 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • FIG. 35 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • the signal lines between the pixel units in the display area of the camera are all transparent metal oxide signal lines, for example, oxidized Indium Tin Oxide (ITO) signal line.
  • ITO oxidized Indium Tin Oxide
  • the larger resistance of the metal oxide signal line will generate a larger load, so that the voltage received by the pixel unit connected to the metal oxide signal line is smaller than the voltage received by the pixel unit in other display areas, so that the display area of the camera display area The effect differs greatly from the display effects of other display areas, resulting in uneven display.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a base substrate 10 having a display area 100 and a peripheral area 200 at least partially surrounding the display area 100 .
  • the display area 100 can be used to arrange pixel circuits
  • the peripheral area 200 can be used to arrange integrated circuits, and the integrated circuits are used to drive the pixel circuits to work.
  • the peripheral area 200 at least partially surrounds the display area 100, and the peripheral area 200 may surround the display area 100; or, both sides of the display area 100 are connected to the peripheral area 200; or, the display area 100 and the peripheral area 200 are side by side, At this time, one side of the display area 100 is in contact with the peripheral area 200 .
  • the display area 100 includes a first display area 101 and a second display area 102 located at least on one side of the first display area 101 , the light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102 .
  • the light transmittance of the first display area 101 is relatively high. In this way, there is no need to dig holes on the base substrate 10, and the required hardware structures such as photosensors can be directly arranged at positions opposite to the first display area 101 to realize A true full-screen display device.
  • the light sensor may be a camera.
  • the shape of the first display area 101 is a rectangle. In other implementation manners, the shape of the first display area 101 may be a circle, a polygon, and other regular or irregular shapes.
  • the second display area 102 located at least on one side of the first display area 101 means that the second display area 102 can surround the first display area 101; Or, the first display area 101 and the second display area 102 are side by side, and at this time, one side of the first display area 101 is in contact with the second display area 102 .
  • the second display area 102 surrounds the first display area 101 .
  • the first display region 101 is located in the middle of the top region of the base substrate 10 .
  • the first display region 101 may also be located at other positions on the base substrate 10 .
  • the first display region 101 may be located at the upper left corner or the upper right corner of the base substrate 10 .
  • FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel further includes a plurality of first pixel units 20 and a plurality of signal lines 30 .
  • a plurality of first pixel units 20 are located on the base substrate 10 and located in the first display area 101 .
  • the plurality of signal lines 30 are located at least in the first display area 101 and are electrically connected to the plurality of first pixel units 20 .
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the plurality of signal lines 30 includes a plurality of first signal lines 301 and a plurality of second signal lines 302 .
  • the first signal line 301 may include a gate signal line and a data signal line
  • the second signal line 302 may include a reset signal line.
  • a plurality of first pixel units 20 are arranged in multiple rows of pixel units. In the arrangement direction of a row of pixel units, the pixel units in two adjacent rows of pixel units are staggered from each other, and the pixel units in two adjacent rows of pixel units pass through a first pixel unit.
  • a signal line 301 or a second signal line 302 are connected. Both the first signal line 301 and the second signal line 302 are wavy lines.
  • the first part of each first signal line 301 in the plurality of first signal lines 301 is a metal signal line, and the first part of the first signal line 301 is at least located in the first display area 101 .
  • the first part of each second signal line 302 in the plurality of second signal lines 302 is a metal oxide signal line, and the first part of the second signal line 302 is at least located in the first display area 101 .
  • the light transmittance of the first display area 101 is relatively high, and the photosensitive sensor (for example: a full-screen camera) can be arranged in the area corresponding to the first display area 101, so that light can pass through the first display area. Area 101 propagates to the light sensor.
  • the first part of the first signal line 301 in the first display area 101 is a metal signal line.
  • the resistance of metal is smaller than that of metal oxide, which can reduce the resistance of the first signal line 301 and reduce the first signal.
  • the load of the line makes the voltage received by the pixel unit 20 in the first display area 101 increase, and the voltage received by the pixel unit 20 located in the first display area 101 is relatively different from the voltage received by the pixel unit 20 in other areas. Small, to improve display unevenness.
  • the first part of the second signal line 302 is a metal oxide signal line, so as to ensure the light transmittance of the first display area 101 .
  • the gaps between the pixel units 20 are also regularly arranged, and light rays are prone to diffraction when passing through the gaps in the first display area 101 , the light that produces the diffraction phenomenon is transmitted to the full-screen camera, which will affect the shooting effect of the full-screen camera.
  • the first part of each of the first signal lines 301 passing through the first display area 101 is arranged as a metal signal line, and the metal signal line is not transparent, thus breaking the pixel unit
  • the regular arrangement of the gaps between 20 can improve the diffraction of light to a certain extent, thereby improving the imaging effect of the full-screen camera.
  • the first signal line 301 also includes a second portion located in the second display area 102
  • the second signal line 302 also includes a second portion located in the second display area 102
  • the first signal line 301 includes a second portion located in the second display area 102 .
  • the second part and the second part of the second signal line 302 are metal signal lines.
  • the second display area 102 does not need to have a high light transmittance
  • the first signal line 301 and the second display area 102 in the second display area 102 are both arranged as metal signal lines, which can reduce the load of the first signal line 301 and the second signal line 302, increase the display brightness of the display panel, and improve the display effect.
  • the first part of each second signal line 302 in the plurality of second signal lines 302 is a transparent metal oxide signal line, so that part of the signal line 30 in the first display area 101 is a transparent signal line , so as to ensure the light transmittance of the first display region 101 .
  • the first signal line 301 includes at least one of a gate (Gate) signal line and a data (Data) signal line.
  • Each first pixel unit 20 includes a switch transistor and a drive transistor, the gate signal line is responsible for providing a turn-on voltage to the gate of the switch transistor, and the data signal line is responsible for providing a turn-on voltage to the gate of the drive transistor.
  • the resistance of the transparent metal oxide signal line is relatively large, and the use of a transparent metal oxide signal line will result in a small turn-on voltage, making the switching thin film transistor unable to conduct, or the switching time of the switching thin film transistor is short, which is different from the use of metal signal lines.
  • the brightness of the area is not consistent, which affects the display uniformity of the display panel.
  • the resistor increases the turn-on voltage of the first pixel unit 20 located in the first display area 101, thereby improving display uniformity.
  • the metal oxide signal line may be an indium tin oxide signal line, and indium tin oxide has good transparency to ensure the transparency of the metal oxide signal line.
  • the display panel further includes a plurality of second pixel units 40, the plurality of second pixel units 40 are located in the second display area 102, and the plurality of second pixel units 40 and the plurality of first pixel units 20 are arranged in multiple rows pixel unit.
  • the size of the first pixel unit 20 can be designed to be smaller than that of the second pixel unit 20 during manufacture.
  • the size of the pixel unit 40 is used to increase the light transmittance of the first display region 101 .
  • the signal line 30 further includes a reset (Reset) signal line, an emission control (EM) signal line, an initial voltage (Vinit) signal line and a power supply (VDD) signal line.
  • the signal lines 30 except the first signal line 301 are all second signal lines 302 , that is, reset signal lines, light emission control signal lines, initial voltage signal lines and power signal lines are all second signal lines 302 .
  • Metal signal lines have low resistance but poor light transmittance, and transparent metal oxide signal lines have high resistance but high light transmittance. Since the light sensor is arranged in the area corresponding to the first display area 101 in the display device, while reducing the resistance of the signal lines in the first display area 101, it is also necessary to ensure the light transmittance of the first display area 101. Through experimental simulation, it is found that signal lines such as reset signal lines, light-emitting control signal lines, initial voltage signal lines, and power signal lines have little influence on display brightness. Arranging these signal lines as transparent metal oxide signal lines can ensure the first display The transmittance of the region 101.
  • the first signal line 301 includes a gate signal line and a data signal line
  • the second signal line 302 includes a reset signal line, a light emission control signal line, an initial voltage signal line and a power signal line .
  • the gate signal lines include molybdenum signal lines.
  • the data signal lines contain titanium signal lines.
  • the material of the first part of the first signal line passing through the first display area is metal oxide, and in the embodiment of the present disclosure, the material of the first part of the first signal line passing through the first display area is metal, In this way, the first signal lines that pass through the first display area and the first signal lines that do not pass through the first display area can be made in the same manner, that is, the entire signal lines are on the same layer.
  • Fig. 4 is a schematic cross-sectional view of plane A-A in Fig. 2 .
  • the display panel includes a first metal layer 201, a first insulating layer 202 and a metal oxide layer 203 sequentially located on the base substrate 10 along a direction away from the base substrate 10, and a first signal line 301 (not shown in FIG.
  • At least one second signal line 302 of the plurality of second signal lines 302 in the first display area 101 is located in the first part of the first display area 101 in the metal oxide Layer 203, the second part of the second display area 102 is located in the first metal layer 201, the first part and the second part of the second signal line 302 are connected through the first via hole 221 penetrating through the first insulating layer 202, the first The via hole 221 is at the junction of the first display area 101 and the second display area 102 .
  • the junction of the first display area 101 and the second display area 102 refers to the area where the boundary connecting the first display area 101 and the second display area 102 is located.
  • At least one second signal line 302 among the plurality of second signal lines 302 may be one second signal line 302 , or a plurality of second signal lines 302 , or all second signal lines 302 .
  • the first signal line 301 is a metal signal line arranged in the first metal layer 201
  • the second signal line 302 is a transparent metal oxide signal line in the first display area 101, and is arranged in the second display area 101.
  • the area 102 is a metal line
  • the second signal line 302 in the first display area 101 is arranged in the metal oxide layer 203 to ensure the light transmittance of the first part of the second signal line 302 .
  • Disposing the second signal line 302 in the second display area 102 in the first metal layer 201 reduces the resistance of the second portion of the second signal line 302 .
  • the first part and the second part of the second signal line 302 are connected through the first via hole 221 to ensure the effectiveness of the electrical connection.
  • the first metal layer 201 includes a first gate metal layer and a first source-drain metal layer
  • the first insulating layer 202 includes a first passivation layer and an interlayer dielectric layer.
  • the first signal line 301 includes one of a gate signal line and a data signal line
  • the second signal line 302 includes the other one of a gate signal line and a data signal line.
  • the first signal line 301 is a gate signal line
  • the second signal line 302 is a data signal line
  • the gate signal line is located in the first gate metal layer 211
  • the data signal line in the first display area 101 is located in the metal oxide layer 211.
  • the material layer 203 , the data signal lines in the second display region 102 are located in the first source-drain metal layer 212 .
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. 4 and 5 are cross-sectional views at different cross-sections.
  • the display panel includes a first gate metal layer 211, a first passivation layer, and a first passivation layer on the base substrate 10 along the direction away from the base substrate 10.
  • layer 222 , the first source-drain metal layer 212 , the interlayer dielectric layer 223 and the metal oxide layer 203 a first gate metal layer 211, a first passivation layer, and a first passivation layer on the base substrate 10 along the direction away from the base substrate 10.
  • layer 222 the first source-drain metal layer 212 , the interlayer dielectric layer 223 and the metal oxide layer 203 .
  • the display panel only includes a gate metal layer and a source-drain metal layer
  • the aforementioned first metal layer 201 includes a first gate metal layer 211 and a first source-drain metal layer 212
  • the aforementioned first insulating layer 202 includes The first passivation layer 222 and the interlayer dielectric layer 223 .
  • the first signal lines 301 include both gate signal lines and data signal lines.
  • the gate signal lines are located on the first gate metal layer 211.
  • the data signal lines are located in the first source-drain metal layer 212 . Only the first signal line 301 is shown in FIG. 5 .
  • FIG. 6 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a first gate metal layer 211, a first passivation layer 222, a first source-drain metal layer 212, an interlayer dielectric layer 223 and a metal oxide layer 203. direction, the first gate metal layer 211 , the first passivation layer 222 , the first source-drain metal layer 212 , the interlayer dielectric layer 223 and the metal oxide layer 203 are stacked in sequence.
  • the second signal line 302 includes an initial voltage signal line.
  • the second signal line 302 is located on the metal oxide layer 203
  • the second signal line 302 is located on the first gate metal layer 211 . Only the second signal line 302 is shown in FIG. 6 .
  • the second signal line 302 further includes a reset signal line and a light emission control signal line.
  • the reset signal line and the light emission control signal line are located in the first gate metal layer 211
  • the reset signal line and the light emission control signal line are located in the metal oxide layer 203 .
  • the reset signal line located in the first display area 101 and the reset signal line located in the second display area 102 are electrically connected through the first via hole 221, and the light emission control signal line located in the first display area 101 and the second display area
  • the light emission control signal line in 102 is electrically connected through the first via hole 221 , and the first via hole 221 passes through the first passivation layer 222 , the first source-drain metal layer 212 and the interlayer dielectric layer 223 .
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a first gate metal layer 211 , a first passivation layer 222 , a first source-drain metal layer 212 , an interlayer dielectric layer 223 and a metal oxide layer 203 on the base substrate 10 .
  • the second signal line 302 includes a power signal line.
  • the second signal line 302 is located on the metal oxide layer 203
  • the second signal line 302 is located on the first source-drain metal layer 212 . Only the second signal line 302 is shown in FIG. 7 .
  • the second signal line 302 is a power signal line.
  • the power signal line is located in the first source-drain metal layer 212.
  • the power signal line is located in the metal oxide layer 212.
  • the power signal lines in the first display area 101 and the power signal lines in the second display area 102 are electrically connected through the first via hole 221 , and the first via hole 221 passes through the interlayer dielectric layer 223 .
  • the power signal line may also be located in the second source-drain metal layer.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel further includes a second insulating layer 204 and a second metal layer 205 , and the second insulating layer 204 is located between the first metal layer 201 and the second metal layer 205 .
  • Another part of the second signal lines 302 in the plurality of second signal lines 302 is located in the metal oxide layer 203 in the first part of the first display area 101 , and is located in the second metal layer 205 in the second part of the second display area 102 , the first part and the second part of the second signal line 302 are connected through the second via hole 241 penetrating through the first insulating layer 202 and the second insulating layer 204, and the second via hole 241 is connected between the first display area 101 and the second display area 102 junction.
  • the second metal layer 205 is a second gate metal layer
  • the second insulating layer 204 is a first gate insulating layer
  • the second signal line 302 may also include a reset signal line, a light emission control signal line, an initial voltage signal line and a power supply signal line.
  • the reset signal line, the light emission control signal line, the initial voltage signal line wires and power signal lines are located on the metal oxide layer 203, and in the second display region 102, reset signal lines, light emission control signal lines, initial voltage signal lines and power signal lines are located on the second gate metal layer.
  • the second metal layer 205 is a second gate metal layer
  • the second insulating layer 204 is a first gate insulating layer
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a second gate metal layer 251 , a first gate insulating layer 242 , a first gate metal layer 211 , a first passivation layer 222 , a first source-drain metal layer 212 , an interlayer dielectric layer 223 and a metal oxide layer 203 .
  • the second signal line 302 is an initial voltage signal line.
  • the initial voltage signal line is located at the second gate metal layer 251.
  • the initial voltage signal line is located at metal oxide layer 203 .
  • Part of the initial voltage signal lines located in the first display area 101 and part of the initial voltage signal lines located in the second display area 102 are electrically connected through the second via hole 241.
  • the second via hole 241 passes through the first gate insulation layer 242 , the first gate metal layer 211 , the first passivation layer 222 , the first source-drain metal layer 212 and the interlayer dielectric layer 223 .
  • the gate signal lines are located in the first gate metal layer 211
  • the data signal lines are located in the first source-drain metal layer 212 .
  • the display panel further includes an active layer 206 , a second gate insulating layer 207 , a second passivation layer 208 and a second source-drain metal layer 209 .
  • the second gate insulating layer 207 is located between the active layer 206 and the second gate metal layer 251
  • the second passivation layer 208 is located between the metal oxide layer 203 and the second source-drain metal layer 209 .
  • the active layer 206 may be a polycrystalline silicon (Polycrystalline Silicon) material layer, referred to as a Poly layer.
  • the second gate insulating layer 207 separates the active layer 206 from the second gate metal layer 251 .
  • the second source-drain metal layer 209 is a wiring layer, and the second passivation layer 208 separates the first source-drain metal layer 212 from the second source-drain metal layer 209 .
  • the first gate metal layer 211 and the second gate metal layer 251 include a metal molybdenum layer
  • the first source-drain metal layer 212 and the second source-drain metal layer 209 include a metal titanium layer.
  • the second gate insulating layer 207, the first gate insulating layer 242, the interlayer dielectric layer 223, the first passivation layer 222 and the second passivation layer 208 may be silicon nitride layer, silicon oxide layer or epoxy resin one of the layers.
  • the base substrate 10 may be a glass substrate or a polyimide substrate.
  • the film layer structure in Figure 10 corresponds to the first pixel unit 20 in the aforementioned Figure 2 Structure.
  • FIG. 10 is a schematic diagram of film layers of a pixel provided by an embodiment of the present disclosure.
  • the display panel includes a buffer layer (Buffer) 2010 , an active layer 206 , a second gate insulating layer 207 , and a second gate metal layer 251 sequentially located on the base substrate 10 in a direction away from the base substrate 10 , first gate insulating layer 242, first gate metal layer 211, interlayer dielectric layer 223, first source-drain metal layer 212, second passivation layer 208, planarization layer 2011, anode layer 2012, pixel definition layer 2013 , spacer layer 2014 , light emitting layer 2015 , cathode layer 2016 , first inorganic encapsulation layer 2017 , organic encapsulation layer 2018 and second inorganic encapsulation layer 2019 .
  • the display panel only includes one source-drain metal layer, that is, the first source-drain metal layer 212 .
  • the buffer layer 2010 is located between the base substrate 10 and the active layer 206 , and the buffer layer 2010 is used to reduce the impact on the base substrate 10 when the active layer 206 is etched.
  • the planarization layer 2011 is located on the side of the second passivation layer 208 away from the first source-drain metal layer 212 , and the planarization layer 2011 is used to make the surface of the display panel manufactured with the first source-drain metal layer 212 more flat.
  • the anode layer 2012 is located on a side of the planarization layer 2011 away from the first source-drain metal layer 212 , and the anode layer 2012 is electrically connected to the first source-drain metal layer 212 .
  • the pixel defining layer 2013 is located on one side of the first source-drain metal layer 212 of the anode layer 2012 , and has an opening in the pixel defining layer 2013 , the opening communicates with the anode layer 2012 , and the light emitting layer 2015 is located in the opening.
  • the spacer layer 2014 can be used to support the mask when evaporating the light emitting layer 2015 .
  • the cathode layer 2016 is located on the side of the light-emitting layer 2015 away from the first source-drain metal layer 212 , and a voltage is formed between the cathode layer 2016 and the anode layer 2012 to control the light-emitting layer 2015 to emit light.
  • the first inorganic encapsulation layer 2017 , the organic encapsulation layer 2018 and the second inorganic encapsulation layer 2019 together form an encapsulation layer to encapsulate the display panel and ensure the integrity of the display panel.
  • the pixel unit includes a capacitor 60.
  • the first plate 601 of the capacitor 60 is located on the second gate metal layer 251
  • the second plate 602 of the capacitor is located on the first gate metal layer 211. .
  • the second gate insulating layer 207 , the second gate metal layer 251 , the first gate insulating layer 242 , and the first gate metal layer 211 are sequentially arranged along a direction away from the base substrate 10 .
  • the second gate insulating layer 207, the first gate metal layer 211, the first gate insulating layer 242 and the second gate metal layer 251 may be arranged in sequence, which is not limited in the present disclosure. .
  • Fig. 11 is a top view of a first display area provided by an embodiment of the present disclosure.
  • the first display area 101 is strip-shaped, the first size L1 of the first display area 101 is larger than the second size L2 of the first display area 101, the first size L1 of the first display area 101 is the first display
  • the size of the area 101 in the extending direction of the gate signal lines, the second size L2 of the first display area 101 is the size of the first display area 101 in the extending direction of the data signal lines.
  • the display device includes a plurality of photosensors 50, the orthographic projections of the plurality of photosensors 50 on the display panel are located in the first display area 101, and the extension direction of the plurality of photosensors 50 is parallel to the extension direction of the gate signal lines.
  • three photosensors 50 are arranged in the area corresponding to the first display area 101 in the display device.
  • Fig. 12 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the display device includes 4 photosensors 50.
  • the 4 photosensors 50 are divided into two groups, one group includes two photosensors 50, and the distance between the two photosensors 50 in the same group is 0, there is a certain gap between two adjacent groups.
  • the ratio of the first size L1 of the first display area 101 to the second size of the first display area 101 is greater than 2.
  • FIG. 13 is a pixel arrangement diagram of a first display area provided by an embodiment of the present disclosure. 11 to 13 , when the ratio of the first size L1 of the first display region 101 to the second size of the first display region 101 is greater than 2, the first signal line 301 is a gate signal line.
  • the gate signal line is electrically connected to a plurality of first pixel units 20, and the gate signal line has a load, then the gate voltage received by the first pixel unit 20 that is closer to the driving circuit will be larger, and the gate voltage received by the first pixel unit 20 that is farther away from the driving circuit will be larger.
  • the gate voltage received by the first pixel unit 20 will be smaller.
  • the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is greater than 2, it means that the length of the gate signal line in the first display area 101 is longer than that of the data signal line in the first display area 101. The length in the first display area 101 .
  • the length of the signal line is negatively correlated with the resistance of the resistance signal line, so in the first display area 101 , the display unevenness caused by the gate signal line is greater.
  • Arranging the gate signal lines as metal signal lines can reduce the display unevenness caused by the gate signal lines and improve the display unevenness.
  • the first display region 101 extends along the extension direction of the first dimension L1 , and in other implementations, the first display region 101 may also extend along other directions.
  • Fig. 14 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the first display area 101 is also elongated, the first size L1 of the first display area 101 is smaller than the second size L2 of the first display area 101, and a plurality of photosensors are arranged in the first display area 101 50.
  • the extending direction of the plurality of photosensors 50 is the extending direction of the second dimension L2.
  • the display device includes two light sensors 50 .
  • Fig. 15 is a top view of another first display area provided by an embodiment of the present disclosure. Referring to Fig. 15, the display device includes 4 photosensors 50. The 4 photosensors 50 are divided into two groups, one group includes two photosensors 50, and the distance between the two photosensors 50 in the same group is 0, there is a certain gap between two adjacent groups.
  • Fig. 16 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the display device includes four light sensors 50 , and the distance between two adjacent light sensors 50 is zero.
  • Fig. 17 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the display device includes three light sensors 50 , and the distance between two adjacent light sensors 50 is zero.
  • the display device may also be arranged with other numbers of photosensors 50 , which is not limited in the present disclosure.
  • FIG. 18 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure. 14 to 18 , when the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is less than 0.5, the first signal line 301 is a data signal line.
  • the data signal line is similar to the gate signal line, the first pixel unit 20 closer to the driving circuit receives a larger data voltage, and the first pixel unit 20 farther away from the driving circuit receives a lower data voltage.
  • the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is less than 0.5, it means that the length of the data signal line in the first display area 101 is longer than that of the gate signal line in the first display area 101. The length in the first display area 101 .
  • the display unevenness caused by the data signal lines is larger. Arranging the data signal lines as metal signal lines can reduce the display unevenness caused by the data signal lines and improve the display unevenness.
  • the first display regions 101 are all strip-shaped. In other implementation manners, the first display area 101 may also be in the shape of a block.
  • Fig. 19 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the first display area 101 is in the shape of a block, the first size L1 of the first display area 101 is not much different from the second size L2 of the first display area 101, and three lights are arranged in the first display area 101.
  • Sensitive sensor 50, three photosensitive sensors 50 are arranged in a triangle.
  • the display device includes three light sensors 50 .
  • Fig. 20 is a top view of another first display area provided by an embodiment of the present disclosure. Referring to FIG. 20 , the display device includes four photosensors 50 arranged in a square.
  • Fig. 21 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the display device includes five photosensors 50 arranged in a pentagon.
  • Fig. 22 is a top view of another first display area provided by an embodiment of the present disclosure.
  • the display device includes six photosensors 50 arranged in a hexagonal shape.
  • the display device may also have other numbers of photosensors 50 arranged therein, which is not limited in the present disclosure.
  • FIG. 23 is another pixel arrangement diagram of the first display area provided by an embodiment of the present disclosure. 19 to 23, when the ratio of the first size L1 of the first display region 101 to the second size L2 of the first display region 101 is between 0.5 and 2, the first signal lines 301 include gate signal lines and Data signal line.
  • the ratio of the first size L1 of the first display area 101 to the second size L2 of the first display area 101 is between 0.5 and 2, it means that in the first display area 101, the length of the gate signal line and the length of the data signal The length of the lines is not much different, and the phenomenon of uneven display caused by the gate signal lines and data signal lines is also not much different. Improve the display unevenness caused by signal lines and data signal lines.
  • FIG. 24 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a plurality of first pixel units 20 and a plurality of second pixel units 40 .
  • a plurality of first pixel units 20 and a plurality of second pixel units 40 are arranged in multiple rows of pixel units. In the arrangement direction of a row of pixel units, the pixel units in two adjacent rows of pixel units are staggered from each other, and two adjacent rows of pixel units The pixel units in are connected through a gate signal line.
  • pixel units Multiple rows of pixel units are arranged in a staggered manner. On the same area, more pixel units can be arranged to increase the density of the pixel units, thereby increasing the resolution of the display panel and further improving the display effect. At the same time, the pixel units in two adjacent rows of pixel units are connected through the gate signal lines, so as to avoid complicated routing and simplify the circuit structure.
  • the gate signal line is in a wavy shape, and the peaks and troughs of the gate signal line are respectively connected to the first pixel unit 20 or the second pixel unit 40 .
  • the data signal line is also in a wave shape.
  • both the first pixel unit 20 and the second pixel unit 40 include a 7T1C pixel circuit.
  • FIG. 25 is a circuit diagram of a 7T1C pixel provided by an embodiment of the present disclosure.
  • the pixel circuit includes a first switch transistor T1, a first compensation transistor T2, a first reset transistor T3, a second reset transistor T4, a drive transistor T5, a first light emission control transistor T6, a second light emission control transistor T7 and a capacitor Cst.
  • the control electrode of the first switching transistor T1 is electrically connected to a gate line through the first scanning signal terminal (Scan[n]), and the first electrode of the first switching transistor T1 is connected to a gate line through the data input terminal (Data[m]).
  • the data lines are electrically connected, and the second pole of the first switching transistor T1 is electrically connected to the first node N1.
  • the control electrode of the first compensation transistor T2 is electrically connected to a gate line through the first scanning signal terminal (Scan[n]), the first electrode of the first compensation transistor T2 is electrically connected to the second node N2, and the first compensation transistor T2 The second pole of is electrically connected to the third node N3.
  • the control electrode of the first reset transistor T3 is electrically connected to another gate line through the second scanning signal terminal (Scan[n-1]), and the first electrode of the first reset transistor T3 is connected to the initial voltage through the initialization voltage terminal (Vinit).
  • the signal lines are electrically connected, and the second pole of the first reset transistor T3 is electrically connected to the third node N3.
  • the control electrode of the second reset transistor T4 is electrically connected to a gate line through the first scanning signal terminal (Scan[n]), and the first electrode of the second reset transistor T4 is electrically connected to the initial voltage signal line through the initialization voltage terminal (Vinit). connected, the second pole of the second reset transistor T4 is electrically connected to the fourth node N4.
  • the control electrode of the driving transistor T5 is electrically connected to the third node N3, the first electrode of the driving transistor T5 is electrically connected to the first node N1, and the second electrode of the driving transistor T5 is electrically connected to the second node N2.
  • the control electrode of the first light emission control transistor T6 is electrically connected to the light emission control signal line through the light emission control signal terminal (EM[n]), the first electrode of the first light emission control transistor T6 is electrically connected to the first node N1, and the first light emission control transistor T6 is electrically connected to the first node N1.
  • the second pole of the transistor T6 is electrically connected to the fifth node N5.
  • the fifth node N5 is electrically connected to the power signal line through the first voltage signal terminal (ELVDD).
  • the control electrode of the second light emission control transistor T7 is electrically connected to the light emission control signal line through the light emission control signal terminal (EM[n]), the first electrode of the second light emission control transistor T7 is electrically connected to the second node N2, and the second light emission control transistor T7 is electrically connected to the second node N2.
  • the second pole of the transistor T7 is electrically connected to the fourth node N4.
  • the first plate of the capacitor Cst is electrically connected to the fifth node N5, and the second plate of the capacitor Cst is electrically connected to the third node N3.
  • the pixel circuit further includes a light emitting diode LED, the fourth node N4 is electrically connected to one end of the light emitting diode LED, and one end of the light emitting diode LED is electrically connected to the second voltage signal terminal (ELVSS).
  • EVSS second voltage signal terminal
  • the 7T1C pixel circuit in the embodiment of the present disclosure is only used as an example, and in other implementation manners, the pixel circuit may also have other structures, for example, the pixel circuit is a 2T1C pixel circuit.
  • FIG. 26 is a flow chart of a method for manufacturing a display panel provided by an implementation of the present disclosure. Wherein the display panel has a light-transmitting first display area, see FIG. 26, and the manufacturing method includes:
  • step S401 a base substrate is provided.
  • the base substrate has a display area and a peripheral area at least partially surrounding the display area, the display area includes a first display area and a second display area at least on one side of the first display area, and the light transmittance of the first display area is Greater than the light transmittance of the second display area.
  • the base substrate may be a glass substrate or a polyimide substrate.
  • step S402 a plurality of first pixel units and a plurality of signal lines are formed on the base substrate.
  • a plurality of first pixel units are located in the first display area; a plurality of signal lines are at least located in the first display area and are electrically connected to the plurality of first pixel units, and the plurality of signal lines include a plurality of first signal lines and a plurality of second signal lines.
  • Two signal lines, the first part of each first signal line in the plurality of first signal lines is a metal signal line, the first part of the first signal line is at least located in the first display area, and each of the plurality of second signal lines
  • the first part of the second signal line is a metal oxide signal line, and the first part of the second signal line is at least located in the first display area.
  • step S402 may include the following steps:
  • FIG. 27 is a flow chart of a method for manufacturing a display panel provided by an implementation of the present disclosure. Referring to Figure 27, the method includes:
  • S421 Form an active layer on one side of the base substrate.
  • FIG. 28 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • an active thin film can be formed on one side of the base substrate by evaporation, and then patterned through a patterning process to obtain the active layer 206 as shown in FIG. 28 .
  • the active layer 206 includes active patterns corresponding to multiple pixel units.
  • the middle part is a complete active pattern, and the four corners are parts of other four active patterns.
  • Fig. 29 to Fig. 35 are similar to Fig. 28, they are all patterns with a pixel unit in the middle, and the four corners are parts of other pixel units.
  • the display panels shown in FIG. 28 to FIG. 35 are located in the first display area.
  • S422 Form a second gate insulating layer on a side of the active layer away from the base substrate.
  • the second gate insulating layer may be a silicon nitride layer, and the second gate insulating layer may be formed on one side of the active layer by evaporation, and the second gate insulating layer covers the active layer.
  • S423 Forming a first gate metal layer on a side of the second gate insulating layer away from the base substrate.
  • FIG. 29 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • a first gate metal layer 211 is formed on the second gate insulating layer.
  • the first gate metal layer includes the second plate 602 of the capacitor, the control electrode G of the thin film transistor, and the gate signal line Gate.
  • the gate signal line Gate is located in the first gate metal layer in the first display area and the second display area, and in the second display area, the first part of the reset signal line and the light emission control signal line in the first gate metal layer.
  • the first gate metal layer may be a metal molybdenum layer, and the first gate metal film may be formed on one side of the first gate insulating layer by sputtering, and then the first gate metal The thin film is patterned to obtain the first gate metal layer.
  • S424 Form a first gate insulating layer on a side of the first gate metal layer away from the base substrate.
  • the first gate insulating layer may be a silicon nitride layer, and the first gate insulating layer may be formed on one side of the second gate metal layer by evaporation, and the first gate insulating layer covers the second gate metal layer. gate metal layer.
  • S425 Form a second gate metal layer on a side of the first gate insulating layer away from the base substrate.
  • the second gate metal layer may be a metal molybdenum layer.
  • FIG. 30 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • a second gate metal film can be formed on one side of the first gate insulating layer by sputtering, and then patterned by a patterning process to obtain a second gate metal film.
  • the second gate metal layer 251 includes the first plate 601 of the capacitor.
  • S426 Form a first passivation layer on a side of the second gate metal layer away from the base substrate.
  • the first passivation layer may be a silicon nitride layer, and the first passivation layer may be formed on one side of the second gate metal layer by evaporation.
  • FIG. 31 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure. Referring to FIG. 31 , a first via hole 221 is formed in the first passivation layer.
  • the first via hole 221 may be formed by etching.
  • S427 Forming a first source-drain metal layer on a side of the first passivation layer away from the base substrate.
  • FIG. 32 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • the first source and drain metal film can be formed on one side of the first passivation layer by sputtering, and then patterned by patterning to obtain the first source and drain metal layer 212.
  • the data signal line Data is located in the first source-drain metal layer.
  • S428 Form an interlayer dielectric layer on a side of the first source-drain metal layer away from the base substrate.
  • the interlayer dielectric layer may be a silicon nitride layer, and the interlayer dielectric layer may be formed on one side of the metal oxide layer by evaporation.
  • S429 Form a metal oxide layer on a side of the interlayer dielectric layer away from the base substrate.
  • FIG. 33 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • a metal oxide film can be formed on one side of the interlayer dielectric layer by sputtering, and then patterned by a patterning process to obtain a metal oxide layer 203 .
  • the reset signal line Reset, the light emission control signal line EM and the second part of the initial voltage signal line Vinit are all located in the metal oxide layer 203, and the second part of the power signal line VDD A part is located in the metal oxide layer.
  • first part and the second part of the reset signal line are electrically connected through the first via hole
  • first part and the second part of the light emission control signal line are electrically connected through the first via hole
  • first part and the second part of the initial voltage signal line are electrically connected through the second via hole.
  • S4210 Form a second passivation layer on a side of the metal oxide layer away from the base substrate.
  • the second passivation layer may be a silicon nitride layer
  • the first passivation layer may be formed on one side of the first source-drain metal layer by evaporation.
  • S4211 Form a second source-drain metal layer on a side of the second passivation layer away from the base substrate.
  • the second source-drain metal layer may be a metal titanium layer.
  • FIG. 34 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure.
  • the second source and drain metal film can be formed on one side of the second passivation layer by sputtering, and then patterned by patterning process to obtain the second source and drain metal layer 209.
  • the second source-drain metal layer 209 covers the first source-drain metal layer 212 .
  • the second part of the power signal line is located in the second source-drain metal layer 209 .
  • the second source-drain metal layer such as a planarization layer, a pixel defining layer, a light-emitting layer, and an encapsulation layer, to complete the fabrication of the display panel.
  • FIG. 35 is a process diagram of a manufacturing method of a display panel provided by an embodiment of the present disclosure. Referring to FIG. 35 , an anode layer 2012 is formed on the second source-drain metal layer 209 .
  • the manufacturing process diagram of the insulating layer is omitted in the above manufacturing process diagram.
  • An embodiment of the present disclosure also provides a display device.
  • the display device includes a power supply component and the above-mentioned display panel, and the power supply component is used to supply power to the display panel.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device further includes a photosensor, the photosensor is located on the side of the display panel away from the plurality of first pixel units, and the orthographic projection of the photosensor on the base substrate is the same as that of the first pixel unit.
  • a display area at least partially overlaps.

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Abstract

本公开是关于一种显示面板及其制作方法和显示装置，属于显示技术领域。显示面板包括衬底基板、多个第一像素单元和多根信号线；衬底基板具有显示区域和周边区域，显示区域包括第一显示区域和第二显示区域，第一显示区域的透光率大于第二显示区域的透光率；多个第一像素单元位于衬底基板上且位于第一显示区域；多根信号线至少位于第一显示区域且与多个第一像素单元电连接；其中，多根信号线包括多根第一信号线和多根第二信号线，多根第一信号线中的每根第一信号线的第一部分为金属信号线，多根第二信号线中的每根第二信号线的第一部分为金属氧化物信号线，第一信号线的第一部分至少位于第一显示区域，第二信号线的第一部分至少位于第一显示区域。

Description

显示面板及其制作方法和显示装置
本公开要求于2021年8月16日提交的申请号为202110939190.3、发明名称为“显示面板及其制作方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及其制作方法和显示装置。
背景技术
全面屏显示装置的屏占比较高，具有很好的观感效果，为了提高全面屏显示装置的屏占比，屏下摄像头技术已经逐渐在手机等显示装置中发展起来。
全面屏显示装置包括显示面板和全显示摄像头(Full Display Camera，FDC)，显示面板具有摄像头显示区域，摄像头显示区域中布置有像素单元，使得摄像头显示区域能够显示画面。FDC布置在显示面板的下方，且与摄像头显示区域相对。
发明内容
本公开实施例提供了一种显示面板及其制作方法和显示装置，可以提高显示装置的显示均一性。所述技术方案如下：
一方面，本公开提供了一种显示面板，所述显示面板包括：衬底基板，具有显示区域和至少部分围绕所述显示区域的周边区域，所述显示区域包括第一显示区域和至少位于所述第一显示区域一侧的第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率；多个第一像素单元，位于所述衬底基板上且位于所述第一显示区域；多根信号线，至少位于所述第一显示区域且与所述多个第一像素单元电连接；其中，所述多根信号线包括多根第一信号线和多根第二信号线，所述多根第一信号线中的每根第一信号线的第一部分为金属信号线，所述第一信号线的第一部分至少位于所述第一显示区域；所述多根第二信号线中的每根第二信号线的第一部分为金属氧化物信号线，所述第二 信号线的第一部分至少位于所述第一显示区域。
在本公开实施例的一种实现方式中，所述第一信号线包括以下信号线中的至少一种：栅极信号线、数据信号线、复位信号线、发光控制信号线、初始电压信号线和电源信号线。
在本公开实施例的一种实现方式中，所述第一信号线包括栅极信号线和数据信号线。
在本公开实施例的一种实现方式中，所述第一信号线还包括位于所述第二显示区域的第二部分，所述第二信号线还包括位于所述第二显示区域的第二部分，所述第一信号线的第二部分和所述第二信号线的第二部分均为金属信号线。
在本公开实施例的一种实现方式中，所述显示面板还包括沿远离所述衬底基板的方向依次位于所述衬底基板上的第一金属层、第一绝缘层以及金属氧化物层；所述第一信号线位于所述第一金属层；所述多根第二信号线中的至少一根第二信号线在所述第一显示区域内的第一部分位于所述金属氧化物层，在所述第二显示区域的第二部分位于所述第一金属层，所述第二信号线的第一部分和第二部分通过贯穿所述第一绝缘层的第一过孔连接，所述第一过孔在所述第一显示区域和所述第二显示区域的交界处。
在本公开实施例的一种实现方式中，所述第一金属层包括第一栅极金属层和第一源漏金属层，所述第一绝缘层包括第一钝化层和层间介电层；沿远离所述衬底基板的方向，所述第一栅极金属层、所述层间介电层、所述第一源漏金属层和所述第一钝化层依次层叠。
在本公开实施例的一种实现方式中，所述显示面板还包括第二绝缘层和第二金属层，沿远离所述衬底基板的方向，所述第二金属层、所述第二绝缘层、所述第一金属层、所述第一绝缘层和金属氧化物层依次层叠；所述多根第二信号线中的另一部分第二信号线在所述第一显示区域内的第一部分位于所述金属氧化物层，在所述第二显示区域的第二部分位于所述第二金属层内，所述第二信号线的第一部分和第二部分通过贯穿所述第一绝缘层和所述第二绝缘层的第二过孔连接，所述第二过孔在所述第一显示区域和所述第二显示区域的交界处。
在本公开实施例的一种实现方式中，所述第二金属层包括第二栅极金属层，所述第二绝缘层包括第一栅极绝缘层。
在本公开实施例的一种实现方式中，所述第一显示区域的第一尺寸与所述 第一显示区域的第二尺寸的比值大于2时，所述第一信号线为栅极信号线，所述第一显示区域的第一尺寸为所述第一显示区域在所述栅极信号线的延伸方向上的尺寸，所述第一显示区域的第二尺寸为所述第一显示区域在数据信号线的延伸方向上的尺寸。
在本公开实施例的一种实现方式中，所述第一显示区域的第一尺寸与所述第一显示区域的第二尺寸的比值小于0.5时，所述第一信号线为数据信号线，所述第一显示区域的第一尺寸为所述第一显示区域在栅极信号线延的伸方向上的第一尺寸，所述第一显示区域的第二尺寸为所述第一显示区域在所述数据信号线的延伸方向上的尺寸。
在本公开实施例的一种实现方式中，所述第一显示区域的第一尺寸与所述第一显示区域的第二尺寸的比值在0.5至2之间时，所述第一信号线包括栅极信号线和数据信号线，所述第一显示区域的第一尺寸为所述第一显示区域在栅极信号线的延伸方向上的尺寸，所述第一显示区域的第二尺寸为所述第一显示区域在所述数据信号线的延伸方向上的尺寸。
在本公开实施例的一种实现方式中，所述显示面板还包括多个第二像素单元，所述多个第二像素单元位于所述第二显示区域，所述多个第一像素单元和所述多个第二像素单元排成多行像素单元，在一行像素单元的排列方向上，相邻两行像素单元中的像素单元相互错开；相邻两行像素单元中的像素单元通过一根栅极信号线相连。
在本公开实施例的一种实现方式中，所述栅极信号线呈波浪线型，且所述栅极信号线的波峰和波谷分别连接相邻两行像素单元中的像素单元。
在本公开实施例的一种实现方式中，所述数据信号线呈波浪线型，且所述数据信号线的波峰和波谷分别连接同一列像素单元中的相邻两个像素单元。
在本公开实施例的一种实现方式中，所述金属信号线包含钼信号线或包含钛信号线。
在本公开实施例的一种实现方式中，所述金属氧化物信号线为透明的金属氧化物信号线。
在本公开实施例的一种实现方式中，所述金属氧化物信号线为氧化铟锡信号线。
另一方面，本公开提供了一种显示面板的制作方法，所述制作方法包括：
提供一衬底基板，所述衬底基板具有显示区域和至少部分围绕所述显示区域的周边区域，所述显示区域包括第一显示区域和至少位于所述第一显示区域一侧的第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率；在所述衬底基板上形成多个第一像素单元和多根信号线，所述多个第一像素单元位于所述第一显示区域；多根信号线至少位于所述第一显示区域且与所述多个第一像素单元电连接，所述多根信号线包括多根第一信号线和多根第二信号线，所述多根第一信号线中的每根第一信号线的第一部分为金属信号线，所述第一信号线的第一部分至少位于所述第一显示区域；所述多根第二信号线中的每根第二信号线的第一部分为金属氧化物信号线，所述第二信号线的第一部分至少位于所述第一显示区域。
另一方面，本公开提供了一种显示装置，所述显示装置包括供电组件，以及上述任一方面所述的显示面板，所述供电组件用于为所述显示面板供电。
在本公开实施例的一种实现方式中，所述显示装置还包括光感传感器，所述光感传感器位于所述显示面板远离所述多个第一像素单元的一侧，且所述光感传感器在所述衬底基板的正投影与所述第一显示区域至少部分重叠。
本公开实施例提供的技术方案带来的有益效果至少包括：
在本公开实施例中，第一显示区域的透光率较高，光感传感器(例如：全面屏摄像头)可布置在与第一显示区域对应的区域，使得光线能够透过第一显示区域传播至光感传感器。第一信号线在第一显示区域内的第一部分为金属信号线，金属的电阻相对于金属氧化物的电阻要小一些，可以减小第一信号线的电阻，减小第一信号线的负载，使得第一显示区域内的像素单元接收到的电压增大，位于第一显示区域内的像素单元接收到的电压与其他区域的像素单元接收到的电压相差较小，改善显示不均一的现象。同时第二信号线的第一部分为金属氧化物信号线，从而保证第一显示区域的透光率。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所 需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示面板的平面示意图；
图2是本公开实施例提供的一种显示面板的结构示意图；
图3是本公开实施例提供的一种显示面板的结构示意图；
图4是图2中A-A面的截面图；
图5是本公开实施例提供的一种显示面板的结构示意图；
图6是本公开实施例提供的一种显示面板的结构示意图；
图7是本公开实施例提供的一种显示面板的结构示意图；
图8是本公开实施例提供的一种显示面板的结构示意图；
图9是本公开实施例提供的一种显示面板的结构示意图；
图10是本公开实施例提供的一种像素的膜层示意图；
图11是本公开实施例提供的一种第一显示区域的俯视图；
图12是本公开实施例提供的另一种第一显示区域的俯视图；
图13是本公开实施例提供的一种第一显示区域的像素排布图；
图14是本公开实施例提供的另一种第一显示区域的俯视图；
图15是本公开实施例提供的另一种第一显示区域的俯视图；
图16是本公开实施例提供的另一种第一显示区域的俯视图；
图17是本公开实施例提供的另一种第一显示区域的俯视图；
图18是本公开实施例提供的另一种第一显示区域的像素排布图；
图19是本公开实施例提供的另一种第一显示区域的俯视图；
图20是本公开实施例提供的另一种第一显示区域的俯视图；
图21是本公开实施例提供的另一种第一显示区域的俯视图；
图22是本公开实施例提供的另一种第一显示区域的俯视图；
图23是本公开实施例提供的另一种第一显示区域的像素排布图；
图24是本公开实施例提供的一种显示面板的结构示意图；
图25是本公开实施例提供的一种7T1C像素电路图；
图26是本公开实施提供的一种显示面板的制作方法的流程图；
图27是本公开实施提供的一种显示面板的制作方法的流程图；
图28是本公开实施例提供的一种显示面板的制作方法的过程图；
图29是本公开实施例提供的一种显示面板的制作方法的过程图；
图30是本公开实施例提供的一种显示面板的制作方法的过程图；
图31是本公开实施例提供的一种显示面板的制作方法的过程图；
图32是本公开实施例提供的一种显示面板的制作方法的过程图；
图33是本公开实施例提供的一种显示面板的制作方法的过程图；
图34是本公开实施例提供的一种显示面板的制作方法的过程图；
图35是本公开实施例提供的一种显示面板的制作方法的过程图。
附图标记：
100、显示区域；200、周边区域；10、衬底基板；101、第一显示区域；102、第二显示区域；20、像素单元；30、信号线；301、第一信号线；302、第二信号线；201、第一金属层；202、第一绝缘层；203、金属氧化物层；221、第一过孔；211、第一栅极金属层；212、第一源漏金属层；222、第一钝化层；223、层间介电层；204、第二绝缘层；205、第二金属层；241、第二过孔；251、第二栅极金属层；242、第一栅极绝缘层；206、有源层；207、第二栅极绝缘层；208、第二钝化层；209、第二源漏金属层；2010、缓冲层；2011、平坦化层；2012、阳极层；2013、像素界定层；2014、隔垫物层；2015、发光层；2016、阴极层；2017、第一无机封装层；2018、有机封装层；2019、第二无机封装层；L1、第一尺寸；L2、第二尺寸；40、第二像素单元；50、光感传感器；60、电容；601、第一极板；602、第二极板。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
相关技术中，为提高摄像头显示区域的透光率，使得FDC能够接收到足够的光线成像，位于摄像头显示区域中的像素单元之间的信号线均为透明的金属氧化物信号线，例如，氧化铟锡(Indium Tin Oxide，ITO)信号线。
金属氧化物信号线的电阻较大会产生较大的负载，使得与金属氧化物信号线连接的像素单元接收到的电压比其他显示区域的像素单元接收到的电压小，从而使得摄像头显示区域的显示效果与其他显示区域的显示效果的差异较大， 造成显示不均一。
图1是本公开实施例提供的一种显示面板的平面示意图。参见图1，显示面板包括衬底基板10，衬底基板10具有显示区域100和至少部分围绕显示区域100的周边区域200。显示区域100可用于布置像素电路，周边区域200可用于布置集成电路，集成电路用于驱动像素电路工作。示例性地，周边区域200至少部分围绕显示区域100表示，周边区域200可以包围显示区域100；或者，显示区域100的两侧与周边区域200相接；或者，显示区域100与周边区域200并排，此时显示区域100的一侧与周边区域200相接。
显示区域100包括第一显示区域101和至少位于第一显示区域101一侧的第二显示区域102，第一显示区域101的透光率大于第二显示区域102的透光率。第一显示区域101的透光率较高，如此，无需在衬底基板10上进行挖孔处理，可以将光感传感器等所需硬件结构直接设置在与第一显示区域101相对的位置，实现真全面屏显示装置。示例性地，光感传感器可以为摄像头。
在图1中，第一显示区域101的形状为矩形，在其他实现方式中，第一显示区域101的形状可以为圆形、多边形、以及其他规则或不规则的形状等。
示例性地，至少位于第一显示区域101一侧的第二显示区域102表示，第二显示区域102可以围绕第一显示区域101；或者，第一显示区域101的两侧与第二显示区域102相接；或者，第一显示区域101与第二显示区域102并排，此时第一显示区域101的一侧与第二显示区域102相接。
再次参见图1，第二显示区域102包围第一显示区域101。示例性地，第一显示区域101位于衬底基板10的顶部区域的中间位置。
在一些实施例中，该第一显示区域101也可以位于衬底基板10的其他位置。例如，结合图1，第一显示区域101可以位于衬底基板10的左上角位置或右上角位置处。
图2是本公开实施例提供的一种显示面板的结构示意图。参见图2，显示面板还包括多个第一像素单元20和多根信号线30。多个第一像素单元20位于衬底基板10上且位于第一显示区域101。多根信号线30至少位于第一显示区域101且与多个第一像素单元20电连接。
图3是本公开实施例提供的一种显示面板的结构示意图。参见图3，多根信号线30包括多根第一信号线301和多根第二信号线302。例如，第一信号线301 可以包括栅极信号线和数据信号线，第二信号线302可以包括复位信号线。多个第一像素单元20排成多行像素单元，在一行像素单元的排列方向上，相邻两行像素单元中的像素单元相互错开，相邻两行像素单元中的像素单元通过一根第一信号线301或一根第二信号线302相连。第一信号线301和第二信号线302线均呈波浪线型。
多根第一信号线301中的每根第一信号线301的第一部分为金属信号线，第一信号线301的第一部分至少位于第一显示区域101。多根第二信号线302中的每根第二信号线302的第一部分为金属氧化物信号线，第二信号线302的第一部分至少位于第一显示区域101。
在本公开实施例中，第一显示区域101的透光率较高，光感传感器(例如：全面屏摄像头)可布置在与第一显示区域101对应的区域，使得光线能够透过第一显示区域101传播至光感传感器。第一信号线301在第一显示区域101内的第一部分为金属信号线，金属的电阻相对于金属氧化物的电阻要小一些，可以减小第一信号线301的电阻，减小第一信号线的负载，使得第一显示区域101内的像素单元20接收到的电压增大，位于第一显示区域101内的像素单元20接收到的电压与其他区域的像素单元20接收到的电压相差较小，改善显示不均一的现象。同时第二信号线302的第一部分为金属氧化物信号线，从而保证第一显示区域101的透光率。
同时，由于第一显示区域101内的第一像素单元20是规律排布的，像素单元20之间的缝隙也是规律排布的，光线经过于第一显示区域101中的缝隙时容易产生衍射现象，产生衍射现象的光线再传播至全面屏摄像头处，会影响全面屏摄像头的摄像效果。在本公开实施例中，将经过第一显示区域101的第一信号线301中的每根第一信号线301的第一部分布置为金属信号线，金属信号线不是透明的，从而打破了像素单元20之间的缝隙的规律排布现象，对于光线的衍射有一定的改善，从而可以提高全面屏摄像头的摄像效果。
在本公开实施例中，第一信号线301还包括位于第二显示区域102的第二部分，第二信号线302还包括位于第二显示区域102的第二部分，第一信号线301的第二部分和第二信号线302的第二部分均为金属信号线。
在本公开实施例中，第二显示区域102中无需布置光感传感器，所以第二显示区域102不需要具备较高的透光率，将第二显示区域102中的第一信号线 301和第二信号线302均布置为金属信号线，可以减小第一信号线301和第二信号线302的负载，提高显示面板的显示亮度，改善显示效果。
在本公开实施例中，多根第二信号线302中的每根第二信号线302的第一部分为透明金属氧化物信号线，使得第一显示区域101的部分信号线30是透明的信号线，从而保证第一显示区域101的透光率。
在本公开实施例的一种实现方式中，第一信号线301包括栅极(Gate)信号线和数据(Data)信号线中的至少一种。
每一个第一像素单元20均包括开关晶体管和驱动晶体管，栅极信号线负责给开关晶体管的栅极提供导通电压，数据信号线负责给驱动晶体管的栅极提供导通电压。透明金属氧化物信号线的电阻较大，采用透明金属氧化物信号线会导致导通电压较小，使得开关薄膜晶体管无法导通，或者开关薄膜晶体管导通的时间较短，与采用金属信号线的区域相比亮度不一致，影响了显示面板的显示均一性。在本公开实施例中，通过将第一显示区域101内的栅极信号线和数据信号线中的至少一种信号线替换成金属信号线，从而可以减小栅极信号线或数据信号线的电阻，提高位于第一显示区域101内的第一像素单元20的导通电压，从而改善显示均一性。
示例性地，金属氧化物信号线可以为氧化铟锡信号线，氧化铟锡的透明性好，保证金属氧化物信号线的透明性。
再次参见图2，显示面板还包括多个第二像素单元40，多个第二像素单元40位于第二显示区域102，多个第二像素单元40和多个第一像素单元20排成多行像素单元。
由于第一像素单元20和第二像素单元40的透光率都较差，为提高第一显示区域101的透光率，可以在制作时，将第一像素单元20的尺寸设计成小于第二像素单元40的尺寸，来提高第一显示区域101的透光率。
在本公开实施例的一种实现方式中，信号线30还包括复位(Reset)信号线、发光控制(EM)信号线、初始电压(Vinit)信号线和电源(VDD)信号线。信号线30中除第一信号线301外均为第二信号线302，也即复位信号线、发光控制信号线、初始电压信号线和电源信号线均为第二信号线302。
金属信号线的电阻小，但透光率较差，透明金属氧化物信号线的电阻大，但透光率较高。由于显示装置中与第一显示区域101对应的区域布置有光感传 感器，在减小第一显示区域101内信号线电阻的同时，还需要保证第一显示区域101的透光率。通过实验模拟发现复位信号线、发光控制信号线、初始电压信号线和电源信号线等信号线对显示亮度的影响较小，将这些信号线布置为透明金属氧化物信号线，可以保证第一显示区域101的透光率。
在本公开实施例的一种实现方式中，第一信号线301包括栅极信号线和数据信号线，第二信号线302包括复位信号线、发光控制信号线、初始电压信号线和电源信号线。
在本公开实施例的一种实现方式中，栅极信号线包含钼信号线。数据信号线包含钛信号线。
在相关技术中，经过第一显示区域的第一信号线的第一部分的材质是金属氧化物，在本公开实施例中，经过第一显示区域的第一信号线的第一部分的材质是金属，这样，经过第一显示区域的第一信号线和未经过第一显示区域的第一信号线可以采用相同方式制作，也即整条信号线都在同一层。
图4是图2中A-A面的截面示意图。参见图4，显示面板包括沿远离衬底基板10的方向依次位于衬底基板10上的第一金属层201、第一绝缘层202和金属氧化物层203，第一信号线301(图4未示出)位于第一金属层201内，位于第一显示区域101内的多根第二信号线302中的至少一根第二信号线302在第一显示区域101内的第一部分位于金属氧化物层203，在第二显示区域102的第二部分位于第一金属层201内，第二信号线302的第一部分和第二部分通过贯穿第一绝缘层202的第一过孔221连接，第一过孔221在第一显示区域101和第二显示区域102的交界处。其中，第一显示区域101和第二显示区域102的交界处指第一显示区域101与第二显示区域102连接的边界所在的区域。多根第二信号线302中的至少一根第二信号线302，表示可以是一根第二信号线302，或者多根第二信号线302，或者全部第二信号线302。
在本公开实施例中，第一信号线301为金属信号线，布置在第一金属层201中，第二信号线302在第一显示区域101内为透明金属氧化物信号线，在第二显示区域102内为金属线，将第一显示区域101内的第二信号线302布置在金属氧化物层203中，保证第二信号线302的第一部分的透光率。将第二显示区域102内的第二信号线302布置在第一金属层201中，减小第二信号线302的第二部分的电阻。同时通过第一过孔221将第二信号线302的第一部分和第二 部分连接起来，保证电连接的有效性。
在本公开实施例中，第一金属层201包括第一栅极金属层和第一源漏金属层，第一绝缘层202包括第一钝化层和层间介电层。
示例性地，第一信号线301包括栅极信号线和数据信号线中一种，第二信号线302包括栅极信号线和数据信号线中另一种。例如，第一信号线301为栅极信号线，第二信号线302为数据信号线，栅极信号线位于第一栅极金属层211，在第一显示区域101中的数据信号线位于金属氧化物层203，在第二显示区域102中的数据信号线位于第一源漏金属层212。
图5是本公开实施例提供的一种显示面板的结构示意图。其中图4和图5分别为不同截面处的截面图，参见图5，显示面板包括沿远离衬底基板10的方向依次位于衬底基板10上的第一栅极金属层211、第一钝化层222、第一源漏金属层212、层间介电层223和金属氧化物层203。此时显示面板只包括一层栅极金属层和一层源漏金属层，前述第一金属层201包括第一栅极金属层211和第一源漏金属层212，前述第一绝缘层202包括第一钝化层222和层间介电层223。第一信号线301既包括栅极信号线又包括数据信号线，在第一显示区域101和第二显示区域102内，栅极信号线均位于第一栅极金属层211，在第一显示区域101和第二显示区域102内，数据信号线均位于第一源漏金属层212中。在图5中只示出了第一信号线301。
图6是本公开实施例提供的一种显示面板的结构示意图。参见图6，显示面板包括第一栅极金属层211、第一钝化层222、第一源漏金属层212、层间介电层223和金属氧化物层203，沿远离衬底基板10的方向，第一栅极金属层211、第一钝化层222、第一源漏金属层212、层间介电层223和金属氧化物层203依次层叠。
示例性地，第二信号线302包括初始电压信号线。在第一显示区域101内，第二信号线302位于金属氧化物层203，在第二显示区域102内，第二信号线302位于第一栅极金属层211。在图6中只示出了第二信号线302。
示例性地，第二信号线302还包括复位信号线和发光控制信号线。在第二显示区域102内，复位信号线和发光控制信号线位于第一栅极金属层211，在第一显示区域101内，复位信号线和发光控制信号线位于金属氧化物层203。位于第一显示区域101内的复位信号线和位于第二显示区域102内的复位信号线通 过第一过孔221电连接，位于第一显示区域101内的发光控制信号线和位于第二显示区域102内的发光控制信号线通过第一过孔221电连接，此时第一过孔221穿过第一钝化层222、第一源漏金属层212和层间介电层223。
图7是本公开实施例提供的一种显示面板的结构示意图。参见图7，显示面板包括位于衬底基板10上的第一栅极金属层211、第一钝化层222、第一源漏金属层212、层间介电层223和金属氧化物层203。此时，第二信号线302包括电源信号线。在第一显示区域101内，第二信号线302位于金属氧化物层203，在第二显示区域102内，第二信号线302位于第一源漏金属层212。在图7中只示出了第二信号线302。
再次参见图7，第二信号线302为电源信号线，在第二显示区域102内，电源信号线位于第一源漏金属层212，在第一显示区域101内，电源信号线位于金属氧化物层203。位于第一显示区域101内的电源信号线和位于第二显示区域102内的电源信号线通过第一过孔221电连接，此时第一过孔221穿过层间介电层223。在其他实现发生中，电源信号线还可以位于第二源漏金属层中。
图8是本公开实施例提供的一种显示面板的结构示意图。参见图8，相比于图4，该显示面板还包括第二绝缘层204和第二金属层205，第二绝缘层204位于第一金属层201和第二金属层205之间。多根第二信号线302中的另一部分第二信号线302在第一显示区域101内的第一部分位于金属氧化物层203，在第二显示区域102的第二部分位于第二金属层205内，第二信号线302的第一部分和第二部分通过贯穿第一绝缘层202和第二绝缘层204的第二过孔241连接，第二过孔241在第一显示区域101和第二显示区域102的交界处。
在本公开实施例的一种实现方式中，第二金属层205为第二栅极金属层，第二绝缘层204为第一栅极绝缘层。
示例性地，第二信号线302还可以包括复位信号线、发光控制信号线、初始电压信号线和电源信号线，在第一显示区域101内，复位信号线、发光控制信号线、初始电压信号线和电源信号线位于金属氧化物层203，在第二显示区域102中，复位信号线、发光控制信号线、初始电压信号线和电源信号线位于第二栅极金属层。
在本公开实施例的一种实现方式中，第二金属层205为第二栅极金属层，第二绝缘层204为第一栅极绝缘层。
图9是本公开实施例提供的一种显示面板的结构示意图。参见图9，相比于图8，显示面板包括沿远离衬底基板10的方向依次位于衬底基板10上的第二栅极金属层251、第一栅极绝缘层242、第一栅极金属层211、第一钝化层222、第一源漏金属层212、层间介电层223和金属氧化物层203。
再次参见图9，第二信号线302为初始电压信号线，在第二显示区域102内，初始电压信号线位于第二栅极金属层251，在第一显示区域101内，初始电压信号线位于金属氧化物层203。位于第一显示区域101内的部分初始电压信号线和位于第二显示区域102内的部分初始电压信号线通过第二过孔241电连接，此时第二过孔241穿过第一栅极绝缘层242、第一栅极金属层211、第一钝化层222、第一源漏金属层212和层间介电层223。
需要说明的是，栅极信号线位于第一栅极金属层211，数据信号线位于第一源漏金属层212。
再次参见图9，显示面板还包括有源层206、第二栅极绝缘层207、第二钝化层208和第二源漏金属层209。第二栅极绝缘层207位于有源层206和第二栅极金属层251之间，第二钝化层208位于金属氧化物层203和第二源漏金属层209之间。
其中，有源层206可以为多晶硅(Polycrystalline Silicon)材料层，简称Poly层。第二栅极绝缘层207将有源层206和第二栅极金属层251隔开。第二源漏金属层209为转线层，第二钝化层208将第一源漏金属层212和第二源漏金属层209隔开。
在本公开实施例中，第一栅极金属层211和第二栅极金属层251包含金属钼层，第一源漏金属层212和第二源漏金属层209包含金属钛层。第二栅极绝缘层207、第一栅极绝缘层242、层间介电层223、第一钝化层222和第二钝化层208可以为氮化硅层、氧化硅层或环氧树脂层中的一种。
在本公开实施例中，衬底基板10可以为玻璃衬底或聚酰亚胺衬底。
前面图4至图9均示出的是显示面板的部分膜层，下面结合图10对显示面板较为完整的膜层结构进行介绍，图10的膜层结构对应前述图2中第一像素单元20的结构。
图10是本公开实施例提供的一种像素的膜层示意图。参见图10，显示面板包括沿远离衬底基板10的方向依次位于衬底基板10上的缓冲层(Buffer)2010、 有源层206、第二栅极绝缘层207、第二栅极金属层251、第一栅极绝缘层242、第一栅极金属层211、层间介电层223、第一源漏金属层212、第二钝化层208、平坦化层2011、阳极层2012、像素界定层2013、隔垫物层2014、发光层2015、阴极层2016、第一无机封装层2017、有机封装层2018和第二无机封装层2019。此时显示面板只包括一层源漏金属层，也即第一源漏金属层212。
缓冲层2010位于衬底基板10和有源层206之间，缓冲层2010用于减小刻蚀有源层206时对衬底基板10的影响。
平坦化层2011位于第二钝化层208远离第一源漏金属层212的一侧，平坦化层2011用于使得制作的了第一源漏金属层212的显示面板的表面更加平坦。
阳极层2012位于平坦化层2011远离第一源漏金属层212的一侧，且阳极层2012与第一源漏金属层212电连接。像素界定层2013位于阳极层2012第一源漏金属层212的一侧，像素界定层2013中具有开口，该开口与阳极层2012连通，且发光层2015位于开口内。隔垫物层2014在蒸镀发光层2015时可用于支撑掩膜板。阴极层2016位于发光层2015远离第一源漏金属层212的一侧，阴极层2016和阳极层2012之间形成电压，从而控制发光层2015发光。第一无机封装层2017、有机封装层2018和第二无机封装层2019共同组成封装层，对显示面板进行封装，保证显示面板的完整性。
在本公开实施例中，像素单元包括电容60，再次参见图10，电容60的第一极板601位于第二栅极金属层251，电容的第二极板602位于第一栅极金属层211。
在图10中，第二栅极绝缘层207、第二栅极金属层251、第一栅极绝缘层242、第一栅极金属层211沿远离衬底基板10的方向依次排布。在其他实现方式中，可以是第二栅极绝缘层207、第一栅极金属层211、第一栅极绝缘层242和第二栅极金属层251依次排布的，本公开对此不作限制。
图11是本公开实施例提供的第一显示区域的俯视图。参见图11，第一显示区域101为长条状，第一显示区域101的第一尺寸L1大于第一显示区域101的第二尺寸L2，第一显示区域101的第一尺寸L1为第一显示区域101在栅极信号线的延伸方向上的尺寸，第一显示区域101的第二尺寸L2为第一显示区域101在数据信号线的延伸方向上的尺寸。显示装置包括多个光感传感器50，多个光感传感器50在显示面板上的正投影位于第一显示区域101内，多个光感传感器 50的延伸方向与栅极信号线的延伸方向平行。
在图11中，显示装置中与第一显示区域101对应的区域内布置有3个光感传感器50。
图12是本公开实施例提供的另一种第一显示区域的俯视图。参见图12，显示装置包括4个光感传感器50。4个光感传感器50分为两组，一组包括两个光感传感器50，同一组中的两个光感传感器50之间的距离为0，相邻两组之间具有一定的间隙。
在其他实现方式中，显示装置内还可以布置有其他数量光感传感器50，本公开对此不做限制。
对于图11和图12所示的第一显示区域101，第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸的比值大于2。
图13是本公开实施例提供的一种第一显示区域的像素排布图。结合图11至图13，第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸的比值大于2时，第一信号线301为栅极信号线。
栅极信号线与多个第一像素单元20电连接，栅极信号线有负载，那么距离驱动电路较近的第一像素单元20接收到的栅极电压会大一些，距离驱动电路较远的第一像素单元20接收到的栅极电压会小一些。当第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2的比值大于2时，说明此时栅极信号线在第一显示区域101中的长度要大于数据信号线在第一显示区域101中的长度。而信号线的长度与电阻信号线的电阻负相关，那么在第一显示区域101中，栅极信号线造成的显示不均一下的现象更大一些。将栅极信号线布置为金属信号线，可以减小栅极信号线造成的显示不均一下的现象，改善显示不均一的现象。
在图11至图13中，第一显示区域101沿第一尺寸L1的延伸方向延伸，在其他实现中，第一显示区域101还可以沿其他方向延伸。
图14是本公开实施例提供的另一种第一显示区域的俯视图。参见图14，第一显示区域101同样为长条状，第一显示区域101的第一尺寸L1小于第一显示区域101的第二尺寸L2，第一显示区域101内布置有多个光感传感器50，多个光感传感器50的延伸方向为第二尺寸L2的延伸方向。
在图14中，显示装置包括2个光感传感器50。图15是本公开实施例提供 的另一种第一显示区域的俯视图。参见图15，显示装置包括4个光感传感器50。4个光感传感器50分为两组，一组包括两个光感传感器50，同一组中的两个光感传感器50之间的距离为0，相邻两组之间具有一定的间隙。
图16是本公开实施例提供的另一种第一显示区域的俯视图。参见图16，显示装置包括4个光感传感器50，相邻的两个光感传感器50之间的距离为0。
图17是本公开实施例提供的另一种第一显示区域的俯视图。参见图17，显示装置包括3个光感传感器50，相邻的两个光感传感器50之间的距离为0。
在其他实现方式中，显示装置包括还可以布置有其他数量光感传感器50，本公开对此不做限制。
对于图14至图17所示的第一显示区域101，第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2的比值小于0.5。图18是本公开实施例提供的另一种第一显示区域的像素排布图。结合图14至图18，第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2的比值小于0.5时，第一信号线301为数据信号线。
数据信号线与栅极信号线相似，距离驱动电路较近的第一像素单元20接收到的数据电压会大一些，距离驱动电路较远的第一像素单元20接收到的数据电压会小一些。当第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2的比值小于0.5时，说明此时数据信号线在第一显示区域101中的长度要大于栅极信号线在第一显示区域101中的长度。在第一显示区域101中，数据信号线造成的显示不均一下的现象更大一些。将数据信号线布置为金属信号线，可以减小数据信号线造成的显示不均一下的现象，改善显示不均一的现象。
在图11至图18中，第一显示区域101均为长条状。在其他实现方式中，第一显示区域101还可以为方块状。
图19是本公开实施例提供的另一种第一显示区域的俯视图。参见图19，第一显示区域101为方块状，第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2相差不大，第一显示区域101内布置有3个光感传感器50，3个光感传感器50呈三角形布置。
在图19中，显示装置包括3个光感传感器50。图20是本公开实施例提供的另一种第一显示区域的俯视图。参见图20，显示装置包括4个光感传感器50，4个光感传感器50呈正方形布置。
图21是本公开实施例提供的另一种第一显示区域的俯视图。参见图21，显示装置包括5个光感传感器50，5个光感传感器50呈五边形布置。
图22是本公开实施例提供的另一种第一显示区域的俯视图。参见图22，显示装置包括6个光感传感器50，6个光感传感器50呈六边形布置。
在其他实现方式中，显示装置包括内还可以布置有其他数量光感传感器50，本公开对此不做限制。
对于图19至图22所示的第一显示区域101，第一显示区域101的第一尺寸与第一显示区域101的第二尺寸的比值在0.5至2之间。图23是本公开实施例提供的另一种第一显示区域的像素排布图。结合图19至图23，在第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2的比值在0.5至2之间时，第一信号线301包括栅极信号线和数据信号线。
当第一显示区域101的第一尺寸L1与第一显示区域101的第二尺寸L2的比值在0.5至2之间时，说明在第一显示区域101内，栅极信号线的长度和数据信号线的长度相差不大，栅极信号线和数据信号线造成的显示不均一下的现象也相差不大，将栅极信号线和数据信号线均布置为金属信号线，可以同时减小栅极信号线和数据信号线造成的显示不均一下的现象，改善显示不均一的现象。
图24是本公开实施例提供的一种显示面板的结构示意图。参见图24，显示面板包括多个第一像素单元20和多个第二像素单元40。多个第一像素单元20和多个第二像素单元40排成多行像素单元，在一行像素单元的排列方向上，相邻两行像素单元中的像素单元相互错开，相邻两行像素单元中的像素单元通过一根栅极信号线相连。
多排像素单元错开布置，在相同的面积上，可以布置更多的像素单元，提高像素单元的密度，从而提高显示面板的分辨率，进一步提高显示效果。同时，通过栅极信号线连接相邻两行像素单元中的像素单元，避免走线过于复杂，简化电路结构。
再次参见图3和图24，栅极信号线呈波浪线型，且栅极信号线的波峰和波谷分别连接第一像素单元20或第二像素单元40。
再次参见图3和图24，数据信号线同样呈波浪型。
在本公开实施例中，第一像素单元20和第二像素单元40均包括7T1C像素电路。
图25是本公开实施例提供的一种7T1C像素电路图。参见图25，像素电路包括第一开关晶体管T1、第一补偿晶体管T2、第一复位晶体管T3、第二复位晶体管T4、驱动晶体管T5、第一发光控制晶体管T6、第二发光控制晶体管T7和电容Cst。
第一开关晶体管T1的控制极通过第一扫描信号端(Scan[n])与一根栅线电连接，第一开关晶体管T1的第一极通过数据输入端(Data[m])与一根数据线电连接，第一开关晶体管T1的第二极和第一节点N1电连接。
第一补偿晶体管T2的控制极通过第一扫描信号端(Scan[n])与一根栅线电连接，第一补偿晶体管T2的第一极与第二节点N2电连接，第一补偿晶体管T2的第二极与第三节点N3电连接。
第一复位晶体管T3的控制极通过第二扫描信号端(Scan[n-1])与另一根栅线电连接，第一复位晶体管T3的第一极通过初始化电压端(Vinit)与初始电压信号线电连接，第一复位晶体管T3的第二极与第三节点N3电连接。
第二复位晶体管T4的控制极通过第一扫描信号端(Scan[n])与一根栅线电连接，第二复位晶体管T4的第一极通过初始化电压端(Vinit)与初始电压信号线电连接，第二复位晶体管T4的第二极与第四节点N4电连接。
驱动晶体管T5的控制极与第三节点N3电连接，驱动晶体管T5的第一极与第一节点N1电连接，驱动晶体管T5的第二极与第二节点N2电连接。
第一发光控制晶体管T6的控制极通过发光控制信号端(EM[n])与发光控制信号线电连接，第一发光控制晶体管T6的第一极与第一节点N1电连接，第一发光控制晶体管T6的第二极与第五节点N5电连接。第五节点N5通过第一电压信号端(ELVDD)与电源信号线电连接。
第二发光控制晶体管T7的控制极通过发光控制信号端(EM[n])与发光控制信号线电连接，第二发光控制晶体管T7的第一极与第二节点N2电连接，第二发光控制晶体管T7的第二极与第四节点N4电连接。
电容Cst的第一极板与第五节点N5电连接，电容Cst的第二极板与第三节点N3电连接。
再次参见图25，像素电路还包括发光二极管LED，第四节点N4与发光二极管LED的一端电连接，发光二极管LED的一端与第二电压信号端(ELVSS)电连接。
本公开实施例中的7T1C像素电路仅作为一种示例，在其他实现方式中，像素电路还可以为其他结构，例如，像素电路为2T1C像素电路。
图26是本公开实施提供的一种显示面板的制作方法的流程图。其中显示面板具有透光的第一显示区域，参见图26，制作方法包括：
在步骤S401中，提供一衬底基板。
其中，衬底基板具有显示区域和至少部分围绕所述显示区域的周边区域，显示区域包括第一显示区域和至少位于第一显示区域一侧的第二显示区域，第一显示区域的透光率大于第二显示区域的透光率。
在本公开实施例中，衬底基板可以为玻璃衬底或聚酰亚胺衬底。
在步骤S402中，在衬底基板上形成多个第一像素单元和多根信号线。
其中，多个第一像素单元位于第一显示区域；多根信号线至少位于第一显示区域且与多个第一像素单元电连接，多根信号线包括多根第一信号线和多根第二信号线，多根第一信号线中的每根第一信号线的第一部分为金属信号线，第一信号线的第一部分至少位于第一显示区域，多根第二信号线中的每根第二信号线的第一部分为金属氧化物信号线，第二信号线的第一部分至少位于第一显示区域。
示例性地，步骤S402可包括以下步骤：
图27是本公开实施提供的一种显示面板的制作方法的流程图。参见图27，该方法包括：
S421：在衬底基板的一侧形成有源层。
示例性地，有源层可以为多晶硅层。图28是本公开实施例提供的一种显示面板的制作方法的过程图。参见图28，可以通过蒸镀的方式在衬底基板的一侧形成有源薄膜，然后通过构图工艺对有源薄膜进行图形化处理，得到如图28所示的有源层206。值得说明的是，有源层206包括对应多个像素单元的有源图案，如图28所示，中部为一个完整的有源图案，四角分别为其他四个有源图案的部分。图29至图35与图28类似，均是中部为一个像素单元的图案，四角分别为其他像素单元的部分。其中图28至图35所示的显示面板位于第一显示区域内。
S422：在有源层远离衬底基板的一侧形成第二栅极绝缘层。
示例性地，第二栅极绝缘层可以为氮化硅层，可以通过蒸镀的方式在有源 层的一侧形成第二栅极绝缘层，第二栅极绝缘层覆盖有源层。
S423：在第二栅极绝缘层远离衬底基板的一侧形成第一栅极金属层。
图29是本公开实施例提供的一种显示面板的制作方法的过程图。参见图29，在第二栅极绝缘层上形成第一栅极金属层211。在第一显示区域中，第一栅极金属层包括电容的第二极板602和薄膜晶体管的控制极G以及栅极信号线Gate。
在本公开实施中，在第一显示区域和第二显示区域中栅极信号线Gate均位于第一栅极金属层中，在第二显示区域中，复位信号线和发光控制信号线的第一部分位于第一栅极金属层中。
示例性地，第一栅极金属层可以为金属钼层，可以通过溅射的方式在第一栅极绝缘层的一侧形成第一栅极金属薄膜，然后通过构图工艺对第一栅极金属薄膜进行图形化处理，得到第一栅极金属层。
S424：在第一栅极金属层远离衬底基板的一侧形成第一栅极绝缘层。
示例性地，第一栅极绝缘层可以为氮化硅层，可以通过蒸镀的方式在第二栅极金属层的一侧形成第一栅极绝缘层，第一栅极绝缘层覆盖第二栅极金属层。
S425：在第一栅极绝缘层远离衬底基板的一侧形成第二栅极金属层。
示例性地，第二栅极金属层可以为金属钼层。图30是本公开实施例提供的一种显示面板的制作方法的过程图。参见图30，可以通过溅射的方式在第一栅极绝缘层的一侧形成第二栅极金属薄膜，然后通过构图工艺对第二栅极金属薄膜进行图形化处理，得到第二栅极金属层251。在第一显示区域中，第二栅极金属层251包括电容的第一极板601。
S426：在第二栅极金属层远离衬底基板的一侧形成第一钝化层。
示例性地，第一钝化层可以为氮化硅层，可以通过蒸镀的方式在第二栅极金属层的一侧形成第一钝化层。
图31是本公开实施例提供的一种显示面板的制作方法的过程图。参见图31，在第一钝化层中形成第一过孔221。
示例性地，可以通过刻蚀的方式形成第一过孔221。
S427：在第一钝化层远离衬底基板的一侧形成第一源漏金属层。
图32是本公开实施例提供的一种显示面板的制作方法的过程图。参见图32，可以通过溅射的方式在第一钝化层的一侧形成第一源漏金属薄膜，然后通过构图工艺对第一源漏金属薄膜进行图形化处理，得到第一源漏金属层212。
在本公开实施例中，数据信号线Data位于第一源漏金属层中。
S428：在第一源漏金属层远离衬底基板的一侧形成层间介电层。
示例性地，层间介电层可以为氮化硅层，可以通过蒸镀的方式在金属氧化物层的一侧形成层间介电层。
S429：在层间介电层远离衬底基板的一侧形成金属氧化物层。
图33是本公开实施例提供的一种显示面板的制作方法的过程图。参见图33，可以通过溅射的方式在层间介电层的一侧形成金属氧化物薄膜，然后通过构图工艺对金属氧化物薄膜进行图形化处理，得到金属氧化物层203。
在本公开实施例中，在第一显示区域中，复位信号线Reset、发光控制信号线EM和初始电压信号线Vinit的第二部分均位于金属氧化物层203中，以及电源信号线VDD的第一部分位于金属氧化物层中。
其中，复位信号线的第一部分和第二部分通过第一过孔电连接，发光控制信号线的第一部分和第二部分通过第一过孔电连接，初始电压信号线的第一部分和第二部分通过第二过孔电连接。
S4210：在金属氧化物层远离衬底基板的一侧形成第二钝化层。
示例性地，第二钝化层可以为氮化硅层，可以通过蒸镀的方式在第一源漏金属层的一侧形成第一钝化层。
S4211：在第二钝化层远离衬底基板的一侧形成第二源漏金属层。
示例性地，第二源漏金属层可以为金属钛层。图34是本公开实施例提供的一种显示面板的制作方法的过程图。参见图34，可以通过溅射的方式在第二钝化层的一侧形成第二源漏金属薄膜，然后通过构图工艺对第二源漏金属薄膜进行图形化处理，得到第二源漏金属层209。在图34中，第二源漏金属层209将第一源漏金属层212遮挡。电源信号线的第二部分位于第二源漏金属层209中。
最后在第二源漏金属层上形成显示面板的其他膜层，例如平坦化层、像素界定层、发光层和封装层等，完成显示面板的制作。
示例性地，图35是本公开实施例提供的一种显示面板的制作方法的过程图。参见图35，在第二源漏金属层209上形成阳极层2012。
需要说明的是，为了将金属层和金属氧化物层的制作过程体现清楚，上述制作过程图中，将绝缘层的制作过程图省去了。
本公开实施例还提供了一种显示装置，显示装置包括供电组件，以及上述的显示面板，供电组件用于为显示面板供电。
在具体实施时，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
在本公开实施例的一种实现方式中，显示装置还包括光感传感器，光感传感器位于显示面板远离多个第一像素单元的一侧，且光感传感器在衬底基板的正投影与第一显示区域至少部分重叠。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示面板，其特征在于，所述显示面板包括：
    衬底基板，具有显示区域和至少部分围绕所述显示区域的周边区域，所述显示区域包括第一显示区域和至少位于所述第一显示区域一侧的第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率；
    多个第一像素单元，位于所述衬底基板上且位于所述第一显示区域；
    多根信号线，至少位于所述第一显示区域且与所述多个第一像素单元电连接；
    其中，所述多根信号线包括多根第一信号线和多根第二信号线，所述多根第一信号线中的每根第一信号线的第一部分为金属信号线，所述第一信号线的第一部分至少位于所述第一显示区域；所述多根第二信号线中的每根第二信号线的第一部分为金属氧化物信号线，所述第二信号线的第一部分至少位于所述第一显示区域。
  2. 根据权利要求1所述的显示面板，其特征在于，所述第一信号线包括以下信号线中的至少一种：栅极信号线、数据信号线、复位信号线、发光控制信号线、初始电压信号线和电源信号线。
  3. 根据权利要求2所述的显示面板，其特征在于，所述第一信号线包括栅极信号线和数据信号线。
  4. 根据权利要求1至3任一项所述的显示面板，其特征在于，所述第一信号线还包括位于所述第二显示区域的第二部分，所述第二信号线还包括位于所述第二显示区域的第二部分，所述第一信号线的第二部分和所述第二信号线的第二部分均为金属信号线。
  5. 根据权利要求4所述的显示面板，其特征在于，所述显示面板还包括沿远离所述衬底基板的方向依次位于所述衬底基板上的第一金属层、第一绝缘层以及金属氧化物层；
    所述第一信号线位于所述第一金属层；
    所述多根第二信号线中的至少一根第二信号线在所述第一显示区域内的第一部分位于所述金属氧化物层，在所述第二显示区域的第二部分位于所述第一金属层，所述第二信号线的第一部分和第二部分通过贯穿所述第一绝缘层的第一过孔连接，所述第一过孔在所述第一显示区域和所述第二显示区域的交界处。
  6. 根据权利要求5所述的显示面板，其特征在于，所述第一金属层包括第一栅极金属层和第一源漏金属层，所述第一绝缘层包括第一钝化层和层间介电层；
    沿远离所述衬底基板的方向，所述第一栅极金属层、所述层间介电层、所述第一源漏金属层和所述第一钝化层依次层叠。
  7. 根据权利要求5所述的显示面板，其特征在于，所述显示面板还包括第二绝缘层和第二金属层，沿远离所述衬底基板的方向，所述第二金属层、所述第二绝缘层、所述第一金属层、所述第一绝缘层和金属氧化物层依次层叠；
    所述多根第二信号线中的另一部分第二信号线在所述第一显示区域内的第一部分位于所述金属氧化物层，在所述第二显示区域的第二部分位于所述第二金属层内，所述第二信号线的第一部分和第二部分通过贯穿所述第一绝缘层和所述第二绝缘层的第二过孔连接，所述第二过孔在所述第一显示区域和所述第二显示区域的交界处。
  8. 根据权利要求7所述的显示面板，其特征在于，所述第二金属层包括第二栅极金属层，所述第二绝缘层包括第一栅极绝缘层。
  9. 根据权利要求1至3和权利要求5至8任一项所述的显示面板，其特征在于，所述第一显示区域的第一尺寸与所述第一显示区域的第二尺寸的比值大于2时，所述第一信号线为栅极信号线，所述第一显示区域的第一尺寸为所述第一显示区域在所述栅极信号线的延伸方向上的尺寸，所述第一显示区域的第二尺寸为所述第一显示区域在数据信号线的延伸方向上的尺寸。
  10. 根据权利要求1至3和权利要求5至8任一项所述的显示面板，其特征在于，所述第一显示区域的第一尺寸与所述第一显示区域的第二尺寸的比值小于0.5时，所述第一信号线为数据信号线，所述第一显示区域的第一尺寸为所述第一显示区域在栅极信号线延的伸方向上的第一尺寸，所述第一显示区域的第二尺寸为所述第一显示区域在所述数据信号线的延伸方向上的尺寸。
  11. 根据权利要求1至3和权利要求5至8任一项所述的显示面板，其特征在于，所述第一显示区域的第一尺寸与所述第一显示区域的第二尺寸的比值在0.5至2之间时，所述第一信号线包括栅极信号线和数据信号线，所述第一显示区域的第一尺寸为所述第一显示区域在栅极信号线的延伸方向上的尺寸，所述第一显示区域的第二尺寸为所述第一显示区域在所述数据信号线的延伸方向上 的尺寸。
  12. 根据权利要求1至3和权利要求5至8任一项所述的显示面板，其特征在于，所述显示面板还包括多个第二像素单元，所述多个第二像素单元位于所述第二显示区域，所述多个第一像素单元和所述多个第二像素单元排成多行像素单元，在一行像素单元的排列方向上，相邻两行像素单元中的像素单元相互错开；
    相邻两行像素单元中的像素单元通过一根栅极信号线相连。
  13. 根据权利要求12所述的显示面板，其特征在于，所述栅极信号线呈波浪线型，且所述栅极信号线的波峰和波谷分别连接相邻两行像素单元中的像素单元。
  14. 根据权利要求12所述的显示面板，其特征在于，所述数据信号线呈波浪线型，且所述数据信号线的波峰和波谷分别连接同一列像素单元中的相邻两个像素单元。
  15. 根据权利要求1至3和权利要求5至8任一项所述的显示面板，其特征在于，所述金属信号线包含钼信号线或包含钛信号线。
  16. 根据权利要求1至3和权利要求5至8任一项所述的显示面板，其特征在于，所述金属氧化物信号线为透明的金属氧化物信号线。
  17. 根据权利要求16所述的显示面板，其特征在于，所述金属氧化物信号线为氧化铟锡信号线。
  18. 一种显示面板的制作方法，其特征在于，所述制作方法包括：
    提供一衬底基板，所述衬底基板具有显示区域和至少部分围绕所述显示区域的周边区域，所述显示区域包括第一显示区域和至少位于所述第一显示区域一侧的第二显示区域，所述第一显示区域的透光率大于所述第二显示区域的透光率；
    在所述衬底基板上形成多个第一像素单元和多根信号线，所述多个第一像素单元位于所述第一显示区域；多根信号线至少位于所述第一显示区域且与所述多个第一像素单元电连接，所述多根信号线包括多根第一信号线和多根第二信号线，所述多根第一信号线中的每根第一信号线的第一部分为金属信号线，所述第一信号线的第一部分至少位于所述第一显示区域；所述多根第二信号线 中的每根第二信号线的第一部分为金属氧化物信号线，所述第二信号线的第一部分至少位于所述第一显示区域。
  19. 一种显示装置，其特征在于，所述显示装置包括供电组件，以及如权利要求1至17中任一项所述的显示面板，所述供电组件用于为所述显示面板供电。
  20. 根据权利要求19所述的显示装置，其特征在于，所述显示装置还包括光感传感器，所述光感传感器位于所述显示面板远离所述多个第一像素单元的一侧，且所述光感传感器在所述衬底基板的正投影与所述第一显示区域至少部分重叠。
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