WO2021184274A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021184274A1
WO2021184274A1 PCT/CN2020/080079 CN2020080079W WO2021184274A1 WO 2021184274 A1 WO2021184274 A1 WO 2021184274A1 CN 2020080079 W CN2020080079 W CN 2020080079W WO 2021184274 A1 WO2021184274 A1 WO 2021184274A1
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WO
WIPO (PCT)
Prior art keywords
scan
data
line
light
base substrate
Prior art date
Application number
PCT/CN2020/080079
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English (en)
French (fr)
Inventor
都蒙蒙
刘彪
王俊喜
杨益祥
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000297.5A priority Critical patent/CN115735184A/zh
Priority to PCT/CN2020/080079 priority patent/WO2021184274A1/zh
Priority to EP20925377.2A priority patent/EP4123430A4/en
Priority to US17/759,701 priority patent/US20230060341A1/en
Publication of WO2021184274A1 publication Critical patent/WO2021184274A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • Micro LED Micro Light Emitting Diode
  • other electroluminescent diodes have self-luminous, low energy consumption, etc.
  • the advantages are one of the hot spots in the application research field of electroluminescent display devices.
  • the base substrate includes a notch area, a display area, and a first non-display area, and the first non-display area is located between the notch area and the display area;
  • the first conductive layer is located on the base substrate
  • the target insulating layer is located between the first conductive layer and the base substrate;
  • the functional layer is located between the target insulating layer and the base substrate;
  • the display area includes a plurality of sub-pixels, a plurality of data lines, a plurality of scan lines, and a plurality of light-emitting control lines; wherein at least one of the plurality of sub-pixels includes: a connection through hole; wherein the connection through hole penetrates The target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connection via;
  • the first non-display area includes: at least one auxiliary via, a plurality of data transmission lines, a plurality of scanning transmission lines, and a plurality of light-emitting transmission lines: wherein at least one of the plurality of data lines is connected to the plurality of data transmission lines.
  • At least one of the plurality of scan lines is electrically connected to at least one of the plurality of scan transmission lines, and at least one of the plurality of light-emitting control lines is electrically connected to one of the plurality of light-emitting transmission lines At least one electrical connection;
  • At least two of the plurality of data transmission lines, the plurality of scanning transmission lines, and the plurality of light-emitting transmission lines form an auxiliary area surrounded by, and the auxiliary through hole is located in the auxiliary area , And the auxiliary through hole penetrates the target insulating layer and the auxiliary through hole is not filled with conductive material.
  • the display panel includes:
  • the first gate insulating layer is located between the semiconductor layer and the first conductive layer;
  • a third conductive layer located between the first gate insulating layer and the first conductive layer;
  • the second gate insulating layer is located between the third conductive layer and the first conductive layer;
  • a fourth conductive layer located between the second gate insulating layer and the first conductive layer
  • An interlayer dielectric layer located between the fourth conductive layer and the first conductive layer;
  • At least one of the plurality of sub-pixels includes: a first connection via, a second connection via, and a third connection via; wherein the first connection via penetrates the first gate insulating layer and the second The second gate insulation layer and the interlayer dielectric layer; the second connection via hole penetrates the second gate insulation layer and the interlayer dielectric layer; the third connection via hole penetrates the interlayer dielectric layer;
  • the first conductive layer is electrically connected to the semiconductor layer through the first connection via;
  • the first conductive layer is electrically connected to the third conductive layer through the second connection through hole;
  • the first conductive layer is electrically connected to the fourth conductive layer through the third connection through hole;
  • the auxiliary through hole is filled with insulating material.
  • the display panel further includes:
  • An interlayer insulating layer located on the side of the first conductive layer away from the base substrate;
  • the auxiliary via hole is filled with the material of the interlayer insulating layer.
  • the functional layer includes the semiconductor layer
  • the target insulating layer includes: the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer;
  • connection through hole includes the first connection through hole
  • the auxiliary via includes a first auxiliary via, the first auxiliary via penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer, and the first auxiliary via The material filled in the hole penetrates the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer.
  • the distribution density of the first auxiliary via holes is less than or substantially equal to the distribution density of the first connection via holes.
  • the orthographic projection of the first auxiliary via on the base substrate is related to the semiconductor layer, the third conductive layer, the fourth conductive layer, and the first The orthographic projection of a conductive layer on the base substrate does not overlap.
  • the functional layer includes the third conductive layer
  • the target insulating layer includes: the second gate insulating layer and the interlayer dielectric layer;
  • connection through hole includes the second connection through hole
  • the auxiliary via hole includes a second auxiliary via hole, the second auxiliary via hole penetrates the second gate insulating layer and the interlayer dielectric layer, and the material filled in the second auxiliary via hole penetrates the The second gate insulating layer and the interlayer dielectric layer.
  • the distribution density of the second auxiliary via holes is less than or substantially equal to the distribution density of the second connection via holes.
  • the orthographic projection of the second auxiliary via on the base substrate is in the same position as the third conductive layer, the fourth conductive layer, and the first conductive layer.
  • the orthographic projection of the base substrate does not overlap.
  • the functional layer includes the fourth conductive layer
  • the target insulating layer includes: the interlayer dielectric layer;
  • connection through hole includes the third connection through hole
  • the auxiliary via hole includes a third auxiliary via hole, the third auxiliary via hole penetrates the interlayer dielectric layer, and the material filled in the third auxiliary via hole penetrates the interlayer dielectric layer.
  • the distribution density of the third auxiliary via holes is less than or substantially equal to the distribution density of the third connection via holes.
  • the orthographic projection of the third auxiliary via on the base substrate and the orthographic projection of the fourth conductive layer and the first conductive layer on the base substrate Do not overlap.
  • the plurality of data transmission lines include a plurality of first data transmission lines; a first conductive layer includes the plurality of data lines and the plurality of first data transmission lines; the layer The inter-insulating layer has a plurality of first data through holes;
  • the display panel further includes:
  • the second conductive layer is located on the side of the interlayer insulating layer away from the base substrate and includes a plurality of first data connection portions;
  • At least one of the plurality of first data connection portions is electrically connected to at least one of the plurality of data lines and at least one of the plurality of first data transmission lines through the first data via hole, respectively.
  • the multiple data transmission lines include multiple second data transmission lines
  • the second conductive layer further includes: the plurality of second data transmission lines; the plurality of second data transmission lines are spaced apart from the first data connection part;
  • the interlayer insulating layer further includes: a plurality of second data vias
  • the plurality of data lines include a plurality of first data lines and a plurality of second data lines; wherein, one of the first data lines is electrically connected to one of the first data transmission lines through the first data connection part; one The second data line is electrically connected to one of the second data transmission lines through the second data via.
  • the third conductive layer includes the plurality of scan lines and the plurality of light-emitting control lines; wherein, the plurality of scan lines includes a plurality of first scan lines and a plurality of Second scan line;
  • the display area further includes a plurality of sub-pixels; wherein, one row of the sub-pixels corresponds to one first scan line and one second scan line; in every two adjacent rows of sub-pixels, the first row of sub-pixels corresponds to The second scan line is electrically connected to the first scan line corresponding to the second row of sub-pixels;
  • One row of the sub-pixels corresponds to one light-emitting control line; and the light-emitting control lines corresponding to two adjacent rows of sub-pixels are electrically connected.
  • the first conductive layer further includes: a plurality of first scan connection portions insulated from the data line and the first data transmission line and arranged at intervals; wherein, the q-th The second scan line corresponding to one row of sub-pixels and the first scan line corresponding to the q-th row of sub-pixels are electrically connected through at least one of the first scan connection portions; q is an integer;
  • the second insulating layer includes a plurality of first scanning through holes and a plurality of second scanning through holes;
  • the first end of the first scan connection portion is electrically connected to the corresponding first scan line through at least one of the plurality of first scan through holes, and the second end of the first scan connection portion passes through the At least one of the plurality of second scan through holes is electrically connected to the corresponding second scan line.
  • all rows of sub-pixels include a first-type row of sub-pixels; at least one row of sub-pixels in the first-type row of sub-pixels corresponds to at least one of the first data connection portions;
  • the orthographic projection of the first data connection portion on the base substrate and the first scan line do not overlap.
  • the first data connection portion is in the The orthographic projection of the base substrate is located between the first scan through hole corresponding to the first scan line and the second scan through hole corresponding to the second scan line between the orthographic projection of the base substrate.
  • the first scan line corresponding to the first scan line The line between the scanning through hole in the center of the orthographic projection of the base substrate and the second scanning through hole corresponding to the second scan line in the center of the orthographic projection of the base substrate and the first data
  • the connection part overlaps the orthographic projection of the base substrate.
  • the orthographic projection of the first data connection portion on the base substrate and the orthographic projection of the first scan line on the base substrate have an overlapping area, and the first data line and the The orthographic projection of the first data transmission line on the base substrate and the orthographic projection of the first scan line on the base substrate do not overlap.
  • the edge area of the first data connection portion is on the edge of the base substrate.
  • the orthographic projection and the orthographic projection of the first scan line on the base substrate have an overlapping area.
  • the central area of the first data connection portion is located on the base substrate.
  • the orthographic projection and the orthographic projection of the first scan line on the base substrate have an overlapping area.
  • some rows of sub-pixels in the first-type row of sub-pixels correspond to the two first data connection portions, and the first scan line, The second scan line and the two first data connection parts, the orthographic projection of the two first data connection parts on the base substrate and the first scan line on the front of the base substrate
  • the projection has an overlapping area, and the orthographic projection of the two first data connection parts on the base substrate and the orthographic projection of the second scan line on the base substrate do not overlap.
  • the first scan line for the first scan line, the second scan line, and the two first data connection portions corresponding to the same row of sub-pixels,
  • the orthographic projection of the first first data connection portion of the two first data connection portions on the base substrate is close to the first scan through hole corresponding to the first scan line on the front of the base substrate. Projection; and/or,
  • the orthographic projection of the second first data connection portion of the two first data connection portions on the base substrate is close to the second scan through hole corresponding to the second scan line on the front of the base substrate. projection.
  • the second conductive layer further includes: a plurality of second data connection parts; wherein one of the second data transmission lines is directly electrically connected to at least one of the second data connection parts, And the second data connection part is electrically connected to one of the second data lines through the second data through hole.
  • the first data line and the second data line are alternately arranged;
  • the projections of the first data connection portion and the second data connection portion on a straight line extending along the first direction are alternately arranged.
  • all rows of sub-pixels include second-type row sub-pixels; the second-type row sub-pixels are different from the first-type row sub-pixels;
  • At least one row of sub-pixels in the second-type row of sub-pixels corresponds to at least one of the second data connection parts
  • the second data connection portion For the first scan line and the second data connection portion corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected by the second data connection portion, the second data connection portion
  • the orthographic projection on the base substrate and the orthographic projection of the first scan line on the base substrate have an overlapping area, and the second data line and the second data transmission line are on the base substrate
  • the orthographic projection of and the orthographic projection of the first scan line on the base substrate do not overlap.
  • the row of sub-pixels further corresponds to one of the second data connection portions
  • the second data connection portion For the first scan line and the second data connection portion corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected by the second data connection portion, the second data connection portion
  • the orthographic projection on the base substrate and the orthographic projection of the first scan line on the base substrate have an overlapping area, and the second data line and the second data transmission line are on the base substrate
  • the orthographic projection of and the orthographic projection of the first scan line on the base substrate do not overlap.
  • the first conductive layer further includes: a plurality of first light-emitting connection parts insulated from the data line and the first data transmission line and arranged at intervals; wherein, they are electrically connected to each other
  • the light-emitting control line corresponds to at least one of the first light-emitting connection parts
  • the second insulating layer includes a plurality of first light-emitting through holes and a plurality of second light-emitting through holes;
  • the first end of the first light-emitting connection part is electrically connected to the corresponding one of the light-emitting control lines through at least one of the plurality of first light-emitting through holes, and the second end of the first light-emitting connection part passes through the At least one of the plurality of second light-emitting through holes is electrically connected to another corresponding light-emitting control line.
  • the plurality of scan transmission lines include: a plurality of first scan transmission lines and a plurality of second scan transmission lines, and the light-emitting transmission line includes a plurality of first light-emitting transmission lines and a plurality of second light-emitting transmission lines.
  • the third conductive layer further includes the plurality of first scan transmission lines and the plurality of first light-emitting transmission lines located in the first non-display area; wherein, the first scan transmission line and the first light-emitting transmission line Interval setting
  • Part of the first scan line and the second scan line that are electrically connected to each other are directly correspondingly electrically connected to one of the first scan transmission lines; and part of the light-emitting control lines that are electrically connected to each other are directly electrically connected to one of the first light-emitting transmission lines;
  • the fourth conductive layer further includes the plurality of second scan transmission lines and the plurality of second light-emitting transmission lines located in the first non-display area; wherein, the second scan transmission line and the second light-emitting transmission line Interval setting
  • the interlayer dielectric layer further includes a plurality of third scanning through holes and a plurality of third light emitting through holes;
  • the remaining parts of the first scan line and the second scan line that are electrically connected to each other correspond to a second scan transmission line, and the first scan connection part is also connected to the second scan via via the third scan via.
  • the remaining part of the light-emitting control line electrically connected to each other corresponds to the second light-emitting transmission line, and the first light-emitting connection portion is also electrically connected to the second light-emitting transmission line through the third light-emitting through hole.
  • the plurality of scan transmission lines include: a plurality of third scan transmission lines, and the light-emitting transmission line includes a plurality of third light-emitting transmission lines;
  • the fourth conductive layer includes a plurality of third scan transmission lines located in the first non-display area;
  • the interlayer dielectric layer includes a plurality of fourth scanning through holes
  • the first scan line and the second scan line that are electrically connected to each other correspond to the third scan transmission line, and the first scan connection portion is also electrically connected to the third scan transmission line through a fourth scan through hole. connect;
  • the third conductive layer further includes a third light-emitting transmission line located in the first non-display area; wherein the light-emitting control lines electrically connected to each other are directly electrically connected to one of the third light-emitting transmission lines.
  • the plurality of scan transmission lines include: a plurality of fourth scan transmission lines, and the light-emitting transmission line includes a plurality of fourth light-emitting transmission lines;
  • the fourth conductive layer includes a plurality of fourth light-emitting transmission lines located in the first non-display area;
  • the interlayer dielectric layer includes a plurality of fourth light-emitting through holes
  • the light-emitting control lines that are electrically connected to each other correspond to the fourth light-emitting transmission line, and the first light-emitting connection portion is also electrically connected to the fourth light-emitting transmission line through a fourth light-emitting through hole;
  • the third conductive layer further includes a fourth scan transmission line located in the first non-display area; wherein the first scan line and the second scan line that are electrically connected to each other are directly electrically connected to one of the fourth scan lines Transmission line.
  • the second data connection portion is located on the substrate
  • the orthographic projection of the base substrate is located between the second scan through hole corresponding to the second scan line and the first light-emitting through hole corresponding to the light-emitting control line between the orthographic projection of the base substrate.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of the structure of some display panels provided by the embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of a circuit structure in some sub-pixels provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a layout structure in some sub-pixels provided by an embodiment of the disclosure.
  • 4a is a schematic diagram of the layout structure of the semiconductor layers in some sub-pixels provided by the embodiments of the present disclosure
  • 4b is a schematic diagram of the layout structure of the third conductive layer in some sub-pixels provided by the embodiments of the present disclosure
  • 4c is a schematic diagram of the layout structure of the fourth conductive layer in some sub-pixels provided by the embodiments of the present disclosure.
  • 4d is a schematic diagram of the layout structure of the first conductive layer in some sub-pixels provided by the embodiments of the present disclosure
  • 4e is a schematic diagram of the layout structure of the second conductive layer in some sub-pixels provided by the embodiments of the present disclosure
  • Fig. 5 is a schematic cross-sectional structure view along the AA' direction in the schematic layout structure shown in Fig. 3;
  • FIG. 6 is a schematic diagram of the structure of still other display panels provided by the embodiments of the present disclosure.
  • FIG. 7a is a schematic diagram of the layout structure of partial areas of some display panels provided by the embodiments of the present disclosure.
  • FIG. 7b is a schematic diagram of the layout structure of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 8a is a schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 7a;
  • FIG. 8b is a schematic cross-sectional structure diagram along the BB' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 7a;
  • FIG. 8c is a schematic cross-sectional structure diagram along the BB' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 7b;
  • FIG. 9a is a schematic diagram of the layout structure of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 9b is a schematic diagram of the layout structure of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 10a is a schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 9a;
  • 10b is a schematic cross-sectional structure diagram along the BB' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 9a;
  • FIG. 10c is a schematic cross-sectional structure diagram along the BB' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 9b;
  • FIG. 11 is a schematic diagram of the layout structure of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 12 is a schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 11;
  • FIG. 13 is a schematic diagram of the layout structure of some other display panels provided by the embodiments of the present disclosure.
  • FIG. 14 is a schematic cross-sectional structure diagram along the AA' direction in the layout structure diagram of a partial area of the display panel shown in FIG. 13.
  • the full screen has a larger screen-to-body ratio and an ultra-narrow bezel. Compared with ordinary display screens, it can greatly improve the viewer's visual effect, and thus has received extensive attention.
  • a front camera, earpiece, etc. are usually set on the front of the display device.
  • the display panel is generally provided with a notch area A2 for setting the front camera, earpiece and other devices.
  • the scan line and the data line need to be routed according to the gap area A2, which causes a coupling effect between the scan line and the data line, which causes signal interference and affects the display effect.
  • the embodiments of the present disclosure provide a display panel, which can reduce the coupling effect between the scan line and the data line, reduce signal interference, and improve the display effect.
  • the display panel provided by the embodiment of the present disclosure may include: a base substrate 010.
  • the base substrate 010 may include a notch area A2, a display area A1, and a first non-display area A3.
  • the first non-display area A3 is located between the notch area A2 and the display area A1.
  • the base substrate 010 may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited herein.
  • the notch area A2 may be a hollow area of the base substrate 010.
  • the position of the base substrate 010 corresponding to the notch area A2 is cut into a hollow area to be used for setting cameras, earpieces and other devices in the display device.
  • the base substrate 010 may not be cut, but the lines on the base substrate 010 may be avoided, so that the position corresponding to the notch area A2 is a transparent area to form the notch area A2.
  • the display panel may generally also include a frame area surrounding the display area A1. Elements such as an electrostatic discharge circuit and a gate drive circuit can be arranged in the frame area.
  • the display panel may not be provided with a frame area, which can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • the display area A1 may further include a plurality of pixel units PX arranged in an array.
  • the pixel unit PX may include a plurality of sub-pixels spx.
  • the sub-pixels spx may be arranged in an array in the display area A1.
  • the sub-pixel spx may include: a pixel driving circuit 0121 and a light emitting device 0120.
  • the pixel driving circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the first light-emitting electrode of the light-emitting device 0120.
  • a corresponding voltage is applied to the second light-emitting electrode of the light-emitting device 0120 to drive the light-emitting device 0120 to emit light.
  • the pixel driving circuit 0121 may include: a driving control circuit 0122, a first light emission control circuit 0123, a second light emission control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129 .
  • the drive control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the driving control circuit 0122 is configured to provide the light emitting device 0120 with a driving current for driving the light emitting device 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the drive control circuit 0122 is configured to realize that the connection between the drive control circuit 0122 and the first voltage terminal VDD is turned on or off.
  • the second light emitting control circuit 0124 is electrically connected to the second end of the driving control circuit 0122 and the first light emitting electrode of the light emitting device 0120. And the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting device 0120 to be turned on or off.
  • the data writing circuit 0126 is electrically connected to the first end of the drive control circuit 0122.
  • the second light emission control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scan line GA2.
  • the storage circuit 0127 is electrically connected to the control terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals.
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the drive control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation for the drive control circuit 0122.
  • the reset circuit 0129 is electrically connected to the control terminal of the drive control circuit 0122 and the first light-emitting electrode of the light-emitting device 0120. And the reset circuit 0129 is configured to reset the control terminal of the drive control circuit 0122 and the first light-emitting electrode of the light-emitting device 0120 under the control of the signal on the gate line GA1.
  • the light-emitting device 0120 may include a first light-emitting electrode, a light-emitting functional layer, and a second light-emitting electrode that are stacked.
  • the first light-emitting electrode may be an anode
  • the second light-emitting electrode may be a cathode.
  • the light-emitting functional layer may include a light-emitting layer.
  • the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • the light emitting device 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited here.
  • the drive control circuit 0122 includes: a drive transistor T1, the control end of the drive control circuit 0122 includes the gate of the drive transistor T1, and the first end of the drive control circuit 0122 includes the first end of the drive transistor T1.
  • the second terminal of the driving control circuit 0122 includes the second terminal of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2.
  • the storage circuit 0127 includes a storage capacitor CST.
  • the threshold compensation circuit 0128 includes a threshold compensation transistor T3.
  • the first light emission control circuit 0123 includes a first light emission control transistor T4.
  • the second light emission control circuit 0124 includes a second light emission control transistor T5.
  • the reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.
  • the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1
  • the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal
  • the data writing transistor The gate of T2 is configured to be electrically connected to the second scan line GA2 to receive a scan signal.
  • the first electrode of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor T1.
  • the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1
  • the gate of the threshold compensation transistor T3 is configured to be connected to the second electrode.
  • the scan line GA2 is electrically connected to receive the compensation control signal.
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset signal line VINIT1 to receive the first reset signal
  • the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1
  • the first reset The gate of the transistor T6 is configured to be electrically connected to the first scan line GA1 to receive a control signal.
  • the first electrode of the second reset transistor T7 is configured to be electrically connected to the second reset signal line VINIT2 to receive the second reset signal
  • the second electrode of the second reset transistor T7 is electrically connected to the first light-emitting electrode of the light-emitting device 0120.
  • the gates of the two reset transistors T7 are configured to be electrically connected to the first scan line GA1 to receive control signals.
  • the first electrode of the first light emission control transistor T4 is electrically connected to the first power supply terminal VDD
  • the second electrode of the first light emission control transistor T4 is electrically connected to the first electrode of the drive transistor T1
  • the gate of the first light emission control transistor T4 is electrically connected to the first electrode of the driving transistor T1. It is configured to be electrically connected to the light emission control line EM to receive the light emission control signal.
  • the first electrode of the second light emission control transistor T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the second light emission control transistor T5 is electrically connected to the first light emitting electrode of the light emitting device 0120
  • the second electrode of the second light emission control transistor T5 is electrically connected to the first light emitting electrode of the light emitting device 0120.
  • the gate is configured to be electrically connected with the emission control line EM to receive the emission control signal.
  • the second light emitting electrode of the light emitting device 0120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the above-mentioned transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the pixel driving circuit in the sub-pixel spx may be a structure including other numbers of transistors in addition to the structure shown in FIG. limited.
  • FIG. 3 is a schematic diagram of a layout structure of a pixel driving circuit provided by some embodiments of the present disclosure.
  • 4a to 4e are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the disclosure. Among them, the examples shown in FIGS. 3 to 4e take a pixel driving circuit of a sub-pixel spx as an example.
  • 3 to 4e also show the first scan line GA1, the second scan line GA2, and the first reset signal line VINIT1 electrically connected to the pixel driving circuit 0121 (the first reset signal line VINIT1 and the second reset signal line VINIT2 is the same signal line, the first reset signal line VINIT1), the light-emitting control line EM, the data line VD, the first power signal line VDD1 and the second power signal line VDD2 that are electrically connected to the first power terminal VDD are shown .
  • the first power supply signal line VDD1 and the second power supply signal line VDD2 are electrically connected to each other.
  • the semiconductor layer 500 of the pixel driving circuit 0121 is shown.
  • the semiconductor layer 500 may be formed by patterning a semiconductor material.
  • the semiconductor layer 500 can be used to make the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7.
  • the source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layer of each transistor is integrated.
  • the semiconductor layer 500 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the semiconductor layer 500 may be patterned by a patterning process.
  • the unpatterned semiconductor layer 500 will remain in the first non-display area A3.
  • the semiconductor layer 500 in the first non-display area A3 and the display area A1 are spaced apart.
  • the present disclosure includes but is not limited to this.
  • a first gate insulating layer 610 (not shown) is formed on the aforementioned semiconductor layer 500 to protect the aforementioned semiconductor layer 500.
  • the third conductive layer 300 of the pixel driving circuit 0121 is shown.
  • the third conductive layer 300 is disposed on the first gate insulating layer 610 so as to be insulated from the semiconductor layer 500.
  • the third conductive layer 300 may include the second electrode CC2a of the storage capacitor CST, the first scan line GA1, the second scan line GA2, the emission control line EM, and the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first The gates of the light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7.
  • the gate of the data writing transistor T2 may be the part where the second scan line GA2 overlaps the semiconductor layer 500
  • the gate of the first light-emitting control transistor T4 may be the light-emitting control line EM
  • the gate of the second light emission control transistor T5 overlaps with the semiconductor layer 500 in the first part where the light emission control line EM overlaps with the semiconductor layer 500.
  • the gate of the first reset transistor T6 is the first scan line GA1 and The first part of the overlap of the semiconductor layer 500
  • the gate of the second reset transistor T7 is the second part where the first scan line GA1 overlaps the semiconductor layer 500
  • the threshold compensation transistor T3 may be a thin film transistor with a double gate structure
  • the threshold compensation transistor T3 The first gate of the second scan line GA2 may be the first part where the semiconductor layer 500 overlaps
  • the second gate of the threshold compensation transistor T3 may be a protrusion protruding from the second scan line GA2 that intersects the semiconductor layer 500 The second part of the stack.
  • the gate of the driving transistor T1 may be the second electrode CC2a of the storage capacitor CST.
  • each dashed rectangular frame in FIG. 4a shows each part where the third conductive layer 300 and the semiconductor layer 500 overlap in the sub-pixel spx.
  • the active layer of the threshold compensation transistor T3 has a first channel region that overlaps the first gate of the threshold compensation transistor T3 and a second channel that overlaps the second gate of the threshold compensation transistor T3. Region, and a source and drain region located between the first channel region and the second channel region. The source and drain regions are used to electrically connect the first channel region and the second channel region.
  • the first scan line GA1, the second scan line GA2, and the emission control line EM are arranged along the second direction F2.
  • the second scan line GA2 is located on the first scan line GA1 and the emission control line. Between lines EM.
  • the second pole CC2a of the storage capacitor CST is located between the second scan line GA2 and the emission control line EM.
  • the protrusion protruding from the second scan line GA2 is located on the side of the second scan line GA2 away from the light emission control line EM.
  • the gate of the data writing transistor T2 in the second direction F2, the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the second reset transistor
  • the gates of T7 are all located on the first side of the gate of the driving transistor T1
  • the gates of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the first direction F1.
  • a second gate insulating layer 620 (not shown) is formed on the aforementioned third conductive layer 300 for protecting the aforementioned third conductive layer 300.
  • the fourth conductive layer 400 of the pixel driving circuit 0121 is shown.
  • the fourth conductive layer 400 is disposed on the second gate insulating layer 620.
  • the fourth conductive layer 400 may include: the first pole CC1a of the storage capacitor CST, the first reset signal line VINIT1, and the light shielding part 344a.
  • the orthographic projection of the first pole CC1a of the storage capacitor CST on the base substrate 010 and the orthographic projection of the second pole CC2a of the storage capacitor CST on the base substrate 010 at least partially overlap to form the storage capacitor CST.
  • the orthographic projection of the light shielding portion 344a on the base substrate 010 and the source and drain regions in the active layer of the threshold compensation transistor T3 have an overlapped area on the orthographic projection of the base substrate 010.
  • an interlayer dielectric layer 630 (not shown) is formed on the above-mentioned fourth conductive layer 400 to protect the above-mentioned fourth conductive layer 400.
  • the first conductive layer 100 of the pixel driving circuit 0121 is shown, and the first conductive layer 100 is disposed on the interlayer dielectric layer 630.
  • the first conductive layer 100 may include: a data line VD, a first power signal line VDD1, and bridge portions 341a, 342a, and 343a.
  • an interlayer insulating layer 640 (not shown) is formed on the aforementioned first conductive layer 100 to protect the aforementioned first conductive layer 100.
  • the second conductive layer 200 of the pixel driving circuit 0121 is shown, and the second conductive layer 200 is disposed on the interlayer insulating layer 640.
  • the second conductive layer 200 includes a second power supply signal line VDD2 and a transfer portion 351a.
  • Fig. 5 is a schematic cross-sectional view of the layout structure shown in Fig. 3 along the AA' direction.
  • a first gate insulating layer 610 is provided between the semiconductor layer 500 and the third conductive layer 300
  • a second gate insulating layer 620 is provided between the third conductive layer 300 and the fourth conductive layer 400
  • the fourth conductive layer 400 is connected to the first
  • An interlayer dielectric layer 630 is provided between the conductive layers 100
  • an interlayer insulating layer 640 is provided between the first conductive layer 100 and the second conductive layer 200.
  • the sub-pixel spx includes a first connection through hole, a second connection through hole, a third connection through hole, and a fourth connection through hole; wherein, the first connection through hole penetrates the first gate insulation Layer 610, the second gate insulating layer 620 and the interlayer dielectric layer 630; the second connection via hole penetrates the second gate insulating layer 620 and the interlayer dielectric layer 630; the third connection via hole penetrates the interlayer dielectric layer 630; the fourth connection The through hole penetrates the interlayer insulating layer 640.
  • the sub-pixel spx may include first connection through holes 381a, 382a, 384a, 387a, and 388a.
  • the sub-pixel spx may include a second connection via 385a.
  • the sub-pixel spx may include third connection vias 386a, 3832a, and 389a.
  • the sub-pixel spx includes fourth connection through holes 385a and 3831a.
  • the data line VD is electrically connected to the source region of the data writing transistor T2 in the semiconductor layer 500 through at least one first connection via 381a.
  • the first power signal line VDD1 is electrically connected to the source region of the corresponding first light emission control transistor T4 in the semiconductor layer 500 through at least one first connection via 382a.
  • One end of the bridge portion 341a is electrically connected to the drain region of the corresponding threshold compensation transistor T3 in the semiconductor layer 500 through at least one first connection via 384a.
  • the other end of the bridge portion 341a is electrically connected to the gate of the driving transistor T1 in the third conductive layer 300 (ie, the second electrode CC2a of the storage capacitor CST) through at least one second connection via 385a.
  • One end of the bridge portion 342a is electrically connected to the first reset signal line VINIT1 through at least one third connection through hole 386a, and the other end of the bridge portion 342a is electrically connected to the second reset transistor T7 in the semiconductor layer 500 through at least one first connection through hole 387a.
  • the drain region is electrically connected.
  • the bridge portion 343a is electrically connected to the drain region of the second light emission control transistor T5 in the semiconductor layer 500 through at least one first connection via 388a.
  • the first power signal line VDD1 is electrically connected to the first pole CC1a of the storage capacitor CST in the fourth conductive layer 400 through at least one third connection via 3832a.
  • the first power signal line VDD1 is also electrically connected to the second power signal line VDD2 in the second conductive layer 200 through at least one fourth connection via 3831a.
  • the adapter portion 351a is electrically connected to the bridge portion 343a by penetrating at least one fourth connection through hole 385a.
  • the first power signal line VDD1 is also electrically connected to the light shielding portion 344a through at least one first connection through hole 389a to input a fixed voltage to the light shielding portion 344a.
  • the first connection through holes 381a, 382a, 384a, 387a, and 388a in the sub-pixels may be provided with one or two respectively.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the second connection via 385a in the sub-pixel may be provided with one, or two, and so on.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the third connection through holes 386a, 3832a, and 389a in the sub-pixels may be provided with one or two respectively.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • the fourth connection through holes 385a and 3831a in the sub-pixels may be provided with one or two respectively.
  • the design can be determined according to the requirements of the actual application environment, which is not limited here.
  • a planarization layer, a layer where the first light-emitting electrode is located, a pixel defining layer, a light-emitting function layer, and a layer where the second light-emitting electrode is located are sequentially provided.
  • the first light-emitting electrode is electrically connected to the via portion 351a through a via hole penetrating the planarization layer.
  • the first scan line GA1, the second scan line GA2, and the first reset signal line VINIT1 are all located on the first side of the gate of the driving transistor T1.
  • the emission control line EM is located on the second side of the driving transistor T1.
  • the first power supply signal line VDD1 and the second power supply signal line VDD2 are electrically connected, so that the signal line electrically connected to the first power supply terminal VDD has a lower resistance and a lower voltage drop. In turn, the stability of the power supply voltage provided by the first power supply terminal VDD can be improved.
  • the first scan line GA1, the second scan line GA2, and the emission control line EM may be located in the same layer (ie, the third conductive layer 300).
  • the first power signal line VDD1 and the data line VD are located in the same layer (ie, the first conductive layer 100).
  • each sub-pixel spx is not limited to the examples shown in FIGS. 3 to 4e, and the positions of the above-mentioned transistors can be specifically set according to actual application requirements.
  • first direction F1 may be the row direction of the sub-pixels
  • second direction F2 may be the column direction of the sub-pixels
  • first direction F1 may also be the column direction of the sub-pixels
  • second direction F2 may be the row direction of the sub-pixels. In actual applications, it can be set according to actual application requirements, which is not limited here.
  • the display area may include multiple data lines, multiple scan lines, and multiple light-emitting control lines.
  • the first non-display area may include a plurality of data transmission lines, a plurality of scan transmission lines, and a plurality of light-emitting transmission lines: wherein at least one of the plurality of data lines is electrically connected to at least one of the plurality of data transmission lines, and At least one is electrically connected to at least one of the plurality of scanning transmission lines, and at least one of the plurality of light-emitting control lines is electrically connected to at least one of the plurality of light-emitting transmission lines.
  • the plurality of data lines in the first conductive layer 100 may include a data line VD1 and a data line VD2.
  • the data lines VD1 and VD2 are both located in the display area A1, and the data lines VD1 and VD2 are respectively arranged along the first direction F1.
  • the data lines VD1 extend from the lower side of the display area A1 to the upper side of the display area A1 along the second direction F2 and are arranged along the first direction F1.
  • the data line VD2 extends along the second direction F2 and is divided by the notch area A2, that is, the data line VD2 can extend from the lower side of the display area A1 to the first non-display area A3, or from the upper side of the display area A1 Extend to the first non-display area A3.
  • the first conductive layer 100 may further include: a plurality of first data transmission lines 711 arranged at intervals.
  • the second conductive layer 200 may further include a plurality of first data connection parts 211 arranged at intervals.
  • the interlayer insulating layer 640 has a plurality of first data via holes.
  • at least one of the plurality of first data connection portions 211 is electrically connected to at least one of the plurality of data lines VD2 and at least one of the plurality of first data transmission lines 711 through the first data vias, respectively.
  • the data line in the first conductive layer 100 and the first data transmission line 711 can be electrically connected to each other through the first data connection portion 211 in the second conductive layer 200.
  • the data lines VD2 corresponding to the sub-pixels spx in the same column and divided by the notch area A2 may be electrically connected to each other through the first data transmission line 711 to form a data line for inputting data signals of the sub-pixels spx in the column.
  • the first data connection portion 211 is disposed in the second conductive layer 200, so that the data line VD2 and the first data transmission line 711 in the first conductive layer 100 can pass through the second conductive layer.
  • the first data connection parts 211 in the layer 200 are electrically connected to each other. In this way, not only the data lines VD2 corresponding to the same column of sub-pixels spx and divided by the notch area A2 can be electrically connected, but also the interference of the first data connection portion 211 to the third conductive layer 300 and the fourth conductive layer 400 can be reduced. , Which can improve the signal stability and improve the display effect.
  • the first conductive layer 100 since there are many bridge portions in the first conductive layer 100, if the first data connection portion 211 is also provided in the first conductive layer 100, then the first conductive layer 100 is used to provide bridge portions, data lines, and The area of the first power signal line will be reduced, which may cause short circuits in the bridge portion, the data line, the first power signal line, and the first data connection portion 211. Therefore, the above-mentioned display panel provided by the embodiments of the present disclosure can also reduce the risk of short circuit, further improve the stability of the display panel, and increase the competitiveness of the display panel.
  • a plurality of first data transmission lines 711 are located in the first non-display area A3.
  • the plurality of first data transmission lines 711 may be arranged in an arc around the gap area A2.
  • the interlayer insulating layer 640 may have a plurality of first data vias 641-1 and a plurality of first data vias 641-2.
  • one first data connection portion 211 corresponds to at least one first data via 641-1 and at least one first data via 641-2.
  • first data connection portion 211 may be electrically connected to the data line VD2 through the corresponding first data through hole 641-1, and the other end of the first data connection portion 211 may be through the corresponding first data through hole 641-2. It is electrically connected to the first data transmission line 711.
  • one first data connection portion 211 may correspond to one, two, three or more first data vias 641-1. It is also possible to make one first data connection part 211 correspond to one, two, three or more first data vias 641-2. These can be designed and determined according to actual application requirements, and are not limited here.
  • the plurality of data lines VD2 may include a plurality of first data lines 121 and a plurality of second data lines 122.
  • the first data lines 121 and the second data lines 122 may be alternately arranged.
  • an odd number of the plurality of data lines VD2 may be used as the first data line 121
  • an even number of the plurality of data lines VD2 may be used as the second data line 122.
  • the first data line 121 and the second data line 122 can also be designed and determined according to the requirements of the actual application environment, which is not limited here.
  • one first data line 121 may be electrically connected to one first data transmission line 711 through the first data connection portion 211.
  • one first data line 121 may correspond to one first data connection part 211 and one first data transmission line 711.
  • the first data line 121 can be electrically connected to the corresponding first data transmission line 711 through the corresponding first data connection portion 211, so as to realize the first data line 121 corresponding to the same column of sub-pixels spx and divided by the notch area A2.
  • the electrical connection with the first data transmission line 711 can be achieved through the corresponding first data connection part 211.
  • the second conductive layer 200 may further include: a plurality of second data transmission lines 712 arranged at intervals from the first data connection portion 211;
  • the insulating layer 640 may further include a plurality of second data via holes 642.
  • a second data line 122 is electrically connected to a second data transmission line 712 through a second data via 642.
  • one second data line 122 can correspond to one second data transmission line 712
  • one second data transmission line 712 corresponds to at least one second data via 642, so that the second data line 122 can pass through the corresponding second data
  • the through hole 642 is electrically connected to the transmission line corresponding to the second data line 122.
  • one second data transmission line 712 may correspond to one, two, three or more second data vias 642. These can be designed and determined according to actual application requirements, and are not limited here.
  • a plurality of second data transmission lines 712 are located in the first non-display area A3.
  • a plurality of second data transmission lines 712 may be arranged around the gap area A2 in an arc shape.
  • the orthographic projection of the second data transmission line 712 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may be arranged at intervals.
  • the orthographic projection of the first data transmission line 711 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may be alternately arranged.
  • the distance between the first data transmission line 711 and the second data transmission line 712 can be increased, and the distance between the first data transmission line 711 and the second data transmission line 712 can be further reduced. Signal interference between.
  • the orthographic projection of one second data transmission line 712 on the base substrate 010 and the orthographic projection of one first data transmission line 711 on the base substrate 010 may also have an overlapping area. Further, the orthographic projection of a second data transmission line 712 on the base substrate 010 and the orthographic projection of a first data transmission line 711 on the base substrate 010 may overlap, so that the first data transmission line 711 and the first data transmission line 711 and the first data transmission line 711 can be minimized.
  • the occupied area of the second data transmission line 712 further reduces the occupied area of the first non-display area A3.
  • the multiple scan lines may include multiple first scan lines GA1 and multiple second scan lines GA2 located in the display area A1, that is, the first scan lines GA2.
  • the three conductive layer 300 may include a plurality of first scan lines GA1 and a plurality of second scan lines GA2 located in the display area A1; wherein, one row of sub-pixels spx corresponds to one first scan line GA1 and one second scan line GA2.
  • FIGS. 7a and 7b show four rows of sub-pixels spx arranged along the second direction F2. In the direction opposite to the arrow in the second direction F2, there may be a q-1th row of sub-pixels G(q-1).
  • the corresponding second scan line GA2 is electrically connected to the first scan line GA1 corresponding to the q-th row sub-pixel G(q), and the second scan line GA2 corresponding to the q-th row sub-pixel G(q) is connected to the q+1
  • the first scan line GA1 corresponding to the row sub-pixel G(q+1) is electrically connected.
  • the rest is the same, and so on, so I won’t repeat them here.
  • q is an integer
  • FIGS. 7a and 7b only show part of the rows of sub-pixels spx in the display panel.
  • the first conductive layer 100 may further include: a plurality of first scan connections insulated from the data line and the first data transmission line 711 and arranged at intervals Section 131; wherein the second scan line GA2 corresponding to the q-1 row sub-pixel G(q-1) and the first scan line GA1 corresponding to the q-th row sub-pixel G(q) pass through at least one first scan connection portion 131 electrical connection.
  • the second insulating layer may further include a plurality of first scan through holes 811 and a plurality of second scan through holes 812; wherein, the first end of the first scan connection portion 131 passes through the plurality of first scan through holes 811 At least one is electrically connected to the corresponding first scan line GA1, and the second end of the first scan connection portion 131 is electrically connected to the corresponding second scan line GA2 through at least one of the plurality of second scan through holes 812.
  • the first scan line GA1 and the second scan line GA2 that are electrically connected to each other may correspond to one first scan connection portion 131.
  • One first scanning connection portion 131 may correspond to at least one first scanning through hole 811 and at least one second scanning through hole 812.
  • one first scanning connection portion 131 may correspond to one first scanning through hole 811 and one second scanning through hole 812.
  • the second scan line GA2 corresponding to the q-1th row sub-pixel G(q-1) is electrically connected to the first scan line GA1 corresponding to the qth row sub-pixel G(q), and the electrically connected second scan line GA2 is connected to
  • the first scan line GA1 corresponds to a first scan connection portion 131, and the first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through the corresponding first scan through hole 811, and the first scan connection The second end of the portion 131 is electrically connected to the corresponding second scan line GA2 through the corresponding second scan through hole 812.
  • the second scan line GA2 corresponding to the qth row sub-pixel G(q) is electrically connected to the first scan line GA1 corresponding to the q+1th row sub-pixel G(q+1), and the electrically connected second scan line GA2 is
  • the first scan line GA1 corresponds to a first scan connection portion 131, and the first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through the corresponding first scan through hole 811, and the first scan connection The second end of the portion 131 is electrically connected to the corresponding second scan line GA2 through the corresponding second scan through hole 812.
  • the second insulating layer may include: a second gate insulating layer 620 and an interlayer dielectric layer 630.
  • all rows of sub-pixels spx may include the first type of row sub-pixels spx. At least one row of sub-pixels spx in the first-type row of sub-pixels spx corresponds to at least one first data connection part 211.
  • the row sub-pixels spx of the first type may include a part of the rows of all the row sub-pixels spx.
  • each row of sub-pixels spx in the first-type row of sub-pixels spx may correspond to at least one first data connection part 211.
  • each row in the partial rows of sub-pixels spx in the first-type row sub-pixels spx corresponds to one first data connection portion 211, and each row in the remaining rows of sub-pixels spx corresponds to two first data connection portions.
  • the first type of row sub-pixels spx may include the q-th row of sub-pixels G(q) shown in FIGS. 7a and 7b.
  • the first scan line GA1, the second scan line GA2, and the first data connection portion 211 corresponding to the same row of sub-pixels spx the first The orthographic projection of the data connection portion 211 on the base substrate 010 does not cross the orthographic projection of the first scan connection portion 131 corresponding to the first scan line GA1 and the first scan connection portion 131 corresponding to the second scan line GA2 on the base substrate 010. Stacked. In this way, the first data connection portion 211 and the first scan connection portion 131 can be spaced apart, reducing the risk of short circuit.
  • the first The orthographic projection of the data connection portion 211 on the base substrate 010 is located between the first scan through hole 811 corresponding to the first scan line GA1 and the second scan through hole 812 corresponding to the second scan line GA2 between the orthographic projection of the base substrate 010 .
  • the first scan through hole 811 corresponding to the first scan line GA1 is on the base substrate 010
  • the line between the center of the orthographic projection and the second scan through hole 812 corresponding to the second scan line GA2 in the center of the orthographic projection of the base substrate intersects the orthographic projection of the first data connection portion 211 on the base substrate 010 Stacked.
  • the center of the above-mentioned orthographic projection may be the geometric center of the orthographic projection.
  • the shape of each of the above-mentioned structures formed generally has a certain deviation from the regular shape of the above-mentioned design.
  • the shape of the above-mentioned structure actually manufactured may have other changes from the designed shape. Therefore, in the embodiment of the present disclosure, the center of the above-mentioned orthographic projection may have a certain offset from the geometric center of the above-mentioned orthographic projection.
  • the second conductive layer 200 may further include: a plurality of second data connection portions 212; wherein, one second data transmission line 712 is directly electrically connected There is at least one second data connection portion 212, and the second data connection portion 212 is electrically connected to one second data line 122 through the second data via 642.
  • one second data line 122 corresponds to one second data transmission line 712 and one second data connection portion 212
  • one second data connection portion 212 corresponds to at least one second data via 642.
  • the second data connection portion 212 is directly electrically connected to the corresponding second data transmission line 712, and the second data connection portion 212 is electrically connected to the corresponding second data line 122 through the corresponding second data via 642.
  • one second data connection portion 212 may correspond to one, two, three or more second data vias 642. These can be designed and determined according to actual application requirements, and are not limited here.
  • the projections of the first data connection portion 211 and the second data connection portion 212 on a straight line extending along the first direction F1 can be arranged alternately . Since the first data line 121 and the second data line 122 are alternately arranged along the first direction F1, by alternately arranging the projections of the first data connection portion 211 and the second data connection portion 212 on a straight line extending along the first direction F1, In this way, the first data connection portion 211 electrically connected to the first data line 121 and the second data connection portion 212 electrically connected to the second data line 122 can be arranged correspondingly, thereby reducing signal interference.
  • the orthographic projection of the first data connection portion 211 and the second data connection portion 212 on the base substrate 010 can be connected to the first scan respectively.
  • the orthographic projections of the portion 131, the first scan line GA1, the second scan line GA2, and the light emission control line EM on the base substrate 010 do not overlap.
  • the light-emitting control lines corresponding to two adjacent rows of sub-pixels spx may be electrically connected.
  • the sub-pixel G(q-1) in the q-1th row is electrically connected to the emission control line corresponding to the sub-pixel in the q-2th row, and the sub-pixel G(q) in the qth row and the sub-pixel in the q+1th row are electrically connected.
  • the light-emitting control line corresponding to G(q+1) is electrically connected, and the sub-pixel G(q+2) in the q+2th row is electrically connected to the light-emitting control line corresponding to the q+3th row of sub-pixels.
  • the rest is the same, and so on, so I won’t repeat them here.
  • the first conductive layer 100 may further include: a plurality of first conductive layers insulated from the data line and the first data transmission line 711 and arranged at intervals A light-emitting connection portion 141; wherein the light-emitting control lines electrically connected to each other correspond to at least one first light-emitting connection portion 141.
  • the second insulating layer may include a plurality of first light emitting via holes 821 and a plurality of second light emitting via holes 822.
  • the first end of the first light-emitting connection portion 141 is electrically connected to a corresponding light-emitting control line through at least one of the plurality of first light-emitting through holes 821, and the second end of the first light-emitting connection portion 141 is electrically connected through a plurality of second light-emitting through holes 821. At least one of the light-emitting through holes 822 is electrically connected to another corresponding light-emitting control line.
  • the light-emitting control lines electrically connected to each other may correspond to one first light-emitting connection portion 141, and one first light-emitting connection portion 141 corresponds to at least one first light-emitting through hole 821 and at least one second light-emitting through hole 822.
  • the first end of the first light-emitting connection portion 141 is electrically connected to the corresponding light-emitting control line through the corresponding first light-emitting through hole 821
  • the second end of the first light-emitting connection portion 141 is electrically connected to the corresponding light-emitting control line through the corresponding second light-emitting through hole 822.
  • the other corresponding light-emitting control line is electrically connected.
  • first end of the first light-emitting connection portion 141 is electrically connected to the light-emission control line corresponding to the q-th row sub-pixel G(q) through the corresponding first light-emitting through hole 821, and the second end of the first light-emitting connection portion 141
  • the corresponding second light-emitting through hole 822 is electrically connected to the light-emitting control line corresponding to the sub-pixel G(q+1) in the q+1th row.
  • one first light-emitting connection part 141 may correspond to one, two, three or more first light-emitting through holes 821.
  • One first light-emitting connection part 141 may correspond to one, two, three or more second light-emitting through holes 822. These can be designed and determined according to actual application requirements, and are not limited here.
  • the third conductive layer 300 may further include a plurality of first scan transmission lines 311 and a plurality of first light emitting lines located in the first non-display area A3. Transmission line 321; wherein, the first scanning transmission line 311 and the first light-emitting transmission line 321 are spaced apart.
  • the orthographic projection of the first scanning transmission line 311 on the base substrate 010 and the orthographic projection of the first light-emitting transmission line 321 on the base substrate 010 may be arranged at intervals.
  • the orthographic projection of the first scanning transmission line 311 on the base substrate 010 and the orthographic projection of the first light-emitting transmission line 321 on the base substrate 010 may be alternately arranged. Further, the first scanning transmission line 311 and the first light-emitting transmission line 321 may be arranged in an arc around the first non-display area A3. Of course, these can be designed and determined according to actual application requirements, and are not limited here.
  • the first scan line GA1 and the second scan line GA2 that are partially electrically connected to each other directly correspond to and electrically connect a first scan transmission line 311; and partially The light-emitting control lines that are electrically connected to each other are directly electrically connected to a first light-emitting transmission line 321.
  • the first scan line GA1 in the third conductive layer 300 can be directly electrically connected to the first scan transmission line 311, and the light-emitting control line can be directly electrically connected to the first light-emitting transmission line 321, so that the design difficulty of these signal lines can be reduced.
  • the fourth conductive layer 400 may further include a plurality of second scan transmission lines 411 and a plurality of second light emitting lines located in the first non-display area A3. Transmission line 421; wherein, the second scanning transmission line 411 and the second light-emitting transmission line 421 are spaced apart.
  • the orthographic projection of the second scanning transmission line 411 on the base substrate 010 and the orthographic projection of the second light-emitting transmission line 421 on the base substrate 010 may be arranged at intervals.
  • the orthographic projection of the second scanning transmission line 411 on the base substrate 010 and the orthographic projection of the second light-emitting transmission line 421 on the base substrate 010 can be alternately arranged.
  • the second scanning transmission line 411 and the second light-emitting transmission line 421 may be arranged in an arc around the first non-display area A3.
  • these can be designed and determined according to actual application requirements, and are not limited here.
  • the interlayer dielectric layer 630 may further include a plurality of third scanning through holes 813 and a plurality of third light emitting through holes 823. Except for the first scan line GA1 and the second scan line GA2 that are electrically connected to each other as described above, the remaining first scan line GA1 and the second scan line GA2 that are electrically connected to each other correspond to a second scan transmission line 411, and the remaining portion The first scan connection portion 131 corresponding to the first scan line GA1 that is electrically connected to each other is also electrically connected to the second scan transmission line 411 through the third scan through hole 813.
  • the first scan line GA1 corresponding to the same row of sub-pixels spx and divided by the notch area A2 can be electrically connected through the second scan transmission line 411.
  • one second scan transmission line 411 may correspond to one, two, three or more third scan through holes 813. These can be designed and determined according to actual application requirements, and are not limited here.
  • the remaining parts of the light-emitting control lines that are electrically connected to each other correspond to a second light-emitting transmission line 421.
  • the first light-emitting connection portion 141 is also electrically connected to the second light-emitting transmission line 421 through the third light-emitting through hole 823.
  • the light-emitting control lines corresponding to the sub-pixels spx in the same row and divided by the notch area A2 can be electrically connected through the second light-emitting transmission line 421.
  • one second light-emitting transmission line 421 may correspond to one, two, three or more third light-emitting through holes 823. These can be designed and determined according to actual application requirements, and are not limited here.
  • first scanning transmission line 311, the second scanning transmission line 411, the first light-emitting transmission line 321, and the second light-emitting transmission line 421 are all arranged in the first non-display area A3.
  • first scan transmission line 311 and the first light-emitting transmission line 321 are arranged on the third conductive layer 300, and the second scan transmission line 411 and the second light-emitting transmission line 421 are arranged on the fourth conductive layer 400, so that the first scan transmission line 311,
  • the signals of the second scanning transmission line 411, the first light-emitting transmission line 321, and the second light-emitting transmission line 421 interfere with each other.
  • the orthographic projection of the first scan transmission line 311 on the base substrate 010 and the orthographic projection of part of the first data transmission line 711 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of a first scanning transmission line 311 on the base substrate 010 may overlap with the orthographic projection of a first data transmission line 711 on the base substrate 010. Exemplarily, the orthographic projection of the first light-emitting transmission line 321 on the base substrate 010 and the orthographic projection of the remaining part of the first data transmission line 711 on the base substrate 010 may have an overlapping area.
  • the orthographic projection of one first light-emitting transmission line 321 on the base substrate 010 may overlap with the orthographic projection of one first data transmission line 711 in the remaining part on the base substrate 010. In this way, the occupied area of the first non-display area can be reduced.
  • the orthographic projection of the second scan transmission line 411 on the base substrate 010 and the orthographic projection of part of the second data transmission line 712 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of a second scanning transmission line 411 on the base substrate 010 and the orthographic projection of a second data transmission line 712 on the base substrate 010 may overlap. Exemplarily, the orthographic projection of the second light-emitting transmission line 421 on the base substrate 010 and the orthographic projection of the remaining part of the second data transmission line 712 on the base substrate 010 may have an overlapping area.
  • the orthographic projection of one second light-emitting transmission line 421 on the base substrate 010 may overlap with the orthographic projection of one second data transmission line 712 in the remaining part on the base substrate 010. In this way, the occupied area of the first non-display area can be reduced.
  • all rows of sub-pixels spx may also include second-type row sub-pixels spx; the second-type row sub-pixels spx and the first type row sub-pixels
  • the pixel spx is different.
  • at least one row of sub-pixels spx in the second-type row of sub-pixels spx corresponds to at least one second data connection portion 212.
  • each row of sub-pixels spx in the second-type row of sub-pixels spx corresponds to at least one second data connection portion 212.
  • each row of sub-pixels spx in the second-type row of sub-pixels spx corresponds to one second data connection portion 212.
  • the row sub-pixels spx of the second type may be part of the rows in the display panel, and the specific positions thereof may be designed and determined according to the requirements of the actual application environment, and are not limited here.
  • the second row of sub-pixels spx may include the first row of sub-pixels and the third row of sub-pixels in FIG. 7b.
  • the second The orthographic projection of the data connection portion 212 on the base substrate 010 does not cross the orthographic projection of the first scan connection portion 131 corresponding to the first scan line GA1 and the first scan connection portion 131 corresponding to the second scan line GA2 on the base substrate 010. Stacked. In this way, the second data connection portion 212 and the first scan connection portion 131 can be spaced apart to reduce the risk of short circuit.
  • the second The orthographic projection of the data connection portion 212 on the base substrate 010 is located between the first scan through hole 811 corresponding to the first scan line GA1 and the second scan through hole 812 corresponding to the second scan line GA2 in the orthographic projection of the base substrate 010 .
  • the second scan through hole 812 corresponding to the first scan line GA1 is formed on the base substrate 010
  • the line between the center of the orthographic projection and the second scan through hole 812 corresponding to the second scan line GA2 in the center of the orthographic projection of the base substrate intersects with the orthographic projection of the second data connection portion 212 on the base substrate 010 Stacked.
  • the orthographic projection of the second data connection portion 212 on the base substrate 010 is opposite to the orthographic projection of the first light-emitting connection portion 141 on the base substrate 010.
  • the projection, the orthographic projection of the first scan connection portion 131 on the base substrate 010, the orthographic projection of the first scan line GA1 on the base substrate 010, and the orthographic projection of the second scan line GA2 on the base substrate 010 do not overlap.
  • the second data connection portion 212 corresponding to the same row of sub-pixels spx
  • the second data The orthographic projection of the connecting portion 212 on the base substrate 010 is located between the second scan through hole 812 corresponding to the second scan line GA2 and the first light-emitting through hole 821 corresponding to the light-emitting control line in the orthographic projection of the base substrate 010.
  • the transistors in the sub-pixel spx generally need to be electrically connected, and the electrical connections of these transistors are related to their transistor characteristics. Therefore, the electrical connections of the transistors are uniform, which can make the characteristics of the transistors uniform.
  • a wet etching method is used to prepare through holes for electrical connection through an etching solution.
  • the through hole of the sub-pixel spx at the edge of the display area A1 is etched, the through hole is not etched outside the edge of the display area A1, so that the etching degree of the through hole of the sub-pixel spx at the edge of the display area A1 is the same as the sub-pixel inside the display area A1.
  • the etching degree of the through hole of the pixel spx is different, which causes the characteristics of the transistor in the edge sub-pixel spx of the display area A1 and the transistor in the inner sub-pixel spx to be uneven.
  • the display panel and the target insulating layer between the first conductive layer and the base substrate are located between the target insulating layer and the base substrate.
  • at least one of the plurality of sub-pixels may include: a connection through hole; wherein the connection through hole penetrates the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connection through hole.
  • the first non-display area includes at least one auxiliary via hole: wherein the auxiliary via hole penetrates the target insulating layer and the auxiliary via hole is not filled with conductive material.
  • the auxiliary via hole penetrates the target insulating layer and the auxiliary via hole is not filled with conductive material.
  • at least two of the plurality of data transmission lines, the plurality of scanning transmission lines, and the plurality of light-emitting transmission lines are surrounded to form an auxiliary area, and the auxiliary through holes are located in the auxiliary area.
  • the distance between two adjacent auxiliary through holes can also be made smaller than or substantially equal to the distance between two adjacent connecting through holes.
  • the first connection through hole is used to realize the electrical connection of the transistors in the sub-pixel spx, and the electrical connection of these transistors is related to their transistor characteristics. Therefore, the electrical connection of the transistors is uniform, which can make the characteristics of the transistors uniform.
  • a wet etching method is used to prepare the first connection through hole through an etching solution.
  • the first connection via hole of the sub-pixel spx at the edge of the display area A1 is etched, the first connection via hole outside the edge of the display area A1 does not need to be etched, so that the first connection via hole of the sub-pixel spx at the edge of the display area A1
  • the etching degree is different from the etching degree of the first connection through hole of the sub-pixel spx in the display area A1, resulting in uneven characteristics of the transistors in the edge sub-pixel spx of the display area A1 and the transistors in the inner sub-pixel spx.
  • the functional layer may include a semiconductor layer;
  • the target insulating layer may include: a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer;
  • the connection via may include a first connection via;
  • the auxiliary via may include a first auxiliary via, and the first auxiliary via penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer.
  • the display panel may further include at least one first auxiliary through hole 911 located in the first non-display area A3.
  • the first auxiliary via 911 penetrates the first gate insulating layer 610, the second gate insulating layer 620, and the interlayer dielectric layer 630, and the first auxiliary via 911 is not filled with conductive material. Also, in the first non-display area A3, at least two of the multiple data transmission lines, the multiple scan transmission lines, and the multiple light-emitting transmission lines may surround the auxiliary area FB, and the first auxiliary via 911 may be located in the auxiliary area FB. In this way, the first auxiliary via 911 can be provided outside the edge of the display area A1, that is, in the first non-display area A3, and the first auxiliary via 911 and the first connecting via 911 penetrate the same insulating layer.
  • the first auxiliary via 911 is also etched in the first non-display area A3, so that the first connection via etched in the display edge sub-pixel spx can be connected to the first connection via etched in the inner sub-pixel spx.
  • the etching effect of the hole is uniform, and the characteristic uniformity of the transistor is improved.
  • the first auxiliary through hole 911 may be filled with an insulating material.
  • the material of the interlayer insulating layer 640 may be filled in the first auxiliary via hole 911. In this way, when the interlayer insulating layer 640 is prepared, the first auxiliary via hole 911 can be directly filled, so that the flatness of the interlayer insulating layer 640 can be improved.
  • auxiliary area FB In specific implementation, which transmission lines are used to form the auxiliary area FB can be determined by design according to actual application requirements, which is not limited here.
  • the semiconductor layer in the first non-display area A3 is not etched away when the semiconductor layer is patterned, the semiconductor layer remains in the first non-display area A3, as shown in FIG. 8b and Shown in Figure 8c.
  • the depth of the first auxiliary via 911 in the direction perpendicular to the plane of the base substrate is substantially the same as the depth of the first connection via in the direction perpendicular to the plane of the base substrate.
  • the etching solution can etch the first auxiliary via 911 and the first connection via to approximately the same degree, thereby further improving the uniformity of the characteristics of the transistor.
  • a plurality of first auxiliary through holes 911 may be provided in the first non-display area A3.
  • the distribution density of the first auxiliary through holes 911 may be approximately equal to the distribution density of the first connection through holes.
  • the distribution density of the first auxiliary through holes 911 may also be made smaller than the distribution density of the first connection through holes. Since other traces or connections are also provided in the first non-display area A3, by reducing the distribution density of the first auxiliary through holes 911, the overall occupied area of all the first auxiliary through holes 911 can be reduced, and the first non-display area A3 is reduced. Occupied area.
  • the etching effect of the first connection through hole etched in the sub-pixel spx at the display edge and the first connection through hole etched in the inner sub-pixel spx can be made uniform. Improve the uniformity of transistor characteristics.
  • the distribution density of the first auxiliary through holes 911 may be the number of the first auxiliary through holes 911 in a unit area.
  • the distribution density of the first connection vias may be the number of the first connection vias per unit area.
  • the distribution density of the first auxiliary through holes 911 and the first connecting through holes can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • the distance between two adjacent first auxiliary through holes may be substantially equal to the distance between two adjacent first connecting through holes.
  • the spacing between the first auxiliary through holes can be used for design.
  • the distance between two adjacent first auxiliary through holes can also be made smaller than the distance between two adjacent first connecting through holes. In this way, the first auxiliary through holes can be arranged more compactly, and the occupied area of the first non-display area can be reduced.
  • the orthographic projection of the first auxiliary via 911 on the base substrate 010 and the semiconductor layer, the first conductive layer 100, and the second The orthographic projections of the three conductive layers 300 and the fourth conductive layer 400 on the base substrate 010 do not overlap. This can reduce the influence on the conductive layer and the semiconductor layer when the first auxiliary via 911 is etched.
  • the second connection via is also used to realize the electrical connection of the transistors in the sub-pixel spx.
  • the electrical connection of these transistors is related to the characteristics of their transistors. Therefore, the electrical connection of the transistors is uniform, which can make the characteristics of the transistors uniform.
  • a wet etching method is used to prepare the second connection through hole through an etching solution.
  • the second connection through hole of the sub-pixel spx at the edge of the display area A1 does not need to be etched outside the edge of the display area A1, so that the second connection of the sub-pixel spx at the edge of the display area A1
  • the etching degree of the via hole is different from the etching degree of the second connection via hole of the sub-pixel spx inside the display area A1, which results in the uneven characteristics of the transistors in the edge sub-pixel spx and the transistors in the inner sub-pixel spx of the display area A1 .
  • the functional layer includes a third conductive layer;
  • the target insulating layer includes: a second gate insulating layer and an interlayer dielectric layer; Connecting through holes; the auxiliary through holes include second auxiliary through holes, the second auxiliary through holes penetrating the second gate insulating layer and the interlayer dielectric layer.
  • the display panel may further include at least one second auxiliary via 912 located in the first non-display area A3; wherein the second auxiliary via 912 penetrates the second gate insulating layer 620 and the interlayer dielectric layer 630, and the second auxiliary via 912 is not filled with conductive material.
  • the second auxiliary through hole 912 may also be located in the auxiliary area FB.
  • an insulating material may be filled in the second auxiliary through hole 912.
  • the material of the interlayer insulating layer 640 may be filled in the second auxiliary via hole 912. In this way, when the interlayer insulating layer 640 is prepared, the second auxiliary via hole 912 can be directly filled, so that the flatness of the interlayer insulating layer 640 can be improved.
  • a plurality of second auxiliary through holes 912 may be provided in the first non-display area A3.
  • the distribution density of the second auxiliary via holes 912 may be approximately equal to the distribution density of the second connection via holes.
  • the distribution density of the second auxiliary through holes 912 may also be made smaller than the distribution density of the second connection through holes. Since other traces or connections are also provided in the first non-display area A3, by reducing the distribution density of the second auxiliary through holes 912, the overall occupied area of all the second auxiliary through holes 912 can be reduced, and the first non-display area A3 is reduced. Occupied area.
  • the second connection via etched in the sub-pixel spx at the display edge can be uniformly etched with the first connection via etched in the inner sub-pixel spx. Improve the uniformity of transistor characteristics.
  • the distribution density of the second auxiliary through holes 912 may be the number of the second auxiliary through holes 912 in a unit area.
  • the distribution density of the second connection vias may be the number of the second connection vias per unit area.
  • the distribution density of the second auxiliary through holes 912 and the second connecting through holes can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • the third conductive layer 300 when the third conductive layer 300 is patterned, the third conductive layer 300 in the first non-display area A3 will be etched away, so the first non-display area A3 will not remain in the first non-display area A3.
  • Three conductive layers 300 as shown in FIG. 8c. In this way, the depth of the second auxiliary via 912 in the direction perpendicular to the plane of the base substrate is greater than the depth of the second connection via in the direction perpendicular to the plane of the base substrate.
  • the spacing between two adjacent second auxiliary through holes may be substantially equal to the spacing between two adjacent second connecting through holes.
  • the spacing between the second auxiliary through holes can also be made smaller than the distance between two adjacent second connecting through holes. In this way, the second auxiliary through holes can be arranged more compactly, and the occupied area of the second non-display area can be reduced.
  • the orthographic projection of the second auxiliary via 912 on the base substrate 010 and the first conductive layer 100, the third conductive layer 300 and the The orthographic projection of the four conductive layers 400 on the base substrate 010 does not overlap. This can reduce the influence on the conductive layer and the semiconductor layer when the second auxiliary via hole 912 is etched.
  • the third connection through hole is also used to realize the electrical connection of the transistors in the sub-pixel spx.
  • the electrical connection of these transistors is related to the characteristics of their transistors. Therefore, the electrical connection of the transistors is uniform, which can make the characteristics of the transistors uniform.
  • a wet etching method is used to prepare the third connection through hole through an etching solution.
  • the third connection through hole of the sub-pixel spx at the edge of the display area A1 does not need to be etched outside the edge of the display area A1, so that the third connection through hole of the sub-pixel spx at the edge of the display area A1 is The etching degree is different from the etching degree of the third connection through hole of the sub-pixel spx inside the display area A1, which results in the uneven characteristics of the transistors in the edge sub-pixel spx of the display area A1 and the transistors in the inner sub-pixel spx.
  • the functional layer includes a fourth conductive layer; the target insulating layer includes: an interlayer dielectric layer; the connection via includes a third connection via; The hole includes a third auxiliary through hole, and the third auxiliary through hole penetrates the interlayer dielectric layer.
  • the display panel may further include at least one third auxiliary through hole 913 located in the first non-display area A3; the third auxiliary through hole 913 penetrates the interlayer dielectric layer 630, and The third auxiliary via 913 is not filled with conductive material.
  • the third auxiliary through hole 913 may also be located in the auxiliary area FB.
  • the third auxiliary through hole 913 may be filled with insulating material.
  • the material of the interlayer insulating layer 640 may be filled in the third auxiliary via hole 913. In this way, when the interlayer insulating layer 640 is prepared, the third auxiliary via 913 can be directly filled, so that the flatness of the interlayer insulating layer 640 can be improved.
  • a plurality of third auxiliary through holes 913 may be provided in the first non-display area A3.
  • the distribution density of the third auxiliary via holes 913 may be approximately equal to the distribution density of the third connection via holes.
  • the etching effect of the third connection through hole etched in the display edge sub-pixel spx and the third connection through hole etched in the inner sub-pixel spx can be made uniform, and the uniformity of the characteristics of the transistor can be improved.
  • the distribution density of the third auxiliary through holes 913 may also be made smaller than the distribution density of the third connection through holes. Since other traces or connections are also provided in the first non-display area A3, by reducing the distribution density of the third auxiliary through holes 913, the overall occupied area of all the third auxiliary through holes 913 can be reduced, and the first non-display area A3 is reduced. Occupied area.
  • the third connection through hole etched in the display edge sub-pixel spx can be uniformly etched with the first connection through hole etched in the inner sub-pixel spx. Improve the uniformity of transistor characteristics.
  • the distribution density of the third auxiliary through holes 913 may be the number of the third auxiliary through holes 913 in a unit area.
  • the distribution density of the third connection vias may be the number of the third connection vias per unit area.
  • the distribution density of the third auxiliary through holes 913 and the third connecting through holes can be designed and determined according to the requirements of the actual application environment, and is not limited here.
  • the fourth conductive layer 400 in the first non-display area A3 will be etched away, so the first non-display area A3 will not remain in the first non-display area A3.
  • the spacing between two adjacent third auxiliary through holes may be substantially equal to the spacing between two adjacent third connecting through holes.
  • the spacing between the third auxiliary through holes can be used for design.
  • the distance between two adjacent third auxiliary through holes can also be made smaller than the distance between two adjacent third connecting through holes. In this way, the third auxiliary through holes can be arranged more compactly, and the occupied area of the first non-display area can be reduced.
  • the orthographic projection of the third auxiliary via 913 on the base substrate 010 and the first conductive layer 100 and the fourth conductive layer 400 line The orthographic projections of the base substrate 010 do not overlap. In this way, the influence on the conductive layer and the semiconductor layer when the third auxiliary via hole 913 is etched can be reduced.
  • GA1-G(q) represents the first scan line corresponding to the q-th row of sub-pixels.
  • GA2-G(q) represents the second scan line corresponding to the sub-pixel in the qth row.
  • GA1-G(q+1) represents the first scan line corresponding to the sub-pixels in the q+1th row.
  • EM-G(q) represents the emission control line corresponding to the sub-pixel in the qth row.
  • EM-G(q+1) represents the emission control line corresponding to the sub-pixel in the q+1th row. The following is the same and will not be repeated here.
  • the same or equal of the above-mentioned features may not be completely the same or equal, and there may be some deviations. Therefore, the same or equal relationship between the above-mentioned features as long as the above-mentioned relationship is substantially satisfied.
  • the conditions are sufficient, and all belong to the protection scope of the present disclosure.
  • the above-mentioned sameness may be the same as allowed within the allowable error range.
  • FIGS. 9a to 10c are modified for some implementations in the above-mentioned embodiments.
  • FIGS. 9a to 10c are modified for some implementations in the above-mentioned embodiments.
  • FIGS. 9a to 10c are modified for some implementations in the above-mentioned embodiments.
  • the orthographic projection of the first data connection portion 211 on the base substrate 010 and the orthographic projection of the first scan line GA1 on the base substrate 010 have an overlapping area, and the first data line 121 and the first data transmission line 711 are on the substrate
  • the orthographic projection of the substrate 010 and the orthographic projection of the first scan line GA1 on the base substrate 010 do not overlap.
  • the first scan line GA1 and the first data line 121 are formed with an area facing each other.
  • the first data connection portion 211 is located in the second conductive layer 200, the distance between the first scan line GA1 and the first data connection portion 211 can be made larger, so that the first scan line GA1 and the first data connection portion 211 can be made larger.
  • the reduction of the coupling capacitance between the data connection parts 211 is small, so that the signal interference can be reduced, and the display effect can be improved.
  • the edge area of the first data connection portion 211 is projected on the base substrate 010 and the first The scanning line GA1 has an overlapping area on the orthographic projection of the base substrate 010.
  • the orthographic projection of the central area of the first data connection portion 211 on the base substrate 010 and the first scan line GA1 on the base substrate has overlapping areas.
  • a part of the row sub-pixels spx in the first type row sub-pixels spx corresponds to two first data connection parts.
  • the sub-pixel G(q+2) in the q+2th row in FIGS. 9a and 9b may correspond to two first data connection parts: 211a and 211b.
  • the two first data connection portions 211a and 211b can be positioned on the front side of the base substrate 010.
  • the projection and the orthographic projection of the first scan line GA1 on the base substrate 010 have an overlapping area, and the orthographic projection of the two first data connection portions 211a and 211b on the base substrate 010 and the second scan line GA2 on the substrate The orthographic projections of the substrate 010 do not overlap.
  • the two first data connection portions As shown in FIGS. 9a to 10a, for the first scan line GA1, second scan line GA2, and two first data connection portions a and 211b corresponding to the same row of sub-pixels spx, the two first data connection portions
  • the orthographic projection of the first first data connection portion 211a on the base substrate 010 is close to the orthographic projection of the first scan through hole 811 corresponding to the first scan line GA1 on the base substrate 010.
  • the first first data connection portion 211a can make the first first data connection portion 211a be on the base substrate.
  • the orthographic projection of 010 is close to the orthographic projection of the first scan through hole 811 corresponding to the first scan line GA1 on the base substrate 010.
  • the second of the two first data connection parts is close to the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 on the base substrate 010.
  • the second first data connection part 211b of the two first data connection parts is compared with the first first data connection part 211a, so that the second first data connection part 211b can be on the base substrate.
  • the orthographic projection of 010 is close to the orthographic projection of the second scan through hole 812 corresponding to the second scan line GA2 on the base substrate 010.
  • the orthographic projection of the second data connection portion 212 on the base substrate 010 and the orthographic projection of the first scan line GA1 on the base substrate 010 have an overlapping area
  • the second data line 122 and the second data transmission line 712 are on the substrate
  • the orthographic projection of the substrate 010 and the orthographic projection of the first scan line GA1 on the base substrate 010 do not overlap.
  • the row of sub-pixels also corresponds to a second data connection portion 212.
  • the second data connection portion 212 is in line
  • the orthographic projection of the base substrate 010 and the orthographic projection of the first scan line GA1 on the base substrate 010 have an overlapping area, and the orthographic projection of the second data line 122 and the second data transmission line 712 on the base substrate 010 and the first scan line
  • the orthographic projection of GA1 on the base substrate 010 does not overlap.
  • a first auxiliary through hole 911, a second auxiliary through hole 912, and a third auxiliary through hole 913 are also provided in the display panel.
  • the arrangement of the first auxiliary through hole 911, the second auxiliary through hole 912, and the third auxiliary through hole 913 can be referred to the above-mentioned embodiment, which will not be repeated here.
  • the embodiments of the present disclosure also provide further display panels, as shown in FIG. 11 and FIG. 12, which are modified for some implementations in the above-mentioned embodiments.
  • FIG. 11 and FIG. 12 are modified for some implementations in the above-mentioned embodiments.
  • the fourth conductive layer 400 may further include a plurality of third scan transmission lines 413 located in the first non-display area A3.
  • the interlayer dielectric layer 630 may further include a plurality of fourth scan through holes 814; the first scan line GA1 and the second scan line GA2 electrically connected to each other correspond to a third scan transmission line 413, and the first scan connection portion 131 It is also electrically connected to the third scan transmission line 413 through the fourth scan via 814.
  • the third conductive layer 300 may further include a third light-emitting transmission line 423 located in the first non-display area A3; wherein the light-emitting control lines electrically connected to each other are directly electrically connected to a third light-emitting transmission line 423.
  • the third light emitting transmission line 423 can be provided in the third conductive layer 300 and the third scan transmission line 413 can be provided in the fourth conductive layer 400.
  • the orthographic projection of the third scanning transmission line 413 on the base substrate 010 and the orthographic projection of the third light-emitting transmission line 423 on the base substrate 010 do not overlap. Further, the orthographic projection of the third scanning transmission line 413 on the base substrate 010 and the orthographic projection of the third light-emitting transmission line 423 on the base substrate 010 are spaced apart.
  • the orthographic projection of the third scanning transmission line 413 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of the third scanning transmission line 413 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may be partially overlapped. Since the third scan transmission layer is located on the fourth conductive layer 400 and the second data transmission line 712 is located on the second conductive layer 200, this not only reduces the coupling capacitance between the third scan transmission line 413 and the second data transmission line 712, but also reduces The occupied area of the first non-display area A3.
  • the orthographic projection of the third light-emitting transmission line 423 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of the third light-emitting transmission line 423 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may partially overlap. Since the third light-emitting transmission line 423 is located on the third conductive layer 300 and the first data transmission line 711 is located on the first conductive layer 100, this not only reduces the coupling capacitance between the third light-emitting transmission layer and the first data transmission line 711, but also reduces The occupied area of the first non-display area A3.
  • first auxiliary through hole 911 the second auxiliary through hole 912, and the third auxiliary through hole 913 can be referred to the above-mentioned embodiment, which will not be repeated here.
  • the embodiments of the present disclosure also provide further display panels, as shown in FIG. 13 and FIG. 14, which are modified for some implementations in the above-mentioned embodiments.
  • FIG. 13 and FIG. 14 are modified for some implementations in the above-mentioned embodiments.
  • the fourth conductive layer 400 may further include a plurality of fourth light-emitting transmission lines 424 located in the first non-display area A3; the interlayer dielectric layer 630 may also include a plurality of fourth light-emitting through holes 824; The light-emitting control lines EM electrically connected to each other correspond to a fourth light-emitting transmission line 424.
  • the first light-emitting connection portion 141 is also electrically connected to the fourth light-emitting transmission line 424 through the fourth light-emitting through hole 824;
  • the third conductive layer 300 may further include a fourth scan transmission line 414 located in the first non-display area A3;
  • the first scan line GA1 and the second scan line GA2 that are electrically connected are directly electrically connected to a fourth scan transmission line 414.
  • the fourth scanning transmission line 414 can be provided in the third conductive layer 300 and the fourth light emitting transmission line 424 can be provided in the fourth conductive layer 400.
  • the orthographic projection of the fourth scanning transmission line 414 on the base substrate 010 and the orthographic projection of the fourth light-emitting transmission line 424 on the base substrate 010 may not overlap.
  • the orthographic projection of the fourth scanning transmission line 414 on the base substrate 010 and the orthographic projection of the fourth light-emitting transmission line 424 on the base substrate 010 may be arranged at intervals.
  • the orthographic projection of the fourth scanning transmission line 414 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of the fourth scanning transmission line 414 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may be partially overlapped. Since the fourth scan transmission layer is located on the third conductive layer 300 and the first data transmission line 711 is located on the first conductive layer 100, this not only reduces the coupling capacitance between the fourth scan transmission layer and the first data transmission line 711, but also reduces The occupied area of the first non-display area A3.
  • the orthographic projection of the fourth light-emitting transmission line 424 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of the fourth light-emitting transmission line 424 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may be partially overlapped. Since the fourth light-emitting transmission line 424 is located on the fourth conductive layer 400 and the second data transmission line 712 is located on the second conductive layer 200, this not only makes the coupling capacitance between the fourth light-emitting transmission layer and the second data transmission line 712 larger, but also Reduce the occupied area of the first non-display area A3.
  • first auxiliary through hole 911 the second auxiliary through hole 912, and the third auxiliary through hole 913 can be referred to the above-mentioned embodiment, which will not be repeated here.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive points will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the first data connection portion is disposed in the second conductive layer, so that the data line and the first data transmission line in the first conductive layer can pass through the second conductive layer.
  • the first data connection parts are electrically connected to each other. In this way, not only the data lines corresponding to the same column of sub-pixels and separated by the notch area can be electrically connected, but also the interference of the first data connection portion to the third conductive layer and the fourth conductive layer can be reduced, thereby improving signal stability. , Improve the display effect.

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Abstract

显示面板及显示装置，其中，显示面板包括：衬底基板（010），包括缺口区（A2）、显示区（A1）以及第一非显示区（A3），第一非显示区（A3）位于缺口区（A2）与显示区（A1）之间；第一导电层，位于衬底基板上；目标绝缘层，位于第一导电层与衬底基板之间；功能层，位于目标绝缘层与衬底基板（010）之间；显示区（A1）包括多个子像素（spx），多个子像素（spx）中的至少一个包括：连接通孔；其中，连接通孔贯穿目标绝缘层，且第一导电层通过连接通孔与功能层电连接；第一非显示区（A3）包括至少一个辅助通孔，其中，辅助通孔贯穿目标绝缘层且辅助通孔未填充导电材料。

Description

显示面板及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今电致发光显示装置应用研究领域的热点之一。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板，包括缺口区、显示区以及第一非显示区，所述第一非显示区位于所述缺口区与所述显示区之间；
第一导电层，位于所述衬底基板上；
目标绝缘层，位于所述第一导电层与所述衬底基板之间；
功能层，位于所述目标绝缘层与所述衬底基板之间；
所述显示区包括多个子像素、多条数据线、多条扫描线、多条发光控制线；其中，所述多个子像素中的至少一个包括：连接通孔；其中，所述连接通孔贯穿所述目标绝缘层，且所述第一导电层通过所述连接通孔与所述功能层电连接；
所述第一非显示区包括：至少一个辅助通孔、多条数据传输线、多条扫描传输线以及多条发光传输线：其中，所述多条数据线中的至少一条与所述多条数据传输线中的至少一条电连接，所述多条扫描线中的至少一条与所述多条扫描传输线中的至少一条电连接，所述多条发光控制线中的至少一条与所述多条发光传输线中的至少一条电连接；
所述第一非显示区中，所述多条数据传输线、所述多条扫描传输线以及所述多条发光传输线中的至少两种传输线围绕形成辅助区域，所述辅助通孔位于所述辅助区域内，且所述辅助通孔贯穿所述目标绝缘层且所述辅助通孔未填充导电材料。
可选地，在本公开实施例中，所述显示面板包括：
半导体层，位于所述衬底基板与所述第一导电层之间；
第一栅绝缘层，位于所述半导体层与所述第一导电层之间；
第三导电层，位于所述第一栅绝缘层与所述第一导电层之间；
第二栅绝缘层，位于所述第三导电层与所述第一导电层之间；
第四导电层，位于所述第二栅绝缘层与所述第一导电层之间；
层间介质层，位于所述第四导电层与所述第一导电层之间；
所述多个子像素中的至少一个包括：第一连接通孔、第二连接通孔以及第三连接通孔；其中，所述第一连接通孔贯穿所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层；所述第二连接通孔贯穿所述第二栅绝缘层与所述层间介质层；所述第三连接通孔贯穿所述层间介质层；
所述第一导电层通过所述第一连接通孔与所述半导体层电连接；
所述第一导电层通过所述第二连接通孔与所述第三导电层电连接；
所述第一导电层通过所述第三连接通孔与所述第四导电层电连接；
所述辅助通孔中填充绝缘材料。
可选地，在本公开实施例中，所述显示面板，还包括：
层间绝缘层，位于所述第一导电层背离所述衬底基板一侧；
所述辅助通孔中填充所述层间绝缘层的材料。
可选地，在本公开实施例中，所述功能层包括所述半导体层；
所述目标绝缘层包括：所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层；
所述连接通孔包括所述第一连接通孔；
所述辅助通孔包括第一辅助通孔，所述第一辅助通孔贯穿所述第一栅绝 缘层、所述第二栅绝缘层以及所述层间介质层，且所述第一辅助通孔中填充的材料贯穿所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层。
可选地，在本公开实施例中，所述第一辅助通孔的分布密度小于或大致等于所述第一连接通孔的分布密度。
可选地，在本公开实施例中，所述第一辅助通孔在所述衬底基板的正投影与所述半导体层、所述第三导电层、所述第四导电层以及所述第一导电层在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述功能层包括所述第三导电层；
所述目标绝缘层包括：所述第二栅绝缘层与所述层间介质层；
所述连接通孔包括所述第二连接通孔；
所述辅助通孔包括第二辅助通孔，所述第二辅助通孔贯穿所述第二栅绝缘层与所述层间介质层，且所述第二辅助通孔中填充的材料贯穿所述第二栅绝缘层与所述层间介质层。
可选地，在本公开实施例中，所述第二辅助通孔的分布密度小于或大致等于所述第二连接通孔的分布密度。
可选地，在本公开实施例中，所述第二辅助通孔在所述衬底基板的正投影与所述第三导电层、所述第四导电层以及所述第一导电层在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述功能层包括所述第四导电层；
所述目标绝缘层包括：所述层间介质层；
所述连接通孔包括所述第三连接通孔；
所述辅助通孔包括第三辅助通孔，所述第三辅助通孔贯穿所述层间介质层，且所述第三辅助通孔中填充的材料贯穿所述层间介质层。
可选地，在本公开实施例中，所述第三辅助通孔的分布密度小于或大致等于所述第三连接通孔的分布密度。
可选地，在本公开实施例中，所述第三辅助通孔在所述衬底基板的正投影与所述第四导电层以及所述第一导电层在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述多条数据传输线包括多条第一数据传输线；第一导电层，包括所述多条数据线和所述多条第一数据传输线；所述层间绝缘层具有多个第一数据通孔；
所述显示面板，还包括：
第二导电层，位于所述层间绝缘层背离所述衬底基板一侧，且包括多个第一数据连接部；
所述多个第一数据连接部中的至少一个通过所述第一数据通孔分别与所述多条数据线中的至少一个和所述多条第一数据传输线中的至少一个电连接。
可选地，在本公开实施例中，所述多条数据传输线包括多条第二数据传输线；
所述第二导电层还包括：所述多条第二数据传输线；所述多条第二数据传输线与所述第一数据连接部间隔设置；
所述层间绝缘层还包括：多个第二数据通孔；
所述多条数据线包括多条第一数据线和多条第二数据线；其中，一条所述第一数据线通过所述第一数据连接部与一条所述第一数据传输线电连接；一条所述第二数据线通过所述第二数据通孔与一条所述第二数据传输线电连接。
可选地，在本公开实施例中，所述第三导电层包括所述多条扫描线和所述多条发光控制线；其中，所述多条扫描线包括多条第一扫描线和多条第二扫描线；
所述显示区还包括多个子像素；其中，一行所述子像素对应一条所述第一扫描线和一条所述第二扫描线；每相邻两行子像素中的第一行子像素对应的第二扫描线与第二行子像素对应的第一扫描线电连接；
一行所述子像素对应一条所述发光控制线；且相邻两行子像素对应的发光控制线电连接。
可选地，在本公开实施例中，所述第一导电层还包括：与所述数据线和所述第一数据传输线绝缘且间隔设置的多个第一扫描连接部；其中，第q-1 行子像素对应的第二扫描线与第q行子像素对应的第一扫描线通过至少一个所述第一扫描连接部电连接；q为整数；
所述第二绝缘层包括多个第一扫描通孔和多个第二扫描通孔；
所述第一扫描连接部的第一端通过所述多个第一扫描通孔中的至少一个与对应的所述第一扫描线电连接，所述第一扫描连接部的第二端通过所述多个第二扫描通孔中的至少一个与对应的所述第二扫描线电连接。
可选地，在本公开实施例中，所述所有行子像素包括第一类行子像素；第一类行子像素中的至少一行子像素对应至少一个所述第一数据连接部；
针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述第一数据连接部，所述第一数据连接部在衬底基板的正投影与所述第一扫描线对应的第一扫描连接部和所述第二扫描线对应的第一扫描连接部在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述第一数据连接部，所述第一数据连接部在所述衬底基板的正投影位于所述第一扫描线对应的第一扫描通孔和所述第二扫描线对应的第二扫描通孔在所述衬底基板的正投影之间。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述第一数据连接部，所述第一扫描线对应的第一扫描通孔在所述衬底基板的正投影的中心和所述第二扫描线对应的第二扫描通孔在所述衬底基板的正投影的中心之间的连线与所述第一数据连接部在所述衬底基板的正投影交叠。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一扫描线与所述第一数据连接部以及采用所述第一数据连接部电连接的第一数据线和第一数据传输线，所述第一数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，且所述第一数据线和所述第一数据传输线在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一扫描线与所述第一数据连接部，所述第一数据连接部的边缘区域在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一扫描线与所述第一数据连接部，所述第一数据连接部的中心区域在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述第一类行子像素中的部分行子像素对应两个所述第一数据连接部，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述两个第一数据连接部，所述两个第一数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，所述两个第一数据连接部在所述衬底基板的正投影与所述第二扫描线在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述两个第一数据连接部，
所述两个第一数据连接部中的第一个第一数据连接部在所述衬底基板的正投影靠近所述第一扫描线对应的第一扫描通孔在所述衬底基板的正投影；和/或，
所述两个第一数据连接部中的第二个第一数据连接部在所述衬底基板的正投影靠近所述第二扫描线对应的第二扫描通孔在所述衬底基板的正投影。
可选地，在本公开实施例中，所述第二导电层还包括：多个第二数据连接部；其中，一条所述第二数据传输线直接电连接至少一个所述第二数据连接部，且所述第二数据连接部通过所述第二数据通孔与一条所述第二数据线电连接。
可选地，在本公开实施例中，沿第一方向，所述第一数据线和所述第二数据线交替排列；
所述第一数据连接部和所述第二数据连接部在沿所述第一方向延伸的直线上的投影交替排列。
可选地，在本公开实施例中，所述所有行子像素包括第二类行子像素；所述第二类行子像素与所述第一类行子像素不同；
所述第二类行子像素中的至少一行子像素对应至少一个所述第二数据连接部；
针对同一行子像素对应的所述第一扫描线与所述第二数据连接部以及采用所述第二数据连接部电连接的第二数据线和第二数据传输线，所述第二数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，且所述第二数据线和所述第二数据传输线在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，针对对应两个所述第一数据连接部的一行子像素，所述行子像素还对应一个所述第二数据连接部；
针对同一行子像素对应的所述第一扫描线与所述第二数据连接部以及采用所述第二数据连接部电连接的第二数据线和第二数据传输线，所述第二数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，且所述第二数据线和所述第二数据传输线在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述第一导电层还包括：与所述数据线和所述第一数据传输线绝缘且间隔设置的多个第一发光连接部；其中，相互电连接的所述发光控制线对应至少一个所述第一发光连接部；
所述第二绝缘层包括多个第一发光通孔和多个第二发光通孔；
所述第一发光连接部的第一端通过所述多个第一发光通孔中的至少一个与对应的一条所述发光控制线电连接，所述第一发光连接部的第二端通过所述多个第二发光通孔中的至少一个与对应的另一条所述发光控制线电连接。
可选地，在本公开实施例中，所述多条扫描传输线包括：多条第一扫描传输线和多条第二扫描传输线，所述发光传输线包括多条第一发光传输线和多条第二发光传输线；
所述第三导电层还包括位于所述第一非显示区的所述多条第一扫描传输 线和所述多条第一发光传输线；其中，所述第一扫描传输线和所述第一发光传输线间隔设置；
部分相互电连接的所述第一扫描线和所述第二扫描线直接对应电连接一条所述第一扫描传输线；且部分相互电连接的发光控制线直接电连接一条所述第一发光传输线；
所述第四导电层还包括位于所述第一非显示区的所述多条第二扫描传输线和所述多条第二发光传输线；其中，所述第二扫描传输线和所述第二发光传输线间隔设置；
所述层间介质层还包括多个第三扫描通孔和多个第三发光通孔；
其余部分相互电连接的所述第一扫描线和所述第二扫描线对应一条所述第二扫描传输线，且所述第一扫描连接部还通过所述第三扫描通孔与所述第二扫描传输线电连接；
其余部分相互电连接的所述发光控制线对应一条所述第二发光传输线，且所述第一发光连接部还通过所述第三发光通孔与所述第二发光传输线电连接。
可选地，在本公开实施例中，所述多条扫描传输线包括：多条第三扫描传输线，所述发光传输线包括多条第三发光传输线；
所述第四导电层包括位于所述第一非显示区的多条第三扫描传输线；
所述层间介质层包括多个第四扫描通孔；
相互电连接的所述第一扫描线和所述第二扫描线对应一条所述第三扫描传输线，并且，所述第一扫描连接部还通过第四扫描通孔与所述第三扫描传输线电连接；
所述第三导电层还包括位于所述第一非显示区的第三发光传输线；其中，相互电连接的发光控制线直接电连接一条所述第三发光传输线。
可选地，在本公开实施例中，所述多条扫描传输线包括：多条第四扫描传输线，所述发光传输线包括多条第四发光传输线；
所述第四导电层包括位于所述第一非显示区的多条第四发光传输线；
所述层间介质层包括多个第四发光通孔；
相互电连接的所述发光控制线对应一条所述第四发光传输线，并且，所述第一发光连接部还通过第四发光通孔与所述第四发光传输线电连接；
所述第三导电层还包括位于所述第一非显示区的第四扫描传输线；其中，相互电连接的所述第一扫描线与所述第二扫描线直接电连接一条所述第四扫描传输线。
可选地，在本公开实施例中，针对同一行子像素对应的所述发光控制线、所述第二扫描线以及所述第二数据连接部，所述第二数据连接部在所述衬底基板的正投影位于所述第二扫描线对应的第二扫描通孔和所述发光控制线对应的第一发光通孔在所述衬底基板的正投影之间。
本公开实施例还提供的显示装置，包括上述显示面板。
附图说明
图1为本公开实施例提供的一些显示面板的结构示意图；
图2为本公开实施例提供的一些子像素中的电路结构示意图；
图3为本公开实施例提供的一些子像素中的布局结构示意图；
图4a为本公开实施例提供的一些子像素中的半导体层的布局结构示意图；
图4b为本公开实施例提供的一些子像素中的第三导电层的布局结构示意图；
图4c为本公开实施例提供的一些子像素中的第四导电层的布局结构示意图；
图4d为本公开实施例提供的一些子像素中的第一导电层的布局结构示意图；
图4e为本公开实施例提供的一些子像素中的第二导电层的布局结构示意图；
图5为图3所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图6为本公开实施例提供的又一些显示面板的结构示意图；
图7a为本公开实施例提供的一些显示面板的局部区域的布局结构示意图；
图7b为本公开实施例提供的又一些显示面板的局部区域的布局结构示意图；
图8a为图7a所示的显示面板的局部区域的布局结构示意图中沿AA’方向上的剖视结构示意图；
图8b为图7a所示的显示面板的局部区域的布局结构示意图中沿BB’方向上的剖视结构示意图；
图8c为图7b所示的显示面板的局部区域的布局结构示意图中沿BB’方向上的剖视结构示意图；
图9a为本公开实施例提供的又一些显示面板的局部区域的布局结构示意图；
图9b为本公开实施例提供的又一些显示面板的局部区域的布局结构示意图；
图10a为图9a所示的显示面板的局部区域的布局结构示意图中沿AA’方向上的剖视结构示意图；
图10b为图9a所示的显示面板的局部区域的布局结构示意图中沿BB’方向上的剖视结构示意图；
图10c为图9b所示的显示面板的局部区域的布局结构示意图中沿BB’方向上的剖视结构示意图；
图11为本公开实施例提供的又一些显示面板的局部区域的布局结构示意图；
图12为图11所示的显示面板的局部区域的布局结构示意图中沿AA’方向上的剖视结构示意图；
图13为本公开实施例提供的又一些显示面板的局部区域的布局结构示意图；
图14为图13所示的显示面板的局部区域的布局结构示意图中沿AA’方向上的剖视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
随着显示技术的发展，全面屏以其具有较大的屏占比、超窄的边框，与普通的显示屏相比，可以大大提高观看者的视觉效果，从而受到了广泛的关注。一般，在采用全面屏的诸如手机的显示装置中，为了实现自拍和通话功能，通常都会在显示装置的正面设置前置摄像头、听筒等。一般在显示面板中一般设置有用于设置前置摄像头、听筒等器件的缺口区A2。然而，由于该缺口区A2的存在，需要使扫描线和数据线根据缺口区A2进行绕线设置，这样导致扫描线和数据线之间具有耦合作用，造成信号干扰，影响显示效果。
有鉴于此，本公开实施例提供了显示面板，可以降低扫描线和数据线之间的耦合作用，降低信号干扰，提高显示效果。
如图1所示，本公开实施例提供的显示面板，可以包括：衬底基板010。 该衬底基板010可以包括缺口区A2、显示区A1以及第一非显示区A3，第一非显示区A3位于缺口区A2与显示区A1之间。其中，该衬底基板010可以为玻璃基板、柔性基板、硅基板等，在此不作限定。在显示面板应用到显示装置中时，一般还会设置摄像头、听筒等器件，因此为了设置摄像头、听筒等器件，缺口区A2可以为衬底基板010的镂空区域。例如，在实际制备过程中，通过将该衬底基板010中对应缺口区A2的位置以切割的方式挖孔使其成为镂空区域，以用于在显示装置中设置摄像头、听筒等器件。或者，也可以不对衬底基板010进行切割，而是通过使衬底基板010上的线路进行避让，以使对应缺口区A2的位置为透明区域，以形成缺口区A2。
在实际应用中，显示面板一般还可以包括围绕显示区A1的边框区域。在边框区域中可以设置静电释放电路、栅极驱动电路等元件。当然，显示面板也可以不设置边框区域，这些可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图1所示，显示区A1还可以包括阵列排布的多个像素单元PX。其中，像素单元PX可以包括多个子像素spx。子像素spx可以阵列排布于显示区A1中。示例性地，结合图1与图2所示，子像素spx可以包括：像素驱动电路0121和发光器件0120。其中，像素驱动电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号输入到发光器件0120的第一发光电极中。并且对发光器件0120的第二发光电极加载相应的电压，可以驱动发光器件0120发光。
结合图2所示，像素驱动电路0121可以包括：驱动控制电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。
驱动控制电路0122可以包括控制端、第一端和第二端。且驱动控制电路0122被配置为发光器件0120提供驱动发光器件0120发光的驱动电流。例如，第一发光控制电路0123与驱动控制电路0122的第一端和第一电压端VDD连接。且驱动控制电路0122被配置为实现驱动控制电路0122和第一电压端VDD 之间的连接导通或断开。
第二发光控制电路0124与驱动控制电路0122的第二端和发光器件0120的第一发光电极电连接。且第二发光控制电路0124被配置为实现驱动控制电路0122和发光器件0120之间的连接导通或断开。
数据写入电路0126与驱动控制电路0122的第一端电连接。且第二发光控制电路0124被配置为在扫描线GA2上的信号的控制下将数据线VD上的信号写入存储电路0127。
存储电路0127与驱动控制电路0122的控制端和第一电压端VDD电连接。且存储电路0127被配置为存储数据信号。
阈值补偿电路0128与驱动控制电路0122的控制端和第二端电连接。且阈值补偿电路0128被配置为对驱动控制电路0122进行阈值补偿。
复位电路0129与驱动控制电路0122的控制端和发光器件0120的第一发光电极电连接。且复位电路0129被配置为在栅线GA1上的信号的控制下对驱动控制电路0122的控制端和发光器件0120的第一发光电极进行复位。
其中，发光器件0120可以包括层叠设置的第一发光电极、发光功能层、第二发光电极。示例性地，第一发光电极可以为阳极、第二发光电极可以为阴极。发光功能层可以包括发光层。进一步地，发光功能层还可以包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光器件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2所示，驱动控制电路0122包括：驱动晶体管T1，驱动控制电路0122的控制端包括驱动晶体管T1的栅极，驱动控制电路0122的第一端包括驱动晶体管T1的第一极，驱动控制电路0122的第二端包括驱动晶体管T1的第二极。
示例性地，结合图2所示，数据写入电路0126包括数据写入晶体管T2。存储电路0127包括存储电容CST。阈值补偿电路0128包括阈值补偿晶体管T3。第一发光控制电路0123包括第一发光控制晶体管T4。第二发光控制电 路0124包括第二发光控制晶体管T5。复位电路0129包括第一复位晶体管T6和第二复位晶体管T7。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线VD电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第二扫描线GA2电连接以接收扫描信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T1的栅极电连接。
阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描线GA2电连接以接收补偿控制信号。
第一复位晶体管T6的第一极被配置为与第一复位信号线VINIT1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一扫描线GA1电连接以接收控制信号。
第二复位晶体管T7的第一极被配置为与第二复位信号线VINIT2电连接以接收第二复位信号，第二复位晶体管T7的第二极与发光器件0120的第一发光电极电连接，第二复位晶体管T7的栅极被配置为与第一扫描线GA1电连接以接收控制信号。
第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光器件0120的第一发光电极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
发光器件0120的第二发光电极与第二电源端VSS电连接。其中，上述晶 体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
需要说明的是，在本公开实施例中，子像素spx中的像素驱动电路除了可以为图2所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
图3为本公开一些实施例提供的像素驱动电路的布居(Layout)结构示意图。图4a至图4e为本公开一些实施例提供的像素驱动电路的各层的示意图。其中，图3至图4e所示的示例以一个子像素spx的像素驱动电路为例。其中，图3至图4e还示出了电连接到像素驱动电路0121的第一扫描线GA1、第二扫描线GA2、第一复位信号线VINIT1(第一复位信号线VINIT1和第二复位信号线VINIT2为同一条信号线，则示出了第一复位信号线VINIT1)、发光控制线EM、数据线VD、与第一电源端VDD电连接的第一电源信号线VDD1和第二电源信号线VDD2。第一电源信号线VDD1和第二电源信号线VDD2彼此电连接。
示例性地，如图3与图4a所示，示出了该像素驱动电路0121的半导体层500。半导体层500可采用半导体材料图案化形成。半导体层500可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
例如，半导体层500可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
需要说明的是，在显示区A1中，半导体层500可以采用构图工艺进行图案化。在第一非显示区A3中会保留未进行图案化的半导体层500。并且，第一非显示区A3和显示区A1中的半导体层500间隔设置。当然，本公开包括但不限于此。
示例性地，在上述的半导体层500上形成有第一栅绝缘层610(未示出)，用于保护上述的半导体层500。如图3与图4b所示，示出了该像素驱动电路0121的第三导电层300。第三导电层300设置在第一栅绝缘层610上，从而与半导体层500绝缘。第三导电层300可以包括存储电容CST的第二极CC2a、第一扫描线GA1、第二扫描线GA2、发光控制线EM以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
例如，如图3至图4b所示，数据写入晶体管T2的栅极可以为第二扫描线GA2与半导体层500交叠的部分，第一发光控制晶体管T4的栅极可以为发光控制线EM与半导体层500交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制线EM与半导体层500交叠的第二部分，第一复位晶体管T6的栅极为第一扫描线GA1与半导体层500交叠的第一部分，第二复位晶体管T7的栅极为第一扫描线GA1与半导体层500交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为第二扫描线GA2与半导体层500交叠的第一部分，阈值补偿晶体管T3的第二个栅极可为从第二扫描线GA2突出的突出部与半导体层500交叠的第二部分。如图3和4b所示，驱动晶体管T1的栅极可为存储电容CST的第二极CC2a。
需要说明的是，图4a中的各虚线矩形框示出了子像素spx中第三导电层300与半导体层500交叠的各个部分。其中，阈值补偿晶体管T3的有源层中具有与阈值补偿晶体管T3的第一个栅极交叠的第一沟道区以及与阈值补偿晶体管T3的第二个栅极交叠的第二沟道区，以及位于第一沟道区和第二沟道区之间的源漏区域。该源漏区域用于将第一沟道区和第二沟道区电连接。
示例性地，如图3与图4b所示，第一扫描线GA1、第二扫描线GA2以及发光控制线EM沿第二方向F2排布第二扫描线GA2位于第一扫描线GA1和发光控制线EM之间。
示例性地，如图3与图4b所示，在第二方向F2上，存储电容CST的第二极CC2a位于第二扫描线GA2和发光控制线EM之间。从第二扫描线GA2突出的突出部位于第二扫描线GA2的远离发光控制线EM的一侧。
示例性地，如图3与图4b所示，在第二方向F2上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。
例如，在一些实施例中，如图3与图4b所示，在第一方向F1上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。其中，驱动晶体管T1的栅极的第三侧和第四侧为在第一方向F1上驱动晶体管T1的栅极的彼此相对的两侧。
示例性地，在上述的第三导电层300上形成有第二栅绝缘层620(未示出)，用于保护上述的第三导电层300。如图3与图4c所示，示出了该像素驱动电路0121的第四导电层400。第四导电层400设置在第二栅绝缘层620上。第四导电层400可以包括：存储电容CST的第一极CC1a、第一复位信号线VINIT1以及遮光部344a。示例性地，存储电容CST的第一极CC1a在衬底基板010的正投影与存储电容CST的第二极CC2a在衬底基板010的正投影至少部分交叠以形成存储电容CST。遮光部344a在衬底基板010的正投影与阈值补偿晶体管T3的有源层中的源漏区域在衬底基板010的正投影具有交叠区域。
示例性地，在上述的第四导电层400上形成有层间介质层630(未示出)， 用于保护上述的第四导电层400。如图3与图4d所示，示出了该像素驱动电路0121的第一导电层100，第一导电层100设置在层间介质层630上。第一导电层100可以包括：数据线VD、第一电源信号线VDD1以及桥接部341a、342a以及343a。
示例性地，在上述的第一导电层100上形成有层间绝缘层640(未示出)，用于保护上述的第一导电层100。如图3与图4e所示，示出了该像素驱动电路0121的第二导电层200，第二导电层200设置在层间绝缘层640上。第二导电层200包括第二电源信号线VDD2和转接部351a。
图5为图3所示的布局结构示意图沿AA’方向上的剖视结构示意图。半导体层500与第三导电层300之间设置有第一栅绝缘层610，第三导电层300与第四导电层400之间设置有第二栅绝缘层620，第四导电层400与第一导电层100之间设置有层间介质层630，第一导电层100与第二导电层200之间设置有层间绝缘层640。
结合图3与图5所示，子像素spx中包括第一连接通孔、第二连接通孔、第三连接通孔以及第四连接通孔；其中，第一连接通孔贯穿第一栅绝缘层610、第二栅绝缘层620以及层间介质层630；第二连接通孔贯穿第二栅绝缘层620与层间介质层630；第三连接通孔贯穿层间介质层630；第四连接通孔贯穿层间绝缘层640。
示例性地，子像素spx中可以包括第一连接通孔381a、382a、384a、387a以及388a。子像素spx中可以包括第二连接通孔385a。子像素spx中可以包括第三连接通孔386a、3832a以及389a。子像素spx中包括第四连接通孔385a和3831a。其中，数据线VD通过至少一个第一连接通孔381a与半导体层500中的数据写入晶体管T2的源极区域电连接。第一电源信号线VDD1通过至少一个第一连接通孔382a与半导体层500中对应的第一发光控制晶体管T4的源极区域电连接。桥接部341a的一端通过至少一个第一连接通孔384a与半导体层500中对应的阈值补偿晶体管T3的漏极区域电连接。桥接部341a的另一端通过至少一个第二连接通孔385a与第三导电层300中的驱动晶体管T1 的栅极(即存储电容CST的第二极CC2a)电连接。桥接部342a的一端通过至少一个第三连接通孔386a与第一复位信号线VINIT1电连接，桥接部342a的另一端通过至少一个第一连接通孔387a与半导体层500中的第二复位晶体管T7的漏极区域电连接。桥接部343a通过至少一个第一连接通孔388a与半导体层500中的第二发光控制晶体管T5的漏极区域电连接。第一电源信号线VDD1通过至少一个第三连接通孔3832a与第四导电层400中的存储电容CST的第一极CC1a电连接。第一电源信号线VDD1还通过至少一个第四连接通孔3831a与第二导电层200中的第二电源信号线VDD2电连接。转接部351a通过贯穿至少一个第四连接通孔385a与桥接部343a电连接。第一电源信号线VDD1还通过至少一个第一连接通孔389a与遮光部344a电连接，以对遮光部344a输入固定电压。
示例性地，子像素中的第一连接通孔381a、382a、384a、387a以及388a可以分别设置一个，也可以分别设置两个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，子像素中的第二连接通孔385a可以设置一个，也可以设置两个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，子像素中的第三连接通孔386a、3832a以及389a可以分别设置一个，也可以分别设置两个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，子像素中的第四连接通孔385a和3831a可以分别设置一个，也可以分别设置两个等。在实际应用中，可以根据实际应用环境的需求进行设计确定，在此不作限定。
进一步地，在第二导电层200背离衬底基板010一侧依次设置有平坦化层、第一发光电极所在层、像素限定层、发光功能层以及第二发光电极所在层。并且，第一发光电极通过贯穿平坦化层的过孔与转接部351a电连接。
例如，如图3至图4e所示，在第二方向F2上，第一扫描线GA1、第二 扫描线GA2、第一复位信号线VINIT1均位于的驱动晶体管T1的栅极的第一侧，发光控制线EM位于驱动晶体管T1的第二侧。
在具体实施时，在整个显示基板上，第一电源信号线VDD1和第二电源信号线VDD2电性连接，从而使第一电源端VDD电连接的信号线的电阻较小、压降较低，进而可以提高第一电源端VDD提供的电源电压的稳定性。
例如，第一扫描线GA1、第二扫描线GA2、发光控制线EM可以位于同一层(即第三导电层300)。第一电源信号线VDD1和数据线VD位于同一层(即第一导电层100)。
需要说明的是，每个子像素spx中的晶体管的位置排布关系不限于图3至图4e所示的示例，根据实际应用需求，可以具体设置上述晶体管的位置。
需要说明的是，第一方向F1可以为子像素的行方向，第二方向F2可以为子像素的列方向。或者，第一方向F1也可以为子像素的列方向，第二方向F2为子像素的行方向。在实际应用中，可以根据实际应用需求进行设置，在此不作限定。
在具体实施时，在本公开实施例中，显示区可以包括多条数据线、多条扫描线、多条发光控制线。第一非显示区可以包括多条数据传输线、多条扫描传输线以及多条发光传输线：其中，多条数据线中的至少一条与多条数据传输线中的至少一条电连接，多条扫描线中的至少一条与多条扫描传输线中的至少一条电连接，多条发光控制线中的至少一条与多条发光传输线中的至少一条电连接。
在具体实施时，在本公开实施例中，如图6所示，第一导电层100中的多条数据线可以包括数据线VD1和数据线VD2。其中，数据线VD1和VD2均位于显示区A1内，且数据线VD1和VD2分别沿第一方向F1排列。数据线VD1沿第二方向F2由显示区A1的下侧延伸至显示区A1的上侧且沿第一方向F1排列。数据线VD2沿第二方向F2延伸且被缺口区A2分割开，也就是说，数据线VD2可以由显示区A1的下侧延伸至第一非显示区A3，也可以由显示区A1的上侧延伸至第一非显示区A3。
在具体实施时，在本公开实施例中，如图6至图8a所示，第一导电层100还可以包括：间隔设置的多条第一数据传输线711。第二导电层200还可以包括：间隔设置的多个第一数据连接部211。以及层间绝缘层640具有多个第一数据通孔。并且，多个第一数据连接部211中的至少一个通过第一数据通孔分别与多条数据线VD2中的至少一个和多条第一数据传输线711中的至少一个电连接。这样可以使第一导电层100中的数据线和第一数据传输线711通过第二导电层200中的第一数据连接部211相互电连接。需要说明的是，同一列子像素spx对应的且被缺口区A2分割开的数据线VD2可以通过第一数据传输线711相互电连接，以形成为该列子像素spx输入数据信号的一条数据线。
本公开实施例提供的上述显示面板，通过将第一数据连接部211设置在第二导电层200中，从而可以使第一导电层100中的数据线VD2和第一数据传输线711通过第二导电层200中的第一数据连接部211相互电连接。这样不仅可以使同一列子像素spx对应的且被缺口区A2分割开的数据线VD2进行电连接，还可以使第一数据连接部211对第三导电层300和第四导电层400的干扰减小，从而可以提高信号稳定性，提高显示效果。
并且，由于第一导电层100中设置有较多的桥接部，若将第一数据连接部211也设置在第一导电层100，那么第一导电层100中用于设置桥接部、数据线以及第一电源信号线的面积将会减少，这样有可能导致桥接部、数据线、第一电源信号线以及第一数据连接部211出现短路的情况。因此，本公开实施例提供的上述显示面板还可以降低短路风险，进一步提高显示面板的稳定性，提高显示面板的竞争力。
在具体实施时，在本公开实施例中，如图6至图8a所示，多条第一数据传输线711位于第一非显示区A3。示例性地，多条第一数据传输线711可以呈弧形绕缺口区A2设置。层间绝缘层640可以具有：多个第一数据通孔641-1和多个第一数据通孔641-2。其中，一个第一数据连接部211对应至少一个第一数据通孔641-1和至少一个第一数据通孔641-2。并且，第一数据连接部211 的一端可以通过对应的第一数据通孔641-1与数据线VD2电连接，第一数据连接部211的另一端可以通过对应的第一数据通孔641-2与第一数据传输线711电连接。在实际应用中，可以使一个第一数据连接部211对应一个、两个、三个或更多个第一数据通孔641-1。也可以使一个第一数据连接部211对应一个、两个、三个或更多个第一数据通孔641-2。这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6至图8a所示，多条数据线VD2可以包括多条第一数据线121和多条第二数据线122。示例性地，沿第一方向F1，可以使第一数据线121和第二数据线122交替排列。例如，在沿第一方向F1的箭头所指的方向上，多条数据线VD2中的第奇数条可以作为第一数据线121，多条数据线VD2中的第偶数条可以作为第二数据线122。当然，第一数据线121和第二数据线122也可以根据实际应用环境的需求来进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6至图8a所示，一条第一数据线121可以通过第一数据连接部211与一条第一数据传输线711电连接。示例性地，一条第一数据线121可以对应一个第一数据连接部211与一条第一数据传输线711。.并且，该第一数据线121可以通过对应第一数据连接部211与对应的第一数据传输线711电连接，以实现同一列子像素spx对应的且被缺口区A2分割开的第一数据线121可以通过应的第一数据连接部211与第一数据传输线711实现电连接。
在具体实施时，在本公开实施例中，如图6至图8a所示，第二导电层200还可以包括：与第一数据连接部211间隔设置的多条第二数据传输线712；层间绝缘层640还可以包括：多个第二数据通孔642。其中，一条第二数据线122通过第二数据通孔642与一条第二数据传输线712电连接。示例性地，可以使一条第二数据线122对应一条第二数据传输线712，一条第二数据传输线712对应至少一个第二数据通孔642，从而可以使第二数据线122通过对应的第二数据通孔642与对应第二数据线122传输线电连接。在实际应用中，可 以使一个第二数据传输线712对应一个、两个、三个或更多个第二数据通孔642。这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6至图7b所示，多条第二数据传输线712位于第一非显示区A3。示例性地，多条第二数据传输线712可以呈弧形绕缺口区A2设置。进一步地，可以使第二数据传输线712在衬底基板010的正投影和第一数据传输线711在衬底基板010的正投影间隔设置。示例性地，如图6至图7b所示，可以使第一数据传输线711在衬底基板010的正投影和第二数据传输线712在衬底基板010的正投影交替设置。由于第一数据传输线711和第二数据传输线712位于不同平面，这样可以增大第一数据传输线711和第二数据传输线712之间的距离，进一步降低第一数据传输线711和第二数据传输线712之间的信号干扰。
示例性地，为了降低占用面积，也可以使一条第二数据传输线712在衬底基板010的正投影和一条第一数据传输线711在衬底基板010的正投影具有交叠区域。进一步地，可以使一条第二数据传输线712在衬底基板010的正投影和一条第一数据传输线711在衬底基板010的正投影部分重叠，这样可以最大程度的降低第一数据传输线711和第二数据传输线712的占用面积，进而降低第一非显示区A3的占用面积。
在具体实施时，在本公开实施例中，如图6至图7b所示，多条扫描线可以包括位于显示区A1的多条第一扫描线GA1和多条第二扫描线GA2，即第三导电层300可以包括位于显示区A1的多条第一扫描线GA1和多条第二扫描线GA2；其中，一行子像素spx对应一条第一扫描线GA1和一条第二扫描线GA2。并且，每相邻两行子像素spx中的第q-1行子像素G(q-1)对应的第二扫描线GA2与第q行子像素G(q)对应的第一扫描线GA1电连接。例如，图7a与图7b示出了沿第二方向F2排列的四行子像素spx，沿与第二方向F2的箭头相反的方向，可以具有第q-1行子像素G(q-1)、第q行子像素G(q)、第q+1行子像素G(q+1)以及第q+2行子像素G(q+2)，第q-1行子像素G(q-1)对应的第二扫描线GA2与第q行子像素G(q)对应的第一 扫描线GA1电连接，第q行子像素G(q)对应的第二扫描线GA2与第q+1行子像素G(q+1)对应的第一扫描线GA1电连接。其余同理，以此类推，在此不作赘述。需要说明的是，q为整数，图7a与图7b仅是示出了显示面板中的部分行子像素spx。
在具体实施时，在本公开实施例中，如图6至图8a所示，第一导电层100还可以包括：与数据线和第一数据传输线711绝缘且间隔设置的多个第一扫描连接部131；其中，第q-1行子像素G(q-1)对应的第二扫描线GA2与第q行子像素G(q)对应的第一扫描线GA1通过至少一个第一扫描连接部131电连接。以及，第二绝缘层还可以包括多个第一扫描通孔811和多个第二扫描通孔812；其中，第一扫描连接部131的第一端通过多个第一扫描通孔811中的至少一个与对应的第一扫描线GA1电连接，第一扫描连接部131的第二端通过多个第二扫描通孔812中的至少一个与对应的第二扫描线GA2电连接。示例性地，可以使相互电连接的第一扫描线GA1和第二扫描线GA2对应一个第一扫描连接部131。一个第一扫描连接部131可以对应至少一个第一扫描通孔811以及至少一个第二扫描通孔812。例如，一个第一扫描连接部131可以对应一个第一扫描通孔811以及一个第二扫描通孔812。第q-1行子像素G(q-1)对应的第二扫描线GA2与第q行子像素G(q)对应的第一扫描线GA1电连接，该电连接的第二扫描线GA2与第一扫描线GA1对应一个第一扫描连接部131，且该第一扫描连接部131的第一端通过对应的第一扫描通孔811与对应的第一扫描线GA1电连接，第一扫描连接部131的第二端通过对应的第二扫描通孔812与对应的第二扫描线GA2电连接。第q行子像素G(q)对应的第二扫描线GA2与第q+1行子像素G(q+1)对应的第一扫描线GA1电连接，该电连接的第二扫描线GA2与第一扫描线GA1对应一个第一扫描连接部131，且该第一扫描连接部131的第一端通过对应的第一扫描通孔811与对应的第一扫描线GA1电连接，第一扫描连接部131的第二端通过对应的第二扫描通孔812与对应的第二扫描线GA2电连接。其余同理，以此类推，在此不作赘述。需要说明的是，第二绝缘层可以包括：第二栅绝缘层620和层间介质层 630。
在具体实施时，在本公开实施例中，如图6至图8a所示，可以使所有行子像素spx包括第一类行子像素spx。第一类行子像素spx中的至少一行子像素spx对应至少一个第一数据连接部211。示例性地，可以使第一类行子像素spx包括所有行子像素spx中的部分行。并且，可以使第一类行子像素spx中的每一行子像素spx对应至少一个第一数据连接部211。例如，可以使第一类行子像素spx中的部分行子像素spx中的每一行对应一个第一数据连接部211，其余行子像素spx中的每一行对应两个第一数据连接部。示例性地，第一类行子像素spx可以包括图7a与图7b中所示的第q行子像素G(q)。
在具体实施时，在本公开实施例中，如图6至图8a所示，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及第一数据连接部211，第一数据连接部211在衬底基板010的正投影与第一扫描线GA1对应的第一扫描连接部131和第二扫描线GA2对应的第一扫描连接部131在衬底基板010的正投影不交叠。这样可以使第一数据连接部211与第一扫描连接部131间隔设置，降低短路风险。
在具体实施时，在本公开实施例中，如图6至图8a所示，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及第一数据连接部211，第一数据连接部211在衬底基板010的正投影位于第一扫描线GA1对应的第一扫描通孔811和第二扫描线GA2对应的第二扫描通孔812在衬底基板010的正投影之间。示例性地，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及第一数据连接部211，第一扫描线GA1对应的第一扫描通孔811在衬底基板010的正投影的中心和第二扫描线GA2对应的第二扫描通孔812在所述衬底基板的正投影的中心之间的连线与第一数据连接部211在衬底基板010的正投影交叠。
需要说明的是，上述正投影的中心可以为该正投影的几何中心。然而，在实际制造工艺中，所形成的上述各结构的形状一般会与上述设计的规则形状有一定的偏差。此外，实际制造的上述结构的形状还可能会与设计的形状 有其他的变化。因此，在本公开的实施例中，上述正投影的中心可以与上述正投影的几何中心有一定的偏移量。
在具体实施时，在本公开实施例中，如图6至图8a所示，第二导电层200还可以包括：多个第二数据连接部212；其中，一条第二数据传输线712直接电连接至少一个第二数据连接部212，且第二数据连接部212通过第二数据通孔642与一条第二数据线122电连接。示例性地，一条第二数据线122对应一条第二数据传输线712和一个第二数据连接部212，一个第二数据连接部212对应至少一个第二数据通孔642。并且，该第二数据连接部212直接电连接对应的第二数据传输线712，且该第二数据连接部212通过对应的第二数据通孔642与对应的第二数据线122电连接。示例性地，在实际应用中，可以使一个第二数据连接部212对应一个、两个、三个或更多个第二数据通孔642。这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图7a与图7b所示，可以使第一数据连接部211和第二数据连接部212在沿第一方向F1延伸的直线上的投影交替排列。由于第一数据线121和第二数据线122沿第一方向F1交替排列，通过使第一数据连接部211和第二数据连接部212在沿第一方向F1延伸的直线上的投影交替排列，这样可以使与第一数据线121电连接的第一数据连接部211和与第二数据线122电连接的第二数据连接部212相对应设置，从而可以降低信号干扰。
在具体实施时，在本公开实施例中，如图6至图8a所示，可以使第一数据连接部211和第二数据连接部212在衬底基板010的正投影分别与第一扫描连接部131、第一扫描线GA1、第二扫描线GA2以及发光控制线EM在衬底基板010的正投影不交叠。
在具体实施时，在本公开实施例中，如图7a与图7b所示，可以使相邻两行子像素spx对应的发光控制线电连接。示例性地，第q-1行子像素G(q-1)与第q-2行子像素对应的发光控制线电连接，第q行子像素G(q)和第q+1行子像素G(q+1)对应的发光控制线电连接，第q+2行子像素G(q+2)与 第q+3行子像素对应的发光控制线电连接。其余同理，以此类推，在此不作赘述。
在具体实施时，在本公开实施例中，如图7a、图7b与图8a所示，第一导电层100还可以包括：与数据线和第一数据传输线711绝缘且间隔设置的多个第一发光连接部141；其中，相互电连接的发光控制线对应至少一个第一发光连接部141。第二绝缘层可以包括多个第一发光通孔821和多个第二发光通孔822。以及，第一发光连接部141的第一端通过多个第一发光通孔821中的至少一个与对应的一条发光控制线电连接，第一发光连接部141的第二端通过多个第二发光通孔822中的至少一个与对应的另一条发光控制线电连接。示例性地，可以使相互电连接的发光控制线对应一个第一发光连接部141，一个第一发光连接部141对应至少一个第一发光通孔821和至少一个第二发光通孔822。并且，第一发光连接部141的第一端通过对应的第一发光通孔821与对应的发光控制线电连接，第一发光连接部141的第二端通过对应的第二发光通孔822与对应的另一条发光控制线电连接。例如，第一发光连接部141的第一端通过对应的第一发光通孔821与第q行子像素G(q)对应的发光控制线电连接，以及第一发光连接部141的第二端通过对应的第二发光通孔822与第q+1行子像素G(q+1)对应的发光控制线电连接。示例性地，一个第一发光连接部141可以对应一个、两个、三个或更多个第一发光通孔821。一个第一发光连接部141可以对应一个、两个、三个或更多个第二发光通孔822。这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图7a至图8a所示，第三导电层300还可以包括位于第一非显示区A3的多条第一扫描传输线311和多条第一发光传输线321；其中，第一扫描传输线311和第一发光传输线321间隔设置。示例性地，可以使第一扫描传输线311在衬底基板010的正投影和第一发光传输线321在衬底基板010的正投影间隔设置。进一步地，可以使第一扫描传输线311在衬底基板010的正投影和第一发光传输线321在衬底基板010的正投影交替设置。进一步地，可以使第一扫描传输线311和第一发光传输 线321呈弧形绕第一非显示区A3设置。当然，这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图7a至图8a所示，部分相互电连接的第一扫描线GA1和第二扫描线GA2直接对应电连接一条第一扫描传输线311；且部分相互电连接的发光控制线直接电连接一条第一发光传输线321。这样可以使第三导电层300中的第一扫描线GA1直接与第一扫描传输线311电连接，以及使发光控制线直接与第一发光传输线321电连接，从而可以使这些信号线的设计难度降低。
在具体实施时，在本公开实施例中，如图7a至图8a所示，第四导电层400还可以包括位于第一非显示区A3的多条第二扫描传输线411和多条第二发光传输线421；其中，第二扫描传输线411和第二发光传输线421间隔设置。示例性地，可以使第二扫描传输线411在衬底基板010的正投影和第二发光传输线421在衬底基板010的正投影间隔设置。进一步地，可以使第二扫描传输线411在衬底基板010的正投影和第二发光传输线421在衬底基板010的正投影交替设置。进一步地，可以使第二扫描传输线411和第二发光传输线421呈弧形绕第一非显示区A3设置。当然，这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图7a至图8a所示，层间介质层630还可以包括多个第三扫描通孔813和多个第三发光通孔823。除上述部分相互电连接的第一扫描线GA1和第二扫描线GA2之外，其余部分相互电连接的第一扫描线GA1和第二扫描线GA2对应一条第二扫描传输线411，且该其余部分相互电连接的第一扫描线GA1对应的第一扫描连接部131还通过第三扫描通孔813与第二扫描传输线411电连接。这样可以使同一行子像素spx对应的且被缺口区A2分割开的第一扫描线GA1能够通过第二扫描传输线411进行电连接。示例性地，一条第二扫描传输线411可以对应一个、两个、三个或更多个第三扫描通孔813。这些可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图7a至图8a所示，除上述部分相互电连接的发光控制线之外，其余部分相互电连接的发光控制线对应一条第二发光传输线421，且第一发光连接部141还通过第三发光通孔823与第二发光传输线421电连接。这样可以使同一行子像素spx对应的且被缺口区A2分割开的发光控制线能够通过第二发光传输线421进行电连接。示例性地，一条第二发光传输线421可以对应一个、两个、三个或更多个第三发光通孔823。这些可以根据实际应用的需求进行设计确定，在此不作限定。
并且，通过将第一扫描传输线311、第二扫描传输线411、第一发光传输线321以及第二发光传输线421均设置在第一非显示区A3。以及将第一扫描传输线311与第一发光传输线321设置在第三导电层300，将第二扫描传输线411与第二发光传输线421设置在第四导电层400，从而可以降低第一扫描传输线311、第二扫描传输线411、第一发光传输线321以及第二发光传输线421的信号干扰。
示例性地，可以使第一扫描传输线311在衬底基板010的正投影与部分第一数据传输线711在衬底基板010的正投影具有交叠区域。进一步地，可以使一条第一扫描传输线311在衬底基板010的正投影与一条第一数据传输线711在衬底基板010的正投影部分重叠。示例性地，可以使第一发光传输线321在衬底基板010的正投影与其余部分第一数据传输线711在衬底基板010的正投影具有交叠区域。进一步地，可以使一条第一发光传输线321在衬底基板010的正投影与其余部分中的一条第一数据传输线711在衬底基板010的正投影部分重叠。这样可以降低第一非显示区的占用面积。
示例性地，可以使第二扫描传输线411在衬底基板010的正投影与部分第二数据传输线712在衬底基板010的正投影具有交叠区域。进一步地，可以使一条第二扫描传输线411在衬底基板010的正投影与一条第二数据传输线712在衬底基板010的正投影部分重叠。示例性地，可以使第二发光传输线421在衬底基板010的正投影与其余部分第二数据传输线712在衬底基板010的正投影具有交叠区域。进一步地，可以使一条第二发光传输线421在衬 底基板010的正投影与其余部分中的一条第二数据传输线712在衬底基板010的正投影部分重叠。这样可以降低第一非显示区的占用面积。
在具体实施时，在本公开实施例中，如图7a至图8a所示，所有行子像素spx也可以包括第二类行子像素spx；第二类行子像素spx与第一类行子像素spx不同。并且，第二类行子像素spx中的至少一行子像素spx对应至少一个第二数据连接部212。示例性地，第二类行子像素spx中的每一行子像素spx对应至少一个第二数据连接部212。示例性地，第二类行子像素spx中的每一行子像素spx对应一个第二数据连接部212。需要说明的是，第二类行子像素spx可以为显示面板中的部分行，其具体位置可以根据实际应用环境的需求进行设计确定，在此不作限定。示例性地，第二类行子像素spx可以包括图7b中的第一行子像素和第三行子像素。
在具体实施时，在本公开实施例中，如图7a至图8a所示，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及第二数据连接部212，第二数据连接部212在衬底基板010的正投影与第一扫描线GA1对应的第一扫描连接部131和第二扫描线GA2对应的第一扫描连接部131在衬底基板010的正投影不交叠。这样可以使第二数据连接部212与第一扫描连接部131间隔设置，降低短路风险。
在具体实施时，在本公开实施例中，如图7a至图8a所示，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及第二数据连接部212，第二数据连接部212在衬底基板010的正投影位于第一扫描线GA1对应的第一扫描通孔811和第二扫描线GA2对应的第二扫描通孔812在衬底基板010的正投影之间。示例性地，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及第二数据连接部212，第一扫描线GA1对应的第二扫描通孔812在衬底基板010的正投影的中心和第二扫描线GA2对应的第二扫描通孔812在所述衬底基板的正投影的中心之间的连线与第二数据连接部212在衬底基板010的正投影交叠。
在具体实施时，在本公开实施例中，如图7a至图8a所示，第二数据连接 部212在衬底基板010的正投影分别与第一发光连接部141在衬底基板010的正投影、第一扫描连接部131在衬底基板010的正投影、第一扫描线GA1在衬底基板010的正投影、第二扫描线GA2在衬底基板010的正投影不交叠。
在具体实施时，在本公开实施例中，如图7a至图8a所示，针对同一行子像素spx对应的发光控制线EM、第二扫描线GA2以及第二数据连接部212，第二数据连接部212在衬底基板010的正投影位于第二扫描线GA2对应的第二扫描通孔812和发光控制线对应的第一发光通孔821在衬底基板010的正投影之间。
由于在实际应用中，子像素spx中的晶体管一般需要电性连接，这些晶体管的电性连接与其晶体管特性相关，因此晶体管的电性连接均匀，可以使晶体管的特性均匀。一般采用湿法刻蚀方法，通过刻蚀液来制备进行电性连接的通孔。然而，在刻蚀显示区A1边缘子像素spx的通孔时，显示区A1边缘外不用刻蚀通孔，从而使得显示区A1边缘子像素spx的通孔的刻蚀程度与显示区A1内部子像素spx的通孔的刻蚀程度不同，从而导致显示区A1边缘子像素spx中的晶体管和内部子像素spx中的晶体管的特性不均一。为了提高晶体管的特征均一性，在具体实施时，在本公开实施例中，显示面板及具有位于第一导电层与衬底基板之间的目标绝缘层，位于目标绝缘层与衬底基板之间的功能层，多个子像素中的至少一个可以包括：连接通孔；其中，连接通孔贯穿目标绝缘层，且第一导电层通过连接通孔与功能层电连接。以及第一非显示区包括至少一个辅助通孔：其中，辅助通孔贯穿目标绝缘层且辅助通孔未填充导电材料。并且，第一非显示区中，多条数据传输线、多条扫描传输线以及多条发光传输线中的至少两种传输线围绕形成辅助区域，辅助通孔位于辅助区域内。进一步地，示例性地，也可以使相邻两个辅助通孔之间的间距小于或大致等于相邻两个连接通孔之间的间距。
由于在实际应用中，第一连接通孔用于实现子像素spx中晶体管的电性连接，这些晶体管的电性连接与其晶体管特性相关，因此晶体管的电性连接均匀，可以使晶体管的特性均匀。一般采用湿法刻蚀方法，通过刻蚀液来制备 第一连接通孔。然而，在刻蚀显示区A1边缘子像素spx的第一连接通孔时，显示区A1边缘外不用刻蚀第一连接通孔，从而使得显示区A1边缘子像素spx的第一连接通孔的刻蚀程度与显示区A1内部子像素spx的第一连接通孔的刻蚀程度不同，从而导致显示区A1边缘子像素spx中的晶体管和内部子像素spx中的晶体管的特性不均一。为了提高晶体管的特征均一性，在具体实施时，在本公开实施例中，功能层可以包括半导体层；目标绝缘层可以包括：第一栅绝缘层、第二栅绝缘层以及层间介质层；连接通孔可以包括第一连接通孔；辅助通孔可以包括第一辅助通孔，第一辅助通孔贯穿第一栅绝缘层、第二栅绝缘层以及层间介质层。示例性地，如图7a至图8c所示，显示面板还可以包括位于第一非显示区A3中的至少一个第一辅助通孔911。其中，第一辅助通孔911贯穿第一栅绝缘层610、第二栅绝缘层620以及层间介质层630，且第一辅助通孔911未填充导电材料。并且，第一非显示区A3中，多条数据传输线、多条扫描传输线以及多条发光传输线中的至少两种传输线可以围绕形成辅助区域FB，第一辅助通孔911可以位于辅助区域FB内。这样可以在显示区A1边缘外，即第一非显示区A3中设置第一辅助通孔911，并且第一辅助通孔911与第一连接通孔贯穿的绝缘层相同。从而使得在第一非显示区A3中也刻蚀第一辅助通孔911，进而可以使显示边缘子像素spx中刻蚀的第一连接通孔与内部子像素spx中刻蚀的第一连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
在具体实施时，可以在第一辅助通孔911中填充绝缘材料。例如，可以在第一辅助通孔911中填充层间绝缘层640的材料。这样可以在制备层间绝缘层640时，直接将第一辅助通孔911进行填充，从而可以提高层间绝缘层640的平坦性。
在具体实施时，辅助区域FB具体采用哪几条传输线围绕形成可以根据实际应用需求进行设计确定，在此不作限定。
需要说明的是，由于在对半导体层进行图案化时，第一非显示区A3中的半导体层并未被刻蚀掉，因此第一非显示区A3中还保留有半导体层，如图 8b与图8c所示。这样使得第一辅助通孔911在垂直于衬底基板所在平面的方向上的深度与第一连接通孔在垂直于衬底基板所在平面的方向上的深度大致相同。这样可以使刻蚀液将第一辅助通孔911和第一连接通孔刻蚀的程度大致相同，从而进一步提高晶体管的特性均一性。
示例性地，在具体实施时，在本公开实施例中，可以在第一非显示区A3中设置多个第一辅助通孔911。例如，可以使第一辅助通孔911的分布密度大致等于第一连接通孔的分布密度。这样可以使显示边缘子像素spx中刻蚀的第一连接通孔与内部子像素spx中刻蚀的第一连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
示例性地，在具体实施时，在本公开实施例中，也可以使第一辅助通孔911的分布密度小于第一连接通孔的分布密度。由于第一非显示区A3中还设置其他走线或连接部，通过降低第一辅助通孔911的分布密度可以降低所有第一辅助通孔911这个整体的占用面积，降低第一非显示区A3的占用面积。并且，还通过设置了第一辅助通孔911，从而可以使显示边缘子像素spx中刻蚀的第一连接通孔与内部子像素spx中刻蚀的第一连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
需要说明的是，第一辅助通孔911的分布密度可以为单位面积中第一辅助通孔911的数量。第一连接通孔的分布密度可以为单位面积中第一连接通孔的数量。在实际应用中，第一辅助通孔911和第一连接通孔的分布密度可以根据实际应用环境的需求来设计确定，在此不作限定。
示例性地，在具体实施时，在本公开实施例中，可以使相邻两个第一辅助通孔之间的间距大致等于相邻两个第一连接通孔之间的间距。这样可以不用额外的设计第一辅助通孔之间的间距，可以采用第一连接通孔之间的间距进行设计即可。当然，也可以使相邻两个第一辅助通孔之间的间距小于相邻两个第一连接通孔之间的间距。这样可以将第一辅助通孔设置的较为紧凑，降低第一非显示区的占用面积。
示例性地，在具体实施时，在本公开实施例中，如图7a至图8c所示，第 一辅助通孔911在衬底基板010的正投影与半导体层、第一导电层100、第三导电层300以及第四导电层400在衬底基板010的正投影不交叠。这样可以降低刻蚀第一辅助通孔911时，对导电层和半导体层的影响。
由于在实际应用中，第二连接通孔也用于实现子像素spx中晶体管的电性连接，这些晶体管的电性连接与其晶体管特性相关，因此晶体管的电性连接均匀，可以使晶体管的特性均匀。一般采用湿法刻蚀方法，通过刻蚀液来制备第二连接通孔。然而，显示区A1在刻蚀显示区A1边缘子像素spx的第二连接通孔时，显示区A1边缘外不用刻蚀第二连接通孔，从而使得显示区A1边缘子像素spx的第二连接通孔的刻蚀程度与显示区A1内部子像素spx的第二连接通孔的刻蚀程度不同，从而导致显示区A1边缘子像素spx中的晶体管和内部子像素spx中的晶体管的特性不均一。为了提高晶体管的特征均一性，在具体实施时，在本公开实施例中，功能层包括第三导电层；目标绝缘层包括：第二栅绝缘层与层间介质层；连接通孔包括第二连接通孔；辅助通孔包括第二辅助通孔，第二辅助通孔贯穿第二栅绝缘层与层间介质层。示例性地，如图7b与图8c所示，显示面板还可以包括位于第一非显示区A3中的至少一个第二辅助通孔912；其中，第二辅助通孔912贯穿第二栅绝缘层620以及层间介质层630，且第二辅助通孔912未填充导电材料。并且，第二辅助通孔912也可以位于辅助区域FB内。在具体实施时，可以在第二辅助通孔912中填充绝缘材料。例如，可以在第二辅助通孔912中填充层间绝缘层640的材料。这样可以在制备层间绝缘层640时，直接将第二辅助通孔912进行填充，从而可以提高层间绝缘层640的平坦性。
示例性地，在具体实施时，在本公开实施例中，可以在第一非显示区A3中设置多个第二辅助通孔912。例如，可以使第二辅助通孔912的分布密度大致等于第二连接通孔的分布密度。这样可以使显示边缘子像素spx中刻蚀的第二连接通孔与内部子像素spx中刻蚀的第二连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
示例性地，在具体实施时，在本公开实施例中，也可以使第二辅助通孔 912的分布密度小于第二连接通孔的分布密度。由于第一非显示区A3中还设置其他走线或连接部，通过降低第二辅助通孔912的分布密度可以降低所有第二辅助通孔912这个整体的占用面积，降低第一非显示区A3的占用面积。并且，还通过设置了第二辅助通孔912，从而可以使显示边缘子像素spx中刻蚀的第二连接通孔与内部子像素spx中刻蚀的第一连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
需要说明的是，第二辅助通孔912的分布密度可以为单位面积中第二辅助通孔912的数量。第二连接通孔的分布密度可以为单位面积中第二连接通孔的数量。在实际应用中，第二辅助通孔912和第二连接通孔的分布密度可以根据实际应用环境的需求来设计确定，在此不作限定。
需要说明的是，由于在对第三导电层300进行图案化时，第一非显示区A3中的第三导电层300会被刻蚀掉，因此第一非显示区A3中不会保留有第三导电层300，如图8c所示。这样使得第二辅助通孔912在垂直于衬底基板所在平面的方向上的深度大于第二连接通孔在垂直于衬底基板所在平面的方向上的深度。
示例性地，在具体实施时，在本公开实施例中，可以使相邻两个第二辅助通孔之间的间距大致等于相邻两个第二连接通孔之间的间距。这样可以不用额外的设计第二辅助通孔之间的间距，可以采用第二连接通孔之间的间距进行设计即可。当然，也可以使相邻两个第二辅助通孔之间的间距小于相邻两个第二连接通孔之间的间距。这样可以将第二辅助通孔设置的较为紧凑，降低第二非显示区的占用面积。
示例性地，在具体实施时，在本公开实施例中，如图7b所示，第二辅助通孔912在衬底基板010的正投影与第一导电层100、第三导电层300以及第四导电层400在衬底基板010的正投影不交叠。这样可以降低刻蚀第二辅助通孔912时，对导电层和半导体层的影响。
由于在实际应用中，第三连接通孔也用于实现子像素spx中晶体管的电性连接，这些晶体管的电性连接与其晶体管特性相关，因此晶体管的电性连接 均匀，可以使晶体管的特性均匀。一般采用湿法刻蚀方法，通过刻蚀液来制备第三连接通孔。然而，在刻蚀显示区A1边缘子像素spx的第三连接通孔时，显示区A1边缘外不用刻蚀第三连接通孔，从而使得显示区A1边缘子像素spx的第三连接通孔的刻蚀程度与显示区A1内部子像素spx的第三连接通孔的刻蚀程度不同，从而导致显示区A1边缘子像素spx中的晶体管和内部子像素spx中的晶体管的特性不均一。为了提高晶体管的特征均一性，在具体实施时，在本公开实施例中，功能层包括第四导电层；目标绝缘层包括：层间介质层；连接通孔包括第三连接通孔；辅助通孔包括第三辅助通孔，第三辅助通孔贯穿层间介质层。示例性地，如图7b与图8c所示，显示面板还可以包括位于第一非显示区A3中的至少一个第三辅助通孔913；第三辅助通孔913贯穿层间介质层630，且第三辅助通孔913未填充导电材料。并且，第三辅助通孔913也可以位于辅助区域FB内。在具体实施时，可以在第三辅助通孔913中填充绝缘材料。例如，可以在第三辅助通孔913中填充层间绝缘层640的材料。这样可以在制备层间绝缘层640时，直接将第三辅助通孔913进行填充，从而可以提高层间绝缘层640的平坦性。
示例性地，在具体实施时，在本公开实施例中，可以在第一非显示区A3中设置多个第三辅助通孔913。例如，可以使第三辅助通孔913的分布密度大致等于第三连接通孔的分布密度。这样可以使显示边缘子像素spx中刻蚀的第三连接通孔与内部子像素spx中刻蚀的第三连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
示例性地，在具体实施时，在本公开实施例中，也可以使第三辅助通孔913的分布密度小于第三连接通孔的分布密度。由于第一非显示区A3中还设置其他走线或连接部，通过降低第三辅助通孔913的分布密度可以降低所有第三辅助通孔913这个整体的占用面积，降低第一非显示区A3的占用面积。并且，还通过设置了第三辅助通孔913，从而可以使显示边缘子像素spx中刻蚀的第三连接通孔与内部子像素spx中刻蚀的第一连接通孔的刻蚀效果均一，提高晶体管的特性均一性。
需要说明的是，第三辅助通孔913的分布密度可以为单位面积中第三辅助通孔913的数量。第三连接通孔的分布密度可以为单位面积中第三连接通孔的数量。在实际应用中，第三辅助通孔913和第三连接通孔的分布密度可以根据实际应用环境的需求来设计确定，在此不作限定。
需要说明的是，由于在对第四导电层400进行图案化时，第一非显示区A3中的第四导电层400会被刻蚀掉，因此第一非显示区A3中不会保留有第四导电层400，如图8c所示。这样使得第三辅助通孔913在垂直于衬底基板所在平面的方向上的深度大于第三连接通孔在垂直于衬底基板所在平面的方向上的深度。
示例性地，在具体实施时，在本公开实施例中，可以使相邻两个第三辅助通孔之间的间距大致等于相邻两个第三连接通孔之间的间距。这样可以不用额外的设计第三辅助通孔之间的间距，可以采用第三连接通孔之间的间距进行设计即可。当然，也可以使相邻两个第三辅助通孔之间的间距小于相邻两个第三连接通孔之间的间距。这样可以将第三辅助通孔设置的较为紧凑，降低第一非显示区的占用面积。
示例性地，在具体实施时，在本公开实施例中，如图7b所示，第三辅助通孔913在衬底基板010的正投影与第一导电层100以及第四导电层400在衬底基板010的正投影不交叠。这样可以降低刻蚀第三辅助通孔913时，对导电层和半导体层的影响。
需要说明的是，图8a所示的，GA1-G(q)代表第q行子像素对应的第一扫描线。GA2-G(q)代表第q行子像素对应的第二扫描线。GA1-G(q+1)代表第q+1行子像素对应的第一扫描线。EM-G(q)代表第q行子像素对应的发光控制线。EM-G(q+1)代表第q+1行子像素对应的发光控制线。以下同理，不再进行赘述。
需要说明的是，由于工艺条件的限制或其他因素，上述各特征中的相同或等于并不能完全相同或等于，可能会有一些偏差，因此上述各特征之间的相同或等于关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述相同可以是在误差允许范围之内所允许的相同。
本公开实施例还提供了另一些显示面板，如图9a至图10c所示，其针对上述实施例中的部分实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中。如图9a至图10a所示，针对同一行子像素spx对应的第一扫描线GA1与第一数据连接部211以及采用第一数据连接部211电连接的第一数据线121和第一数据传输线711，第一数据连接部211在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影具有交叠区域，且第一数据线121和第一数据传输线711在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影不交叠。这样可以避免使该第一扫描线GA1与第一数据线121之间具有正对面积形成。并且，由于第一数据连接部211位于第二导电层200，可以使该第一扫描线GA1与第一数据连接部211之间的间距较大，这样可以使该第一扫描线GA1与第一数据连接部211之间的耦合电容降低较小，从而可以使得信号干扰降低，进而可以提高显示效果。
在具体实施时，在本公开实施例中。如图9a至图10a所示，针对同一行子像素spx对应的第一扫描线GA1与第一数据连接部211，第一数据连接部211的边缘区域在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影具有交叠区域。或者，针对同一行子像素spx对应的第一扫描线GA1与第一数据连接部211，第一数据连接部211的中心区域在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影具有交叠区域。
在具体实施时，在本公开实施例中。如图9a至图10a所示，第一类行子像素spx中的部分行子像素spx对应两个第一数据连接部。例如，图9a和图9b中的第q+2行子像素G(q+2)可以对应两个第一数据连接部：211a和211b。其中，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及两个第一数据连接部，可以使这两个第一数据连接部211a和211b在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影具有交叠区域，以及使这两个第一数据连接部211a和211b在衬底基板010的正投影与第二扫描 线GA2在衬底基板010的正投影不交叠。
在具体实施时，在本公开实施例中。如图9a至图10a所示，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及两个第一数据连接部a和211b，其中，这两个第一数据连接部中的第一个第一数据连接部211a在衬底基板010的正投影靠近第一扫描线GA1对应的第一扫描通孔811在衬底基板010的正投影。示例性地，这两个第一数据连接部中的第一个第一数据连接部211a相比第二个第一数据连接部211b，可以使第一个第一数据连接部211a在衬底基板010的正投影靠近第一扫描线GA1对应的第一扫描通孔811在衬底基板010的正投影。
在具体实施时，在本公开实施例中。如图9a至图10a所示，针对同一行子像素spx对应的第一扫描线GA1、第二扫描线GA2以及两个第一数据连接部，这两个第一数据连接部中的第二个第一数据连接部211b在衬底基板010的正投影靠近第二扫描线GA2对应的第二扫描通孔812在衬底基板010的正投影。示例性地，这两个第一数据连接部中的第二个第一数据连接部211b相比第一个第一数据连接部211a，可以使第二个第一数据连接部211b在衬底基板010的正投影靠近第二扫描线GA2对应的第二扫描通孔812在衬底基板010的正投影。
在具体实施时，在本公开实施例中。如图9a至图10a所示，针对同一行子像素spx对应的第一扫描线GA1与第二数据连接部212以及采用第二数据连接部212电连接的第二数据线122和第二数据传输线712，第二数据连接部212在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影具有交叠区域，且第二数据线122和第二数据传输线712在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影不交叠。
在具体实施时，在本公开实施例中。如图9a至图10a所示，针对对应两个第一数据连接部的一行子像素，该行子像素还对应一个第二数据连接部212。针对同一行子像素对应的第一扫描线GA1与第二数据连接部212以及采用第二数据连接部212电连接的第二数据线122和第二数据传输线712，第二数据 连接部212在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影具有交叠区域，且第二数据线122和第二数据传输线712在衬底基板010的正投影与第一扫描线GA1在衬底基板010的正投影不交叠。
需要说明的是，如图10b与图10c所示，显示面板中还设置了第一辅助通孔911、第二辅助通孔912以及第三辅助通孔913。并且，第一辅助通孔911、第二辅助通孔912以及第三辅助通孔913的设置方式可以参见上述实施方式，在此不作赘述。
本公开实施例还提供了又一些显示面板，如图11与图12所示，其针对上述实施例中的部分实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中。如图11与图12所示，第四导电层400还可以包括位于第一非显示区A3的多条第三扫描传输线413。并且，层间介质层630还可以包括多个第四扫描通孔814；相互电连接的第一扫描线GA1和第二扫描线GA2对应一条第三扫描传输线413，并且，第一扫描连接部131还通过第四扫描通孔814与第三扫描传输线413电连接。第三导电层300还可以包括位于第一非显示区A3的第三发光传输线423；其中，相互电连接的发光控制线直接电连接一条第三发光传输线423。这样可以在第三导电层300中设置第三发光传输线423，在第四导电层400中设置第三扫描传输线413。
示例性地，为了降低信号干扰，第三扫描传输线413在衬底基板010的正投影与第三发光传输线423在衬底基板010的正投影不交叠。进一步地，第三扫描传输线413在衬底基板010的正投影与第三发光传输线423在衬底基板010的正投影间隔设置。
进一步地，为了降低信号干扰，可以使第三扫描传输线413在衬底基板010的正投影与第二数据传输线712在衬底基板010的正投影具有交叠区域。进一步地，可以使第三扫描传输线413在衬底基板010的正投影与第二数据传输线712在衬底基板010的正投影部分重叠。由于第三扫描传输层位于第 四导电层400，第二数据传输线712位于第二导电层200，这样不仅可以使第三扫描传输线413与第二数据传输线712之间的耦合电容降低，还可以降低第一非显示区A3的占用面积。
进一步地，为了降低信号干扰，可以使第三发光传输线423在衬底基板010的正投影与第一数据传输线711在衬底基板010的正投影具有交叠区域。进一步地，可以使第三发光传输线423在衬底基板010的正投影与第一数据传输线711在衬底基板010的正投影部分重叠。由于第三发光传输线423位于第三导电层300，第一数据传输线711位于第一导电层100，这样不仅可以使第三发光传输层与第一数据传输线711之间的耦合电容降低，还可以降低第一非显示区A3的占用面积。
需要说明的是，第一辅助通孔911、第二辅助通孔912以及第三辅助通孔913的设置方式可以参见上述实施方式，在此不作赘述。
本公开实施例还提供了又一些显示面板，如图13与图14所示，其针对上述实施例中的部分实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中。如图13与图14所示，第四导电层400还可以包括位于第一非显示区A3的多条第四发光传输线424；层间介质层630还可以包括多个第四发光通孔824；相互电连接的发光控制线EM对应一条第四发光传输线424。并且，第一发光连接部141还通过第四发光通孔824与第四发光传输线424电连接；第三导电层300还可以包括位于第一非显示区A3的第四扫描传输线414；其中，相互电连接的第一扫描线GA1与第二扫描线GA2直接电连接一条第四扫描传输线414。这样可以在第三导电层300中设置第四扫描传输线414，在第四导电层400中设置第四发光传输线424。
示例性地，为了降低信号干扰，如图13与图14所示，可以使第四扫描传输线414在衬底基板010的正投影与第四发光传输线424在衬底基板010的正投影不交叠。示例性地，可以使第四扫描传输线414在衬底基板010的正投影与第四发光传输线424在衬底基板010的正投影间隔设置。
进一步地，为了降低信号干扰，可以使第四扫描传输线414在衬底基板010的正投影与第一数据传输线711在衬底基板010的正投影具有交叠区域。进一步地，可以使第四扫描传输线414在衬底基板010的正投影与第一数据传输线711在衬底基板010的正投影部分重叠。由于第四扫描传输层位于第三导电层300，第一数据传输线711位于第一导电层100，这样不仅可以使第四扫描传输层与第一数据传输线711之间的耦合电容降低，还可以降低第一非显示区A3的占用面积。
进一步地，为了降低信号干扰，可以使第四发光传输线424在衬底基板010的正投影与第二数据传输线712在衬底基板010的正投影具有交叠区域。进一步地，可以使第四发光传输线424在衬底基板010的正投影与第二数据传输线712在衬底基板010的正投影部分重叠。由于第四发光传输线424位于第四导电层400，第二数据传输线712位于第二导电层200，这样不仅可以使第四发光传输层与第二数据传输线712之间的耦合电容较大，还可以降低第一非显示区A3的占用面积。
需要说明的是，第一辅助通孔911、第二辅助通孔912以及第三辅助通孔913的设置方式可以参见上述实施方式，在此不作赘述。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的显示面板及显示装置，通过将第一数据连接部设置在第二导电层中，从而可以使第一导电层中的数据线和第一数据传输线通过第二导电层中的第一数据连接部相互电连接。这样不仅可以使同一列子像素 对应的且被缺口区分割开的数据线进行电连接，还可以使第一数据连接部对第三导电层和第四导电层的干扰减小，从而可以提高信号稳定性，提高显示效果。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (34)

  1. 一种显示面板，其中，包括：
    衬底基板，包括缺口区、显示区以及第一非显示区，所述第一非显示区位于所述缺口区与所述显示区之间；
    第一导电层，位于所述衬底基板上；
    目标绝缘层，位于所述第一导电层与所述衬底基板之间；
    功能层，位于所述目标绝缘层与所述衬底基板之间；
    所述显示区包括多个子像素、多条数据线、多条扫描线、多条发光控制线；其中，所述多个子像素中的至少一个包括：连接通孔；其中，所述连接通孔贯穿所述目标绝缘层，且所述第一导电层通过所述连接通孔与所述功能层电连接；
    所述第一非显示区包括：至少一个辅助通孔、多条数据传输线、多条扫描传输线以及多条发光传输线：其中，所述多条数据线中的至少一条与所述多条数据传输线中的至少一条电连接，所述多条扫描线中的至少一条与所述多条扫描传输线中的至少一条电连接，所述多条发光控制线中的至少一条与所述多条发光传输线中的至少一条电连接；
    所述第一非显示区中，所述多条数据传输线、所述多条扫描传输线以及所述多条发光传输线中的至少两种传输线围绕形成辅助区域，所述辅助通孔位于所述辅助区域内，且所述辅助通孔贯穿所述目标绝缘层且所述辅助通孔未填充导电材料。
  2. 如权利要求1所述的显示面板，其中，所述显示面板包括：
    半导体层，位于所述衬底基板与所述第一导电层之间；
    第一栅绝缘层，位于所述半导体层与所述第一导电层之间；
    第三导电层，位于所述第一栅绝缘层与所述第一导电层之间；
    第二栅绝缘层，位于所述第三导电层与所述第一导电层之间；
    第四导电层，位于所述第二栅绝缘层与所述第一导电层之间；
    层间介质层，位于所述第四导电层与所述第一导电层之间；
    所述多个子像素中的至少一个包括：第一连接通孔、第二连接通孔以及第三连接通孔；其中，所述第一连接通孔贯穿所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层；所述第二连接通孔贯穿所述第二栅绝缘层与所述层间介质层；所述第三连接通孔贯穿所述层间介质层；
    所述第一导电层通过所述第一连接通孔与所述半导体层电连接；
    所述第一导电层通过所述第二连接通孔与所述第三导电层电连接；
    所述第一导电层通过所述第三连接通孔与所述第四导电层电连接；
    所述辅助通孔中填充绝缘材料。
  3. 如权利要求2所述的显示面板，其中，所述显示面板，还包括：
    层间绝缘层，位于所述第一导电层背离所述衬底基板一侧；
    所述辅助通孔中填充所述层间绝缘层的材料。
  4. 如权利要求3所述的显示面板，其中，所述功能层包括所述半导体层；
    所述目标绝缘层包括：所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层；
    所述连接通孔包括所述第一连接通孔；
    所述辅助通孔包括第一辅助通孔，所述第一辅助通孔贯穿所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层，且所述第一辅助通孔中填充的材料贯穿所述第一栅绝缘层、所述第二栅绝缘层以及所述层间介质层。
  5. 如权利要求4所述的显示面板，其中，所述第一辅助通孔的分布密度小于或大致等于所述第一连接通孔的分布密度。
  6. 如权利要求4或5所述的显示面板，其中，所述第一辅助通孔在所述衬底基板的正投影与所述半导体层、所述第三导电层、所述第四导电层以及所述第一导电层在所述衬底基板的正投影不交叠。
  7. 如权利要求3-6任一项所述的显示面板，其中，所述功能层包括所述第三导电层；
    所述目标绝缘层包括：所述第二栅绝缘层与所述层间介质层；
    所述连接通孔包括所述第二连接通孔；
    所述辅助通孔包括第二辅助通孔，所述第二辅助通孔贯穿所述第二栅绝缘层与所述层间介质层，且所述第二辅助通孔中填充的材料贯穿所述第二栅绝缘层与所述层间介质层。
  8. 如权利要求7所述的显示面板，其中，所述第二辅助通孔的分布密度小于或大致等于所述第二连接通孔的分布密度。
  9. 如权利要求7或8所述的显示面板，其中，所述第二辅助通孔在所述衬底基板的正投影与所述第三导电层、所述第四导电层以及所述第一导电层在所述衬底基板的正投影不交叠。
  10. 如权利要求3-9任一项所述的显示面板，其中，所述功能层包括所述第四导电层；
    所述目标绝缘层包括：所述层间介质层；
    所述连接通孔包括所述第三连接通孔；
    所述辅助通孔包括第三辅助通孔，所述第三辅助通孔贯穿所述层间介质层，且所述第三辅助通孔中填充的材料贯穿所述层间介质层。
  11. 如权利要求10所述的显示面板，其中，所述第三辅助通孔的分布密度小于或大致等于所述第三连接通孔的分布密度。
  12. 如权利要求10或11所述的显示面板，其中，所述第三辅助通孔在所述衬底基板的正投影与所述第四导电层以及所述第一导电层在所述衬底基板的正投影不交叠。
  13. 如权利要求2-12任一项所述的显示面板，其中，所述多条数据传输线包括多条第一数据传输线；第一导电层，包括所述多条数据线和所述多条第一数据传输线；所述层间绝缘层具有多个第一数据通孔；
    所述显示面板，还包括：
    第二导电层，位于所述层间绝缘层背离所述衬底基板一侧，且包括多个第一数据连接部；
    所述多个第一数据连接部中的至少一个通过所述第一数据通孔分别与所 述多条数据线中的至少一个和所述多条第一数据传输线中的至少一个电连接。
  14. 如权利要求13所述的显示面板，其中，所述多条数据传输线包括多条第二数据传输线；
    所述第二导电层还包括：所述多条第二数据传输线；所述多条第二数据传输线与所述第一数据连接部间隔设置；
    所述层间绝缘层还包括：多个第二数据通孔；
    所述多条数据线包括多条第一数据线和多条第二数据线；其中，一条所述第一数据线通过所述第一数据连接部与一条所述第一数据传输线电连接；一条所述第二数据线通过所述第二数据通孔与一条所述第二数据传输线电连接。
  15. 如权利要求14所述的显示面板，其中，所述第三导电层包括所述多条扫描线和所述多条发光控制线；其中，所述多条扫描线包括多条第一扫描线和多条第二扫描线；
    所述显示区还包括多个子像素；其中，一行所述子像素对应一条所述第一扫描线和一条所述第二扫描线；每相邻两行子像素中的第一行子像素对应的第二扫描线与第二行子像素对应的第一扫描线电连接；
    一行所述子像素对应一条所述发光控制线；且相邻两行子像素对应的发光控制线电连接。
  16. 如权利要求15所述的显示面板，其中，所述第一导电层还包括：与所述数据线和所述第一数据传输线绝缘且间隔设置的多个第一扫描连接部；其中，第q-1行子像素对应的第二扫描线与第q行子像素对应的第一扫描线通过至少一个所述第一扫描连接部电连接；q为整数；
    所述第二绝缘层包括多个第一扫描通孔和多个第二扫描通孔；
    所述第一扫描连接部的第一端通过所述多个第一扫描通孔中的至少一个与对应的所述第一扫描线电连接，所述第一扫描连接部的第二端通过所述多个第二扫描通孔中的至少一个与对应的所述第二扫描线电连接。
  17. 如权利要求16所述的显示面板，其中，所述所有行子像素包括第一 类行子像素；第一类行子像素中的至少一行子像素对应至少一个所述第一数据连接部；
    针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述第一数据连接部，所述第一数据连接部在衬底基板的正投影与所述第一扫描线对应的第一扫描连接部和所述第二扫描线对应的第一扫描连接部在所述衬底基板的正投影不交叠。
  18. 如权利要求17所述的显示面板，其中，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述第一数据连接部，所述第一数据连接部在所述衬底基板的正投影位于所述第一扫描线对应的第一扫描通孔和所述第二扫描线对应的第二扫描通孔在所述衬底基板的正投影之间。
  19. 如权利要求18所述的显示面板，其中，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述第一数据连接部，所述第一扫描线对应的第一扫描通孔在所述衬底基板的正投影的中心和所述第二扫描线对应的第二扫描通孔在所述衬底基板的正投影的中心之间的连线与所述第一数据连接部在所述衬底基板的正投影交叠。
  20. 如权利要求17-19任一项所述的显示面板，其中，针对同一行子像素对应的所述第一扫描线与所述第一数据连接部以及采用所述第一数据连接部电连接的第一数据线和第一数据传输线，所述第一数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，且所述第一数据线和所述第一数据传输线在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影不交叠。
  21. 如权利要求20所述的显示面板，其中，针对同一行子像素对应的所述第一扫描线与所述第一数据连接部，所述第一数据连接部的边缘区域在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域。
  22. 如权利要求20所述的显示面板，其中，针对同一行子像素对应的所述第一扫描线与所述第一数据连接部，所述第一数据连接部的中心区域在所 述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域。
  23. 如权利要求17-22任一项所述的显示面板，其中，所述第一类行子像素中的部分行子像素对应两个所述第一数据连接部，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述两个第一数据连接部，所述两个第一数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，所述两个第一数据连接部在所述衬底基板的正投影与所述第二扫描线在所述衬底基板的正投影不交叠。
  24. 如权利要求23所述的显示面板，其中，针对同一行子像素对应的所述第一扫描线、所述第二扫描线以及所述两个第一数据连接部，
    所述两个第一数据连接部中的第一个第一数据连接部在所述衬底基板的正投影靠近所述第一扫描线对应的第一扫描通孔在所述衬底基板的正投影；和/或，
    所述两个第一数据连接部中的第二个第一数据连接部在所述衬底基板的正投影靠近所述第二扫描线对应的第二扫描通孔在所述衬底基板的正投影。
  25. 如权利要求17-24任一项所述的显示面板，其中，所述第二导电层还包括：多个第二数据连接部；其中，一条所述第二数据传输线直接电连接至少一个所述第二数据连接部，且所述第二数据连接部通过所述第二数据通孔与一条所述第二数据线电连接。
  26. 如权利要求25所述的显示面板，其中，沿第一方向，所述第一数据线和所述第二数据线交替排列；
    所述第一数据连接部和所述第二数据连接部在沿所述第一方向延伸的直线上的投影交替排列。
  27. 如权利要求26所述的显示面板，其中，所述所有行子像素包括第二类行子像素；所述第二类行子像素与所述第一类行子像素不同；
    所述第二类行子像素中的至少一行子像素对应至少一个所述第二数据连接部；
    针对同一行子像素对应的所述第一扫描线与所述第二数据连接部以及采用所述第二数据连接部电连接的第二数据线和第二数据传输线，所述第二数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，且所述第二数据线和所述第二数据传输线在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影不交叠。
  28. 如权利要求27所述的显示面板，其中，针对对应两个所述第一数据连接部的一行子像素，所述行子像素还对应一个所述第二数据连接部；
    针对同一行子像素对应的所述第一扫描线与所述第二数据连接部以及采用所述第二数据连接部电连接的第二数据线和第二数据传输线，所述第二数据连接部在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影具有交叠区域，且所述第二数据线和所述第二数据传输线在所述衬底基板的正投影与所述第一扫描线在所述衬底基板的正投影不交叠。
  29. 如权利要求15-28任一项所述的显示面板，其中，所述第一导电层还包括：与所述数据线和所述第一数据传输线绝缘且间隔设置的多个第一发光连接部；其中，相互电连接的所述发光控制线对应至少一个所述第一发光连接部；
    所述第二绝缘层包括多个第一发光通孔和多个第二发光通孔；
    所述第一发光连接部的第一端通过所述多个第一发光通孔中的至少一个与对应的一条所述发光控制线电连接，所述第一发光连接部的第二端通过所述多个第二发光通孔中的至少一个与对应的另一条所述发光控制线电连接。
  30. 如权利要求29所述的显示面板，其中，所述多条扫描传输线包括：多条第一扫描传输线和多条第二扫描传输线，所述发光传输线包括多条第一发光传输线和多条第二发光传输线；
    所述第三导电层还包括位于所述第一非显示区的所述多条第一扫描传输线和所述多条第一发光传输线；其中，所述第一扫描传输线和所述第一发光传输线间隔设置；
    部分相互电连接的所述第一扫描线和所述第二扫描线直接对应电连接一 条所述第一扫描传输线；且部分相互电连接的发光控制线直接电连接一条所述第一发光传输线；
    所述第四导电层还包括位于所述第一非显示区的所述多条第二扫描传输线和所述多条第二发光传输线；其中，所述第二扫描传输线和所述第二发光传输线间隔设置；
    所述层间介质层还包括多个第三扫描通孔和多个第三发光通孔；
    其余部分相互电连接的所述第一扫描线和所述第二扫描线对应一条所述第二扫描传输线，且所述第一扫描连接部还通过所述第三扫描通孔与所述第二扫描传输线电连接；
    其余部分相互电连接的所述发光控制线对应一条所述第二发光传输线，且所述第一发光连接部还通过所述第三发光通孔与所述第二发光传输线电连接。
  31. 如权利要求29所述的显示面板，其中，所述多条扫描传输线包括：多条第三扫描传输线，所述发光传输线包括多条第三发光传输线；
    所述第四导电层包括位于所述第一非显示区的多条第三扫描传输线；
    所述层间介质层包括多个第四扫描通孔；
    相互电连接的所述第一扫描线和所述第二扫描线对应一条所述第三扫描传输线，并且，所述第一扫描连接部还通过第四扫描通孔与所述第三扫描传输线电连接；
    所述第三导电层还包括位于所述第一非显示区的第三发光传输线；其中，相互电连接的发光控制线直接电连接一条所述第三发光传输线。
  32. 如权利要求29所述的显示面板，其中，所述多条扫描传输线包括：多条第四扫描传输线，所述发光传输线包括多条第四发光传输线；
    所述第四导电层包括位于所述第一非显示区的多条第四发光传输线；
    所述层间介质层包括多个第四发光通孔；
    相互电连接的所述发光控制线对应一条所述第四发光传输线，并且，所述第一发光连接部还通过第四发光通孔与所述第四发光传输线电连接；
    所述第三导电层还包括位于所述第一非显示区的第四扫描传输线；其中，相互电连接的所述第一扫描线与所述第二扫描线直接电连接一条所述第四扫描传输线。
  33. 如权利要求29-32任一项所述的显示面板，其中，针对同一行子像素对应的所述发光控制线、所述第二扫描线以及所述第二数据连接部，所述第二数据连接部在所述衬底基板的正投影位于所述第二扫描线对应的第二扫描通孔和所述发光控制线对应的第一发光通孔在所述衬底基板的正投影之间。
  34. 一种显示装置，其中，包括如权利要求1-33任一项所述的显示面板。
PCT/CN2020/080079 2020-03-18 2020-03-18 显示面板及显示装置 WO2021184274A1 (zh)

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