WO2022067581A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022067581A1
WO2022067581A1 PCT/CN2020/119087 CN2020119087W WO2022067581A1 WO 2022067581 A1 WO2022067581 A1 WO 2022067581A1 CN 2020119087 W CN2020119087 W CN 2020119087W WO 2022067581 A1 WO2022067581 A1 WO 2022067581A1
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WO
WIPO (PCT)
Prior art keywords
pixel
sub
base substrate
orthographic projection
color sub
Prior art date
Application number
PCT/CN2020/119087
Other languages
English (en)
French (fr)
Inventor
杜丽丽
周宏军
魏锋
马倩
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/119087 priority Critical patent/WO2022067581A1/zh
Priority to US17/418,900 priority patent/US20220310753A1/en
Priority to CN202080002193.8A priority patent/CN114730796A/zh
Priority to PCT/CN2020/124166 priority patent/WO2022067923A1/zh
Priority to CN202080002490.2A priority patent/CN115769700A/zh
Priority to US17/424,769 priority patent/US20220320194A1/en
Publication of WO2022067581A1 publication Critical patent/WO2022067581A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • a base substrate including a plurality of sub-pixels:
  • transistor array layer located on the base substrate, and the transistor array layer includes an anode transfer part located in each of the sub-pixels;
  • a first flat layer located on the side of the transistor array layer away from the base substrate;
  • a first electrode layer located on the side of the first flat layer away from the base substrate, the first electrode layer includes an anode located in each of the sub-pixels; wherein the anode includes a main body part that is electrically connected to each other and the via hole portion; and the via hole portion in each of the sub-pixels is electrically connected to the anode transfer portion through a first via hole; the first via hole penetrates the first flat layer;
  • the plurality of sub-pixels include first-color sub-pixels and second-color sub-pixels adjacent to each other along the first direction; the first via hole in the first-color sub-pixel is located at the orthographic projection of the base substrate The main body portion in the first color sub-pixel and the main body portion in the second color sub-pixel are between the orthographic projections of the base substrate;
  • one side of the anode in the second color sub-pixel faces the first color sub-pixel in the orthographic projection of the base substrate
  • the anode in the pixel has a first recess on the orthographic projection side of the base substrate; and the first recess is disposed toward the center of the main body of the second color sub-pixel;
  • the display panel includes a plurality of repeating units, and each repeating unit includes at least one sub-pixel of the first color and at least one sub-pixel of the second color;
  • Two adjacent repeating units have at least two of the first recesses and two of the first via holes; and, in the first direction, at least two adjacent repeating units have The two first recesses and the first via holes are arranged on the same straight line.
  • the orthographic projection of the first recess of the anode in the second color sub-pixel in the second direction covers where the first via hole in the first color sub-pixel is located. orthographic projection in the second direction.
  • the orthographic projection of the via portion on the base substrate covers the orthographic projection of the first via on the base substrate
  • the first recess is disposed in the main body portion of the second color sub-pixel, and the orthographic projection of the first recess in the second direction covers the via portion in the first color sub-pixel in the first color sub-pixel. Orthographic projection in two directions.
  • an edge of the orthographic projection of the first recess on the base substrate is substantially parallel to an edge of the orthographic projection of the base substrate of the via portion in the first color sub-pixel.
  • the first recess is between an edge of the orthographic projection of the base substrate and an edge of the orthographic projection of the base substrate of the via portion in the first color sub-pixel The distance is 2.5 to 20 ⁇ m.
  • the first color sub-pixel is a red sub-pixel
  • the second color sub-pixel is a green sub-pixel
  • the transistor array layer includes a driving transistor located in each of the sub-pixels; the orthographic projection of the anode in the green sub-pixel on the base substrate and the channel region of the driving transistor in the red sub-pixel are located there.
  • the orthographic projection of the base substrate has an overlapping area.
  • the orthographic projection of the anode in the red sub-pixel on the base substrate does not overlap with the orthographic projection of the channel region of each of the driving transistors on the base substrate.
  • the transistor array layer includes: a plurality of scan lines, a plurality of reset lines, and a plurality of light-emitting control lines spaced apart from each other; wherein, one of the repeating units corresponds to at least one of the scan lines, at least one of the the reset line and at least one of the light-emitting control lines;
  • the orthographic projection of the reset line on the base substrate does not overlap with the orthographic projection of the anode in the red sub-pixel controlled by the reset line on the base substrate, so
  • the orthographic projection of the light-emitting control line on the base substrate and the anode in the green sub-pixel controlled by the light-emitting control line have an overlapping area on the orthographic projection of the base substrate, and the scan line is on the
  • the orthographic projection of the base substrate does not overlap with the orthographic projection of each of the anodes controlled by the scan lines on the base substrate.
  • the transistor array layer further includes an active layer of a conduction control transistor located in each of the sub-pixels; and in the same sub-pixel, the anode transfer portion is connected to all the sub-pixels through a second via hole. the conductive region of the active layer of the conduction control transistor is electrically connected;
  • the first via hole and the second via hole in the red sub-pixel have a first overlapping area on the orthographic projection of the base substrate;
  • the first via hole and the second via hole in the green sub-pixel have a second overlapping area on the orthographic projection of the base substrate;
  • the area of the first overlapping area is not larger than the area of the second overlapping area.
  • the area of the first overlapping region is 0-0.9 ⁇ m; the area of the second overlapping region is 0-0.9 ⁇ m.
  • the first color sub-pixel is a green sub-pixel
  • the second color sub-pixel is a blue sub-pixel
  • the orthographic projection of the anode in the blue sub-pixel on the base substrate and the orthographic projection of the driving transistor in the green sub-pixel on the base substrate have an overlapping area.
  • the orthographic projection of the anode on the base substrate and the orthographic projection of the channel region of the driving transistor on the base substrate have an overlapping region.
  • the orthographic projection of the light-emitting control line of the repeating unit on the base substrate and the anode in the blue sub-pixel and the anode in the green sub-pixel are in the The orthographic projections of the base substrate respectively have overlapping regions, and the orthographic projections of the reset lines and scan lines of the repeating units on the base substrate are controlled to not overlap with the orthographic projections of the anodes on the base substrate.
  • the first via hole and the second via hole in the green sub-pixel have a second overlapping area in the orthographic projection of the base substrate, and the first via hole in the blue sub-pixel and The second via hole has a third overlapping area on the orthographic projection of the base substrate, and the area of the third overlapping area is 0-9 ⁇ m 2 .
  • the area of the third overlapping region is less than or equal to the area of the second overlapping region.
  • the repeating unit further includes at least one sub-pixel of a third color
  • the connecting lines between the anodes in the adjacent first color sub-pixels, the second color sub-pixels and the third color sub-pixels form a triangle.
  • the orthographic projection of the first via hole in the second color sub-pixel on the base substrate is located at the via hole portion in the first color sub-pixel and the The body portion in the third color subpixel is between the orthographic projections of the base substrate, and the first via hole in the second color subpixel, the via hole portion in the first color subpixel, and The orthographic projection of the main body in the third color sub-pixel on the base substrate is located on the same straight line, and the straight line is substantially parallel to the first direction.
  • the orthographic projection of the main body portion in the third color sub-pixel on the base substrate faces the first via hole in the second color sub-pixel on the backing
  • the orthographic side of the base substrate has a second recess.
  • the orthographic projection of the second recess of the main body portion in the third color sub-pixel in the first direction is the same as the first cross in the second color sub-pixel.
  • the orthographic projection of the hole in the first direction has at least an overlapping area.
  • the orthographic projection of the second recess of the main body portion in the third color sub-pixel in the first direction covers the first overhang in the second color sub-pixel orthographic projection of the hole in the first direction.
  • the orthographic projection of the second recess of the main body portion in the third color sub-pixel in the first direction covers the via portion in the second color sub-pixel orthographic projection on the first direction.
  • an edge of the orthographic projection of the second recess on the base substrate is substantially parallel to an edge of the orthographic projection of the main portion of the second color sub-pixel on the base substrate.
  • a second distance between an edge of the orthographic projection of the second recess in the base substrate and an edge of the orthographic projection of the main portion of the second color sub-pixel in the base substrate 2.5 to 20 ⁇ m.
  • the orthographic projection of the first via hole in the third color sub-pixel on the base substrate is located at an orthographic projection of the second recess on the base substrate away from the second color sub-pixel
  • the via portion in the base plate is on one side of the orthographic projection of the base substrate.
  • the anode in the first color sub-pixel further includes a first connection portion electrically connected between the main body portion and the via portion;
  • the first connection portion extends along the first direction.
  • the anode in the second color sub-pixel further includes a second connection portion electrically connected between the main body portion and the via portion;
  • the second connecting portion extends along a third direction
  • the third direction is different from both the first direction and the second direction.
  • the orthographic projection of the anode in the third color sub-pixel on the base substrate is respectively at the reset line and the light-emitting control line that control the pixel circuit in the repeating unit.
  • the orthographic projection of the base substrate has an overlapping area.
  • the first vias in the repeating units adjacent along the second direction are sequentially arranged substantially along the second direction.
  • the orthographic projections of the first vias in the first direction in the adjacent repeating units along the second direction overlap.
  • a base substrate including a plurality of sub-pixels:
  • transistor array layer located on the base substrate, and the transistor array layer includes an anode transfer part located in each of the sub-pixels;
  • a first flat layer located on the side of the transistor array layer away from the base substrate;
  • a first electrode layer located on the side of the first flat layer away from the base substrate, the first electrode layer includes an anode located in each of the sub-pixels, and the anode in each of the sub-pixels passes through the first electrode a via hole is electrically connected to the anode transfer part; the first via hole penetrates the first flat layer; each of the anodes includes a main body part and a via hole part;
  • a pixel-defining layer located on the side of the first electrode layer away from the base substrate;
  • the pixel-defining layer includes an opening in each of the sub-pixels, and in the same sub-pixel, the opening is in the
  • the orthographic projection of the base substrate is located within the orthographic projection of the anode on the base substrate;
  • the plurality of sub-pixels include third-color sub-pixels; in the third-color sub-pixels, the orthographic projection of the opening on the base substrate faces the first via hole in the third-color sub-pixels One side of the orthographic projection of the base substrate has an opening recess;
  • the main part of the anode faces on the orthographic projection of the base substrate, and the first via hole of the anode of the third-color sub-pixel faces at one of the orthographic projections of the base substrate.
  • the side has a third recess, and the third recess is substantially parallel to the opening recess.
  • the orthographic projection of the opening recess in the first direction covers the orthographic projection of the first via hole in the first direction.
  • the edge of the orthographic projection of the opening recess on the base substrate is substantially parallel to the edge of the orthographic projection of the first via hole on the base substrate.
  • the opening is recessed between an edge of the orthographic projection of the base substrate and an edge of the orthographic projection of the first via hole of the base substrate
  • the third distance is 2.25 to 20 ⁇ m.
  • the edge of the orthographic projection of the third recess on the base substrate overlaps the edge of the orthographic projection of the opening recess on the base substrate.
  • the plurality of subpixels further includes: a first color subpixel and a second color subpixel;
  • the orthographic projection of the opening on the base substrate is a rectangle.
  • the area of the opening in the third color sub-pixel is larger than the area of the opening in the second color sub-pixel
  • the area of the opening in the second color sub-pixel is larger than the area of the opening in the first color sub-pixel.
  • An embodiment of the present disclosure further provides a display device, including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2a is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 2b is a signal timing diagram provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a layout structure of a display panel according to an embodiment of the present disclosure
  • FIG. 4a is a schematic diagram of some active semiconductor layers provided in an embodiment of the present disclosure.
  • 4b is a schematic diagram of some gate conductive layers provided in an embodiment of the present disclosure.
  • 4c is a schematic diagram of some reference conductive layers provided in an embodiment of the present disclosure.
  • 4d is a schematic diagram of some source-drain metal layers provided in an embodiment of the present disclosure.
  • FIG. 4e is a schematic diagram of some first electrode layers provided in an embodiment of the present disclosure.
  • 4f is a schematic diagram of some first electrode layers and spacer layers provided in embodiments of the present disclosure.
  • 5a is a schematic diagram of some stacking of the active semiconductor layer and the gate conductive layer provided by the embodiments of the present disclosure
  • 5b is a schematic diagram of some stacking of an active semiconductor layer, a gate conductive layer, and a reference conductive layer according to an embodiment of the present disclosure
  • 5c is a schematic diagram of some stacking of an active semiconductor layer, a gate conductive layer, a reference conductive layer, and a source-drain metal layer according to an embodiment of the present disclosure
  • 5d is a schematic diagram of some stacking of an active semiconductor layer, a gate conductive layer, a reference conductive layer, a source-drain metal layer, and a spacer layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of other first electrode layers provided by embodiments of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure may include: a base substrate 10 .
  • the plurality of sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the display panel can use red sub-pixels, green sub-pixels and blue sub-pixels to mix light to realize color display.
  • the embodiments of the present disclosure include but are not limited to this.
  • At least one sub-pixel spx (eg, each sub-pixel) in the plurality of sub-pixels spx may include: a pixel circuit 0121 and a light-emitting element 0120 .
  • the pixel circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the anode of the light-emitting element 0120.
  • a corresponding voltage is applied to the cathode of the light-emitting element 0120, so that the light-emitting element 0120 can be driven to emit light.
  • the pixel circuit 0121 may include: a driving control circuit 0122, a first lighting control circuit 0123, a second lighting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128 and a reset circuit 0129.
  • the driving control circuit 0122 may include a control terminal, a first terminal and a second terminal. And the drive control circuit 0122 is configured to provide the light-emitting element 0120 with a drive current for driving the light-emitting element 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the first light-emitting control circuit 0123 is configured to turn on or off the connection between the driving control circuit 0122 and the first voltage terminal VDD.
  • the second light-emitting control circuit 0124 is electrically connected to the second terminal of the driving control circuit 0122 and the anode of the light-emitting element 0120 . And the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting element 0120 to be turned on or off.
  • the data writing circuit 0126 is electrically connected to the first terminal of the driving control circuit 0122 . And the data writing circuit 0126 is configured to write the signal on the data line VD into the memory circuit 0127 .
  • the storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store the data signal and the information of the drive control circuit 0122 .
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the driving control circuit 0122, respectively. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the drive control circuit 0122 .
  • the reset circuit 0129 is also electrically connected to the control terminal of the drive control circuit 0122 and the anode of the light-emitting element 0120, respectively. And the reset circuit 0129 is configured to reset the anode of the light-emitting element 0120 and reset the control terminal of the drive control circuit 0122.
  • the light-emitting element 0120 can be set as an electroluminescent diode, such as at least one of OLED, QLED, micro LED, and mini OLED.
  • the light-emitting element 0120 may include a stacked anode, a light-emitting layer, and a cathode. Further, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the light-emitting element 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited herein.
  • the drive control circuit 0122 includes a drive transistor T1
  • the control end of the drive control circuit 0122 includes the gate of the drive transistor T1
  • the first end of the drive control circuit 0122 includes the first end of the drive transistor T1.
  • the second terminal of the driving control circuit 0122 includes the second terminal of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2.
  • the storage circuit 0127 includes a storage capacitor CST.
  • Threshold compensation circuit 0128 includes threshold compensation transistor T3.
  • the first light emission control circuit 0123 includes a light emission control transistor T4.
  • the second light emission control circuit 0124 includes a turn-on control transistor T5.
  • the reset circuit 0129 includes an initialization transistor T6 and a reset transistor T7.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1
  • the second pole of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal
  • the data writing transistor T1 The gate of T2 is configured to be electrically connected to the scan line GA to receive a signal.
  • the first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second pole of the storage capacitor CST is electrically connected to the gate of the driving transistor T1.
  • the first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the driving transistor T1
  • the second pole of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1
  • the gate of the threshold compensation transistor T3 is configured to be connected to the scan line.
  • the GA is electrically connected to receive the signal.
  • the first electrode of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT to receive the reset signal
  • the second electrode of the initialization transistor T6 is electrically connected to the gate of the drive transistor T1
  • the gate of the initialization transistor T6 is configured to be connected to the reset line
  • the RST is electrically connected to receive the signal.
  • the first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT to receive a reset signal
  • the second pole of the reset transistor T7 is electrically connected to the anode of the light emitting element 0120
  • the gate of the reset transistor T7 is configured to be connected to the reset line RST Electrically connected to receive signals.
  • the first electrode of the light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD
  • the second electrode of the light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1
  • the gate of the light-emitting control transistor T4 is configured to be connected to the light-emitting control line
  • the EM is electrically connected to receive the lighting control signal.
  • the first electrode of the turn-on control transistor T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the turn-on control transistor T5 is electrically connected to the anode of the light-emitting element 0120
  • the gate of the turn-on control transistor T5 is configured to be connected to the
  • the light emission control line EM is electrically connected to receive the light emission control signal.
  • the cathode of the light-emitting element 0120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage, for example, the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant first voltage
  • the second voltage for example, the second voltage is 0 or a negative voltage, or the like.
  • the second power supply terminal VSS may be grounded.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 2a is shown in FIG. 2b.
  • the working process of the pixel circuit has three stages: T10 stage, T20 stage, and T30 stage.
  • rst represents the signal transmitted on the reset line RST
  • ga represents the signal transmitted on the scan line GA
  • em represents the signal transmitted on the light-emitting control line EM.
  • the signal rst controls the initialization transistor T6 to be turned on, so that the signal transmitted on the initialization line VINIT can be supplied to the gate of the driving transistor T1 to reset the gate of the driving transistor T1.
  • the signal rst controls the reset transistor T7 to be turned on, so as to supply the signal transmitted on the initialization line VINIT to the anode of the light-emitting element 0120 to reset the anode of the light-emitting element 0120 .
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the signal em controls both the light-emitting control transistor T4 and the conduction control transistor T5 to be turned off.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, and the turned-on data writing transistor T2 makes the data signal transmitted on the data line VD charge the gate of the driving transistor T1, so that the driving The voltage of the gate of the transistor T1 becomes: Vdata+Vth.
  • Vth represents the threshold voltage of the driving transistor T1
  • Vdata represents the voltage of the data signal.
  • the signal rst controls both the initialization transistor T6 and the reset transistor T7 to be turned off.
  • the signal em controls both the light-emitting control transistor T4 and the conduction control transistor T5 to be turned off.
  • the signal em controls both the light-emitting control transistor T4 and the conduction control transistor T5 to be turned on.
  • the turned-on light emitting control transistor T4 supplies the voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T1 so that the voltage of the first electrode of the driving transistor T1 is Vdd.
  • the driving transistor T1 generates a driving current according to the gate voltage Vdata+
  • the driving current is supplied to the light-emitting element 0120 through the turned-on conduction control transistor T5, and the light-emitting element 0120 is driven to emit light.
  • the signal rst controls the initialization transistor T6 and the reset transistor T7 to be turned off.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the first electrode of the above-mentioned transistor may be its source electrode and the second electrode may be its drain electrode; or the first electrode may be its drain electrode and the second electrode may be its source electrode.
  • the requirements of the application are determined by design.
  • the pixel circuit in the sub-pixel may be a structure including other numbers of transistors in addition to the structure shown in FIG. 2a and FIG. 2b, which is not limited in this embodiment of the present disclosure. The following description takes the structure shown in FIG. 2a as an example.
  • the display panel includes a base substrate 10, a transistor array layer disposed on the base substrate 10, a first flat layer located on the side of the transistor array layer away from the base substrate 10, and the first flat layer located away from the base substrate
  • the transistor array layer can be used to form transistors and capacitors in the pixel circuit, and to form scan lines, reset lines, light-emitting control lines EM, initialization lines VINIT, and first power supply signal lines VDD electrically connected to the first power supply terminal VDD, etc. .
  • the transistor array layer may include an active semiconductor layer 0310 , a gate conductive layer 0320 , a reference conductive layer 0330 , and a source-drain metal layer 0340 .
  • the active semiconductor layer 0310 of the pixel circuit 0121 is shown.
  • the active semiconductor layer 0310 may be formed by patterning using a semiconductor material.
  • the active semiconductor layer 0310 can be used to fabricate the above-mentioned driving active layer T1-A of the driving transistor T1, the active layer T2-A of the data writing transistor T2, the active layer T3-A of the threshold compensation transistor T3, and the light-emitting control transistor.
  • each active layer may include A source region, a drain region, and a channel region between the source and drain regions.
  • the active layers of the respective transistors are integrally provided.
  • the active semiconductor layer 0310 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • a gate insulating layer is formed on the above-mentioned active semiconductor layer 0310 for protecting the above-mentioned active semiconductor layer 0310 .
  • the gate conductive layer 0320 of the pixel circuit 0121 is shown.
  • the gate conductive layer 0320 is disposed on the side of the gate insulating layer away from the base substrate 10 , so as to be insulated from the active semiconductor layer 0310 .
  • the gate conductive layer 0320 may include the second electrode cc2 of the storage capacitor CST, the scan line GA, the reset line RST, the light emission control line EM, the protrusion TB, the gates T2-G of the data writing transistor T2, and the gate of the threshold compensation transistor T3.
  • the protruding portion of the scanning line GA forms the protruding portion TB.
  • one repeating unit corresponds to at least one scan line GA, at least one reset line RST and at least one light emission control line EM.
  • one repeating unit may correspond to one scan line GA, one reset line RST and one light emission control line EM.
  • the gate T2-G of the data writing transistor T2 may be the portion where the scan line GA overlaps with the active semiconductor layer 0310
  • the gate T4-G of the light-emitting control transistor T4 may be the light-emitting control line
  • the gate T5-G of the turn-on control transistor T5 can be the second part where the light emitting control line EM overlaps with the active semiconductor layer 0310
  • the gate T6 of the initialization transistor T6 -G is the first part where the reset line RST overlaps with the active semiconductor layer 0310
  • the gate T7-G of the reset transistor T7 is the second part where the reset line RST overlaps with the active semiconductor layer 0310
  • the threshold compensation transistor T3 can be
  • the first gate of the threshold compensation transistor T3 may be the portion where the scan line GA overlaps with the active semiconductor layer 0310
  • the second gate of the threshold compensation transistor T3 may be protrude
  • each dotted line in FIG. 5a shows each part where the gate conductive layer 0320 and the active semiconductor layer 0310 overlap.
  • the scan line GA, the reset line RST and the light emission control line EM are arranged along the first direction F1.
  • the scan line GA, the reset line RST and the light emission control line EM extend substantially along the second direction F2.
  • the orthographic projection of the scan line GA on the base substrate 10 is located between the orthographic projection of the reset line RST on the base substrate 10 and the orthographic projection of the light emission control line EM on the base substrate 10 .
  • FIG. 3 only takes the first direction F1 as the column direction and the second direction F2 as the row direction as an example for description.
  • the first direction F1 may also be the row direction
  • the second direction F2 may also be the column direction, which is not limited herein.
  • the second pole cc2 of the storage capacitor CST is located between the scan line GA and the light emission control line EM.
  • the protrusion TB protruding from the scan line GA is located on the side of the scan line GA away from the light emission control line EM.
  • the protrusion TB protrudes from the scanning line GA in a direction opposite to the arrow in the first direction F1.
  • an interlayer dielectric layer is formed on the above-mentioned gate conductive layer 0320 to protect the above-mentioned gate conductive layer 0320 .
  • the reference conductive layer 0330 of the pixel circuit 120 a is shown.
  • the reference conductive layer 0330 includes the first pole cc1 of the storage capacitor CST, the initialization line VINIT, and the light shielding layer ZG.
  • the first pole cc1 of the storage capacitor CST and the second pole cc2 of the storage capacitor CST at least partially overlap to form the storage capacitor CST.
  • the first pole cc1 of the storage capacitor CST has a hollow area LQ
  • the orthographic projection of the hollow area LQ on the base substrate 10 may overlap with the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 . area.
  • the orthographic projection of the light shielding layer ZG on the base substrate 10 and the drain region of the initialization transistor T6 in the active semiconductor layer 0310 (that is, the drain region of the initialization transistor T6 )
  • the side of the region electrically connected to the gate of the driving transistor T1 ) overlaps in the orthographic projection of the base substrate 10 . In this way, the influence of light on the initialization transistor T6 can be reduced, and the reset accuracy can be improved.
  • the threshold compensation transistor T3 is a double-gate transistor.
  • the light shielding layer ZG shields the active layer part between the two gates of the threshold compensation transistor T3, because the threshold compensation transistor T3 is directly connected to the driving transistor T1, which can stabilize the working state of the driving transistor T1.
  • an interlayer insulating layer is formed on the above-mentioned reference conductive layer 0330 to protect the above-mentioned reference conductive layer 0330 .
  • the source-drain metal layer 0340 of the pixel circuit 0121 is shown, and the source-drain metal layer 0340 is located on the side of the interlayer insulating layer away from the base substrate 10 .
  • the source-drain metal layer 0340 may include a first power signal line VDD, a data line VD, a first transfer portion ZB1, a second transfer portion ZB2, and an anode transfer portion YZ.
  • each sub-pixel spx includes a first transfer portion ZB1, a second transfer portion ZB2, and an anode transfer portion YZ, respectively.
  • the anode transfer part YZ is electrically connected to the conductive region of the active layer of the conduction control transistor through the second via hole GK2 .
  • the second via hole GK2 penetrates through the interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the first end of the first adapter ZB1 is electrically connected to the initialization line VINIT through the through hole TK01
  • the second end of the first adapter ZB1 is electrically connected through the through hole.
  • TK02 is electrically connected to the source region of the initialization transistor T6 in the active semiconductor layer 0310 (eg, the source region of the initialization transistor T6 in the active semiconductor layer 0310 and the source region of the reset transistor T7 in an integrated structure).
  • the through hole TK01 penetrates through the interlayer insulating layer.
  • the through hole TK02 penetrates through the interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the first end of the second transfer portion ZB2 communicates with the drain region of the initialization transistor T6 in the active semiconductor layer 0310 (the drain region of the initialization transistor T6 through the through hole TK03 ).
  • the drain region is electrically connected to the gate of the driving transistor
  • the second end of the second transfer portion ZB2 is electrically connected to the second pole cc2 of the storage capacitor CST (ie, the gate of the driving transistor) through the through hole TK04.
  • the through hole TK03 penetrates through the interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the through hole TK04 penetrates through the interlayer insulating layer and the interlayer dielectric layer.
  • the anode transfer part YZ is electrically connected to the drain region of the second light emitting control circuit 0124 in the active semiconductor layer 0310 through the second via hole GK2 .
  • the second via hole GK2 penetrates through the interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the data line VD is electrically connected to the source region of the data writing transistor T2 in the active semiconductor layer 0310 through the through hole TK05 .
  • the through hole TK05 penetrates through the interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the first power signal line VDD is electrically connected to the source region of the light emitting control transistor T4 in the active semiconductor layer 0310 through the through hole TK06 .
  • the through hole TK06 penetrates through the interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer.
  • the first power signal line VDD and the data line VD are arranged along the second direction F2, and the first power signal line VDD and the data line VD are roughly along the first direction F1 extension. It should be noted that, in the actual process, due to the limitation of process conditions or other factors such as the arrangement of wiring or via holes, the extension directions of the first power signal line VDD and the data line VD only need to roughly meet the above conditions, which belong to the present invention. the scope of protection of the invention.
  • an auxiliary insulating layer may also be formed on the above-mentioned source-drain metal layer 0340 to protect the above-mentioned source-drain metal layer 0340 .
  • An auxiliary conductive layer may also be formed on the side of the auxiliary insulating layer away from the base substrate 10, so that the auxiliary conductive layer can be electrically connected to the first power supply signal line VDD to reduce the resistance of the first power supply signal line VDD.
  • a first flat layer is formed on the above-mentioned source-drain metal layer 0340 for protecting the above-mentioned source-drain metal layer 0340 .
  • a first electrode layer is formed away from the first flat layer.
  • the first electrode layer includes an anode located in each sub-pixel. The anode in each sub-pixel is electrically connected to the anode transfer part YZ through the first via hole GK1. Moreover, the first via hole GK1 penetrates through the first flat layer.
  • the plurality of sub-pixels includes a first color sub-pixel spx1 and a second color sub-pixel spx2 adjacent along the first direction F1; wherein the first color sub-pixel spx1 includes an anode YG1. , the second color sub-pixel spx2 includes an anode YG2.
  • the orthographic projection of the first via hole GK1 in the first color sub-pixel spx1 on the base substrate 1000 is located in the main body part ZT1 in the first color sub-pixel spx1 and the main body part ZT2 in the second color sub-pixel on the base substrate 1000 . between orthographic projections.
  • the display panel includes a plurality of repeating units PX; each repeating unit PX includes at least one first color sub-pixel spx1 and at least one second color sub-pixel spx2.
  • each repeating unit PX includes a first color sub-pixel spx1 and a second color sub-pixel spx2 adjacent along the first direction F1, and the two adjacent repeating units have two first recesses AX1 and two first overhangs. hole GK1; and, in the first direction F1, two first recesses AX1 and two first via holes GK1 of at least two adjacent repeating units are arranged on the same straight line.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the red sub-pixel and the green sub-pixel are adjacent along the first direction F1.
  • the schematic diagrams of the layout structure of the pixel circuits included in each sub-pixel are arranged in an array along the first direction and the second direction. That is, the layout structure of the pixel circuits included in each sub-pixel is periodically arranged in the row direction and the column direction. Further, a plurality of repeating units PX are arranged along the second direction F2 to form a repeating unit group PXZ, and the repeating unit group PXZ is arranged along the first direction F1. And, the repeating unit includes a first color sub-pixel spx1 and a second color sub-pixel spx2 sequentially arranged along the first direction F1.
  • the anode in the second color sub-pixel spx2 faces the anode in the first color sub-pixel spx1 in the orthographic projection of the base substrate 10 and has a first recess AX1 on the orthographic side of the base substrate 10, that is, the first recess AX1 is provided in the main body portion ZT2 in the second color sub-pixel spx2.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel.
  • one repeating unit group PXZ may correspond to one scan line GA, one reset line RST and one light emission control line EM.
  • the repeating unit further includes at least one sub-pixel spx3 of the third color.
  • the repeat unit may include a third color sub-pixel spx3.
  • the connecting lines between the anodes in the adjacent first color sub-pixel spx1, second color sub-pixel spx2 and third color sub-pixel form a triangle.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third color sub-pixel spx3 is a blue sub-pixel.
  • the red sub-pixel, green sub-pixel and blue sub-pixel The lines between the anodes in the color subpixels form triangles.
  • the anode may include a main body portion and a via portion that are electrically connected to each other; wherein the orthographic projection of the via portion on the base substrate 10 covers the first via GK1 on the base substrate. 10, and in each sub-pixel, the via portion is electrically connected to the anode transfer portion YZ through the first via GK1.
  • the anode YG1 in the first color sub-pixel spx1 may further include a first connection part LB1 electrically connected between the main body part ZT1 and the via hole part GB1, that is, the main body part ZT1 in the first color sub-pixel spx1 passes through.
  • the first connection portion LB1 is electrically connected to the via hole portion GB1.
  • the anode YZ2 in the second color sub-pixel spx2 further includes a second connection part LB2 electrically connected between the main body part ZT2 and the via hole part GB2, that is, the main body part ZT2 in the second color sub-pixel spx2 passes through the second connection part LB2 It is electrically connected to the via hole GB2.
  • the main body portion ZT3 in the third color sub-pixel spx3 is directly electrically connected to the via hole portion GB3. For example, if the first color sub-pixel spx1 is a red sub-pixel, the main body portion in the red sub-pixel is electrically connected to the via portion through the first connection portion.
  • the second color sub-pixel spx2 is a green sub-pixel, and the main body portion in the green sub-pixel is electrically connected to the via portion through the second connection portion.
  • the third color sub-pixel spx3 is a blue sub-pixel, and the main body portion in the blue sub-pixel is directly electrically connected to the via portion.
  • the first connection portion extends along the first direction F1.
  • the second connection portion extends along the third direction F3.
  • the third direction F3 is different from the first direction F1 and the second direction F2.
  • the third direction F3 has an included angle with the first direction F1 and the second direction F2 respectively, so that the second connecting portion can be extended obliquely upward.
  • the main body in the third color sub-pixel spx3 faces the first via GK1 in the second color sub-pixel spx2 on the orthographic projection of the base substrate 10
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the main part of the blue sub-pixel is in The orthographic projection of the base substrate 10 faces the first via hole GK1 in the green sub-pixel and has a second recess AX2 on the orthographic side of the base substrate 10 .
  • the orthographic projection of the first via hole GK1 in the first color sub-pixel spx1 on the base substrate 10 is located at the anode YZ1 in the first color sub-pixel spx1. and the anode YZ2 in the second color sub-pixel spx2 is between the orthographic projections of the base substrate 10 .
  • the orthographic projection of the first via hole GK1 in the second color sub-pixel spx2 on the base substrate 10 is located in the via hole in the first color sub-pixel spx1
  • the portion GB1 and the main body portion ZT3 in the third color sub-pixel spx3 are between the orthographic projections of the base substrate 10 .
  • the orthographic projections of the first via hole GK1 in the second color sub-pixel spx2, the via hole portion GB1 in the first color sub-pixel spx1, and the main body portion ZT3 in the third color sub-pixel spx3 on the base substrate 1000 are located at On the same straight line, and the straight line may be substantially parallel to the first direction F1.
  • the orthographic projection of the first via hole GK1 in the sub-pixel spx3 of the third color on the base substrate 10 is located in the second recess AX2 on the base substrate 10 .
  • the orthographic projection is away from the via portion GB2 in the second color sub-pixel spx2 on the side of the orthographic projection of the base substrate 10 .
  • the second color subpixel spx2 is a green subpixel
  • the first color subpixel spx1 is a red subpixel
  • the third color subpixel spx3 is a blue subpixel.
  • the first via hole in the red subpixel The orthographic projection of GK1 on the base substrate 10 is located between the anode in the red sub-pixel and the orthographic projection of the anode in the green sub-pixel on the base substrate 10 .
  • the orthographic projection of the first via hole GK1 in the green sub-pixel on the base substrate 10 is located between the orthographic projection of the via hole portion in the red sub-pixel and the main portion of the blue sub-pixel on the base substrate 10 .
  • the orthographic projection of the first via hole GK1 in the blue sub-pixel on the base substrate 10 is located in the orthographic projection of the second recess AX2 on the base substrate 10 away from the orthographic projection of the via hole in the green sub-pixel on the base substrate 10 side.
  • the orthographic projection of the first recess AX1 of the anode in the second color sub-pixel spx2 in the second direction F2 is the same as that in the first color sub-pixel spx1.
  • the orthographic projection of the first via hole GK1 on the second direction F2 at least has an overlapping area; wherein the first direction F1 is different from the second direction F2.
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel.
  • the first color of the anode in the green subpixel is the first
  • the orthographic projection of the recess AX1 in the second direction F2 and the orthographic projection of the first via hole GK1 in the red sub-pixel in the second direction F2 at least have an overlapping area.
  • the orthographic projection in the second direction F2 refers to the line projection of the anode first recess AX1 of the green sub-pixel and the first via hole GK1 in the red sub-pixel on the straight line where the second direction F2 is located.
  • the line projection lengths of the two overlap.
  • the orthographic projection in the first direction or the second direction all refers to the line projection on the straight line where the first direction or the second direction is located.
  • the orthographic projection of the second recess AX2 of the main body in the third color sub-pixel spx3 in the first direction F1 is the same as that in the second color sub-pixel spx2.
  • the orthographic projection of the first via hole GK1 in the first direction F1 at least has an overlapping area.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second-color sub-pixel spx2 is a green sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the orthographic projection of the second recess AX2 in the first direction F1 and the orthographic projection of the first via hole GK1 in the green sub-pixel in the first direction F1 at least have an overlapping area.
  • the orthographic projection of the first recess AX1 of the anode in the second color sub-pixel spx2 in the second direction F2 covers the first-color sub-pixel spx1 in the orthographic projection.
  • the orthographic projection of the first recess AX1 of the anode in the second color subpixel spx2 in the second direction F2 covers the orthographic projection of the via hole GB1 in the first color subpixel spx1 in the second direction F2.
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel.
  • the first color of the anode in the green subpixel is the first
  • the orthographic projection of the recess AX1 in the second direction F2 covers the orthographic projection of the first via hole GK1 in the red sub-pixel in the second direction F2.
  • the orthographic projection of the second recess AX2 of the main body part ZT3 in the third color sub-pixel spx3 in the first direction F1 covers the second color sub-pixel spx2
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third color sub-pixel spx3 is a blue sub-pixel.
  • the orthographic projection of the recess AX2 in the first direction F1 covers the orthographic projection of the first via hole GK1 in the green sub-pixel in the first direction F1.
  • the orthographic projection of the second recess AX2 of the main body part ZT3 in the third color sub-pixel spx3 in the first direction F1 covers the second color sub-pixel spx2
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third color sub-pixel spx3 is a blue sub-pixel.
  • the orthographic projection of the recess AX2 in the first direction F1 covers the orthographic projection of the via hole portion GB2 in the green sub-pixel in the first direction F1.
  • the main body part ZT2 in the second color sub-pixel spx2 has a first recess AX1, and in the same repeating unit, the orthographic projection of the first recess AX1 in the second direction F2 covers The orthographic projection of the via portion in the first color sub-pixel spx1 on the second direction F2.
  • the second color sub-pixel spx2 is a green sub-pixel
  • the first-color sub-pixel spx1 is a red sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel
  • the main part of the green sub-pixel has the first recess AX1
  • the orthographic projection of the first recess AX1 in the second direction F2 covers the orthographic projection of the via portion in the red sub-pixel in the second direction F2.
  • the orthographic projection of the second recess AX2 of the main body part ZT3 in the third color sub-pixel spx3 in the first direction F1 covers the second color sub-pixel spx2
  • the second color sub-pixel spx2 is a green sub-pixel
  • the first color sub-pixel spx1 is a red sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel, then in the same repeating unit, the main part of the blue sub-pixel
  • the orthographic projection of the second recess AX2 in the first direction F1 covers the orthographic projection of the via portion in the green sub-pixel in the first direction F1.
  • the edge of the orthographic projection of the first recess AX1 on the base substrate 10 and the edge of the orthographic projection of the via portion GB1 in the first color sub-pixel spx1 on the base substrate 10 roughly parallel.
  • the second color sub-pixel spx2 is a green sub-pixel
  • the first color sub-pixel spx1 is a red sub-pixel
  • the third color sub-pixel spx3 is a blue sub-pixel.
  • the first recess AX1 is in the base substrate 10 .
  • the edge of the orthographic projection of is substantially parallel to the edge of the orthographic projection of the via portion in the red sub-pixel on the base substrate 10 . It should be noted that, in the actual process, due to the limitation of process conditions or other factors such as the arrangement of wirings or vias, the above-mentioned parallel relationship only needs to roughly satisfy the above-mentioned conditions, which all belong to the protection scope of the present invention.
  • the edge of the orthographic projection of the second recess AX2 on the base substrate 10 is approximately the same as the edge of the orthographic projection of the main body portion ZT2 in the second color sub-pixel spx2 on the base substrate 10 parallel.
  • the second color sub-pixel spx2 is a green sub-pixel
  • the first color sub-pixel spx1 is a red sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the second recess AX2 is in the base substrate 10 .
  • the edge of the orthographic projection of the green sub-pixel is substantially parallel to the edge of the orthographic projection of the main body portion in the green sub-pixel on the base substrate 10 . It should be noted that, in the actual process, due to the limitation of process conditions or other factors such as the arrangement of wirings or vias, the above-mentioned parallel relationship only needs to roughly satisfy the above-mentioned conditions, which all belong to the protection scope of the present invention.
  • the edge of the orthographic projection of the first recess AX1 on the base substrate 10 and the edge of the orthographic projection of the via portion ZT1 in the first color sub-pixel spx1 on the base substrate 10 The first distance between them is not less than 2.5 ⁇ m.
  • the second color sub-pixel spx2 is a green sub-pixel
  • the first-color sub-pixel spx1 is a red sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel
  • the first recess AX1 is on the edge of the orthographic projection of the base substrate 10
  • the first distance from the edge of the orthographic projection of the via portion in the red sub-pixel to the base substrate 10 is not less than 2.5 ⁇ m.
  • the first distance between the edge of the orthographic projection of the first recess AX1 on the base substrate 10 and the edge of the orthographic projection of the via portion in the red sub-pixel on the base substrate 10 is 2.5 ⁇ 20 ⁇ m.
  • the first distance may be set to 2.5 ⁇ m.
  • the first distance may be set to 3.5 ⁇ m, or the first distance may be set to 5.5 ⁇ m, or the first distance may be set to 10 ⁇ m, or the first distance may be set to 20 ⁇ m.
  • the first distance can be set to 3.5 ⁇ m when mass-producing the display panel in combination with the precision of the manufacturing process and the equipment.
  • the value of the first distance can be set according to the requirements of practical applications, which is not limited here.
  • the edge of the orthographic projection of the second recess AX2 on the base substrate 10 and the edge of the orthographic projection of the main body portion ZT2 in the second color sub-pixel spx2 on the base substrate 10 are between.
  • the second distance between them is not less than 2.5 ⁇ m.
  • the second distance between the edge of the orthographic projection of the second recess AX2 on the base substrate 10 and the edge of the orthographic projection of the main body portion ZT2 in the second color sub-pixel spx2 on the base substrate 10 is 2.5 ⁇ 20 ⁇ m.
  • the second color sub-pixel spx2 is a green sub-pixel
  • the first-color sub-pixel spx1 is a red sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel
  • the orthographic projection of the second recess AX2 on the base substrate 10 The second distance between the edge of the green sub-pixel and the edge of the orthographic projection of the via portion in the green sub-pixel on the base substrate 10 is not less than 2.5 ⁇ m. Further, the second distance is 2.5 ⁇ 20 ⁇ m, and the second distance may be set to 2.5 ⁇ m.
  • the second distance may be set to 3.5 ⁇ m, or the second distance may be set to 5.5 ⁇ m, or the second distance may be set to 10 ⁇ m, or the second distance may be set to 20 ⁇ m.
  • the second distance can be set to 3.5 ⁇ m when the display panel is mass-produced in combination with the precision of the manufacturing process and the equipment.
  • the value of the second distance can be set according to the requirements of practical applications, which is not limited here.
  • the transistor array layer includes driving transistors located in each sub-pixel.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third color sub-pixel spx3 is a blue sub-pixel.
  • the channel regions of the driving transistors in the sub-pixels have overlapping regions on the orthographic projection of the base substrate 10 .
  • the orthographic projection of the anode in the red sub-pixel on the base substrate 10 does not overlap with the orthographic projection of the channel region of each driving transistor on the base substrate 10 .
  • the orthographic projection of the anode in the red sub-pixel on the base substrate 10 and the orthographic projection of the pixel circuit in the red sub-pixel on the base substrate 10 have an overlapping area.
  • one repeating unit corresponds to one scan line GA, one reset line RST and one light emission control line EM.
  • a repeating unit group PXZ corresponds to a scanning line GA, a reset line RST and a light-emitting control line EM, that is, the pixel circuits in a repeating unit group PXZ are electrically connected to the same scanning line GA, the same reset line RST and the same A luminous control line EM.
  • the orthographic projection of the scanning line GA on the base substrate 10 is located between the orthographic projection of the reset line RST and the light emission control line EM on the base substrate 10 between.
  • the orthographic projection of the scan lines GA on the base substrate 10 is located at the orthographic projection of the reset lines RST and the luminescence control lines EM on the base substrate 10 between.
  • the orthographic projection of the reset line RST on the base substrate 1000 and the anode in the red sub-pixel controlled by the reset line RST are on the base substrate.
  • the orthographic projection of 1000 does not overlap
  • the orthographic projection of the light emission control line EM on the base substrate 1000 and the orthographic projection of the anode in the green sub-pixel controlled by the light emission control line EM on the base substrate 1000 have an overlapping area
  • the scanning line GA has an overlapping area.
  • the orthographic projection on the base substrate 1000 does not overlap with the orthographic projection of each anode controlled by the scanning line GA on the base substrate 1000 .
  • the orthographic projection of the reset line RST on the base substrate 1000 does not overlap with the orthographic projection of the anode in the red sub-pixel controlled by the reset line RST on the base substrate 1000, and the light emission control line
  • the orthographic projection of EM on the base substrate 1000 and the orthographic projection of the anode in the green sub-pixel controlled by the luminescence control line EM on the base substrate 1000 have an overlapping area, and the orthographic projection of the scanning line GA on the base substrate 1000 and the scanning The orthographic projections of the anodes controlled by the line GA on the base substrate 1000 do not overlap.
  • the orthographic projection of the light-emitting control line EM controlling the repeating unit on the base substrate 1000 and the orthographic projection of the anode in the blue sub-pixel and the anode in the green sub-pixel on the base substrate 1000 respectively have In the overlapping area, the orthographic projection of the reset line RST and the scanning line GA of the repeating unit on the base substrate 1000 is controlled not to overlap with the orthographic projection of each anode on the base substrate 1000 .
  • the reset line RST is a signal line for controlling the initialization transistor T6 and the reset transistor T7 in one repeating unit.
  • the light-emitting control line EM is a signal line for controlling the light-emitting control transistor T4 and the turn-on control transistor T5 in one repeating unit.
  • the scan line GA is a signal line for controlling the data writing transistor T2 and the threshold compensation transistor T3 in one repeating unit.
  • the orthographic projection of the emission control line EM of the repeating unit group PXZ on the base substrate 1000 and the orthographic projection of the anode in the blue sub-pixel and the anode in the green sub-pixel on the base substrate 1000 There are overlapping regions respectively, and the orthographic projections of the reset lines RST and the scanning lines GA of the control repeating unit group PXZ on the base substrate 1000 do not overlap with the orthographic projections of the anodes on the base substrate 1000 .
  • the reset line RST is a signal line for controlling the initialization transistor T6 and the reset transistor T7 in one repeating unit group.
  • the light-emitting control line EM is a signal line for controlling the light-emitting control transistor T4 and the turn-on control transistor T5 in one repeating unit group.
  • the scan line GA is a signal line for controlling the data writing transistor T2 and the threshold compensation transistor T3 in one repeating unit group.
  • the orthographic projection of the reset line on the base substrate 10 and the orthographic projection of the anode in the red sub-pixel on the base substrate 10 have an overlapping area, and the light-emitting control line is at
  • the orthographic projection of the base substrate 10 and the orthographic projection of the anodes in the green sub-pixels on the base substrate 10 have an overlapping area, and the orthographic projection of the scan lines on the base substrate 10 does not intersect with the orthographic projection of each anode on the base substrate 10 stack.
  • the orthographic projection of the anode in the third-color sub-pixel spx3 on the base substrate 10 is respectively related to controlling the reset of the pixel circuit in the third-color sub-pixel spx3.
  • the lines and the light emission control lines have overlapping regions on the orthographic projection of the base substrate 10 .
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second-color sub-pixel spx2 is a green sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the anode in the blue sub-pixel is lining
  • the orthographic projections of the base substrate 10 and the orthographic projections of the reset lines and the light emission control lines on the base substrate 10 have overlapping regions, respectively.
  • the first via hole GK1 and the second via hole GK2 in the red sub-pixel have a first overlapping area on the orthographic projection of the base substrate 10 .
  • the orthographic projection of the first via hole GK1 and the second via hole GK2 in the green sub-pixel has a second overlapping area on the base substrate 10 .
  • the orthographic projection of the first via hole GK1 and the second via hole GK2 in the blue sub-pixel has a third overlapping area on the base substrate 10 .
  • the area of the first overlapping area is not larger than the area of the second overlapping area.
  • the area of the first overlapping area is not larger than that of the third overlapping area.
  • the area of the third overlapping region can be made to be substantially equal to that of the second overlapping region. It should be noted that, in the actual process, due to the limitation of process conditions or other factors such as the arrangement of wirings or vias, as long as the above-mentioned equality relationship roughly satisfies the above-mentioned conditions, it belongs to the protection scope of the present invention.
  • the area of the first overlapping region is 0 ⁇ 0.9 ⁇ m.
  • the area of the first overlapping region may also be 0.5 ⁇ m, or the area of the first overlapping region may also be 0.9 ⁇ m.
  • the area of the first overlapping region may be 0, so that the orthographic projections of the first via hole GK1 and the second via hole GK2 in the red sub-pixel on the base substrate 10 do not overlap.
  • the area of the second overlapping region is 0 ⁇ 0.9 ⁇ m.
  • the area of the second overlapping region may also be 0.5 ⁇ m, or the area of the second overlapping region may also be 0.9 ⁇ m.
  • the area of the second overlapping region may be 0, so that the orthographic projections of the first via hole GK1 and the second via hole GK2 in the green sub-pixel on the base substrate 10 do not overlap.
  • the area of the third overlapping region is 0 ⁇ 0.9 ⁇ m.
  • the area of the third overlapping region may also be 0.5 ⁇ m, or the area of the third overlapping region may also be 0.9 ⁇ m.
  • the area of the third overlapping region may be 0, so that the orthographic projections of the first via hole GK1 and the second via hole GK2 in the blue sub-pixel on the base substrate 10 do not overlap.
  • the second overlapping area may be set larger. Some to ensure the distance between the anodes in the blue sub-pixel and the green sub-pixel to avoid color mixing.
  • the first vias GK1 in adjacent repeating units along the second direction F2 are arranged in sequence approximately along the second direction F2.
  • the first vias in the repeating unit group The GK1 are arranged in sequence substantially along the second direction F2.
  • the orthographic projections of the first via holes GK1 in the adjacent repeating units along the second direction F2 on the first direction F1 overlap.
  • the orthographic projections of the first via hole GK1 in the repeating unit group in the first direction F1 overlap. It should be noted that, in the actual process, due to the limitation of process conditions or other factors such as the arrangement of wirings or vias, the arrangement relationship of the first vias GK1 only needs to roughly satisfy the above conditions, which belong to the protection scope of the present invention.
  • a pixel defining layer is formed on the side of the first electrode layer away from the base substrate 10 , and the pixel defining layer includes openings in each sub-pixel, and the same sub-pixel , the orthographic projection of the opening on the base substrate 10 is located within the orthographic projection of the anode on the base substrate 10 .
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third color sub-pixel spx3 is a blue sub-pixel
  • the red sub-pixel has an opening KK1
  • the green sub-pixel has an opening KK2
  • the blue sub-pixel has an opening KK3. It should be noted that the region where the opening in each sub-pixel is located corresponds to the light-emitting region.
  • the orthographic projection of the opening on the base substrate 10 is a rectangle.
  • the orthographic projections of the openings in the first color sub-pixel spx1 and the second color sub-pixel spx2 on the base substrate 10 are both rectangles.
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel
  • the orthographic projections of KK2 on the base substrate 10 are all rectangles.
  • the area of the opening in the third color sub-pixel spx3 is larger than the area of the opening in the second color sub-pixel spx2, and the opening in the second color sub-pixel spx2 is The area is larger than the area of the opening in the first color sub-pixel spx1.
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel
  • the area of the opening KK3 in the blue subpixel is larger than that of the green subpixel
  • the area of the opening KK2 in the green sub-pixel is larger than the area of the opening KK1 in the red sub-pixel.
  • the opening area in each sub-pixel can be inversely proportional to the light-emitting life of the sub-pixel.
  • the area of the opening in the color sub-pixel is larger than the area of the opening in the green sub-pixel
  • the area of the opening in the green sub-pixel is larger than the area of the opening in the red sub-pixel.
  • the orthographic projection of the opening on the base substrate 10 faces the first via GK1 in the third color sub-pixel spx3 in the substrate.
  • One side of the orthographic projection of the substrate 10 has an opening recess AX0.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the opening KK3 is in the base substrate 10
  • the orthographic projection of the first via hole GK1 has an opening recess AX0 on the side of the orthographic projection of the base substrate 10 .
  • the orthographic projection of the opening recess AX0 in the first direction F1 covers the orthographic projection of the first via GK1 in the first direction F1.
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel.
  • the opening recess AX0 is in the first direction
  • the orthographic projection on F1 covers the orthographic projection of the first via hole GK1 on the first direction F1.
  • the opening recess AX0 is on the edge of the orthographic projection of the base substrate 10 and the first via hole GK1 is on the positive side of the base substrate 10 .
  • the projected edges are roughly parallel.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the opening recess AX0 is in the base substrate.
  • the edge of the orthographic projection of 10 is substantially parallel to the edge of the orthographic projection of the first via hole GK1 on the base substrate 10 . It should be noted that, in the actual process, due to the limitation of process conditions or other factors such as the arrangement of wirings or vias, the above-mentioned parallel relationship only needs to roughly satisfy the above-mentioned conditions, which all belong to the protection scope of the present invention.
  • the opening recess AX0 is on the edge of the orthographic projection of the base substrate 10 and the first via hole GK1 is on the positive side of the base substrate 10 .
  • the third distance between the projected edges is not less than 2.25 ⁇ m. Further, the third distance is 2.25 ⁇ 20 ⁇ m.
  • the first color sub-pixel spx1 is a red sub-pixel
  • the second color sub-pixel spx2 is a green sub-pixel
  • the third-color sub-pixel spx3 is a blue sub-pixel.
  • the opening recess AX0 is in the base substrate.
  • the third distance between the edge of the orthographic projection of 10 and the edge of the orthographic projection of the first via hole GK1 on the base substrate 10 is not less than 2.25 ⁇ m.
  • the third distance may be set to 2.25 ⁇ m.
  • the third distance may be set to 2.5 ⁇ m.
  • the third distance may be set to 20 ⁇ m.
  • the third distance can be set to 2.5 ⁇ m when the display panel is mass-produced in combination with the precision of the fabrication process and the equipment.
  • the value of the third distance can be set according to the requirements of practical applications, which is not limited here.
  • the main body ZT3 of the anode YG3 faces the first part of the anode YG3 of the third color sub-pixel spx3 in the orthographic projection of the base substrate 1000 .
  • a via hole GK1 has a third recess AX3 on the side of the orthographic projection of the base substrate 1000 , and the third recess AX3 is substantially parallel to the opening recess AX0 .
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel.
  • the main body ZT3 of the anode YG3 is in the blue subpixel
  • the first via hole GK1 of the orthographic projection of the base substrate 1000 facing the anode YG3 of the third color sub-pixel spx3 has a third recess AX3 on the side of the orthographic projection of the base substrate 1000 , and the third recess AX3 is approximately the same as the opening recess AX0 parallel.
  • the edge of the orthographic projection of the third recess AX3 on the base substrate 1000 and the orthographic projection of the opening recess AX0 on the base substrate 1000 overlap.
  • the first color subpixel spx1 is a red subpixel
  • the second color subpixel spx2 is a green subpixel
  • the third color subpixel spx3 is a blue subpixel.
  • the third recess AX3 is in the substrate
  • the edge of the orthographic projection of the substrate 1000 overlaps the edge of the orthographic projection of the opening recess AX0 on the base substrate 1000 .
  • a spacer layer is formed on the side of the pixel defining layer away from the base substrate 10 , and the spacer layer includes a plurality of spacers PS arranged at intervals.
  • a spacer PS is disposed between the anodes in the adjacent third sub-pixels along the first direction F1.
  • via holes and through holes can be formed in a circle, a square, an octagon, etc., which can be designed according to actual application requirements, which are not limited herein.
  • the first color sub-pixel spx1 may also be a green sub-pixel
  • the second color sub-pixel spx2 may be a blue sub-pixel.
  • the first direction F1 may be the row direction of the sub-pixels
  • the second direction F2 may be the column direction of the sub-pixels.
  • the repeating unit includes green sub-pixels and blue sub-pixels sequentially arranged along the first direction F1.
  • the repeating unit may further include red sub-pixels; wherein, the red sub-pixels and the green sub-pixels are arranged along the second direction F2.
  • the anode in the blue sub-pixel faces the anode in the green sub-pixel on the orthographic projection side of the base substrate 10 and has a first recess AX1 on the orthographic side of the base substrate 10 .
  • the first via GK1 in the green sub-pixel is The orthographic projection of the base substrate 10 is located between the anode in the green sub-pixel and the anode in the blue sub-pixel in the orthographic projection of the base substrate 10 .
  • the first color sub-pixel spx1 is a green sub-pixel
  • the second color sub-pixel spx2 is a blue sub-pixel
  • the first color of the anode in the blue sub-pixel The orthographic projection of the recess AX1 in the second direction F2 and the orthographic projection of the first via hole GK1 in the green sub-pixel in the second direction F2 at least have an overlapping area.
  • the first color sub-pixel spx1 is a green sub-pixel
  • the second color sub-pixel spx2 is a blue sub-pixel
  • the first color of the anode in the blue sub-pixel The orthographic projection of the recess AX1 in the second direction F2 covers the orthographic projection of the first via hole GK1 in the green sub-pixel in the second direction F2.
  • the main body in the blue sub-pixel has a first recess AX1, and
  • the orthographic projection of the first recess AX1 in the second direction F2 covers the orthographic projection of the via portion in the green sub-pixel in the second direction F2.
  • the first recess AX1 is on the edge of the orthographic projection of the base substrate 10 and the via portion in the green sub-pixel is substantially parallel to the edge of the orthographic projection of the base substrate 10 .
  • the first recess AX1 is on the edge of the orthographic projection of the base substrate 10 and
  • the first distance between the edges of the orthographic projection of the via portion in the green sub-pixel and the base substrate 10 is not less than 2.5 ⁇ m.
  • the first distance may be 2.5 ⁇ 20 ⁇ m.
  • the first distance may be 2.5 ⁇ m.
  • the first distance may be 3.5 ⁇ m.
  • the first distance may also be 20 ⁇ m, which is not limited here.
  • the setting method of the red sub-pixel in the repeating unit may refer to the setting method of the red sub-pixel above. This will not be repeated.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.

Abstract

显示面板及显示装置，包括：衬底基板（10），晶体管阵列层，第一平坦层，第一电极层，多个子像素包括沿第一方向（F1）相邻的第一颜色子像素（spx1）和第二颜色子像素（spx2）；针对沿第一方向（F1）相邻的第一颜色子像素（spx1）和第二颜色子像素（spx2），第二颜色子像素（spx2）中的阳极（YG2）的一边在衬底基板（10）的正投影面向第一颜色子像素（spx1）中的阳极（YG1）在衬底基板（10）的正投影一侧具有第一凹陷（AX1）；且第一凹陷（AX1）朝向第二颜色子像素（spx2）的主体部的中心设置；每个重复单元（PX）包括至少一个第一颜色子像素（spx1）和至少一个第二颜色子像素（spx2）；相邻的两个重复单元（PX）具有两个第一凹陷（AX1）和两个第一过孔（GK1）；并且，在第一方向（F1）上，至少相邻的两个重复单元（PX）具有的两个第一凹陷（AX1）和两个第一过孔（GK1）排列于同一直线上。

Description

显示面板及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及显示面板及显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示面板因其自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。随着人们对于OLED显示面板的要求的提高，为了实现显示面板中的高分辨率设计，OLED显示面板通常会采用SPR像素排列，即像素借用的方式。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板，包括多个子像素：
晶体管阵列层，位于所述衬底基板上，且所述晶体管阵列层包括位于各所述子像素中的阳极转接部；
第一平坦层，位于所述晶体管阵列层背离所述衬底基板一侧；
第一电极层，位于所述第一平坦层背离所述衬底基板一侧，所述第一电极层包括位于各所述子像素中的阳极；其中，所述阳极包括相互电连接的主体部与过孔部；且各所述子像素中的过孔部通过第一过孔与所述阳极转接部电连接；所述第一过孔贯穿所述第一平坦层；
其中，所述多个子像素包括沿第一方向相邻的第一颜色子像素和第二颜色子像素；所述第一颜色子像素中的第一过孔在所述衬底基板的正投影位于所述第一颜色子像素中的主体部和所述第二颜色子像素中的主体部在所述衬底基板的正投影之间；
针对沿所述第一方向相邻的第一颜色子像素和第二颜色子像素，所述第 二颜色子像素中的阳极的一边在所述衬底基板的正投影面向所述第一颜色子像素中的阳极在所述衬底基板的正投影一侧具有第一凹陷；且所述第一凹陷朝向所述第二颜色子像素的主体部的中心设置；
所述显示面板包括多个重复单元，每个所述重复单元包括至少一个所述第一颜色子像素和至少一个所述第二颜色子像素；
相邻的两个所述重复单元至少具有两个所述第一凹陷和两个所述第一过孔；并且，在所述第一方向上，至少相邻的两个所述重复单元具有的两个第一凹陷和第一过孔排列于同一直线上。
在一些示例中，同一所述重复单元中，所述第二颜色子像素中的阳极的第一凹陷在第二方向上的正投影覆盖所述第一颜色子像素中的第一过孔在所述第二方向上的正投影。
在一些示例中，同一所述子像素中，所述过孔部在所述衬底基板的正投影覆盖所述第一过孔在所述衬底基板的正投影；
所述第一凹陷设置在所述第二颜色子像素中的主体部，且第一凹陷在所述第二方向上的正投影覆盖所述第一颜色子像素中的过孔部在所述第二方向上的正投影。
在一些示例中，所述第一凹陷在所述衬底基板的正投影的边缘与所述第一颜色子像素中的过孔部在所述衬底基板的正投影的边缘大致平行。
在一些示例中，所述第一凹陷在所述衬底基板的正投影的边缘与所述第一颜色子像素中的过孔部在所述衬底基板的正投影的边缘之间的第一距离为2.5～20μm。
在一些示例中，所述第一颜色子像素为红色子像素，所述第二颜色子像素为绿色子像素；
所述晶体管阵列层包括位于各所述子像素中的驱动晶体管；所述绿色子像素中的阳极在所述衬底基板的正投影与所述红色子像素中的驱动晶体管的沟道区在所述衬底基板的正投影具有交叠区域。
在一些示例中，所述红色子像素中的阳极在所述衬底基板的正投影与各 所述驱动晶体管的沟道区在所述衬底基板的正投影不交叠。
在一些示例中，所述晶体管阵列层包括：相互间隔设置的多条扫描线、多条复位线以及多条发光控制线；其中，一个所述重复单元对应至少一条所述扫描线、至少一条所述复位线以及至少一条所述发光控制线；
在一个所述重复单元中，所述复位线在所述衬底基板的正投影与所述复位线控制的所述红色子像素中的阳极在所述衬底基板的正投影不交叠，所述发光控制线在所述衬底基板的正投影与所述发光控制线控制的所述绿色子像素中的阳极在所述衬底基板的正投影具有交叠区域，所述扫描线在所述衬底基板的正投影与所述扫描线控制的各所述阳极在所述衬底基板的正投影不交叠。
在一些示例中，所述晶体管阵列层还包括位于各所述子像素中的导通控制晶体管的有源层；且同一所述子像素中，所述阳极转接部通过第二过孔与所述导通控制晶体管的有源层的导体化区电连接；
所述红色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第一交叠区域；
所述绿色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第二交叠区域；
所述第一交叠区域的面积不大于所述第二交叠区域的面积。
在一些示例中，所述第一交叠区域的面积为0～0.9μm；所述第二交叠区域的面积为0～0.9μm。
在一些示例中，所述第一颜色子像素为绿色子像素，所述第二颜色子像素为蓝色子像素；
所述蓝色子像素中的阳极在所述衬底基板的正投影与所述绿色子像素中的驱动晶体管的沟道区在所述衬底基板的正投影具有交叠区域。
在一些示例中，同一所述蓝色子像素中，所述阳极在所述衬底基板的正投影与所述驱动晶体管的沟道区在所述衬底基板的正投影具有交叠区域。
在一些示例中，针对一个所述重复单元，控制所述重复单元的发光控制 线在所述衬底基板的正投影与所述蓝色子像素中的阳极和绿色子像素中的阳极在所述衬底基板的正投影分别具有交叠区域，控制所述重复单元的复位线和扫描线在所述衬底基板的正投影与各所述阳极在所述衬底基板的正投影不交叠。
在一些示例中，所述绿色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第二交叠区域，所述蓝色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第三交叠区域，所述第三交叠区域的面积为0-9μm2。
在一些示例中，所述第三交叠区域的面积小于等于所述第二交叠区域的面积。
在一些示例中，所述重复单元还包括至少一个第三颜色子像素；
相邻的所述第一颜色子像素、所述第二颜色子像素以及所述第三颜色子像素中的阳极之间的连线构成三角形。
在一些示例中，同一所述重复单元中，所述第二颜色子像素中的第一过孔在所述衬底基板的正投影位于所述第一颜色子像素中的过孔部与所述第三颜色子像素中的主体部在所述衬底基板的正投影之间，并且所述第二颜色子像素中的第一过孔、所述第一颜色子像素中的过孔部、和所述第三颜色子像素中的主体部在所述衬底基板上的正投影位于同一直线上，所述直线与所述第一方向大致平行。
在一些示例中，同一所述重复单元中，所述第三颜色子像素中的主体部在所述衬底基板的正投影面向所述第二颜色子像素中的第一过孔在所述衬底基板的正投影一侧具有第二凹陷。
在一些示例中，同一所述重复单元中，所述第三颜色子像素中的主体部的第二凹陷在所述第一方向上的正投影与所述第二颜色子像素中的第一过孔在所述第一方向上的正投影至少具有交叠区域。
在一些示例中，同一所述重复单元中，所述第三颜色子像素中的主体部的第二凹陷在所述第一方向上的正投影覆盖所述第二颜色子像素中的第一过 孔在所述第一方向上的正投影。
在一些示例中，同一所述重复单元中，所述第三颜色子像素中的主体部的第二凹陷在所述第一方向上的正投影覆盖所述第二颜色子像素中的过孔部在所述第一方向上的正投影。
在一些示例中，所述第二凹陷在所述衬底基板的正投影的边缘与所述第二颜色子像素中的主体部在所述衬底基板的正投影的边缘大致平行。
在一些示例中，所述第二凹陷在所述衬底基板的正投影的边缘与所述第二颜色子像素中的主体部在所述衬底基板的正投影的边缘之间的第二距离为2.5～20μm。
在一些示例中，所述第三颜色子像素中的第一过孔在所述衬底基板的正投影位于所述第二凹陷在所述衬底基板的正投影背离所述第二颜色子像素中的过孔部在所述衬底基板的正投影的一侧。
在一些示例中，所述第一颜色子像素中的阳极还包括电连接在主体部和过孔部之间的第一连接部；
所述第一连接部沿所述第一方向延伸。
在一些示例中，所述第二颜色子像素中的阳极还包括电连接在主体部和过孔部之间的第二连接部；
所述第二连接部沿第三方向延伸；
所述第三方向与所述第一方向和所述第二方向均不同。
在一些示例中，同一所述重复单元中，所述第三颜色子像素中的阳极在所述衬底基板的正投影分别与控制所述重复单元中的像素电路的复位线和发光控制线在所述衬底基板的正投影具有交叠区域。
在一些示例中，沿所述第二方向相邻的所述重复单元中的所述第一过孔大致沿第二方向依次排列。
在一些示例中，沿所述第二方向相邻的所述重复单元中的所述第一过孔在第一方向上的正投影重叠。
本公开实施例提供的显示面板，包括：
衬底基板，包括多个子像素：
晶体管阵列层，位于所述衬底基板上，且所述晶体管阵列层包括位于各所述子像素中的阳极转接部；
第一平坦层，位于所述晶体管阵列层背离所述衬底基板一侧；
第一电极层，位于所述第一平坦层背离所述衬底基板一侧，所述第一电极层包括位于各所述子像素中的阳极，且各所述子像素中的阳极通过第一过孔与所述阳极转接部电连接；所述第一过孔贯穿所述第一平坦层；各所述阳极包括主体部和过孔部；
像素限定层，位于所述第一电极层背离所述衬底基板一侧；所述像素限定层包括位于各所述子像素中的开口，且同一所述子像素中，所述开口在所述衬底基板的正投影位于所述阳极在所述衬底基板的正投影内；
其中，所述多个子像素包括第三颜色子像素；所述第三颜色子像素中，所述开口在所述衬底基板的正投影面向所述第三颜色子像素中的第一过孔在所述衬底基板的正投影的一侧具有开口凹陷；
所述第三颜色子像素中，所述阳极的主体部在所述衬底基板的正投影面向所述第三颜色子像素的阳极的第一过孔在所述衬底基板的正投影的一侧具有第三凹陷，且所述第三凹陷与所述开口凹陷大致平行。
在一些示例中，所述第三颜色子像素中，所述开口凹陷在所述第一方向上的正投影覆盖所述第一过孔在所述第一方向上的正投影。
在一些示例中，所述第三颜色子像素中，所述开口凹陷在所述衬底基板的正投影的边缘与所述第一过孔在所述衬底基板的正投影的边缘大致平行。
在一些示例中，所述第三颜色子像素中，所述开口凹陷在所述衬底基板的正投影的边缘与所述第一过孔在所述衬底基板的正投影的边缘之间的第三距离为2.25～20μm。
在一些示例中，所述第三颜色子像素中，所述第三凹陷在所述衬底基板的正投影的边缘与所述开口凹陷在所述衬底基板的正投影的边缘重叠。
在一些示例中，所述多个子像素还包括：第一颜色子像素和第二颜色子 像素；
所述第一颜色子像素和所述第二颜色子像素中的至少一个子像素中，所述开口在所述衬底基板的正投影为矩形。
在一些示例中，所述第三颜色子像素中的开口的面积大于所述第二颜色子像素中的开口的面积；
所述第二颜色子像素中的开口的面积大于所述第一颜色子像素中的开口的面积。
本公开实施例还提供的显示装置，包括上述显示面板。
附图说明
图1为本公开实施例提供的显示面板的结构示意图；
图2a为本公开实施例提供的像素电路的结构示意图；
图2b为本公开实施例提供的信号时序图；
图3为本公开实施例提供的显示面板的布局结构示意图；
图4a为本公开实施例提供的一些有源半导体层的示意图；
图4b为本公开实施例提供的一些栅导电层的示意图；
图4c为本公开实施例提供的一些参考导电层的示意图；
图4d为本公开实施例提供的一些源漏金属层的示意图；
图4e为本公开实施例提供的一些第一电极层的示意图；
图4f为本公开实施例提供的一些第一电极层和隔垫物层的示意图；
图5a为本公开实施例提供的有源半导体层和栅导电层的一些层叠示意图；
图5b为本公开实施例提供的有源半导体层、栅导电层以及参考导电层的一些层叠示意图；
图5c为本公开实施例提供的有源半导体层、栅导电层、参考导电层以及源漏金属层的一些层叠示意图；
图5d为本公开实施例提供的有源半导体层、栅导电层、参考导电层、源漏金属层以及隔垫物层的一些层叠示意图；
图6为本公开实施例提供的另一些第一电极层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本发明内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的显示面板，可以包括：衬底基板10。位于衬底基板10上的多个子像素spx。示例性地，多个子像素可以包括红色子像素、绿色子像素以及蓝色子像素。这样可以使显示面板采用红色子像素、绿色子像素以及蓝色子像素进行混光，以实现彩色显示。当然，本公开实施例包括但不限于此。
示例性地，结合图1与图2a所示，多个子像素spx中的至少一个子像素spx(例如每一个子像素)可以包括：像素电路0121和发光元件0120。其中，像素电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信 号，产生的电信号输入到发光元件0120的阳极中。并且对发光元件0120的阴极加载相应的电压，可以驱动发光元件0120发光。
结合图2a所示，像素电路0121可以包括：驱动控制电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。
驱动控制电路0122可以包括控制端、第一端和第二端。且驱动控制电路0122被配置为向发光元件0120提供驱动发光元件0120发光的驱动电流。例如，第一发光控制电路0123与驱动控制电路0122的第一端和第一电压端VDD连接。且第一发光控制电路0123被配置为实现驱动控制电路0122和第一电压端VDD之间的连接导通或断开。
第二发光控制电路0124与驱动控制电路0122的第二端和发光元件0120的阳极电连接。且第二发光控制电路0124被配置为实现驱动控制电路0122和发光元件0120之间的连接导通或断开。
数据写入电路0126与驱动控制电路0122的第一端电连接。且数据写入电路0126被配置为将数据线VD上的信号写入存储电路0127。
存储电路0127与驱动控制电路0122的控制端和第一电压端VDD电连接。且存储电路0127被配置为存储数据信号以及驱动控制电路0122的信息。
阈值补偿电路0128分别与驱动控制电路0122的控制端和第二端电连接。且阈值补偿电路0128被配置为对驱动控制电路0122进行阈值补偿。
复位电路0129还分别与驱动控制电路0122的控制端和发光元件0120的阳极电连接。且复位电路0129被配置为对发光元件0120的阳极进行复位，以及对驱动控制电路0122的控制端进行复位。
其中，发光元件0120可以设置为电致发光二极管，例如OLED、QLED、micro LED，mini OLED中的至少一种。其中，发光元件0120可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光元件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2a所示，驱动控制电路0122包括：驱动晶体管T1，驱动控制电路0122的控制端包括驱动晶体管T1的栅极，驱动控制电路0122的第一端包括驱动晶体管T1的第一极，驱动控制电路0122的第二端包括驱动晶体管T1的第二极。
示例性地，结合图2a所示，数据写入电路0126包括数据写入晶体管T2。存储电路0127包括存储电容CST。阈值补偿电路0128包括阈值补偿晶体管T3。第一发光控制电路0123包括发光控制晶体管T4。第二发光控制电路0124包括导通控制晶体管T5。复位电路0129包括初始化晶体管T6和复位晶体管T7。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线VD电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与扫描线GA电连接以接收信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T1的栅极电连接。
阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与扫描线GA电连接以接收信号。
初始化晶体管T6的第一极被配置为与初始化线VINIT电连接以接收复位信号，初始化晶体管T6的第二极与驱动晶体管T1的栅极电连接，初始化晶体管T6的栅极被配置为与复位线RST电连接以接收信号。
复位晶体管T7的第一极被配置为与初始化线VINIT电连接以接收复位信号，复位晶体管T7的第二极与发光元件0120的阳极电连接，复位晶体管T7的栅极被配置为与复位线RST电连接以接收信号。
发光控制晶体管T4的第一极与第一电源端VDD电连接，发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，发光控制晶体管T4的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
导通控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，导通控 制晶体管T5的第二极与发光元件0120的阳极电连接，导通控制晶体管T5的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
发光元件0120的阴极与第二电源端VSS电连接。其中，上述晶体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2a所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，例如第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，例如第二电压为0或者为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
图2a所示的像素电路对应的信号时序图，如图2b所示。一帧显示时间中，像素电路的工作过程具有三个阶段：T10阶段、T20阶段、T30阶段。其中，rst代表复位线RST上传输的信号，ga代表扫描线GA上传输的信号，em代表发光控制线EM上传输的信号。
在T10阶段，信号rst控制初始化晶体管T6导通，从而可以将初始化线VINIT上传输的信号提供给驱动晶体管T1的栅极，以对驱动晶体管T1的栅极进行复位。信号rst控制复位晶体管T7导通，以将初始化线VINIT上传输的信号提供给发光元件0120的阳极，以对发光元件0120的阳极进行复位。并且，此阶段中，信号ga控制数据写入晶体管T2和阈值补偿晶体管T3均截止。信号em控制发光控制晶体管T4和导通控制晶体管T5均截止。
在T20阶段，信号ga控制数据写入晶体管T2和阈值补偿晶体管T3导通，导通的数据写入晶体管T2使数据线VD上传输的数据信号对驱动晶体管T1的栅极进行充电，以使驱动晶体管T1的栅极的电压变为：Vdata+Vth。其中，Vth代表驱动晶体管T1的阈值电压，Vdata代表数据信号的电压。并且，此阶段中，信号rst控制初始化晶体管T6和复位晶体管T7均截止。信号em控制发光控制晶体管T4和导通控制晶体管T5均截止。
在T30阶段，信号em控制发光控制晶体管T4和导通控制晶体管T5均导通。导通的发光控制晶体管T4将第一电源端VDD的电压Vdd提供给驱动 晶体管T1的第一极，以使驱动晶体管T1的第一极的电压为Vdd。驱动晶体管T1根据其栅极电压Vdata+|Vth|，以及第一极的电压Vdd，产生驱动电流。该驱动电流通过导通的导通控制晶体管T5提供给发光元件0120，驱动发光元件0120发光。并且，此阶段中，信号rst控制初始化晶体管T6和复位晶体管T7截止。信号ga控制数据写入晶体管T2和阈值补偿晶体管T3截止。
需要说明的是，在本公开实施例中，上述晶体管的第一极可以为其源极，第二极为其漏极；或第一极为其漏极，第二极为其源极，这可以根据实际应用的需求进行设计确定。并且，子像素中的像素电路除了可以为图2a和图2b所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。下面以图2a所示的结构为例进行说明。
示例性地，显示面板包括衬底基板10、设置在衬底基板10上的晶体管阵列层，位于晶体管阵列层背离衬底基板10一侧的第一平坦层，位于第一平坦层背离衬底基板10一侧的第一电极层，位于第一电极层背离衬底基板10一侧的像素限定层，位于像素限定层背离衬底基板10一侧的发光层以及位于发光层背离衬底基板10一侧的阴极。其中，晶体管阵列层可以用于形成像素电路中的晶体管和电容，以及形成扫描线、复位线、发光控制线EM、初始化线VINIT、与第一电源端VDD电连接的第一电源信号线VDD等。示例性地，晶体管阵列层可以包括有源半导体层0310、栅导电层0320、参考导电层0330以及源漏金属层0340。
示例性地，如图3与图4a示出了该像素电路0121的有源半导体层0310。有源半导体层0310可采用半导体材料通过图案化形成。有源半导体层0310可用于制作上述的驱动晶体管T1的驱动有源层T1-A、数据写入晶体管T2的有源层T2-A、阈值补偿晶体管T3的有源层T3-A、发光控制晶体管T4的有源层T4-A、导通控制晶体管T5的有源层T5-A、初始化晶体管T6的有源层T6-A和复位晶体管T7的有源层T7-A，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
示例性地，有源半导体层0310可采用非晶硅、多晶硅、氧化物半导体材 料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
示例性地，在上述的有源半导体层0310上形成有栅绝缘层，用于保护上述的有源半导体层0310。如图3、图4b以及图5a所示，示出了该像素电路0121的栅导电层0320，栅导电层0320设置在栅绝缘层背离衬底基板10一侧，从而与有源半导体层0310绝缘。栅导电层0320可以包括存储电容CST的第二极cc2、扫描线GA、复位线RST、发光控制线EM、突出部TB以及数据写入晶体管T2的栅极T2-G、阈值补偿晶体管T3的栅极T3-G、发光控制晶体管T4的栅极T4-G、导通控制晶体管T5的栅极T5-G、初始化晶体管T6的栅极T6-G和复位晶体管T7的栅极T7-G。其中，扫描线GA突出的部分形成了突出部TB。其中，一个重复单元对应至少一条扫描线GA、至少一条复位线RST以及至少一条发光控制线EM。例如，一个重复单元可以对应一条扫描线GA、一条复位线RST以及一条发光控制线EM。
例如，如图4b所示，数据写入晶体管T2的栅极T2-G可以为扫描线GA与有源半导体层0310交叠的部分，发光控制晶体管T4的栅极T4-G可以为发光控制线EM与有源半导体层0310交叠的第一部分，导通控制晶体管T5的栅极T5-G可以为发光控制线EM与有源半导体层0310交叠的第二部分，初始化晶体管T6的栅极T6-G为复位线RST与有源半导体层0310交叠的第一部分，复位晶体管T7的栅极T7-G为复位线RST与有源半导体层0310交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为扫描线GA与有源半导体层0310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从扫描线GA突出的突出部TB与有源半导体层0310交叠的部分。如图3与图4b所示，存储电容CST的第二极cc2复用为驱动晶体管T1的栅极。
需要说明的是，图5a中的各虚线示出了栅导电层0320与有源半导体层0310交叠的各个部分。
示例性地，如图3与图4b所示，扫描线GA、复位线RST和发光控制线 EM沿第一方向F1排布。且扫描线GA、复位线RST和发光控制线EM大致沿第二方向F2延伸。示例性地，扫描线GA在衬底基板10的正投影位于复位线RST在衬底基板10的正投影和发光控制线EM在衬底基板10的正投影之间。示例性地，图3仅是以第一方向F1为列方向，第二方向F2为行方向为例进行说明。在具体实施时，第一方向F1也可以为行方向，第二方向F2也可以为列方向，在此不作限定。
示例性地，在第一方向F1上，存储电容CST的第二极cc2位于扫描线GA和发光控制线EM之间。并且，从扫描线GA突出的突出部TB位于扫描线GA远离发光控制线EM的一侧。突出部TB沿与第一方向F1的箭头相反的方向从扫描线GA突出来。
示例性地，在上述的栅导电层0320上形成有层间介质层，用于保护上述的栅导电层0320。如图3、图4c以及图5b所示，示出了该像素电路120a的参考导电层0330，参考导电层0330包括存储电容CST的第一极cc1、初始化线VINIT、遮光层ZG。其中，存储电容CST的第一极cc1与存储电容CST的第二极cc2至少部分交叠以形成存储电容CST。示例性地，存储电容CST的第一极cc1具有镂空区LQ，该镂空区LQ在衬底基板10的正投影可以与存储电容CST的第二极cc2在衬底基板10的正投影具有交叠区域。
示例性地，如图3、图4c以及图5b所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的初始化晶体管T6的漏极区域(即初始化晶体管T6的漏极区域与驱动晶体管T1的栅极电连接的一侧)在衬底基板10的正投影交叠。这样可以降低光对初始化晶体管T6的影响，提高复位准确性。
示例性地，如图3、图4c以及图5b所示，阈值补偿晶体管T3为双栅晶体管。例如，遮光层ZG遮挡阈值补偿晶体管T3的两个栅极中间的有源层部分，因为阈值补偿晶体管T3直接连接驱动晶体管T1，可以起到稳定驱动晶体管T1工作状态的作用。
示例性地，在上述的参考导电层0330上形成有层间绝缘层，用于保护上述的参考导电层0330。如图3、图4d以及图5c所示，示出了该像素电路0121 的源漏金属层0340，源漏金属层0340位于层间绝缘层背离衬底基板10一侧。其中，源漏金属层0340可以包括第一电源信号线VDD、数据线VD、第一转接部ZB1、第二转接部ZB2以及阳极转接部YZ。示例性地，各子像素spx分别包括第一转接部ZB1、第二转接部ZB2以及阳极转接部YZ。
示例性地，如图3、图4d以及图5c所示，同一子像素中，阳极转接部YZ通过第二过孔GK2与导通控制晶体管的有源层的导体化区电连接。其中，第二过孔GK2贯穿层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图3、图4d以及图5c所示，第一转接部ZB1的第一端通过通孔TK01与初始化线VINIT电连接，第一转接部ZB1的第二端通过通孔TK02与有源半导体层0310中的初始化晶体管T6的源极区(如有源半导体层0310中的初始化晶体管T6的源极区和复位晶体管T7的源极区一体结构)电连接。其中，通孔TK01贯穿层间绝缘层。通孔TK02贯穿层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图3、图4d以及图5c所示，第二转接部ZB2的第一端通过通孔TK03与有源半导体层0310中的初始化晶体管T6的漏极区(初始化晶体管T6的漏极区与驱动晶体管的栅极电连接)电连接，第二转接部ZB2的第二端通过通孔TK04与存储电容CST的第二极cc2(即驱动晶体管的栅极)电连接。其中，通孔TK03贯穿层间绝缘层、层间介质层以及栅绝缘层。通孔TK04贯穿层间绝缘层和层间介质层。
示例性地，如图3、图4d以及图5c所示，阳极转接部YZ通过第二过孔GK2与有源半导体层0310中的第二发光控制电路0124的漏极区电连接。其中，第二过孔GK2贯穿层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图3、图4d以及图5c所示，数据线VD通过通孔TK05与有源半导体层0310中的数据写入晶体管T2的源极区电连接。其中，通孔TK05贯穿层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图3、图4d以及图5c所示，第一电源信号线VDD通过通孔TK06与有源半导体层0310中的发光控制晶体管T4的源极区电连接。其 中，通孔TK06贯穿层间绝缘层、层间介质层以及栅绝缘层。
示例性地，如图3、图4d以及图5c所示，第一电源信号线VDD和数据线VD沿第二方向F2排列，并且，第一电源信号线VDD和数据线VD大致沿第一方向F1延伸。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，第一电源信号线VDD和数据线VD的延伸方向只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，在上述的源漏金属层0340还可以形成有辅助绝缘层，用于保护上述的源漏金属层0340。在辅助绝缘层背离衬底基板10一侧还可以形成有辅助导电层，这样可以使辅助导电层与第一电源信号线VDD电连接，以降低第一电源信号线VDD的电阻。
示例性地，在上述的源漏金属层0340形成有第一平坦层，用于保护上述的源漏金属层0340。示例性地，如图3与图4e以及图5d所示，在第一平坦层背离形成有第一电极层。其中，第一电极层包括位于各子像素中的阳极。其中，各子像素中的阳极通过第一过孔GK1与阳极转接部YZ电连接。并且，第一过孔GK1贯穿第一平坦层。
示例性地，如图1与图4e所示，多个子像素包括沿第一方向F1相邻的第一颜色子像素spx1和第二颜色子像素spx2；其中，第一颜色子像素spx1包括阳极YG1，第二颜色子像素spx2包括阳极YG2。第一颜色子像素spx1中的第一过孔GK1在衬底基板1000的正投影位于第一颜色子像素spx1中的主体部ZT1和第二颜色子像素中的主体部ZT2在衬底基板1000的正投影之间。示例性地，针对沿第一方向F1相邻的第一颜色子像素spx1和第二颜色子像素spx2，第二颜色子像素spx2中的阳极的一边在衬底基板10的正投影面向第一颜色子像素spx1中的阳极在衬底基板10的正投影一侧具有第一凹陷AX1。且第一凹陷AX1朝向第二颜色子像素spx2的主体部的中心设置。进一步地，显示面板包括多个重复单元PX；每个重复单元PX包括至少一个第一颜色子像素spx1和至少一个第二颜色子像素spx2。例如，每个重复单元PX包括沿第一方向F1相邻的第一颜色子像素spx1和第二颜色子像素spx2，相 邻的两个重复单元具有两个第一凹陷AX1和两个第一过孔GK1；并且，在第一方向F1上，至少相邻的两个重复单元具有的两个第一凹陷AX1和两个第一过孔GK1排列于同一直线上。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，则红色子像素和绿色子像素沿第一方向F1相邻。并且，针对沿第一方向F1相邻的红色子像素和绿色子像素，绿色子像素中的阳极在衬底基板10的正投影面向红色子像素中的阳极在衬底基板10的正投影一侧具有第一凹陷AX1。
示例性地，如图1与图4e所示，各子像素中包括的像素电路的布局结构示意图沿第一方向和第二方向阵列排布。也就是说，各子像素中包括的像素电路的布局结构沿行方向和列方向周期排列。进一步地，多个重复单元PX沿第二方向F2排列形成重复单元组PXZ，重复单元组PXZ沿第一方向F1排列。并且，重复单元包括沿第一方向F1依次排列的第一颜色子像素spx1和第二颜色子像素spx2。第二颜色子像素spx2中的阳极在衬底基板10的正投影面向第一颜色子像素spx1中的阳极在衬底基板10的正投影一侧具有第一凹陷AX1，也就是说，第一凹陷AX1设置在第二颜色子像素spx2中的主体部ZT2。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，同一重复单元中，绿色子像素中的阳极在衬底基板10的正投影面向红色子像素中的阳极在衬底基板10的正投影一侧具有第一凹陷AX1。例如，一个重复单元组PXZ可以对应一条扫描线GA、一条复位线RST以及一条发光控制线EM。
示例性地，如图1与图4e所示，重复单元还包括至少一个第三颜色子像素spx3。例如，重复单元可以包括一个第三颜色子像素spx3。其中，相邻的第一颜色子像素spx1、第二颜色子像素spx2以及第三颜色子像素中的阳极之间的连线构成三角形。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，红色子像素、绿色子像素以及蓝色子像素中的阳极之间的连线构成三角形。
示例性地，如图3与图4e所示，阳极可以包括相互电连接的主体部与过孔部；其中，过孔部在衬底基板10的正投影覆盖第一过孔GK1在衬底基板10的正投影，且各子像素中，过孔部通过第一过孔GK1与阳极转接部YZ电连接。示例性地，第一颜色子像素spx1中的阳极YG1还可以包括电连接在主体部ZT1和过孔部GB1之间的第一连接部LB1，即第一颜色子像素spx1中的主体部ZT1通过第一连接部LB1与过孔部GB1电连接。第二颜色子像素spx2中的阳极YZ2还包括电连接在主体部ZT2和过孔部GB2之间的第二连接部LB2，即第二颜色子像素spx2中的主体部ZT2通过第二连接部LB2与过孔部GB2电连接。第三颜色子像素spx3中的主体部ZT3与过孔部GB3直接电连接。例如，第一颜色子像素spx1为红色子像素，则红色子像素中的主体部通过第一连接部与过孔部电连接。第二颜色子像素spx2为绿色子像素，则绿色子像素中的主体部通过第二连接部与过孔部电连接。第三颜色子像素spx3为蓝色子像素，则蓝色子像素中的主体部与过孔部直接电连接。
示例性地，如图3与图4e所示，第一连接部沿第一方向F1延伸。第二连接部沿第三方向F3延伸。其中，第三方向F3与第一方向F1和第二方向F2均不同。例如，第三方向F3分别与第一方向F1和第二方向F2具有夹角，从而可以使第二连接部斜向上方向延伸。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的主体部在衬底基板10的正投影面向第二颜色子像素spx2中的第一过孔GK1在衬底基板10的正投影一侧具有第二凹陷AX2。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，蓝色子像素中的主体部在衬底基板10的正投影面向绿色子像素中的第一过孔GK1在衬底基板10的正投影一侧具有第二凹陷AX2。
示例性地，如图3与图4e所示，同一重复单元中，第一颜色子像素spx1中的第一过孔GK1在衬底基板10的正投影位于第一颜色子像素spx1中的阳极YZ1和第二颜色子像素spx2中的阳极YZ2在衬底基板10的正投影之间。
示例性地，如图3与图4e所示，同一重复单元中，第二颜色子像素spx2中的第一过孔GK1在衬底基板10的正投影位于第一颜色子像素spx1中的过孔部GB1与第三颜色子像素spx3中的主体部ZT3在衬底基板10的正投影之间。并且第二颜色子像素spx2中的第一过孔GK1、第一颜色子像素spx1中的过孔部GB1、和第三颜色子像素spx3中的主体部ZT3在衬底基板1000上的正投影位于同一直线上，并且该直线可以与第一方向F1大致平行。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的第一过孔GK1在衬底基板10的正投影位于第二凹陷AX2在衬底基板10的正投影背离第二颜色子像素spx2中的过孔部GB2在衬底基板10的正投影的一侧。例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，红色子像素中的第一过孔GK1在衬底基板10的正投影位于红色子像素中的阳极和绿色子像素中的阳极在衬底基板10的正投影之间。绿色子像素中的第一过孔GK1在衬底基板10的正投影位于红色子像素中的过孔部与蓝色子像素中的主体部在衬底基板10的正投影之间。蓝色子像素中的第一过孔GK1在衬底基板10的正投影位于第二凹陷AX2在衬底基板10的正投影背离绿色子像素中的过孔部在衬底基板10的正投影的一侧。
示例性地，如图3与图4e所示，同一重复单元中，第二颜色子像素spx2中的阳极的第一凹陷AX1在第二方向F2上的正投影与第一颜色子像素spx1中的第一过孔GK1在第二方向F2上的正投影至少具有交叠区域；其中，第一方向F1与第二方向F2不同。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，绿色子像素中的阳极的第一凹陷AX1在第二方向F2上的正投影与红色子像素中的第一过孔GK1在第二方向F2上的正投影至少具有交叠区域。需要说明的是，在第二方向F2上的正投影指的是，绿色子像素的阳极第一凹陷AX1和红色子像素中的第一过孔GK1在第二方向F2所在的直线上的线投影，二者的线投影长度存在交叠。本申请中在第一或者第二方向的 正投影，均指的是在第一方向或者第二方向所在直线上的线投影。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的主体部的第二凹陷AX2在第一方向F1上的正投影与第二颜色子像素spx2中的第一过孔GK1在第一方向F1上的正投影至少具有交叠区域。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，蓝色子像素中的主体部的第二凹陷AX2在第一方向F1上的正投影与绿色子像素中的第一过孔GK1在第一方向F1上的正投影至少具有交叠区域。
示例性地，如图3与图4e所示，同一重复单元中，第二颜色子像素spx2中的阳极的第一凹陷AX1在第二方向F2上的正投影覆盖第一颜色子像素spx1中的第一过孔GK1在第二方向F2上的正投影。第二颜色子像素spx2中的阳极的第一凹陷AX1在第二方向F2上的正投影覆盖第一颜色子像素spx1中的过孔部GB1在第二方向F2上的正投影。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，绿色子像素中的阳极的第一凹陷AX1在第二方向F2上的正投影覆盖红色子像素中的第一过孔GK1在第二方向F2上的正投影。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的主体部ZT3的第二凹陷AX2在第一方向F1上的正投影覆盖第二颜色子像素spx2中的第一过孔GK1在第一方向F1上的正投影。第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，蓝色子像素中的主体部的第二凹陷AX2在第一方向F1上的正投影覆盖绿色子像素中的第一过孔GK1在第一方向F1上的正投影。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的主体部ZT3的第二凹陷AX2在第一方向F1上的正投影覆盖第二颜色子像素spx2中的过孔部GB2在第一方向F1上的正投影。第一颜色子像素spx1 为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，蓝色子像素中的主体部的第二凹陷AX2在第一方向F1上的正投影覆盖绿色子像素中的过孔部GB2在第一方向F1上的正投影。
示例性地，如图3与图4e所示，第二颜色子像素spx2中的主体部ZT2具有第一凹陷AX1，且同一重复单元中，第一凹陷AX1在第二方向F2上的正投影覆盖第一颜色子像素spx1中的过孔部在第二方向F2上的正投影。例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，则绿色子像素中的主体部具有第一凹陷AX1，且同一重复单元中，第一凹陷AX1在第二方向F2上的正投影覆盖红色子像素中的过孔部在第二方向F2上的正投影。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的主体部ZT3的第二凹陷AX2在第一方向F1上的正投影覆盖第二颜色子像素spx2中的过孔部ZT2在第一方向F1上的正投影。例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，则同一重复单元中，蓝色子像素中的主体部的第二凹陷AX2在第一方向F1上的正投影覆盖绿色子像素中的过孔部在第一方向F1上的正投影。
示例性地，如图3与图4e所示，第一凹陷AX1在衬底基板10的正投影的边缘与第一颜色子像素spx1中的过孔部GB1在衬底基板10的正投影的边缘大致平行。例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，第一凹陷AX1在衬底基板10的正投影的边缘与红色子像素中的过孔部在衬底基板10的正投影的边缘大致平行。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，上述平行关系只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，如图3与图4e所示，第二凹陷AX2在衬底基板10的正投影 的边缘与第二颜色子像素spx2中的主体部ZT2在衬底基板10的正投影的边缘大致平行。例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，第二凹陷AX2在衬底基板10的正投影的边缘与绿色子像素中的主体部在衬底基板10的正投影的边缘大致平行。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，上述平行关系只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，如图3与图4e所示，第一凹陷AX1在衬底基板10的正投影的边缘与第一颜色子像素spx1中的过孔部ZT1在衬底基板10的正投影的边缘之间的第一距离不小于2.5μm。例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，第一凹陷AX1在衬底基板10的正投影的边缘与红色子像素中的过孔部在衬底基板10的正投影的边缘之间的第一距离不小于2.5μm。例如，第一凹陷AX1在衬底基板10的正投影的边缘与红色子像素中的过孔部在衬底基板10的正投影的边缘之间的第一距离为2.5～20μm。例如，可以使第一距离设置为2.5μm。或者，也可以使第一距离设置为3.5μm，或者，也可以使第一距离设置为5.5μm，或者，也可以使第一距离设置为10μm，或者，也可以使第一距离设置为20μm。在实际应用中，可以结合制备工艺和设备的精度，在批量生产显示面板时，可以将第一距离设置为3.5μm。当然，在实际应用中，可以根据实际应用的需求设置第一距离的数值，在此不作限定。
示例性地，如图3与图4e所示，第二凹陷AX2在衬底基板10的正投影的边缘与第二颜色子像素spx2中的主体部ZT2在衬底基板10的正投影的边缘之间的第二距离不小于2.5μm。例如，第二凹陷AX2在衬底基板10的正投影的边缘与第二颜色子像素spx2中的主体部ZT2在衬底基板10的正投影的边缘之间的第二距离为2.5～20μm。例如，例如，第二颜色子像素spx2为绿色子像素，第一颜色子像素spx1为红色子像素，第三颜色子像素spx3为蓝色子像素，第二凹陷AX2在衬底基板10的正投影的边缘与绿色子像素中的 过孔部在衬底基板10的正投影的边缘之间的第二距离不小于2.5μm。进一步地，第二距离为2.5～20μm，可以使第二距离设置为2.5μm。或者，也可以使第二距离设置为3.5μm，或者，也可以使第二距离设置为5.5μm，或者，也可以使第二距离设置为10μm，或者，也可以使第二距离设置为20μm。在实际应用中，可以结合制备工艺和设备的精度，在批量生产显示面板时，可以将第二距离设置为3.5μm。当然，在实际应用中，可以根据实际应用的需求设置第二距离的数值，在此不作限定。
示例性地，如图3与图4e所示，晶体管阵列层包括位于各子像素中的驱动晶体管。第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，绿色子像素中的阳极在衬底基板10的正投影与红色子像素中的驱动晶体管的沟道区在衬底基板10的正投影具有交叠区域。红色子像素中的阳极在衬底基板10的正投影与各驱动晶体管的沟道区在衬底基板10的正投影不交叠。示例性地，红色子像素中的阳极在衬底基板10的正投影与红色子像素中的像素电路在衬底基板10的正投影具有交叠区域。
示例性地，如图1、图3与图4e所示，一个重复单元对应一条扫描线GA、一条复位线RST以及一条发光控制线EM。进一步地，一个重复单元组PXZ对应一条扫描线GA、一条复位线RST以及一条发光控制线EM，即一个重复单元组PXZ中的像素电路电连接同一条扫描线GA、同一条复位线RST以及同一条发光控制线EM。其中，针对同一重复单元对应的扫描线GA、复位线RST以及发光控制线EM，扫描线GA在衬底基板10的正投影位于复位线RST与发光控制线EM在衬底基板10的正投影之间。例如，针对同一重复单元组对应的扫描线GA、复位线RST以及发光控制线EM，扫描线GA在衬底基板10的正投影位于复位线RST与发光控制线EM在衬底基板10的正投影之间。
示例性地，如图1、图3与图4e所示，在一个重复单元中，复位线RST在衬底基板1000的正投影与该复位线RST控制的红色子像素中的阳极在衬底基板1000的正投影不交叠，发光控制线EM在衬底基板1000的正投影与该 发光控制线EM控制的绿色子像素中的阳极在衬底基板1000的正投影具有交叠区域，扫描线GA在衬底基板1000的正投影与该扫描线GA控制的各阳极在衬底基板1000的正投影不交叠。进一步地，在一个重复单元组PXZ中，复位线RST在衬底基板1000的正投影与该复位线RST控制的红色子像素中的阳极在衬底基板1000的正投影不交叠，发光控制线EM在衬底基板1000的正投影与该发光控制线EM控制的绿色子像素中的阳极在衬底基板1000的正投影具有交叠区域，扫描线GA在衬底基板1000的正投影与该扫描线GA控制的各阳极在衬底基板1000的正投影不交叠。进一步地，针对一个重复单元，控制该重复单元的发光控制线EM在衬底基板1000的正投影与蓝色子像素中的阳极和绿色子像素中的阳极在衬底基板1000的正投影分别具有交叠区域，控制该重复单元的复位线RST和扫描线GA在衬底基板1000的正投影与各阳极在衬底基板1000的正投影不交叠。需要说明的是，复位线RST为控制一个重复单元中的初始化晶体管T6和复位晶体管T7的信号线。发光控制线EM为控制一个重复单元中的发光控制晶体管T4和导通控制晶体管T5的信号线。扫描线GA为控制一个重复单元中的数据写入晶体管T2和阈值补偿晶体管T3的信号线。例如，针对一个重复单元组PXZ，控制重复单元组PXZ的发光控制线EM在衬底基板1000的正投影与蓝色子像素中的阳极和绿色子像素中的阳极在衬底基板1000的正投影分别具有交叠区域，控制重复单元组PXZ的复位线RST和扫描线GA在衬底基板1000的正投影与各阳极在衬底基板1000的正投影不交叠。需要说明的是，复位线RST为控制一个重复单元组中的初始化晶体管T6和复位晶体管T7的信号线。发光控制线EM为控制一个重复单元组中的发光控制晶体管T4和导通控制晶体管T5的信号线。扫描线GA为控制一个重复单元组中的数据写入晶体管T2和阈值补偿晶体管T3的信号线。
示例性地，如图1、图3与图4e所示，复位线在衬底基板10的正投影与红色子像素中的阳极在衬底基板10的正投影具有交叠区域，发光控制线在衬底基板10的正投影与绿色子像素中的阳极在衬底基板10的正投影具有交叠 区域，扫描线在衬底基板10的正投影与各阳极在衬底基板10的正投影不交叠。
示例性地，如图3与图4e所示，同一重复单元中，第三颜色子像素spx3中的阳极在衬底基板10的正投影分别与控制第三颜色子像素spx3中的像素电路的复位线和发光控制线在衬底基板10的正投影具有交叠区域。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，同一重复单元中，蓝色子像素中的阳极在衬底基板10的正投影分别与复位线和发光控制线在衬底基板10的正投影具有交叠区域。
示例性地，如图3与图4e所示，红色子像素中的第一过孔GK1和第二过孔GK2在衬底基板10的正投影具有第一交叠区域。绿色子像素中的第一过孔GK1和第二过孔GK2在衬底基板10的正投影具有第二交叠区域。蓝色子像素中的第一过孔GK1和第二过孔GK2在衬底基板10的正投影具有第三交叠区域。其中，第一交叠区域的面积不大于第二交叠区域的面积。第一交叠区域的面积不大于第三交叠区域的面积。进一步地，可以使第三交叠区域的面积小于第二交叠区域的面积大致相等。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，上述相等关系只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，第一交叠区域的面积为0～0.9μm。例如，第一交叠区域的面积也可以为0.5μm，或者，第一交叠区域的面积也可以为0.9μm。或者，第一交叠区域的面积可以为0，这样可以使红色子像素中的第一过孔GK1和第二过孔GK2在衬底基板10的正投影不交叠。
示例性地，第二交叠区域的面积为0～0.9μm。例如，第二交叠区域的面积也可以为0.5μm，或者，第二交叠区域的面积也可以为0.9μm。或者，第二交叠区域的面积可以为0，这样可以使绿色子像素中的第一过孔GK1和第二过孔GK2在衬底基板10的正投影不交叠。
示例性地，第三交叠区域的面积为0～0.9μm。例如，第三交叠区域的面 积也可以为0.5μm，或者，第三交叠区域的面积也可以为0.9μm。或者，第三交叠区域的面积可以为0，这样可以使蓝色子像素中的第一过孔GK1和第二过孔GK2在衬底基板10的正投影不交叠。
示例性地，在第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素时，可以使第二交叠区域设置的大一些，以保证蓝色子像素和绿色子像素中的阳极之间的距离，避免混色。
示例性地，如图3与图4e所示，沿第二方向F2相邻的重复单元中的第一过孔GK1大致沿第二方向F2依次排列.例如，重复单元组中的第一过孔GK1大致沿第二方向F2依次排列。示例性地，沿第二方向F2相邻的重复单元中的第一过孔GK1在第一方向F1上的正投影重叠。例如，重复单元组中的第一过孔GK1在第一方向F1上的正投影重叠。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，第一过孔GK1的排列关系只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，如图3、图4e与图4f所示，位于第一电极层背离衬底基板10一侧形成有像素限定层，像素限定层包括位于各子像素中的开口，且同一子像素中，开口在衬底基板10的正投影位于阳极在衬底基板10的正投影内。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，红色子像素具有开口KK1，绿色子像素具有开口KK2，蓝色子像素具有开口KK3。需要说明的是，各子像素中的开口所在的区域相当于发光区域。
示例性地，如图3、图4e与图4f所示，第一颜色子像素spx1和第二颜色子像素spx2中的至少一个子像素中，开口在衬底基板10的正投影为矩形。例如，第一颜色子像素spx1和第二颜色子像素spx2中的开口在衬底基板10的正投影均为矩形。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，红色子像素中的开口KK1和绿色子像素中的开口KK2在衬底基板10的正投影均为矩形。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中的开口的面积大于第二颜色子像素spx2中的开口的面积，第二颜色子像素spx2中的开口的面积大于第一颜色子像素spx1中的开口的面积。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，蓝色子像素中的开口KK3的面积大于绿色子像素中的开口KK2的面积，绿色子像素中的开口KK2的面积大于红色子像素中的开口KK1的面积。在实际应用中，各子像素中的开口面积可以与子像素的发光寿命成反比，例如，红色子像素的发光寿命大于绿色子像素的发光寿命大于蓝色子像素的发光寿命，则可以将蓝色子像素中的开口的面积大于绿色子像素中的开口的面积，绿色子像素中的开口的面积大于红色子像素中的开口的面积。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中，开口在衬底基板10的正投影面向第三颜色子像素spx3中的第一过孔GK1在衬底基板10的正投影的一侧具有开口凹陷AX0。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，在蓝色子像素中，开口KK3在衬底基板10的正投影面向第一过孔GK1在衬底基板10的正投影的一侧具有开口凹陷AX0。通过设置开口凹陷AX0可以为第一过孔GK1扇出所需要的面积，从而可以保证开口KK3中的阳极平整度较高，提高显示效果。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中，开口凹陷AX0在第一方向F1上的正投影覆盖第一过孔GK1在第一方向F1上的正投影。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，在蓝色子像素中，开口凹陷AX0在第一方向F1上的正投影覆盖第一过孔GK1在第一方向F1上的正投影。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中，开口凹陷AX0在衬底基板10的正投影的边缘与第一过孔GK1在衬底基板10的正 投影的边缘大致平行。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，在蓝色子像素中，开口凹陷AX0在衬底基板10的正投影的边缘与第一过孔GK1在衬底基板10的正投影的边缘大致平行。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，上述平行关系只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中，开口凹陷AX0在衬底基板10的正投影的边缘与第一过孔GK1在衬底基板10的正投影的边缘之间的第三距离不小于2.25μm。进一步地，第三距离为2.25～20μm。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，在蓝色子像素中，开口凹陷AX0在衬底基板10的正投影的边缘与第一过孔GK1在衬底基板10的正投影的边缘之间的第三距离不小于2.25μm。示例性地，可以使第三距离设置为2.25μm。或者，也可以使第三距离设置为2.5μm。或者，也可以使第三距离设置为20μm。在实际应用中，可以结合制备工艺和设备的精度，在批量生产显示面板时，可以将第三距离设置为2.5μm。当然，在实际应用中，可以根据实际应用的需求设置第三距离的数值，在此不作限定。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中，阳极YG3的主体部ZT3在衬底基板1000的正投影面向第三颜色子像素spx3的阳极YG3的第一过孔GK1在衬底基板1000的正投影的一侧具有第三凹陷AX3，且第三凹陷AX3与开口凹陷AX0大致平行。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，在蓝色子像素中，阳极YG3的主体部ZT3在衬底基板1000的正投影面向第三颜色子像素spx3的阳极YG3的第一过孔GK1在衬底基板1000的正投影的一侧具有第三凹陷AX3，且第三凹陷AX3与开口凹陷AX0大致平行。
示例性地，如图3、图4e与图4f所示，第三颜色子像素spx3中，第三 凹陷AX3在衬底基板1000的正投影的边缘与开口凹陷AX0在衬底基板1000的正投影的边缘重叠。例如，第一颜色子像素spx1为红色子像素，第二颜色子像素spx2为绿色子像素，第三颜色子像素spx3为蓝色子像素，在蓝色子像素中，第三凹陷AX3在衬底基板1000的正投影的边缘与开口凹陷AX0在衬底基板1000的正投影的边缘重叠。
示例性地，如图3、图4e与图4f所示，位于像素限定层背离衬底基板10一侧形成有隔垫物层，隔垫物层包括间隔设置的多个隔垫物PS。沿第一方向F1相邻的第三子像素中的阳极之间设置有一个隔垫物PS。
需要说明的是，上述各过孔和各通孔的形成可以为圆形，正方形，八边形等，其可以根据实际应用的需求进行设计，在此不作限定。
在一些示例中，如图6所示，也可以使第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素。此时，可以使第一方向F1为子像素的行方向，第二方向F2为子像素的列方向。重复单元包括沿第一方向F1依次排列的绿色子像素和蓝色子像素。并且重复单元还可以包括红色子像素；其中，红色子像素和绿色子像素沿第二方向F2排列。其中，蓝色子像素中的阳极在衬底基板10的正投影面向绿色子像素中的阳极在衬底基板10的正投影一侧具有第一凹陷AX1。
在一些示例中，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，如图6所示，同一重复单元中，绿色子像素中的第一过孔GK1在衬底基板10的正投影位于绿色子像素中的阳极和蓝色子像素中的阳极在衬底基板10的正投影之间。
在一些示例中，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，如图6所示，同一重复单元中，蓝色子像素中的阳极的第一凹陷AX1在第二方向F2上的正投影与绿色子像素中的第一过孔GK1在第二方向F2上的正投影至少具有交叠区域。
在一些示例中，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，如图6所示，同一重复单元中，蓝色子像素中的阳极的第 一凹陷AX1在第二方向F2上的正投影覆盖绿色子像素中的第一过孔GK1在第二方向F2上的正投影。
在一些示例中，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，如图6所示，蓝色子像素中的主体部具有第一凹陷AX1，且同一重复单元中，第一凹陷AX1在第二方向F2上的正投影覆盖绿色子像素中的过孔部在第二方向F2上的正投影。
在一些示例中，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，如图6所示，第一凹陷AX1在衬底基板10的正投影的边缘与绿色子像素中的过孔部在衬底基板10的正投影的边缘大致平行。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素例如布线或过孔的设置，上述平行关系只要大致满足上述条件即可，均属于本发明的保护范围。
在一些示例中，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，如图6所示，第一凹陷AX1在衬底基板10的正投影的边缘与绿色子像素中的过孔部在衬底基板10的正投影的边缘之间的第一距离不小于2.5μm。进一步地，第一距离可以为2.5～20μm。例如，第一距离可以为2.5μm。或者，第一距离也可以为3.5μm。或者，第一距离也可以为20μm，在此不作限定。
需要说明的是，第一颜色子像素spx1为绿色子像素，第二颜色子像素spx2为蓝色子像素时，重复单元中的红色子像素的设置方式可以参照上述红色子像素的设置方式，在此不作赘述。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了 基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (37)

  1. 一种显示面板，其中，包括：
    衬底基板，包括多个子像素：
    晶体管阵列层，位于所述衬底基板上，且所述晶体管阵列层包括位于各所述子像素中的阳极转接部；
    第一平坦层，位于所述晶体管阵列层背离所述衬底基板一侧；
    第一电极层，位于所述第一平坦层背离所述衬底基板一侧，所述第一电极层包括位于各所述子像素中的阳极；其中，所述阳极包括相互电连接的主体部与过孔部；且各所述子像素中的过孔部通过第一过孔与所述阳极转接部电连接；所述第一过孔贯穿所述第一平坦层；
    其中，所述多个子像素包括沿第一方向相邻的第一颜色子像素和第二颜色子像素；所述第一颜色子像素中的第一过孔在所述衬底基板的正投影位于所述第一颜色子像素中的主体部和所述第二颜色子像素中的主体部在所述衬底基板的正投影之间；
    针对沿所述第一方向相邻的第一颜色子像素和第二颜色子像素，所述第二颜色子像素中的阳极的一边在所述衬底基板的正投影面向所述第一颜色子像素中的阳极在所述衬底基板的正投影一侧具有第一凹陷；且所述第一凹陷朝向所述第二颜色子像素的主体部的中心设置；
    所述显示面板包括多个重复单元，每个所述重复单元包括至少一个所述第一颜色子像素和至少一个所述第二颜色子像素；
    相邻的两个所述重复单元至少具有两个所述第一凹陷和两个所述第一过孔；并且，在所述第一方向上，至少相邻的两个所述重复单元具有的两个第一凹陷和第一过孔排列于同一直线上。
  2. 如权利要求1所述的显示面板，其中，同一所述重复单元中，所述第二颜色子像素中的阳极的第一凹陷在第二方向上的正投影覆盖所述第一颜色子像素中的第一过孔在所述第二方向上的正投影。
  3. 如权利要求2所述的显示面板，其中，同一所述子像素中，所述过孔部在所述衬底基板的正投影覆盖所述第一过孔在所述衬底基板的正投影；
    所述第一凹陷设置在所述第二颜色子像素中的主体部，且第一凹陷在所述第二方向上的正投影覆盖所述第一颜色子像素中的过孔部在所述第二方向上的正投影。
  4. 如权利要求3所述的显示面板，其中，所述第一凹陷在所述衬底基板的正投影的边缘与所述第一颜色子像素中的过孔部在所述衬底基板的正投影的边缘大致平行。
  5. 如权利要求4所述的显示面板，其中，所述第一凹陷在所述衬底基板的正投影的边缘与所述第一颜色子像素中的过孔部在所述衬底基板的正投影的边缘之间的第一距离为2.5～20μm。
  6. 如权利要求1-5任一项所述的显示面板，其中，所述第一颜色子像素为红色子像素，所述第二颜色子像素为绿色子像素；
    所述晶体管阵列层包括位于各所述子像素中的驱动晶体管；所述绿色子像素中的阳极在所述衬底基板的正投影与所述红色子像素中的驱动晶体管的沟道区在所述衬底基板的正投影具有交叠区域。
  7. 如权利要求6所述的显示面板，其中，所述红色子像素中的阳极在所述衬底基板的正投影与各所述驱动晶体管的沟道区在所述衬底基板的正投影不交叠。
  8. 如权利要求7所述的显示面板，其中，所述晶体管阵列层包括：相互间隔设置的多条扫描线、多条复位线以及多条发光控制线；其中，一个所述重复单元对应至少一条所述扫描线、至少一条所述复位线以及至少一条所述发光控制线；
    在一个所述重复单元中，所述复位线在所述衬底基板的正投影与所述复位线控制的所述红色子像素中的阳极在所述衬底基板的正投影不交叠，所述发光控制线在所述衬底基板的正投影与所述发光控制线控制的所述绿色子像素中的阳极在所述衬底基板的正投影具有交叠区域，所述扫描线在所述衬底 基板的正投影与所述扫描线控制的各所述阳极在所述衬底基板的正投影不交叠。
  9. 如权利要求6-8任一项所述的显示面板，其中，所述晶体管阵列层还包括位于各所述子像素中的导通控制晶体管的有源层；且同一所述子像素中，所述阳极转接部通过第二过孔与所述导通控制晶体管的有源层的导体化区电连接；
    所述红色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第一交叠区域；
    所述绿色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第二交叠区域；
    所述第一交叠区域的面积不大于所述第二交叠区域的面积。
  10. 如权利要求9所述的显示面板，其中，所述第一交叠区域的面积为0～0.9μm；所述第二交叠区域的面积为0～0.9μm。
  11. 如权利要求1-5任一项所述的显示面板，其中，所述第一颜色子像素为绿色子像素，所述第二颜色子像素为蓝色子像素；
    所述蓝色子像素中的阳极在所述衬底基板的正投影与所述绿色子像素中的驱动晶体管的沟道区在所述衬底基板的正投影具有交叠区域。
  12. 如权利要求11所述的显示面板，其中，同一所述蓝色子像素中，所述阳极在所述衬底基板的正投影与所述驱动晶体管的沟道区在所述衬底基板的正投影具有交叠区域。
  13. 如权利要求12所述的显示面板，其中，针对一个所述重复单元，控制所述重复单元的发光控制线在所述衬底基板的正投影与所述蓝色子像素中的阳极和绿色子像素中的阳极在所述衬底基板的正投影分别具有交叠区域，控制所述重复单元的复位线和扫描线在所述衬底基板的正投影与各所述阳极在所述衬底基板的正投影不交叠。
  14. 如权利要求11-13任一项所述的显示面板，其中，所述绿色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第二交叠区域，所述蓝 色子像素中的第一过孔和第二过孔在所述衬底基板的正投影具有第三交叠区域，所述第三交叠区域的面积为0-9μm 2。
  15. 如权利要求14所述的显示面板，其中，所述第三交叠区域的面积小于等于所述第二交叠区域的面积。
  16. 如权利要求2-8任一项所述的显示面板，其中，所述重复单元还包括至少一个第三颜色子像素；
    相邻的所述第一颜色子像素、所述第二颜色子像素以及所述第三颜色子像素中的阳极之间的连线构成三角形。
  17. 如权利要求16所述的显示面板，其中，同一所述重复单元中，所述第二颜色子像素中的第一过孔在所述衬底基板的正投影位于所述第一颜色子像素中的过孔部与所述第三颜色子像素中的主体部在所述衬底基板的正投影之间，并且所述第二颜色子像素中的第一过孔、所述第一颜色子像素中的过孔部、和所述第三颜色子像素中的主体部在所述衬底基板上的正投影位于同一直线上，所述直线与所述第一方向大致平行。
  18. 如权利要求17所述的显示面板，其中，同一所述重复单元中，所述第三颜色子像素中的主体部在所述衬底基板的正投影面向所述第二颜色子像素中的第一过孔在所述衬底基板的正投影一侧具有第二凹陷。
  19. 如权利要求18所述的显示面板，其中，同一所述重复单元中，所述第三颜色子像素中的主体部的第二凹陷在所述第一方向上的正投影与所述第二颜色子像素中的第一过孔在所述第一方向上的正投影至少具有交叠区域。
  20. 如权利要求19所述的显示面板，其中，同一所述重复单元中，所述第三颜色子像素中的主体部的第二凹陷在所述第一方向上的正投影覆盖所述第二颜色子像素中的第一过孔在所述第一方向上的正投影。
  21. 如权利要求20所述的显示面板，其中，同一所述重复单元中，所述第三颜色子像素中的主体部的第二凹陷在所述第一方向上的正投影覆盖所述第二颜色子像素中的过孔部在所述第一方向上的正投影。
  22. 如权利要求21所述的显示面板，其中，所述第二凹陷在所述衬底基 板的正投影的边缘与所述第二颜色子像素中的主体部在所述衬底基板的正投影的边缘大致平行。
  23. 如权利要求22所述的显示面板，其中，所述第二凹陷在所述衬底基板的正投影的边缘与所述第二颜色子像素中的主体部在所述衬底基板的正投影的边缘之间的第二距离为2.5～20μm。
  24. 如权利要求16-23任一项所述的显示面板，其中，所述第三颜色子像素中的第一过孔在所述衬底基板的正投影位于所述第二凹陷在所述衬底基板的正投影背离所述第二颜色子像素中的过孔部在所述衬底基板的正投影的一侧。
  25. 如权利要求3-24任一项所述的显示面板，其中，所述第一颜色子像素中的阳极还包括电连接在主体部和过孔部之间的第一连接部；
    所述第一连接部沿所述第一方向延伸。
  26. 如权利要求3-25任一项所述的显示面板，其中，所述第二颜色子像素中的阳极还包括电连接在主体部和过孔部之间的第二连接部；
    所述第二连接部沿第三方向延伸；
    所述第三方向与所述第一方向和所述第二方向均不同。
  27. 如权利要求16-26任一项所述的显示面板，其中，同一所述重复单元中，所述第三颜色子像素中的阳极在所述衬底基板的正投影分别与控制所述重复单元中的像素电路的复位线和发光控制线在所述衬底基板的正投影具有交叠区域。
  28. 如权利要求16-27任一项所述的显示面板，其中，沿所述第二方向相邻的所述重复单元中的所述第一过孔大致沿第二方向依次排列。
  29. 如权利要求28所述的显示面板，其中，沿所述第二方向相邻的所述重复单元中的所述第一过孔在第一方向上的正投影重叠。
  30. 一种显示面板，其中，包括：
    衬底基板，包括多个子像素：
    晶体管阵列层，位于所述衬底基板上，且所述晶体管阵列层包括位于各 所述子像素中的阳极转接部；
    第一平坦层，位于所述晶体管阵列层背离所述衬底基板一侧；
    第一电极层，位于所述第一平坦层背离所述衬底基板一侧，所述第一电极层包括位于各所述子像素中的阳极，且各所述子像素中的阳极通过第一过孔与所述阳极转接部电连接；所述第一过孔贯穿所述第一平坦层；各所述阳极包括主体部和过孔部；
    像素限定层，位于所述第一电极层背离所述衬底基板一侧；所述像素限定层包括位于各所述子像素中的开口，且同一所述子像素中，所述开口在所述衬底基板的正投影位于所述阳极在所述衬底基板的正投影内；
    其中，所述多个子像素包括第三颜色子像素；所述第三颜色子像素中，所述开口在所述衬底基板的正投影面向所述第三颜色子像素中的第一过孔在所述衬底基板的正投影的一侧具有开口凹陷；
    所述第三颜色子像素中，所述阳极的主体部在所述衬底基板的正投影面向所述第三颜色子像素的阳极的第一过孔在所述衬底基板的正投影的一侧具有第三凹陷，且所述第三凹陷与所述开口凹陷大致平行。
  31. 如权利要求30所述的显示面板，其中，所述第三颜色子像素中，所述开口凹陷在所述第一方向上的正投影覆盖所述第一过孔在所述第一方向上的正投影。
  32. 如权利要求31所述的显示面板，其中，所述第三颜色子像素中，所述开口凹陷在所述衬底基板的正投影的边缘与所述第一过孔在所述衬底基板的正投影的边缘大致平行。
  33. 如权利要求32所述的显示面板，其中，所述第三颜色子像素中，所述开口凹陷在所述衬底基板的正投影的边缘与所述第一过孔在所述衬底基板的正投影的边缘之间的第三距离为2.25～20μm。
  34. 如权利要求30-33任一项所述的显示面板，其中，所述第三颜色子像素中，所述第三凹陷在所述衬底基板的正投影的边缘与所述开口凹陷在所述衬底基板的正投影的边缘重叠。
  35. 如权利要求30-34任一项所述的显示面板，其中，所述多个子像素还包括：第一颜色子像素和第二颜色子像素；
    所述第一颜色子像素和所述第二颜色子像素中的至少一个子像素中，所述开口在所述衬底基板的正投影为矩形。
  36. 如权利要求35所述的显示面板，其中，所述第三颜色子像素中的开口的面积大于所述第二颜色子像素中的开口的面积；
    所述第二颜色子像素中的开口的面积大于所述第一颜色子像素中的开口的面积。
  37. 一种显示装置，其中，包括如权利要求1-36任一项所述的显示面板。
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