WO2022041203A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022041203A1
WO2022041203A1 PCT/CN2020/112495 CN2020112495W WO2022041203A1 WO 2022041203 A1 WO2022041203 A1 WO 2022041203A1 CN 2020112495 W CN2020112495 W CN 2020112495W WO 2022041203 A1 WO2022041203 A1 WO 2022041203A1
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WIPO (PCT)
Prior art keywords
sub
base substrate
pixel
orthographic projection
anode
Prior art date
Application number
PCT/CN2020/112495
Other languages
English (en)
French (fr)
Inventor
尚庭华
张毅
青海刚
于鹏飞
杨路路
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080001760.8A priority Critical patent/CN114730795A/zh
Priority to US17/312,983 priority patent/US20220320213A1/en
Priority to PCT/CN2020/112495 priority patent/WO2022041203A1/zh
Publication of WO2022041203A1 publication Critical patent/WO2022041203A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • a plurality of sub-pixels at least one sub-pixel in the plurality of sub-pixels includes: a pixel circuit and a light-emitting element located on the base substrate, the pixel circuit includes a driving transistor for driving the light-emitting element to emit light;
  • the display substrate includes an active semiconductor layer; the driving active layer of the driving transistor is located in the active semiconductor layer;
  • the drive gate in the drive transistor is electrically connected to the active semiconductor layer through a drive via hole;
  • a first conductive layer located on the side of the active semiconductor layer away from the base substrate, and the first conductive layer includes an anode transfer part and a signal line spaced apart from each other;
  • the orthographic projection of at least part of the driving via hole on the base substrate does not overlap with the orthographic projection of the anode transfer portion and the signal line on the base substrate, respectively.
  • the display substrate further includes:
  • a first insulating layer located on the side of the first conductive layer away from the base substrate, and the first insulating layer includes a first via hole, and the first via hole exposes at least a part of the anode transfer part ;
  • the light-emitting element includes an anode, the anode is located on the side of the first insulating layer away from the base substrate, and the anode includes a main part and an auxiliary part that are electrically connected to each other; wherein, the auxiliary part passes through the the first via hole is electrically connected to the anode adapter;
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel
  • the orthographic projection of the anode transition portion on the base substrate does not overlap with the orthographic projection of the driving active layer on the base substrate, and the main body portion is located on the base substrate.
  • the orthographic projection of the base substrate does not overlap with the orthographic projection of the anode transfer portion on the base substrate;
  • the orthographic projection of the anode transfer portion on the base substrate overlaps with the orthographic projection of the driving active layer on the base substrate, and the main body portion is on the base substrate.
  • the orthographic projection of the base substrate overlaps with the orthographic projection of the anode transition portion on the base substrate.
  • the anode transition part in the second sub-pixel includes: a first sub-anode transition part and a second sub-anode transition part that are electrically connected to each other; wherein the first sub-anode transition part
  • the connecting portion has a hollow structure, and the second sub-anode transfer portion has a solid structure; the auxiliary portion is electrically connected to the second sub-anode transfer portion through the first via hole;
  • the orthographic projection of the first sub-anode transfer portion on the base substrate overlaps the orthographic projection of the driving active layer on the base substrate.
  • the display substrate further includes: a gate conductive layer located between the active semiconductor layer and the first conductive layer, the gate conductive layer including: scan lines;
  • the orthographic projection of the scan line on the base substrate is located at the orthographic projection of the driving active layer on the base substrate on the side of the orthographic projection of the base substrate away from the second sub-anode adapter;
  • the orthographic projection of the first sub-anode transfer portion on the base substrate overlaps the orthographic projection of the scan line on the base substrate.
  • the orthographic projection of the hollowed-out region in the hollowed-out structure in the first sub-anode transfer portion on the base substrate and the driving via on the substrate overlap.
  • the first sub-anode adapter has a first sub- adapter and a second sub- adapter disposed oppositely;
  • the orthographic projection of the main body portion on the base substrate overlaps with the orthographic projection of the two signal lines on the base substrate; and in the first direction, the first sub-pixel
  • the orthographic projection of the switching portion on the base substrate is located between the second sub-switching portion and the orthographic projection of the two signal lines on the base substrate.
  • At least one of the plurality of repeating units includes: a first color subpixel, a second color subpixel, a third color subpixel, and a fourth color subpixel; wherein the plurality of repeating units are along the The first direction is arranged to form a repeating unit group, and the repeating unit group is arranged along a second direction, and the first direction is different from the second direction;
  • the first subpixel includes the first color subpixel
  • the second subpixel includes at least one of a second color subpixel, a third color subpixel, and the fourth color subpixel.
  • the second subpixel includes the second color subpixel
  • the orthographic projection of the main body portion on the base substrate overlaps the orthographic projection of the first sub-anode transition portion on the base substrate.
  • the orthographic projection of the main body portion on the base substrate is the same as that of the first sub-transit portion and the second sub-transition portion on the substrate.
  • the orthographic projections of the substrates all overlap.
  • the body portion in the second color sub-pixel has a second body axis of symmetry along the second direction
  • the center line of the part of the two signal lines that overlaps with the orthographic projection of the main body part on the base substrate along the second direction is the same as that of the first sub-pixel.
  • the centerlines of the transfer part and the second sub-transfer part along the first direction are respectively located on opposite sides of the symmetry axis of the second main body.
  • the second subpixel includes the fourth color subpixel
  • the orthographic projection of the main body portion on the base substrate overlaps the orthographic projection of the second sub-anode adapter portion on the base substrate, and the main body portion is in the base substrate.
  • the orthographic projection of the base substrate overlaps the orthographic projection of the two signal lines on the base substrate.
  • the orthographic projection of at least part of the main body portion on the base substrate is located where the second sub-anode transition portion is located.
  • the orthographic projection of the base substrate is away from the first sub-anode transfer part and is on a side of the orthographic projection of the base substrate.
  • the body portion in the fourth color sub-pixel has a fourth body axis of symmetry along the second direction
  • the part where the two signal lines overlap with the orthographic projection of the main body part on the base substrate, along the center line in the second direction, is the same as the second sub-pixel.
  • the centerlines of the anode adapter parts along the second direction are respectively located on opposite sides of the symmetry axis of the fourth body.
  • each of the signal lines further includes a signal protrusion;
  • the plurality of signal lines include a first signal line and a second signal line; wherein one column of sub-pixels corresponds to one of the first signal lines and one of all the signal lines.
  • the second signal line; the signal raised parts of the first signal line are respectively electrically connected to the sub-pixels in odd-numbered rows, and the signal raised parts of the second signal line are respectively electrically connected to the sub-pixels of even-numbered rows;
  • the second color sub-pixel and the fourth color sub-pixel in adjacent repeating units along the second direction are adjacent along the second direction;
  • each of the signal lines further includes a signal protrusion;
  • the plurality of signal lines include a first signal line and a second signal line; wherein one column of sub-pixels corresponds to one of the first signal lines and one of all the signal lines.
  • the second signal line; the signal raised parts of the first signal line are respectively electrically connected to the sub-pixels in odd-numbered rows, and the signal raised parts of the second signal line are respectively electrically connected to the sub-pixels of even-numbered rows;
  • two of the first signal lines are adjacent to form a first signal line group, or, two of the second signal lines A second signal line group is formed adjacently.
  • the area of the orthographic projection of the second sub-anode transition part in one of the fourth-color sub-pixels on the base substrate is larger than that of the second sub-anode transition in one of the second-color sub-pixels The area of the part in the orthographic projection of the base substrate.
  • the second sub-anode transition portion in the second color sub-pixel has a second width along the second direction in the orthographic projection of the base substrate, and the fourth color sub-pixel has a second width.
  • the second sub-anode transfer portion has a fourth width along the second direction in the orthographic projection of the base substrate; the fourth width is greater than the second width.
  • the second subpixel includes the third color subpixel
  • the orthographic projection of the main body portion on the base substrate overlaps with the orthographic projection of the first sub-anode adapter portion on the base substrate, and the main body portion is on the base substrate.
  • the orthographic projection of the base substrate overlaps the orthographic projection of the two signal lines on the base substrate.
  • the orthographic projection of the main body portion on the base substrate is the same as that of the first sub-transit portion and the second sub-transition portion on the substrate.
  • the orthographic projections of the substrates all overlap.
  • the body portion in the third color sub-pixel has a third body axis of symmetry along the second direction;
  • the portion of the two signal lines that overlap with the orthographic projection of the main body portion on the base substrate, along the center line in the second direction, is the same as the first sub-pixel.
  • the centerlines of the transfer portion and the second sub-transfer portion along the second direction are respectively located on opposite sides of the symmetry axis of the third body.
  • the orthographic projection of the main body portion on the base substrate covers the orthographic projection of the signal protrusion portion on the base substrate.
  • the signal raised portion is located on a side of the first sub-anode transfer portion away from the second sub-anode transfer portion.
  • the orthographic projection of the main body portion on the base substrate overlaps the orthographic projection of the two signal lines on the base substrate, and the main body The orthographic projection of a portion on the base substrate does not overlap with the orthographic projection of the anode transfer portion and the signal protrusion portion on the base substrate.
  • the body portion in the first color sub-pixel has a first body axis of symmetry along the second direction;
  • the two signal lines overlapping with the orthographic projection of the main body portion on the base substrate are respectively located at the symmetric axis of the first main body. opposite sides.
  • the distance in the first direction of the first sub-transition part and the second sub-transition part in the same first sub-anode transition part is the same as that of the two signal lines in the first sub-transition part.
  • the distance ratio in one direction is 0.8 to 1.2.
  • the signal lines are configured as data lines that transmit data signals.
  • a display device provided by an embodiment of the present disclosure includes the above-mentioned display substrate.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2a is a schematic structural diagram of some pixel circuits according to an embodiment of the present disclosure.
  • FIG. 2b is a signal timing diagram provided by an embodiment of the present disclosure.
  • FIG. 2c is a schematic structural diagram of some pixel circuits according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the layout structure of some display substrates according to an embodiment of the present disclosure.
  • FIG. 4a is a schematic diagram of a layout structure of an active semiconductor layer provided by an embodiment of the present disclosure.
  • 4b is a schematic diagram of a layout structure of a gate conductive layer provided by an embodiment of the present disclosure
  • FIG. 4c is a schematic diagram of a layout structure of a reference conductive layer provided by an embodiment of the present disclosure.
  • FIG. 4d is a schematic diagram of a layout structure of a source-drain metal layer according to an embodiment of the present disclosure
  • FIG. 4e is a schematic diagram of a layout structure of a first conductive layer provided by an embodiment of the present disclosure.
  • FIG. 4f is a schematic diagram of the layout structure of the anode layer provided by the embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of the layout structure of further display substrates according to an embodiment of the present disclosure.
  • Figure 6a is a schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure shown in Figure 5;
  • Figure 6b is a schematic cross-sectional structure diagram along the BB' direction in the schematic layout structure shown in Figure 5;
  • Figure 6c is a schematic cross-sectional structure diagram along the CC' direction in the schematic layout structure shown in Figure 5;
  • FIG. 6d is a schematic cross-sectional structural diagram along the DD' direction in the schematic layout structure shown in FIG. 5 .
  • the display substrate provided by the embodiment of the present disclosure may include: a base substrate 10 .
  • the plurality of repeating units PX on the base substrate 10, at least one repeating unit PX (eg, each repeating unit) of the plurality of repeating units PX may include a plurality of sub-pixels spx.
  • the plurality of sub-pixels may include a first-color sub-pixel spx1, a second-color sub-pixel spx2, a third-color sub-pixel spx3, and a fourth-color sub-pixel spx4.
  • the repeating unit may include the first color subpixel spx1, the second color subpixel spx2, the third color subpixel spx3, and the fourth color subpixel spx4.
  • the display substrate can use the first color sub-pixel spx1, the second color sub-pixel spx2, the third color sub-pixel spx3 and the fourth color sub-pixel spx4 for light mixing, so as to realize color display.
  • the first color, the second color, the third color, and the fourth color may be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue
  • the fourth color is green.
  • the embodiments of the present disclosure include but are not limited to this.
  • the repeating unit includes a first color sub-pixel spx1, a second color sub-pixel spx2, a third color sub-pixel spx3 and a fourth color sub-pixel spx4, and the second and fourth colors are green, and the first color is red,
  • the third color is blue as an example for description.
  • a plurality of repeating units are arranged along the first direction F1 to form a repeating unit group PXZ, and the repeating unit group PXZ is arranged along the second direction F2.
  • the first direction F1 is different from the second direction F2.
  • the first direction F1 is perpendicular to the second direction F2.
  • the first direction F1 is the row direction
  • the second direction F2 is the column direction
  • the first direction F1 is the column direction
  • the second direction F2 is the row direction.
  • At least one sub-pixel spx (eg, each sub-pixel) in the plurality of sub-pixels spx may include: a pixel circuit 0121 and a light-emitting element 0120 .
  • the pixel circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the anode of the light-emitting element 0120 .
  • a corresponding voltage is applied to the cathode of the light-emitting element 0120, so that the light-emitting element 0120 can be driven to emit light.
  • the pixel circuit 0121 may include: a driving control circuit 0122, a first lighting control circuit 0123, a second lighting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128 and a reset circuit 0129.
  • the driving control circuit 0122 may include a control terminal, a first terminal and a second terminal. And the drive control circuit 0122 is configured to provide the light-emitting element 0120 with a drive current for driving the light-emitting element 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the first light-emitting control circuit 0123 is configured to turn on or off the connection between the driving control circuit 0122 and the first voltage terminal VDD.
  • the second light-emitting control circuit 0124 is electrically connected to the second terminal of the driving control circuit 0122 and the anode of the light-emitting element 0120 . And the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting element 0120 to be turned on or off.
  • the data writing circuit 0126 is electrically connected to the first terminal of the driving control circuit 0122 . And the data writing circuit 0126 is configured to write the signal on the data line VD into the memory circuit 0127 .
  • the storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store the data signal and the information of the drive control circuit 0122 .
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the driving control circuit 0122, respectively. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the drive control circuit 0122 .
  • the reset circuit 0129 is also electrically connected to the control terminal of the drive control circuit 0122 and the anode of the light-emitting element 0120, respectively. And the reset circuit 0129 is configured to reset the anode of the light-emitting element 0120 and reset the control terminal of the drive control circuit 0122.
  • the light-emitting element 0120 can be set as an electroluminescent diode, such as at least one of OLED, QLED, micro LED, and mini OLED.
  • the light-emitting element 0120 may include a stacked anode, a light-emitting layer, and a cathode. Further, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the light-emitting element 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited herein.
  • the drive control circuit 0122 includes a drive transistor T1
  • the control end of the drive control circuit 0122 includes the drive gate of the drive transistor T1
  • the first end of the drive control circuit 0122 includes the first end of the drive transistor T1.
  • One pole, the second terminal of the driving control circuit 0122 includes the second pole of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2.
  • the storage circuit 0127 includes a storage capacitor CST.
  • Threshold compensation circuit 0128 includes threshold compensation transistor T3.
  • the first light emission control circuit 0123 includes a first light emission control transistor T4.
  • the second light emission control circuit 0124 includes a second light emission control transistor T5.
  • the reset circuit 0129 includes an initialization transistor T6 and a reset transistor T7.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1
  • the second pole of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal
  • the data writing transistor T1 The gate of T2 is configured to be electrically connected to the scan line GA to receive a signal.
  • the first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second pole of the storage capacitor CST is electrically connected to the driving gate of the driving transistor T1.
  • the first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the driving transistor T1
  • the second pole of the threshold compensation transistor T3 is electrically connected to the driving gate of the driving transistor T1
  • the gate of the threshold compensation transistor T3 is configured to be connected to the scanning Line GA is electrically connected to receive the signal.
  • the first pole of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT to receive the reset signal
  • the second pole of the initialization transistor T6 is electrically connected to the drive gate of the drive transistor T1
  • the gate of the initialization transistor T6 is configured to be connected to the reset signal.
  • Line RST is electrically connected to receive the signal.
  • the first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT to receive a reset signal
  • the second pole of the reset transistor T7 is electrically connected to the anode of the light emitting element 0120
  • the gate of the reset transistor T7 is configured to be connected to the reset line RST Electrically connected to receive signals.
  • the first electrode of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT1 to receive the first reset signal
  • the second electrode of the initialization transistor T6 is electrically connected to the drive gate of the drive transistor T1
  • the initialization The gate of transistor T6 is configured to be electrically connected to reset line RST to receive a signal.
  • the first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT2 to receive the second reset signal
  • the second pole of the reset transistor T7 is electrically connected to the anode of the light-emitting element 0120
  • the gate of the reset transistor T7 is configured to be connected to the reset Line RST is electrically connected to receive the signal.
  • the initialization transistor T6 and the reset transistor T7 can respectively receive different reset signals.
  • the first electrode of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light-emitting control transistor T4 is electrically connected. It is configured to be electrically connected to the lighting control line EM to receive the lighting control signal.
  • the first electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the second light-emitting control transistor T5 is electrically connected to the anode of the light-emitting element 0120
  • the gate of the second light-emitting control transistor T5 is It is configured to be electrically connected to the lighting control line EM to receive the lighting control signal.
  • the cathode of the light-emitting element 0120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage, for example, the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant first voltage
  • the second voltage for example, the second voltage is 0 or a negative voltage, or the like.
  • the second power supply terminal VSS may be grounded.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 2a is shown in FIG. 2b.
  • the working process of the pixel circuit has three stages: T10 stage, T20 stage, and T30 stage.
  • rst represents the signal transmitted on the reset line RST
  • ga represents the signal transmitted on the scan line GA
  • em represents the signal transmitted on the light-emitting control line EM.
  • the signal rst controls the initialization transistor T6 to be turned on, so that the signal transmitted on the initialization line VINIT can be provided to the driving gate of the driving transistor T1 to reset the driving gate of the driving transistor T1.
  • the signal rst controls the reset transistor T7 to be turned on, so as to supply the signal transmitted on the initialization line VINIT to the anode of the light-emitting element 0120 to reset the anode of the light-emitting element 0120 .
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned off.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, and the turned-on data writing transistor T2 makes the data signal transmitted on the data line VD charge the driving gate of the driving transistor T1, so that the driving gate of the driving transistor T1 is charged.
  • the voltage of the drive gate of the drive transistor T1 becomes: Vdata+Vth.
  • Vth represents the threshold voltage of the driving transistor T1
  • Vdata represents the voltage of the data signal.
  • the signal rst controls both the initialization transistor T6 and the reset transistor T7 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on.
  • the turned-on first light-emitting control transistor T4 supplies the voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T1, so that the voltage of the first electrode of the driving transistor T1 is Vdd.
  • the driving transistor T1 generates a driving current according to the gate voltage Vdata+
  • the driving current is supplied to the light-emitting element 0120 through the turned-on second light-emitting control transistor T5, and the light-emitting element 0120 is driven to emit light.
  • the signal rst controls the initialization transistor T6 and the reset transistor T7 to be turned off.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the first electrode of the above-mentioned transistor may be its source electrode, and the second electrode may be its drain electrode; or the first electrode may be its drain electrode, and the second electrode may be its source electrode.
  • the requirements of the application are determined by design.
  • the pixel circuit in the sub-pixel may be a structure including other numbers of transistors in addition to the structure shown in FIG. 2a and FIG. 2b, which is not limited in this embodiment of the present disclosure. The following description takes the structure shown in FIG. 2a as an example.
  • the display substrate includes a base substrate 10, a transistor array layer disposed on the base substrate 10, a first conductive layer located on the side of the transistor array layer away from the base substrate 10, and a first conductive layer located on the side away from the base substrate 10.
  • the transistor array layer can be used to form transistors and capacitors in the pixel circuit, and to form scan lines, reset lines, light emission control lines EM, initialization lines VINIT, and first power supply signal lines VDD of the first power supply terminal VDD.
  • the transistor array layer may include an active semiconductor layer 0310 , a gate conductive layer 0320 , a reference conductive layer 0330 , and a source-drain metal layer 0340 .
  • the active semiconductor layer 0310 of the pixel circuit 0121 is shown.
  • the active semiconductor layer 0310 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 0310 can be used to fabricate the above-mentioned driving active layer T1-A of the driving transistor T1, the active layer T2-A of the data writing transistor T2, the active layer T3-A of the threshold compensation transistor T3, the first light emitting layer
  • the active layer T4-A of the control transistor T4 the active layer T5-A of the second light-emitting control transistor T5, the active layer T6-A of the initialization transistor T6 and the active layer T7-A of the reset transistor T7, each active
  • the layers may include a source region, a drain region, and a channel region between the source and drain regions.
  • the active layers of the respective transistors are integrally provided.
  • the active semiconductor layer 0310 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • a gate insulating layer is formed on the above-mentioned active semiconductor layer 0310 for protecting the above-mentioned active semiconductor layer 0310 .
  • the gate conductive layer 0320 of the pixel circuit 0121 is shown, and the gate conductive layer 0320 is provided on the gate insulating layer so as to be insulated from the active semiconductor layer 0310 .
  • the gate conductive layer 0320 may include a second electrode cc2 of the storage capacitor CST, a scan line GA, a reset line RST, a light emission control line EM, a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, and a first light emission control transistor T4 , the gates of the second light emission control transistor T5, the initialization transistor T6 and the reset transistor T7.
  • the gate of the data writing transistor T2 may be the portion where the scan line GA and the active semiconductor layer 0310 overlap
  • the gate of the first light-emitting control transistor T4 may be the light-emitting control line EM and the active semiconductor layer 0310.
  • the gate of the second light-emitting control transistor T5 can be the second part where the light-emitting control line EM and the active semiconductor layer 0310 overlap
  • the gate of the initialization transistor T6 is the reset line RST and the active semiconductor layer.
  • the first part where the layer 0310 overlaps, the gate of the reset transistor T7 is the second part where the reset line RST overlaps with the active semiconductor layer 0310, the threshold compensation transistor T3 can be a thin film transistor with a double gate structure, and the first part of the threshold compensation transistor T3
  • the first gate may be the portion where the scan line GA overlaps with the active semiconductor layer 0310
  • the second gate of the threshold compensation transistor T3 may be the portion where the protrusion protruding from the scan line GA overlaps the active semiconductor layer 0310 .
  • the driving gate of the driving transistor T1 may be the second electrode cc2 of the storage capacitor CST.
  • each dotted line in FIG. 4a shows each part where the gate conductive layer 0320 and the active semiconductor layer 0310 overlap.
  • the scan line GA, the reset line RST and the light emission control line EM are arranged along the second direction F2. And the scan line GA, the reset line RST and the light emission control line EM extend substantially along the first direction F1.
  • the scan line GA is located between the reset line RST and the light emission control line EM.
  • FIG. 3 only takes the second direction F2 as the column direction and the first direction F1 as the row direction as an example for description.
  • the second pole cc2 of the storage capacitor CST is located between the scan line GA and the light emission control line EM.
  • the protrusion protruding from the scanning line GA is located on the side of the scanning line GA away from the light emission control line EM.
  • an interlayer dielectric layer is formed on the above-mentioned gate conductive layer 0320 to protect the above-mentioned gate conductive layer 0320 .
  • the reference conductive layer 0330 of the pixel circuit 120a is shown.
  • the reference conductive layer 0330 includes the first pole cc1 of the storage capacitor CST, the initialization line VINIT, and the light shielding layer ZG.
  • the first pole cc1 of the storage capacitor CST and the second pole cc2 of the storage capacitor CST at least partially overlap to form the storage capacitor CST.
  • the first pole cc1 of the storage capacitor CST has a hollow area LQ, and the hollow area LQ may expose a portion of the second pole cc2 of the storage capacitor CST.
  • the orthographic projection of the light shielding layer ZG on the base substrate 10 and the source region of the reset transistor T7 in the active semiconductor layer 0310 (such as the source region of the reset transistor T7 and the initialization
  • the source region of the transistor T6 has an integrated structure) overlapping on the orthographic projection of the base substrate 10 .
  • the threshold compensation transistor T3 is a dual gate transistor.
  • the light shielding layer ZG shields the active layer part between the two gates of the threshold compensation transistor T3, because the threshold compensation transistor T3 is directly connected to the driving transistor T1, which can stabilize the working state of the driving transistor T1.
  • the projection of the light shielding layer ZG on the base substrate is located in the pixel circuit area where it is located, and is located in the projection of a signal line (such as a data line) and a first power signal line VDD on the base substrate In between, play the role of shielding signal interference.
  • the projection of the light shielding layer ZG on the base substrate is located between the projections of the signal lines such as data lines and the first power signal line VDD connected to the pixel circuit in the pixel circuit region where it is located on the base substrate. between.
  • the orthographic projection of the light shielding layer ZG on the base substrate 10 overlaps with the orthographic projection of the drain region of the initialization transistor T6 in the active semiconductor layer 0310 on the base substrate 10 .
  • the influence of light on the initialization transistor T6 can be reduced, and the reset accuracy can be improved.
  • the conductive region between the orthographic projection of the light shielding layer ZG on the base substrate 10 and the active layer T3-A of the threshold compensation transistor T3 in the active semiconductor layer 0310 is on the lining.
  • the orthographic projections of the base substrate 10 overlap. In this way, the influence of light on the threshold compensation transistor T3 can be reduced, and the accuracy of the threshold compensation can be improved.
  • a first interlayer insulating layer is formed on the above-mentioned reference conductive layer 0330 for protecting the above-mentioned reference conductive layer 0330 .
  • the source-drain metal layer 0340 of the pixel circuit 0121 is shown, and the source-drain metal layer 0340 may include a first power supply signal line VDD, connection parts LB1 , LB2 , LB3 , and LB4 .
  • the first color sub-pixel spx1 , the second color sub-pixel spx2 , the third color sub-pixel spx3 and the fourth color sub-pixel spx4 include connection parts LB1 , LB2 , LB3 , and LB4 , respectively.
  • a second interlayer insulating layer is formed on the above-mentioned source-drain metal layer 0340 to protect the above-mentioned source-drain metal layer 0340 .
  • the first conductive layer 0350 of the pixel circuit 0121 is shown.
  • the first conductive layer 0350 includes signal lines and anode transfer parts YZ1, YZ2, YZ3, and YZ4 spaced apart from each other.
  • the first color sub-pixel spx1 may include an anode transfer portion YZ1
  • the second color sub-pixel spx2 may include an anode transfer portion YZ2
  • the third color sub-pixel spx3 may include an anode transfer portion YZ3
  • the fourth color sub-pixel spx3 may include an anode transfer portion YZ3.
  • the pixel spx4 may include an anode transition portion YZ4.
  • the plurality of signal lines include a first signal line and a second signal line; wherein, one column of sub-pixels corresponds to one first signal line and one second signal line, for example, the left and right sides of the pixel circuit of one column of sub-pixels are respectively connected to one
  • the first signal line is adjacent to a second signal line.
  • adjacent means that, for example, in the first direction, there is no other first signal line or second signal line between the pixel circuit and the first signal line and the second signal line adjacent thereto.
  • the signal raised portions of the first signal lines are respectively electrically connected to the sub-pixels in odd-numbered rows, and the signal raised portions of the second signal lines are electrically connected to the sub-pixels of even-numbered rows respectively.
  • the signal lines may be configured as data lines VD that transmit data signals.
  • the data lines VD have signal bumps TQ.
  • the data lines Vd extend along the second direction F2 and are arranged along the first direction F1.
  • one column of sub-pixels corresponds to two data lines, for example, the left and right sides of the pixel circuit of one column of sub-pixels are respectively adjacent to a first signal line and a second signal line;
  • the signal protrusions of the lines are respectively electrically connected to the pixel circuits of the sub-pixels in odd rows, and the signal protrusions of the other data line are respectively electrically connected to the pixel circuits of the sub-pixels in the even rows.
  • a column of sub-pixels corresponds to a first signal line and a second signal line, which may refer to signal lines (eg, data lines) directly adjacent to the pixel circuits of the column of sub-pixels.
  • signal lines eg, data lines
  • directly adjacent means that there is no other signal line between the signal line and the pixel circuit, for example, directly adjacent means that there is no other data line between the data line and the pixel circuit.
  • two of the first signal lines may be adjacent to form a first signal line group.
  • two adjacent first signal lines electrically connected to sub-pixels in odd-numbered rows may form a first signal line group. It should be noted that there are no other corresponding signal lines between the two first signal lines in the first signal line group, for example, no other data lines are set between the two adjacent data lines.
  • the two second signal lines may be adjacent to form a second signal line group.
  • two adjacent second signal lines electrically connected to sub-pixels in even rows may form a second signal line group.
  • there are no other corresponding signal lines between the two second signal lines in the second signal line group for example, no other data lines are set between the two adjacent data lines.
  • the adjacent repeating units along the second direction F2 are arranged in dislocation, so that the second color sub-pixel spx2 and the other repeating unit in one repeating unit of the two adjacent repeating units along the second direction F2
  • the fourth color sub-pixels spx4 in one repeating unit are adjacent along the second direction F2.
  • the second-color sub-pixel spx2 and the fourth-color sub-pixel spx4 in adjacent repeating units in the second direction F2 are located in the same column along the second direction F2 to form a sub-pixel pair, for example, aligned up and down in the column direction.
  • the first color subpixel spx1, a subpixel pair formed by a second color subpixel spx2 and a fourth color subpixel spx4, and a third color subpixel spx3 are sequentially arranged in the first direction F1.
  • the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the adjacent repeating units in the second direction F2 are used to display the same color, and the light-emitting layers thereof are integrally formed.
  • the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the adjacent repeating units in the second direction F2 have the same area of light-emitting regions.
  • the light-emitting areas of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the adjacent repeating units in the second direction F2 are approximately two rounded polygonal areas or circular areas that are vertically symmetrical, such as rounded five border area.
  • the light-emitting area of the first color sub-pixel spx1 is approximately a rounded polygonal area or an elliptical area, such as a rounded hexagonal area.
  • the light-emitting area of the third color sub-pixel spx3 is approximately a rounded polygonal area or an elliptical area, such as a rounded hexagonal area.
  • the size of the light emitting area of the first color subpixel spx1 in the second direction F2 is larger than the sizes of the second color subpixel spx2, the third color subpixel spx3, and the fourth color subpixel spx4 in the second direction F2.
  • the size of the light-emitting region of the third color sub-pixel spx3 in the second direction F2 is larger than the respective sizes of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the second direction F2.
  • the size of the light-emitting area of the third color subpixel spx3 in the first direction F1 is larger than the sizes of the second color subpixel spx2, the fourth color subpixel spx4, and the first color subpixel spx1 in the first direction F1.
  • the size of the light-emitting region of the first color sub-pixel spx1 in the first direction F1 is smaller than the respective sizes of the second color sub-pixel spx2 and the fourth color sub-pixel spx4 in the first direction F1.
  • a first insulating layer is formed on the above-mentioned first conductive layer 0350 for protecting the above-mentioned first conductive layer 0350 .
  • an anode layer 0360 is shown on the side of the first conductive layer 0350 away from the base substrate 10 , and the anode layer 0360 includes anodes Y1 , Y2 , Y3 , and Y4 .
  • the first color subpixel spx1 may include anode Y1
  • the second color subpixel spx2 may include anode Y2
  • the third color subpixel spx3 may include anode Y3
  • the fourth color subpixel spx4 may include anode Y4.
  • the first power signal line VDD passes through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer to correspond to the first light emitting diode in the active semiconductor layer 0310
  • the source region of the control transistor T4 is electrically connected.
  • the first power signal line VDD is electrically connected to the first electrode cc1 of the storage capacitor CST in the reference conductive layer 0330 through at least one via hole penetrating through the first interlayer insulating layer.
  • the first power signal line VDD is also electrically connected to the light shielding layer ZG through at least one via hole penetrating through the first interlayer insulating layer.
  • the first power signal line VDD is electrically connected to the light shielding layer ZG in the reference conductive layer 0330 through at least one via hole penetrating through the first interlayer insulating layer.
  • connection part LB1 is connected to the corresponding threshold compensation transistor T3 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the drain region is electrically connected.
  • the other end of the connection part LB1 is electrically connected to the initialization line VINIT through at least one via hole penetrating through the first interlayer insulating layer.
  • connection part LB2 is electrically connected to the signal raised part TQ of the data line through a via hole penetrating the second interlayer insulating layer, and the other end of the connection part LB2 is connected through the gate insulating layer, At least one via hole in the interlayer dielectric layer and the first interlayer insulating layer is electrically connected to the source region of the data writing transistor T2 in the active semiconductor layer 0310 .
  • connection part LB3 drives the via hole GK0 and the second electrode cc2 of the storage capacitor CST (that is, the second electrode cc2 of the driving transistor T1 through at least one of the interlayer dielectric layer and the first interlayer insulating layer) drive gate) are electrically connected.
  • the other end of the connection part LB3 is electrically connected to the drain region of the initialization transistor T6 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the driving gate of the driving transistor is electrically connected to the active semiconductor layer through the driving via hole, which may mean that the driving gate of the driving transistor T1 is electrically connected to one end of the connection part LB3 through the driving via hole GK0, and the connection is The other end of the portion LB3 is electrically connected to the drain region of the initialization transistor T6 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the orthographic projections of at least part of the driving via GK0 on the base substrate do not overlap with the orthographic projections of the anode transfer portion and the signal line on the base substrate, respectively.
  • connection portion LB4 is connected to the second light-emitting control transistor T5 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the drain region is electrically connected.
  • the first insulating layer includes a first via that exposes a portion of the anode transition, and the anode includes a main portion and an auxiliary portion that are electrically connected to each other; wherein , the auxiliary part is electrically connected with the anode transfer part through the first via hole.
  • the anode Y1 includes a main part Y11 and an auxiliary part Y12 that are electrically connected to each other, the auxiliary part Y12 is electrically connected to the anode transfer part YZ1 through the first via K11, and the anode transfer part YZ1 passes through the through hole K11.
  • the via hole of the second interlayer insulating layer is electrically connected to the connecting portion LB4.
  • the anode Y2 includes a main part Y21 and an auxiliary part Y22 that are electrically connected to each other, the auxiliary part Y22 is electrically connected to the anode transfer part YZ2 through the first via K12, and the anode transfer part YZ2 passes through the second through hole K12.
  • the via hole of the interlayer insulating layer is electrically connected to the connection portion LB4.
  • the anode Y3 includes a main part Y31 and an auxiliary part Y32 that are electrically connected to each other, the auxiliary part Y32 is electrically connected to the anode transfer part YZ3 through the first via K13, and the anode transfer part YZ3 passes through the second through hole K13.
  • the via hole of the interlayer insulating layer is electrically connected to the connection portion LB4.
  • the anode Y4 includes a main part Y41 and an auxiliary part Y42 that are electrically connected to each other.
  • the via hole of the interlayer insulating layer is electrically connected to the connection portion LB4.
  • the anode includes the main body part and the auxiliary part which are electrically connected to each other in an integrated structure, that is, the main body part and the auxiliary part are formed continuously.
  • the plurality of sub-pixels include a first sub-pixel 01 and a second sub-pixel 02 ; wherein, in the first sub-pixel 01 , the anode transfer part is on the positive side of the base substrate 10 .
  • the projection and the orthographic projection of the driving active layer on the base substrate 10 do not overlap, and the orthographic projection of the main body portion on the base substrate 10 and the orthographic projection of the anode transfer portion on the base substrate 10 do not overlap.
  • the orthographic projection of the anode transition portion on the base substrate 10 overlaps with the orthographic projection of the driving active layer on the base substrate 10
  • the orthographic projection of the main body portion on the base substrate 10 overlaps the anode
  • the transition portion overlaps with the orthographic projection of the base substrate 10 .
  • the anode layer is further provided with a pixel defining layer on the side facing away from the base substrate, some pixel defining layers are further provided with a light emitting layer facing away from the base substrate, and the light emitting layer is further provided with a cathode layer on the side facing away from the substrate substrate.
  • the pixel defining layer may include a plurality of opening regions (eg, KK1, KK2, KK3, KK4).
  • one anode corresponds to one opening area
  • the orthographic projection of the opening area on the base substrate 10 is located in the orthographic projection of the main portion of the corresponding anode on the base substrate 10 .
  • the opening area KK1 corresponds to the main body portion Y11 of the anode Y1.
  • the opening area KK2 corresponds to the main portion Y21 of the anode Y2.
  • the opening region KK3 corresponds to the main body portion Y31 of the anode Y3.
  • the opening area KK4 corresponds to the main portion Y41 of the anode Y4.
  • the orthographic projection of the opening region corresponding to the anode on the base substrate overlaps the orthographic projection of the anode transition portion on the base substrate.
  • the orthographic projection of the opening region corresponding to the anode on the base substrate does not overlap with the orthographic projection of the anode transition portion on the base substrate.
  • the light-emitting area of each sub-pixel corresponds to each opening area.
  • the light-emitting area of the first color sub-pixel is the opening area corresponding to the anode
  • the light-emitting area of the second color sub-pixel is the opening area corresponding to the anode
  • the light-emitting area of the third color sub-pixel is the opening area corresponding to the anode.
  • the light-emitting area of the four-color sub-pixel is the opening area corresponding to its anode.
  • the first subpixel 01 includes a first color subpixel spx1. That is to say, in the first color sub-pixel spx1, the orthographic projection of the anode transition portion YZ1 on the base substrate 10 does not overlap with the orthographic projection of the driving active layer T1-A on the base substrate 10, and the main body portion Y11 is on the base substrate 10.
  • the orthographic projection of the base substrate 10 does not overlap with the orthographic projection of the anode transfer portion YZ1 on the base substrate 10 .
  • the orthographic projection of the anode transfer portion YZ1 on the base substrate 10 does not overlap with the orthographic projection of the opening region KK1 on the base substrate 10 .
  • the orthographic projection of the anode transfer portion YZ1 on the base substrate 10 overlaps with the edge of the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and the anode transfer portion
  • the orthographic projection of YZ1 on the base substrate 10 does not overlap with the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the orthographic projection of the main body portion Y11 on the base substrate 10 is associated with two signal lines (for example, the first signal line group described below (such as The orthographic projection of the two data lines Vd) or the second signal line group (such as the two data lines Vd)) overlaps on the base substrate 10, and the orthographic projection of the main body portion Y11 on the base substrate 10 and the anode transfer portion YZ1 It does not overlap with the orthographic projection of the signal bump on the base substrate 10 .
  • the first signal line group described below such as The orthographic projection of the two data lines Vd
  • the second signal line group such as the two data lines Vd
  • two signal lines for example, the following first signal line group (for example, two data lines Vd) overlapping the orthographic projection of the main body portion Y11 on the base substrate 10 ) or the second signal line group (eg, two data lines Vd)) are located on both sides of the center of the main body portion Y11, respectively.
  • the main body portion Y11 in the first color sub-pixel spx1 has a first main body symmetry axis along the second direction F2, and in the first color sub-pixel spx1, in the second direction F2, the main body portion Y11 is on the base substrate.
  • the two signal lines (for example, the first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd) described below) whose orthographic projections overlap each other are located symmetrically in the first main body. opposite sides of the shaft. Further, in the first color sub-pixel spx1, in the first direction F1, two signal lines (such as the following first signal line group (such as two The ratio of the distance between the first data line Vd) or the second signal line group (eg, two data lines Vd) and the symmetry axis of the first body is 0.8 ⁇ 1.2.
  • two signal lines for example, the following first signal line group (for example, two data lines Vd) or second signal lines overlapping the orthographic projection of the main body portion Y11 on the base substrate 10
  • the ratio of the distance between the line group (eg, two data lines Vd) and the symmetry axis of the first body is 0.8, 1.0, 1.1 or 1.2.
  • the main body portion Y11 does not overlap with the signal raised portion TQ connected to the same pixel circuit.
  • the second subpixel 02 may include at least one of a second color subpixel spx2 , a third color subpixel spx3 , and a fourth color subpixel spx4 .
  • the orthographic projection of the anode transition portion YZ2 on the base substrate 10 is the same as the driving active layer T1-A.
  • the orthographic projections of the base substrate 10 overlap, and the orthographic projections of the main body portion Y21 on the base substrate 10 overlap with the orthographic projections of the anode adapter portion YZ2 on the base substrate 10 . Further, the orthographic projection of the opening region KK2 on the base substrate 10 overlaps with the orthographic projection of the anode transfer portion YZ2 on the base substrate 10 . Further, in the second color sub-pixel spx2, the main body portion Y21 does not overlap with the signal raised portion TQ connected to the same pixel circuit.
  • the orthographic projection of the anode transfer portion YZ2 on the base substrate 10 overlaps with the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and the anode transfer portion YZ2
  • the orthographic projection on the base substrate 10 also overlaps with the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the orthographic projection of the anode transfer portion YZ2 on the base substrate 10 passes through the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and in the second direction, the anode turns The orthographic projection of the junction YZ2 on the base substrate 10 also passes through the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the orthographic projection of the anode transition portion YZ3 on the base substrate 10 and the driving active layer T1-A are The orthographic projections of the base substrate 10 overlap, and the orthographic projections of the main body portion Y31 on the base substrate 10 overlap with the orthographic projections of the anode adapter portion YZ3 on the base substrate 10 . Further, the orthographic projection of the opening region KK3 on the base substrate 10 overlaps with the orthographic projection of the anode transfer portion YZ3 on the base substrate 10 . Further, in the third color sub-pixel spx3, the main body portion Y31 overlaps with the signal raised portion TQ connected to the same pixel circuit.
  • the orthographic projection of the anode transfer portion YZ3 on the base substrate 10 overlaps with the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and the anode transfer portion YZ3
  • the orthographic projection on the base substrate 10 also overlaps with the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the orthographic projection of the anode transfer portion YZ3 on the base substrate 10 passes through the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and in the second direction, the anode turns The orthographic projection of the junction YZ3 on the base substrate 10 also passes through the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the orthographic projection of the anode transition portion YZ4 on the base substrate 10 is the same as the driving active layer T1-A.
  • the orthographic projections of the base substrate 10 overlap, and the orthographic projections of the main body portion Y41 on the base substrate 10 overlap with the orthographic projections of the anode adapter portion YZ4 on the base substrate 10 .
  • the orthographic projection of the opening region KK4 on the base substrate 10 overlaps with the orthographic projection of the anode transfer portion YZ4 on the base substrate 10 .
  • the main body portion Y41 does not overlap with the signal raised portion TQ connected to the same pixel circuit.
  • the main body portion Y41 in the fourth color sub-pixel spx4 overlaps with the signal raised portion TQ in the pixel circuit connected to the adjacent second color sub-pixel spx2.
  • the orthographic projection of the anode transfer portion YZ4 on the base substrate 10 overlaps with the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and the anode transfer portion YZ4
  • the orthographic projection on the base substrate 10 also overlaps with the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the orthographic projection of the anode transfer portion YZ4 on the base substrate 10 passes through the orthographic projection of the first pole cc1 of the storage capacitor CST on the base substrate 10, and in the second direction, the anode turns The orthographic projection of the junction YZ4 on the base substrate 10 also passes through the orthographic projection of the second pole cc2 of the storage capacitor CST on the base substrate 10 .
  • the anode transition portion in the second sub-pixel 02 may include: The first sub-anode adapter part and the second sub-anode adapter part are electrically connected; wherein, the first sub-anode adapter part has a hollow structure, and the second sub-anode adapter part has a solid structure; the auxiliary part passes through the first via hole It is electrically connected to the second sub-anode adapter.
  • the orthographic projection of the first sub-anode transition portion on the base substrate 10 overlaps with the orthographic projection of the driving active layer on the base substrate 10 .
  • the solid structure may refer to: the orthographic projection of the second sub-anode transfer portion on the base substrate is a whole surface, and there is no hollow inside.
  • the anode transfer part YZ2 may include: a first sub-anode transfer part YZ21 and a second sub-anode transfer part YZ22 that are electrically connected to each other. ; wherein, the first sub-anode transfer part YZ21 has a hollow structure, the second sub-anode transfer part YZ22 has a solid structure; the auxiliary part Y22 is electrically connected to the second sub-anode transfer part YZ22 through the first via K12.
  • the orthographic projection of the first sub-anode transfer portion YZ21 on the base substrate 10 overlaps with the orthographic projection of the driving active layer T1 -A on the base substrate 10 .
  • the anode transfer part YZ3 may include: a first sub-anode transfer part YZ31 and a second sub-anode transfer part YZ32 that are electrically connected to each other. ; wherein, the first sub-anode transfer portion YZ31 has a hollow structure, the second sub-anode transfer portion YZ32 has a solid structure; the auxiliary portion Y32 is electrically connected to the second sub-anode transfer portion YZ32 through the first via K13.
  • the orthographic projection of the first sub-anode transfer portion YZ31 on the base substrate 10 overlaps with the orthographic projection of the driving active layer T1 -A on the base substrate 10 .
  • the anode transfer part YZ4 may include: a first sub-anode transfer part YZ41 and a second sub-anode transfer part YZ42 that are electrically connected to each other. ; wherein, the first sub-anode transfer portion YZ41 has a hollow structure, the second sub-anode transfer portion YZ42 has a solid structure; the auxiliary portion Y42 is electrically connected to the second sub-anode transfer portion YZ42 through the first via K14.
  • the orthographic projection of the first sub-anode transfer portion YZ41 on the base substrate 10 overlaps with the orthographic projection of the driving active layer T1 -A on the base substrate 10 .
  • the orthographic projection of the scan line on the base substrate 10 is located at the orthographic projection of the driving active layer on the base substrate 10 away from the second direction.
  • the sub-anode adapter is on the side of the orthographic projection of the base substrate 10 .
  • the orthographic projection of the first sub-anode transition portion on the base substrate 10 overlaps with the orthographic projection of the scan line on the base substrate 10 .
  • the orthographic projection of the first sub-anode switching portion YZ21 on the base substrate 10 is orthogonal to the orthographic projection of the scan line GA on the base substrate 10 . stack.
  • the orthographic projection of the first sub-anode transfer portion YZ31 on the base substrate 10 is orthogonal to the orthographic projection of the scan line GA on the base substrate 10 . stack.
  • the orthographic projection of the first sub-anode adapter YZ31 on the base substrate 10 is at least partially covered by the orthographic projection of the anode Y3 on the base substrate 10 .
  • the orthographic projection of the first sub-anode adapter YZ31 on the base substrate 10 is covered by the orthographic projection of the anode Y3 on the base substrate 10 .
  • the orthographic projection of the first sub-anode switching portion YZ41 on the base substrate 10 is orthogonal to the orthographic projection of the scan line GA on the base substrate 10 . stack.
  • the orthographic projection of the anode Y4 in the fourth color sub-pixel spx4 on the base substrate 10 covers part of the orthographic projection of the anode transition portion YZ4 on the base substrate 10 .
  • the orthographic projection of the anode Y2 in the second color sub-pixel spx2 on the base substrate 10 covers part of the orthographic projection of the anode transition portion YZ2 on the base substrate 10 .
  • the area of the part of the anode transfer part YZ2 in the second color sub-pixel spx2 covered by the anode Y2 is larger than the area of the part of the anode transfer part YZ4 in the fourth color sub-pixel spx4 covered by the anode Y4 .
  • the orthographic projection of the hollowed-out region LQ in the hollowed-out structure in the first sub-anode transition portion on the base substrate 10 is connected to the driving gate.
  • the orthographic projection of the via hole GK0 of the base substrate 10 overlaps.
  • the orthographic projection of the hollow structure in the first sub-anode transfer portion on the base substrate 10 overlaps with the hollow region LQ of the first pole cc1 of the storage capacitor CST.
  • the hollow area LQ is used as a via hole to connect the driving gate (ie, the second electrode cc2 of the storage capacitor CST) and other transistors, for example, one electrode (the source or drain) and the drive gate (ie, the second pole cc2 of the storage capacitor CST).
  • the driving gate ie, the second electrode cc2 of the storage capacitor CST
  • other transistors for example, one electrode (the source or drain) and the drive gate (ie, the second pole cc2 of the storage capacitor CST).
  • the hollow structure in the first sub-anode transfer portion YZ21 is aligned with the orthographic projection of the base substrate 10 and the central area of the driving gate.
  • the orthographic projections of the base substrate 10 overlap.
  • the orthographic projection of the hollow structure in the first sub-anode transfer portion YZ21 on the base substrate 10 overlaps with the hollow area of the first pole cc1 of the storage capacitor CST.
  • the orthographic projection of the hollow structure in the first sub-anode transfer portion YZ31 on the base substrate 10 overlaps with the orthographic projection of the central region of the driving gate on the base substrate 10 .
  • the orthographic projection of the hollow structure in the first sub-anode transfer portion YZ21 on the base substrate 10 overlaps with the hollow area of the first pole cc1 of the storage capacitor CST.
  • the orthographic projection of the hollow structure in the first sub-anode transfer portion YZ41 on the base substrate 10 overlaps with the orthographic projection of the central region of the driving gate on the base substrate 10.
  • the orthographic projection of the hollow structure in the first sub-anode transfer portion YZ21 on the base substrate 10 overlaps with the hollow area of the first pole cc1 of the storage capacitor CST.
  • the orthographic projection of the main body portion Y21 on the base substrate 10 is associated with two signal lines (for example, the first signal line group described below (for example, two signal lines).
  • the data lines Vd) or the second signal line group are overlapped on the orthographic projection of the base substrate 10 .
  • the orthographic projection of the main body part Y21 on the base substrate 10 and the two signal lines (for example, two data lines Vd) on the base substrate 10 orthographic overlap.
  • the orthographic projection of the main body portion Y31 on the base substrate 10 overlaps with the orthographic projection of the two signal lines (eg, two data lines Vd) on the base substrate 10 .
  • the orthographic projection of the main body portion Y41 on the base substrate 10 overlaps with the orthographic projection of the two signal lines (eg, two data lines Vd) on the base substrate 10 .
  • the first sub-anode adaptor has a first sub- adaptor and a second sub- adaptor that are oppositely disposed; wherein, in the first direction, the first sub-adapter
  • the orthographic projection of the switching portion on the base substrate 10 is located between the second sub-switching portion and the orthographic projection of the two signal lines on the base substrate 10 .
  • the first sub-adaptation portion may extend substantially along the second direction F2
  • the second sub-adaptation portion may extend substantially along the second direction F2.
  • the first sub-anode transfer part YZ21 has a first sub-transfer part YZ211 and a second sub-transfer part YZ212 arranged oppositely; wherein , the orthographic projection of the first sub-transition portion YZ211 on the base substrate 10 is located at the two signal lines (for example, two data lines Vd) of the second sub-transition portion YZ212 that overlap with the main body portion Y21 of the second color sub-pixel spx2 ) between the orthographic projections of the base substrate 10 .
  • the two signal lines for example, two data lines Vd
  • the first sub-transition part YZ211 is closer to the center of the main body part Y21 than the second sub-transition part YZ212.
  • the orthographic projection of the second sub-transit portion YZ212 on the base substrate 10 overlaps the edge of the orthographic projection of the main body portion Y21 on the base substrate 10 .
  • the projected overlapping parts of the first sub-adaptation part YZ211 and the second sub-adaptation part YZ212 and the main body part Y21 are located on the same side of the projection center of the main body part Y21.
  • the projected overlapping parts of the first sub-adaptation part YZ211 and the second sub-adaptation part YZ212 and the main body part Y21 are located on the first side of the projection center of the main body part Y21,
  • the projections of the two signal lines (eg, two data lines Vd) overlapped by the main body portion Y21 of the color sub-pixel spx2 are respectively located on the second side of the center of the projection of the main body portion Y21, and the first side and the second side are opposite sides .
  • the first sub-transition portion YZ211 , the second sub-transition portion YZ212 , and the two signal lines overlapping the main body portion Y21 of the second color sub-pixel spx2 can play a better flattening role. Further, as shown in FIGS. 3 to 5 , in the sub-pixel spx2 of the second color, the main body part Y21 and the second sub-anode transfer part YZ22 are partially overlapped.
  • the projection of the anode transfer portion YZ2 located on the second side of the projection center of the main body portion Y21 completely penetrates the projection of the main body portion Y21, and the projection of the anode transition portion YZ2 located at the projection center of the main body portion Y21 is the first.
  • the projection of the signal line on the side completely penetrates the projection of the main body part Y21 to achieve a better flat effect.
  • the first sub-anode transfer part YZ31 has a first sub-transfer part YZ311 and a second sub-transfer part YZ312 arranged oppositely; wherein , the orthographic projection of the first sub-transition portion YZ311 on the base substrate 10 is located at the two signal lines (eg, two data lines Vd) that overlap the second sub-transition portion YZ312 and the main body portion Y31 of the third color sub-pixel spx3 ) between the orthographic projections of the base substrate 10 .
  • the two signal lines eg, two data lines Vd
  • the first sub-transition part YZ311 is closer to the center of the main body part Y31 than the second sub-transition part YZ312.
  • the orthographic projection of the second sub-transit portion YZ312 on the base substrate 10 overlaps the edge of the orthographic projection of the main body portion Y31 on the base substrate 10 .
  • the projected overlapping parts of the first sub-adaptation part YZ311 and the second sub-adaptation part YZ312 and the main body part Y31 are located on the same side of the projection center of the main body part Y31.
  • the projected overlapping parts of the first sub-adaptation part YZ311 and the second sub-adaptation part YZ312 and the main body part Y31 are all located on the first side of the projection center of the main body part Y31, and are on the first side of the projection center of the main body part Y31.
  • Projection of two signal lines for example, the first signal line group (such as two data lines Vd) or the second signal line group (such as two data lines Vd) described below
  • the second sides are respectively located at the center of the projection of the main body portion Y31, and the first side and the second side are opposite sides.
  • the first sub-transition portion YZ311 , the second sub-transition portion YZ312 , and the two signal lines overlapping the main body portion Y31 of the third-color sub-pixel spx3 can play a better flattening role. Further, in the third color sub-pixel spx3, in the second direction, the projection of the signal line located on the first side of the projection center of the main body part Y31 completely penetrates the projection of the main body part Y31 to achieve a better flat effect.
  • the signal raised part TQ and the anode transfer part YZ3 overlap in the first direction.
  • a straight line parallel to the second direction may pass through the signal raised portion TQ and the anode transfer portion YZ3.
  • the signal raised portion TQ and the anode transfer portion YZ3 do not overlap, and the anode transfer portion YZ3 is at least partially located on the side of the center of the main body portion Y31 away from the signal raised portion TQ.
  • the anode transfer part YZ3 and the signal protrusion part TQ can be located on both sides of the center of the main body part Y31, respectively, so that the anode Y3 can be further flattened.
  • the center of the signal raised portion TQ and the center lines of the two data lines that overlap with the main body portion Y31 of the third color sub-pixel spx3 can be located at the center of the main body portion Y31, respectively. on both sides. In this way, the anode Y3 can be further flattened.
  • the first sub-anode transfer part YZ41 has a first sub-transfer part YZ411 and a second sub-transfer part YZ412 arranged oppositely; wherein , the orthographic projection of the first sub-transition portion YZ411 on the base substrate 10 is located at the two signal lines (for example, the following first sub-transition portion YZ412 overlapped with the main portion Y41 of the fourth color sub-pixel spx4)
  • a signal line group eg, two data lines Vd
  • a second signal line group eg, two data lines Vd
  • the first sub-transition part YZ411 is closer to the center of the main body part Y41 than the second sub-transition part YZ412.
  • the projected overlapping parts of the first sub-adaptation part YZ311 and the second sub-adaptation part YZ312 and the main body part Y31 are located on the same side of the projection center of the main body part Y31.
  • the projected overlapping parts of the first sub-adaptation part YZ311 and the second sub-adaptation part YZ312 and the main body part Y31 are all located on the first side of the projection center of the main body part Y31, which is on the first side of the projection center of the main body part Y31.
  • the projections of the two signal lines (eg, two data lines Vd) overlapped by the main body portion Y41 of the color sub-pixel spx4 are respectively located on the second side of the center of the projection of the main body portion Y41, and the first side and the second side are opposite sides .
  • the first sub-transition portion YZ411, the second sub-transition portion YZ412, and the two signal lines overlapping the main body portion Y41 of the fourth color sub-pixel spx4 can play a better flattening role.
  • the main body portion Y41 completely covers the second sub-anode transition portion YZ42.
  • the signal raised portion TQ overlapping the main body portion Y41 is located on the side of the anode transfer portion YZ4 away from the overlapping main body portion Y41.
  • the projection of the signal line located on the first side of the projection center of the main body part Y41 completely penetrates the projection of the main body part Y41 to achieve a better flat effect.
  • the two signal lines overlapping the main body part Y21 in the second color sub-pixel spx2 are located in the same repeating unit, and the second color sub-pixel spx2 is close to the first-color sub-pixel spx1 and the anode transfer part YZ2 in the second color sub-pixel spx2 is located on the side of the second color sub-pixel spx2 close to the third-color sub-pixel spx3 in the same repeating unit.
  • the two signal lines that overlap with the main body portion Y41 in the fourth color subpixel spx4 are located on the side of the fourth color subpixel spx4 close to the third color subpixel spx3 in the same repeating unit, and the fourth color subpixel spx4
  • the anode transfer part YZ4 is located on the side of the fourth color sub-pixel spx4 far from the third color sub-pixel spx3 in the same repeating unit.
  • the orthographic projection of the main body portion Y21 on the base substrate 10 is the same as the second color sub-pixel spx2
  • a sub-anode adapter YZ21 overlaps the orthographic projection of the base substrate 10 .
  • the orthographic projection of the main body portion Y21 on the base substrate 10 overlaps with the orthographic projections of the first sub-transition portion YZ211 and the second sub-transition portion YZ212 on the base substrate 10. .
  • the main body portion Y21 in the second color sub-pixel spx2 has a second main body symmetry axis along the second direction F2; and, in the second color sub-pixel spx2, two signal lines (eg, two data lines Vd)
  • the center line of the first sub-adaptation portion YZ211 and the second sub-adaptation portion YZ212 along the second direction F2 They are respectively located on opposite sides of the symmetry axis of the second body.
  • the center lines along the second direction F2 of the two signal lines (for example, the two data lines Vd) overlapping the orthographic projection of the main body portion Y21 on the base substrate 10 are aligned with the first sub-connection portion YZ211 and the second
  • the ratio of the distance between the center line of the second sub-transition portion YZ212 along the second direction F2 and the second body symmetry axis is 0.8 ⁇ 1.2, for example, it may be one of 0.8, 0.9, 1.0, 1.1 and 1.2.
  • the main body portion Y21 is supported by the data line Vd and the first and second sub-connection portions YZ211 and YZ212, so that the body portion Y21 can be as flat as possible, thereby reducing the asymmetry of the body portion Y21. Further, the light emission asymmetry of the effective light emitting area EQ can be improved, and even the light emission asymmetry of the effective light emitting area EQ can be eliminated, so that the color shift phenomenon of the display substrate can be improved or even eliminated.
  • the orthographic projection of the main body portion Y41 on the base substrate 10 It overlaps with the orthographic projection of the second sub-anode transfer portion YZ42 on the base substrate 10 , and the orthographic projection of the main body portion Y41 on the base substrate 10 and two signal lines (for example, two data lines Vd) on the base substrate 10 orthographic overlap.
  • the orthographic projection of at least part of the main body portion Y41 on the base substrate 10 is located at the orthographic projection of the second sub-anode transition portion YZ42 on the base substrate 10
  • the orthographic projection side of the base substrate 10 is away from the first sub-anode switching portion YZ41 .
  • the main body portion in the fourth color sub-pixel spx4 has a fourth main body symmetry axis along the second direction F2; in the fourth color sub-pixel spx4, two signal lines (for example, two data lines Vd) and the main body portion
  • the part of Y41 that overlaps the orthographic projection of the base substrate 10, the center line along the second direction F2, and the center line of the second sub-anode adapter YZ42 along the second direction F2 are located on both sides of the fourth main body symmetry axis, respectively .
  • the center lines of the two signal lines (for example, the two data lines Vd) that overlap the orthographic projection of the main body portion Y41 on the base substrate 10 are along the second direction F2, and the center lines of the second sub-anode transfer portion YZ42 are along the second direction F2.
  • the ratio of the distance between the center line of the second direction F2 and the fourth body symmetry axis is 0.8 ⁇ 1.2, for example, it may be one of 0.8, 1.0 and 1.2.
  • the orthographic projection of the main body portion Y41 in the fourth color sub-pixel spx4 on the base substrate 10 is aligned with the signal protrusion in the adjacent second color sub-pixel spx2.
  • the orthographic projections of the base substrate 10 overlap.
  • the main body portion Y41 is supported by the second sub-anode transfer portion YZ42 of the data line Vd and the signal raised portion, so that the main body portion Y41 can be as flat as possible, thereby reducing the asymmetry of the main body portion Y41.
  • the light emission asymmetry of the effective light emitting area EQ can be improved, and even the light emission asymmetry of the effective light emitting area EQ can be eliminated, so that the color shift phenomenon of the display substrate can be improved or even eliminated.
  • the area of the orthographic projection of the second sub-anode transfer part YZ42 in one fourth-color sub-pixel spx4 on the base substrate 10 is larger than that in one second-color sub-pixel spx2
  • the area of the orthographic projection of the second sub-anode transfer portion YZ22 on the base substrate 10 is larger than that in one second-color sub-pixel spx2
  • the area of the orthographic projection of the second sub-anode transfer portion YZ22 on the base substrate 10 has a second width W2 along the second direction F2
  • the second sub-anode transfer portion in the fourth color sub-pixel spx4 has a second width W2.
  • the orthographic projection of the junction YZ42 on the base substrate 10 has a fourth width W4 along the second direction F2; the fourth width W4 is greater than the second width W2.
  • the orthographic projection of the second sub-anode switching portion YZ22 in the second color sub-pixel spx2 on the base substrate 10 has a first width W1 along the first direction F1, which can make W2:W1 Set to 1.5:1.
  • the sizes of different second color sub-pixels spx2 have different requirements for the values of the first width W1 and the second width W2. Therefore, combined with the condition that W2:W1 is set to 1.5:1, set the first width according to the actual application requirements.
  • the values of the width W1 and the second width W2 are not limited here.
  • the second width W2 may be 5 ⁇ 18 ⁇ m.
  • the second width W2 may be 10 ⁇ 15 ⁇ m.
  • the second width W2 may be 5 microns
  • the second width W2 may be 10 microns
  • the second width W2 may be 12 microns
  • the second width W2 may be 15 microns
  • the second width W2 may be 18 microns .
  • the first width W1 may be 4 ⁇ 15 ⁇ m.
  • the first width W1 is 8-12 micrometers.
  • the first width W1 may be 4 microns
  • the first width W1 may be 8 microns
  • the first width W1 may be 10 microns
  • the first width W1 may be 12 microns
  • the first width W1 may be 15 microns .
  • the size of the second sub-anode transfer part YZ22 is at least larger than the size of the via hole.
  • the size of a via hole is, for example, about 5*5 microns.
  • the size of a via hole is, for example, about 4*4 microns.
  • the size of a via hole is, for example, about 3*4 microns.
  • the size of a via hole is, for example, about 3*3 microns.
  • the size of a via hole is, for example, a circular hole with a diameter of 2-5 microns.
  • the second sub-anode adapter YZ32 in the third-color sub-pixel spx3 has a fifth width W5 along the first direction F1 in the orthographic projection of the base substrate 10, and the third-color sub-pixel has a fifth width W5.
  • the orthographic projection of the second sub-anode connecting portion YZ32 in the spx3 on the base substrate 10 has a sixth width W6 along the second direction F2, and W6:W5 can be set to 1.5:1.
  • the sizes of the sub-pixels spx3 of different third colors have different requirements for the values of the fifth width W5 and the sixth width W6.
  • the fifth width W5 and the sixth width W6 are set according to the actual application requirements.
  • the values of the width W5 and the sixth width W6 are not limited here.
  • the sixth width W6 may be 5 ⁇ 18 ⁇ m.
  • the sixth width W6 may be 10 ⁇ 15 ⁇ m.
  • the sixth width W6 may be 5 microns
  • the sixth width W6 may be 10 microns
  • the sixth width W6 may be 12 microns
  • the sixth width W6 may be 15 microns
  • the sixth width W6 may be 18 microns .
  • the fifth width W5 may be 4 ⁇ 18 ⁇ m.
  • the fifth width W5 is 8 ⁇ 15 ⁇ m.
  • the fifth width W5 may be 4 microns, the fifth width W5 may be 8 microns, the fifth width W5 may be 10 microns, the fifth width W5 may be 15 microns, and the fifth width W5 may be 18 microns .
  • the size of the second sub-anode transfer part YZ32 is at least larger than the size of the via hole.
  • the size of a via hole is, for example, about 5*5 microns.
  • the size of a via hole is, for example, about 4*4 microns.
  • the size of a via hole is, for example, about 3*4 microns.
  • the size of a via hole is, for example, about 3*3 microns.
  • the size of a via hole is, for example, a circular hole with a diameter of 2-5 microns.
  • the orthographic projection of the second sub-anode transfer part YZ42 in the fourth-color sub-pixel spx4 on the base substrate 10 has a third width W3 along the first direction F1, and in the first direction F1
  • the second direction F2 has a fourth width W4, so that W4:W3 can be set to 2:1.
  • the center of the opening area of the fourth color sub-pixel spx4 is further away from the anode transition part or further away from the anode transition part than the center of the opening area of the other sub-pixels (eg, at least one of spx1, spx2 and spx3)
  • the size of the second sub-anode transfer portion YZ42 of the fourth color sub-pixel spx4 in the second direction is larger than that of other sub-pixels.
  • the size of the second sub-anode transfer portion of each sub-pixel is approximately equal in the first direction.
  • the sizes of the different third color sub-pixels spx3 have different requirements for the values of the third width W3 and the fourth width W4. Therefore, combined with the condition that W4:W3 is set to 2:1, set the third width according to the actual application requirements.
  • the values of the width W3 and the fourth width W4 are not limited here.
  • the fourth width W4 may be 10 ⁇ 30 ⁇ m.
  • the fourth width W4 may be 14-25 microns.
  • the fourth width W4 may be 16 ⁇ 24 ⁇ m.
  • the fourth width W4 may be 10 microns, the fourth width W4 may be 14 microns, the fourth width W4 may be 16 microns, the fourth width W4 may be 20 microns, and the fourth width W4 may be 24 microns , the fourth width W4 may also be 25 microns, and the fourth width W4 may also be 30 microns.
  • the third width W3 is 8 to 15 ⁇ m.
  • the third width W3 is 10-13 micrometers.
  • the third width W3 may be 8 microns, the third width W3 may be 10 microns, the third width W3 may be 12 microns, the third width W3 may be 13 microns, and the third width W3 may be 15 microns .
  • the size of the second sub-anode transfer portion YZ42 is at least larger than the size of the via hole.
  • the size of a via hole is, for example, about 5*5 microns.
  • the size of a via hole is, for example, about 4*4 microns.
  • the size of a via hole is, for example, about 3*4 microns.
  • the size of a via hole is, for example, about 3*3 microns.
  • the size of a via hole is, for example, a circular hole with a diameter of 2-5 microns.
  • the orthographic projection of the anode transfer portion YZ1 in the first color sub-pixel spx1 on the base substrate 10 has a seventh width W7 along the first direction F1, and the first color sub-pixel spx1 has a seventh width W7.
  • the orthographic projection of the anode transfer portion YZ1 on the base substrate 10 has an eighth width W8 along the second direction F2, and W8:W7 can be set to 1.5:1.
  • the sizes of different first color sub-pixels spx1 have different requirements for the values of the seventh width W7 and the eighth width W8. Therefore, combined with the condition that W8:W7 is set to 1.5:1, the seventh width W7 is set according to the actual application requirements.
  • the eighth width W8 may be 5 ⁇ 18 ⁇ m.
  • the eighth width W8 may be 10 ⁇ 15 ⁇ m.
  • the eighth width W8 may be 5 microns
  • the eighth width W8 may be 10 microns
  • the eighth width W8 may be 13 microns
  • the eighth width W8 may be 15 microns
  • the eighth width W8 may be 18 microns .
  • the seventh width W7 may be 4 ⁇ 15 ⁇ m.
  • the seventh width W7 is 8-12 micrometers.
  • the seventh width W7 may be 4 microns, the seventh width W7 may be 8 microns, the seventh width W7 may be 10 microns, the seventh width W7 may be 12 microns, and the seventh width W7 may be 15 microns .
  • the size of the second sub-anode transfer part YZ12 is at least larger than the size of the via hole.
  • the size of a via hole is, for example, about 5*5 microns.
  • the size of a via hole is, for example, about 4*4 microns.
  • the size of a via hole is, for example, about 3*4 microns.
  • the size of a via hole is, for example, about 3*3 microns.
  • the size of a via hole is, for example, a circular hole with a diameter of 2-5 microns.
  • the orthographic projection of the main body portion Y31 on the base substrate 10 it overlaps with the orthographic projection of the first sub-anode switching portion YZ31 on the base substrate 10 , and the orthographic projection of the main body portion Y31 on the base substrate 10 and two signal lines (for example, two data lines Vd) on the base substrate 10 orthographic overlap.
  • the orthographic projection of the main body portion Y31 on the base substrate 10 overlaps with the orthographic projections of the first sub-transition portion YZ311 and the second sub-transition portion YZ312 on the base substrate 10 .
  • the main body portion Y31 in the third color sub-pixel spx3 has a third main body symmetry axis along the second direction F2; and, in the third color sub-pixel spx3, two signal lines (eg, two data lines Vd)
  • the portion overlapping with the orthographic projection of the main body portion Y31 on the base substrate 10, along the center line of the second direction F2, and the center line of the first sub-adaptation portion YZ311 and the second sub-adaptation portion YZ312 along the second direction F2 They are respectively located on opposite sides of the symmetry axis of the third body.
  • the center lines of the two signal lines (for example, the two data lines Vd) overlapping the orthographic projection of the main body portion Y31 on the base substrate 10 along the second direction F2, and the first sub-connection portion YZ311 and the second
  • the ratio of the distance between the centerline of the second sub-transition portion YZ312 along the second direction F2 and the third body symmetry axis is 0.8 ⁇ 1.2, for example, may be one of 0.8, 0.9, 1.0, 1.1 and 1.2.
  • the orthographic projection of the main body portion Y31 on the base substrate 10 covers the orthographic projection of the signal protrusion portion on the base substrate 10 .
  • the signal protrusion is located on the side of the first sub-anode transfer portion YZ31 away from the second sub-anode transfer portion YZ32.
  • the signal bump TQ includes a bump body tq1 and a connection tq2 connecting the bump body tq1 and the data line Vd.
  • the signal raised portion TQ is used for electrical connection between the signal line and other film layers, and is generally connected through via holes.
  • the main body tq1 of the raised portion is provided with a via hole for connecting the data line Vd integrally connected with other film layers. , so its corresponding size in the first direction F1 and the second direction F2 cannot be too small, at least larger than the size of the via hole.
  • the size of a via hole is, for example, 4*4 microns.
  • the size of a via hole is, for example, 3*3 microns.
  • the size of a via hole is, for example, a circular hole with a diameter of 2-4 microns.
  • the main body tq1 of the raised portion transmits data signals for display by sub-pixels.
  • the corresponding dimensions in the first direction F1 and the second direction F2 cannot be too large.
  • the first direction F1 there is an interval between the main body tq1 of the protruding portion and another adjacent signal line such as a data line, and the interval is, for example, 3-18 microns.
  • a first raised portion for connecting one of odd-numbered rows and even-numbered rows, and a second raised portion for connecting the other one of odd-numbered and even-numbered rows with another adjacent data line The lines are spaced differently.
  • the main body tq1 of the signal raised portion connecting the odd-numbered rows is the first raised portion T1
  • the main body tq1 of the signal raised portion connecting the even-numbered rows is the second raised portion T2
  • the first raised portion T1 is adjacent to the signal raised portion T1.
  • the spacing between the data lines is different from the spacing between the second raised portion and its adjacent data lines.
  • the first raised portions T1 and the second raised portions T2 in the same column are alternately arranged along the second direction F2.
  • the interval between the first raised portion T1 and another adjacent data line is 3-8 microns.
  • the interval between the second raised portion T2 and another adjacent data line is 6-18 microns.
  • the dimensions of the first raised portion T1 and the second raised portion T2 are approximately equal.
  • the size and shape of the first protruding portion T1 and the second protruding portion T2 are approximately a rectangular block.
  • the size of the connection portion tq2 connecting the first raised portion T1 and the data line in the first direction F1 is approximately 6-20 microns.
  • the size of the connecting portion tq2 connecting the second raised portion T2 and the data line in the first direction F1 is approximately 3-8 microns.
  • the raised portions corresponding to the two data lines are approximately flush, that is, approximately at the same height in the second direction F2, and one has the first One protruding portion T1, the other having a second protruding portion T2.
  • the distance between the first sub-adapter part and the second sub-adapter part in the same first sub-anode transition part in the first direction F1 is the same as that of the two signal lines
  • the ratio between the distances in the first direction F1 may be 0.8 ⁇ 1.2.
  • the ratio between the distance in the first direction F1 and the distance between the two signal lines in the first direction F1 between the first sub-transition part and the second sub-transition part in the same first sub-anode transition part Can be 0.8, 1.0, 1.1 or 1.2.
  • the distance between the first sub-adapter part and the second sub-adapter part in the same first sub-anode transition part in the first direction F1 is the same as that of the two signal lines
  • the distances in the first direction F1 are approximately the same.
  • the distance H1 of the first sub-transition portion YZ211 and the second sub-transition portion YZ212 in the same first sub-anode transition portion YZ21 in the first direction F1 is the same as that of the two
  • the distance H2 of the signal lines (eg, two data lines Vd) in the first direction F1 is approximately the same.
  • the distance H1 between the first sub-transition portion YZ311 and the second sub-transition portion YZ312 in the same first sub-anode transition portion YZ31 in the first direction F1 and the two signal lines (for example, The distance H2 of the two data lines Vd) in the first direction F1 is approximately the same.
  • the distance H1 between the first sub-transition portion YZ411 and the second sub-transition portion YZ412 in the same first sub-anode transition portion YZ41 in the first direction F1 and the two signal lines (for example, The distance H2 of the two data lines Vd) in the first direction F1 is approximately the same.
  • the distance H2 can be set to 5 ⁇ 7 ⁇ m.
  • the distance H2 may be set to 5 ⁇ m
  • the distance H2 may be set to 6 ⁇ m
  • the distance H2 may be set to 7 ⁇ m.
  • the specific value of the distance H2 can be determined according to the requirements of practical applications, which is not limited here.
  • the distance H1 may be set to 5 ⁇ 6 ⁇ m.
  • the distance H1 may be set to 5 ⁇ m
  • the distance H1 may be set to 5.5 ⁇ m
  • the distance H1 may be set to 6 ⁇ m.
  • the specific value of the distance H1 can be determined according to the requirements of practical applications, which is not limited here.
  • an embodiment of the present disclosure further provides a display device, including the above electroluminescent display substrate provided by an embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.

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Abstract

提供一种显示基板及显示装置，显示基板包括多个重复单元，多个重复单元中的至少一个包括多个子像素，每个子像素包括：具有驱动晶体管的像素电路、具有阳极的发光元件和阳极转接部，其中阳极包括相互电连接的主体部分和辅助部分。多个子像素包括第一子像素和第二子像素，第一子像素中，阳极转接部（YZ1）在衬底基板的正投影与驱动有源层在衬底基板的正投影不交叠，且阳极的主体部分（Y11）在衬底基板的正投影与阳极转接部（YZ1）在衬底基板的正投影不交叠；第二子像素中，阳极转接部（YZ2）在衬底基板的正投影与驱动有源层在衬底基板的正投影交叠，且阳极的主体部分（Y21）在衬底基板的正投影与阳极转接部（YZ2）在衬底基板的正投影交叠。

Description

显示基板及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及显示基板及显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示基板因其自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。随着人们对于OLED显示基板的要求的提高，为了实现显示基板中的高分辨率设计，OLED显示基板通常会采用SPR像素排列，即像素借用的方式。
发明内容
本公开实施例提供的显示基板，包括：
多个子像素，所述多个子像素中的至少一个子像素包括：位于衬底基板上的像素电路和发光元件，所述像素电路包括驱动晶体管，用于驱动发光元件发光；
所述显示基板包括有源半导体层；所述驱动晶体管的驱动有源层位于所述有源半导体层中；
所述驱动晶体管中的驱动栅极通过驱动过孔与所述有源半导体层电连接；
第一导电层，位于所述有源半导体层背离衬底基板一侧，并且所述第一导电层包括相互间隔设置的阳极转接部和信号线；
所述子像素中，所述驱动过孔的至少部分在所述衬底基板的正投影分别与所述阳极转接部和所述信号线在所述衬底基板的正投影不交叠。
在一些示例中，所述显示基板还包括：
第一绝缘层，位于所述第一导电层背离所述衬底基板一侧，并且所述第一绝缘层包括第一过孔，所述第一过孔暴露所述阳极转接部的至少一部分；
所述发光元件包括阳极，所述阳极位于所述第一绝缘层背离所述衬底基板一侧，并且所述阳极包括相互电连接的主体部分和辅助部分；其中，所述辅助部分通过所述第一过孔与所述阳极转接部电连接；
其中，所述多个子像素包括第一子像素和第二子像素；
所述第一子像素中，所述阳极转接部在所述衬底基板的正投影与所述驱动有源层在所述衬底基板的正投影不交叠，且所述主体部分在所述衬底基板的正投影与所述阳极转接部在所述衬底基板的正投影不交叠；
所述第二子像素中，所述阳极转接部在所述衬底基板的正投影与所述驱动有源层在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与所述阳极转接部在所述衬底基板的正投影交叠。
在一些示例中，所述第二子像素中的所述阳极转接部包括：相互电连接的第一子阳极转接部和第二子阳极转接部；其中，所述第一子阳极转接部具有镂空结构，所述第二子阳极转接部具有实体结构；所述辅助部分通过所述第一过孔与所述第二子阳极转接部电连接；
所述第二子像素中，所述第一子阳极转接部在所述衬底基板的正投影与所述驱动有源层在所述衬底基板的正投影交叠。
在一些示例中，所述显示基板还包括：位于所述有源半导体层与所述第一导电层之间的栅导电层，所述栅导电层包括：扫描线；
在平行于所述衬底基板的方向上，同一所述第二子像素中，所述扫描线在所述衬底基板的正投影位于所述驱动有源层在所述衬底基板的正投影背离所述第二子阳极转接部在所述衬底基板的正投影一侧；
所述第二子像素中，所述第一子阳极转接部在所述衬底基板的正投影与所述扫描线在所述衬底基板的正投影交叠。
在一些示例中，所述第二子像素中，所述第一子阳极转接部中的镂空结构中的镂空区域在所述衬底基板的正投影与所述驱动过孔在所述衬底基板的正投影交叠。
在一些示例中，所述第一子阳极转接部具有相对设置的第一子转接部和 第二子转接部；
所述第二子像素中，所述主体部分在所述衬底基板的正投影与两条信号线在所述衬底基板的正投影交叠；且在第一方向上，所述第一子转接部在所述衬底基板的正投影位于所述第二子转接部与所述两条信号线在所述衬底基板的正投影之间。
在一些示例中，所述多个重复单元中的至少一个包括：第一颜色子像素、第二颜色子像素、第三颜色子像素以及第四颜色子像素；其中，所述多个重复单元沿第一方向排列形成重复单元组，所述重复单元组沿第二方向排列，所述第一方向与所述第二方向不同；
所述第一子像素包括所述第一颜色子像素；
所述第二子像素包括：第二颜色子像素、第三颜色子像素以及所述第四颜色子像素中的至少一个。
在一些示例中，所述第二子像素包括所述第二颜色子像素；
所述第二颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子阳极转接部在所述衬底基板的正投影交叠。
在一些示例中，所述第二颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子转接部和所述第二子转接部在所述衬底基板的正投影均交叠。
在一些示例中，所述第二颜色子像素中的主体部分具有沿所述第二方向的第二主体对称轴；
所述第二颜色子像素中，所述两条信号线的与所述主体部分在所述衬底基板的正投影交叠的部分沿所述第二方向的中心线，与所述第一子转接部和所述第二子转接部沿所述第一方向的中心线分别位于所述第二主体对称轴的相对的两侧。
在一些示例中，所述第二子像素包括所述第四颜色子像素；
所述第四颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第二子阳极转接部在所述衬底基板的正投影交叠，且所述主体部分在所述衬 底基板的正投影与两条所述信号线在所述衬底基板的正投影交叠。
在一些示例中，在所述第二方向上，所述第四颜色子像素中，所述主体部分的至少部分在所述衬底基板的正投影位于所述第二子阳极转接部在所述衬底基板的正投影背离所述第一子阳极转接部在所述衬底基板的正投影一侧。
在一些示例中，所述第四颜色子像素中的主体部分具有沿所述第二方向的第四主体对称轴；
所述第四颜色子像素中，所述两条信号线与所述主体部分在所述衬底基板的正投影交叠的部分，沿所述第二方向的中心线，与所述第二子阳极转接部沿所述第二方向的中心线分别位于所述第四主体对称轴相对的两侧。
在一些示例中，各所述信号线还包括信号凸起部；所述多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条所述第一信号线和一条所述第二信号线；所述第一信号线的信号凸起部分别电连接奇数行子像素，所述第二信号线的信号凸起部分别电连接偶数行子像素；
沿所述第二方向相邻的重复单元中的第二颜色子像素和第四颜色子像素沿所述第二方向相邻；
沿所述第二方向，所述第四颜色子像素中的主体部分在所述衬底基板的正投影与相邻的所述第二颜色子像素中的信号凸起部在所述衬底基板的正投影交叠。
在一些示例中，各所述信号线还包括信号凸起部；所述多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条所述第一信号线和一条所述第二信号线；所述第一信号线的信号凸起部分别电连接奇数行子像素，所述第二信号线的信号凸起部分别电连接偶数行子像素；
相邻两列子像素对应的两条第一信号线和两条第二信号线中，其中的两条第一信号线相邻形成一个第一信号线组，或者，其中的两条第二信号线相邻形成一个第二信号线组。
在一些示例中，一个所述第四颜色子像素中的第二子阳极转接部在所述衬底基板的正投影的面积大于一个所述第二颜色子像素中的第二子阳极转接 部在所述衬底基板的正投影的面积。
在一些示例中，所述第二颜色子像素中的第二子阳极转接部在所述衬底基板的正投影沿所述第二方向具有第二宽度，所述第四颜色子像素中的第二子阳极转接部在所述衬底基板的正投影沿所述第二方向具有第四宽度；所述第四宽度大于所述第二宽度。
在一些示例中，所述第二子像素包括所述第三颜色子像素；
所述第三颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子阳极转接部在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与两条所述信号线在所述衬底基板的正投影交叠。
在一些示例中，所述第三颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子转接部和所述第二子转接部在所述衬底基板的正投影均交叠。
在一些示例中，所述第三颜色子像素中的主体部分具有沿所述第二方向的第三主体对称轴；
所述第三颜色子像素中，所述两条信号线与所述主体部分在所述衬底基板的正投影交叠的部分，沿所述第二方向的中心线，与所述第一子转接部和所述第二子转接部沿所述第二方向的中心线分别位于所述第三主体对称轴的相对的两侧。
在一些示例中，所述第三颜色子像素中，所述主体部分在所述衬底基板的正投影覆盖所述信号凸起部在所述衬底基板的正投影。
在一些示例中，所述第三颜色子像素中，所述信号凸起部位于所述第一子阳极转接部远离所述第二子阳极转接部的一侧。
在一些示例中，所述第一颜色子像素中，所述主体部分在所述衬底基板的正投影与两条所述信号线在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与所述阳极转接部和信号凸起部在所述衬底基板的正投影不交叠。
在一些示例中，所述第一颜色子像素中的主体部分具有沿所述第二方向 的第一主体对称轴；
所述第一颜色子像素中，在所述第二方向上，与所述主体部分在所述衬底基板的正投影交叠的所述两条信号线分别位于所述第一主体对称轴的相对的两侧。
在一些示例中，同一所述第一子阳极转接部中的第一子转接部和第二子转接部在所述第一方向上的距离与所述两条信号线在所述第一方向上的距离比值为0.8～1.2。
在一些示例中，所述信号线被配置为传输数据信号的数据线。
本公开实施例提供的显示装置，包括上述显示基板。
附图说明
图1为本公开实施例提供的显示基板的结构示意图；
图2a为本公开实施例提供的一些像素电路的结构示意图；
图2b为本公开实施例提供的信号时序图；
图2c为本公开实施例提供的一些像素电路的结构示意图；
图3为本公开实施例提供的一些显示基板的布局结构示意图；
图4a为本公开实施例提供的有源半导体层的布局结构示意图；
图4b为本公开实施例提供的栅导电层的布局结构示意图；
图4c为本公开实施例提供的参考导电层的布局结构示意图；
图4d为本公开实施例提供的源漏金属层的布局结构示意图；
图4e为本公开实施例提供的第一导电层的布局结构示意图；
图4f为本公开实施例提供的阳极层的布局结构示意图；
图5为本公开实施例提供的又一些显示基板的布局结构示意图；
图6a为图5所示的布局结构示意图中沿AA’方向的剖视结构示意图；
图6b为图5所示的布局结构示意图中沿BB’方向的剖视结构示意图；
图6c为图5所示的布局结构示意图中沿CC’方向的剖视结构示意图；
图6d为图5所示的布局结构示意图中沿DD’方向的剖视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的显示基板，可以包括：衬底基板10。位于衬底基板10上的多个重复单元PX，多个重复单元PX中的至少一个重复单元PX(例如每一个重复单元)可以包括多个子像素spx。例如，多个子像素可以包括第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4。也就是说，可以使重复单元包括第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4。这样可以使显示基板采用第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4进行混光，以实现彩色显示。在一些示例中，第一颜色、第二颜色、第三颜色以及第四颜色可以从红色、绿色以及蓝色中进行选取。例如，第一颜色为红色、第二颜色为绿色、第三颜色 为蓝色，第四颜色为绿色。当然，本公开实施例包括但不限于此。下面以重复单元包括第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4，且第二颜色和第四颜色为绿色，第一颜色为红色，第三颜色为蓝色为例进行说明。
示例性地，结合图1所示，多个重复单元沿第一方向F1排列形成重复单元组PXZ，重复单元组PXZ沿第二方向F2排列。其中，第一方向F1与第二方向F2不同。示例性地，第一方向F1与第二方向F2垂直。例如，第一方向F1为行方向，第二方向F2为列方向。或者，第一方向F1为列方向，第二方向F2为行方向。
示例性地，结合图1与图2a所示，多个子像素spx中的至少一个子像素spx(例如每一个子像素)可以包括：像素电路0121和发光元件0120。其中，像素电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号输入到发光元件0120的阳极中。并且对发光元件0120的阴极加载相应的电压，可以驱动发光元件0120发光。
结合图2a所示，像素电路0121可以包括：驱动控制电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。
驱动控制电路0122可以包括控制端、第一端和第二端。且驱动控制电路0122被配置为向发光元件0120提供驱动发光元件0120发光的驱动电流。例如，第一发光控制电路0123与驱动控制电路0122的第一端和第一电压端VDD连接。且第一发光控制电路0123被配置为实现驱动控制电路0122和第一电压端VDD之间的连接导通或断开。
第二发光控制电路0124与驱动控制电路0122的第二端和发光元件0120的阳极电连接。且第二发光控制电路0124被配置为实现驱动控制电路0122和发光元件0120之间的连接导通或断开。
数据写入电路0126与驱动控制电路0122的第一端电连接。且数据写入电路0126被配置为将数据线VD上的信号写入存储电路0127。
存储电路0127与驱动控制电路0122的控制端和第一电压端VDD电连接。且存储电路0127被配置为存储数据信号以及驱动控制电路0122的信息。
阈值补偿电路0128分别与驱动控制电路0122的控制端和第二端电连接。且阈值补偿电路0128被配置为对驱动控制电路0122进行阈值补偿。
复位电路0129还分别与驱动控制电路0122的控制端和发光元件0120的阳极电连接。且复位电路0129被配置为对发光元件0120的阳极进行复位，以及对驱动控制电路0122的控制端进行复位。
其中，发光元件0120可以设置为电致发光二极管，例如OLED、QLED、micro LED，mini OLED中的至少一种。其中，发光元件0120可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光元件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2a所示，驱动控制电路0122包括：驱动晶体管T1，驱动控制电路0122的控制端包括驱动晶体管T1的驱动栅极，驱动控制电路0122的第一端包括驱动晶体管T1的第一极，驱动控制电路0122的第二端包括驱动晶体管T1的第二极。
示例性地，结合图2a所示，数据写入电路0126包括数据写入晶体管T2。存储电路0127包括存储电容CST。阈值补偿电路0128包括阈值补偿晶体管T3。第一发光控制电路0123包括第一发光控制晶体管T4。第二发光控制电路0124包括第二发光控制晶体管T5。复位电路0129包括初始化晶体管T6和复位晶体管T7。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线VD电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与扫描线GA电连接以接收信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T1的驱动栅极电连接。
阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补 偿晶体管T3的第二极与驱动晶体管T1的驱动栅极电连接，阈值补偿晶体管T3的栅极被配置为与扫描线GA电连接以接收信号。
初始化晶体管T6的第一极被配置为与初始化线VINIT电连接以接收复位信号，初始化晶体管T6的第二极与驱动晶体管T1的驱动栅极电连接，初始化晶体管T6的栅极被配置为与复位线RST电连接以接收信号。
复位晶体管T7的第一极被配置为与初始化线VINIT电连接以接收复位信号，复位晶体管T7的第二极与发光元件0120的阳极电连接，复位晶体管T7的栅极被配置为与复位线RST电连接以接收信号。
或者，如图2c所示，初始化晶体管T6的第一极被配置为与初始化线VINIT1电连接以接收第一复位信号，初始化晶体管T6的第二极与驱动晶体管T1的驱动栅极电连接，初始化晶体管T6的栅极被配置为与复位线RST电连接以接收信号。复位晶体管T7的第一极被配置为与初始化线VINIT2电连接以接收第二复位信号，复位晶体管T7的第二极与发光元件0120的阳极电连接，复位晶体管T7的栅极被配置为与复位线RST电连接以接收信号。这样可以使初始化晶体管T6和复位晶体管T7分别接收不同的复位信号。
第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光元件0120的阳极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
发光元件0120的阴极与第二电源端VSS电连接。其中，上述晶体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2a所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，例如第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，例如第二电压为0或者为负电压等。例如，在一 些示例中，第二电源端VSS可以接地。
图2a所示的像素电路对应的信号时序图，如图2b所示。一帧显示时间中，像素电路的工作过程具有三个阶段：T10阶段、T20阶段、T30阶段。其中，rst代表复位线RST上传输的信号，ga代表扫描线GA上传输的信号，em代表发光控制线EM上传输的信号。
在T10阶段，信号rst控制初始化晶体管T6导通，从而可以将初始化线VINIT上传输的信号提供给驱动晶体管T1的驱动栅极，以对驱动晶体管T1的驱动栅极进行复位。信号rst控制复位晶体管T7导通，以将初始化线VINIT上传输的信号提供给发光元件0120的阳极，以对发光元件0120的阳极进行复位。并且，此阶段中，信号ga控制数据写入晶体管T2和阈值补偿晶体管T3均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T20阶段，信号ga控制数据写入晶体管T2和阈值补偿晶体管T3导通，导通的数据写入晶体管T2使数据线VD上传输的数据信号对驱动晶体管T1的驱动栅极进行充电，以使驱动晶体管T1的驱动栅极的电压变为：Vdata+Vth。其中，Vth代表驱动晶体管T1的阈值电压，Vdata代表数据信号的电压。并且，此阶段中，信号rst控制初始化晶体管T6和复位晶体管T7均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T30阶段，信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均导通。导通的第一发光控制晶体管T4将第一电源端VDD的电压Vdd提供给驱动晶体管T1的第一极，以使驱动晶体管T1的第一极的电压为Vdd。驱动晶体管T1根据其栅极电压Vdata+|Vth|，以及第一极的电压Vdd，产生驱动电流。该驱动电流通过导通的第二发光控制晶体管T5提供给发光元件0120，驱动发光元件0120发光。并且，此阶段中，信号rst控制初始化晶体管T6和复位晶体管T7截止。信号ga控制数据写入晶体管T2和阈值补偿晶体管T3截止。
需要说明的是，在本公开实施例中，上述晶体管的第一极可以为其源极， 第二极为其漏极；或第一极为其漏极，第二极为其源极，这可以根据实际应用的需求进行设计确定。并且，子像素中的像素电路除了可以为图2a和图2b所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。下面以图2a所示的结构为例进行说明。
示例性地，显示基板包括衬底基板10、设置在衬底基板10上的晶体管阵列层，位于晶体管阵列层背离衬底基板10一侧的第一导电层，位于第一导电层背离衬底基板10一侧的第一绝缘层，位于第一绝缘层背离衬底基板10一侧的阳极，位于阳极背离衬底基板10一侧的发光层以及位于发光层背离衬底基板10一侧的阴极。其中，晶体管阵列层可以用于形成像素电路中的晶体管和电容，以及形成扫描线、复位线、发光控制线EM、初始化线VINIT、第一电源端VDD的第一电源信号线VDD等。示例性地，晶体管阵列层可以包括有源半导体层0310、栅导电层0320、参考导电层0330以及源漏金属层0340。
示例性地，如图3与图4a示出了该像素电路0121的有源半导体层0310。有源半导体层0310可采用半导体材料图案化形成。有源半导体层0310可用于制作上述的驱动晶体管T1的驱动有源层T1-A、数据写入晶体管T2的有源层T2-A、阈值补偿晶体管T3的有源层T3-A、第一发光控制晶体管T4的有源层T4-A、第二发光控制晶体管T5的有源层T5-A、初始化晶体管T6的有源层T6-A和复位晶体管T7的有源层T7-A，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
示例性地，有源半导体层0310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
示例性地，在上述的有源半导体层0310上形成有栅绝缘层，用于保护上述的有源半导体层0310。如图3与图4b所示，示出了该像素电路0121的栅导电层0320，栅导电层0320设置在栅绝缘层上，从而与有源半导体层0310绝缘。栅导电层0320可以包括存储电容CST的第二极cc2、扫描线GA、复 位线RST、发光控制线EM、以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、初始化晶体管T6和复位晶体管T7的栅极。
例如，如图4b所示，数据写入晶体管T2的栅极可以为扫描线GA与有源半导体层0310交叠的部分，第一发光控制晶体管T4的栅极可以为发光控制线EM与有源半导体层0310交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制线EM与有源半导体层0310交叠的第二部分，初始化晶体管T6的栅极为复位线RST与有源半导体层0310交叠的第一部分，复位晶体管T7的栅极为复位线RST与有源半导体层0310交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为扫描线GA与有源半导体层0310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从扫描线GA突出的突出部与有源半导体层0310交叠的部分。如图3与图4b所示，驱动晶体管T1的驱动栅极可为存储电容CST的第二极cc2。
需要说明的是，图4a中的各虚线示出了栅导电层0320与有源半导体层0310交叠的各个部分。
示例性地，如图3与图4b所示，扫描线GA、复位线RST和发光控制线EM沿第二方向F2排布。且扫描线GA、复位线RST和发光控制线EM大致沿第一方向F1延伸。示例性地，扫描线GA位于复位线RST和发光控制线EM之间。示例性地，图3仅是以第二方向F2为列方向，第一方向F1为行方向为例进行说明。
示例性地，在第二方向F2上，存储电容CST的第二极cc2位于扫描线GA和发光控制线EM之间。并且，从扫描线GA突出的突出部位于扫描线GA远离发光控制线EM的一侧。
示例性地，在上述的栅导电层0320上形成有层间介质层，用于保护上述的栅导电层0320。如图3与图4c所示，示出了该像素电路120a的参考导电层0330，参考导电层0330包括存储电容CST的第一极cc1、初始化线VINIT、 遮光层ZG。其中，存储电容CST的第一极cc1与存储电容CST的第二极cc2至少部分交叠以形成存储电容CST。示例性地，存储电容CST的第一极cc1具有镂空区LQ，该镂空区LQ可以暴露出存储电容CST的第二极cc2的部分。
示例性地，如图3与图4c所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的复位晶体管T7的源极区域(如复位晶体管T7的源极区域与初始化晶体管T6的源极区域为一体结构)在衬底基板10的正投影交叠。这样可以降低光对复位晶体管T7的影响，提高复位准确性。例如，阈值补偿晶体管T3为双栅晶体管。例如，遮光层ZG遮挡阈值补偿晶体管T3的两个栅极中间的有源层部分，因为阈值补偿晶体管T3直接连接驱动晶体管T1，可以起到稳定驱动晶体管T1工作状态的作用。例如，在第一方向上，遮光层ZG在衬底基板的投影位于其所在的像素电路区域中，且位于一信号线(如数据线)和一第一电源信号线VDD在衬底基板的投影之间，起到屏蔽信号干扰的作用。例如，在第一方向上，遮光层ZG在衬底基板的投影位于其所在的像素电路区域中与该像素电路连接的信号线如数据线和第一电源信号线VDD在衬底基板的投影之间。
示例性地，如图3与图4c所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的初始化晶体管T6的漏极区域在衬底基板10的正投影交叠。这样可以降低光对初始化晶体管T6的影响，提高复位准确性。
示例性地，如图3与图4c所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的阈值补偿晶体管T3的有源层T3-A之间的导电区在衬底基板10的正投影交叠。这样可以降低光对阈值补偿晶体管T3的影响，提高阈值补偿的准确性。
示例性地，在上述的参考导电层0330上形成有第一层间绝缘层，用于保护上述的参考导电层0330。如图3与图4d所示，示出了该像素电路0121的源漏金属层0340，源漏金属层0340可以包括第一电源信号线VDD、连接部LB1、LB2、LB3、LB4。示例性地，第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4分别包括连接部LB1、 LB2、LB3、LB4。
示例性地，在上述的源漏金属层0340上形成有第二层间绝缘层，用于保护上述的源漏金属层0340。如图3与图4e所示，示出了该像素电路0121的第一导电层0350，第一导电层0350包括相互间隔设置的信号线和阳极转接部YZ1、YZ2、YZ3、YZ4。示例性地，第一颜色子像素spx1可以包括阳极转接部YZ1，第二颜色子像素spx2可以包括阳极转接部YZ2，第三颜色子像素spx3可以包括阳极转接部YZ3，第四颜色子像素spx4可以包括阳极转接部YZ4。
示例性地，多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条第一信号线和一条第二信号线，例如一列子像素的像素电路左右两侧分别与一条第一信号线和一条第二信号线相邻。例如相邻是指，例如在第一方向上，在该像素电路和与其相邻的第一信号线和第二信号线之间，没有其他的第一信号线或第二信号线。第一信号线的信号凸起部分别电连接奇数行子像素，第二信号线的信号凸起部分别电连接偶数行子像素。例如，信号线可以被配置为传输数据信号的数据线VD。在一些实施例中，数据线VD具有信号凸起部TQ。数据线Vd沿第二方向F2延伸，沿第一方向F1排列。在一些实施例中，一列子像素对应两条数据线，例如一列子像素的像素电路左右两侧分别与一条第一信号线和一条第二信号线相邻；这两条数据线中的一条数据线的信号凸起部分别电连接奇数行子像素的像素电路，另一条数据线的信号凸起部分别电连接偶数行子像素的像素电路。
需要说明的是，一列子像素对应一条第一信号线和一条第二信号线，指的可以是：与该列子像素的像素电路直接相邻的信号线(例如数据线)。其中，直接相邻是指该信号线与像素电路之间没有其他信号线，例如，直接相邻是指该数据线与像素电路之间没有其他数据线。
示例性地，可以使相邻两列子像素对应的两条第一信号线和两条第二信号线中，其中的两条第一信号线相邻形成一个第一信号线组。例如相邻的两个电连接奇数行子像素的第一信号线可以形成一个第一信号线组。需要说明的是，第一信号线组中的这两条第一信号线之间没有其他相应的信号线，例 如相邻的这两条数据线之间没有设置其他数据线。
示例性地，可以使相邻两列子像素对应的两条第一信号线和两条第二信号线中，其中的两条第二信号线相邻形成一个第二信号线组。例如相邻的两个电连接偶数行子像素的第二信号线可以形成一个第二信号线组。需要说明的是，第二信号线组中的这两条第二信号线之间没有其他相应的信号线，例如相邻的这两条数据线之间没有设置其他数据线。
例如，如图5所示，沿第二方向F2相邻的重复单元错位排列，这样在沿第二方向F2相邻的两个重复单元中的一个重复单元中的第二颜色子像素spx2和另一个重复单元中的第四颜色子像素spx4沿第二方向F2相邻。例如，第二方向F2相邻的重复单元中的第二颜色子像素spx2和第四颜色子像素spx4沿第二方向F2位于同一列，形成一个子像素对，例如在列方向上下对齐。例如，第一颜色子像素spx1，一个由一第二颜色子像素spx2和一第四颜色子像素spx4形成的子像素对，以及一个第三颜色子像素spx3在第一方向F1依次排列。例如，第二方向F2相邻的重复单元中的第二颜色子像素spx2和第四颜色子像素spx4用于显示相同的颜色，且其发光层为一体形成。例如，第二方向F2相邻的重复单元中的第二颜色子像素spx2和第四颜色子像素spx4的发光区域面积相同。例如，第二方向F2相邻的重复单元中的第二颜色子像素spx2和第四颜色子像素spx4的发光区域大致为上下对称的两个圆角多边形区域或圆形区域，例如为圆角五边形区域。例如，第一颜色子像素spx1的发光区域大致为圆角多边形区域或椭圆形区域，例如为圆角六边形区域。例如，第三颜色子像素spx3的发光区域大致为圆角多边形区域或椭圆形区域，例如为圆角六边形区域。例如，第一颜色子像素spx1的发光区域在第二方向F2的尺寸大于第二颜色子像素spx2、第三颜色子像素spx3、第四颜色子像素spx4各自在第二方向F2的尺寸。例如，第三颜色子像素spx3的发光区域在第二方向F2的尺寸大于第二颜色子像素spx2、第四颜色子像素spx4各自在第二方向F2的尺寸。例如，第三颜色子像素spx3的发光区域在第一方向F1的尺寸大于第二颜色子像素spx2、第四颜色子像素spx4、第一颜色子像素spx1各 自在第一方向F1的尺寸。例如，第一颜色子像素spx1的发光区域在第一方向F1的尺寸小于第二颜色子像素spx2、第四颜色子像素spx4各自在第一方向F1的尺寸。
示例性地，在上述的第一导电层0350上形成有第一绝缘层，用于保护上述的第一导电层0350。如图3与图4f所示，示出了位于第一导电层0350背离衬底基板10一侧的阳极层0360，阳极层0360包括阳极Y1、Y2、Y3、Y4。示例性地，第一颜色子像素spx1可以包括阳极Y1，第二颜色子像素spx2可以包括阳极Y2，第三颜色子像素spx3可以包括阳极Y3，第四颜色子像素spx4可以包括阳极Y4。
如图3至图4f所示，第一电源信号线VDD通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中对应的第一发光控制晶体管T4的源极区域电连接。第一电源信号线VDD通过贯穿第一层间绝缘层中的至少一个过孔与参考导电层0330中的存储电容CST的第一极cc1电连接。第一电源信号线VDD还通过贯穿第一层间绝缘层中的至少一个过孔与遮光层ZG电连接。以及，第一电源信号线VDD通过贯穿第一层间绝缘层中的至少一个过孔与参考导电层0330中的遮光层ZG电连接。
如图3至图4f所示，连接部LB1的一端通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中对应的阈值补偿晶体管T3的漏极区域电连接。连接部LB1的另一端通过贯穿第一层间绝缘层中的至少一个过孔与初始化线VINIT电连接。
如图3至图4f所示，连接部LB2的一端通过贯穿第二层间绝缘层中的过孔与数据线的信号凸起部TQ电连接，连接部LB2的另一端通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中的数据写入晶体管T2的源极区域电连接。
如图3至图4f所示，连接部LB3的一端通过贯穿层间介质层和第一层间绝缘层中的至少一个驱动过孔GK0与存储电容CST的第二极cc2(即驱动晶体管T1的驱动栅极)电连接。连接部LB3的另一端通过贯穿栅绝缘层、层间 介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中的初始化晶体管T6的漏极区域电连接。也就是说，驱动晶体管中的驱动栅极通过驱动过孔与有源半导体层电连接，指的可以是：驱动晶体管T1的驱动栅极通过驱动过孔GK0与连接部LB3的一端电连接，连接部LB3的另一端通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中的初始化晶体管T6的漏极区域电连接。并且，如图3至图4f所示，子像素中，驱动过孔GK0的至少部分在衬底基板的正投影分别与阳极转接部和信号线在衬底基板的正投影不交叠。
如图3至图4f所示，连接部LB4通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中的第二发光控制晶体管T5的漏极区域电连接。
在一些示例中，如图3至图4f所示，第一绝缘层包括第一过孔，第一过孔暴露阳极转接部的一部分，且阳极包括相互电连接的主体部分和辅助部分；其中，辅助部分通过第一过孔与阳极转接部电连接。例如，第一颜色子像素spx1中，阳极Y1包括相互电连接的主体部分Y11和辅助部分Y12，辅助部分Y12通过第一过孔K11与阳极转接部YZ1电连接，阳极转接部YZ1通过贯穿第二层间绝缘层的过孔与连接部LB4电连接。第二颜色子像素spx2中，阳极Y2包括相互电连接的主体部分Y21和辅助部分Y22，辅助部分Y22通过第一过孔K12与阳极转接部YZ2电连接，阳极转接部YZ2通过贯穿第二层间绝缘层的过孔与连接部LB4电连接。第三颜色子像素spx3中，阳极Y3包括相互电连接的主体部分Y31和辅助部分Y32，辅助部分Y32通过第一过孔K13与阳极转接部YZ3电连接，阳极转接部YZ3通过贯穿第二层间绝缘层的过孔与连接部LB4电连接。第四颜色子像素spx4中，阳极Y4包括相互电连接的主体部分Y41和辅助部分Y42，辅助部分Y42通过第一过孔K14与阳极转接部YZ4电连接，阳极转接部YZ4通过贯穿第二层间绝缘层的过孔与连接部LB4电连接。
需要说明的是，阳极包括的相互电连接的主体部分和辅助部分为一体结 构，即主体部分和辅助部分是连续形成的。
在一些示例中，如图3至图5所示，多个子像素包括第一子像素01和第二子像素02；其中，第一子像素01中，阳极转接部在衬底基板10的正投影与驱动有源层在衬底基板10的正投影不交叠，且主体部分在衬底基板10的正投影与阳极转接部在衬底基板10的正投影不交叠。以及，第二子像素02中，阳极转接部在衬底基板10的正投影与驱动有源层在衬底基板10的正投影交叠，且主体部分在衬底基板10的正投影与阳极转接部在衬底基板10的正投影交叠。这样一来，通过将部分子像素中的阳极的主体部分与阳极转接部进行交叠，可以通过阳极转接部对阳极的主体部分的平坦度进行调整，从而可以避免由于第一导电层导致的阳极不平整的情况出现，进而改善显示基板的色偏现象。
在一些示例中，阳极层背离衬底基板一侧还设置有像素限定层，像素限定层背离衬底基板一些还设置有发光层，发光层背离衬底基板一侧还设置有阴极层。这样可以使阳极、发光层以及阴极形成发光元件。示例性地，结合图4f至图6c，像素限定层可以包括多个开口区域(如：KK1、KK2、KK3、KK4)。其中，一个阳极对应一个开口区域，该开口区域在衬底基板10的正投影位于对应的阳极的主体部分在衬底基板10的正投影内。例如，第一颜色子像素中，开口区域KK1对应阳极Y1的主体部分Y11。第二颜色子像素中，开口区域KK2对应阳极Y2的主体部分Y21。第三颜色子像素中，开口区域KK3对应阳极Y3的主体部分Y31。第四颜色子像素中，开口区域KK4对应阳极Y4的主体部分Y41。在一些示例中，第二子像素中，阳极对应的开口区域在衬底基板的正投影与阳极转接部在衬底基板的正投影交叠。第一子像素中，阳极对应的开口区域在衬底基板的正投影与阳极转接部在衬底基板的正投影不交叠。例如，各个子像素的发光区域对应各个开口区域。例如第一颜色子像素的发光区域为其阳极对应的开口区域，第二颜色子像素的发光区域为其阳极对应的开口区域，第三颜色子像素的发光区域为其阳极对应的开口区域，第四颜色子像素的发光区域为其阳极对应的开口区域。
在一些示例中，如图3至图5以及图6d所示，第一子像素01包括第一颜色子像素spx1。也就是说，第一颜色子像素spx1中，阳极转接部YZ1在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影不交叠，且主体部分Y11在衬底基板10的正投影与阳极转接部YZ1在衬底基板10的正投影不交叠。进一步地，阳极转接部YZ1在衬底基板10的正投影与开口区域KK1在衬底基板10的正投影不交叠。
进一步地，第一颜色子像素spx1中，阳极转接部YZ1在衬底基板10的正投影与存储电容CST的第一极cc1在衬底基板10的正投影的边缘交叠，阳极转接部YZ1在衬底基板10的正投影与存储电容CST的第二极cc2在衬底基板10的正投影不交叠。
在一些示例中，如图3至图5所示，第一颜色子像素spx1中，主体部分Y11在衬底基板10的正投影与两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))在衬底基板10的正投影交叠，且主体部分Y11在衬底基板10的正投影与阳极转接部YZ1和信号凸起部在衬底基板10的正投影不交叠。在一些实施例中，第一颜色子像素spx1中，与主体部分Y11在衬底基板10的正投影交叠的两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))分别位于主体部分Y11中心的两侧。示例性地，第一颜色子像素spx1中的主体部分Y11具有沿第二方向F2的第一主体对称轴，第一颜色子像素spx1中，在第二方向F2上，主体部分Y11在衬底基板10的正投影交叠的两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))分别位于第一主体对称轴的相对的两侧。进一步地，第一颜色子像素spx1中，在第一方向F1上，与主体部分Y11在衬底基板10的正投影交叠的两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))与第一主体对称轴的距离比值为0.8～1.2。例如，在第一方向F1上，与主体部分Y11在衬底基板10的正投影交叠的两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条 数据线Vd))与第一主体对称轴的距离比值为0.8、1.0、1.1或1.2。进一步地，第一颜色子像素spx1中，主体部分Y11与连接同一像素电路的信号凸起部TQ不交叠。
在一些示例中，如图3至图5所示，第二子像素02可以包括：第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4中的至少一个。例如，第二子像素02包括第二颜色子像素spx2时，也就是说，第二颜色子像素spx2中，阳极转接部YZ2在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影交叠，且主体部分Y21在衬底基板10的正投影与阳极转接部YZ2在衬底基板10的正投影交叠。进一步地，开口区域KK2在衬底基板10的正投影与阳极转接部YZ2在衬底基板10的正投影交叠。进一步地，第二颜色子像素spx2中，主体部分Y21与连接同一像素电路的信号凸起部TQ不交叠。
进一步地，第二颜色子像素spx2中，阳极转接部YZ2在衬底基板10的正投影与存储电容CST的第一极cc1在衬底基板10的正投影交叠，以及阳极转接部YZ2在衬底基板10的正投影与存储电容CST的第二极cc2在衬底基板10的正投影也交叠。进一步地，在第二方向上，阳极转接部YZ2在衬底基板10的正投影穿过存储电容CST的第一极cc1在衬底基板10的正投影，以及在第二方向上，阳极转接部YZ2在衬底基板10的正投影也穿过存储电容CST的第二极cc2在衬底基板10的正投影。
例如，第二子像素02包括第三颜色子像素spx3时，也就是说，第三颜色子像素spx3中，阳极转接部YZ3在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影交叠，且主体部分Y31在衬底基板10的正投影与阳极转接部YZ3在衬底基板10的正投影交叠。进一步地，开口区域KK3在衬底基板10的正投影与阳极转接部YZ3在衬底基板10的正投影交叠。进一步地，第三颜色子像素spx3中，主体部分Y31与连接同一像素电路的信号凸起部TQ交叠。
进一步地，第三颜色子像素spx3中，阳极转接部YZ3在衬底基板10的 正投影与存储电容CST的第一极cc1在衬底基板10的正投影交叠，以及阳极转接部YZ3在衬底基板10的正投影与存储电容CST的第二极cc2在衬底基板10的正投影也交叠。进一步地，在第二方向上，阳极转接部YZ3在衬底基板10的正投影穿过存储电容CST的第一极cc1在衬底基板10的正投影，以及在第二方向上，阳极转接部YZ3在衬底基板10的正投影也穿过存储电容CST的第二极cc2在衬底基板10的正投影。
例如，第二子像素02包括第四颜色子像素spx4时，也就是说，第四颜色子像素spx4中，阳极转接部YZ4在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影交叠，且主体部分Y41在衬底基板10的正投影与阳极转接部YZ4在衬底基板10的正投影交叠。进一步地，开口区域KK4在衬底基板10的正投影与阳极转接部YZ4在衬底基板10的正投影交叠。进一步地，第四颜色子像素spx4中，主体部分Y41与连接同一像素电路的信号凸起部TQ不交叠。而第四颜色子像素spx4中的主体部分Y41与相邻的第二颜色子像素spx2连接的像素电路中的信号凸起部TQ交叠。
进一步地，第四颜色子像素spx4中，阳极转接部YZ4在衬底基板10的正投影与存储电容CST的第一极cc1在衬底基板10的正投影交叠，以及阳极转接部YZ4在衬底基板10的正投影与存储电容CST的第二极cc2在衬底基板10的正投影也交叠。进一步地，在第二方向上，阳极转接部YZ4在衬底基板10的正投影穿过存储电容CST的第一极cc1在衬底基板10的正投影，以及在第二方向上，阳极转接部YZ4在衬底基板10的正投影也穿过存储电容CST的第二极cc2在衬底基板10的正投影。
在一些示例中，如图3至图5所示，第二子像素02中的阳极转接部(即与主体部分在衬底基板10的正投影交叠的阳极转接部)可以包括：相互电连接的第一子阳极转接部和第二子阳极转接部；其中，第一子阳极转接部具有镂空结构，第二子阳极转接部具有实体结构；辅助部分通过第一过孔与第二子阳极转接部电连接。并且，第二子像素02中，第一子阳极转接部在衬底基板10的正投影与驱动有源层在衬底基板10的正投影交叠。需要说明的是， 实体结构指的可以是：第二子阳极转接部在衬底基板的正投影为整面的，其内部没有镂空。
示例性地，如图3至图5所示，第二颜色子像素spx2中，阳极转接部YZ2可以包括：相互电连接的第一子阳极转接部YZ21和第二子阳极转接部YZ22；其中，第一子阳极转接部YZ21具有镂空结构，第二子阳极转接部YZ22具有实体结构；辅助部分Y22通过第一过孔K12与第二子阳极转接部YZ22电连接。并且，第一子阳极转接部YZ21在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影交叠。
示例性地，如图3至图5所示，第三颜色子像素spx3中，阳极转接部YZ3可以包括：相互电连接的第一子阳极转接部YZ31和第二子阳极转接部YZ32；其中，第一子阳极转接部YZ31具有镂空结构，第二子阳极转接部YZ32具有实体结构；辅助部分Y32通过第一过孔K13与第二子阳极转接部YZ32电连接。并且，第一子阳极转接部YZ31在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影交叠。
示例性地，如图3至图5所示，第四颜色子像素spx4中，阳极转接部YZ4可以包括：相互电连接的第一子阳极转接部YZ41和第二子阳极转接部YZ42；其中，第一子阳极转接部YZ41具有镂空结构，第二子阳极转接部YZ42具有实体结构；辅助部分Y42通过第一过孔K14与第二子阳极转接部YZ42电连接。并且，第一子阳极转接部YZ41在衬底基板10的正投影与驱动有源层T1-A在衬底基板10的正投影交叠。
示例性地，如图3至图5所示，在第二方向F2，同一子像素中，扫描线在衬底基板10的正投影位于驱动有源层在衬底基板10的正投影背离第二子阳极转接部在衬底基板10的正投影一侧。并且，第二子像素02中，第一子阳极转接部在衬底基板10的正投影与扫描线在衬底基板10的正投影交叠。示例性地，如图3至图5所示，第二颜色子像素spx2中，第一子阳极转接部YZ21在衬底基板10的正投影与扫描线GA在衬底基板10的正投影交叠。
示例性地，如图3至图5所示，第三颜色子像素spx3中，第一子阳极转 接部YZ31在衬底基板10的正投影与扫描线GA在衬底基板10的正投影交叠。示例性地，第一子阳极转接部YZ31在衬底基板10的正投影至少部分被阳极Y3在衬底基板10的正投影覆盖。进一步地，第一子阳极转接部YZ31在衬底基板10的正投影基板均被阳极Y3在衬底基板10的正投影覆盖。
示例性地，如图3至图5所示，第四颜色子像素spx4中，第一子阳极转接部YZ41在衬底基板10的正投影与扫描线GA在衬底基板10的正投影交叠。
示例性地，第四颜色子像素spx4中的阳极Y4在衬底基板10的正投影覆盖部分阳极转接部YZ4在衬底基板10的正投影。第二颜色子像素spx2中的阳极Y2在衬底基板10的正投影覆盖部分阳极转接部YZ2在衬底基板10的正投影。并且，同一重复单元中，第二颜色子像素spx2中的阳极转接部YZ2被阳极Y2覆盖的部分的面积大于第四颜色子像素spx4中的阳极转接部YZ4被阳极Y4覆盖的部分的面积。
在一些示例中，如图3至图5所示，第二子像素02中，第一子阳极转接部中的镂空结构中的镂空区域LQ在衬底基板10的正投影与连接驱动栅极的过孔GK0在衬底基板10的正投影交叠。例如，第一子阳极转接部中的镂空结构在衬底基板10的正投影与存储电容CST的第一极cc1具有镂空区LQ交叠。该镂空区LQ作为过孔用于连接驱动栅极(即存储电容CST的第二极cc2)和其他晶体管，例如通过位于源漏金属层的连接线LB3连接阈值补偿晶体管的一极(源极或漏极)与驱动栅极(即存储电容CST的第二极cc2)。示例性地，如图3至图5所示，第二颜色子像素spx2中，第一子阳极转接部YZ21中的镂空结构在衬底基板10的正投影与驱动栅极的中心区域在衬底基板10的正投影交叠。并且，第一子阳极转接部YZ21中的镂空结构在衬底基板10的正投影与存储电容CST的第一极cc1具有镂空区交叠。第三颜色子像素spx3中，第一子阳极转接部YZ31中的镂空结构在衬底基板10的正投影与驱动栅极的中心区域在衬底基板10的正投影交叠。并且，第一子阳极转接部YZ21中的镂空结构在衬底基板10的正投影与存储电容CST的第一极cc1具有镂空区交叠。第四颜色子像素spx4中，第一子阳极转接部YZ41中的镂空结构在 衬底基板10的正投影与驱动栅极的中心区域在衬底基板10的正投影交叠。并且，第一子阳极转接部YZ21中的镂空结构在衬底基板10的正投影与存储电容CST的第一极cc1具有镂空区交叠。
在一些示例中，如图3至图5所示，第二子像素02中，主体部分Y21在衬底基板10的正投影与两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))在衬底基板10的正投影交叠。示例性地，如图3至图5所示，第二颜色子像素spx2中，主体部分Y21在衬底基板10的正投影与两条信号线(例如两条数据线Vd)在衬底基板10的正投影交叠。第三颜色子像素spx3中，主体部分Y31在衬底基板10的正投影与两条信号线(例如两条数据线Vd)在衬底基板10的正投影交叠。第四颜色子像素spx4中，主体部分Y41在衬底基板10的正投影与两条信号线(例如两条数据线Vd)在衬底基板10的正投影交叠。
在一些示例中，如图3至图5所示，第一子阳极转接部具有相对设置的第一子转接部和第二子转接部；其中，在第一方向上，第一子转接部在衬底基板10的正投影位于第二子转接部与两条信号线在衬底基板10的正投影之间。示例性地，可以使第一子转接部大致沿第二方向F2延伸，也可以使第二子转接部大致沿第二方向F2延伸。
示例性地，如图3至图5所示，第二颜色子像素spx2中，第一子阳极转接部YZ21具有相对设置的第一子转接部YZ211和第二子转接部YZ212；其中，第一子转接部YZ211在衬底基板10的正投影位于第二子转接部YZ212与和第二颜色子像素spx2的主体部分Y21交叠的两条信号线(例如两条数据线Vd)在衬底基板10的正投影之间。示例性地，第一子转接部YZ211相比第二子转接部YZ212靠近主体部分Y21的中心。例如，第二子转接部YZ212在衬底基板10的正投影与主体部分Y21在衬底基板10的正投影的边缘交叠。例如，在第一方向F1上，第一子转接部YZ211和第二子转接部YZ212与主体部分Y21投影交叠的部分均位于主体部分Y21投影中心的同一侧。示例性地，在第一方向F1上，第一子转接部YZ211和第二子转接部YZ212与主体 部分Y21投影交叠的部分均位于主体部分Y21投影中心的第一侧，与第二颜色子像素spx2的主体部分Y21交叠的两条信号线(例如两条数据线Vd)的投影分别位于主体部分Y21投影的中心的第二侧，第一侧和第二侧为相对的两侧。这样一来，可以使第一子转接部YZ211、第二子转接部YZ212以及和第二颜色子像素spx2的主体部分Y21交叠的两条信号线起到更好的平坦作用。进一步地，如图3至图5所示，第二颜色子像素spx2中，主体部分Y21与第二子阳极转接部YZ22部分交叠。进一步地，第二颜色子像素spx2中，在第二方向上，位于主体部分Y21投影中心第二侧的阳极转接部YZ2的投影完全贯穿主体部分Y21的投影，位于主体部分Y21投影中心第一侧的信号线的投影完全贯穿主体部分Y21的投影，以实现更好的平坦的效果。
示例性地，如图3至图5所示，第三颜色子像素spx3中，第一子阳极转接部YZ31具有相对设置的第一子转接部YZ311和第二子转接部YZ312；其中，第一子转接部YZ311在衬底基板10的正投影位于第二子转接部YZ312与和第三颜色子像素spx3的主体部分Y31交叠的两条信号线(例如两条数据线Vd)在衬底基板10的正投影之间。示例性地，第一子转接部YZ311相比第二子转接部YZ312靠近主体部分Y31的中心。例如，第二子转接部YZ312在衬底基板10的正投影与主体部分Y31在衬底基板10的正投影的边缘交叠。例如，在第一方向F1上，第一子转接部YZ311和第二子转接部YZ312与主体部分Y31投影交叠的部分均位于主体部分Y31投影中心的同一侧。
示例性地，在第一方向F1上，第一子转接部YZ311和第二子转接部YZ312与主体部分Y31投影交叠的部分均位于主体部分Y31投影中心的第一侧，与第三颜色子像素spx3的主体部分Y31交叠的两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))的投影分别位于主体部分Y31投影的中心的第二侧，第一侧和第二侧为相对的两侧。这样一来，可以使第一子转接部YZ311、第二子转接部YZ312以及和第三颜色子像素spx3的主体部分Y31交叠的两条信号线起到更好的平坦作用。进一步地，第三颜色子像素spx3中，在第二方向上，位于主体部分Y31投影中心 第一侧的信号线的投影完全贯穿主体部分Y31的投影，以实现更好的平坦的效果。
示例性地，如图3至图5所示，第三颜色子像素spx3中，信号凸起部TQ和阳极转接部YZ3在第一方向上交叠。或者，平行于第二方向的直线可以穿过信号凸起部TQ和阳极转接部YZ3。进一步地，在第二方向上，信号凸起部TQ和阳极转接部YZ3不交叠，且阳极转接部YZ3至少部分位于主体部分Y31的中心远离信号凸起部TQ的一侧。这样可以使阳极转接部YZ3和信号凸起部TQ分别位于主体部分Y31的中心的两侧，从而可以进一步使阳极Y3更平坦。进一步地，第三颜色子像素spx3中，还可以使信号凸起部TQ的中心与和第三颜色子像素spx3的主体部分Y31交叠的两条数据线的中心线分别位于主体部分Y31的中心的两侧。这样一来可以进一步使阳极Y3更平坦。
示例性地，如图3至图5所示，第四颜色子像素spx4中，第一子阳极转接部YZ41具有相对设置的第一子转接部YZ411和第二子转接部YZ412；其中，第一子转接部YZ411在衬底基板10的正投影位于第二子转接部YZ412与和第四颜色子像素spx4的主体部分Y41交叠的两条信号线(例如下述的第一信号线组(如两条数据线Vd)或第二信号线组(如两条数据线Vd))在衬底基板10的正投影之间。示例性地，第一子转接部YZ411相比第二子转接部YZ412靠近主体部分Y41的中心。例如，在第一方向F1上，第一子转接部YZ311和第二子转接部YZ312与主体部分Y31投影交叠的部分均位于主体部分Y31投影中心的同一侧。示例性地，在第一方向F1上，第一子转接部YZ311和第二子转接部YZ312与主体部分Y31投影交叠的部分均位于主体部分Y31投影中心的第一侧，与第四颜色子像素spx4的主体部分Y41交叠的两条信号线(例如两条数据线Vd)的投影分别位于主体部分Y41投影的中心的第二侧，第一侧和第二侧为相对的两侧。这样一来，可以使第一子转接部YZ411、第二子转接部YZ412以及和第四颜色子像素spx4的主体部分Y41交叠的两条信号线起到更好的平坦作用。进一步地，第四颜色子像素spx4中，主体部分Y41完全覆盖第二子阳极转接部YZ42。进一步地，第四颜色子像素spx4中， 与主体部分Y41交叠的信号凸起部TQ位于阳极转接部YZ4背离交叠的主体部分Y41的一侧。进一步地，第四颜色子像素spx4中，在第二方向上，位于主体部分Y41投影中心第一侧的信号线的投影完全贯穿主体部分Y41的投影，以实现更好的平坦的效果。
示例性地，如图3至图5所示，和第二颜色子像素spx2中的主体部分Y21交叠的两条信号线位于同一重复单元中第二颜色子像素spx2靠近第一颜色子像素spx1的一侧，且第二颜色子像素spx2中的阳极转接部YZ2位于同一重复单元中第二颜色子像素spx2靠近第三颜色子像素spx3的一侧。和第四颜色子像素spx4中的主体部分Y41交叠的两条信号线位于同一重复单元中第四颜色子像素spx4靠近第三颜色子像素spx3的一侧，且第四颜色子像素spx4中的阳极转接部YZ4位于同一重复单元中第四颜色子像素spx4远离第三颜色子像素spx3的一侧。这样一来，可以使和第二颜色子像素spx2中的主体部分Y21交叠的两条信号线以及和第四颜色子像素spx4中的主体部分Y41交叠的两条信号线均位于同一侧。
在一些示例中，如图3至图6a所示，第二子像素02包括第二颜色子像素spx2时，在第二颜色子像素spx2中，主体部分Y21在衬底基板10的正投影与第一子阳极转接部YZ21在衬底基板10的正投影交叠。示例性地，第二颜色子像素spx2中，主体部分Y21在衬底基板10的正投影与第一子转接部YZ211和第二子转接部YZ212在衬底基板10的正投影均交叠。示例性地，第二颜色子像素spx2中的主体部分Y21具有沿第二方向F2的第二主体对称轴；并且，第二颜色子像素spx2中，两条信号线(例如两条数据线Vd)的与主体部分Y21在衬底基板10的正投影交叠的部分沿第二方向F2的中心线，与第一子转接部YZ211和第二子转接部YZ212沿第二方向F2的中心线分别位于第二主体对称轴相对的两侧。示例性地，与主体部分Y21在衬底基板10的正投影交叠的两条信号线(例如两条数据线Vd)沿第二方向F2的中心线，与第一子转接部YZ211和第二子转接部YZ212沿第二方向F2的中心线与第二主体对称轴之间的距离的比值为0.8～1.2，例如可以为0.8、0.9、1.0、1.1以及 1.2中的一个。这样通过数据线Vd和第一子转接部YZ211和第二子转接部YZ212对主体部分Y21进行支撑，可以使主体部分Y21尽可能平坦，从而可以降低主体部分Y21的不对称性。进而可以改善有效发光区EQ的发光不对称性，甚至消除有效发光区EQ的发光不对称性，从而可改善，甚至消除显示基板的色偏现象。
在一些示例中，如图3至图5以及图6b所示，第二子像素02包括第四颜色子像素spx4时，第四颜色子像素spx4中，主体部分Y41在衬底基板10的正投影与第二子阳极转接部YZ42在衬底基板10的正投影交叠，且主体部分Y41在衬底基板10的正投影与两条信号线(例如两条数据线Vd)在衬底基板10的正投影交叠。示例性地，在第二方向F2上，第四颜色子像素spx4中，主体部分Y41的至少部分在衬底基板10的正投影位于第二子阳极转接部YZ42在衬底基板10的正投影背离第一子阳极转接部YZ41在衬底基板10的正投影一侧。示例性地，第四颜色子像素spx4中的主体部分具有沿第二方向F2的第四主体对称轴；第四颜色子像素spx4中，两条信号线(例如两条数据线Vd)与主体部分Y41在衬底基板10的正投影交叠的部分，沿第二方向F2的中心线，与第二子阳极转接部YZ42沿第二方向F2的中心线分别位于第四主体对称轴的两侧。示例性地，与主体部分Y41在衬底基板10的正投影交叠的两条信号线(例如两条数据线Vd)沿第二方向F2的中心线，与第二子阳极转接部YZ42沿第二方向F2的中心线与第四主体对称轴之间的距离的比值为0.8～1.2，例如可以为0.8、1.0以及1.2中的一个。进一步地，沿第二方向，例如同一列中，第四颜色子像素spx4中的主体部分Y41在衬底基板10的正投影与相邻的第二颜色子像素spx2中的信号凸起部在衬底基板10的正投影交叠。这样通过数据线Vd第二子阳极转接部YZ42以及信号凸起部对主体部分Y41进行支撑，可以使主体部分Y41尽可能平坦，从而可以降低主体部分Y41的不对称性。进而可以改善有效发光区EQ的发光不对称性，甚至消除有效发光区EQ的发光不对称性，从而可改善，甚至消除显示基板的色偏现象。
在一些示例中，如图3至图5所示，一个第四颜色子像素spx4中的第二 子阳极转接部YZ42在衬底基板10的正投影的面积大于一个第二颜色子像素spx2中的第二子阳极转接部YZ22在衬底基板10的正投影的面积。例如，第二颜色子像素spx2中的第二子阳极转接部YZ22在衬底基板10的正投影沿第二方向F2具有第二宽度W2，第四颜色子像素spx4中的第二子阳极转接部YZ42在衬底基板10的正投影沿第二方向F2具有第四宽度W4；第四宽度W4大于第二宽度W2。
示例性地，如图4e所示，第二颜色子像素spx2中的第二子阳极转接部YZ22在衬底基板10的正投影沿第一方向F1具有第一宽度W1，可以使W2:W1设置为1.5:1。在实际应用中，不同第二颜色子像素spx2的尺寸对第一宽度W1和第二宽度W2的数值的需求不同，因此结合W2:W1设置为1.5:1的条件，根据实际应用需求设置第一宽度W1和第二宽度W2的数值，在此不作限定。例如，第二宽度W2可以为5～18微米。例如第二宽度W2可以为10～15微米。例如，第二宽度W2可以为5微米，第二宽度W2也可以为10微米，第二宽度W2也可以为12微米，第二宽度W2也可以为15微米，第二宽度W2也可以为18微米。例如，第一宽度W1可以为4～15微米。例如第一宽度W1为8～12微米。例如，第一宽度W1可以为4微米，第一宽度W1也可以为8微米，第一宽度W1也可以为10微米，第一宽度W1也可以为12微米，第一宽度W1也可以为15微米。例如，第二子阳极转接部YZ22的尺寸至少要大于过孔的尺寸。例如，一个过孔的尺寸例如大约为5*5微米。例如，一个过孔的尺寸例如大约为4*4微米。例如，一个过孔的尺寸例如大约为3*4微米。例如，一个过孔的尺寸例如大约为3*3微米。例如，一个过孔的尺寸例如为圆形孔，直径为2～5微米。
示例性地，如图4e所示，第三颜色子像素spx3中的第二子阳极转接部YZ32在衬底基板10的正投影沿第一方向F1具有第五宽度W5，第三颜色子像素spx3中的第二子阳极转接部YZ32在衬底基板10的正投影沿第二方向F2具有第六宽度W6，可以使W6:W5设置为1.5:1。在实际应用中，不同第三颜色子像素spx3的尺寸对第五宽度W5和第六宽度W6的数值的需求不同， 因此结合W6:W5设置为1.5:1的条件，根据实际应用需求设置第五宽度W5和第六宽度W6的数值，在此不作限定。例如，第六宽度W6可以为5～18微米。例如第六宽度W6可以为10～15微米。例如，第六宽度W6可以为5微米，第六宽度W6也可以为10微米，第六宽度W6也可以为12微米，第六宽度W6也可以为15微米，第六宽度W6也可以为18微米。例如，第五宽度W5可以为4～18微米。例如第五宽度W5为8～15微米。例如，第五宽度W5可以为4微米，第五宽度W5也可以为8微米，第五宽度W5也可以为10微米，第五宽度W5也可以为15微米，第五宽度W5也可以为18微米。例如，第二子阳极转接部YZ32的尺寸至少要大于过孔的尺寸。例如，一个过孔的尺寸例如大约为5*5微米。例如，一个过孔的尺寸例如大约为4*4微米。例如，一个过孔的尺寸例如大约为3*4微米。例如，一个过孔的尺寸例如大约为3*3微米。例如，一个过孔的尺寸例如为圆形孔，直径为2～5微米。
示例性地，如图4e与图5所示，第四颜色子像素spx4中的第二子阳极转接部YZ42在衬底基板10的正投影沿第一方向F1具有第三宽度W3，在第二方向F2具有第四宽度W4，可以使W4:W3设置为2:1。例如，第四颜色子像素spx4的开口区域的中心相比其他子像素(例如，spx1，spx2和spx3中至少一个)的开口区域的中心更远离阳极转接部或者更远离阳极转接部在第二方向尺寸的中点，因此第四颜色子像素spx4的第二子阳极转接部YZ42在第二方向的尺寸相比其他子像素更大。例如，各个子像素的第二子阳极转接部在第一方向尺寸大致相等。在实际应用中，不同第三颜色子像素spx3的尺寸对第三宽度W3和第四宽度W4的数值的需求不同，因此结合W4:W3设置为2:1的条件，根据实际应用需求设置第三宽度W3和第四宽度W4的数值，在此不作限定。例如，第四宽度W4可以为10～30微米。例如第四宽度W4可以为14～25微米。例如，第四宽度W4可以为16～24微米。例如，第四宽度W4可以为10微米，第四宽度W4也可以为14微米，第四宽度W4也可以为16微米，第四宽度W4也可以为20微米，第四宽度W4也可以为24微米，第四宽度W4也可以为25微米，第四宽度W4也可以为30微米。例如第三宽 度W3为8～15微米。例如第三宽度W3为10～13微米。例如，第三宽度W3可以为8微米，第三宽度W3也可以为10微米，第三宽度W3也可以为12微米，第三宽度W3也可以为13微米，第三宽度W3也可以为15微米。进一步地，第二子阳极转接部YZ42的尺寸至少要大于过孔的尺寸。例如，一个过孔的尺寸例如大约为5*5微米。例如，一个过孔的尺寸例如大约为4*4微米。例如，一个过孔的尺寸例如大约为3*4微米。例如，一个过孔的尺寸例如大约为3*3微米。例如，一个过孔的尺寸例如为圆形孔，直径为2～5微米。
示例性地，如图4e所示，第一颜色子像素spx1中的阳极转接部YZ1在衬底基板10的正投影沿第一方向F1具有第七宽度W7，第一颜色子像素spx1中的阳极转接部YZ1在衬底基板10的正投影沿第二方向F2具有第八宽度W8，可以使W8:W7设置为1.5:1。在实际应用中，不同第一颜色子像素spx1的尺寸对第七宽度W7和第八宽度W8的数值的需求不同，因此结合W8:W7设置为1.5:1的条件，根据实际应用需求设置第七宽度W7和第八宽度W8的数值，在此不作限定。例如，第八宽度W8可以为5～18微米。例如第八宽度W8可以为10～15微米。例如，第八宽度W8可以为5微米，第八宽度W8也可以为10微米，第八宽度W8也可以为13微米，第八宽度W8也可以为15微米，第八宽度W8也可以为18微米。例如，第七宽度W7可以为4～15微米。例如第七宽度W7为8～12微米。例如，第七宽度W7可以为4微米，第七宽度W7也可以为8微米，第七宽度W7也可以为10微米，第七宽度W7也可以为12微米，第七宽度W7也可以为15微米。例如，第二子阳极转接部YZ12的尺寸至少要大于过孔的尺寸。例如，一个过孔的尺寸例如大约为5*5微米。例如，一个过孔的尺寸例如大约为4*4微米。例如，一个过孔的尺寸例如大约为3*4微米。例如，一个过孔的尺寸例如大约为3*3微米。例如，一个过孔的尺寸例如为圆形孔，直径为2-5微米。
在一些示例中，如图3至图5以及图6c所示，第二子像素02包括第三颜色子像素spx3时，第三颜色子像素spx3中，主体部分Y31在衬底基板10的正投影与第一子阳极转接部YZ31在衬底基板10的正投影交叠，且主体部 分Y31在衬底基板10的正投影与两条信号线(例如两条数据线Vd)在衬底基板10的正投影交叠。示例性地，第三颜色子像素spx3中，主体部分Y31在衬底基板10的正投影与第一子转接部YZ311和第二子转接部YZ312在衬底基板10的正投影均交叠。示例性地，第三颜色子像素spx3中的主体部分Y31具有沿第二方向F2的第三主体对称轴；并且，第三颜色子像素spx3中，两条信号线(例如两条数据线Vd)与主体部分Y31在衬底基板10的正投影交叠的部分，沿第二方向F2的中心线，与第一子转接部YZ311和第二子转接部YZ312沿第二方向F2的中心线分别位于第三主体对称轴相对的两侧。示例性地，与主体部分Y31在衬底基板10的正投影交叠的两条信号线(例如两条数据线Vd)沿第二方向F2的中心线，与第一子转接部YZ311和第二子转接部YZ312沿第二方向F2的中心线与第三主体对称轴之间的距离的比值为0.8～1.2，例如可以为0.8、0.9、1.0、1.1以及1.2中的一个。进一步地，第三颜色子像素spx3中，主体部分Y31在衬底基板10的正投影覆盖信号凸起部在衬底基板10的正投影。示例性地，第三颜色子像素spx3中，信号凸起部位于第一子阳极转接部YZ31远离第二子阳极转接部YZ32的一侧。
在一些示例中，如图3与图4e所示，信号凸起部TQ包括凸起部主体tq1和连接凸起部主体tq1与数据线Vd的连接部tq2。例如，信号凸起部TQ用于信号线与其他膜层的电连接，一般通过过孔连接，例如，凸起部主体tq1上设置有其一体连接的数据线Vd与其他膜层连接的过孔，所以其对应的在第一方向F1和第二方向F2的尺寸不能过小，至少要大于过孔的尺寸。例如，一个过孔的尺寸例如为4*4微米。例如，一个过孔的尺寸例如为3*3微米。例如，一个过孔的尺寸例如为圆形孔，直径为2～4微米。例如，凸起部主体tq1上传输的是用于各个子像素显示的数据信号，为了减小与其他信号的干扰，其对应的在第一方向F1和第二方向F2的尺寸也不能过大。例如，在第一方向F1，凸起部主体tq1与相邻的另一信号线例如数据线之间具有间隔，该间隔例如为3～18微米。例如，同一条数据线Vd上用于连接奇数行和偶数行中之一的第一凸起部，和用于连接奇数行和偶数行中另外一个的第二凸起部与相邻另一 条数据线的间隔不同。例如，以连接奇数行的信号凸起部主体tq1为第一凸起部T1，以连接偶数行的信号凸起部主体tq1为第二凸起部T2，第一凸起部T1与其相邻的数据线之间的间距和第二凸起部与其相邻的数据线之间的间距不同。例如，同一列中第一凸起部T1和第二凸起部T2沿第二方向F2交替排列。例如第一凸起部T1到相邻另一条数据线的间隔为3～8微米。例如第二凸起部T2到相邻另一条数据线的间隔为6～18微米。例如，第一凸起部T1和第二凸起部T2的尺寸大致相等。例如，第一凸起部T1和第二凸起部T2尺寸形状大致为一个矩形块。例如，连接第一凸起部T1和数据线的连接部tq2在第一方向F1的尺寸大致为6～20微米。例如，连接第二凸起部T2和数据线的连接部tq2在第一方向F1的尺寸大致为3～8微米。例如，相邻两个像素电路区域之间相邻的有两条数据线，该两条数据线对应的凸起部大致平齐，即大致在第二方向F2上位于同一高度，且一个具有第一凸起部T1，另一个具有第二凸起部T2。
在一些示例中，如图3至图5所示，同一第一子阳极转接部中的第一子转接部和第二子转接部在第一方向F1上的距离与两条信号线在第一方向F1上的距离之间的比值可以为0.8～1.2。例如，同一第一子阳极转接部中的第一子转接部和第二子转接部在第一方向F1上的距离与两条信号线在第一方向F1上的距离之间的比值可以为0.8、1.0、1.1或1.2。
在一些示例中，如图3至图5所示，同一第一子阳极转接部中的第一子转接部和第二子转接部在第一方向F1上的距离与两条信号线在第一方向F1上的距离大致相同。示例性地，第二颜色子像素spx2中，同一第一子阳极转接部YZ21中的第一子转接部YZ211和第二子转接部YZ212在第一方向F1上的距离H1与两条信号线(例如两条数据线Vd)在第一方向F1上的距离H2大致相同。第三颜色子像素spx3中，同一第一子阳极转接部YZ31中的第一子转接部YZ311和第二子转接部YZ312在第一方向F1上的距离H1与两条信号线(例如两条数据线Vd)在第一方向F1上的距离H2大致相同。第四颜色子像素spx4中，同一第一子阳极转接部YZ41中的第一子转接部YZ411 和第二子转接部YZ412在第一方向F1上的距离H1与两条信号线(例如两条数据线Vd)在第一方向F1上的距离H2大致相同。
示例性地，可以使距离H2设置为5～7μm。例如，可以使距离H2设置为5μm，也可以使距离H2设置为6μm，也可以使距离H2设置为7μm。当然，在实际应用中，可以根据实际应用的需求确定距离H2的具体数值，在此不作限定。
示例性地，可以使距离H1设置为5～6μm。例如，可以使距离H1设置为5μm，也可以使距离H1设置为5.5μm，也可以使距离H1设置为6μm。当然，在实际应用中，可以根据实际应用的需求确定距离H1的具体数值，在此不作限定。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述电致发光显示基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述电致发光显示基板的实施例，重复之处不再赘述。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (27)

  1. 一种显示基板，其中，包括：
    多个子像素，所述多个子像素中的至少一个子像素包括：位于衬底基板上的像素电路和发光元件，所述像素电路包括驱动晶体管，用于驱动发光元件发光；
    所述显示基板包括有源半导体层；所述驱动晶体管的驱动有源层位于所述有源半导体层中；
    所述驱动晶体管中的驱动栅极通过驱动过孔与所述有源半导体层电连接；
    第一导电层，位于所述有源半导体层背离衬底基板一侧，并且所述第一导电层包括相互间隔设置的阳极转接部和信号线；
    所述子像素中，所述驱动过孔的至少部分在所述衬底基板的正投影分别与所述阳极转接部和所述信号线在所述衬底基板的正投影不交叠。
  2. 如权利要求1所述的显示基板，其中，所述显示基板还包括：
    第一绝缘层，位于所述第一导电层背离所述衬底基板一侧，并且所述第一绝缘层包括第一过孔，所述第一过孔暴露所述阳极转接部的至少一部分；
    所述发光元件包括阳极，所述阳极位于所述第一绝缘层背离所述衬底基板一侧，并且所述阳极包括相互电连接的主体部分和辅助部分；其中，所述辅助部分通过所述第一过孔与所述阳极转接部电连接；
    其中，所述多个子像素包括第一子像素和第二子像素；
    所述第一子像素中，所述阳极转接部在所述衬底基板的正投影与所述驱动有源层在所述衬底基板的正投影不交叠，且所述主体部分在所述衬底基板的正投影与所述阳极转接部在所述衬底基板的正投影不交叠；
    所述第二子像素中，所述阳极转接部在所述衬底基板的正投影与所述驱动有源层在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与所述阳极转接部在所述衬底基板的正投影交叠。
  3. 如权利要求2所述的显示基板，其中，所述第二子像素中的所述阳极 转接部包括：相互电连接的第一子阳极转接部和第二子阳极转接部；其中，所述第一子阳极转接部具有镂空结构，所述第二子阳极转接部具有实体结构；所述辅助部分通过所述第一过孔与所述第二子阳极转接部电连接；
    所述第二子像素中，所述第一子阳极转接部在所述衬底基板的正投影与所述驱动有源层在所述衬底基板的正投影交叠。
  4. 如权利要求3所述的显示基板，其中，所述显示基板还包括：位于所述有源半导体层与所述第一导电层之间的栅导电层，所述栅导电层包括：扫描线；
    在平行于所述衬底基板的方向上，同一所述第二子像素中，所述扫描线在所述衬底基板的正投影位于所述驱动有源层在所述衬底基板的正投影背离所述第二子阳极转接部在所述衬底基板的正投影一侧；
    所述第二子像素中，所述第一子阳极转接部在所述衬底基板的正投影与所述扫描线在所述衬底基板的正投影交叠。
  5. 如权利要求1-3任一项所述的显示基板，其中，所述第二子像素中，所述第一子阳极转接部中的镂空结构中的镂空区域在所述衬底基板的正投影与所述驱动过孔在所述衬底基板的正投影交叠。
  6. 如权利要求2-5任一项所述的显示基板，其中，所述第一子阳极转接部具有相对设置的第一子转接部和第二子转接部；
    所述第二子像素中，所述主体部分在所述衬底基板的正投影与两条信号线在所述衬底基板的正投影交叠；且在第一方向上，所述第一子转接部在所述衬底基板的正投影位于所述第二子转接部与所述两条信号线在所述衬底基板的正投影之间。
  7. 如权利要求1-6任一项所述的显示基板，其中，多个重复单元中的至少一个包括：第一颜色子像素、第二颜色子像素、第三颜色子像素以及第四颜色子像素；其中，所述多个重复单元沿第一方向排列形成重复单元组，所述重复单元组沿第二方向排列，所述第一方向与所述第二方向不同；
    所述第一子像素包括所述第一颜色子像素；
    所述第二子像素包括：第二颜色子像素、第三颜色子像素以及所述第四颜色子像素中的至少一个。
  8. 如权利要求7所述的显示基板，其中，所述第二子像素包括所述第二颜色子像素；
    所述第二颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子阳极转接部在所述衬底基板的正投影交叠。
  9. 如权利要求8所述的显示基板，其中，所述第二颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子转接部和所述第二子转接部在所述衬底基板的正投影均交叠。
  10. 如权利要求9所述的显示基板，其中，所述第二颜色子像素中的主体部分具有沿所述第二方向的第二主体对称轴；
    所述第二颜色子像素中，所述两条信号线的与所述主体部分在所述衬底基板的正投影交叠的部分沿所述第二方向的中心线，与所述第一子转接部和所述第二子转接部沿所述第一方向的中心线分别位于所述第二主体对称轴的相对的两侧。
  11. 如权利要求7-10任一项所述的显示基板，其中，所述第二子像素包括所述第四颜色子像素；
    所述第四颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第二子阳极转接部在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与两条所述信号线在所述衬底基板的正投影交叠。
  12. 如权利要求11所述的显示基板，其中，在所述第二方向上，所述第四颜色子像素中，所述主体部分的至少部分在所述衬底基板的正投影位于所述第二子阳极转接部在所述衬底基板的正投影背离所述第一子阳极转接部在所述衬底基板的正投影一侧。
  13. 如权利要求12所述的显示基板，其中，所述第四颜色子像素中的主体部分具有沿所述第二方向的第四主体对称轴；
    所述第四颜色子像素中，所述两条信号线与所述主体部分在所述衬底基 板的正投影交叠的部分，沿所述第二方向的中心线，与所述第二子阳极转接部沿所述第二方向的中心线分别位于所述第四主体对称轴相对的两侧。
  14. 如权利要求13所述的显示基板，其中，各所述信号线还包括信号凸起部；所述多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条所述第一信号线和一条所述第二信号线；所述第一信号线的信号凸起部分别电连接奇数行子像素，所述第二信号线的信号凸起部分别电连接偶数行子像素；
    沿所述第二方向相邻的重复单元中的第二颜色子像素和第四颜色子像素沿所述第二方向相邻；
    沿所述第二方向，所述第四颜色子像素中的主体部分在所述衬底基板的正投影与相邻的所述第二颜色子像素中的信号凸起部在所述衬底基板的正投影交叠。
  15. 如权利要求13所述的显示基板，其中，各所述信号线还包括信号凸起部；所述多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条所述第一信号线和一条所述第二信号线；所述第一信号线的信号凸起部分别电连接奇数行子像素，所述第二信号线的信号凸起部分别电连接偶数行子像素；
    相邻两列子像素对应的两条第一信号线和两条第二信号线中，其中的两条第一信号线相邻形成一个第一信号线组，或者，其中的两条第二信号线相邻形成一个第二信号线组。
  16. 如权利要求8-15任一项所述的显示基板，其中，一个所述第四颜色子像素中的第二子阳极转接部在所述衬底基板的正投影的面积大于一个所述第二颜色子像素中的第二子阳极转接部在所述衬底基板的正投影的面积。
  17. 如权利要求16所述的显示基板，其中，所述第二颜色子像素中的第二子阳极转接部在所述衬底基板的正投影沿所述第二方向具有第二宽度，所述第四颜色子像素中的第二子阳极转接部在所述衬底基板的正投影沿所述第二方向具有第四宽度；所述第四宽度大于所述第二宽度。
  18. 如权利要求7-17任一项所述的显示基板，其中，所述第二子像素包括所述第三颜色子像素；
    所述第三颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子阳极转接部在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与两条所述信号线在所述衬底基板的正投影交叠。
  19. 如权利要求18所述的显示基板，其中，所述第三颜色子像素中，所述主体部分在所述衬底基板的正投影与所述第一子转接部和所述第二子转接部在所述衬底基板的正投影均交叠。
  20. 如权利要求19所述的显示基板，其中，所述第三颜色子像素中的主体部分具有沿所述第二方向的第三主体对称轴；
    所述第三颜色子像素中，所述两条信号线与所述主体部分在所述衬底基板的正投影交叠的部分，沿所述第二方向的中心线，与所述第一子转接部和所述第二子转接部沿所述第二方向的中心线分别位于所述第三主体对称轴的相对的两侧。
  21. 如权利要求20所述的显示基板，其中，所述第三颜色子像素中，所述主体部分在所述衬底基板的正投影覆盖所述信号凸起部在所述衬底基板的正投影。
  22. 如权利要求21所述的显示基板，其中，所述第三颜色子像素中，所述信号凸起部位于所述第一子阳极转接部远离所述第二子阳极转接部的一侧。
  23. 如权利要求7-22任一项所述的显示基板，其中，所述第一颜色子像素中，所述主体部分在所述衬底基板的正投影与两条所述信号线在所述衬底基板的正投影交叠，且所述主体部分在所述衬底基板的正投影与所述阳极转接部和信号凸起部在所述衬底基板的正投影不交叠。
  24. 如权利要求23所述的显示基板，其中，所述第一颜色子像素中的主体部分具有沿所述第二方向的第一主体对称轴；
    所述第一颜色子像素中，在所述第二方向上，与所述主体部分在所述衬底基板的正投影交叠的所述两条信号线分别位于所述第一主体对称轴的相对 的两侧。
  25. 如权利要求6-24任一项所述的显示基板，其中，同一所述第一子阳极转接部中的第一子转接部和第二子转接部在所述第一方向上的距离与所述两条信号线在所述第一方向上的距离比值为0.8～1.2。
  26. 如权利要求1-25任一项所述的显示基板，其中，所述信号线被配置为传输数据信号的数据线。
  27. 一种显示装置，其中，包括如权利要求1-26任一项所述的显示基板。
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