WO2022041204A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022041204A1
WO2022041204A1 PCT/CN2020/112496 CN2020112496W WO2022041204A1 WO 2022041204 A1 WO2022041204 A1 WO 2022041204A1 CN 2020112496 W CN2020112496 W CN 2020112496W WO 2022041204 A1 WO2022041204 A1 WO 2022041204A1
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WIPO (PCT)
Prior art keywords
sub
pixel
anode
signal line
effective
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Application number
PCT/CN2020/112496
Other languages
English (en)
French (fr)
Inventor
尚庭华
张毅
青海刚
于鹏飞
周洋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/112496 priority Critical patent/WO2022041204A1/zh
Priority to US17/416,595 priority patent/US20230200155A1/en
Priority to CN202080001750.4A priority patent/CN114450798A/zh
Publication of WO2022041204A1 publication Critical patent/WO2022041204A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80516—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • the first conductive layer is located on one side of the base substrate, and the first conductive layer includes: signal lines arranged in sequence along the first direction and extending in the second direction, at least partially adjacent to the two signal lines Signal line protruding parts and anode adapter parts arranged at intervals therebetween, the signal line protruding parts are integrally connected with the signal lines;
  • a pixel defining layer located on a side of the first conductive layer away from the base substrate, comprising a plurality of sub-pixel openings corresponding to the sub-pixels;
  • each of the anodes includes an effective portion exposed by the sub-pixel opening, and the anode transfer portion is connected to the anode through an insulating layer via hole connect;
  • the effective parts of the sub-pixels have overlapping regions with the signal line protrusions and the anode transfer parts in the second direction, and the second direction and the first One direction is vertical.
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel, and the area of the anode of the first sub-pixel is larger than the area of the anode of the second sub-pixel ;
  • the effective portion of the first sub-pixel has an overlapping area with both the signal line protruding portion and the anode transfer portion in the second direction.
  • the overlapping area of the effective portion of the first sub-pixel and the signal line protrusion is a first overlapping area, and the effective portion of the first sub-pixel
  • the overlapping area with the anode transfer part is the second overlapping area
  • the first overlapping area and the second overlapping area are located on both sides of the center of the effective portion of the first subpixel, respectively.
  • the ratio of the distance between the first overlapping area and the second overlapping area to the center of the effective portion of the first sub-pixel is 0.8 ⁇ 1.2.
  • the orthographic projection of the anode transfer portion of the second sub-pixel on the base substrate covers the center of the orthographic projection of the effective portion on the base substrate, and all The size of the anode transfer portion of the second sub-pixel in the second direction is larger than the maximum size of the effective portion in the second direction.
  • the length of the anode transfer portion of the second sub-pixel in the second direction is greater than that of the anode transfer portion of the first sub-pixel in the second direction. length in both directions.
  • the signal line protruding portion includes: a protruding main portion, and a protruding connecting portion connecting the protruding main portion and the signal line;
  • the length of the protruding main portion in the second direction is greater than the length of the protruding connecting portion in the second direction.
  • the ratio of the length of the protruding main portion in the first direction to the length of the anode adapter portion in the first direction is 0.8 ⁇ 1.2.
  • the length of the protruding main portion in the second direction is smaller than the length of the anode adapter portion in the second direction.
  • the ratio of the length of the interval in the first direction to the length of the protruding connecting portion in the first direction is 0.8 ⁇ 1.2.
  • the effective portion of the first sub-pixel is a rhombus
  • the overlapping area of the effective portion of the first sub-pixel and the protruding main portion is approximately a triangular area; the overlapping area of the effective portion of the first sub-pixel and the anode transfer portion is approximately a triangular area;
  • the overlapping area of the effective part of the first sub-pixel and the protruding main part, the overlapping area of the effective part of the first sub-pixel and the anode transfer part respectively corresponds to a diamond shape two opposite corners.
  • the anode includes a main body part and an auxiliary part that are electrically connected to each other; the main body part includes the effective part, and an anode expansion part extended from the effective part;
  • the anode extension portion of the first sub-pixel further includes an anode shielding portion on the side facing the second sub-pixel, and the anode shielding portion covers the first region in the orthographic projection of the base substrate, wherein,
  • the first region includes a region between two channel regions of a threshold compensation transistor in a pixel circuit corresponding to at least part of the second sub-pixel.
  • a side of the protruding main portion that is far away from the anode transfer portion and a side of the protruding connecting portion that are far away from the anode transfer portion are in roughly the same straight line.
  • the shape of the effective portion of the second sub-pixel is approximately a quadrilateral area
  • the size of the overlapping portion of the effective portion and the anode transfer portion accounts for 50% to 100% of the size of the effective portion.
  • the auxiliary part is connected to the anode through a first via hole penetrating the first insulating layer electrical connection;
  • the orthographic projection of the first via hole on the base substrate does not overlap with the orthographic projection of the region of the anode transfer portion overlapping the effective portion on the base substrate.
  • the patterns of the overlapping signal line protrusions of two adjacent sub-pixels in a column are different.
  • the first subpixel includes: a first color subpixel and a third color subpixel;
  • the second subpixel includes: a second color subpixel and a fourth color subpixel;
  • the first color subpixels are red subpixels
  • the third color subpixels are blue subpixels
  • the second color subpixels and the fourth color subpixels are green subpixels.
  • each of the signal lines further includes a signal line protrusion, and the signal line protrusion and the signal line protrusion have the same structure;
  • the plurality of signal lines include a first a signal line and a second signal line; wherein, one column of sub-pixels corresponds to one of the first signal lines and one of the second signal lines; the signal line protrusions of the first signal lines are respectively electrically connected to odd-numbered rows of sub-pixels, The signal line protrusions of the second signal line are respectively electrically connected to the even-numbered rows of sub-pixels;
  • two of the first signal lines are adjacent to form a first signal line group, or, two of the second signal lines A second signal line group is formed adjacently.
  • At least some of the effective parts of the sub-pixels have overlapping regions with two adjacent signal lines in the first direction.
  • a third overlapping area exists between the effective part and the first signal line, and a fourth overlapping area exists between the effective part and the second signal line ;
  • the third overlapping area and the fourth overlapping area are located on both sides of the effective portion of the anode in the first direction.
  • Embodiments of the present disclosure further provide a display device including the display substrate provided by the embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2a is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 2b is a signal timing diagram provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of the layout structure of some display substrates according to an embodiment of the present disclosure.
  • FIG. 4a is a schematic diagram of a layout structure of an active semiconductor layer provided by an embodiment of the present disclosure.
  • 4b is a schematic diagram of a layout structure of a gate conductive layer provided by an embodiment of the present disclosure
  • FIG. 4c is a schematic diagram of a layout structure of a reference conductive layer provided by an embodiment of the present disclosure.
  • FIG. 4d is a schematic diagram of a layout structure of a source-drain metal layer according to an embodiment of the present disclosure
  • FIG. 4e is a schematic diagram of a layout structure of a first conductive layer provided by an embodiment of the present disclosure.
  • Fig. 4f is a partial enlarged schematic diagram of Fig. 4e;
  • 4g is a schematic diagram of a layout structure of an anode layer provided by an embodiment of the present disclosure.
  • 4h is a schematic diagram of the layout structure of the source-drain metal layer and the first conductive stack layer provided by an embodiment of the present disclosure
  • FIG. 5a is a schematic structural diagram of a first conductive layer and an anode layer laminated according to an embodiment of the present disclosure
  • FIG. 5b is an enlarged schematic view of the sub-pixel of the third color in FIG. 5a;
  • Figure 6a is a schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure shown in Figure 5a;
  • Fig. 6b is a schematic cross-sectional structural diagram taken along the BB' direction in the schematic layout structure shown in Fig. 5a.
  • the display substrate provided by the embodiment of the present disclosure may include: a base substrate 10 .
  • the plurality of repeating units PX on the base substrate 10, at least one repeating unit PX (eg, each repeating unit) of the plurality of repeating units PX may include a plurality of sub-pixels spx.
  • the plurality of sub-pixels may include a first-color sub-pixel spx1, a second-color sub-pixel spx2, a third-color sub-pixel spx3, and a fourth-color sub-pixel spx4.
  • the repeating unit may include the first color subpixel spx1, the second color subpixel spx2, the third color subpixel spx3, and the fourth color subpixel spx4.
  • the display substrate can use the first color sub-pixel spx1, the second color sub-pixel spx2, the third color sub-pixel spx3 and the fourth color sub-pixel spx4 for light mixing, so as to realize color display.
  • the first color, the second color, the third color, and the fourth color may be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue
  • the fourth color is green.
  • the embodiments of the present disclosure include but are not limited to this.
  • the repeating unit includes a first color sub-pixel spx1, a second color sub-pixel spx2, a third color sub-pixel spx3 and a fourth color sub-pixel spx4, and the second and fourth colors are green, and the first color is red,
  • the third color is blue as an example for description.
  • a plurality of repeating units are arranged along the second direction F2 to form a repeating unit group PXZ, and the repeating unit group PXZ is arranged along the first direction F1.
  • the first direction F1 is different from the second direction F2.
  • the first direction F1 is perpendicular to the second direction F2.
  • the first direction F1 is the row direction
  • the second direction F2 is the column direction
  • the first direction F1 is the column direction
  • the second direction F2 is the row direction.
  • At least one sub-pixel spx (eg, each sub-pixel) in the plurality of sub-pixels spx may include: a pixel circuit 0121 and a light-emitting element 0120 .
  • the pixel circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor.
  • the generated electrical signal (eg, current) is input to the light-emitting element 0120 to drive the light-emitting element 0120 to emit light.
  • the anode of the light-emitting element 0120 is connected to the pixel circuit 0121, and the cathode of the light-emitting element 0120 is connected to a power supply terminal.
  • the pixel circuit 0121 may include: a driving control circuit 0122, a first lighting control circuit 0123, a second lighting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128 and a reset circuit 0129.
  • the driving control circuit 0122 may include a control terminal, a first terminal and a second terminal. And the drive control circuit 0122 is configured to provide the light-emitting element 0120 with a drive current for driving the light-emitting element 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the first light-emitting control circuit 0123 is configured to turn on or off the connection between the driving control circuit 0122 and the first voltage terminal VDD.
  • the second light-emitting control circuit 0124 is electrically connected to the second terminal of the driving control circuit 0122 and the anode of the light-emitting element 0120 . And the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting element 0120 to be turned on or off.
  • the data writing circuit 0126 is electrically connected to the first terminal of the driving control circuit 0122 . And the data writing circuit 0126 is configured to write the signal on the data line VD into the memory circuit 0127 .
  • the storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store the data signal and the information of the drive control circuit 0122 .
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the driving control circuit 0122, respectively. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the drive control circuit 0122 .
  • the reset circuit 0129 is also electrically connected to the control terminal of the drive control circuit 0122 and the anode of the light-emitting element 0120, respectively. And the reset circuit 0129 is configured to reset the anode of the light-emitting element 0120 and reset the control terminal of the drive control circuit 0122.
  • the light-emitting element 0120 can be set as an electroluminescent diode, such as at least one of OLED, QLED, micro LED, and micro OLED.
  • the light-emitting element 0120 may include a stacked anode, a light-emitting layer, and a cathode. Further, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the light-emitting element 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited herein.
  • the drive control circuit 0122 includes a drive transistor T1
  • the control end of the drive control circuit 0122 includes the drive gate of the drive transistor T1
  • the first end of the drive control circuit 0122 includes the first end of the drive transistor T1.
  • One pole, the second terminal of the driving control circuit 0122 includes the second pole of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2.
  • the storage circuit 0127 includes a storage capacitor CST.
  • Threshold compensation circuit 0128 includes threshold compensation transistor T3.
  • the first light emission control circuit 0123 includes a first light emission control transistor T4.
  • the second light emission control circuit 0124 includes a second light emission control transistor T5.
  • the reset circuit 0129 includes an initialization transistor T6 and a reset transistor T7.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1
  • the second pole of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal
  • the data writing transistor T1 The gate of T2 is configured to be electrically connected to the scan line GA to receive scan signals.
  • the first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second pole of the storage capacitor CST is electrically connected to the driving gate of the driving transistor T1.
  • the first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the driving transistor T1
  • the second pole of the threshold compensation transistor T3 is electrically connected to the driving gate of the driving transistor T1
  • the gate of the threshold compensation transistor T3 is configured to be connected to the scanning
  • the line GA is electrically connected to receive the scan signal.
  • the first pole of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT to receive the reset signal
  • the second pole of the initialization transistor T6 is electrically connected to the drive gate of the drive transistor T1
  • the gate of the initialization transistor T6 is configured to be connected to the reset signal.
  • Line RST is electrically connected to receive the reset control signal.
  • the first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT to receive a reset signal
  • the second pole of the reset transistor T7 is electrically connected to the anode of the light emitting element 0120
  • the gate of the reset transistor T7 is configured to be connected to the reset line RST Electrically connected to receive a reset control signal.
  • the first electrode of the first light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light-emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light-emitting control transistor T4 is electrically connected. It is configured to be electrically connected to the lighting control line EM to receive the lighting control signal.
  • the first electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the second light-emitting control transistor T5 is electrically connected to the anode of the light-emitting element 0120
  • the gate of the second light-emitting control transistor T5 is It is configured to be electrically connected to the lighting control line EM to receive the lighting control signal.
  • the cathode of the light-emitting element 0120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • the above transistor may be a P-type transistor, an N-type transistor, or a pixel circuit composed of a mixture of P-type transistors and N-type transistors, which is not limited herein.
  • the embodiments of the present disclosure are described by taking that each transistor is a P-type transistor as an example.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage, for example, the first voltage is a positive voltage or a high voltage
  • the second power supply terminal VSS can be a voltage source to output a constant first voltage.
  • a constant second voltage is output, for example, the second voltage is a low voltage or 0 or a negative voltage.
  • the second power supply terminal VSS may be grounded.
  • the signal timing diagram corresponding to the pixel circuit shown in FIG. 2a is shown in FIG. 2b.
  • the working process of the pixel circuit has three stages: T10 stage, T20 stage, and T30 stage.
  • rst represents the signal transmitted on the reset line RST
  • ga represents the signal transmitted on the scan line GA
  • em represents the signal transmitted on the light-emitting control line EM.
  • the signal rst controls the initialization transistor T6 to be turned on, so that the signal transmitted on the initialization line VINIT can be provided to the driving gate of the driving transistor T1 to reset the driving gate of the driving transistor T1.
  • the signal rst controls the reset transistor T7 to be turned on, so as to provide the signal transmitted on the initialization line VINIT to the anode of the light-emitting element 0120 of the previous stage, so as to reset the anode of the light-emitting element 0120 of the previous stage.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned off.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, and the turned on data writing transistor T2 makes the data signal transmitted on the data line VD charge the driving gate of the driving transistor T1, so that the driving gate of the driving transistor T1 is charged.
  • the voltage of the drive gate of the drive transistor T1 becomes: Vdata+Vth.
  • Vth represents the threshold voltage of the driving transistor T1
  • Vdata represents the voltage of the data signal.
  • the signal rst controls both the initialization transistor T6 and the reset transistor T7 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on.
  • the turned-on first light-emitting control transistor T4 supplies the voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T1, so that the voltage of the first electrode of the driving transistor T1 is Vdd.
  • the driving transistor T1 generates a driving current according to the gate voltage Vdata+
  • the driving current is supplied to the light-emitting element 0120 through the turned-on second light-emitting control transistor T5, and the light-emitting element 0120 is driven to emit light.
  • the signal rst controls the initialization transistor T6 and the reset transistor T7 to be turned off.
  • the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the first electrode of the above-mentioned transistor may be its source electrode and the second electrode may be its drain electrode; or the first electrode may be its drain electrode and the second electrode may be its source electrode.
  • the requirements of the application are determined by design.
  • the pixel circuit in the sub-pixel may be a structure including other numbers of transistors in addition to the structure shown in FIG. 2a and FIG. 2b, which is not limited in this embodiment of the present disclosure. The following description takes the structure shown in FIG. 2a as an example.
  • the display substrate includes a base substrate 10, a transistor array layer disposed on the base substrate 10, a first conductive layer located on the side of the transistor array layer away from the base substrate 10, and a first conductive layer located on the side away from the base substrate 10.
  • the transistor array layer can be used to form transistors and capacitors in the pixel circuit, and to form scan lines, reset lines, light emission control lines EM, initialization lines VINIT, and first power supply signal lines VDD of the first power supply terminal VDD.
  • the transistor array layer may include an active semiconductor layer 0310 , a gate conductive layer 0320 , a reference conductive layer 0330 , and a source-drain metal layer 0340 .
  • the active semiconductor layer 0310 of the pixel circuit 0121 is shown.
  • the active semiconductor layer 0310 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 0310 is formed of, for example, a polysilicon material.
  • the active semiconductor layer 0310 can be used to fabricate the above-mentioned driving active layer T1-A of the driving transistor T1, the active layer T2-A of the data writing transistor T2, the active layer T3-A of the threshold compensation transistor T3, the first light emitting layer
  • the active layer T4-A of the control transistor T4 the active layer T5-A of the second light emission control transistor T5, the active layer T6-A of the first reset transistor T6, and the active layer T7-A of the second reset transistor T7 .
  • Each active layer may include a source region, a drain region, and a channel region between the source and drain regions.
  • the active layers of the respective transistors are integrally provided.
  • the active semiconductor layer 0310 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like.
  • the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the channel region may be an undoped region, or a region with a different doping type from the source region and the drain region.
  • the channel region may be the portion overlapping the gate electrode in the direction perpendicular to the substrate, and in the active layer, the source region and the drain region of the same transistor may be the portions on both sides of the channel region, respectively, And substantially no overlap with the corresponding gate electrode (without considering the effect of ion diffusion).
  • a gate insulating layer is formed on the above-mentioned active semiconductor layer 0310 for protecting the above-mentioned active semiconductor layer 0310 .
  • the gate conductive layer 0320 of the pixel circuit 0121 is shown, and the gate conductive layer 0320 is provided on the gate insulating layer so as to be insulated from the active semiconductor layer 0310 .
  • the gate conductive layer 0320 may include a second electrode cc2 of the storage capacitor CST, a scan line GA, a reset line RST, a light emission control line EM, a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, and a first light emission control transistor T4 , the gates of the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7.
  • the gate of the data writing transistor T2 may be the portion where the scan line GA and the active semiconductor layer 0310 overlap
  • the gate of the first light-emitting control transistor T4 may be the light-emitting control line EM and the active semiconductor layer 0310.
  • the gate of the second light-emitting control transistor T5 can be the second part where the light-emitting control line EM overlaps with the active semiconductor layer 0310
  • the gate of the first reset transistor T6 is the reset line RST and the active semiconductor layer 0310.
  • the first part where the source semiconductor layer 0310 overlaps, the gate of the second reset transistor T7 is the second part where the reset line RST overlaps with the active semiconductor layer 0310, the threshold compensation transistor T3 can be a double gate structure thin film transistor, and the threshold compensation transistor
  • the first gate of T3 may be a portion where the scan line GA overlaps with the active semiconductor layer 0310, and the second gate of the threshold compensation transistor T3 may be a protrusion protruding from the scan line GA to intersect with the active semiconductor layer 0310 overlapping part.
  • the driving gate of the driving transistor T1 may be the second electrode cc2 of the storage capacitor CST.
  • each dotted line in FIG. 4a shows each part where the gate conductive layer 0320 and the active semiconductor layer 0310 overlap.
  • the scan line GA, the reset line RST and the light emission control line EM are arranged along the second direction F2. And the scan line GA, the reset line RST and the light emission control line EM extend substantially along the first direction F1.
  • the scan line GA is located between the reset line RST of the row and the emission control line EM of the row.
  • FIG. 3 only takes the second direction F2 as the column direction and the first direction F1 as the row direction as an example for description.
  • the second pole cc2 of the storage capacitor CST is located between the scan line GA and the light emission control line EM.
  • the protrusion protruding from the scanning line GA is located on the side of the scanning line GA away from the light emission control line EM.
  • an interlayer dielectric layer is formed on the above-mentioned gate conductive layer 0320 to protect the above-mentioned gate conductive layer 0320 .
  • the reference conductive layer 0330 of the pixel circuit 120a is shown, and the reference conductive layer 0330 includes the first pole cc1 of the storage capacitor CST, the initialization line VINIT, and the light shielding layer ZG.
  • the first pole cc1 of the storage capacitor CST and the second pole cc2 of the storage capacitor CST at least partially overlap to form the storage capacitor CST.
  • the first pole cc1 of the storage capacitor CST has a hollow area, and the hollow area may expose a portion of the second pole cc2 of the storage capacitor CST.
  • the orthographic projection of the light shielding layer ZG on the base substrate 10 and the source region of the second reset transistor T7 in the active semiconductor layer 0310 (such as the source of the second reset transistor T7 )
  • the electrode region and the source region of the first reset transistor T6 have an integral structure) overlapping on the orthographic projection of the base substrate 10 .
  • the threshold compensation transistor T3 is a dual gate transistor.
  • the light shielding layer ZG shields the active layer part between the two gates of the threshold compensation transistor T3, because the threshold compensation transistor T3 is directly connected to the driving transistor T1, which can stabilize the working state of the driving transistor T1.
  • the projection of the light shielding layer ZG on the base substrate is located between the data line directly electrically connected to the pixel circuit and the first power supply signal line VDD in the pixel circuit area where it is located, and plays the role of shielding signal interference.
  • the orthographic projection of the light shielding layer ZG on the base substrate 10 intersects with the orthographic projection of the drain region of the first reset transistor T6 in the active semiconductor layer 0310 on the base substrate 10 . stack. In this way, the influence of light on the first reset transistor T6 can be reduced, and the reset accuracy can be improved.
  • the conductive region between the orthographic projection of the light shielding layer ZG on the base substrate 10 and the active layer T3-A of the threshold compensation transistor T3 in the active semiconductor layer 0310 is on the lining.
  • the orthographic projections of the base substrate 10 overlap. In this way, the influence of light on the threshold compensation transistor T3 can be reduced, and the accuracy of the threshold compensation can be improved.
  • a first interlayer insulating layer is formed on the above-mentioned reference conductive layer 0330 for protecting the above-mentioned reference conductive layer 0330 .
  • the source-drain metal layer 0340 of the pixel circuit 0121 is shown, and the source-drain metal layer 0340 may include a first power supply signal line VDD, connection parts LB1 , LB2 , LB3 , and LB4 .
  • the first color sub-pixel spx1 , the second color sub-pixel spx2 , the third color sub-pixel spx3 and the fourth color sub-pixel spx4 respectively include connection parts LB1 , LB2 , LB3 , and LB4 .
  • a second interlayer insulating layer is formed on the above-mentioned source-drain metal layer 0340 to protect the above-mentioned source-drain metal layer 0340 .
  • FIG. 3 the first conductive layer 0350 of the pixel circuit 0121 is shown, wherein FIG. 4f is an enlarged schematic diagram of FIG.
  • the first conductive layer 0350 includes : The signal lines Vd arranged in sequence along the first direction F1 and extending in the second direction F2, the signal line protrusions TQ (TQ1/TQ2/TQ3/TQ4) located on the same side of the signal line Vd and spaced apart from each other and the anode turn
  • the connection part YZ (YZ1/YZ2/YZ3/YZ4), the signal line protruding part TQ is integrally connected with the signal line Vd.
  • the signal line Vd may be configured as a data line Vd for transmitting data signals.
  • the first color sub-pixel spx1 may include a signal line protrusion TQ1 and an anode transfer portion YZ1
  • the second color sub-pixel spx2 may include a signal line protrusion TQ2 and an anode transfer portion YZ2
  • the third color sub-pixel spx2 may include a signal line protrusion TQ2 and an anode transfer portion YZ2.
  • the pixel spx3 may include a signal line protrusion TQ3 and an anode transfer portion YZ3
  • the fourth color sub-pixel spx4 may include a signal line protrusion TQ4 and an anode transfer portion YZ4, and the anode transfer portion YZ is connected to the anode through an insulating layer via hole. connect.
  • the patterns of the signal line protrusions overlapping two adjacent sub-pixels in a column are different. Specifically, for example, as shown in FIG.
  • the first signal line protrusion TQ1 located in the first row from the left , and the first signal line protrusion TQ5 located in the second row from the left belongs to the two signal line protrusions of two adjacent sub-pixels in a column, and the first signal line protrusion located in the first row from the left
  • the part TQ1 includes a protruding connection part TQL1 extending to the right
  • the first signal line protruding part TQ5 located in the second row from the left includes a protruding connection part TQL5 extending to the left, which is located in the first signal line
  • the pattern of the first signal line protrusion TQ1 in the row from the left is different from the pattern of the first signal line protrusion TQ5 in the second row from the left.
  • each signal line Vd further includes a signal line protrusion, and the signal line protrusion TQ may have the same structure as the signal line protrusion; the plurality of signal lines Vd include a first signal line.
  • one column of sub-pixels corresponds to one first signal line Vd1 and one second signal line Vd2;
  • the signal line protrusions of the first signal line Vd1 are respectively electrically connected to odd-numbered rows of sub-pixels, and the second signal line
  • the signal line protrusions of the line Vd2 are respectively electrically connected to the sub-pixels in the even rows; among the two first signal lines Vd1 and the two second signal lines Vd2 corresponding to the two adjacent columns of sub-pixels, two of the first signal lines Vd1 are in phase with each other.
  • Adjacent it can be understood that there is no other corresponding signal line between the two first signal lines Vd1, for example, there is no other data line between the two adjacent data lines
  • the two second signal lines Vd2 are adjacent (it can be understood that there are no other corresponding signal lines between the two second signal lines Vd2, for example, there are no other data lines between the two adjacent data lines) to form a second signal line.
  • Signal line set Specifically, the plurality of signal lines Vd are divided into a plurality of signal line groups Vdx (Vdx1/Vdx2/Vdx3/Vdx4), and the plurality of signal line groups Vdx are arranged periodically.
  • Each signal line group Vdx includes a first signal line Vd1 and a second signal line Vd2 located on both sides of the same column of sub-pixels.
  • the first signal line Vd1 is located on the first side of a column of sub-pixels
  • the second signal line Vd2 is located on the second side of the column of sub-pixels.
  • the first side may be the left side and the second side may be the right side; for another example, the first column may be the right side and the second side may be the left side.
  • the pitch of the gaps between adjacent signal line groups may be ax. In the same signal line group, the interval of the gap between the first signal line Vd1 and the second signal line Vd2 may be ay.
  • ax can be less than ay.
  • ax can be 3-7 microns.
  • ay can be 12-20 microns.
  • one column of sub-pixels corresponds to one first signal line Vd1 and one second signal line Vd2 of one signal line group Vdx, for example, the left and right sides of the pixel circuit of one column of sub-pixels are respectively connected with one first signal line Vd1 and one second signal line Vd1 Line Vd2 is adjacent.
  • the first signal line Vd1 drives the sub-pixels in the odd-numbered rows
  • the second signal line Vd2 drives the sub-pixels in the even-numbered rows.
  • the signal line protrusion TQ can be a signal line protrusion that is integrally and electrically connected to the data line Vd, which is beneficial to simplify the manufacturing process of the display substrate and simplify the wiring complexity of the display substrate.
  • the signal line protrusions can also be other structures independent of the signal line protrusions.
  • the data lines Vd extend along the second direction F2 and are sequentially arranged along the first direction F1.
  • the signal line protrusions of the first signal line Vd1 are respectively electrically connected to the sub-pixels in odd-numbered rows, and the signal-line protrusions of the second signal line Vd2 are respectively electrically connected to the sub-pixels in even-numbered rows.
  • a first insulating layer is formed on the above-mentioned first conductive layer 0350 for protecting the above-mentioned first conductive layer 0350 .
  • the anode layer 0360 on the side of the first conductive layer 0350 away from the base substrate 10 is shown, and the anode layer 0360 includes the anode Y (Y1/Y2/Y3/Y4).
  • the first color subpixel spx1 may include anode Y1
  • the second color subpixel spx2 may include anode Y2
  • the third color subpixel spx3 may include anode Y3
  • the fourth color subpixel spx4 may include anode Y4.
  • the first power signal line VDD passes through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer to correspond to the first light emitting diode in the active semiconductor layer 0310
  • the source region of the control transistor T4 is electrically connected.
  • the first power signal line VDD is electrically connected to the first electrode cc1 of the storage capacitor CST in the reference conductive layer 0330 through at least one via hole penetrating through the first interlayer insulating layer.
  • the first power signal line VDD is also electrically connected to the light shielding layer ZG through at least one via hole penetrating through the first interlayer insulating layer.
  • connection part LB1 is connected to the corresponding threshold compensation transistor T3 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the drain region is electrically connected.
  • the other end of the connection part LB1 is electrically connected to the initialization line VINIT through at least one via hole penetrating through the first interlayer insulating layer.
  • connection part LB2 passes through the third via hole K3 (K31/K32/K33/K34) in the second interlayer insulating layer and the signal line protrusion TQ (TQ1/TQ2/ TQ3/TQ4) are electrically connected, and the other end of the connection part LB2 is connected to the data writing transistor T2 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the source regions are electrically connected.
  • connection part LB3 is electrically connected to the second pole cc2 of the storage capacitor CST through at least one via hole penetrating through the interlayer dielectric layer and the first interlayer insulating layer.
  • the other end of the connection part LB3 is electrically connected to the drain region of the first reset transistor T6 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • connection portion LB4 is connected to the second light-emitting control transistor T5 in the active semiconductor layer 0310 through at least one via hole penetrating through the gate insulating layer, the interlayer dielectric layer and the first interlayer insulating layer.
  • the drain region is electrically connected.
  • the first insulating layer includes a first via hole K1 (K11/K12/K13/K14), and the first via hole K1 exposes a part of the anode transfer part YZ
  • the anode Y includes a main part and an auxiliary part that are electrically connected to each other
  • the main part may include an effective part exposed by the sub-pixel openings of the subsequently formed pixel-defining layer, and an anode extension part extended from the effective part
  • the auxiliary part is formed by the anode
  • the expansion part extends to the anode adapter part along the second direction;
  • the outer contour shape of the anode expansion part is similar to the outer contour shape of the effective part; wherein, the auxiliary part is electrically connected to the anode adapter part YZ through the first via K1 .
  • the anode Y1 includes a main part Y11 and an auxiliary part Y12 that are electrically connected to each other, the main part Y11 includes an effective part Y13 and an anode extension part Y14, and the auxiliary part Y12 is connected to the anode through the first via K11.
  • the connecting portion YZ1 is electrically connected, and the anode connecting portion YZ1 is electrically connected to the corresponding connecting portion LB4 through the second via hole K21 penetrating the second interlayer insulating layer.
  • the anode Y2 includes a main part Y21 and an auxiliary part Y22 that are electrically connected to each other, the main part Y21 includes an effective part Y23 and an anode extension part Y24, and the auxiliary part Y22 passes through the first via K12 and the anode transfer part
  • the YZ2 is electrically connected, and the anode transfer portion YZ2 is electrically connected to the corresponding connection portion LB4 through the second via hole K22 penetrating the second interlayer insulating layer.
  • the anode Y3 includes a main part Y31 and an auxiliary part Y32 that are electrically connected to each other, the main part Y31 includes an effective part Y33 and an anode extension part Y34, and the auxiliary part Y32 passes through the first via K13 and the anode transfer part
  • the YZ3 is electrically connected, and the anode transfer portion YZ3 is electrically connected to the corresponding connection portion LB4 through the second via hole K23 penetrating the second interlayer insulating layer.
  • the anode Y4 includes a main part Y41 and an auxiliary part Y42 that are electrically connected to each other, the main part Y41 includes an effective part Y43 and an anode extension part Y44, and the auxiliary part Y42 passes through the first via K14 and the anode transfer part
  • the YZ4 is electrically connected, and the anode transfer portion YZ4 is electrically connected to the corresponding connecting portion LB4 through the second via hole K24 penetrating the second interlayer insulating layer.
  • the center Q1 of the effective part Y13 of the first color sub-pixel spx1, the center O2 of the effective part Y23 of the second color sub-pixel spx2, and the third color sub-pixel spx3 The center O3 of the effective portion Y33 of the , and the center O4 of the effective portion Y43 of the fourth color sub-pixel spx4 substantially enclose a quadrilateral, such as a parallelogram.
  • the center O1 of the effective part Y13 of the first color sub-pixel spx1 and the center O3 of the effective part Y33 of the third color sub-pixel spx3 are located at two adjacent vertices of the quadrilateral, and the connecting line is perpendicular to the second direction F2.
  • the center O2 of the effective part Y23 of the second color sub-pixel spx2 and the center O4 of the effective part Y43 of the fourth color sub-pixel spx4 are located at the other two adjacent vertices of the quadrilateral, and the connecting line is perpendicular to the second direction F2.
  • the vertical line connecting the center O1 of the effective part Y13 of the first color sub-pixel spx1 and the center O3 of the effective part Y33 of the third color sub-pixel spx3 may pass through the effective part Y23 of a second color sub-pixel spx2, For example, it can pass through the center O2 of the effective portion Y23 of a second color sub-pixel spx2.
  • a vertical line connecting the center O2 of the effective part Y23 of the second color sub-pixel spx2 and the center O4 of the effective part Y43 of the fourth color sub-pixel spx4 passes through the effective part Y33 of the third color sub-pixel spx3, for example, it can be Passing through the center O3 of the effective portion Y33 of the third color sub-pixel spx3.
  • the anode extension part in the first sub-pixel, further includes an anode shielding part on the side facing the second sub-pixel, and the anode shielding part is on the positive side of the base substrate.
  • the projection covers the first area, wherein the first area includes at least a part of the area between the two channel regions of the threshold compensation transistor in the pixel circuit corresponding to the second sub-pixel.
  • the first region includes more than half of the area between the two channel regions of the threshold compensation transistor in the pixel circuit corresponding to the second sub-pixel.
  • the anode extending portion Y14 further includes an anode shielding portion YA1 on the side facing the second color sub-pixel spx3, and the anode shielding portion YA1 covers the same sub-pixel in the orthographic projection of the base substrate 10
  • the anode extending portion Y34 further includes an anode shielding portion YA3 on the side facing the fourth color sub-pixel spx4, and the anode shielding portion YA3 covers the same sub-pixel in the orthographic projection of the base substrate 10.
  • the threshold value of the compensation transistor T3 is the region between the two channel regions T3-A.
  • the main body part and the auxiliary part that are electrically connected to each other included in the anode have an integrated structure, that is, the main body part and the auxiliary part are formed continuously.
  • a pixel defining layer is formed on the side of the anode layer away from the base substrate 10 , and the pixel defining layer includes a plurality of sub-pixel openings corresponding to the sub-pixels one-to-one.
  • the effective parts of the sub-pixels in the second direction F2 have an overlapping area with the signal line protrusions TQ and the anode transfer parts YZ connected to the corresponding pixel circuits, that is, a line parallel to the second direction F2
  • the straight line can pass through the signal line protrusion TQ and the anode transfer portion YZ at the same time.
  • a straight line parallel to the second direction F2 can pass through the signal line protrusion TQ and the anode transfer portion YZ of all sub-pixels in the same column.
  • the signal line protruding parts TQ and the anode transition parts YZ passing through them are alternately distributed in the second direction F2.
  • the effective part Y13 of the first color sub-pixel spx1 and the signal line protrusion TQ1 connected to the corresponding pixel circuit have a first overlap area S1
  • the anode transfer part YZ1 connected to the corresponding pixel circuit has a second overlap area S1'.
  • the effective part Y33 of the third color sub-pixel spx3 and the signal line protrusion TQ3 connected to the corresponding pixel circuit have a first overlap area S3
  • the anode transfer part YZ3 connected to the corresponding pixel circuit has a second overlap Area S3'.
  • At least some of the effective parts of the sub-pixels have overlapping areas in the second direction with the signal line protrusions TQ and the anode transition parts YZ connected to the corresponding pixel circuits, which can improve the effectiveness of the anode Y if
  • the effective portion will be relatively high at the end corresponding to the anode adapter portion YZ, which will cause the problem of color shift.
  • the effective portion of the anode exposed by the opening of the sub-pixel can be in contact with the light-emitting layer formed subsequently, thereby defining the light-emitting area of the sub-pixel.
  • the area of the pixel-defining layer other than the sub-pixel opening can be a covering part covering the anode and other areas other than the area where the anode is located. out.
  • a plurality of sub-pixels are divided into a first sub-pixel 01 and a second sub-pixel 02, and the area of the anode of the first sub-pixel 01 is larger than that of the second sub-pixel 02;
  • the effective part of the sub-pixel 01 has an overlapping area with the signal line protruding part TQ and the anode transfer part YZ connected to the corresponding pixel circuit.
  • the orthographic projection of the anode transition portion YZ of the second sub-pixel 02 on the base substrate 10 passes through the orthographic projection of the effective portion on the base substrate 10 , for example, through the center of the orthographic projection of the effective portion on the base substrate 10 .
  • the first subpixel 01 may include a first color subpixel spx1 and a third color subpixel spx3, the second subpixel 02 may include a second color subpixel and a fourth color subpixel spx4, and the first color subpixel
  • the pixel spx1 may specifically be a red sub-pixel
  • the third color sub-pixel spx1 may specifically be a blue sub-pixel
  • the second color sub-pixel spx2 and the fourth color sub-pixel spx4 may specifically be a green sub-pixel.
  • the effective portion Y13 of the first color sub-pixel spx1 has an overlapping area with the signal line protruding portion TQ1 and the anode transfer portion YZ1 connected to the corresponding pixel circuit in the second direction F2.
  • the effective part Y33 of the third color sub-pixel spx3 has an overlapping area with the signal line protrusion TQ3 and the anode transfer part YZ3 connected to the corresponding pixel circuit.
  • the orthographic projection of the anode transfer portion YZ2 of the second color sub-pixel spx2 on the base substrate 10 covers the orthographic projection of the effective portion Y23 on the base substrate 10 , for example, covers the center of the orthographic projection of the effective portion Y23 on the base substrate 10 O2.
  • the orthographic projection of the anode transfer portion YZ4 of the fourth color sub-pixel spx4 on the base substrate 10 covers the orthographic projection of the effective portion Y43 on the base substrate 10 , for example, covering the center of the orthographic projection of the effective portion Y43 on the base substrate 10 O4.
  • the overlapping area of the anode transfer portion YZ of the first sub-pixel 01 and the effective portion is small, the overlapping area of the anode transfer portion YZ of the second sub-pixel 02 and the effective portion is generally larger (the first The area occupied by the hole where the anode transfer portion YZ of the two sub-pixels 02 is connected to the source-drain metal layer 0340 is closer to the center of the effective portion), and further, the color improvement of the first sub-pixel 01 and the second sub-pixel 02 is carried out.
  • the orthographic projection of the base substrate 10 covers the orthographic projection of the effective portion on the base substrate 10 , for example, covers the center of the orthographic projection of the effective portion YZ on the base substrate 10 to improve the color shift of the first sub-pixel 01 and the second sub-pixel 02 question.
  • the anode transfer portion YZ of the second sub-pixel 02 covers the center of the orthographic projection of the base substrate 10 on the orthographic projection of the base substrate 10, and covers the effective portion of the base substrate 10.
  • the portion is more than 60% of the orthographic projection of the base substrate 10, eg, covers more than 70%, eg, covers more than 80%.
  • FIG. 5a and FIG. 6b covers the center of the orthographic projection of the base substrate 10 on the orthographic projection of the base substrate 10, and covers the effective portion of the base substrate 10.
  • the portion is more than 60% of the orthographic projection of the base substrate 10, eg, covers more than 70%, eg, covers more than 80%.
  • the orthographic projection of the anode transfer portion YZ2 of the second color sub-pixel spx2 on the base substrate 10 covers the center O2 of the orthographic projection of the effective portion Y23 on the base substrate 10, and covers the effective portion Y23 Over 60% of the orthographic projection of the base substrate 10 , eg, over 70%, eg over 80%.
  • the orthographic projection of the anode transfer portion YZ of the second sub-pixel 02 on the base substrate 10 passes through most of the area of the orthographic projection of the effective portion on the base substrate 10, eg, more than 60%, eg, covers more than 70%, eg Over 80% coverage.
  • the orthographic projection of the anode transition portion of the second sub-pixel on the base substrate may pass through the entire orthographic projection of the effective portion on the base substrate.
  • the anode transfer portion YZ extends along the second direction F2
  • the anode transfer portion YZ of the second sub-pixel 02 covers the center of the orthographic projection of the base substrate 10 of the effective portion on the base substrate 10 .
  • the orthographic projection of the anode transfer portion YZ of the second sub-pixel 02 on the base substrate 10 passes through the center of the orthographic projection of the effective portion on the base substrate 10 in the second direction F2.
  • FIG. 5a the first overlapping area S1 and the second overlapping area S2 are similar in shape and have the same area.
  • FIG. 5b is an enlarged schematic diagram of a first sub-pixel 01 (third color sub-pixel spx3) in FIG. 5a, and the maximum length of the first overlapping area in the second direction accounts for One tenth to one third of the maximum length of the effective portion in the second direction.
  • the maximum length of the second overlapping region in the second direction accounts for one tenth to one third of the maximum length of the effective portion in the second direction.
  • the maximum length k1 of the first overlapping area S1 in the second direction F2 accounts for one tenth to one third of the maximum length k of the effective portion Y33 in the second direction F2;
  • the maximum length k2 of the second overlapping region S2 in the second direction F2 accounts for one tenth to one third of the maximum length k of the effective portion Y33 in the second direction F2.
  • the first overlapping area and the second overlapping area are symmetrical about a line passing through the center of the effective portion and perpendicular to the second direction.
  • the first overlapping area S1 and the second overlapping area S2 are symmetrical with respect to the line X passing through the center O3 of the effective portion Y33 and perpendicular to the second direction F2.
  • the first overlapping region and the second overlapping region are symmetrical with respect to a line perpendicular to the center of the effective portion and perpendicular to the second direction, which can effectively improve the color shift problem of the first sub-pixel.
  • it can be understood that, in the specific implementation, it is difficult to realize the complete and precise symmetry of the first overlapping area and the second overlapping area with respect to the center of the effective portion and the line perpendicular to the second direction.
  • the first overlapping area and the second overlapping area in the embodiment of the present disclosure are symmetrical with respect to the center of the over-effective portion and a line perpendicular to the second direction, which can be understood as the first overlapping area and the second overlapping area are related to A line passing through the center of the effective portion and perpendicular to the second direction is substantially symmetrical.
  • the length h2 of the anode transfer portion YZ of the second sub-pixel 02 in the second direction F2 is greater than the length h2 of the anode transfer portion YZ of the first sub-pixel 01 in the second direction F2
  • the length h1 is greater than the length h1 of the anode transfer portion YZ1 of the first color sub-pixel spx1 in the second direction F2.
  • the length of the anode transfer portion YZ of the second sub-pixel 02 in the second direction F2 is set to be relatively long, so that the anode transfer portion YZ of the second sub-pixel 02 itself can connect the lower portion of the anode to the effective portion of the anode. to compensate for the flatness.
  • the signal line protruding parts TQ include: protruding main parts TQZ (TQZ1/TQZ2/TQZ3/TQZ4), and connecting protruding main parts TQZ and the protruding connection portion TQL (TQL1/TQL2/TQL3/TQL4) of the signal line Vd.
  • the length h3 of the protruding main portion TQZ in the second direction F2 is greater than the length h4 of the protruding connecting portion TQL in the second direction F2.
  • the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) in the second direction F2
  • the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) can be further realized. There is more overlap with the effective part of the anode, thereby improving the color shift problem.
  • the length h5 of the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) in the first direction F1 is the same as that of the anode transition portion YZ (YZ1/YZ2/YZ3/YZ4) in the first direction F1.
  • the length h6 in the first direction F1 is substantially the same.
  • the ratio of the length h5 of the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) in the first direction F1 to the length h6 of the anode transition portion YZ (YZ1/YZ2/YZ3/YZ4) in the first direction F1 Roughly 0.8-1.2.
  • the length of the main protruding part TQZ (TQZ1/TQZ2/TQZ3/TQZ4) and the anode adapter part YZ (YZ1/YZ2/YZ3/YZ4) in the first direction F1 are the same, which is beneficial to the anode
  • the effective part of overlaps with the main protruding part TQZ (TQZ1/TQZ2/TQZ3/TQZ4) and the anode transfer part YZ (YZ1/YZ2/YZ3/YZ4), the resulting overlapping area is approximately the same.
  • the overlapping area ratio of the effective portion of the anode, the main protruding portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) and the anode transition portion YZ (YZ1/YZ2/YZ3/YZ4) is approximately 0.8-1.2.
  • the length h3 of the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) in the second direction F2 is smaller than that of the anode transition portion YZ (YZ1/YZ2/YZ3) /YZ4) length h1 in the second direction F2.
  • the length h3 of the protruding main portion TQZ1 in the second direction F2 is smaller than the length h1 of the anode transition portion YZ1 in the second direction F2.
  • the length h3 of the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) in the second direction F2 is smaller than the length h3 of the anode adapter portion YZ (YZ1/YZ2/YZ3/YZ4) in the second direction F2
  • the length h1 is beneficial to realize conduction with other film layers through the via hole through the anode adapter YZ (YZ1/YZ2/YZ3/YZ4).
  • the length h3 of the protruding main portion TQZ ( TQZ1 / TQZ2 / TQZ3 / TQZ4 ) in the second direction F2 is less than 15 ⁇ m.
  • h3 is less than 12 microns.
  • h3 is larger than 6 microns.
  • h4 is less than 5 microns.
  • h4 is less than 4 microns.
  • h5 is greater than half of the distance between the two signal lines on both sides of the adjacent protruding main parts.
  • h5 is 8 micrometers - 20 micrometers.
  • h5 is 10 micrometers - 15 micrometers.
  • the main protruding part is used for the electrical connection between the signal line and other film layers, it is generally connected by via holes, that is, the main protruding part is provided with a via hole for connecting the signal line integrally connected with other film layers, so its corresponding Dimensions h3 and h5 cannot be too small, at least larger than the vias.
  • the size of a via hole is, for example, 4*4 microns.
  • a via is 3*3 microns in size.
  • the size of a via hole is, for example, a circular hole with a diameter of 2-4 microns.
  • the data signal used for each sub-pixel display in order to reduce interference with other signals, h3 and h5 should not be too large.
  • the interval in the first direction, there is an interval between the protruding main portion and another adjacent signal line, such as a data line, for example, the interval is approximately equal to h4, or the ratio is approximately 0.8-1.2.
  • the anode transfer part YZ also has an interval between the two adjacent signal lines on both sides in the first direction, and the interval on the left and right sides is approximately equal.
  • the interval between the anode transfer part YZ and its left adjacent signal line is less than 5 microns.
  • the interval between the anode transfer part YZ and the signal line adjacent to the left side thereof is less than 4 microns.
  • the interval between the anode transfer part YZ and the signal line adjacent to the right side thereof is less than 5 microns.
  • the interval between the anode transfer part YZ and the signal line adjacent to the right side thereof is less than 4 micrometers.
  • the shape of the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) is similar to the shape of the anode adapter YZ (YZ1/YZ2/YZ3/YZ4) as shown in conjunction with FIG. 4f. Specifically, the shape of the protruding main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) and the shape of the anode adapter portion YZ (YZ1/YZ2/YZ3/YZ4) are both rectangular.
  • the shape of the main protruding part TQZ (TQZ1/TQZ2/TQZ3/TQZ4) is similar to the shape of the anode adapter part YZ (YZ1/YZ2/YZ3/YZ4), which is beneficial to the effective part of the anode and the protruding part.
  • the main portion TQZ (TQZ1/TQZ2/TQZ3/TQZ4) and the anode transition portion YZ (YZ1/YZ2/YZ3/YZ4) overlap, the resulting overlap area is the same.
  • the effective part of the first sub-pixel is a rhombus, for example, a square.
  • the effective portion Y13 of the first color sub-pixel spx1 is a rhombus, such as a square.
  • the effective part Y33 of the third color sub-pixel spx3 is a rhombus, such as a square.
  • One of the diagonals of the rhombus is parallel to the second direction F2.
  • the vertical diagonal of the first color sub-pixel spx1 is parallel to the second direction F2.
  • the overlapping area of the effective part of the first sub-pixel and the main protruding part is roughly a triangular area, corresponding to one corner of the rhombus.
  • the overlapping area of the effective part of the first sub-pixel and the anode transfer part is approximately a triangular area, corresponding to one corner of the rhombus.
  • the overlapping areas of the effective part of the first sub-pixel and the protruding main part, and the overlapping areas of the effective part of the first sub-pixel and the anode transfer part respectively correspond to two opposite corners of the rhombus. For example, as shown in FIG.
  • the overlapping area of the effective part Y13 of the first color sub-pixel spx1 and the main protruding part TQZ1 is roughly a triangular area.
  • the overlapping area of the effective part Y13 of the first color sub-pixel spx1 and the anode transfer part YZ1 is approximately a triangular area.
  • the shape of the effective part of the second sub-pixel 02 is a quadrilateral, for example, a rounded quadrilateral. As shown in FIG.
  • the effective part Y23 is connected to the anode
  • the size of the overlapping part of the part YZ accounts for 50% to 100% of the size of the effective part Y23, that is, the anode transfer part YZ passes through most of the area of the effective part Y23.
  • the effective part Y23 overlaps the anode transfer part YZ.
  • Part of the size accounts for 60% to 90% of the size of the effective part Y23
  • the part of the effective part Y23 that overlaps with the anode transfer part YZ accounts for 70% to 80% of the size of the effective part Y23.
  • the effective part Y23 overlaps with the anode transfer part YZ.
  • the part size accounts for 80% of the size of the effective part Y23.
  • the orthographic projection of the anode transition portion on the base substrate passes through the orthographic projection of the two diagonal regions of the effective portion of the second sub-pixel on the base substrate.
  • the shape of the effective portion Y23 of the second color sub-pixel spx2 is a quadrilateral, for example, a rounded quadrilateral.
  • the orthographic projection of the anode transfer portion Y22 on the base substrate 10 passes through the orthographic projection of the upper and lower diagonal regions of the effective portion Y23 of the second color sub-pixel spx2 on the base substrate 10 .
  • the effective quadrilateral portion of the second sub-pixel 02 may also be a non-right-angled transition at the corner position, for example, may be an arc-shaped transition.
  • the side of the protruding main portion TQZ far away from the anode transfer portion YZ and the side of the protruding connection portion TQL far away from the anode transfer portion YZ The sides are on the same straight line, that is, in the first sub-pixel 01, the side of the signal line protrusion TQZ that is far from the anode transfer portion YZ is flush, and in the second sub-pixel, the signal line protrusion TQZ is far away from the anode transfer portion.
  • One side of the part YZ is flush.
  • the orthographic projection of the first via hole K1 (K11/K12/K13/K14) on the base substrate 10 is the same as that of the anode transfer part YZ (YZ1/YZ2/YZ3/YZ4).
  • the orthographic projection of the base substrate 10 of the region overlapping with the effective portion does not overlap with each other.
  • the orthographic projection of the first via hole K11 (the first via hole K11 conducts the auxiliary portion Y12 of the anode Y1 and the anode transfer portion YZ1) on the base substrate 10 is connected to the anode
  • the region of the portion YZ1 overlapping the effective portion Y13 ie, the first overlapping region S1 ) does not overlap with each other in the orthographic projection of the base substrate 10 .
  • the orthographic projection of the first via hole K1 (K11/K12/K13/K14) on the base substrate 10 overlaps with the effective portion of the anode transfer portion YZ (YZ1/YZ2/YZ3/YZ4)
  • the orthographic projections of the base substrate 10 do not overlap each other, so that when the anode transfer part YZ (YZ1/YZ2/YZ3/YZ4) overlaps the effective part in the area where the first via hole K1 is located, the The overlapping area creates unevenness, which makes it impossible to compensate for the flatness.
  • the effective part of the anode has an overlapping area with two adjacent signal lines Vd in the first direction F1 .
  • the effective portion Y13 of the anode Y1 has an overlapping area with the two adjacent signal lines Vd in the first direction F1.
  • the effective part of the anode in at least some sub-pixels, has an overlapping area with two adjacent signal lines in the first direction, or the effective part of the anode has two adjacent signal lines in the first direction.
  • the signal lines do not have overlapping areas, which can avoid the problem of color shift when the effective part of the anode only overlaps with the signal line on one side in the first direction.
  • the effective portion of the anode has overlapping regions with two adjacent signal lines Vd in the first direction F1.
  • the overlapping area of the effective part of the anode with the first signal line in the first direction is taken as the third overlapping area
  • the overlapping area of the effective part of the anode with the second signal line in the first direction is taken as the third overlapping area
  • Four overlapping regions, the third overlapping region and the fourth overlapping region are located on both sides of the effective portion of the anode in the first direction.
  • the ratio of the distances between the third overlapping area and the fourth overlapping area to a straight line passing through the center of the effective portion and perpendicular to the first direction is 0.8-1.2, and the further distance from the third overlapping area and the fourth overlapping area to The distances of straight lines passing through the center of the effective portion and perpendicular to the first direction may be equal.
  • the third overlapping area and the fourth overlapping area are substantially symmetrical with respect to a line passing through the center of the effective portion and perpendicular to the first direction. For example, as shown in FIG.
  • the overlapping area of the effective part Y33 of the anode Y3 and the first signal line Vd1 in the first direction F1 is taken as the third overlapping area S3"
  • the The overlapping area of the effective portion Y33 of the anode Y3 and the second signal line Vd2 in the first direction F1 is used as the fourth overlapping area S3"'
  • the third overlapping area S3" and the fourth overlapping area S3"' are located at The effective portion Y33 of the anode Y3 is on both sides in the first direction F1.
  • the ratio of the distance between the third overlapping area S3 ′′ and the fourth overlapping area S3 ′′' to the straight line Y passing through the center O3 of the effective portion Y33 and perpendicular to the first direction F1 is 0.8-1.2.
  • the distances from the overlapping region S3 ′′ and the fourth overlapping region S3 ′′′ to the straight line Y passing through the center O3 of the effective portion Y33 and perpendicular to the first direction F1 may be equal.
  • the third overlapping region S3 ′′ and the fourth overlapping region S3 ′′′ are substantially symmetrical with respect to a line Y passing through the center O3 of the effective portion Y33 and perpendicular to the first direction F1 .
  • Embodiments of the present disclosure further provide a display device, which includes the display substrate provided by the embodiments of the present disclosure.

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Abstract

本公开实施例提供一种显示基板及显示装置，所述显示基板包括：多个子像素，位于衬底基板上；所述子像素包括：第一导电层，位于所述衬底基板一侧，所述第一导电层包括：沿第一方向依次排列且向第二方向延伸的信号线，位于所述信号线的同一侧且相互间隔设置的信号线凸出部和阳极转接部；阳极，位于所述第一导电层与所述像素限定层之间；每一所述阳极包括被所述子像素开口暴露的有效部；其中，至少部分所述子像素的所述有效部在所述第二方向上与所述信号线凸出部和所述阳极转接部均存在交叠区域，所述第二方向与所述第一方向垂直。

Description

显示基板及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及显示基板及显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示基板因其自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。但现有技术的OLED显示基板存在大视角色偏，目视时呈现类似一侧发红，另一侧发青的问题。
发明内容
本公开实施例提供的显示基板，包括：
多个子像素，位于衬底基板上；
第一导电层，位于所述衬底基板一侧，所述第一导电层包括：沿第一方向依次排列且向第二方向延伸的信号线，位于至少部分相邻的两条所述信号线之间且相互间隔设置的信号线凸出部和阳极转接部，所述信号线凸出部与所述信号线一体连接；
像素限定层，位于所述第一导电层的背离所述衬底基板的一侧，包括多个与所述子像素对应的子像素开口；
阳极，位于所述第一导电层与所述像素限定层之间；每一所述阳极包括被所述子像素开口暴露的有效部，所述阳极转接部通过绝缘层过孔与所述阳极连接；
其中，至少部分所述子像素的所述有效部在所述第二方向上与所述信号线凸出部和所述阳极转接部均存在交叠区域，所述第二方向与所述第一方向垂直。
在一种可能的实施方式中，所述多个子像素包括第一子像素和第二子像 素，所述第一子像素的所述阳极的面积大于所述第二子像素的所述阳极的面积；
所述第一子像素的所述有效部在所述第二方向上与所述信号线凸出部和所述阳极转接部均存在交叠区域。
在一种可能的实施方式中，所述第一子像素的所述有效部与所述信号线凸出部的交叠区域为第一交叠区域，所述第一子像素的所述有效部与所述阳极转接部的交叠区域为第二交叠区域；
在第二方向上，所述第一交叠区域和所述第二交叠区域分别位于所述第一子像素的所述有效部的中心的两侧。
在一种可能的实施方式中，所述第一交叠区域和所述第二交叠区域到所述第一子像素的所述有效部的中心的间距比例为0.8～1.2。
在一种可能的实施方式中，所述第二子像素的所述阳极转接部在所述衬底基板的正投影覆盖所述有效部在所述衬底基板的正投影的中心，且所述第二子像素的所述阳极转接部在第二方向的尺寸大于所述有效部在第二方向的最大尺寸。
在一种可能的实施方式中，所述第二子像素的所述阳极转接部在所述第二方向上的长度，大于所述第一子像素的所述阳极转接部在所述第二方向上的长度。
在一种可能的实施方式中，所述信号线凸出部包括：凸出主部，以及连接所述凸出主部和所述信号线的凸出连接部；
所述凸出主部在所述第二方向上的长度大于所述凸出连接部在所述第二方向上的长度。
在一种可能的实施方式中，所述凸出主部在所述第一方向上的长度与所述阳极转接部在所述第一方向上的长度比值为0.8～1.2。
在一种可能的实施方式中，所述凸出主部在所述第二方向的长度小于所述阳极转接部在所述第二方向上的长度。
在一种可能的实施方式中，在由所述凸出连接部指向所述凸出主部的方 向上，所述凸出主部与最近邻的所述信号线之间具有间隔。
在一种可能的实施方式中，所述间隔在所述第一方向上的长度与所述凸出连接部在所述第一方向上的长度比值为0.8～1.2。
在一种可能的实施方式中，所述第一子像素的所述有效部为菱形；
所述第一子像素的有效部与所述凸出主部的交叠区域大致为三角形区域；所述第一子像素的有效部与所述阳极转接部的交叠区域大致为三角形区域；所述第一子像素的所述有效部与所述凸出主部的交叠区域，所述第一子像素的所述有效部与所述阳极转接部的所述交叠区域分别对应菱形的两个相对的角部。
在一种可能的实施方式中，所述阳极包括相互电连接的主体部分和辅助部分；所述主体部分包括所述有效部，以及由所述有效部外扩展的阳极扩展部；
所述第一子像素的所述阳极扩展部在朝向所述第二子像素的一侧还包括阳极遮挡部，所述阳极遮挡部在所述衬底基板的正投影覆盖第一区域，其中，所述第一区域包括至少部分与所述第二子像素对应像素电路中，阈值补偿晶体管的两个沟道区之间的区域。
在一种可能的实施方式中，同一所述子像素中，所述凸出主部的远离所述阳极转接部的侧边与所述凸出连接部的远离所述阳极转接部的侧边处于大致同一直线。
在一种可能的实施方式中，所述第二子像素的所述有效部的形状大致为四边形区域；
在列方向上，所述有效部与所述阳极转接部交叠的部分尺寸占所述有效部尺寸50％～100％。
在一种可能的实施方式中，所述阳极与所述第一导电层之间具有第一绝缘层；所述辅助部分通过贯穿所述第一绝缘层的第一过孔与所述阳极转接部电连接；
所述第一过孔在所述衬底基板的正投影，与所述阳极转接部的与所述有 效部交叠的区域在所述衬底基板的正投影互不交叠。
在一种可能的实施方式中，一列中相邻两个所述子像素交叠的所述信号线凸出部的图案不同。
在一种可能的实施方式中，所述第一子像素包括：第一颜色子像素和第三颜色子像素；所述第二子像素包括：第二颜色子像素和第四颜色子像素；
所述第一颜色子像素为红色子像素，所述第三颜色子像素为蓝色子像素，所述第二颜色子像素和所述第四颜色子像素为绿色子像素。
在一种可能的实施方式中，各所述信号线还包括信号线凸起部，所述信号线凸出部与所述信号线凸起部为同一结构；所述多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条所述第一信号线和一条所述第二信号线；所述第一信号线的信号线凸起部分别电连接奇数行子像素，所述第二信号线的信号线凸起部分别电连接偶数行子像素；
相邻两列子像素对应的两条第一信号线和两条第二信号线中，其中的两条第一信号线相邻形成一个第一信号线组，或者，其中的两条第二信号线相邻形成一个第二信号线组。
在一种可能的实施方式中，至少部分所述子像素的所述有效部在所述第一方向上与相邻的两条所述信号线均具有交叠区域。
在一种可能的实施方式中，所述子像素中，所述有效部与所述第一信号线存在第三交叠区域，所述有效部与所述第二信号线存在第四交叠区域；所述第三交叠区域和所述第四交叠区域位于所述阳极的所述有效部在所述第一方向上的两侧。
本公开实施例还提供一种显示装置，包括如本公开实施例提供的所述显示基板。
附图说明
图1为本公开实施例提供的显示基板的结构示意图；
图2a为本公开实施例提供的像素电路的结构示意图；
图2b为本公开实施例提供的信号时序图；
图3为本公开实施例提供的一些显示基板的布局结构示意图；
图4a为本公开实施例提供的有源半导体层的布局结构示意图；
图4b为本公开实施例提供的栅导电层的布局结构示意图；
图4c为本公开实施例提供的参考导电层的布局结构示意图；
图4d为本公开实施例提供的源漏金属层的布局结构示意图；
图4e为本公开实施例提供的第一导电层的布局结构示意图；
图4f为图4e的局部放大示意图；
图4g为本公开实施例提供的阳极层的布局结构示意图；
图4h为本公开实施例提供的源漏金属层与第一导电层叠层后的布局结构示意图；
图5a为本公开实施例提供的第一导电层与阳极层叠层后的结构示意图；
图5b为图5a中的第三颜色子像素的放大结构示意图；
图6a为图5a所示的布局结构示意图中沿AA’方向的剖视结构示意图；
图6b为图5a所示的布局结构示意图中沿BB’方向的剖视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元 件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的显示基板，可以包括：衬底基板10。位于衬底基板10上的多个重复单元PX，多个重复单元PX中的至少一个重复单元PX(例如每一个重复单元)可以包括多个子像素spx。例如，多个子像素可以包括第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4。也就是说，可以使重复单元包括第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4。这样可以使显示基板采用第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4进行混光，以实现彩色显示。在一些示例中，第一颜色、第二颜色、第三颜色以及第四颜色可以从红色、绿色以及蓝色中进行选取。例如，第一颜色为红色、第二颜色为绿色、第三颜色为蓝色，第四颜色为绿色。当然，本公开实施例包括但不限于此。下面以重复单元包括第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4，且第二颜色和第四颜色为绿色，第一颜色为红色，第三颜色为蓝色为例进行说明。
示例性地，结合图1所示，多个重复单元沿第二方向F2排列形成重复单元组PXZ，重复单元组PXZ沿第一方向F1排列。其中，第一方向F1与第二方向F2不同。示例性地，第一方向F1与第二方向F2垂直。例如，第一方向F1为行方向，第二方向F2为列方向。或者，第一方向F1为列方向，第二方向F2为行方向。
示例性地，结合图1与图2a所示，多个子像素spx中的至少一个子像素spx(例如每一个子像素)可以包括：像素电路0121和发光元件0120。其中， 像素电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号(如电流)输入到发光元件0120中，可以驱动发光元件0120发光。发光元件0120的阳极连接像素电路0121，同时发光元件0120的阴极连接一电源端。
结合图2a所示，像素电路0121可以包括：驱动控制电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。
驱动控制电路0122可以包括控制端、第一端和第二端。且驱动控制电路0122被配置为向发光元件0120提供驱动发光元件0120发光的驱动电流。例如，第一发光控制电路0123与驱动控制电路0122的第一端和第一电压端VDD连接。且第一发光控制电路0123被配置为实现驱动控制电路0122和第一电压端VDD之间的连接导通或断开。
第二发光控制电路0124与驱动控制电路0122的第二端和发光元件0120的阳极电连接。且第二发光控制电路0124被配置为实现驱动控制电路0122和发光元件0120之间的连接导通或断开。
数据写入电路0126与驱动控制电路0122的第一端电连接。且数据写入电路0126被配置为将数据线VD上的信号写入存储电路0127。
存储电路0127与驱动控制电路0122的控制端和第一电压端VDD电连接。且存储电路0127被配置为存储数据信号以及驱动控制电路0122的信息。
阈值补偿电路0128分别与驱动控制电路0122的控制端和第二端电连接。且阈值补偿电路0128被配置为对驱动控制电路0122进行阈值补偿。
复位电路0129还分别与驱动控制电路0122的控制端和发光元件0120的阳极电连接。且复位电路0129被配置为对发光元件0120的阳极进行复位，以及对驱动控制电路0122的控制端进行复位。
其中，发光元件0120可以设置为电致发光二极管，例如OLED、QLED、micro LED，micro OLED中的至少一种。其中，发光元件0120可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空 穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光元件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2a所示，驱动控制电路0122包括：驱动晶体管T1，驱动控制电路0122的控制端包括驱动晶体管T1的驱动栅极，驱动控制电路0122的第一端包括驱动晶体管T1的第一极，驱动控制电路0122的第二端包括驱动晶体管T1的第二极。
示例性地，结合图2a所示，数据写入电路0126包括数据写入晶体管T2。存储电路0127包括存储电容CST。阈值补偿电路0128包括阈值补偿晶体管T3。第一发光控制电路0123包括第一发光控制晶体管T4。第二发光控制电路0124包括第二发光控制晶体管T5。复位电路0129包括初始化晶体管T6和复位晶体管T7。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线VD电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与扫描线GA电连接以接收扫描信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T1的驱动栅极电连接。
阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的驱动栅极电连接，阈值补偿晶体管T3的栅极被配置为与扫描线GA电连接以接收扫描信号。
初始化晶体管T6的第一极被配置为与初始化线VINIT电连接以接收复位信号，初始化晶体管T6的第二极与驱动晶体管T1的驱动栅极电连接，初始化晶体管T6的栅极被配置为与复位线RST电连接以接收复位控制信号。
复位晶体管T7的第一极被配置为与初始化线VINIT电连接以接收复位信号，复位晶体管T7的第二极与发光元件0120的阳极电连接，复位晶体管T7的栅极被配置为与复位线RST电连接以接收复位控制信号。
第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶 体管T4的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光元件0120的阳极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
发光元件0120的阴极与第二电源端VSS电连接。其中，上述晶体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。上述晶体管可以为P型晶体管，可以为N型晶体管，也可以为P型晶体管和N型晶体管混合构成的像素电路，在此不做限定。本公开实施例以各晶体管为P型晶体管为例进行说明。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2a所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，例如第一电压为正电压或高电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，例如第二电压为低电压或0或者为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
图2a所示的像素电路对应的信号时序图，如图2b所示。一帧显示时间中，像素电路的工作过程具有三个阶段：T10阶段、T20阶段、T30阶段。其中，rst代表复位线RST上传输的信号，ga代表扫描线GA上传输的信号，em代表发光控制线EM上传输的信号。
在T10阶段，信号rst控制初始化晶体管T6导通，从而可以将初始化线VINIT上传输的信号提供给驱动晶体管T1的驱动栅极，以对驱动晶体管T1的驱动栅极进行复位。信号rst控制复位晶体管T7导通，以将初始化线VINIT上传输的信号提供给上一级发光元件0120的阳极，以对上一级发光元件0120的阳极进行复位。并且，此阶段中，信号ga控制数据写入晶体管T2和阈值补偿晶体管T3均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T20阶段，信号ga控制数据写入晶体管T2和阈值补偿晶体管T3导通，导通的数据写入晶体管T2使数据线VD上传输的数据信号对驱动晶体管T1 的驱动栅极进行充电，以使驱动晶体管T1的驱动栅极的电压变为：Vdata+Vth。其中，Vth代表驱动晶体管T1的阈值电压，Vdata代表数据信号的电压。并且，此阶段中，信号rst控制初始化晶体管T6和复位晶体管T7均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T30阶段，信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均导通。导通的第一发光控制晶体管T4将第一电源端VDD的电压Vdd提供给驱动晶体管T1的第一极，以使驱动晶体管T1的第一极的电压为Vdd。驱动晶体管T1根据其栅极电压Vdata+|Vth|，以及第一极的电压Vdd，产生驱动电流。该驱动电流通过导通的第二发光控制晶体管T5提供给发光元件0120，驱动发光元件0120发光。并且，此阶段中，信号rst控制初始化晶体管T6和复位晶体管T7截止。信号ga控制数据写入晶体管T2和阈值补偿晶体管T3截止。
需要说明的是，在本公开实施例中，上述晶体管的第一极可以为其源极，第二极为其漏极；或第一极为其漏极，第二极为其源极，这可以根据实际应用的需求进行设计确定。并且，子像素中的像素电路除了可以为图2a和图2b所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。下面以图2a所示的结构为例进行说明。
示例性地，显示基板包括衬底基板10、设置在衬底基板10上的晶体管阵列层，位于晶体管阵列层背离衬底基板10一侧的第一导电层，位于第一导电层背离衬底基板10一侧的第一绝缘层，位于第一绝缘层背离衬底基板10一侧的阳极，位于阳极背离衬底基板10一侧的发光层以及位于发光层背离衬底基板10一侧的阴极。其中，晶体管阵列层可以用于形成像素电路中的晶体管和电容，以及形成扫描线、复位线、发光控制线EM、初始化线VINIT、第一电源端VDD的第一电源信号线VDD等。示例性地，晶体管阵列层可以包括有源半导体层0310、栅导电层0320、参考导电层0330以及源漏金属层0340。
示例性地，如图3与图4a示出了该像素电路0121的有源半导体层0310。有源半导体层0310可采用半导体材料图案化形成。有源半导体层0310例如 采用多晶硅材料形成。有源半导体层0310可用于制作上述的驱动晶体管T1的驱动有源层T1-A、数据写入晶体管T2的有源层T2-A、阈值补偿晶体管T3的有源层T3-A、第一发光控制晶体管T4的有源层T4-A、第二发光控制晶体管T5的有源层T5-A、第一复位晶体管T6的有源层T6-A和第二复位晶体管T7的有源层T7-A。各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
示例性地，有源半导体层0310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。例如，沟道区可以为没有掺杂的区域，或者与源极区域、漏极区域掺杂类型不同的区域。例如，沟道区可以为在垂直衬底基板方向上与栅电极交叠的部分，在有源层中，同一个晶体管的源极区域和漏极区域可以分别为沟道区两侧的部分，且基本上与对应的栅电极无交叠(不考虑离子扩散的影响)。
示例性地，在上述的有源半导体层0310上形成有栅绝缘层，用于保护上述的有源半导体层0310。如图3与图4b所示，示出了该像素电路0121的栅导电层0320，栅导电层0320设置在栅绝缘层上，从而与有源半导体层0310绝缘。栅导电层0320可以包括存储电容CST的第二极cc2、扫描线GA、复位线RST、发光控制线EM、以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
例如，如图4b所示，数据写入晶体管T2的栅极可以为扫描线GA与有源半导体层0310交叠的部分，第一发光控制晶体管T4的栅极可以为发光控制线EM与有源半导体层0310交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制线EM与有源半导体层0310交叠的第二部分，第一复位晶体管T6的栅极为复位线RST与有源半导体层0310交叠的第一部分，第二复位晶体管T7的栅极为复位线RST与有源半导体层0310交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一 个栅极可为扫描线GA与有源半导体层0310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从扫描线GA突出的突出部与有源半导体层0310交叠的部分。如图3与图4b所示，驱动晶体管T1的驱动栅极可为存储电容CST的第二极cc2。
需要说明的是，图4a中的各虚线示出了栅导电层0320与有源半导体层0310交叠的各个部分。
示例性地，如图3与图4b所示，扫描线GA、复位线RST和发光控制线EM沿第二方向F2排布。且扫描线GA、复位线RST和发光控制线EM大致沿第一方向F1延伸。示例性地，扫描线GA位于本行复位线RST和本行发光控制线EM之间。示例性地，图3仅是以第二方向F2为列方向，第一方向F1为行方向为例进行说明。
示例性地，在第二方向F2上，存储电容CST的第二极cc2位于扫描线GA和发光控制线EM之间。并且，从扫描线GA突出的突出部位于扫描线GA远离发光控制线EM的一侧。
示例性地，在上述的栅导电层0320上形成有层间介质层，用于保护上述的栅导电层0320。如图3与图4c所示，示出了该像素电路120a的参考导电层0330，参考导电层0330包括存储电容CST的第一极cc1、初始化线VINIT、遮光层ZG。其中，存储电容CST的第一极cc1与存储电容CST的第二极cc2至少部分交叠以形成存储电容CST。示例性地，存储电容CST的第一极cc1具有镂空区，该镂空区可以暴露出存储电容CST的第二极cc2的部分。
示例性地，如图3与图4c所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的第二复位晶体管T7的源极区域(如第二复位晶体管T7的源极区域与第一复位晶体管T6的源极区域为一体结构)在衬底基板10的正投影交叠。这样可以降低光对第二复位晶体管T7的影响，提高复位准确性。例如，阈值补偿晶体管T3为双栅晶体管。例如，遮光层ZG遮挡阈值补偿晶体管T3的两个栅极中间的有源层部分，因为阈值补偿晶体管T3直接连接驱动晶体管T1，可以起到稳定驱动晶体管T1工作状态的作用。例如，遮光层 ZG在衬底基板的投影位于其所在的像素电路区域中与该像素电路直接电连接的数据线和第一电源信号线VDD之间，起到屏蔽信号干扰的作用。
示例性地，如图3与图4c所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的第一复位晶体管T6的漏极区域在衬底基板10的正投影交叠。这样可以降低光对第一复位晶体管T6的影响，提高复位准确性。
示例性地，如图3与图4c所示，遮光层ZG在衬底基板10的正投影与有源半导体层0310中的阈值补偿晶体管T3的有源层T3-A之间的导电区在衬底基板10的正投影交叠。这样可以降低光对阈值补偿晶体管T3的影响，提高阈值补偿的准确性。
示例性地，在上述的参考导电层0330上形成有第一层间绝缘层，用于保护上述的参考导电层0330。如图3与图4d所示，示出了该像素电路0121的源漏金属层0340，源漏金属层0340可以包括第一电源信号线VDD、连接部LB1、LB2、LB3、LB4。示例性地，第一颜色子像素spx1、第二颜色子像素spx2、第三颜色子像素spx3以及第四颜色子像素spx4分别包括连接部LB1、LB2、LB3、LB4。
示例性地，在上述的源漏金属层0340上形成有第二层间绝缘层，用于保护上述的源漏金属层0340。如图3、图4e、图4f、图5a所示，示出了该像素电路0121的第一导电层0350，其中，图4f为图4e在虚线框处的放大示意图，第一导电层0350包括：沿第一方向F1依次排列且向第二方向F2延伸的信号线Vd，位于信号线Vd的同一侧且相互间隔设置的信号线凸出部TQ(TQ1/TQ2/TQ3/TQ4)和阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)，信号线凸出部TQ与信号线Vd一体连接。具体的，信号线Vd可以被配置为传输数据信号的数据线Vd。示例性地，第一颜色子像素spx1可以包括信号线凸出部TQ1和阳极转接部YZ1，第二颜色子像素spx2可以包括信号线凸出部TQ2和阳极转接部YZ2，第三颜色子像素spx3可以包括信号线凸出部TQ3和阳极转接部YZ3，第四颜色子像素spx4可以包括信号线凸出部TQ4和阳极转接部YZ4，阳极转接部YZ通过绝缘层过孔与阳极连接。具体的，一列中相邻两个子像素 交叠的信号线凸出部的图案不同，具体的，例如，结合图4f所示，位于第一行在左起的第一个信号线凸出部TQ1，与位于第二行左起的第一个信号线凸出部TQ5属于一列中相邻两个子像素的两个信号线凸出部，位于第一行在左起的第一个信号线凸出部TQ1包括向右侧延伸出的凸出连接部TQL1，而位于第二行左起的第一个信号线凸出部TQ5包括向左侧延伸出的凸出连接部TQL5，也即位于第一行在左起的第一个信号线凸出部TQ1，与位于第二行左起的第一个信号线凸出部TQ5的图案不同。
示例性地，结合图4e所示，各信号线Vd还包括信号线凸起部，信号线凸出部TQ具体可以与信号线凸起部为同一结构；多条信号线Vd包括第一信号线Vd1和第二信号线Vd2；其中，一列子像素对应一条第一信号线Vd1和一条第二信号线Vd2；第一信号线Vd1的信号线凸起部分别电连接奇数行子像素，第二信号线Vd2的信号线凸起部分别电连接偶数行子像素；相邻两列子像素对应的两条第一信号线Vd1和两条第二信号线Vd2中，其中的两条第一信号线Vd1相邻(可以理解为两条第一信号线Vd1之间没有其他相应的信号线，例如，相邻的这两条数据线之间没有其他数据线)形成一个第一信号线组，或者，其中的两条第二信号线Vd2相邻(可以理解为两条第二信号线Vd2之间没有其他相应的信号线，例如，相邻的这两条数据线之间没有其他数据线)形成一个第二信号线组。具体的，多条信号线Vd分为多个信号线组Vdx(Vdx1/Vdx2/Vdx3/Vdx4)，多个信号线组Vdx呈周期性排布。每一信号线组Vdx包括位于同一列子像素两侧的第一信号线Vd1和第二信号线Vd2。例如，第一信号线Vd1位于一列子像素的第一侧，第二信号线Vd2位于该列子像素的第二侧。例如，第一侧可以为左侧，第二侧可以为右侧；又例如，第一列可以为右侧，第二侧可以为左侧。相邻信号线组之间的间隙的间距可以为ax。同一信号线组中，第一信号线Vd1和第二信号线Vd2之间的间隙的间距可以为ay。其中，ax可以小于ay。例如，ax可以为3-7微米。例如，ay可以为12-20微米。其中，一列子像素对应一个信号线组Vdx的一条第一信号线Vd1和一条第二信号线Vd2，例如，一列子像素的像素电路左右两侧分 别与一条第一信号线Vd1和一条第二信号线Vd2相邻。第一信号线Vd1驱动奇数行子像素，第二信号线Vd2驱动偶数行子像素。具体的，信号线凸出部TQ可以为与数据线Vd一体电连接的信号线凸起部，有利于简化显示基板的制作工艺以及简化显示基板的走线复杂度，当然，若不考虑显示基板的制作工艺难度以及走线复杂度，信号线凸出部也可以是独立于信号线凸起部以外的其它结构。数据线Vd沿第二方向F2延伸，沿第一方向F1依次排列。第一信号线Vd1的信号线凸起部分别电连接奇数行子像素，第二信号线Vd2的信号线凸起部分别电连接偶数行子像素。
示例性地，在上述的第一导电层0350上形成有第一绝缘层，用于保护上述的第一导电层0350。如图3、图4g、图5a所示，示出了位于第一导电层0350背离衬底基板10一侧的阳极层0360，阳极层0360包括阳极Y(Y1/Y2/Y3/Y4)。示例性地，第一颜色子像素spx1可以包括阳极Y1，第二颜色子像素spx2可以包括阳极Y2，第三颜色子像素spx3可以包括阳极Y3，第四颜色子像素spx4可以包括阳极Y4。
如图3至图4f所示，第一电源信号线VDD通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中对应的第一发光控制晶体管T4的源极区域电连接。第一电源信号线VDD通过贯穿第一层间绝缘层中的至少一个过孔与参考导电层0330中的存储电容CST的第一极cc1电连接。第一电源信号线VDD还通过贯穿第一层间绝缘层中的至少一个过孔与遮光层ZG电连接。
如图3至图4f所示，连接部LB1的一端通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中对应的阈值补偿晶体管T3的漏极区域电连接。连接部LB1的另一端通过贯穿第一层间绝缘层中的至少一个过孔与初始化线VINIT电连接。
如图3至图4h所示，连接部LB2的一端通过贯穿第二层间绝缘层中的第三过孔K3(K31/K32/K33/K34)与信号线凸出部TQ(TQ1/TQ2/TQ3/TQ4)电连接，连接部LB2的另一端通过贯穿栅绝缘层、层间介质层和第一层间绝 缘层中的至少一个过孔与有源半导体层0310中的数据写入晶体管T2的源极区域电连接。
如图3至图4f所示，连接部LB3的一端通过贯穿层间介质层和第一层间绝缘层中的至少一个过孔与存储电容CST的第二极cc2电连接。连接部LB3的另一端通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中的第一复位晶体管T6的漏极区域电连接。
如图3至图4f所示，连接部LB4通过贯穿栅绝缘层、层间介质层和第一层间绝缘层中的至少一个过孔与有源半导体层0310中的第二发光控制晶体管T5的漏极区域电连接。
在一些示例中，如图3至图5a以及图6a所示，第一绝缘层包括第一过孔K1(K11/K12/K13/K14)，第一过孔K1暴露阳极转接部YZ的一部分，且阳极Y包括相互电连接的主体部分和辅助部分；主体部分可以包括被后续形成的像素限定层的子像素开口暴露的有效部，以及由有效部外扩展的阳极扩展部；辅助部分由阳极扩展部沿第二方向向阳极转接部一侧延伸出；阳极扩展部的外轮廓形状与有效部的外轮廓形状相似；其中，辅助部分通过第一过孔K1与阳极转接部YZ电连接。例如，第一颜色子像素spx1中，阳极Y1包括相互电连接的主体部分Y11和辅助部分Y12，主体部分Y11包括有效部Y13以及阳极扩展部Y14，辅助部分Y12通过第一过孔K11与阳极转接部YZ1电连接，阳极转接部YZ1通过贯穿第二层间绝缘层的第二过孔K21与对应的连接部LB4电连接。第二颜色子像素spx2中，阳极Y2包括相互电连接的主体部分Y21和辅助部分Y22，主体部分Y21包括有效部Y23以及阳极扩展部Y24，辅助部分Y22通过第一过孔K12与阳极转接部YZ2电连接，阳极转接部YZ2通过贯穿第二层间绝缘层的第二过孔K22与对应的连接部LB4电连接。第三颜色子像素spx3中，阳极Y3包括相互电连接的主体部分Y31和辅助部分Y32，主体部分Y31包括有效部Y33以及阳极扩展部Y34，辅助部分Y32通过第一过孔K13与阳极转接部YZ3电连接，阳极转接部YZ3通过贯穿第二层间绝缘层的第二过孔K23与对应的连接部LB4电连接。第四颜色子像素 spx4中，阳极Y4包括相互电连接的主体部分Y41和辅助部分Y42，主体部分Y41包括有效部Y43以及阳极扩展部Y44，辅助部分Y42通过第一过孔K14与阳极转接部YZ4电连接，阳极转接部YZ4通过贯穿第二层间绝缘层的第二过孔K24与对应的连接部LB4电连接。在一些示例中，结合图4g所示，同一重复单元中，第一颜色子像素spx1的有效部Y13的中心Q1、第二颜色子像素spx2的有效部Y23的中心O2、第三颜色子像素spx3的有效部Y33的中心O3、第四颜色子像素spx4的有效部Y43的中心O4大致围成一四边形，例如为一平行四边形。例如，第一颜色子像素spx1的有效部Y13的中心O1、第三颜色子像素spx3的有效部Y33的中心O3位于四边形的相邻两个顶点，连线垂直于第二方向F2。例如，第二颜色子像素spx2的有效部Y23的中心O2、第四颜色子像素spx4的有效部Y43的中心O4位于四边形的另外相邻两个顶点，连线垂直于第二方向F2。例如，第一颜色子像素spx1的有效部Y13的中心O1、第三颜色子像素spx3的有效部Y33的中心O3连线的中垂线可以穿过一第二颜色子像素spx2的有效部Y23，例如可以穿过一第二颜色子像素spx2的有效部Y23的中心O2。例如，第二颜色子像素spx2的有效部Y23的中心O2、第四颜色子像素spx4的有效部Y43的中心O4连线的中垂线穿过第三颜色子像素spx3的有效部Y33，例如可以穿过第三颜色子像素spx3的有效部Y33的中心O3。
在一些示例中，结合图4g和图4a所示，在第一子像素中，阳极扩展部在朝向第二子像素的一侧还包括有阳极遮挡部，该阳极遮挡部在衬底基板的正投影覆盖第一区域，其中，第一区域包括至少部分与第二子像素对应像素电路中，阈值补偿晶体管的两个沟道区之间的区域。例如，第一区域包括与第二子像素对应像素电路中，阈值补偿晶体管的两个沟道区之间的区域面积的一半以上。例如，第一颜色子像素spx1中，阳极扩展部Y14在朝向第二颜色子像素spx3的一侧还包括有阳极遮挡部YA1，该阳极遮挡部YA1在衬底基板10的正投影覆盖同一子像素中相邻的第二颜色子像素spx2的有源半导体层0310中的第一区域在衬底基板10的正投影，其中，第一区域包括至少部分第 二颜色子像素spx2对应的像素电路中的阈值补偿晶体管T3的两个沟道区T3-A之间的区域。又例如，第三颜色子像素spx3中，阳极扩展部Y34在朝向第四颜色子像素spx4的一侧还包括有阳极遮挡部YA3，该阳极遮挡部YA3在衬底基板10的正投影覆盖同一子像素中相邻的第四颜色子像素spx4的有源半导体层0310中的第一区域在衬底基板10的正投影，其中，第一区域包括至少部分第四颜色子像素spx4对应的像素电路中的阈值补偿晶体管T3的两个沟道区T3-A之间的区域。
需要说明的是，阳极包括的相互电连接的主体部分和辅助部分为一体结构，即主体部分和辅助部分是连续形成的。
在一些示例中，结合图5a所示，在上述的阳极层的背离衬底基板10的一侧形成有像素限定层，像素限定层包括多个与子像素一一对应的子像素开口。例如，至少部分子像素的有效部在第二方向F2上与对应的像素电路连接的信号线凸出部TQ和阳极转接部YZ均存在交叠区域，即一平行于第二方向F2的一条直线可以同时穿过信号线凸出部TQ和阳极转接部YZ，例如一平行于第二方向F2的一条直线可以穿过同一列所有子像素的信号线凸出部TQ和阳极转接部YZ，且其穿过的信号线凸出部TQ和阳极转接部YZ在第二方向F2上交替分布。例如，第一颜色子像素spx1的有效部Y13与对应的像素电路连接的信号线凸出部TQ1存在第一交叠区域S1，与对应的像素电路连接的阳极转接部YZ1存在第二交叠区域S1’。例如，第三颜色子像素spx3的有效部Y33与对应的像素电路连接的信号线凸出部TQ3存在第一交叠区域S3，与对应的像素电路连接的阳极转接部YZ3存在第二交叠区域S3’。本公开实施例中，至少部分子像素的有效部在第二方向上与对应的像素电路连接的信号线凸出部TQ和阳极转接部YZ均存在交叠区域，可以改善若阳极Y的有效部仅与阳极转接部YZ存在交叠时，会使有效部在与阳极转接部YZ对应的一端位置相对较高，进而会存在色偏的问题。
在具体实施时，阳极的被子像素开口暴露的有效部，可以与后续形成的发光层接触，进而对该子像素的发光区域进行限定。像素限定层的除子像素 开口以外的区域可以为覆盖阳极以及阳极所在区域以外其它区域的覆盖部，其图案简单，可以与常规显示基板的像素限定层的图案一致，本公开实施例不再示出。
在一些示例中，结合图5a所示，多个子像素分为第一子像素01和第二子像素02，第一子像素01的阳极的面积大于第二子像素02的阳极的面积；第一子像素01的有效部在第二方向F2上与对应的像素电路连接的信号线凸出部TQ和阳极转接部YZ均存在交叠区域。第二子像素02的阳极转接部YZ在衬底基板10的正投影穿过有效部在衬底基板10的正投影，例如穿过有效部在衬底基板10的正投影的中心。具体的，例如，第一子像素01可以包括第一颜色子像素spx1和第三颜色子像素spx3，第二子像素02可以包括第二颜色子像素和第四颜色子像素spx4，第一颜色子像素spx1具体可以为红色子像素，第三颜色子像素spx1具体可以为蓝色子像素，第二颜色子像素spx2和第四颜色子像素spx4具体可以为绿色子像素。具体的，例如，第一颜色子像素spx1的有效部Y13在第二方向F2上与对应的像素电路连接的信号线凸出部TQ1和阳极转接部YZ1均存在交叠区域。例如，第三颜色子像素spx3有效部Y33在第二方向F2上与对应的像素电路连接的信号线凸出部TQ3和阳极转接部YZ3均存在交叠区域。例如，第二颜色子像素spx2的阳极转接部YZ2在衬底基板10的正投影覆盖有效部Y23在衬底基板10的正投影，例如覆盖有效部Y23在衬底基板10的正投影的中心O2。例如，第四颜色子像素spx4的阳极转接部YZ4在衬底基板10的正投影覆盖有效部Y43在衬底基板10的正投影，例如覆盖有效部Y43在衬底基板10的正投影的中心O4。本公开实施例中，由于第一子像素01的阳极转接部YZ与有效部交叠区域较小，而第二子像素02的阳极转接部YZ通常与有效部交叠区域较大(第二子像素02的阳极转接部YZ与源漏极金属层0340导通的孔所占区域更接近有效部的中心)，进而，在对第一子像素01和第二子像素02进行改善色偏时，使第一子像素01的有效部在第二方向F2上与信号线凸出部TQ和阳极转接部YZ均存在交叠区域，使第二子像素02的阳极转接部YZ在衬底基板10的正投影覆 盖有效部在衬底基板10的正投影，例如覆盖有效部YZ在衬底基板10的正投影的中心，改善第一子像素01和第二子像素02的色偏问题。
在具体实施时，结合图5a以及图6b所示，第二子像素02的阳极转接部YZ在衬底基板10的正投影覆盖有效部在衬底基板10的正投影的中心，并覆盖有效部在衬底基板10的正投影的60％以上，例如覆盖70％以上，例如覆盖80％以上。例如，结合图5a所示，第二颜色子像素spx2的阳极转接部YZ2在衬底基板10的正投影，覆盖有效部Y23在衬底基板10的正投影的中心O2，并覆盖有效部Y23在衬底基板10的正投影的60％以上，例如覆盖70％以上，例如覆盖80％以上。例如，第二子像素02的阳极转接部YZ在衬底基板10的正投影穿过有效部在衬底基板10的正投影的大部分区域，例如60％以上，例如覆盖70％以上，例如覆盖80％以上。例如，第二子像素的阳极转接部在衬底基板的正投影也可以是穿过有效部在衬底基板的正投影的全部。例如，阳极转接部YZ沿第二方向F2延伸，第二子像素02的阳极转接部YZ在衬底基板10的正投影覆盖有效部在衬底基板10的正投影的中心。例如，第二子像素02的阳极转接部YZ在衬底基板10的正投影，穿过有效部在衬底基板10的正投影在第二方向F2上的正投影的中心。
在一些示例中，结合图5a所示，第一交叠区域S1和第二交叠区域S2的形状相似，面积相同。具体的，结合图5b所示，其中，图5b为图5a中的一第一子像素01(第三颜色子像素spx3)的放大示意图，第一交叠区域在第二方向上的最大长度占有效部在第二方向上最大长度的十分之一至三分之一。例如，第二交叠区域在第二方向上的最大长度占有效部在第二方向上最大长度的十分之一至三分之一。例如，第三颜色子像素spx3中，第一交叠区域S1在第二方向F2上的最大长度k1占有效部Y33在第二方向上F2最大长度k的十分之一至三分之一；第二交叠区域S2在第二方向F2上的最大长度k2占有效部Y33在第二方向F2上最大长度k的十分之一至三分之一。进一步的，第一交叠区域和第二交叠区域关于过有效部的中心且垂直于第二方向的直线对称。例如，第三子像素spx3中，第一交叠区域S1和第二交叠区域S2关于 过有效部Y33的中心O3且垂直于第二方向F2的直线X对称。本公开实施例中，第一交叠区域和第二交叠区域关于过有效部的中心且垂直于第二方向的直线对称，可以对第一子像素的色偏问题进行效果较佳的改善。当然，可以理解的是，在具体实施时，要实现使第一交叠区域和第二交叠区域关于过有效部的中心且垂直于第二方向的直线完全精准对称，工艺上较难实现，因此，本公开实施例中的第一交叠区域和第二交叠区域关于过有效部的中心且垂直于第二方向的直线对称，可以理解为第一交叠区域和第二交叠区域关于过有效部的中心且垂直于第二方向的直线大致对称。
在一些示例中，结合图4f所示，第二子像素02的阳极转接部YZ在第二方向F2上的长度h2，大于第一子像素01的阳极转接部YZ在第二方向F2上的长度h1。例如，第二颜色子像素spx2的阳极转接部YZ2在第二方向F2上的长度h2，大于第一颜色子像素spx1的阳极转接部YZ1在第二方向F2上的长度h1。本公开实施例中，设置第二子像素02的阳极转接部YZ在第二方向F2上的长度较长，可以实现通过第二子像素02的阳极转接部YZ自身对阳极的有效部下方的平坦性进行补偿。
在一些示例中，结合图4f所示，信号线凸出部TQ(TQ1/TQ2/TQ3/TQ4)包括：凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)，以及连接凸出主部TQZ和信号线Vd的凸出连接部TQL(TQL1/TQL2/TQL3/TQL4)。例如，凸出主部TQZ在第二方向F2上的长度h3大于凸出连接部TQL在第二方向F2上的长度h4。本公开实施例中，通过设置在第二方向F2上较长的凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)，进而可以实现通过凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)与阳极的有效部产生较多交叠，进而改善色偏问题。
在一些示例中，结合图4f所示，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)在第一方向F1上的长度h5与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)在第一方向F1上的长度h6大致相同。例如，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)在第一方向F1上的长度h5与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)第一方向 F1上的长度h6的比值大致为0.8-1.2。本公开实施例中，通过使凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)在第一方向F1上的长度相同，有利于阳极的有效部与凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)和阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)交叠时，产生的交叠面积大致相同。例如，阳极的有效部与凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)和阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)交叠的交叠面积比例大致为0.8-1.2。
在一些示例中，结合图4f所示，同一子像素中，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)在第二方向F2的长度h3小于阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)在第二方向F2上的长度h1。例如，第一颜色子像素中，凸出主部TQZ1在第二方向F2的长度h3小于阳极转接部YZ1在第二方向F2上的长度h1。本公开实施例中，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)在第二方向F2的长度h3小于阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)在第二方向F2上的长度h1，有利于通过阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)实现通过过孔与其它膜层的导通。例如，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)在第二方向F2的长度h3小于15微米。例如h3小于12微米。例如h3大于6微米。例如，h4小于5微米。例如，h4小于4微米。例如，h5大于相邻凸出主部两侧的两条信号线之间间距的一半。例如，h5为8微米～20微米。例如，h5为10微米～15微米。因为凸出主部用于信号线与其他膜层的电连接，一般通过过孔连接，即凸出主部上设置有其一体连接的信号线与其他膜层连接的过孔，所以其对应的尺寸h3和h5的尺寸不能过小，至少要大于过孔的尺寸。例如，一个过孔的尺寸例如为4*4微米。例如，一个过孔的尺寸为3*3微米。例如，一个过孔的尺寸例如为圆形孔，直径为2-4微米。例如，凸出主部上传输的是用于各个子像素显示的数据信号，为了减小与其他信号的干扰，h3和h5也不能过大。例如，在第一方向，凸出主部与相邻的另一信号线例如数据线之间具有间隔，该间隔例如和h4大致相等，或比例大致为0.8-1.2。例如，阳极转接部YZ与其第一方向两侧相邻的两条信号线之间也具有间隔，左 右两侧间隔大致相等，该间隔例如和h4大致相等，或比例大致为0.8-1.2。例如，阳极转接部YZ与其左侧相邻的信号线之间的间隔小于5微米。例如，阳极转接部YZ与其左侧相邻的信号线之间的间隔小于4微米。例如，阳极转接部YZ与其右侧相邻的信号线之间的间隔小于5微米。例如，阳极转接部YZ与其右侧相邻的信号线之间的间隔小于4微米。
在一些示例中，结合图4f所示，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)的形状与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)的形状相似。具体的，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)的形状与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)的形状均为矩形。本公开实施例中，凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)的形状与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)的形状相似，有利于阳极的有效部与凸出主部TQZ(TQZ1/TQZ2/TQZ3/TQZ4)和阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)交叠时，产生的交叠面积相同。
在一些示例中，结合图4g或图5a所示，第一子像素的有效部为菱形，例如为正方形。例如，第一颜色子像素spx1的有效部Y13为菱形，例如为正方形。例如，第三颜色子像素spx3的有效部Y33为菱形，例如为正方形。菱形的其中一条对角线与第二方向F2平行。例如，图5a中，第一颜色子像素spx1的竖向对角线与第二方向F2平行。例如，第一子像素的有效部与凸出主部的交叠区域大致为三角形区域，对应菱形的一个角部。例如，第一子像素的有效部与阳极转接部的交叠区域大致为三角形区域，对应菱形的一个角部。例如，第一子像素的有效部与凸出主部的交叠区域，第一子像素的有效部与阳极转接部的交叠区域分别对应菱形的两个相对的角部。例如，结合图5a所示，第一颜色子像素spx1的有效部Y13与凸出主部TQZ1的交叠区域大致为三角形区域。例如，第一颜色子像素spx1的有效部Y13与阳极转接部YZ1的交叠区域大致为三角形区域。在一些示例中，结合图4g或图5a所示，第二子像素02的有效部形状为四边形，例如为圆角四边形，结合图5a所示，在列方向上，有效部Y23与阳极转接部YZ交叠的部分尺寸占有效部Y23尺寸50％～100％，即，阳极转接部YZ穿过有效部Y23的大部分区域，具体的， 有效部Y23与阳极转接部YZ交叠的部分尺寸占有效部Y23尺寸60％～90％，有效部Y23与阳极转接部YZ交叠的部分尺寸占有效部Y23尺寸70％～80％.有效部Y23与阳极转接部YZ交叠的部分尺寸占有效部Y23尺寸的80％。例如，阳极转接部在衬底基板上的正投影穿过第二子像素的有效部的两个对角区域在衬底基板的正投影。例如，第二颜色子像素spx2的有效部Y23形状为四边形，例如为圆角四边形。例如，阳极转接部Y22在衬底基板10的正投影穿过第二颜色子像素spx2的有效部Y23的上下两个对角区域在衬底基板10上的正投影。在具体实施时，由于实际工艺限制，第二子像素02的四边形的有效部在拐角位置处也可以为非直角形过渡，例如，可以为弧形过渡。
在一些示例中，结合图4e或图4f所示，同一子像素01中，凸出主部TQZ的远离阳极转接部YZ的侧边与凸出连接部TQL的远离阳极转接部YZ的侧边处于同一直线，即，第一子像素01中，信号线凸出部TQZ的远离阳极转接部YZ的一侧齐平，第二子像素中，信号线凸出部TQZ的远离阳极转接部YZ的一侧齐平。
在一些示例中，结合图5a所示，第一过孔K1(K11/K12/K13/K14)在衬底基板10的正投影，与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)的与有效部交叠的区域在衬底基板10的正投影互不交叠。例如，第一颜色子像素spx1中，第一过孔K11(该第一过孔K11导通阳极Y1的辅助部分Y12与阳极转接部YZ1)在衬底基板10的正投影，与阳极转接部YZ1的与有效部Y13交叠的区域(也即第一交叠区域S1)在衬底基板10的正投影互不交叠。本公开实施例中，第一过孔K1(K11/K12/K13/K14)在衬底基板10的正投影，与阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)的与有效部交叠的区域在衬底基板10的正投影互不交叠，可以避免在第一过孔K1所在区域使阳极转接部YZ(YZ1/YZ2/YZ3/YZ4)的与有效部交叠时，会使交叠区域产生不平坦，进而无法实现平坦性补偿。
在一些示例中，结合图5a所示，至少部分子像素中，阳极的有效部在第一方向F1上与相邻的两条信号线Vd均具有交叠区域。例如，第一颜色子像 素spx1中，阳极Y1的有效部Y13在第一方向F1上与相邻的两条信号线Vd均具有交叠区域。本公开实施例中，至少部分子像素中，阳极的有效部在第一方向上与相邻的两条信号线均具有交叠区域或者阳极的有效部在第一方向上与相邻的两条信号线均不具有交叠区域，可以避免若阳极的有效部在第一方向上仅与一侧的信号线交叠时会存在色偏的问题。
在一些示例中，也可以是全部的子像素中，阳极的有效部在第一方向F1上与相邻的两条信号线Vd均具有交叠区域。
具体的，将阳极的有效部在第一方向上与第一信号线的交叠区域作为第三交叠区域，将阳极的有效部在第一方向上与第二信号线的交叠区域作为第四交叠区域，第三交叠区域与第四交叠区域位于阳极的有效部在第一方向上的两侧。例如，第三交叠区域与第四交叠区域到过有效部的中心且垂直于第一方向的直线的距离比值为0.8-1.2，进一步的距离第三交叠区域与第四交叠区域到过有效部的中心且垂直于第一方向的直线的距离可以相等。例如，第三交叠区域与第四交叠区域相对到过有效部的中心且垂直于第一方向的直线大致对称。例如，结合图5b所示，在第三颜色子像素spx3中，将阳极Y3的有效部Y33在第一方向F1上与第一信号线Vd1的交叠区域作为第三交叠区域S3”，将阳极Y3的有效部Y33在第一方向F 1上与第二信号线Vd2的交叠区域作为第四交叠区域S3”'，第三交叠区域S3”与第四交叠区域S3”'位于阳极Y3的有效部Y33在第一方向F1上的两侧。例如，第三交叠区域S3”与第四交叠区域S3”'到过有效部Y33的中心O3且垂直于第一方向F1的直线Y的距离比值为0.8-1.2，进一步的，距离第三交叠区域S3”与第四交叠区域S3”'到过有效部Y33的中心O3且垂直于第一方向F1的直线Y的距离可以相等。例如，第三交叠区域S3”与第四交叠区域S3”'相对到过有效部Y33的中心O3且垂直于第一方向F1的直线Y大致对称。
本公开实施例还提供一种显示装置，其中，包括如本公开实施例提供的显示基板。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了 基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (22)

  1. 一种显示基板，其中，包括：
    多个子像素，位于衬底基板上；
    第一导电层，位于所述衬底基板一侧，所述第一导电层包括：沿第一方向依次排列且向第二方向延伸的信号线，位于至少部分相邻的两条所述信号线之间且相互间隔设置的信号线凸出部和阳极转接部，所述信号线凸出部与所述信号线一体连接；
    像素限定层，位于所述第一导电层的背离所述衬底基板的一侧，包括多个与所述子像素对应的子像素开口；
    阳极，位于所述第一导电层与所述像素限定层之间；每一所述阳极包括被所述子像素开口暴露的有效部，所述阳极转接部通过绝缘层过孔与所述阳极连接；
    其中，至少部分所述子像素的所述有效部在所述第二方向上与所述信号线凸出部和所述阳极转接部均存在交叠区域，所述第二方向与所述第一方向垂直。
  2. 如权利要求1所述的显示基板，其中，所述多个子像素包括第一子像素和第二子像素，所述第一子像素的所述阳极的面积大于所述第二子像素的所述阳极的面积；
    所述第一子像素的所述有效部在所述第二方向上与所述信号线凸出部和所述阳极转接部均存在交叠区域。
  3. 如权利要求2所述的显示基板，其中，所述第一子像素的所述有效部与所述信号线凸出部的交叠区域为第一交叠区域，所述第一子像素的所述有效部与所述阳极转接部的交叠区域为第二交叠区域；
    在第二方向上，所述第一交叠区域和所述第二交叠区域分别位于所述第一子像素的所述有效部的中心的两侧。
  4. 如权利要求3所述的显示基板，其中，所述第一交叠区域和所述第二 交叠区域到所述第一子像素的所述有效部的中心的间距比例为0.8～1.2。
  5. 如权利要求2所述的显示基板，其中，所述第二子像素的所述阳极转接部在所述衬底基板的正投影覆盖所述第二子像素的有效部在所述衬底基板的正投影的中心，且所述第二子像素的所述阳极转接部在第二方向的最大尺寸大于所述有效部在第二方向的最大尺寸。
  6. 如权利要求2所述的显示基板，其中，所述第二子像素的所述阳极转接部在所述第二方向上的长度，大于所述第一子像素的所述阳极转接部在所述第二方向上的长度。
  7. 如权利要求2-6任一项所述的显示基板，其中，所述信号线凸出部包括：凸出主部，以及连接所述凸出主部和所述信号线的凸出连接部；
    所述凸出主部在所述第二方向上的长度大于所述凸出连接部在所述第二方向上的长度。
  8. 如权利要求7所述的显示基板，其中，所述凸出主部在所述第一方向上的长度与所述阳极转接部在所述第一方向上的长度比值为0.8～1.2。
  9. 如权利要求8所述的显示基板，其中，所述凸出主部在所述第二方向的长度小于所述阳极转接部在所述第二方向上的长度。
  10. 如权利要求7-9所述的显示基板，其中，在由所述凸出连接部指向所述凸出主部的方向上，所述凸出主部与最近邻的所述信号线之间具有间隔。
  11. 如权利要求10所述的显示基板，其中，所述间隔在所述第一方向上的长度与所述凸出连接部在所述第一方向上的长度比值为0.8～1.2。
  12. 如权利要求2所述的显示基板，其中，所述第一子像素的所述有效部大致为菱形；
    所述第一子像素的有效部与所述凸出主部的交叠区域大致为三角形区域；所述第一子像素的有效部与所述阳极转接部的交叠区域大致为三角形区域；所述第一子像素的所述有效部与所述凸出主部的交叠区域，所述第一子像素的所述有效部与所述阳极转接部的所述交叠区域分别对应菱形的两个相对的角部。
  13. 如权利要求12所述的显示基板，其中，所述阳极包括相互电连接的主体部分和辅助部分；所述主体部分包括所述有效部，以及由所述有效部外扩展的阳极扩展部；
    所述第一子像素的所述阳极扩展部在朝向所述第二子像素的一侧还包括阳极遮挡部，所述阳极遮挡部在所述衬底基板的正投影覆盖第一区域，其中，所述第一区域包括至少部分与所述第二子像素对应像素电路中，阈值补偿晶体管的两个沟道区之间的区域。
  14. 如权利要求7所述的显示基板，其中，同一所述子像素中，所述凸出主部的远离所述阳极转接部的侧边与所述凸出连接部的远离所述阳极转接部的侧边处于大致同一直线。
  15. 如权利要求2-5所述的显示基板，其中，所述第二子像素的所述有效部的形状大致为四边形区域；
    在列方向上，所述有效部与所述阳极转接部交叠的部分尺寸占所述有效部尺寸50％～100％。
  16. 如权利要求1所述的显示基板，其中，所述阳极与所述第一导电层之间具有第一绝缘层；所述辅助部分通过贯穿所述第一绝缘层的第一过孔与所述阳极转接部电连接；
    所述第一过孔在所述衬底基板的正投影，与所述阳极转接部的与所述有效部交叠的区域在所述衬底基板的正投影互不交叠。
  17. 如权利要求1所述的显示基板，其中，一列中相邻两个所述子像素交叠的所述信号线凸出部的图案不同。
  18. 如权利要求2所述的显示基板，其中，所述第一子像素包括：第一颜色子像素和第三颜色子像素；所述第二子像素包括：第二颜色子像素和第四颜色子像素；
    所述第一颜色子像素为红色子像素，所述第三颜色子像素为蓝色子像素，所述第二颜色子像素和所述第四颜色子像素为绿色子像素。
  19. 如权利要求2所述的显示基板，其中，各所述信号线还包括信号线 凸起部，所述信号线凸出部与所述信号线凸起部为同一结构；所述多条信号线包括第一信号线和第二信号线；其中，一列子像素对应一条所述第一信号线和一条所述第二信号线；所述第一信号线的信号线凸起部分别电连接奇数行子像素，所述第二信号线的信号线凸起部分别电连接偶数行子像素；
    相邻两列子像素对应的两条第一信号线和两条第二信号线中，其中的两条第一信号线相邻形成一个第一信号线组，或者，其中的两条第二信号线相邻形成一个第二信号线组。
  20. 如权利要求1所述的显示基板，其中，至少部分所述子像素的所述有效部在所述第一方向上与相邻的两条所述信号线均具有交叠区域。
  21. 如权利要求20所述的显示基板，其中，所述子像素中，所述有效部与所述第一信号线存在第三交叠区域，所述有效部与所述第二信号线存在第四交叠区域；所述第三交叠区域和所述第四交叠区域位于所述阳极的所述有效部在所述第一方向上的两侧。
  22. 一种显示装置，其中，包括如权利要求1-21任一项所述的显示基板。
PCT/CN2020/112496 2020-08-31 2020-08-31 显示基板及显示装置 WO2022041204A1 (zh)

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CN110690360A (zh) * 2019-09-26 2020-01-14 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN111403452A (zh) * 2020-03-26 2020-07-10 武汉华星光电半导体显示技术有限公司 一种显示面板、显示模组及电子装置

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KR20190077673A (ko) * 2017-12-26 2019-07-04 엘지디스플레이 주식회사 유기 발광 표시 장치
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CN111403452A (zh) * 2020-03-26 2020-07-10 武汉华星光电半导体显示技术有限公司 一种显示面板、显示模组及电子装置

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