WO2023159388A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2023159388A1
WO2023159388A1 PCT/CN2022/077463 CN2022077463W WO2023159388A1 WO 2023159388 A1 WO2023159388 A1 WO 2023159388A1 CN 2022077463 W CN2022077463 W CN 2022077463W WO 2023159388 A1 WO2023159388 A1 WO 2023159388A1
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WIPO (PCT)
Prior art keywords
signal line
sub
power signal
display substrate
pixel
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Application number
PCT/CN2022/077463
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English (en)
French (fr)
Inventor
陈星宇
向炼
卢红婷
任艳萍
杨燕
杨超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000255.0A priority Critical patent/CN117178319A/zh
Priority to PCT/CN2022/077463 priority patent/WO2023159388A1/zh
Priority to CN202210195806.5A priority patent/CN116709807A/zh
Priority to CN202220431588.6U priority patent/CN217562599U/zh
Priority to PCT/CN2023/073673 priority patent/WO2023160329A1/zh
Publication of WO2023159388A1 publication Critical patent/WO2023159388A1/zh

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24—Vacuum evaporation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/824—Cathodes combined with auxiliary electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display technology, in particular to a display substrate, a display panel and a display device.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • advantages such as self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, wide operating temperature range, and flexible display. It is widely used in display field, lighting field and smart wear field.
  • Embodiments of the present application provide a display substrate, a display panel, and a display device.
  • a display substrate includes a display area, and at least part of the display area is a transparent display area; the display substrate includes a base substrate and a plurality of pixels located on the base substrate and in the transparent display area;
  • the pixel includes a plurality of sub-pixels, and the sub-pixels include an organic light emitting element and a pixel circuit for driving the organic light emitting element; the organic light emitting element includes a first electrode, a second electrode, and an electrode located between the first electrode and the second electrode.
  • the display substrate is also provided with a first power signal line and a second power signal line, the pixel circuit is connected to the first power signal line, and the second electrode is connected to the second power signal line;
  • the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction; and/or, the second power signal line includes a sub-power signal line extending along the first direction A third sub-power signal line extending and a fourth sub-power signal line extending along the second direction; the first direction intersects the second direction.
  • the display substrate further includes an overlapping portion electrically connected to the second power signal line, and at least the second electrodes of two adjacent pixels are in contact with the same overlapping portion.
  • the second power signal line when the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, there are at least two adjacent The second electrode of each pixel is electrically connected to the third sub-power signal line through the same overlapping portion, or is electrically connected to the fourth sub-power signal line through the same overlapping portion.
  • the plurality of overlapping parts arranged in the first direction are electrically connected through the third sub-power signal line, and/or, the plurality of overlapping parts arranged in the second direction The two overlapping parts are electrically connected through the fourth sub-power signal line.
  • the display substrate further includes an overlapping portion electrically connected to the second power signal line, and there are at least four adjacent second electrodes of the pixels in contact with the same overlapping portion.
  • the adjacent four pixels are arranged in two rows and two columns.
  • the second power signal line when the second power signal line includes a third sub-power signal line extending along the first direction and a fourth sub-power signal line extending along the second direction, there are at least four adjacent sub-power signal lines
  • the second electrode of each pixel is connected to the third sub-power signal line and the fourth sub-power signal line through the same overlapping portion.
  • the display substrate includes a plurality of overlapping parts, at least one of the overlapping parts and other overlapping parts arranged in the first direction pass through the third sub-section.
  • the power signal line is electrically connected, and is electrically connected with the other overlapping parts arranged in the second direction through the fourth sub-power signal line.
  • the display substrate further includes an electrode connection structure connected to the second electrode, each of the second electrodes in contact with the same overlapping portion is connected to the same electrode connection structure, and the The second electrode is in contact with the overlapping portion through the electrode connection structure.
  • the first power signal line when the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, there are at least two adjacent pixels
  • the pixel circuit is connected to the same first sub-power signal line of the first power signal line, or connected to the same second sub-power signal line.
  • the first power signal line when the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction, at least one of the first sub-power signal lines The line is electrically connected to the pixel circuit through the second sub-power supply signal line;
  • At least some of the second sub-power signal lines are arranged in different layers from the first sub-power signal lines.
  • the display substrate further includes a driving signal line arranged on the same layer as the first sub-power supply signal line, and the driving signal line is configured to provide a driving signal for the pixel circuit; the second The orthographic projection of the portion of the sub-power signal line and the first sub-power signal line arranged in different layers on the base substrate overlaps with the orthographic projection of the driving signal line on the base substrate.
  • the orthographic projection of the first power signal line on the substrate does not overlap with the orthographic projection of the second power signal line on the substrate.
  • the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction
  • the second power signal line includes a sub-power signal line extending along a
  • the first power signal line further includes a plurality of first sub-power signal lines extending in the second direction A connection section
  • the second power signal line further includes a plurality of second connection sections extending along the second direction
  • each of the first sub-power signal lines includes a plurality of sub-power signal lines arranged at intervals in the first direction a first sub-signal segment
  • each of the second sub-power signal lines includes a plurality of second sub-signal segments arranged at intervals in the second direction, each of the first sub-signal segments is connected to at least one of the The second sub-signal segments are connected
  • each of the third sub-power signal lines includes a plurality of third sub-sign
  • the first sub-signal segments adjacent in the second direction are connected through the first connecting segment, and the third sub-signal segments adjacent in the second direction are connected through the second connecting segment connection;
  • the orthographic projection of at least one of the first connection segments on the base substrate is located between the orthographic projections of two adjacent third sub-signal segments on the base substrate;
  • at least one of the The orthographic projection of the second connection segment on the base substrate is located between the orthographic projections of two adjacent first sub-signal segments on the base substrate.
  • the transparent display area includes a light-emitting area and a non-light-emitting area; the pixels are arranged in the light-emitting area;
  • the display substrate is further provided with a plurality of driving signal lines; at least one of the driving signal lines is located in the light-emitting area and has a width greater than that in the non-light-emitting area.
  • the driving signal lines include scanning signal lines configured to provide scanning signals for the pixels;
  • the width of at least one scanning signal line located in the light-emitting area is larger than the width of the non-luminous area; the width of the scanning signal line located in the light-emitting area ranges from 3.5 ⁇ m to 5.5 ⁇ m, The width of the portion of the scanning signal line located in the non-light-emitting area ranges from 2 ⁇ m to 3.5 ⁇ m.
  • the pixel circuit includes a driving transistor, and the display substrate further includes an active semiconductor layer, and the active semiconductor layer includes a channel of the driving transistor of each sub-pixel;
  • the channel of the driving transistor of at least one of the sub-pixels includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment connected in sequence, The first section, the third section and the fifth section extend along the second direction, the second section and the fourth section extend along the first direction; at least The channel of the driving transistor of one sub-pixel includes a sixth section, a seventh section and an eighth section connected in sequence, and the sixth section and the eighth section are along the second direction Extending, the seventh section extends along the first direction.
  • the display substrate further includes a shielding line and a reset power signal line, and the reset power signal line is configured to provide a reset power signal for the sub-pixel; the shielding line and the reset power signal line electrical connection.
  • the transparent display area includes a light-emitting area and a non-light-emitting area, and the pixels are located in the light-emitting area;
  • the display substrate further includes a pixel definition layer, and the pixel definition layer is provided with area openings;
  • the orthographic projection of the opening on the base substrate is at least partially located at the orthographic projection of the second electrode on the base substrate and the orthographic projection of the second power signal line on the base substrate , and the first power signal line is outside the orthographic projection on the base substrate.
  • the display substrate further includes a frame area located on at least one side of the display area, the display substrate further includes auxiliary wiring located in the frame area, and the auxiliary wiring is connected to the second The electrodes are electrically connected; the auxiliary wiring includes a first conductive film layer and a second conductive film layer located on the side of the first conductive film layer away from the base substrate, and the first conductive film layer is on the substrate The edge of the orthographic projection on the base substrate close to the display area is located inside the edge of the orthographic projection of the second conductive film layer on the base substrate close to the edge of the display area.
  • a display panel including the above-mentioned display substrate.
  • a display device including the above-mentioned display panel.
  • the display substrate, display panel, and display device provided by the embodiments of the present application, since the number of the first electrodes is greater than the number of the second electrodes, at least two sub-pixels share one second electrode; In the solution where the electrodes are independently arranged, at least two sub-pixels share a second electrode in the embodiment of the present application, which can reduce the total area of the second electrode in the transparent display area and help to improve the light transmission in the transparent display area of the display substrate. rate; by setting one of the first power signal line and the second power signal line as a grid structure, it is helpful to reduce the voltage drop of the first power signal line and the second power signal line, and improve the display effect of the display substrate Uniformity.
  • FIG. 1 is a schematic circuit diagram of a pixel circuit provided by an exemplary embodiment of the present application
  • FIG. 2 to 7 are partial schematic views of various layers of the display substrate provided by an exemplary embodiment of the present application; wherein, FIG. 3 is a partial enlarged view of FIG. 2;
  • Fig. 8 is a schematic diagram of stacking multiple film layers of a display substrate provided by an exemplary embodiment of the present application.
  • Fig. 9 is a partial schematic diagram of a second conductive layer of a display substrate provided by an exemplary embodiment of the present application.
  • Fig. 10 is a partial schematic diagram of a third conductive layer of a display substrate provided by an exemplary embodiment of the present application.
  • Fig. 11 is a partial schematic diagram of the superposition of the third conductive layer and the fourth conductive layer of the display substrate provided by an exemplary embodiment of the present application;
  • Fig. 12 is a partial schematic diagram of the stacking of multiple film layers of a display substrate provided by an exemplary embodiment of the present application.
  • Fig. 13 is a partial schematic diagram of a second conductive layer of a display substrate provided by another exemplary embodiment of the present application.
  • Fig. 14 is a partial schematic diagram of a third conductive layer of a display substrate provided by another exemplary embodiment of the present application.
  • Fig. 15 is a partial schematic diagram of the superposition of the third conductive layer and the fourth conductive layer of the display substrate provided by another exemplary embodiment of the present application;
  • Fig. 16 is a partial schematic diagram of the stacking of multiple film layers of a display substrate provided by another exemplary embodiment of the present application.
  • Fig. 17 is a partial schematic diagram of superimposing the first power signal line and the second power signal line of the display substrate provided by an exemplary embodiment of the present application;
  • FIG. 18 is a partial schematic diagram of the stacking of multiple film layers of a display substrate provided by an exemplary embodiment of the present application.
  • first, second, third, etc. may be used in this application to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of the present application, first information may also be called second information, and similarly, second information may also be called first information. Depending on the context, the word “if” as used herein may be interpreted as “at” or “when” or “in response to a determination.”
  • Embodiments of the present application provide a display substrate, a display panel, and a display device.
  • the display substrate, display panel, and display device in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the case of no conflict, the features in the following embodiments may complement each other or be combined with each other.
  • Embodiments of the present application provide a display substrate, a display panel, and a display device.
  • the display substrate, display panel, and display device in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the case of no conflict, the features in the following embodiments may complement each other or be combined with each other.
  • the embodiment of the present application provides a display substrate.
  • the display substrate includes a display area, and at least a part of the display area is a transparent display area.
  • the entire area of the display area is a transparent display area, that is, the display substrate is a transparent display substrate.
  • the transparent display area refers to that the display area includes a sub-display area and a light-transmitting area
  • the sub-display area refers to an area provided with pixels
  • the light-transmitting area refers to an area not provided with pixels
  • the sub-display area refers to a The area where the pixel circuit is provided, and the light-transmitting area refer to the area where no pixel circuit is provided.
  • a part of the display area is a transparent display area, and another part of the area is a non-transparent display area.
  • the area where the camera and the light sensor are arranged under the display substrate is a transparent display area, and other areas are non-transparent display areas.
  • the display substrate includes a base substrate and a plurality of pixels located on the base substrate and in the transparent display area.
  • a plurality of pixels are arranged at intervals on the base substrate. It should be noted that, unless otherwise specified, the following descriptions about pixels refer to the pixels in the transparent display area.
  • the pixel includes a plurality of sub-pixels, and the sub-pixels include an organic light-emitting element and a pixel circuit for driving the organic light-emitting element; the organic light-emitting element includes a first electrode, a second electrode, and a An organic light-emitting material between the second electrodes.
  • the first electrode of the sub-pixel is electrically connected to the pixel circuit.
  • the first electrode may be an anode
  • the second electrode may be a cathode
  • the first electrode is located on the side where the luminescent material is close to the substrate
  • the second electrode is located on the side where the luminescent material is away from the substrate.
  • Each pixel may include three sub-pixels with different light emitting colors, for example, may include red sub-pixels, green sub-pixels and blue sub-pixels.
  • the display substrate further includes a pixel defining layer, and the pixel defining layer is provided with pixel openings corresponding to the sub-pixels one by one.
  • the pixel opening is used to define the light emitting area of each sub-pixel.
  • the organic luminescent material is located on a side of the first electrode away from the base substrate.
  • the first electrode of each sub-pixel is in contact with the organic luminescent material at the pixel opening of the pixel defining layer, and the pixel opening of the pixel defining layer defines the shape of the light emitting area of the sub-pixel.
  • the first electrode (for example, anode) of the organic light-emitting element can be arranged below the pixel defining layer, and the pixel opening of the pixel defining layer exposes a part of the first electrode.
  • the organic luminescent material is in contact with the first electrode, so that this part of the first electrode can drive the organic luminescent material to emit light.
  • the orthographic projection of the pixel opening of the pixel defining layer on the substrate is located within the orthographic projection of the corresponding organic luminescent material on the substrate, that is, the organic luminescent material covers the pixel opening of the pixel defining layer.
  • the area of the organic luminescent material is larger than the area of the corresponding pixel opening, that is, the organic luminescent material includes at least a portion covering the physical structure of the pixel defining layer, in addition to the part inside the pixel opening, usually at each boundary of the pixel opening.
  • the physical structure of the pixel defining layer is covered with organic luminescent material.
  • the above description of the pattern of the organic light-emitting material is based on the patterned organic light-emitting material of each sub-pixel formed by the FMM process.
  • the FMM process there are also some organic light-emitting materials that use the open mask process on the entire display.
  • the area forms an integral film layer, and the orthographic projection of its shape on the substrate is continuous, so there must be a part located in the pixel opening and a part located on the physical structure of the pixel defining layer.
  • the number of the first electrodes is greater than the number of the second electrodes.
  • the display substrate is also provided with a first power signal line and a second power signal line, the pixel circuit is connected to the first power signal line, and the second electrode is connected to the second power signal line;
  • the first power signal line includes a first sub-power signal line extending along a first direction and a second sub-power signal line extending along a second direction; and/or, the second power signal line includes a sub-power signal line extending along the first direction A third sub-power signal line extending and a fourth sub-power signal line extending along the second direction; the first direction intersects the second direction.
  • the display substrate since the number of the first electrodes is greater than the number of the second electrodes, at least two sub-pixels share one second electrode; if the second electrodes of each sub-pixel are independently set, each second electrode The two electrodes need to have a larger area in order to overlap with the second power supply signal line.
  • at least two sub-pixels share one second electrode, which can reduce the total area of the second electrode in the transparent display area, which is helpful It is used to improve the light transmittance of the transparent display area of the display substrate.
  • By setting one of the first power signal line and the second power signal line as a grid structure it is helpful to reduce the voltage drop of the first power signal line and the second power signal line, and improve the uniformity of the display effect of the display substrate .
  • each sub-pixel of the pixel may share one second electrode.
  • a pixel includes a red sub-pixel, a green sub-pixel and a blue sub-pixel
  • the red sub-pixel, the green sub-pixel and the blue sub-pixel in the same pixel share one second electrode.
  • the area between adjacent pixels is not provided with the second electrode, so as to ensure the light transmittance of the display substrate.
  • the first power signal line may be a high-level power signal line
  • the second power signal line may be a low-level power signal line
  • the first direction is a column direction and the second direction is a row direction.
  • the pixel circuits of the sub-pixels in each pixel are arranged at intervals along the second direction.
  • the transparent display area of the display substrate includes a light-emitting area and a non-light-emitting area.
  • the area outside the light-emitting area is a non-light-emitting area.
  • the pixels are located in the light-emitting area.
  • the fact that the pixel is located in the light-emitting area means that the pixel circuit, the first electrode, the organic light-emitting material and part of the second electrode of the pixel are located in the light-emitting area.
  • the area covered by the orthographic projection of the pixel circuit of the sub-pixel on the base substrate is roughly located within a rectangular frame.
  • the orthographic projection of the pixel circuit on the base substrate mainly includes the orthographic projection of the structures of elements such as transistors and capacitors on the base substrate.
  • the display substrate also includes a plurality of signal lines for driving the pixel circuits. It should be noted that some signal lines include a part inside the rectangular frame and a part extending out of the rectangular frame.
  • the pixel circuit 221 includes a driving circuit 222 .
  • the driving circuit 222 includes a control terminal, a first terminal and a second terminal, and is configured to provide a driving current to the organic light emitting element 220 to drive the organic light emitting element 220 to emit light.
  • the pixel circuit 221 includes a first light emission control circuit 223 and a second light emission control circuit 224 .
  • the first light emission control circuit 223 is connected to the first terminal of the driving circuit 222 and the first voltage terminal VDD, and is configured to enable or disable the connection between the driving circuit 222 and the first voltage terminal VDD
  • the second The light emission control circuit 224 is electrically connected to the second terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220 , and is configured to enable or disable the connection between the driving circuit 222 and the organic light emitting element 220 .
  • the pixel circuit 221 further includes a data writing circuit 226 , a storage circuit 227 , a threshold compensation circuit 228 and a reset circuit 229 .
  • the data writing circuit 226 is electrically connected to the first terminal of the driving circuit 222 and is configured to write data signals into the storage circuit 227 under the control of the scan signal.
  • the storage circuit 227 is electrically connected to the control terminal of the driving circuit 222 and the first voltage terminal VDD, and is configured to store data signals.
  • the threshold compensation circuit 228 is electrically connected to the control terminal and the second terminal of the driving circuit 222 and is configured to perform threshold compensation on the driving circuit 222 .
  • the reset circuit 229 is electrically connected to the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220, and is configured to reset the control terminal of the driving circuit 222 and the first electrode of the organic light emitting element 220 under the control of the reset control signal .
  • the driving circuit 222 includes a driving transistor T1
  • the control terminal of the driving circuit 222 includes the gate of the driving transistor T1
  • the first end of the driving circuit 222 includes a first pole of the driving transistor T1
  • the second end of the driving circuit 222 includes a second pole of the driving transistor T1.
  • the data writing circuit 226 includes a data writing transistor T2
  • the storage circuit 227 includes a capacitor C
  • the threshold compensation circuit 228 includes a threshold compensation transistor T3
  • the first light emission control circuit 223 includes a first
  • the light emission control transistor T4 the second light emission control circuit 224 includes a second light emission control transistor T5
  • the reset circuit 229 includes a first reset transistor T6 and a second reset transistor T7
  • the reset control signal may include a first sub reset control signal and a second sub reset control signal. Reset control signal.
  • the first pole of the data writing transistor T2 is electrically connected to the first pole of the driving transistor T1
  • the second pole of the data writing transistor T2 is configured to be electrically connected to the data line Vd
  • the gate of the data writing transistor T2 is configured to be electrically connected to the scanning signal line Ga1 to receive the scanning signal
  • the first pole of the capacitor C is electrically connected to the first power supply terminal VDD
  • the second pole of the capacitor C is electrically connected to the first power supply terminal VDD.
  • the gate of the driving transistor T1 is electrically connected; the first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the driving transistor T1, the second pole of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the threshold compensation transistor T3
  • the gate of the first reset transistor T6 is configured to be electrically connected to the scanning signal line Ga2 to receive the compensation control signal; the first pole of the first reset transistor T6 is configured to be electrically connected to the reset power supply terminal Vinit1 to receive the first reset signal, and the first reset transistor T6
  • the second pole of the drive transistor T1 is electrically connected to the gate of the first reset transistor T6, and the gate of the first reset transistor T6 is configured to be electrically connected to the reset control signal line Rst1 to receive the first sub-reset control signal; the first sub-reset control signal of the second reset transistor T7
  • the electrode is configured to be electrically connected to the reset power supply terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is
  • one of the first power supply terminal VDD and the second power supply terminal vss is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; and the second power supply terminal VSS can be a voltage source to output a constant second voltage, The second voltage is a negative voltage or the like.
  • the second power supply terminal vss may be grounded.
  • the scan signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can be electrically connected to the same signal line, such as scan
  • the signal line Ga1 is used to receive the same signal (for example, a scanning signal).
  • the display substrate may not be provided with the scanning signal line Ga2 to reduce the number of signal lines.
  • the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 may also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the scanning signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the scanning signal line Ga1.
  • the gate of T3 is electrically connected to the scanning signal line Ga2, and the signals transmitted by the scanning signal line Ga1 and the scanning signal line Ga2 are the same.
  • the scanning signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately, increasing the flexibility of controlling the pixel circuit.
  • the first light emission control signal and the second light emission control signal may be the same, that is, the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may be electrically connected To the same signal line, such as the light emission control signal line EM1, to receive the same signal (for example, the first light emission control signal), at this time, the display substrate may not be provided with the light emission control signal line EM2 to reduce the number of signal lines.
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 may also be electrically connected to different signal lines, that is, the gate of the first light emission control transistor T4 is electrically connected to The light emission control signal line EM1 and the gate of the second light emission control transistor T5 are electrically connected to the light emission control signal line EM2, and the light emission control signal line EM1 and the light emission control signal line EM2 transmit the same signal.
  • first light emission control transistor T4 and the second light emission control transistor T5 are transistors of different types, for example, the first light emission control transistor T4 is a P-type transistor, and the second light emission control transistor T5 is an N-type transistor.
  • the first light emission control signal and the second light emission control signal may also be different, which is not limited in this embodiment of the present application.
  • the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line,
  • the reset control signal line Rst1 receives the same signal (eg, the first sub-reset control signal).
  • the display substrate may not be provided with the reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the reset control signal line Rst1.
  • the gate of the second reset transistor T7 is electrically connected to the reset control signal line Rst2, and the signals transmitted by the reset control signal line Rst1 and the reset control signal line Rst2 are the same.
  • the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the first sub-reset control signal is different from the second sub-reset control signal
  • the pulse width of the reset control signal line Rst2 is greater than the pulse width of the reset control signal line Rst1
  • the pulse width of the reset control signal line Rst2 is smaller than
  • the pulse width of the light emission control signal line EM2 is controlled when the second light emission control transistor T5 is turned off. This helps to improve the lifetime of the organic light emitting element of the sub-pixel.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.
  • the gate of the first reset transistor T6 and the source of the second reset transistor T7 are respectively connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2, and the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit1
  • the power terminal Vinit2 can be a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same, for example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide the first reset signal and the second reset signal to drive the gate of the transistor T1 and the light-emitting element 220. It only needs to reset the first electrode, which is not limited in the present application.
  • the specific structures of circuits such as 226, storage circuit 227, threshold compensation circuit 228, and reset circuit 229 can be set according to actual application requirements, and are not specifically limited in this embodiment of the present application.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present application take the transistors as P-type transistors (for example, P-type MOS transistors) as an example to elaborate on the technical solutions of the present application. That is to say, in the description of this application, the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T6 Transistors T7 and the like can all be P-type transistors.
  • the transistors in the embodiments of the present application are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to realize the functions of one or more transistors in the embodiments of the present application according to actual needs. .
  • the transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor can be symmetrical in structure, so there can be no difference in the physical structure of the source and drain.
  • the transistors except for the gate as the control electrode, it is directly described that one of them is the first pole and the other is the second pole, so the first pole of all or part of the transistors in the embodiments of the present application
  • the first and second poles are interchangeable as desired.
  • the pixel circuit of the sub-pixel can also be a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, which is not limited in this embodiment of the present application.
  • FIGS. 2-7 are schematic views of various layers of a display substrate provided by an embodiment of the present application
  • FIG. 8 is a schematic view of partial layer stacking of a display substrate.
  • the following describes the positional relationship of each circuit in the pixel circuit and the signal line on the backplane in conjunction with Figures 2-8.
  • the example shown in Figures 2-8 takes the pixel circuit 221 of one pixel as an example, and the sub-pixel 110 includes The position of each transistor of the pixel circuit is schematically shown, and the components included in the pixel circuit in the sub-pixel 120 and the sub-pixel 130 are approximately the same as the positions of the transistors included in the sub-pixel 110 . It can be seen from Fig.
  • the pixel circuit 221 of the sub-pixel 110 includes the drive transistor T1 shown in FIG. The reset transistor T6, the second reset transistor T7 and the capacitor C.
  • 2-8 also show the scanning signal line Ga1, reset control signal line Rst1, reset power signal line Init1, light emission control signal line EM1, data line Vd, and The second sub-power signal line VDD12 of the first power signal line VDD1 connected to the first power terminal VDD, the second power signal line VSS connected to the second power terminal vss, and the shielding line 344 .
  • 2-7 also shows the third power signal line VDD2, the fourth power signal line VDD3 and the fifth power signal line VDD4, the third power signal line VDD2, the fourth power signal line VDD3 and the fifth power signal line VDD4 respectively It is electrically connected with the first power signal line VDD1.
  • the scanning signal line Ga1 is configured to provide a scanning signal for the pixel; the reset control signal line Rst1 and the reset control signal line Rst2 are configured to provide a reset control signal for the pixel; the reset power signal line Init1 is configured to provide a reset power signal for the pixel;
  • the control signal line EM1 is configured to provide light emission control signals for the pixels; the data line Vd is configured to provide light emission data signals for the pixels; the first power signal line VDD1 and the second power signal line VSS are configured to provide power signals for the pixels.
  • FIG. 2 shows the active semiconductor layer 310 of the pixel circuit in the display substrate.
  • the active semiconductor layer 310 can be formed by patterning a semiconductor material.
  • the active semiconductor layer 310 can be used to make the above-mentioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6 and second reset transistor T7 channel.
  • the active semiconductor layer 310 includes the channel and the source-drain region of each transistor of each sub-pixel (that is, the source region s and the drain region d shown in the sub-pixel 120), and the channel of each transistor in the same pixel circuit It is set integrally with the source and drain regions.
  • the active semiconductor layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region therein may be conductiveized by doping or the like to realize electrical connection of various structures. That is to say, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed by p-silicon, and each transistor in the same pixel circuit includes a source-drain region (that is, a source region s and a drain region d) and a channel , the channels of different transistors are separated by source and drain regions.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of different colors arranged along the second direction are not connected and are disconnected from each other.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of the same color arranged along the first direction may be integrally arranged, or may be disconnected from each other.
  • the channels 31 and 32 of the driving transistor T1 of at least one of the sub-pixels include sequentially connected first section 301 , second section 302 , third section Section 303, fourth section 304 and fifth section 305, the first section 301, the third section 303 and the fifth section 305 extend along the second direction Y, the first The second section 302 and the fourth section 304 extend along the first direction X;
  • the channel 33 of the driving transistor T1 of at least one sub-pixel includes a sixth section 306 and a seventh section connected in sequence 307 and an eighth section 308 , the sixth section 306 and the eighth section 308 extend along the second direction Y, and the seventh section 307 extends along the first direction X.
  • the width-to-length ratio of the channel 33 is greater than the width-to-length ratio of the channels 31 and 32 .
  • the channel 31 and the channel 32 may be channels of a red sub-pixel and a green sub-pixel, and the channel 33 may be a channel of a blue sub-pixel.
  • the driving transistor T1 of the sub-pixel includes a first source-drain region 311 and a second source-drain region 312, and the first source-drain region of at least one driving transistor T1 of the sub-pixel
  • the lengths of the first source and drain regions 311 and the second source and drain regions 312 are different, and one of the first source and drain regions 311 and the second source and drain regions 312 is a source region, and the other is a drain region.
  • the first source-drain region 311 is connected to the first segment 301, and the second source-drain region 312 is connected to the fifth segment 305; the driving transistor T1 where the channel 33 is located Among them, the first source and drain region 311 is connected to the sixth segment 306 , and the second source and drain region 312 is connected to the eighth segment 308 .
  • the signal writing of the pixel circuit can be optimized, and the light-shielding design for the channel can be optimized.
  • the lengths of the first source-drain region 311 and the second source-drain region 312 are different.
  • the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer.
  • a gate insulating layer is formed on the above-mentioned active semiconductor layer 310 for protecting the above-mentioned active semiconductor layer 310 , and the active semiconductor layer 310 is located on the base substrate 100 .
  • FIG. 4 shows the first conductive layer 320 included in the display substrate, and the first conductive layer 320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 310 .
  • the first conductive layer 320 may include the second plate CC2 of the capacitor C, the scanning signal line Ga1, the reset control signal line Rst1, the light emission control signal line EM1, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first Gates of the light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7.
  • the scanning signal line Ga1 includes a scanning signal line body portion Ga11 and a protruding portion P protruding from one side of the scanning signal line body portion Ga11 .
  • the gate of the data writing transistor T2 can be the overlapping part of the scanning signal line Ga1 and the active semiconductor layer 310;
  • the first part where the active semiconductor layer 310 overlaps, the gate of the second light emission control transistor T5 can be the second part where the light emission control signal line EM1 overlaps the active semiconductor layer 310;
  • the gate of the first reset transistor T6 is the reset control
  • the first part where the signal line Rst1 overlaps with the active semiconductor layer 310, the gate of the second reset transistor T7 is the second part where the reset control signal line Rst1 overlaps with the active semiconductor layer 310;
  • the threshold compensation transistor T3 can be a double-gate structure
  • the first gate of the threshold compensation transistor T3 can be the overlapping part of the scanning signal line Ga1 and the active semiconductor layer 310, and the second gate of the threshold compensation transistor T3 can be the protruding part of the scanning signal line Ga1 P overlaps the active semiconductor layer 310 .
  • the gate of the driving transistor T1 can be the overlapping part of the scanning
  • each dotted rectangular box in FIG. 2 shows each portion where the first conductive layer 320 overlaps with the active semiconductor layer 310 .
  • the scanning signal line Ga1, the reset control signal line Rst1 and the light emission control signal line EM1 are arranged along the first direction X
  • the scanning signal line Ga1, the reset control signal line Rst1 and the light emission control signal line EM1 are arranged along the first direction X.
  • Two directions Y extend.
  • the extension of the signal line along the second direction means that the entire row of signal lines extends along the second direction, and the area of the part of the signal line extending in the second direction is much larger than the area of the part extending in the second direction;
  • Extending in the first direction means that the entire row of signal lines extends along the first direction, and the area of the portion of the signal line extending in the first direction is much larger than the area of the portion extending in the second direction.
  • the second plate CC2 of the capacitor C (ie, the gate of the driving transistor T1 ) is located between the scanning signal line Ga1 and the light emission control signal line EM1 .
  • the protrusion P of the scanning signal line Ga1 is located on a side of the scanning signal line Ga1 away from the emission control signal line EM1 .
  • the gate of the data write transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all Located on the first side of the gate of the driving transistor T1, the gates of the first light emitting control transistor T4 and the second light emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the first side and the second side of the gate of the driving transistor T1 of the pixel circuit of the first color sub-pixel are opposite to each other in the first direction X of the gate of the driving transistor T1 opposite sides.
  • the first side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel 110 may be the upper side of the gate of the driving transistor T1, and the pixel circuit of the sub-pixel 110
  • the second side of the gate of the driving transistor T1 may be the lower side of the gate of the driving transistor T1.
  • the lower side for example, the side of the display substrate for binding the driving chip is the lower side of the display substrate, and the lower side of the gate of the driving transistor T1 is the side closer to the driving chip of the gate of the driving transistor T1 .
  • the upper side is the side opposite to the lower side, for example, the side of the gate of the driving transistor T1 that is farther away from the driving chip.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1.
  • the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel 110 are opposite to each other in the second direction Y of the gate of the driving transistor T1. sides. For example, as shown in FIG.
  • the third side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel 110 may be the left side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel 110, and the gate of the sub-pixel 110
  • the fourth side of the gate of the driving transistor T1 of the pixel circuit may be the right side of the gate of the driving transistor T1 of the pixel circuit of the sub-pixel 110 .
  • the left side and the right side for example, in the same pixel circuit, the data line is on the left side of the first power signal line VDD1, and the first power signal line VDD1 is on the right side of the data line.
  • FIG. 5 shows the second conductive layer 330 of the pixel circuit.
  • the second conductive layer 330 includes the first plate CC1 of the capacitor C, the reset power signal line Init1 and the third power signal line VDD2 .
  • the third power signal line VDD2 is integrally formed with the first plate CC1 of the capacitor C.
  • the first plate CC1 of the capacitor C and the second plate CC2 of the capacitor C at least partially overlap to form the capacitor C.
  • FIG. 6 shows the source-drain metal layer 340 of the pixel circuit.
  • the source-drain metal layer 340 includes a data line Vd, a fourth power signal line VDD3 and a shielding line 344 .
  • the data line Vd, the fourth power signal line VDD3 and the shielding line 344 all extend along the first direction X.
  • the source-drain metal layer 340 further includes a connection structure 341 , a connection portion 342 and a first sub-electrode connection structure 343 of the electrode connection portion.
  • One end of the connection structure 341 is connected to the gate of the driving transistor T1, and the other end of the connection structure 341 is connected to the source and drain regions of the threshold compensation transistor T3.
  • FIG. 6 also shows exemplary positions of a plurality of via holes, through which the source-drain metal layer 340 is connected to a plurality of film layers located between the source-drain metal layer 340 and the substrate.
  • the source-drain metal layer 340 is connected to the active semiconductor layer 310 shown in FIG.
  • the vias 386 , 385 , and 332 are connected to the second conductive layer 330 shown in FIG. 5 .
  • a third insulating layer and a fourth insulating layer are formed on the above-mentioned source-drain metal layer 340 for protecting the above-mentioned source-drain metal layer 340 .
  • the organic light emitting element of each sub-pixel can be disposed on a side of the third insulating layer and the fourth insulating layer away from the base substrate.
  • FIG. 7 shows the third conductive layer 350 of the pixel circuit
  • the third conductive layer 350 includes the second sub-electrode connection structure 353 of the electrode connection part, the second sub-power supply of the first power signal line VDD1 extending along the second direction
  • the signal line VDD12 and the fifth power signal line VDD4 extending along the first direction X
  • the second sub-power signal line VDD12 cross each fifth power signal line VDD4.
  • the specific structure of the first power signal line VDD1 will be introduced later in the related description of FIG. 9 to FIG. 16 .
  • FIG. 7 also shows exemplary positions of a plurality of via holes 351 and a via hole 354 , through which the third conductive layer 350 is connected to the source-drain metal layer 340 .
  • FIG. 8 is a schematic view showing the stacked positional relationship of the above-mentioned active semiconductor layer 310 , the first conductive layer 320 , the second conductive layer 330 , the source-drain metal layer 340 and the third conductive layer 350 .
  • the data line Vd communicates with the data writing in the active semiconductor layer 310 through at least one via hole (for example, via hole 381) in the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the source regions of transistor T2 are connected.
  • the fourth power signal line VDD3 is connected to the corresponding first light emission control transistor T4 in the active semiconductor layer 310 through at least one via hole (for example, the via hole 382) in the gate insulating layer, the first insulating layer and the second insulating layer.
  • the source region is connected.
  • connection structure 341 is connected to the corresponding one of the active semiconductor layer 310 through at least one via hole (for example, via hole 384 ) in the gate insulating layer, the first insulating layer, and the second insulating layer.
  • the drain region of the threshold compensation transistor T3 is connected, and the other end of the connection structure 341 is connected to the driving transistor T1 in the first conductive layer 320 through at least one via hole (for example, the via hole 385) in the first insulating layer and the second insulating layer.
  • the gate that is, the second plate CC2 of the capacitor C) is connected.
  • One end of the connecting part 342 is connected to the reset power signal line Init1 through a via hole (for example, via hole 386) in the second insulating layer, and the other end of the connecting part 342 is connected through the gate insulating layer, the first insulating layer and the second insulating layer.
  • At least one via in the layer (for example, the via 387 ) is connected to the drain region of the second reset transistor T7 in the active semiconductor layer 310 .
  • the first sub-electrode connection structure 343 is connected to the second light emission control transistor T5 in the active semiconductor layer 310 through at least one via hole (for example, the via hole 352) in the gate insulating layer, the first insulating layer, and the second insulating layer. connected to the drain region.
  • the source region and the drain region of the transistor used in the embodiment of the present application may be structurally the same, so there may be no structural difference between the source region and the drain region, so as required The two are interchangeable.
  • the fourth power signal line VDD3 communicates with at least one via hole (for example, via hole 3832) in the second insulating layer between the second conductive layer 330 and the source-drain metal layer 340.
  • the first plate CC1 of the capacitor C in the second conductive layer 330 is connected.
  • the shielding line 344 extends along the first direction X, and its orthographic projection on the substrate is located between the orthographic projections of the corresponding data lines of two adjacent pixels on the substrate.
  • the shielding line can reduce the influence of the signals transmitted on the corresponding data lines of two adjacent pixels on the performance of the threshold compensation transistor T3 and reduce the crosstalk problem.
  • the shielding wire 344 is connected to the reset power signal line Init1 through at least one via hole (for example, the via hole 332) in the second insulating layer.
  • the shielding wire In addition to making the shielding wire have a fixed potential, it also makes the The voltage of the initialization signal transmitted on the reset power signal line is more stable, which is more conducive to the working performance of the pixel driving circuit.
  • the shielding line 344 is electrically connected to the reset power signal line, so that the shielding line has a fixed potential.
  • the shielding line 344 can be respectively electrically connected to two reset power signal lines Init1 extending along the Y direction, and the two reset power signal lines Init1 are respectively located on two sides of the shielding line 344 along the X direction.
  • the two reset power signal lines correspond to the nth row of pixel circuits and the n+1th row of pixel circuits respectively.
  • the shielding line 344 in the same column can be a whole shielding line, and the whole shielding line includes a plurality of sub-parts located between two adjacent reset power signal lines, and each sub-part is respectively located in each row of the column. within the pixel circuit area. Pixels in the same row can share one shielding line 344 .
  • the shielding line 344 can also be coupled to the first power signal line, so that the shielding line 344 has the same fixed potential as the power signal transmitted by the first power signal line .
  • the fifth power signal line VDD4 is connected to the fourth power signal line VDD3 through at least one via 351 in the third insulating layer and the fourth insulating layer, and the second sub-electrode connection structure 353 passes through The via holes 354 in the third insulating layer and the fourth insulating layer are connected to the first sub-electrode connection structure 343 .
  • the third insulating layer may be a passivation layer
  • the fourth insulating layer may be a planarization layer
  • the third insulating layer is located between the fourth insulating layer and the base substrate.
  • the fourth insulating layer may be an organic layer, and the organic layer is thicker than the passivation layer and other inorganic layers.
  • both the via hole 351 and the via hole 354 are nested via holes, that is, the via hole 351 includes a first via hole in the third insulating layer and a second via hole in the fourth insulating layer, and the second via hole in the third insulating layer A via hole is opposite to the position of the second via hole in the fourth insulating layer, and the orthographic projection of the second via hole in the fourth insulating layer on the base substrate is located on the substrate of the first via hole in the third insulating layer. Inside the orthographic projection on the base substrate.
  • the orthographic projection of the fifth power signal line VDD4 on the base substrate approximately coincides with the orthographic projection of the fourth power signal line VDD3 on the base substrate, or the orthographic projection of the fourth power signal line VDD3 on the base substrate is located at In the orthographic projection of the fifth power signal line VDD4 on the base substrate, and the electrical connection between the fifth power signal line VDD4 and the fourth power signal line VDD3 can reduce the voltage drop of the first power signal line VDD1, thereby improving the uniformity of the display device.
  • the fifth power signal line VDD4 can be made of the same material as the source-drain metal layer.
  • the first sub-electrode connection structures 343 of each sub-pixel are block structures.
  • the first electrode of each color sub-pixel formed subsequently will be connected to the corresponding second sub-electrode connection structure 353 through a via hole so as to be connected to the drain region of the second light emission control transistor T5.
  • This embodiment includes but is not limited thereto.
  • the position of the second sub-electrode connection structure in each sub-pixel is determined according to the arrangement rule of the organic light-emitting elements and the position of the light-emitting region.
  • the first sub-electrode connection structure 343 of the sub-pixel is connected to the second electrode T5d of the second light emission control transistor T5 in the active semiconductor layer through the gate insulating layer, the first insulating layer and the via hole 352 of the second insulating layer. .
  • the first sub-electrode connection structure 343 overlaps both the third power signal line VDD2 and the light emission control signal line EM1 .
  • the second sub-electrode connection structure 353 is connected to the first sub-electrode connection structure 343 through the nested via hole 354 located in the third insulating layer and the fourth insulating layer, and then is connected to the second light emission control transistor.
  • the data line Vd is connected to the source electrode T2s of the data writing transistor T2 through the via hole 381 in the gate insulating layer, the first insulating layer and the second insulating layer; one end of the connection structure 341 is connected through the gate insulating layer, the first insulating layer
  • the via hole 384 in the insulating layer and the second insulating layer is connected to the drain T3d of the threshold compensation transistor T3, and the other end of the connection structure 341 is connected to the gate of the driving transistor T1 through the via hole 385 in the first insulating layer and the second insulating layer.
  • the channel T1c of the driving transistor T1 is located on the side of the gate facing the substrate, and does not overlap with the via hole 385; the source T1d of the driving transistor T1 is connected to the Both the grid and the first plate CC1 of the capacitor C overlap.
  • the arrangement relationship of the drive circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit in each pixel circuit is not limited to that shown in Fig. 2 In the example shown in -8, the positions of the drive circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit can be specifically set according to actual application requirements.
  • the first electrode of the sub-pixel 110 is connected to the second sub-electrode connection structure 353 through a via hole (not shown) in the fifth insulating layer, so as to be connected to the drain region of the second light emission control transistor T5.
  • the first power signal line VDD1 includes a first sub-power signal line VDD1 extending along a first direction X and a second sub-power signal line VDD12 extending along a second direction Y.
  • the second power signal line VSS includes a third sub power signal line VSS1 extending along the first direction X and a fourth sub power signal line VSS2 extending along the second direction Y.
  • the second sub-power signal line VDD12 includes a first connection signal line VDD13 and a second connection signal line VDD14 .
  • the first connection signal line VDD13 is located on the same layer as the first sub-power supply signal line VDD11 , and is connected to the first sub-power supply signal line VDD11 .
  • the first sub-power signal segment VDD11 and the first connection signal line VDD13 can be located at the source-drain metal layer 340 .
  • the second connection signal line VDD14 is located on a different layer from the first connection signal line VDD13 .
  • the second connection signal line VDD14 may be located on the third conductive layer 350 .
  • the second connection signal line VDD14 intersects with the fifth power supply signal line VDD4, and the second connection signal line VDD14 connects with the first connection signal line through the through holes of the third insulating layer and the fourth insulating layer.
  • Line VDD13 is connected.
  • the third sub-power signal line VSS1 and the fourth sub-power signal line VSS2 of the second power signal line VSS intersect and can be located on the same layer.
  • the third sub-power signal line VSS1 and the fourth sub-power signal line VSS2 can be located on the third conductive line.
  • the display substrate further includes an overlapping portion 40 connected to the second power signal line VSS.
  • the overlapping portion 40 can be disposed on the same layer as the second power signal line VSS.
  • the sub-pixels include a first electrode 21 and a second electrode 22 , and each sub-pixel in the same pixel shares one second electrode 22 .
  • the display substrate may further include a pixel defining layer, and the pixel defining layer is provided with a plurality of pixel openings 23 . Both the first electrode 21 and the pixel opening 23 are located in the light emitting area AA1.
  • Each sub-pixel corresponds to a pixel opening, and the orthographic projection of the pixel opening 23 of the sub-pixel on the substrate is located within the orthographic projection of the first electrode 21 on the substrate.
  • the second electrodes 22 of two adjacent pixels are in contact with the same overlapping portion 40 .
  • the second electrode being in contact with the overlapping portion means that the second electrode is in contact with the overlapping portion through the contact hole of the insulating layer between the second electrode and the overlapping portion.
  • the second electrodes 22 of two adjacent pixels are in contact with the same bonding portion 40 to realize the electrical connection with the second power signal line VSS, and the second electrodes of each pixel are respectively contacted through different bonding portions.
  • the number of overlapping parts and contact holes can be reduced, and the light transmittance of the display substrate can be improved; and in the scheme where the second electrode of each pixel passes through the same overlapping part and the second power signal line, each pixel
  • the second electrodes of each need to be set larger so as to overlap and contact with the overlapping portion 40 in the stacking direction of the film layer.
  • Contact can reduce the total area of the second electrode in the display substrate, which helps to improve the light transmittance of the display substrate; and this embodiment can reduce the number of sub-power signal lines of the second power signal line VSS, which also helps Improve the light transmittance of the display substrate.
  • the second electrodes 22 of at least two adjacent pixels are electrically connected to the third sub-power signal line VSS1 through the same overlapping portion 40, or connected to the third sub-power signal line VSS1 through the same overlapping portion 40.
  • the fourth sub power signal line VSS2 is electrically connected.
  • the second electrodes 22 of two adjacent pixels are electrically connected to the same fourth sub-power signal line VSS2 through the same overlapping portion 40 .
  • the second electrodes 22 of two adjacent pixels may be electrically connected to the same third sub-power signal line VSS1 through the same overlapping portion 40 .
  • the plurality of pixels arranged at intervals in the second direction Y is a row of pixels
  • the plurality of pixels arranged at intervals in the first direction X is a row of pixels.
  • the second electrodes of two adjacent rows of sub-pixels may be respectively connected to the same fourth sub-power signal line VSS2 through overlapping portions. Specifically, among two adjacent rows of pixels, the second electrodes of the two adjacent pixels in the first direction X are in contact with the same overlapping portion 40 . With such an arrangement, compared with the solution of the second electrodes of pixels in different rows and different fourth sub-power signal lines VSS2 , the number of the fourth sub-power signal lines VSS2 can be reduced by half.
  • a plurality of overlapping portions 40 arranged at intervals in the second direction Y are provided between two adjacent rows of sub-pixels, and the plurality of overlapping portions 40 arranged in the second direction Y are electrically connected through the fourth sub-power supply signal line VSS2.
  • the second electrodes of two adjacent columns of pixels may be respectively connected to the same third sub-power supply signal line VSS1 through overlapping portions. Specifically, in two adjacent columns of sub-pixels, the second electrodes of two adjacent sub-pixels in the second direction Y are in contact with the same overlapping portion 40 . With such an arrangement, compared with the solution of the second electrodes of pixels in different columns and different third sub-power signal lines VSS1 , the number of the third sub-power signal lines VSS1 can be reduced by half.
  • a plurality of overlapping portions 40 arranged at intervals in the first direction X are provided between two adjacent columns of pixels, and the plurality of overlapping portions 40 arranged in the first direction X
  • the unit 40 is electrically connected through the third sub-power supply signal line VSS1.
  • the adjacent pixels are arranged in two rows and two columns.
  • the total area of the second electrodes of the display substrate is smaller, and the number of overlapping parts 40 is less, and the number of sub-power signal lines of the second power signal line VSS is less, so it is more helpful to improve the performance of the display substrate. Transmittance.
  • the orthographic projection of the overlapping portion 40 on the base substrate is located between the orthographic projections of the second electrodes 22 of four adjacent pixels on the base substrate.
  • At least the second electrodes 22 of four adjacent pixels are connected to the third sub-power supply signal line VSS1 and the fourth sub-power supply signal line through the same overlapping portion 40 .
  • the four adjacent pixels are arranged in two rows and two columns, a fourth sub-power supply signal line VSS2 is provided between the two rows of pixels, and a third sub-power supply signal line VSS1 is provided between the two columns of pixels.
  • the portion 40 is located between four pixels, so the bridge portion 40 is connected to both the third sub-power signal line VSS1 and the fourth sub-power signal line VSS2.
  • At least one overlapping portion 40 is electrically connected to other overlapping portions arranged in the first direction X through the third sub-power signal line VSS1, and is connected to the second sub-power signal line VSS1.
  • the other overlapping parts arranged in the direction Y are connected through the fourth sub-power signal line VSS2.
  • the display substrate includes a plurality of overlapping portions 40 , each overlapping portion 40 is respectively in contact with the second electrodes of four adjacent pixels, and the plurality of overlapping portions 40 are arranged in multiple rows and columns.
  • a plurality of overlapping parts 40 arranged at intervals in the first direction X are connected through the third sub-power supply signal line VSS1, and a plurality of overlapping parts 40 arranged in the second direction Y are connected through the fourth sub-power supply The signal line VSS2 is connected.
  • the display substrate further includes an electrode connection structure 24 connected to the second electrode 22 , each of the second electrodes in contact with the same overlapping portion 40
  • the electrode 22 is connected to the same electrode connection structure 24 , and the second electrode 22 is in contact with the overlapping portion 40 through the electrode connection structure 24 .
  • the electrode connection structures 24 corresponding to the plurality of second electrodes 22 in contact with the same overlapping portion 40 are located between the plurality of second electrodes 22, so that the electrode connection structures 24 are connected to each second electrode 22.
  • the electrode connection structure 24 and the second electrode 22 can be disposed on the same layer.
  • the first power signal line VDD1 includes a plurality of sub-power signal lines VDD11, VDD12, each of the sub-power signal lines extends along the first direction or along the second direction, at least The pixel circuits of two adjacent pixels are connected to the same sub power signal line of the first power signal line.
  • Such setting can reduce the number of sub-power signal lines of the first power signal line VDD1 and improve the light transmittance of the display substrate.
  • the pixel circuits of two adjacent sub-pixels in the second direction Y are connected to the same second sub-power signal line VDD11 .
  • At least one of the first sub-power signal lines VDD11 of the first power signal line VDD1 is connected to the pixel circuit circuit through the second power signal line VDD12 .
  • Connection; at least part of the second sub-power signal line VDD12 and the first sub-power signal line VDD11 are arranged in different layers. Such an arrangement can prevent the driving signal line for driving the pixel in the source-drain metal layer 340 from being short-circuited with the second sub-power signal line VDD12 .
  • the second sub-power signal line VDD12 includes a first connection signal line VDD13 and a second connection signal line VDD14, and the second connection signal line VDD14 is connected to the first sub-power signal line VDD11. Heterogeneous settings.
  • the display substrate further includes a driving signal line disposed on the same layer as the first sub-power supply signal line, and the driving signal line is configured to provide a driving signal for the pixel circuit.
  • the orthographic projection of the portion of the second sub-power signal line VDD12 and the first sub-power signal line VDD11 arranged in different layers on the base substrate and the orthographic projection of the driving signal line on the base substrate There is an overlap. Such arrangement can not only ensure that the first sub-power signal line VDD11 is electrically connected to the pixel circuit through the second sub-power signal line VDD12, but also avoid short circuit between the second sub-power signal line VDD12 and the driving signal line. In the embodiments shown in FIGS.
  • the driving signal line includes a data line Vd
  • the second connection signal line VDD14 of the second sub-power supply signal line VDD12 is arranged in a different layer from the first sub-power supply signal line VDD11
  • the second The orthographic projection of the connection signal line VDD14 on the base substrate overlaps with the orthographic projection of the data line Vd on the base substrate.
  • the pixel defining layer is provided with an opening 25 located in the non-light-emitting area AA2 .
  • the light transmittance of the non-light-emitting area AA2 can be improved by opening the opening 25 in the non-light-emitting area AA2 on the pixel defining layer.
  • a plurality of openings 25 may be opened on the pixel defining layer.
  • the orthographic projection of the opening 25 on the base substrate is at least partially located at the orthographic projection of the second electrode 22 on the base substrate, the first The orthographic projection of the second power signal line VSS on the base substrate and the orthographic projection of the first power signal line VDD1 on the base substrate are outside.
  • the orthographic projections of the openings 25 on the base substrate are located outside the orthographic projections of the second electrodes 22 on the base substrate. In this way, the height difference of the film layer below the second electrode 22 is small, and the second electrode 22 is prevented from climbing and breaking.
  • the orthographic projection of the opening 25 on the base substrate is outside the orthographic projection of the first power signal line VDD1 on the base substrate.
  • the orthographic projection of the opening 25 on the base substrate is located outside the orthographic projection of the first sub-power signal line VDD11 of the first power signal line VDD1 on the base substrate, and the opening 25 is on the substrate.
  • the orthographic projection on the base substrate partially overlaps with the orthographic projection of the second sub-power signal line VDD12 of the first power signal line VDD1 on the base substrate.
  • the orthographic projections of the openings 25 on the base substrate are all outside the orthographic projections of the second power signal line VSS on the base substrate.
  • the orthographic projection of the first power signal line VDD1 on the substrate is the same as the orthographic projection of the second power signal line VSS on the substrate. overlap.
  • Such an arrangement can avoid overlapping of the first power signal line VDD1 and the second power signal line VSS in the film lamination direction of the display substrate, and the light transmittance of the overlapping area is small, which affects the light transmittance of the display substrate; And it can prevent the overlapping area of the first power signal line VDD1 and the second power signal line VSS from generating more heat during the working process of the display panel, which is prone to burns, thereby helping to improve the service life of the display substrate.
  • the first power signal line VDD1 includes a first sub-power signal line VDD11 extending along the first direction X, and a second sub-power signal line VDD12 extending along the second direction Y. , and a plurality of first connection segments 63 extending along the second direction Y;
  • the second power signal line VSS includes a third sub-power signal line VSS1 extending along the first direction X, along the second The fourth sub power supply signal line VSS2 extending in the direction Y, and a plurality of second connection segments 53 extending in the second direction Y.
  • Each of the first sub-power signal lines VDD11 includes a plurality of first sub-signal segments 61 arranged at intervals in the first direction X
  • each of the second sub-power signal lines VDD12 includes a plurality of first sub-signal segments 61 arranged in the second direction Y.
  • a plurality of second sub-signal segments 62 arranged at intervals, each of the first sub-signal segments 61 is respectively connected to at least one of the second sub-signal segments 62, and the connected first sub-signal segments 61 are connected to the second sub-signal segments
  • the orthographic projection of the signal segment 62 on the substrate substrate intersects.
  • Each of the third sub-power signal lines VSS1 includes a plurality of third sub-signal segments 51 arranged at intervals in the first direction X
  • each of the fourth sub-power signal lines VSS2 includes a plurality of third sub-signal segments 51 arranged in the second direction Y.
  • a plurality of fourth sub-signal segments 52 arranged at intervals, each of the third sub-signal segments 51 is respectively connected to at least one of the fourth sub-signal segments 52, and the connected third sub-signal segments 51 are connected to the fourth sub-signal segments.
  • the orthographic projection of the signal segment 52 on the substrate substrate intersects.
  • the adjacent first sub-signal segments 61 in the second direction Y are connected by the first connecting segment 63, and the orthographic projection of at least one of the first connecting segments 63 on the base substrate is located at the same Between the orthographic projections of two adjacent third sub-signal segments 51 on the base substrate.
  • the third sub-signal segments 51 adjacent in the second direction Y are connected through the second connecting segment 53; the orthographic projection of at least one second connecting segment 53 on the base substrate is located at the same Between the orthographic projections of two adjacent first sub-signal segments 61 on the base substrate.
  • each first sub-signal segment 61 and each second sub-signal segment 62 of the first power signal line VDD1 can be electrically connected, and each third sub-signal segment 51 and each second sub-signal segment 51 of the second power signal line VSS can be electrically connected to each other.
  • the fourth sub-signal segments 52 are all electrically connected, and at the same time, the overlapping area of the orthographic projections of the first power signal line VDD1 and the second power signal line on the base substrate can be reduced, thereby improving the light transmittance and usability of the display substrate. life.
  • each of the first connecting sections 63 on the base substrate are respectively located between the orthographic projections of two adjacent third sub-signal sections 51 on the base substrate
  • each The orthographic projections of the second connecting section 53 on the base substrate are respectively located between the orthographic projections of two adjacent first sub-signal sections 61 on the base substrate. In this way, the orthographic projections of the first power signal line VDD1 and the second power signal line on the base substrate do not overlap.
  • first connection section 63 and the first sub-power signal line VDD11 of the first power signal line VDD1 can be arranged on the same layer, and the second connection section 53 can be arranged on the same layer as the second power signal line VSS. Such setting helps to simplify the complexity of the manufacturing process of the display substrate.
  • the display substrate is further provided with a plurality of driving signal lines and the driving signal lines are configured to provide driving signals for the pixel circuits.
  • the width of at least one driving signal line located in the light-emitting area is larger than the width of the part located in the non-light-emitting area.
  • the width of the driving signal line in the non-light-emitting area By setting the width of the driving signal line in the non-light-emitting area to be small, it is helpful to improve the light transmittance of the non-light-emitting area, thereby improving the light transmittance of the display substrate; by setting the width of the part of the driving signal line in the light-emitting area to be large, it can be Avoid the high resistance of the part of the driving signal line located in the non-light-emitting area, which will cause the heat of the light-emitting area to rise rapidly.
  • the driving signal lines include a reset control signal line Rst1 , a scanning signal line Ga1 , an emission control signal line EM1 and a third power signal line VDD2 .
  • the reset control signal line Rst1, reset control signal line Rst2, scan signal line Ga1, light emission control signal line EM1 and third power signal line VDD2 are located in the light-emitting area AA1 and have a width greater than that in the non-light-emitting area AA2.
  • the width of at least one scanning signal line Ga1 located in the light emitting area AA1 is greater than the width of the portion located in the non-emitting area AA2; the scanning signal line Ga1 located in the light emitting area AA1
  • the width range of the portion is 3.5 ⁇ m ⁇ 5.5 ⁇ m, and the width range of the portion of the scanning signal line Ga1 located in the non-light-emitting area AA2 is 2 ⁇ m ⁇ 3.5 ⁇ m.
  • the width of the part of the scanning signal line Ga1 located in the non-luminous area AA2 is 2 ⁇ m to 3.5 ⁇ m, it is possible to avoid the too small width of the part of the scanning signal line Ga1 located in the non-luminous area AA2 resulting in a large resistance, and also to avoid The width of the part of the scanning signal line Ga1 located in the non-light-emitting area AA2 is too large to affect the light transmittance of the non-light-emitting area.
  • the width of the part of the scanning signal line Ga1 located in the light-emitting area AA1 may be 3.5 ⁇ m, 3.8 ⁇ m, 4.0 ⁇ m, 4.5 ⁇ m, 5.0 ⁇ m, 5.5 ⁇ m, etc.
  • the width of the portion of area AA2 may be 2 ⁇ m, 2.3 ⁇ m, 2.5 ⁇ m, 3.0 ⁇ m, 3.2 ⁇ m, 3.5 ⁇ m, or the like.
  • the display substrate further includes a frame area CC located on at least one side of the display area AA, and the display substrate further includes an auxiliary wiring 70 located in the frame area CC,
  • the auxiliary wiring 70 is electrically connected to the second electrode 22 .
  • the auxiliary wiring 70 can be electrically connected to the auxiliary wiring 70 through the second power signal line VSS.
  • the auxiliary wiring can reduce the resistance of the second electrode 22, thereby improving the IR drop problem of the second electrode 22.
  • the auxiliary wiring 70 includes a first conductive film layer 71 and a second conductive film layer 72 located on the side of the first conductive film layer 71 away from the base substrate, and the first conductive film layer 71 is on the The edge of the orthographic projection on the base substrate close to the display area AA is located inside the edge of the orthographic projection of the second conductive film layer 72 on the base substrate close to the edge of the display area AA. Such setting can ensure the overlapping effect of the second conductive film layer 72 and the first conductive film layer 71 .
  • the orthographic projection of the first conductive film layer on the base substrate is far away from the edge of the display area AA
  • the orthographic projection of the second conductive film layer 72 on the base substrate is far away from the display area.
  • the inner side of the edge of AA is used to more effectively ensure the overlapping effect of the second conductive film layer 72 and the first conductive film layer 71 .
  • the first conductive film layer 71 is provided on the same layer as the first electrode 21
  • the second conductive film layer 72 is provided on the same layer as the second electrode 22
  • the auxiliary wiring 70 may further include a third conductive film layer located between the first conductive layer and the base substrate, and the third conductive film layer may be located in the source-drain metal layer.
  • the display substrate may further include an encapsulation layer located above the pixels.
  • the encapsulation layer may be a thin-film encapsulation layer, including alternately arranged organic layers and inorganic layers, and the topmost is an inorganic layer.
  • Embodiments of the present application further provide a display panel, which includes the display substrate described in any one of the above embodiments.
  • the display panel may further include a glass cover located on a side of the display substrate away from the substrate.
  • An embodiment of the present application further provides a display device, which includes the above-mentioned display panel.
  • the display device may further include a housing, and the display panel may be embedded in the housing.
  • the display device in this embodiment can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, and vehicle-mounted display device.

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Abstract

一种显示基板、显示面板及显示装置。显示基板包括显示区，显示区至少部分区域为透明显示区。显示基板包括位于透明显示区的多个像素。像素包括多个子像素，子像素包括有机发光元件(220)和像素电路(221)。有机发光元件(220)包括第一电极、第二电极及位于第一电极与第二电极之间的有机发光材料。子像素的第一电极与像素电路(221)电连接。第一电极的数量大于第二电极的数量。显示基板还设有与像素电路(221)相连的第一电源信号线(VDD1)和与第二电极相连的第二电源信号线(VSS)。第一电源信号线(VDD1)包括沿第一方向延伸的第一子电源信号线(VDD11)和沿第二方向延伸的第二子电源信号线(VDD12)；和/或，第二电源信号线(VSS)包括沿第一方向延伸的第三子电源信号线(VSS1)和沿第二方向延伸的第四子电源信号线(VSS2)。

Description

显示基板、显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)显示器由于具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、使用温度范围宽、可实现柔性显示等诸多优点，在显示领域、照明领域及智能穿戴等领域有着广泛地应用。
发明内容
本申请实施例提供了一种显示基板、显示面板及显示装置。
根据本申请实施例的第一方面，提供了一种显示基板。所述显示基板包括显示区，所述显示区的至少部分区域为透明显示区；所述显示基板包括衬底基板及位于所述衬底基板上且位于所述透明显示区的多个像素；所述像素包括多个子像素，所述子像素包括有机发光元件和驱动所述有机发光元件的像素电路；所述有机发光元件包括第一电极、第二电极及位于所述第一电极与所述第二电极之间的有机发光材料；所述子像素的第一电极与像素电路电连接；所述第一电极的数量大于所述第二电极的数量；
所述显示基板还设有第一电源信号线和第二电源信号线，所述像素电路与所述第一电源信号线相连，所述第二电极与所述第二电源信号线相连；所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线；和/或，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线；所述 第一方向与所述第二方向相交。
在一个实施例中，所述显示基板还包括与所述第二电源信号线电连接的搭接部，至少存在相邻两个所述像素的第二电极与同一所述搭接部接触。
在一个实施例中，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线时，至少存在相邻两个所述像素的第二电极通过同一所述搭接部与所述第三子电源信号线电连接，或者通过同一所述搭接部与所述第四子电源信号线电连接。
在一个实施例中，在所述第一方向上排布的多个所述搭接部通过所述第三子电源信号线电连接，和/或，在所述第二方向上排布的多个所述搭接部通过所述第四子电源信号线电连接。
在一个实施例中，所述显示基板还包括与所述第二电源信号线电连接的搭接部，至少存在相邻四个所述像素的第二电极与同一所述搭接部接触，相邻四个所述像素排列为两行两列。
在一个实施例中，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线时，至少存在相邻四个所述像素的第二电极通过同一所述搭接部连接至所述第三子电源信号线及所述第四子电源信号线。
在一个实施例中，所述显示基板包括多个所述搭接部，至少存在一个所述搭接部与在所述第一方向上排布的其他所述搭接部通过所述第三子电源信号线电连接，且与在所述第二方向上排布的其他所述搭接部通过所述第四子电源信号线电连接。
在一个实施例中，所述显示基板还包括与所述第二电极连接的电极连接结构，与同一所述搭接部接触的各所述第二电极连接至同一所述电极连接结构，所述第二电极通过所述电极连接结构与所述搭接部接触。
在一个实施例中，所述第一电源信号线包括沿第一方向延伸的第一子 电源信号线和沿第二方向延伸的第二子电源信号线时，至少存在相邻两个所述像素的像素电路与所述第一电源信号线的同一所述第一子电源信号线相连，或者与同一所述第二子电源信号线相连。
在一个实施例中，所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线时，至少一条所述第一子电源信号线通过所述第二子电源信号线与所述像素电路电连接；
至少部分所述第二子电源信号线与所述第一子电源信号线异层设置。
在一个实施例中，所述显示基板还包括与所述第一子电源信号线同层设置的驱动信号线，所述驱动信号线被配置为为所述像素电路提供驱动信号；所述第二子电源信号线与所述第一子电源信号线异层设置的部分在所述衬底基板上的正投影与所述驱动信号线在所述衬底基板上的正投影存在交叠。
在一个实施例中，所述第一电源信号线在所述衬底基板上的正投影与所述第二电源信号线在所述衬底基板上的正投影无交叠。
在一个实施例中，所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线，且所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线时，所述第一电源信号线还包括多个沿所述第二方向延伸的第一连接段；所述第二电源信号线还包括多个沿所述第二方向延伸的第二连接段；各所述第一子电源信号线包括在所述第一方向上间隔排布的多个第一子信号段，各所述第二子电源信号线包括在所述第二方向上间隔排布的多个第二子信号段，各所述第一子信号段分别与至少一个所述第二子信号段相连；各所述第三子电源信号线包括在所述第一方向上间隔排布的多个第三子信号段，各所述第四子电源信号线包括在所述第二方向上间隔排布的多个第四子信号段，各所述第三子信号段分别与至少一个所述第四子信号段相连；
在所述第二方向上相邻的所述第一子信号段通过所述第一连接段连 接，在所述第二方向上相邻的所述第三子信号段通过所述第二连接段连接；至少一个所述第一连接段在所述衬底基板上的正投影位于相邻的两个所述第三子信号段在所述衬底基板上的正投影之间；至少一个所述第二连接段在所述衬底基板上的正投影位于相邻的两个所述第一子信号段在所述衬底基板上的正投影之间。
在一个实施例中，所述透明显示区包括发光区及非发光区；所述像素设置在所述发光区；
所述显示基板还设有多个驱动信号线；至少一个所述驱动信号线位于所述发光区的部分的宽度大于位于所述非发光区的部分的宽度。
在一个实施例中，所述驱动信号线包括扫描信号线，所述扫描信号线被配置为为所述像素提供扫描信号；
至少一个所述扫描信号线位于所述发光区的部分的宽度大于位于所述非发光区的部分的宽度；所述扫描信号线位于所述发光区的部分的宽度范围为3.5μm～5.5μm，所述扫描信号线位于所述非发光区的部分的宽度范围为2μm～3.5μm。
在一个实施例中，所述像素电路包括驱动晶体管，所述显示基板还包括有源半导体层，所述有源半导体层包括各所述子像素的驱动晶体管的沟道；
在至少一个所述像素中，至少一个所述子像素的驱动晶体管的沟道包括顺次连接的第一区段、第二区段、第三区段、第四区段和第五区段，所述第一区段、所述第三区段及所述第五区段沿所述第二方向延伸，所述第二区段及所述第四区段沿所述第一方向延伸；至少一个所述子像素的驱动晶体管的沟道包括顺次连接的第六区段、第七区段和第八区段，所述第六区段与所述第八区段沿所述第二方向延伸，所述第七区段沿所述第一方向延伸。
在一个实施例中，所述显示基板还包括屏蔽线及复位电源信号线，所述复位电源信号线被配置为为所述子像素提供复位电源信号；所述屏蔽线与 所述复位电源信号线电连接。
在一个实施例中，所述透明显示区包括发光区与非发光区，所述像素位于所述发光区；所述显示基板还包括像素限定层，所述像素限定层设有位于所述非发光区的开孔；
所述开孔在所述衬底基板上的正投影至少部分位于所述第二电极在所述衬底基板上的正投影、所述第二电源信号线在所述衬底基板上的正投影、以及所述第一电源信号线在所述衬底基板上的正投影之外。
在一个实施例中，所述显示基板还包括位于所述显示区至少一侧的边框区，所述显示基板还包括位于所述边框区的辅助走线，所述辅助走线与所述第二电极电连接；所述辅助走线包括第一导电膜层及位于所述第一导电膜层背离所述衬底基板一侧的第二导电膜层，所述第一导电膜层在所述衬底基板上的正投影靠近所述显示区的边缘位于所述第二导电膜层在所述衬底基板上的正投影靠近所述显示区的边缘内侧。
根据本申请实施例的第二方面，提供了一种显示面板，包括上述的显示基板。
根据本申请实施例的第三方面，提供了一种显示装置，包括上述的显示面板。
本申请实施例提供的显示基板、显示面板及显示装置，由于第一电极的数量大于所述第二电极的数量，则存在至少两个子像素共用一个第二电极；相对于各子像素的第二电极均独立设置的方案，本申请实施例中至少两个子像素共用一个第二电极，可减小透明显示区的第二电极的总面积，有助于提升显示基板的透明显示区的光线透过率；通过设置第一电源信号线与第二电源信号线中的一个为网格状结构，有助于减小第一电源信号线和第二电源信号线的压降，提升显示基板显示效果的均一性。
附图说明
图1是本申请一示例性实施例提供的像素电路的电路示意图；
图2至图7是本申请一示例性实施例提供的显示基板的各层的局部示意图；其中，图3为图2的局部放大图；
图8是本申请一示例性实施例提供的显示基板的多个膜层叠加的示意图；
图9是本申请一示例性实施例提供的显示基板的第二导电层的局部示意图；
图10是本申请一示例性实施例提供的显示基板的第三导电层的局部示意图；
图11是本申请一示例性实施例提供的显示基板的第三导电层与第四导电层叠加的局部示意图；
图12是本申请一示例性实施例提供的显示基板的多个膜层叠加的局部示意图；
图13是本申请另一示例性实施例提供的显示基板的第二导电层的局部示意图；
图14是本申请另一示例性实施例提供的显示基板的第三导电层的局部示意图；
图15是本申请另一示例性实施例提供的显示基板的第三导电层与第四导电层叠加的局部示意图；
图16是本申请另一示例性实施例提供的显示基板的多个膜层叠加的局部示意图；
图17是本申请一示例性实施例提供的显示基板的第一电源信号线与第二电源信号线叠加后的局部示意图；
图18是本申请一示例性实施例提供的显示基板的多个膜层叠加的局部示意图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本申请相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
本申请实施例提供了一种显示基板、显示面板及显示装置。下面结合附图，对本申请实施例中的显示基板、显示面板及显示装置进行详细说明。在不冲突的情况下，下述的实施例中的特征可以相互补充或相互组合。
本申请实施例提供了一种显示基板、显示面板及显示装置。下面结合附图，对本申请实施例中的显示基板、显示面板及显示装置进行详细说明。在不冲突的情况下，下述的实施例中的特征可以相互补充或相互组合。
本申请实施例提供了一种显示基板。所述显示基板包括显示区，所述显示区的至少部分区域为透明显示区。
在一个实施例中，所述显示区的全部区域均为透明显示区，也即是显示基板为透明显示基板。其中透明显示区指的是显示区包括子显示区和透光区，子显示区指的是设有像素的区域，透光区指的是未设置像素的区域；或者，子显示区指的是设有像素电路的区域，透光区指的是未设置像素电路的区域。在另一个实施例中，所述显示区的部分区域为透明显示区，另一部分区域为非透明显示区。例如显示基板下方设置摄像头及光线传感器的区域为透明显示区，其他区域为非透明显示区。
所述显示基板包括衬底基板及位于所述衬底基板上且位于所述透明显示区的多个像素。多个像素在衬底基板上间隔排布。需要说的是，以下关于像素的介绍，如无特殊说明，均指的是透明显示区的像素。
所述像素包括多个子像素，所述子像素包括有机发光元件和驱动所述有机发光元件的像素电路；所述有机发光元件包括第一电极、第二电极及位于所述第一电极与所述第二电极之间的有机发光材料。所述子像素的第一电极与像素电路电连接。在一些实施例中，第一电极可以是阳极，第二电极可以是阴极，第一电极位于有发光材料靠近衬底的一侧，第二电极位于有发光材料背离衬底的一侧。各像素可包括三个不同发光颜色的子像素，例如可包括红色的子像素、绿色的子像素和蓝色的子像素。
在一个实施例中，所述显示基板还包括像素限定层，所述像素限定层设有与所述子像素一一对应的像素开口。像素开口用于限定各子像素的发光区。
在一些实施例中，有机发光材料位于第一电极远离衬底基板的一侧。各子像素的第一电极与有机发光材料在像素限定层的像素开口处接触，像素限定层的像素开口定义出子像素发光区的形状。例如，有机发光元件的第一 电极(例如，阳极)可以设置在像素限定层的下方，像素限定层的像素开口露出第一电极的一部分，当有机发光材料形成在上述像素限定层中的像素开口中时，有机发光材料与第一电极接触，从而这部分第一电极能够驱动有机发光材料进行发光。
在一些实施例中，像素限定层的像素开口在衬底基板上的正投影位于相应的有机发光材料在衬底基板上的正投影内，即有机发光材料覆盖了像素限定层的像素开口。例如，有机发光材料的面积大于对应的像素开口的面积，即有机发光材料除位于像素开口内部的部分，至少还包括覆盖像素限定层的实体结构上的部分，通常在像素开口的各个边界处的像素限定层的实体结构上均覆盖有机发光材料。需要说明的是，以上对于有机发光材料图案的描述，是基于例如FMM工艺形成的图案化的各个子像素的有机发光材料，除了FMM制作工艺，也有一些有机发光材料是采用open mask工艺在整个显示区形成整体的膜层，其形状在衬底基板上的正投影是连续的，所以必然有位于像素开口内的部分和位于像素限定层实体结构上的部分。
在一个实施例中，所述第一电极的数量大于所述第二电极的数量。所述显示基板还设有第一电源信号线和第二电源信号线，所述像素电路与所述第一电源信号线相连，所述第二电极与所述第二电源信号线相连；所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线；和/或，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线；所述第一方向与所述第二方向相交。
本申请实施例提供的显示基板，由于第一电极的数量大于所述第二电极的数量，则存在至少两个子像素共用一个第二电极；若各子像素的第二电极均独立设置，各第二电极为了与第二电源信号线搭接均需设置较大的面积，本申请实施例中至少两个子像素共用一个第二电极，可减小透明显示区的第二电极的总面积，有助于提升显示基板的透明显示区的光线透过率。通过设 置第一电源信号线与第二电源信号线中的一个为网格状结构，有助于减小第一电源信号线和第二电源信号线的压降，提升显示基板显示效果的均一性。
在一个实施例中，所述像素的各子像素可共用一个第二电极。例如，像素包括红色的子像素、绿色的子像素和蓝色的子像素时，同一像素中红色的子像素、绿色的子像素和蓝色的子像素共用一个第二电极。相邻像素之间的区域未设置第二电极，以保证显示基板的光线透过率。
在一个实施例中，所述第一电源信号线可为高电平电源信号线，所述第二电源信号线可为低电平电源信号线。
在一些实施例中，第一方向为列方向，第二方向为行方向。在一些实施例中，每一所述像素中子像素的像素电路在所述第二方向上间隔排布。
显示基板的透明显示区包括发光区和非发光区。发光区之外的区域均为非发光区。像素位于发光区。像素位于发光区指的是，像素的像素电路、第一电极、有机发光材料及部分第二电极位于发光区。
在一个实施例中，所述子像素的像素电路在衬底基板上的正投影覆盖的区域大致位于一个矩形框内。像素电路在衬底基板上的正投影主要包括各个晶体管、电容等元件的结构在衬底基板上的正投影。显示基板还包括多个信号线，信号线用来驱动像素电路。需要说明的是，有一些信号线包括位于矩形框内的部分以及延伸出该矩形框外的部分。
在一个实施例中，如图1所示，像素电路221包括驱动电路222。驱动电路222包括控制端、第一端和第二端，且被配置为对有机发光元件220提供驱动有机发光元件220发光的驱动电流。
在一个实施例中，如图1所示，像素电路221包括第一发光控制电路223和第二发光控制电路224。例如，第一发光控制电路223与驱动电路222的第一端和第一电压端VDD连接，且被配置为实现驱动电路222和第一电压端VDD之间的连接导通或断开，第二发光控制电路224与驱动电路222的第 二端和有机发光元件220的第一电极电连接，且被配置为实现驱动电路222和有机发光元件220之间的连接导通或断开。
在一个实施例中，如图1所示，像素电路221还包括数据写入电路226、存储电路227、阈值补偿电路228和复位电路229。数据写入电路226与驱动电路222的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路227。存储电路227与驱动电路222的控制端和第一电压端VDD电连接，且被配置为存储数据信号。阈值补偿电路228与驱动电路222的控制端和第二端电连接，且被配置为对驱动电路222进行阈值补偿。复位电路229与驱动电路222的控制端和有机发光元件220的第一电极电连接，且配置为在复位控制信号的控制下对驱动电路222的控制端和有机发光元件220的第一电极进行复位。
在一个实施例中，如图1所示，驱动电路222包括驱动晶体管T1，驱动电路222的控制端包括驱动晶体管T1的栅极，驱动电路222的第一端包括驱动晶体管T1的第一极，驱动电路222的第二端包括驱动晶体管T1的第二极。
在一个实施例中，如图1所示，数据写入电路226包括数据写入晶体管T2，存储电路227包括电容C，阈值补偿电路228包括阈值补偿晶体管T3，第一发光控制电路223包括第一发光控制晶体管T4，第二发光控制电路224包括第二发光控制晶体管T5，复位电路229包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
在一个实施例中，如图1所示，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与扫描信号线Ga1电连接以接收扫描信号；电容C的第一极与第一电源端VDD电连接，电容C的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极 与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与有机发光元件220的第一电极电连接，第二复位晶体管T7的栅极被配置为与复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与有机发光元件220的第二电极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制信号线EM2电连接以接收第二发光控制信号；有机发光元件220的第一电极与第二电源端vss电连接。
在一个实施例中，第一电源端VDD和第二电源端vss中的其中一个为高压端，另一个为低压端。图1所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端vss可以为电压源以输出恒定的第二电压，第二电压为负电压等。在一些示例性实施例中，第二电源端vss可以接地。
在一个实施例中，如图1所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极可以电连接到同一条信号线，例如扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T2的栅极和阈值补偿晶体管T3的栅极也可以分别电连接至 不同的信号线，即数据写入晶体管T2的栅极电连接到扫描信号线Ga1，阈值补偿晶体管T3的栅极电连接到扫描信号线Ga2，而扫描信号线Ga1和扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T2的栅极和阈值补偿晶体管T3可以被分开单独控制，增加控制像素电路的灵活性。
在一个实施例中，如图1所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极可以电连接到同一条信号线，例如发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置发光控制信号线EM2，减少信号线的数量。在其他实施例中，第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T4的栅极电连接到发光控制信号线EM1，第二发光控制晶体管T5的栅极电连接到发光控制信号线EM2，而发光控制信号线EM1和发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本申请的实施例对此不作限制。
在一个实施例中，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T6的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T6的栅极电连接到复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到复位控制信号线 Rst2，而复位控制信号线Rst1和复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。在另一实施例中，第一子复位控制信号与第二子复位控制信号不同，复位控制信号线Rst2的脉冲宽度大于复位控制信号线Rst1的脉冲宽度，且复位控制信号线Rst2的脉冲宽度小于第二发光控制晶体管T5在截止时发光控制信号线EM2的脉冲宽度。如此有助于提升子像素的有机发光元件的寿命。
在一个实施例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到扫描信号线Ga1以接收扫描信号作为第二子复位控制信号。
在一个实施例中，第一复位晶体管T6的栅极和第二复位晶体管T7的源极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T6的栅极和第二复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的栅极和发光元件220的第一电极进行复位即可，本申请对此不作限制。
需要说明的是，图1所示的像素电路中的驱动电路222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229仅为示意性的，驱动电路222、数据写入电路226、存储电路227、阈值补偿电路228和复位电路229等电路的具体结构可以根据实际应用需求进行设定，本申请的实施例对此不作具体限定。
按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本申请的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本申请的技术方案，也就是说，在本申请的描述中，驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、 第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。当然本申请的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本申请的实施例中的一个或多个晶体管的功能。
需要说明的是，本申请的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本申请的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本申请的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，在本申请实施例中，子像素的像素电路除了可以为图1所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本申请实施例对此不作限定。
图2-7为本申请一实施例提供的显示基板的各层的示意图，图8为显示基板的部分膜层叠加的示意图。下面结合附图2-8描述像素电路中的各个电路及信号线在背板上的位置关系，图2-8所示的示例以一个像素的像素电路221为例，且以子像素110包括的像素电路的各晶体管的位置进行示意，子像素120与子像素130中像素电路包括的部件与子像素110包括的各晶体管的位置大致相同。图2-7可以看出，像素电路位于发光区AA1，一些信号线仅位于发光区AA1，一些信号线部分位于发光区AA1，部分位于非发光区AA2。如图2所示，子像素110的像素电路221包括图1所示的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7及电容C。
图2-8还示出了电连接到同一像素的各子像素的像素电路121的扫描信 号线Ga1、复位控制信号线Rst1、复位电源信号线Init1、发光控制信号线EM1、数据线Vd、与第一电源端VDD相连的第一电源信号线VDD1的第二子电源信号线VDD12、与第二电源端vss相连的第二电源信号线VSS及屏蔽线344。图2-7还示出了第三电源信号线VDD2、第四电源信号线VDD3和第五电源信号线VDD4，第三电源信号线VDD2、第四电源信号线VDD3和第五电源信号线VDD4分别与第一电源信号线VDD1电连接。
扫描信号线Ga1被配置为为像素提供扫描信号；复位控制信号线Rst1和复位控制信号线Rst2被配置为为像素提供复位控制信号；复位电源信号线Init1被配置为为像素提供复位电源信号；发光控制信号线EM1被配置为为像素提供发光控制信号；数据线Vd被配置为为像素提供发光数据信号；第一电源信号线VDD1及第二电源信号线VSS被配置为为像素提供电源信号。
例如，图2示出了该显示基板中像素电路的有源半导体层310。有源半导体层310可采用半导体材料图案化形成。有源半导体层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的沟道。有源半导体层310包括各子像素的各晶体管的沟道和源漏区(即子像素120中示出的源极区域s和漏极区域d)，且同一像素电路中的各晶体管的沟道和源漏区一体设置。
需要说明的是，有源半导体层可以包括一体形成的低温多晶硅层，其中的源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括源漏区(即源极区域s和漏极区域d)和沟道，不同晶体管的沟道之间由源漏区隔开。
在一个实施例中，沿第二方向排列的不同颜色子像素的像素电路中的有源半导体层没有连接关系，彼此断开。沿第一方向排列的相同颜色子像素的像素电路中的有源半导体层可以为一体设置，也可以彼此断开。
如图3所示，在至少一个所述像素中，至少一个所述子像素的驱动晶体管T1的沟道31、32包括顺次连接的第一区段301、第二区段302、第三区段303、第四区段304和第五区段305，所述第一区段301、所述第三区段303及所述第五区段305沿所述第二方向Y延伸，所述第二区段302及所述第四区段304沿所述第一方向X延伸；至少一个所述子像素的驱动晶体管T1的沟道33包括顺次连接的第六区段306、第七区段307和第八区段308，所述第六区段306与所述第八区段308沿所述第二方向Y延伸，所述第七区段307沿所述第一方向X延伸。如此设置，可在子像素所占空间一定的前提下，优化显示基板上的不同颜色子像素的驱动晶体管的沟道宽长比，提高显示基板的亮度。在该实施例中，沟道33的宽长比大于沟道31和沟道32的宽长比。在一些实施例中，沟道31和沟道32可以是红色的子像素与绿色的子像素的沟道，沟道33可以是蓝色的子像素的沟道。
在一个实施例中，如图3所示，所述子像素的驱动晶体管T1包括第一源漏区311和第二源漏区312，至少一个所述子像素的驱动晶体管T1的第一源漏区和第二源漏区的长度不同，第一源漏区311和第二源漏区312中的一个为源极区域，另一个为漏极区域。沟道31及沟道32所在的驱动晶体管T1中，第一源漏区311与第一区段301相连，第二源漏区312与第五区段305相连；沟道33所在的驱动晶体管T1中，第一源漏区311与第六区段306相连，第二源漏区312与第八区段308相连。如此设置，可优化像素电路的信号写入，优化对沟道的遮光设计。
图3所示的实施例中，沟道31、沟道32及沟道33所在的驱动晶体管T1中，第一源漏区311与第二源漏区312的长度均不同。
例如，像素电路的栅极金属层可以包括第一导电层和第二导电层。在上述的有源半导体层310上形成有栅极绝缘层，用于保护上述的有源半导体层310，有源半导体层310位于衬底基板100上。图4示出了该显示基板包括的第一导电层320，第一导电层320设置在栅极绝缘层上，从而与有源半导体 层310绝缘。第一导电层320可以包括电容C的第二极板CC2、扫描信号线Ga1、复位控制信号线Rst1、发光控制信号线EM1以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。扫描信号线Ga1包括扫描信号线主体部Ga11及由由所述扫描信号线主体部Ga11的一侧凸出的凸出部P。
例如，如图4所示，数据写入晶体管T2的栅极可以为扫描信号线Ga1与有源半导体层310交叠的部分；第一发光控制晶体管T4的栅极可以为发光控制信号线EM1与有源半导体层310交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线EM1与有源半导体层310交叠的第二部分；第一复位晶体管T6的栅极为复位控制信号线Rst1与有源半导体层310交叠的第一部分，第二复位晶体管T7的栅极为复位控制信号线Rst1与有源半导体层310交叠的第二部分；阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为扫描信号线Ga1与有源半导体层310交叠的部分，阈值补偿晶体管T3的第二个栅极可为扫描信号线Ga1的突出部P与有源半导体层310交叠的部分。如图1和4所示，驱动晶体管T1的栅极可为电容C的第二极板CC2。
需要说明的是，图2中的各虚线矩形框示出了第一导电层320与有源半导体层310交叠的各个部分。
例如，如图4所示，扫描信号线Ga1、复位控制信号线Rst1和发光控制信号线EM1沿第一方向X排布，扫描信号线Ga1、复位控制信号线Rst1和发光控制信号线EM1沿第二方向Y延伸。其中信号线沿第二方向延伸指的是，信号线整体行沿第二方向延伸，信号线在第二方向上延伸的部分的面积远大于在第二方向上延伸的部分的面积；信号线沿第一方向延伸指的是，信号线整体行沿第一方向延伸，信号线在第一方向上延伸的部分的面积远大于在第二方向上延伸的部分的面积。
例如，在第一方向X上，电容C的第二极板CC2(即驱动晶体管T1的栅极)位于扫描信号线Ga1和发光控制信号线EM1之间。扫描信号线Ga1的突出部P位于扫描信号线Ga1的远离发光控制信号线EM1的一侧。
例如，如图2所示，在第一方向X上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。例如，图2-7所示的示例中，第一颜色子像素的像素电路的驱动晶体管T1的栅极的第一侧和第二侧为在第一方向X上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图2-8所示，在XY面内，子像素110的像素电路的驱动晶体管T1的栅极的第一侧可以为驱动晶体管T1的栅极的上侧，子像素110的像素电路的驱动晶体管T1的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。所述下侧，例如显示基板的用于绑定驱动芯片的一侧为显示基板的下侧，驱动晶体管T1的栅极的下侧，为驱动晶体管T1的栅极的更靠近驱动芯片的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管T1的栅极的更远离驱动芯片的一侧。
例如，在一些实施例中，如图2-8所示，在第二方向Y上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。例如，图2-8所示的示例中，子像素110的像素电路的驱动晶体管T1的栅极的第三侧和第四侧为在第二方向Y上驱动晶体管T1的栅极的彼此相对的两侧。例如，如图2-7所示，子像素110的像素电路的驱动晶体管T1的栅极的第三侧可以为子像素110的像素电路的驱动晶体管T1的栅极的左侧，子像素110的像素电路的驱动晶体管T1的栅极的第四侧可以为子像素110的像素电路的驱动晶体管T1的栅极的右侧。所述左侧和右侧，例如在同一像素电路中，数 据线在第一电源信号线VDD1左侧，第一电源信号线VDD1在数据线右侧。
例如，在上述的第一导电层320上形成有第一绝缘层，用于保护上述的第一导电层320。图5示出了该像素电路的第二导电层330，第二导电层330包括电容C的第一极板CC1、复位电源信号线Init1以及第三电源信号线VDD2。第三电源信号线VDD2与电容C的第一极板CC1一体形成。电容C的第一极板CC1与电容C的第二极板CC2至少部分重叠以形成电容C。
例如，在上述的第二导电层330上形成有第二绝缘层，用于保护上述的第二导电层330。图6示出了该像素电路的源漏极金属层340，源漏极金属层340包括数据线Vd、第四电源信号线VDD3以及屏蔽线344。上述数据线Vd、第四电源信号线VDD3以及屏蔽线344均沿第一方向X延伸。屏蔽线344与数据线Vd同层同材料设置，使得屏蔽线可与数据线在同一次构图工艺中同时形成，避免为了制作屏蔽线而增加额外的构图工艺，从而简化了显示基板的制作流程，节约了制作成本。例如，源漏极金属层340还包括连接结构341、连接部342和电极连接部的第一子电极连接结构343。所述连接结构341的一端与所述驱动晶体管T1的栅极连接，所述连接结构341的另一端与所述阈值补偿晶体管T3的源漏区连接。
图6还示出了多个过孔的示例性位置，源漏金属层340通过所示的多个过孔与位于该源漏金属层340与衬底基板之间的多个膜层连接。例如，源漏金属层340通过过孔381、过孔382、过孔384、过孔387及过孔352连接至图2所示的有源半导体层310，源漏金属层340通过过孔3832、过孔386、过孔385、过孔332连接至图5所示的第二导电层330。
例如，在上述的源漏极金属层340上形成有第三绝缘层和第四绝缘层，用于保护上述的源漏极金属层340。各个子像素的有机发光元件可设置在第三绝缘层和第四绝缘层远离衬底基板的一侧。
图7示出了该像素电路的第三导电层350，第三导电层350包括电极连 接部的第二子电极连接结构353、沿第二方向延伸的第一电源信号线VDD1的第二子电源信号线VDD12、以及沿第一方向X延伸的第五电源信号线VDD4，第二子电源信号线VDD12与各第五电源信号线VDD4相交。第一电源信号线VDD1的具体结构将在后面图9至图16相关的描述中介绍。图7还示出了多个过孔351和过孔354的示例性位置，第三导电层350通过所示的多个过孔351和过孔354与源漏金属层340连接。
图8为上述的有源半导体层310、第一导电层320、第二导电层330、源漏极金属层340以及第三导电层350的层叠位置关系的示意图。如图2-8所示，数据线Vd通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔381)与有源半导体层310中的数据写入晶体管T2的源极区域相连。第四电源信号线VDD3通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔382)与有源半导体层310中对应的第一发光控制晶体管T4的源极区域相连。
如图2-8所示，连接结构341的一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔384)与有源半导体层310中对应的阈值补偿晶体管T3的漏极区域相连，连接结构341的另一端通过第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔385)与第一导电层320中的驱动晶体管T1的栅极(即电容C的第二极板CC2)相连。连接部342的一端通过第二绝缘层中的一个过孔(例如，过孔386)与复位电源信号线Init1相连，连接部342的另一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔387)与有源半导体层310中的第二复位晶体管T7的漏极区域相连。第一子电极连接结构343通过栅极绝缘层、第一绝缘层和第二绝缘层中的至少一个过孔(例如，过孔352)与有源半导体层310中的第二发光控制晶体管T5的漏极区域相连。需要说明的是，本申请实施例中采用的晶体管的源极区域和漏极区域在结构上可以是相同的，所以其源极区域和漏极区域在结构上可以是没有区别的，因此根据需要二者是可以互换的。
例如，如图2-7所示，第四电源信号线VDD3通过位于第二导电层330和源漏金属层340之间的第二绝缘层中的至少一个过孔(例如，过孔3832)与第二导电层330中的电容C的第一极板CC1相连。
例如，如图2-8所示，屏蔽线344沿第一方向X延伸，且其在衬底基板上的正投影位于相邻两个像素相应的数据线在衬底基板上的正投影之间。例如，屏蔽线能够减小相邻两个像素相应的数据线上传输的信号对阈值补偿晶体管T3的性能产生的影响，减弱串扰问题。
例如，如图2-8所示，屏蔽线344通过第二绝缘层中的至少一个过孔(例如过孔332)与复位电源信号线Init1相连，除了使得屏蔽线具有固定电位之外，还使得复位电源信号线上传输的初始化信号的电压更稳定，从而更有利于像素驱动电路的工作性能。
例如，如图2-8所示，屏蔽线344与复位电源信号线电连接，以使屏蔽线具有固定电位。屏蔽线344可分别与沿Y方向延伸的两条复位电源信号线Init1电连接，且这两条复位电源信号线Init1分别位于屏蔽线344沿X方向的两侧。例如，这两条复位电源信号线分别与第n行像素电路和第n+1行像素电路对应。
例如，同一列屏蔽线344可以为一整条屏蔽线，该整条屏蔽线包括多个位于相邻两条复位电源信号线之间的子部分，且每一子部分分别位于该列的每个像素电路区域内。同一列像素可共用一条屏蔽线344。
例如，除了将屏蔽线344与复位电源信号线耦接外，还可以将屏蔽线344与第一电源信号线耦接，使得屏蔽线344具有与第一电源信号线传输的电源信号相同的固定电位。
例如，如图2-7所示，第五电源信号线VDD4通过第三绝缘层和第四绝缘层中的至少一个过孔351与第四电源信号线VDD3相连，第二子电极连接结构353通过第三绝缘层和第四绝缘层中的过孔354与第一子电极连接结 构343相连。
例如，第三绝缘层可以为钝化层，第四绝缘层可以为平坦化层，第三绝缘层位于第四绝缘层与衬底基板之间。第四绝缘层可以为有机层，且有机层的厚度较钝化层等无机层厚。
例如，过孔351和过孔354均为嵌套过孔，即过孔351包括第三绝缘层中的第一过孔和第四绝缘层中的第二过孔，第三绝缘层中的第一过孔与第四绝缘层中的第二过孔的位置相对，且第四绝缘层中的第二过孔在衬底基板上的正投影位于第三绝缘层中的第一过孔在衬底基板上的正投影内。
例如，第五电源信号线VDD4在衬底基板上的正投影与第四电源信号线VDD3在衬底基板上的正投影大致重合，或者第四电源信号线VDD3在衬底基板上的正投影位于第五电源信号线VDD4在衬底基板上的正投影内，且第五电源信号线VDD4与第四电源信号线VDD3电连接可以降低第一电源信号线VDD1的电压降，从而改善显示器件的均一性。例如，第五电源信号线VDD4可以与源漏金属层采用相同的材料。
例如，如图6所示，各子像素的第一子电极连接结构343均为块状结构。后续形成的各颜色子像素的第一电极会通过过孔与相应的第二子电极连接结构353连接以实现与第二发光控制晶体管T5的漏极区域相连。
本实施例包括但不限于此，各子像素中的第二子电极连接结构的位置根据有机发光元件的排列规律以及发光区域的位置而定。
例如，子像素的第一子电极连接结构343通过栅极绝缘层、第一绝缘层以及第二绝缘层的过孔352与有源半导体层中的第二发光控制晶体管T5的第二极T5d相连。第一子电极连接结构343与第三电源信号线VDD2和发光控制信号线EM1均有交叠。第二子电极连接结构353通过位于第三绝缘层和第四绝缘层中的嵌套过孔354与第一子电极连接结构343相连，进而实现与第二发光控制晶体管相连。
例如，数据线Vd通过栅极绝缘层、第一绝缘层和第二绝缘层中的过孔381与数据写入晶体管T2的源极T2s相连；连接结构341的一端通过栅极绝缘层、第一绝缘层和第二绝缘层中的过孔384与阈值补偿晶体管T3的漏极T3d相连，连接结构341的另一端通过第一绝缘层和第二绝缘层中的过孔385与驱动晶体管T1的栅极(即电容C的第二极板CC2)相连；驱动晶体管T1的沟道T1c位于其栅极面向衬底基板的一侧，且与过孔385没有交叠，驱动晶体管T1的源极T1d与其栅极以及电容C的第一极板CC1均有交叠。
需要说明的是，每个像素电路中的驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路等的位置排布关系不限于图2-8所示的示例，根据实际应用需求，可以具体设置驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路的位置。
例如，子像素110的第一电极通过第五绝缘层的过孔(未示出)与第二子电极连接结构353相连，从而实现与第二发光控制晶体管T5的漏极区域相连。
如图9至图16所示，所述第一电源信号线VDD1包括沿第一方向X延伸的第一子电源信号线VDD1和沿第二方向Y延伸的第二子电源信号线VDD12。所述第二电源信号线VSS包括沿所述第一方向X延伸的第三子电源信号线VSS1和沿所述第二方向Y延伸的第四子电源信号线VSS2。
第二子电源信号线VDD12包括第一连接信号线VDD13和第二连接信号线VDD14。第一连接信号线VDD13与第一子电源信号线VDD11位于同一层，且与第一子电源信号段VDD11相连。第一子电源信号段VDD11与第一连接信号线VDD13可位于源漏金属层340。第二连接信号线VDD14与第一连接信号线VDD13位于不同层。第二连接信号线VDD14可位于第三导电层350。
例如，如图10及图11所示，第二连接信号线VDD14与第五电源信号线VDD4相交，第二连接信号线VDD14通过第三绝缘层和第四绝缘层的通孔与第一连接信号线VDD13相连。
第二电源信号线VSS的第三子电源信号线VSS1和第四子电源信号线VSS2相交，且可位于同一层，第三子电源信号线VSS1和第四子电源信号线VSS2可位于第三导电层350。
在一个实施例中，如图10至图12、图14至图16所示，所述显示基板还包括与所述第二电源信号线VSS连接的搭接部40。搭接部40可与第二电源信号线VSS同层设置。
如图12及图16所示，所述子像素包括第一电极21和第二电极22，同一像素中各子像素共用一个第二电极22。显示基板还可包括像素限定层，像素限定层设有多个像素开口23。第一电极21及像素开口23均位于发光区AA1。每一子像素对应一个像素开口，且子像素的像素开口23在衬底基板上的正投影位于第一电极21在衬底基板上的正投影内。
在一个实施例中，如图12所示，至少存在相邻两个所述像素的第二电极22与同一所述搭接部40接触。第二电极与搭接部接触指的是，第二电极通过其与搭接部之间的绝缘层的接触孔与搭接部接触。如此设置，相邻两个像素的第二电极22与同一个搭接部40接触来实现与第二电源信号线VSS的电连接，相对于各像素的第二电极分别通过不同的搭接部接触的方案来说，可减小搭接部及接触孔的数量，提升显示基板的透光率；并且各像素的第二电极分别通过同一搭接部与第二电源信号线的方案中，各像素的第二电极均需要设置的较大以与搭接部40在膜层的层叠方向上重叠与搭接部接触，本实施例中通过设置至少两个像素的第二电极与同一搭接部40接触，可减小显示基板中第二电极的总面积，有助于提升显示基板的透光率；并且本实施例可减小第二电源信号线VSS的子电源信号线的数量，也有助于提升显示基板的透光率。
进一步地，至少存在相邻两个所述像素的第二电极22通过同一所述搭接部40与所述第三子电源信号线VSS1电连接，或者通过同一所述搭接部40与所述第四子电源信号线VSS2电连接。图12所示的实施例中，相邻两个像素的第二电极22通过同一搭接部40与同一第四子电源信号线VSS2电连接。在其他实施例中，相邻两个像素的第二电极22可通过同一搭接部40与同一第三子电源信号线VSS1电连接。
显示基板的多个子像素中，在第二方向Y上间隔排布的多个像素为一行像素，在第一方向X上间隔排布的多个像素为一列像素。
在一个实施例中，相邻两行子像素的第二电极可分别通过搭接部连接至同一第四子电源信号线VSS2。具体来说，相邻两行像素中，在第一方向X上相邻的两个像素的第二电极与同一搭接部40接触。如此设置，相对于不同行像素的第二电极与不同的第四子电源信号线VSS2的方案来说，第四子电源信号线VSS2的数量可减少一半。
进一步地，相邻两行子像素之间设有在第二方向Y上间隔排布的多个搭接部40，且在所述第二方向Y上排布的多个所述搭接部40通过所述第四子电源信号线VSS2电连接。
在另一实施例中，相邻两列像素的第二电极可分别通过搭接部连接至同一第三子电源信号线VSS1。具体来说，相邻两列子像素中，在第二方向Y上相邻的两个子像素的第二电极与同一搭接部40接触。如此设置，相对于不同列像素的第二电极与不同的第三子电源信号线VSS1的方案来说，第三子电源信号线VSS1的数量可减少一半。
在该实施例中，相邻两列像素之间设有在第一方向X上间隔排布的多个搭接部40，且在所述第一方向X上排布的多个所述搭接部40通过所述第三子电源信号线VSS1电连接。
在一个实施例中，如图16所示，至少存在相邻四个所述像素的第二电 极22与同一所述搭接部40接触，相邻四个所述像素排列为两行两列。如此设置，显示基板的第二电极的总面积更小，且搭接部40的数量更少，第二电源信号线VSS的子电源信号线的数量更少，因此更有助于提升显示基板的透光率。
进一步地，所述搭接部40在衬底基板上的正投影位于相邻四个像素的第二电极22在衬底基板上的正投影之间。
进一步地，如图16所示，至少存在相邻四个所述像素的第二电极22通过同一所述搭接部40连接至所述第三子电源信号线VSS1及所述第四子电源信号线VSS2。相邻四个所述像素排列为两行两列，该两行像素之间设有一条第四子电源信号线VSS2，该两列像素之间设有一条第三子电源信号线VSS1，搭接部40位于四个像素之间，因此搭接部40既与第三子电源信号线VSS1连接，又与第四子电源信号线VSS2连接。
进一步地，至少存在一个所述搭接部40与在所述第一方向X上排布的其他所述搭接部通过所述第三子电源信号线VSS1电连接，且与在所述第二方向Y上排布的其他所述搭接部通过所述第四子电源信号线VSS2连接。如此设置，更有助于减小第二电源信号线VSS的子电源信号线的数量，从而进一步提升显示基板的透光率。
在一个实施例中，显示基板包括多个搭接部40，每一搭接部40分别与相邻四个像素的第二电极接触，多个搭接部40排列为多行多列。在第一方向X上间隔排布的多个搭接部40通过所述第三子电源信号线VSS1连接，在第二方向Y上排布的多个搭接部40通过所述第四子电源信号线VSS2连接。
在一个实施例中，如图12及图16所示，所述显示基板还包括与所述第二电极22连接的电极连接结构24，与同一所述搭接部40接触的各所述第二电极22连接至同一所述电极连接结构24，所述第二电极22通过所述电极连接结构24与所述搭接部40接触。与同一所述搭接部40接触的多个所述第 二电极22对应的电极连接结构24位于多个第二电极22之间，以便于电极连接结构24与各第二电极22相连。电极连接结构24与第二电极22可同层设置。
在一个实施例中，所述第一电源信号线VDD1包括多个子电源信号线VDD11、VDD12，每一所述子电源信号线沿所述第一方向延伸或沿所述第二方向延伸，至少存在相邻两个所述像素的像素电路与所述第一电源信号线的同一子电源信号线相连。如此设置，可减少第一电源信号线VDD1的子电源信号线的数量，提升显示基板的透光率。图12所示的实施例中，在第二方向Y上相邻的两个子像素的像素电路与同一第以子电源信号线VDD11相连。
在一个实施例中，如图9至图16所示，所述第一电源信号线VDD1的至少一条所述第一子电源信号线VDD11通过所述第二电源信号线VDD12与所述像素电路电连接；至少部分所述第二子电源信号线VDD12与所述第一子电源信号线VDD11异层设置。如此设置，可避免源漏金属层340中用于驱动像素的驱动信号线与第二子电源信号线VDD12短路。图9至图16所示的实施例中，所述第二子电源信号线VDD12包括第一连接信号线VDD13和第二连接信号线VDD14，第二连接信号线VDD14与第一子电源信号线VDD11异层设置。
进一步地，所述显示基板还包括与所述第一子电源信号线同层设置的驱动信号线，所述驱动信号线被配置为为所述像素电路提供驱动信号。所述第二子电源信号线VDD12与所述第一子电源信号线VDD11异层设置的部分在所述衬底基板上的正投影与所述驱动信号线在所述衬底基板上的正投影存在交叠。如此设置，既可保证第一子电源信号线VDD11通过第二子电源信号线VDD12与像素电路电连接，也可避免第二子电源信号线VDD12与驱动信号线短路。图9至图16所示的实施例中，驱动信号线包括数据线Vd，所述第二子电源信号线VDD12的第二连接信号线VDD14与第一子电源信号线VDD11异层设置，第二连接信号线VDD14在衬底基板上的正投影与数据线 Vd在衬底基板上的正投影存在交叠。
在一个实施例中，如图12至图16所示，所述像素限定层设有位于所述非发光区AA2的开孔25。通过在像素限定层上开设位于非发光区AA2的开孔25，可提升非发光区AA2的透光率。所述像素限定层上可开设有多个开孔25。
进一步地，如图12至图16所示，所述开孔25在所述衬底基板上的正投影至少部分位于所述第二电极22在所述衬底基板上的正投影、所述第二电源信号线VSS在所述衬底基板上的正投影、以及所述第一电源信号线VDD1在所述衬底基板上的正投影之外。
图12及图16所示的实施例中，所述开孔25在所述衬底基板上的正投影均位于所述第二电极22在所述衬底基板上的正投影之外。如此可避免第二电极22下方的膜层的高度差较小，避免第二电极22发生爬坡断裂的情况。
图12及图16所示的实施例中，所述开孔25在所述衬底基板上的正投影位于所述第一电源信号线VDD1在所述衬底基板上的正投影之外。具体来说，所述开孔25在衬底基板上的正投影位于第一电源信号线VDD1的第一子电源信号线VDD11在衬底基板上的正投影之外，所述开孔25在衬底基板上的正投影与第一电源信号线VDD1的第二子电源信号线VDD12在衬底基板上的正投影存在部分交叠。
图12及图16所示的实施例中，所述开孔25在所述衬底基板上的正投影均位于所述第二电源信号线VSS在所述衬底基板上的正投影之外。
在一个实施例中，如图17所示，所述第一电源信号线VDD1在所述衬底基板上的正投影与所述第二电源信号线VSS在所述衬底基板上的正投影无交叠。如此设置，可避免第一电源信号线VDD1与第二电源信号线VSS在显示基板的膜层叠层方向上存在交叠，交叠区域的透光率较小，而影响显示基板的透光率；且可避免显示面板工作过程中，第一电源信号线VDD1与第二 电源信号线VSS的交叠区域产生的热量较多，交叠区域容易发生灼伤，从而有助于提升显示基板的使用寿命。
在一个实施例中，如图17所示，所述第一电源信号线VDD1包括沿第一方向X延伸的第一子电源信号线VDD11、沿第二方向Y延伸的第二子电源信号线VDD12、以及多个沿所述第二方向Y延伸的第一连接段63；所述第二电源信号线VSS包括沿所述第一方向X延伸的第三子电源信号线VSS1、沿所述第二方向Y延伸的第四子电源信号线VSS2、以及多个沿所述第二方向Y延伸的第二连接段53。各所述第一子电源信号线VDD11包括在所述第一方向X上间隔排布的多个第一子信号段61，各所述第二子电源信号线VDD12包括在所述第二方向Y上间隔排布的多个第二子信号段62，各所述第一子信号段61分别与至少一个所述第二子信号段62连接，且相连的第一子信号段61与第二子信号段62在衬底基板上的正投影交叉。各所述第三子电源信号线VSS1包括在所述第一方向X上间隔排布的多个第三子信号段51，各所述第四子电源信号线VSS2包括在所述第二方向Y上间隔排布的多个第四子信号段52，各所述第三子信号段51分别与至少一个所述第四子信号段52连接，且相连的第三子信号段51与第四子信号段52在衬底基板上的正投影交叉。
在所述第二方向Y上相邻的所述第一子信号段61通过所述第一连接段63连接，至少一个所述第一连接段63在所述衬底基板上的正投影位于相邻的两个所述第三子信号段51在所述衬底基板上的正投影之间。在所述第二方向Y上相邻的所述第三子信号段51通过所述第二连接段53连接；至少一个所述第二连接段53在所述衬底基板上的正投影位于相邻的两个所述第一子信号段61在所述衬底基板上的正投影之间。
通过上述的设置方式，可使得第一电源信号线VDD1的各第一子信号段61及各第二子信号段62均电连接，第二电源信号线VSS的各第三子信号段51及各第四子信号段52均电连接，同时可减小第一电源信号线VDD1与第二电源信号线在衬底基板上的正投影存在交叠的区域，从而提升显示基板 的透光率及使用寿命。
进一步地，各所述第一连接段63在所述衬底基板上的正投影分别位于相邻的两个所述第三子信号段51在所述衬底基板上的正投影之间，各所述第二连接段53在所述衬底基板上的正投影分别位于相邻的两个所述第一子信号段61在所述衬底基板上的正投影之间。如此可使得第一电源信号线VDD1与第二电源信号线在衬底基板上的正投影不存在交叠。
在一个实施例中，所述第一连接段63与第一电源信号线VDD1的第一子电源信号线VDD11可同层设置，第二连接段53与第二电源信号线VSS同层设置。如此设置，有助于简化显示基板的制备工艺复杂度。
在一个实施例中，所述显示基板还设有多个驱动信号线驱动信号线被配置为为像素电路提供驱动信号。至少一个所述驱动信号线位于所述发光区的部分的宽度大于位于所述非发光区的部分的宽度。通过设置驱动信号线位于非发光区的宽度较小，有助于提升非发光区的透光率，进而提升显示基板的透光率；通过设置驱动信号线位于发光区的部分宽度较大，可避免驱动信号线位于非发光区的部分电阻较大，进而导致发光区的热量升高较快。
如图4及图5所示，驱动信号线包括复位控制信号线Rst1、扫描信号线Ga1、发光控制信号线EM1及第三电源信号线VDD2。复位控制信号线Rst1、复位控制信号线Rst2、扫描信号线Ga1、发光控制信号线EM1及第三电源信号线VDD2位于发光区AA1的部分的宽度均大于其位于非发光区AA2的部分的宽度。
在一个实施例中，至少一个所述扫描信号线Ga1位于所述发光区AA1的部分的宽度大于位于所述非发光区AA2的部分的宽度；所述扫描信号线Ga1位于所述发光区AA1的部分的宽度范围为3.5μm～5.5μm，所述扫描信号线Ga1位于所述非发光区AA2的部分的宽度范围为2μm～3.5μm。通过设置扫描信号线Ga1位于所述非发光区AA2的部分的宽度范围为2μm～3.5μm，既可 避免扫描信号线Ga1位于非发光区AA2的部分宽度太小导致其电阻较大，也可避免扫描信号线Ga1位于非发光区AA2的部分宽度太大导致其影响非发光区的透光率。在一些实施例中，所述扫描信号线Ga1位于发光区AA1的部分的宽度可以是3.5μm、3.8μm、4.0μm、4.5μm、5.0μm、5.5μm等，所述扫描信号线Ga1位于非发光区AA2的部分的宽度可以是2μm、2.3μm、2.5μm、3.0μm、3.2μm、3.5μm等。
在一个实施例中，如图18所示，所述显示基板还包括位于所述显示区AA至少一侧的边框区CC，所述显示基板还包括位于所述边框区CC的辅助走线70，所述辅助走线70与所述第二电极22电连接。辅助走线70可通过第二电源信号线VSS与辅助走线70电连接。辅助走线可降低第二电极22的电阻，从而改善第二电极22的IR drop问题。
所述辅助走线70包括第一导电膜层71及位于所述第一导电膜层71背离所述衬底基板一侧的第二导电膜层72，所述第一导电膜层71在所述衬底基板上的正投影靠近所述显示区AA的边缘位于所述第二导电膜层72在所述衬底基板上的正投影靠近所述显示区AA的边缘内侧。如此设置，可保证第二导电膜层72与第一导电膜层71的搭接效果。
进一步地，第一导电膜层在所述衬底基板上的正投影远离所述显示区AA的边缘位于所述第二导电膜层72在所述衬底基板上的正投影远离所述显示区AA的边缘内侧，以更有效地保证第二导电膜层72与第一导电膜层71的搭接效果。
在一些实施例中，所述第一导电膜层71与第一电极21同层设置，所述第二导电膜层72与第二电极22同层设置。辅助走线70还可包括位于第一导电层与衬底基板之间的第三导电膜层，第三导电膜层可位于源漏金属层。
在一个实施例中，所述显示基板还可包括位于所述像素上方的封装层。封装层可以是薄膜封装层，包括交替排布的有机层和无机层，且最上方为无 机层。
本申请实施例还提供了一种显示面板，所述显示面板包括上述任一实施例所述的显示基板。
所述显示面板还可包括位于显示基板背离衬底一侧的玻璃盖板。
本申请实施例还提供了一种显示装置，所述显示装置包括上述的显示面板。显示装置还可包括外壳，显示面板可嵌入在外壳中。
本实施例中的显示装置可以为：电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、车载显示设备等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (21)

  1. 一种显示基板，其特征在于，所述显示基板包括显示区，所述显示区的至少部分区域为透明显示区；所述显示基板包括衬底基板及位于所述衬底基板上且位于所述透明显示区的多个像素；所述像素包括多个子像素，所述子像素包括有机发光元件和驱动所述有机发光元件的像素电路；所述有机发光元件包括第一电极、第二电极及位于所述第一电极与所述第二电极之间的有机发光材料；所述子像素的第一电极与像素电路电连接；所述第一电极的数量大于所述第二电极的数量；
    所述显示基板还设有第一电源信号线和第二电源信号线，所述像素电路与所述第一电源信号线相连，所述第二电极与所述第二电源信号线相连；所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线；和/或，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线；所述第一方向与所述第二方向相交。
  2. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括与所述第二电源信号线电连接的搭接部，至少存在相邻两个所述像素的第二电极与同一所述搭接部接触。
  3. 根据权利要求2所述的显示基板，其特征在于，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线时，至少存在相邻两个所述像素的第二电极通过同一所述搭接部与所述第三子电源信号线电连接，或者通过同一所述搭接部与所述第四子电源信号线电连接。
  4. 根据权利要求3所述的显示基板，其特征在于，在所述第一方向上排布的多个所述搭接部通过所述第三子电源信号线电连接，和/或，在所述第二方向上排布的多个所述搭接部通过所述第四子电源信号线电连接。
  5. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括与所述第二电源信号线电连接的搭接部，至少存在相邻四个所述像素的第二电极与同一所述搭接部接触，相邻四个所述像素排列为两行两列。
  6. 根据权利要求5所述的显示基板，其特征在于，所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线时，至少存在相邻四个所述像素的第二电极通过同一所述搭接部连接至所述第三子电源信号线及所述第四子电源信号线。
  7. 根据权利要求6所述的显示基板，其特征在于，所述显示基板包括多个所述搭接部，至少存在一个所述搭接部与在所述第一方向上排布的其他所述搭接部通过所述第三子电源信号线电连接，且与在所述第二方向上排布的其他所述搭接部通过所述第四子电源信号线电连接。
  8. 根据权利要求2至7任一项所述的显示基板，其特征在于，所述显示基板还包括与所述第二电极连接的电极连接结构，与同一所述搭接部接触的各所述第二电极连接至同一所述电极连接结构，所述第二电极通过所述电极连接结构与所述搭接部接触。
  9. 根据权利要求1所述的显示基板，其特征在于，所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线时，至少存在相邻两个所述像素的像素电路与所述第一电源信号线的同一所述第一子电源信号线相连，或者与同一所述第二子电源信号线相连。
  10. 根据权利要求1所述的显示基板，其特征在于，所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线时，至少一条所述第一子电源信号线通过所述第二子电源信号线与所述像素电路电连接；
    至少部分所述第二子电源信号线与所述第一子电源信号线异层设置。
  11. 根据权利要求10所述的显示基板，其特征在于，所述显示基板还 包括与所述第一子电源信号线同层设置的驱动信号线，所述驱动信号线被配置为为所述像素电路提供驱动信号；所述第二子电源信号线与所述第一子电源信号线异层设置的部分在所述衬底基板上的正投影与所述驱动信号线在所述衬底基板上的正投影存在交叠。
  12. 根据权利要求1所述的显示基板，其特征在于，所述第一电源信号线在所述衬底基板上的正投影与所述第二电源信号线在所述衬底基板上的正投影无交叠。
  13. 根据权利要求12所述的显示基板，其特征在于，所述第一电源信号线包括沿第一方向延伸的第一子电源信号线和沿第二方向延伸的第二子电源信号线，且所述第二电源信号线包括沿所述第一方向延伸的第三子电源信号线和沿所述第二方向延伸的第四子电源信号线时，所述第一电源信号线还包括多个沿所述第二方向延伸的第一连接段；所述第二电源信号线还包括多个沿所述第二方向延伸的第二连接段；各所述第一子电源信号线包括在所述第一方向上间隔排布的多个第一子信号段，各所述第二子电源信号线包括在所述第二方向上间隔排布的多个第二子信号段，各所述第一子信号段分别与至少一个所述第二子信号段相连；各所述第三子电源信号线包括在所述第一方向上间隔排布的多个第三子信号段，各所述第四子电源信号线包括在所述第二方向上间隔排布的多个第四子信号段，各所述第三子信号段分别与至少一个所述第四子信号段相连；
    在所述第二方向上相邻的所述第一子信号段通过所述第一连接段连接，在所述第二方向上相邻的所述第三子信号段通过所述第二连接段连接；至少一个所述第一连接段在所述衬底基板上的正投影位于相邻的两个所述第三子信号段在所述衬底基板上的正投影之间；至少一个所述第二连接段在所述衬底基板上的正投影位于相邻的两个所述第一子信号段在所述衬底基板上的正投影之间。
  14. 根据权利要求1所述的显示基板，其特征在于，所述透明显示区 包括发光区及非发光区；所述像素设置在所述发光区；
    所述显示基板还设有多个驱动信号线；至少一个所述驱动信号线位于所述发光区的部分的宽度大于位于所述非发光区的部分的宽度。
  15. 根据权利要求14所述的显示基板，其特征在于，所述驱动信号线包括扫描信号线，所述扫描信号线被配置为为所述像素提供扫描信号；
    至少一个所述扫描信号线位于所述发光区的部分的宽度大于位于所述非发光区的部分的宽度；所述扫描信号线位于所述发光区的部分的宽度范围为3.5μm～5.5μm，所述扫描信号线位于所述非发光区的部分的宽度范围为2μm～3.5μm。
  16. 根据权利要求1所述的显示基板，其特征在于，所述像素电路包括驱动晶体管，所述显示基板还包括有源半导体层，所述有源半导体层包括各所述子像素的驱动晶体管的沟道；
    在至少一个所述像素中，至少一个所述子像素的驱动晶体管的沟道包括顺次连接的第一区段、第二区段、第三区段、第四区段和第五区段，所述第一区段、所述第三区段及所述第五区段沿所述第二方向延伸，所述第二区段及所述第四区段沿所述第一方向延伸；至少一个所述子像素的驱动晶体管的沟道包括顺次连接的第六区段、第七区段和第八区段，所述第六区段与所述第八区段沿所述第二方向延伸，所述第七区段沿所述第一方向延伸。
  17. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括屏蔽线及复位电源信号线，所述复位电源信号线被配置为为所述子像素提供复位电源信号；所述屏蔽线与所述复位电源信号线电连接。
  18. 根据权利要求1所述的显示基板，其特征在于，所述透明显示区包括发光区与非发光区，所述像素位于所述发光区；所述显示基板还包括像素限定层，所述像素限定层设有位于所述非发光区的开孔；
    所述开孔在所述衬底基板上的正投影至少部分位于所述第二电极在所 述衬底基板上的正投影、所述第二电源信号线在所述衬底基板上的正投影、以及所述第一电源信号线在所述衬底基板上的正投影之外。
  19. 根据权利要求1所述的显示基板，其特征在于，所述显示基板还包括位于所述显示区至少一侧的边框区，所述显示基板还包括位于所述边框区的辅助走线，所述辅助走线与所述第二电极电连接；所述辅助走线包括第一导电膜层及位于所述第一导电膜层背离所述衬底基板一侧的第二导电膜层，所述第一导电膜层在所述衬底基板上的正投影靠近所述显示区的边缘位于所述第二导电膜层在所述衬底基板上的正投影靠近所述显示区的边缘内侧。
  20. 一种显示面板，其特征在于，所述显示面板包括权利要求1至19任一项所述的显示基板。
  21. 一种显示装置，其特征在于，所述显示装置包括权利要求20所述的显示面板。
PCT/CN2022/077463 2022-02-23 2022-02-23 显示基板、显示面板及显示装置 WO2023159388A1 (zh)

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