WO2021217993A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021217993A1
WO2021217993A1 PCT/CN2020/114559 CN2020114559W WO2021217993A1 WO 2021217993 A1 WO2021217993 A1 WO 2021217993A1 CN 2020114559 W CN2020114559 W CN 2020114559W WO 2021217993 A1 WO2021217993 A1 WO 2021217993A1
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WIPO (PCT)
Prior art keywords
anode
base substrate
orthographic projection
display substrate
area
Prior art date
Application number
PCT/CN2020/114559
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English (en)
French (fr)
Inventor
杨路路
尚庭华
张国梦
王裕
姜晓峰
张鑫
和玉鹏
屈忆
刘彪
都蒙蒙
董向丹
马宏伟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20904234.0A priority Critical patent/EP4145519A4/en
Priority to US17/299,565 priority patent/US11903274B2/en
Priority to CN202080002061.5A priority patent/CN114097090A/zh
Publication of WO2021217993A1 publication Critical patent/WO2021217993A1/zh
Priority to US18/539,847 priority patent/US20240114736A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • the embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • the embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate includes: a base substrate; a pixel circuit layer on the base substrate; an anode layer located on the side of the pixel circuit layer away from the base substrate, and the pixel circuit layer includes a plurality of pixel drivers A circuit, the anode layer includes a plurality of anodes, the plurality of pixel driving circuits are arranged in a one-to-one correspondence with the plurality of anodes, and the plurality of anodes includes a plurality of anodes arranged in an array along a first direction and a second direction Group, each of the anode groups includes a first anode and a second anode disposed opposite to each other in the second direction, the first anode includes a first main body portion and a first connecting portion, the first connecting portion and the
  • the pixel drive circuit corresponding to the first anode is electrically connected, the first anode further includes an extension portion and an anode compensation portion, and
  • the extended first centerline is located on the first side of the second centerline of the first main body portion extending in the second direction, and the anode compensation portion has a first point on the side away from the second centerline
  • the first body portion has a second point on the first side, a line connecting the first anode, the first point and the second point encloses a gap area, and the area of the gap area is larger than At least one of the area of the anode compensation part and the area of the first connection part.
  • the display substrate designs the shape of the first anode so that the extension of the first anode avoids the light-transmitting area of the display substrate as much as possible, thereby improving the light transmittance of the display substrate.
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate; a pixel circuit layer on the base substrate; an anode layer located on a side of the pixel circuit layer away from the base substrate,
  • the pixel circuit layer includes a plurality of pixel driving circuits, the anode layer includes a plurality of anodes, the plurality of pixel driving circuits are arranged in a one-to-one correspondence with the plurality of anodes, and the plurality of anodes includes A plurality of anode groups arranged in an array in the second direction, each of the anode groups includes a first anode and a second anode disposed opposite to each other in the second direction, and the first anode includes a first body portion and a first connection Part, the first connection part is electrically connected to the pixel drive circuit corresponding to the first anode, the first anode further includes an extension part and an anode compensation part, the anode compensation part is on the base substrate
  • One side of the two center lines has a first point
  • the first main body has a second point on the first side
  • the first anode is surrounded by a line connecting the first point and the second point
  • the area of the gap area is larger than at least one of the area of the anode compensation portion and the area of the first connecting portion.
  • the area of the notch area is larger than the sum of the area of the anode compensation part and the area of the first connection part.
  • the anode compensation portion is located on the first side of the second center line of the first main body portion extending along the second direction.
  • the extension portion includes a first extension portion and a second extension portion, and the first extension portion is located at a distance of the first connecting portion away from the first main body portion.
  • the second extension portion is respectively connected to the first extension portion and the anode compensation portion, and the first extension portion is located on a side of the second extension portion away from the anode compensation portion.
  • the third center line of the first extension portion extending in the second direction is located at the first body portion extending in the second direction.
  • Two second sides of the center line, the second side being opposite to the first side.
  • the first extension portion is located on the second side of the second center line that the first main body portion extends along the second direction.
  • the orthographic projection of the notch area on the base substrate and the orthographic projection of the first anode on the base substrate do not overlap.
  • the fourth center line extending along the second direction of the first connecting portion is located at the second center line of the second center line of the first main body portion.
  • One side is located at the fourth center line of the second center line of the first main body portion.
  • each of the pixel driving circuits includes a driving thin film transistor and a compensation thin film transistor, and the drain of the driving thin film transistor and the source of the compensation thin film transistor are connected to the first Node, the orthographic projection of the anode compensation portion on the base substrate covers the first node of the pixel drive circuit connected to the first connection portion.
  • the size of the first connecting portion in the first direction is smaller than the size of the first main body portion in the first direction, and the first extension portion The size in the first direction is smaller than the size of the first connecting portion in the first direction.
  • each of the anode groups further includes a third anode and a fourth anode; in each of the anode groups, the first anode and the second anode form an anode Yes, the third anode, the anode pair, and the fourth anode are sequentially arranged along the first direction, and the first anode and the second anode are sequentially arranged along the second direction.
  • the notch area includes a first notch located between the first main body part and the anode compensation part, and the first notch is in the base substrate.
  • the orthographic projection includes a first edge and a second edge extending along the second direction, the first edge is connected with the orthographic projection of the first connecting portion on the base substrate, and the second The edge is located on the line connecting the first point and the second point.
  • the area of the orthographic projection of the first notch on the base substrate is larger than the area of the orthographic projection of the first connecting portion on the base substrate 1/2.
  • the notch area further includes a second notch located between the first notch and the anode compensation part, and the second notch is on the base substrate.
  • the orthographic projection on the upper surface includes a fourth edge and a fifth edge extending along the second direction, the fourth edge is in contact with the orthographic projection of the first extension on the base substrate, and the fifth The edge is also located on the line connecting the first point and the second point.
  • the area of the orthographic projection of the second notch on the base substrate is larger than the area of the orthographic projection of the first connecting portion on the base substrate 1/2.
  • the second anode includes a second body portion and a second connection portion, and the second connection portion is electrically connected to the pixel driving circuit corresponding to the second anode.
  • the first node of the pixel drive circuit that is electrically connected to the second connection portion, the first connection portion and The second connecting portion is arranged axisymmetrically with respect to a symmetry axis parallel to the first direction, the first connecting portion is located on the side of the first main body away from the second main body, and the second The connecting part is on a side of the second main body part away from the first main body part.
  • the second anode further includes a first supplementary portion, and the first supplementary portion protrudes from the second main body portion in a direction approaching the first anode ,
  • the channel region of the compensation thin film transistor in the pixel drive circuit that is electrically connected to the second connection portion of the orthographic projection on the base substrate of the first supplementary portion is on the base substrate
  • each of the pixel driving circuits further includes a storage capacitor and a light emission control line
  • the storage capacitor includes a first electrode plate arranged in a direction perpendicular to the base substrate.
  • the first main body portion is located on the side of the light emission control line in the pixel drive circuit connected to the first connection portion away from the storage capacitor, and the anode compensation portion is located on the side The light-emitting control line is away from a side of the first main body part.
  • each of the pixel driving circuits further includes a data line and a power line.
  • the second electrode plate is on the base substrate.
  • the orthographic projection, the orthographic projection of the light-emitting control line on the base substrate, the data line and the power line enclose a first interval area, and the first extension is on the front of the base substrate.
  • the area of the projection covering the first interval area is less than 1/2 of the total area of the first interval area.
  • each of the pixel driving circuits further includes an initialization signal line, and the light emission control line in the pixel driving circuit corresponding to the first anode is on the substrate.
  • the orthographic projection on the substrate, the orthographic projection of the initialization signal line in the pixel drive circuit corresponding to the second anode on the base substrate, the data line and the power line enclose a second interval Area, the area of the orthographic projection of the first anode on the base substrate covering the second interval area is less than 2/3 of the total area of the second interval area.
  • the third anode includes a third main body portion and a third connection portion, and the third connection portion is electrically connected to the pixel driving circuit corresponding to the third anode.
  • the fourth anode includes a fourth main body portion and a fourth connection portion, and the fourth connection portion is electrically connected to the pixel driving circuit corresponding to the fourth anode.
  • the fourth anode further includes a second supplementary portion protruding from the fourth main body portion in a direction approaching the second anode, and the fourth anode Orthographic projection of the second supplementary part on the base substrate Orthographic projection of the channel region of the compensation thin film transistor in the pixel drive circuit electrically connected to the third connection part on the base substrate At least partially overlap.
  • the fourth anode further includes a third supplementary portion protruding from the fourth main body portion in a direction away from the second anode, and the second anode Orthographic projection of three supplementary parts on the base substrate Orthographic projection of the channel region of the compensation thin film transistor in the pixel drive circuit electrically connected to the first connection part on the base substrate At least partially overlap.
  • the display substrate provided by an embodiment of the present disclosure further includes: a pixel defining layer located on a side of the anode layer away from the base substrate; and a light emitting layer located on a side of the anode layer away from the base substrate.
  • the pixel defining layer includes a plurality of openings, the plurality of openings are arranged in a one-to-one correspondence with the plurality of anodes, each of the openings partially exposes the corresponding anode, and the light-emitting layer includes a plurality of light-emitting parts, The plurality of light-emitting parts are arranged in a one-to-one correspondence with the plurality of openings, and at least a part of each of the light-emitting parts is located in the corresponding opening and covers the corresponding exposed part of the anode.
  • the plurality of openings are divided into a plurality of opening groups, each of the opening groups includes a first opening and a second opening, and the plurality of light emitting parts are divided into a plurality of opening groups.
  • each of the light-emitting part groups includes a first light-emitting part and a second light-emitting part
  • the orthographic projection of the first opening on the base substrate falls into the first body part on the base substrate
  • the orthographic projection on the upper part at least a part of the first light-emitting part is located in the first opening and covers the exposed part of the first body part, which is on the base substrate
  • the shape of the orthographic projection of the first opening is similar to the shape of the orthographic projection of the first opening on the base substrate.
  • the pixel circuit layer includes: a semiconductor layer located on the base substrate; and a first gate layer located on the semiconductor layer away from the base substrate
  • the semiconductor layer includes a plurality of pixel driving units, which are arranged in a one-to-one correspondence with the plurality of anodes, and each of the pixel driving units includes a first unit, a second unit, a third unit, a fourth unit, and a first unit.
  • the first cell includes a first channel region and a first source region and a first drain region located on both sides of the first channel region.
  • the second The cell includes a second channel region and a second source region and a second drain region located on both sides of the second channel region.
  • the third cell includes a third channel region and a second drain region located on both sides of the second channel region.
  • the third source region and the third drain region on both sides of the region, the fourth cell includes a fourth channel region and a fourth source region and a fourth drain region located on both sides of the fourth channel region.
  • the fifth cell includes a fifth channel region and a fifth source region and a fifth drain region located on both sides of the fifth channel region, and the sixth cell includes a sixth channel region and a fifth drain region located on both sides of the fifth channel region.
  • the sixth source region and the sixth drain region on both sides of the sixth channel region, the seventh cell includes a seventh channel region and a seventh source region located on both sides of the seventh channel region and A seventh drain region, the third source region, the first drain region, and the fifth source region are connected to the first node, the sixth drain region and the third drain
  • the electrode regions are connected, the first source region, the second drain region, and the fourth drain region are connected to a second node, and the fifth drain region is connected to the seventh drain region
  • the first gate layer includes a reset signal line, a gate line, a first electrode block, and a light emission control line, and the reset signal line overlaps the seventh channel region and the sixth channel region to overlap with
  • the seventh cell and the sixth cell form a seventh thin film transistor and a sixth thin film transistor
  • the gate line overlaps the third channel region and the second channel region to overlap with the
  • the third cell and the second cell form a third thin film transistor and a second thin film transistor
  • the first electrode block overlaps the first channel region to form
  • the reset signal line, the gate line, and the light emission control line all extend along the first direction, and the reset signal line, the gate line, the first The electrode blocks and the light emission control line are arranged along the second direction.
  • the pixel circuit layer includes: a second gate layer located on a side of the first gate layer away from the semiconductor layer; and the second gate
  • the layer includes an initialization signal line and a second electrode block, the initialization signal line is connected to the seventh source region and the sixth source region, and the orthographic projection of the second electrode block on the base substrate is the same as the first electrode block.
  • the orthographic projection of an electrode block on the base substrate at least partially overlaps to form a storage capacitor.
  • the pixel circuit layer further includes: a source and drain electrode layer located on a side of the second gate layer away from the first gate layer, and the source The drain electrode layer includes the data line and the power line, the second source region is connected to the data line, and the fourth source region is connected to the power line.
  • the source-drain electrode layer further includes: a connection block, including a first terminal and a second terminal, the first terminal and the drain region of the compensation thin film transistor The second end is connected to the first electrode block, and the orthographic projection of the anode compensation portion on the base substrate covers the orthographic projection of the second end on the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate of any one of the above.
  • FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a display substrate along the section line A-A in FIG. 1 according to an embodiment of the present disclosure
  • 3A is a schematic plan view of an anode layer in a display substrate provided by an embodiment of the present disclosure
  • 3B is a schematic plan view of a first anode and a second anode in a display substrate provided by an embodiment of the present disclosure
  • 3C is a schematic plan view of another anode layer in a display substrate provided by an embodiment of the present disclosure.
  • 4A-4D are schematic plan views of various functional film layers in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate includes a base substrate; a pixel circuit layer on the base substrate; an anode layer located on the side of the pixel circuit layer away from the base substrate; the pixel circuit layer includes a plurality of pixel driving circuits, and the anode layer includes a plurality of anodes, A plurality of pixel driving circuits are arranged in a one-to-one correspondence with a plurality of anodes.
  • the plurality of anodes include a plurality of anode groups arranged in an array along a first direction and a second direction, and each anode group includes a first electrode set opposite to each other in the second direction.
  • the first anode includes a first body portion and a first connection portion, the first connection portion is electrically connected to the pixel driving circuit corresponding to the first anode, and the first anode further includes an extension portion and an anode compensation portion,
  • the orthographic projection of the anode compensation part on the base substrate covers a thin film transistor in the pixel drive circuit connected to the first connection part.
  • the first main body part and the anode compensation part at least partially overlap in the first direction.
  • the first center line extending in the second direction is located on the first side of the second center line of the first main body part extending in the second direction, the anode compensation part has a first point on the side away from the second center line, and the first main body part There is a second point on the first side, and the line connecting the first anode and the first point and the second point encloses a gap area, and the area of the gap area is larger than at least one of the area of the anode compensation part and the area of the first connection part .
  • the display substrate designs the shape of the first anode so that the extension of the first anode avoids the light-transmitting area of the display substrate as much as possible, thereby improving the light transmittance of the display substrate.
  • FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure along the section line AA in FIG. 1
  • FIG. 3A is an implementation of the present disclosure The example provides a schematic plan view of the anode layer in the display substrate
  • FIG. 3B is a schematic plan view of the first anode and the second anode in the display substrate provided by an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate 110, a pixel circuit layer 210, and an anode layer 170; the pixel circuit layer 210 is disposed on the base substrate 110, and the anode layer 170 is disposed on the pixel circuit.
  • the layer 210 is away from the side of the base substrate.
  • the pixel circuit layer 210 includes a plurality of pixel driving circuits 215, the anode layer 170 includes a plurality of anodes 175, and the plurality of pixel driving circuits 215 and the plurality of anodes 175 are arranged in one-to-one correspondence, that is, one pixel driving circuit 215 corresponds to one anode 175. , And is electrically connected to the corresponding anode 175 to provide the corresponding anode 175 with electrical signals for driving the sub-pixels to emit light.
  • the plurality of anodes 175 includes a plurality of anode groups 1750 arranged in an array along a first direction and a second direction, and each anode group 1750 includes a first anode 1751 and a second anode 1752 disposed oppositely.
  • the first anode 1751 includes a first main body portion 1751A and a first connection portion 1751B.
  • the first connection portion 1751B is electrically connected to the pixel driving circuit 215 corresponding to the first anode 1751, so that the pixel driving circuit 215 can pass through the first connection portion 1751B.
  • An electrical signal for driving the sub-pixel to emit light is applied to the first anode 1751 including the first body portion 1751A.
  • the first anode 1751 further includes an extension portion 1751F and an anode compensation portion 1751E.
  • the orthographic projection of the anode compensation portion 1751E on the base substrate 110 covers the pixels connected to the first connection portion 1751B.
  • the first body portion 1751A and the anode compensation portion 1751E at least partially overlap in the first direction, and the first center line 701 of the anode compensation portion 1751E extending in the second direction is located in the first body portion 1751A
  • the anode compensation portion 1751E On the first side of the second centerline 702 extending in the second direction, the anode compensation portion 1751E has a first point P1 on the side away from the second centerline 702, and the first body portion 1751A has a second point P2 on the first side
  • the first anode 1751 and the line P12 of the first point P1 and the second point P2 enclose a gap area 450, the area of the gap area 450 is larger than at least one of the area of the anode compensation portion 1751E and the area of the first connection portion 1751B .
  • the extension part is used to connect the anode compensation part with the first connection part;
  • the area of the notch area is larger than at least one of the area of the anode compensation portion and the area of the first connection portion, so that the overlapping area of the extension portion and the light-transmitting area of the pixel driving circuit can be reduced. Therefore, the design of the first anode can make the extension of the first anode avoid the light-transmitting area of the display substrate as much as possible, thereby improving the light transmittance of the display substrate. Since the display substrate has a high light transmittance, a photosensitive device such as a camera and a fingerprint recognition module can be arranged under the display substrate.
  • the transmittance of at least two of all the film layers from the base substrate 110 of the display substrate to the anode layer 170 is greater than 90 %.
  • the area of the notch area 450 is larger than the sum of the area of the anode compensation portion 1751E and the area of the first connecting portion 1751B.
  • the display substrate can further reduce the overlapping area of the extension portion and the light-transmitting area of the pixel driving circuit, thereby further improving the light transmittance of the display substrate.
  • the anode compensation portion 1751E is located on the first side of the second center line of the first main body portion 1751A extending in the second direction. That is, the anode compensation portion 1751E is all located on the first side of the second center line of the first main body portion 1751A extending in the second direction.
  • the orthographic projection of the notch area 450 on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 do not overlap.
  • the notch area 450 does not belong to the first anode, but the area enclosed by the first anode and the line P12 between the first point P1 and the second point P2.
  • the distance between the first centerline 701 of the anode compensation portion 1751E and the second centerline 702 of the first main body portion 1751A is greater than or equal to the distance between the anode compensation portion 1751E 1/2 of the width in the first direction.
  • the fourth centerline 703 of the first connecting portion 1751B extending in the second direction substantially coincides with the second centerline 702 of the first main body portion 1751A.
  • the above-mentioned “approximately coincident” includes the situation that the fourth center line and the second center line completely overlap, and also includes that the distance between the fourth center line and the second center line is smaller than the first center line. In the case of 1/10 of the width of the connecting portion in the first direction.
  • the embodiments of the present disclosure include but are not limited thereto, and the fourth center line extending along the second direction of the first connecting portion may also be located on the first side of the first main body portion.
  • 3C is a schematic plan view of another anode layer in a display substrate provided by an embodiment of the present disclosure.
  • the fourth center line 703 of the first connecting portion 1751B of the first anode 1751 extending in the second direction is also located on the first side of the second center line 702 of the first main body portion 1751A extending in the second direction. That is, the fourth center line 703 and the first center line 701 extending in the second direction of the anode compensation portion 1751E are located on the same side of the second center line 702.
  • the fourth center line 703 of the first connecting portion 1751B is located on the side of the first center line 701 away from the second center line 702.
  • the first anode can make the first connecting portion avoid the light-transmitting area of the display substrate as much as possible, thereby further improving the light transmittance of the display substrate.
  • each pixel driving circuit 215 includes a driving thin film transistor T1 and a compensation thin film transistor T3.
  • the drain D1 of the driving thin film transistor T1 and the source S3 of the compensation thin film transistor T3 are connected to the first node N1.
  • the orthographic projection of the anode compensation portion 1751E on the base substrate 110 covers the first node N1 of the pixel driving circuit 215 connected to the first connection portion 1751B, that is, the orthographic projection of the anode compensation portion 1751E on the base substrate 110 and The orthographic projection of the first node N1 of the pixel driving circuit 215 connected to the first connecting portion 1751B on the base substrate 110 at least partially overlaps.
  • the shape and size of the first anode and the second anode, the first anode 1751 and the second anode 1752 of the same anode pair 1758 are configured to drive the sub-pixels to emit light of the same color.
  • the main body part of 1752 covers the first node N1 of the corresponding pixel driving circuit 215, while the first main body part 1751 does not cover the first node N1 of the corresponding pixel driving circuit 215. Therefore, the above-mentioned anode is added to the first anode 1751.
  • the compensation portion 1751E, and the orthographic projection of the anode compensation portion 1751E on the base substrate 110 covers the first node N1 of the pixel driving circuit 215 connected to the first connection portion 1751B, which can balance the first anode 1751 and the corresponding first node
  • the load between N1 and the load between the second anode 1752 and the corresponding first node N1 can improve the display quality.
  • the extension portion 1751F further includes a first extension portion 1751C and a second extension portion 1751D.
  • the first extension portion 1751C is located on the side of the first connecting portion 1751B away from the first main body portion 1751A.
  • the two extension portions 1751D are respectively connected to the first extension portion 1751C and the anode compensation portion 1751E, and the first extension portion 1751C is located on the side of the second extension portion 1751D away from the anode compensation portion 1751E. Therefore, the first extension is located on the side of the first connecting part away from the first main body. At this time, the first extension extends from the first connecting part instead of extending from the first main body, so that the first extension can be reduced.
  • the first node N1 may be a connection block 1542 provided on the same layer as the data line 152 and the power line 151 in the pixel driving circuit 215.
  • the specific settings of the connection block 1542 will be described in detail in the following layered schematic diagram.
  • the third centerline 703 of the first extension portion 1751C extending in the second direction is located on the second centerline 702 of the first main body portion 1751A extending in the second direction. Side, the second side is opposite to the first side.
  • the first anode can make the first extension part avoid the light-transmitting area of the display substrate as much as possible, thereby improving the light transmittance of the display substrate.
  • the first extension portion 1751C is located on the second side of the second center line 702 of the first main body portion 1751A extending in the second direction. That is, the first extension portion 1751C is all located on the second side of the second center line of the first main body portion 1751A extending in the second direction, so that the overlap between the first extension portion and the light-transmitting area of the display substrate can be further reduced. Area, thereby further improving the light transmittance of the display substrate.
  • FIG. 1 the first extension portion 1751C is located on the second side of the second center line 702 of the first main body portion 1751A extending in the second direction. That is, the first extension portion 1751C is all located on the second side of the second center line of the first main body portion 1751A extending in the second direction, so that the overlap between the first extension portion and the light-transmitting area of the display substrate can be further reduced. Area, thereby further improving the light transmittance of the display substrate.
  • the size of the first connecting portion 1751B in the first direction is smaller than the size of the first main body portion 1751A in the first direction
  • the size of the first extension portion 1751C in the first direction is smaller than The size of the first connecting portion 1751B in the first direction, the first direction being perpendicular to the arrangement direction of the first main body portion 1751A, the first connecting portion 1751B, and the first extension portion 1751C.
  • the first anode 1751 and the second anode 1752 are arranged along a second direction, the second direction is perpendicular to the first direction, and both the first direction and the second direction are located on a plane parallel to the base substrate 110. Therefore, the area occupied by the first extension portion 1751C in the first direction is small, and the overlap area of the first extension portion and the light-transmitting area of the pixel driving circuit can be reduced, thereby improving the light transmittance of the display substrate.
  • each anode group 1750 further includes a third anode 1753 and a fourth anode 1754; in each anode group 1750, the first anode 1751 and the second anode 1752 constitute an anode pair 1758 ; The third anode 1753, the anode pair 1758, and the fourth anode 1754 are sequentially arranged along the first direction, and the first anode 1751 and the second anode 1752 are sequentially arranged along the second direction.
  • the above-mentioned first direction may be the arrangement direction of the third anode, the anode pair, and the fourth anode.
  • the above-mentioned first direction may be the row direction of the sub-pixel arrangement in the display substrate, that is, the extending direction of the gate line.
  • the embodiments of the present disclosure include but are not limited thereto, and the above-mentioned first direction may also be the column direction of the sub-pixel arrangement, that is, the extension direction of the data line.
  • the above-mentioned notch area 450 includes a first notch 451 located between the first body portion 1751A and the anode compensation portion 1751E, and the first notch 451 is on the base substrate.
  • the orthographic projection on the 110 includes a first edge 401 and a second edge 402 extending in the second direction. The first edge 401 is in contact with the orthographic projection of the first connecting portion 1751B on the base substrate 110, and the second edge 402 is located On the line P12 between the point P1 and the second point P2.
  • the first anode 1751 has a gap between the first main body portion 1751A and the anode compensation portion 1751E, and the area between the first main body portion 1751A and the anode compensation portion 1751E corresponds to the light-transmitting area of the pixel driving circuit, so Therefore, the display substrate can reduce the overlap area of the first anode and the light-transmitting area of the pixel driving circuit, thereby improving the light transmittance.
  • the edge of the first notch 451 close to the first body portion 1751A is connected to the first body portion 1751A, and the edge of the first notch 451 away from the first body portion 1751A is aligned with the edge of the first connecting portion 1751B away from the first body portion 1751A. flat.
  • the area of the orthographic projection of the first notch 451 on the base substrate 110 is greater than 1/ of the area of the orthographic projection of the first connecting portion 1751B on the base substrate 110. 2.
  • the area of the first notch is relatively large, so that the display substrate can greatly reduce the overlapping area of the first anode and the light-transmitting area of the pixel driving circuit, thereby improving the light transmittance.
  • the above-mentioned notch area 450 further includes a second notch 452, which is located between the first notch 451 and the anode compensation portion 452, and the second notch 452 is on the base substrate 110
  • the orthographic projection includes a fourth edge 404 and a fifth edge 405 extending in the second direction.
  • the fourth edge 404 is in contact with the orthographic projection of the first extension 1751C on the base substrate 110, and the fifth edge 405 is also located in the first On the line P12 between the point P1 and the second point P2.
  • the first extension of the first anode is retracted by a certain distance relative to the edge of the first main body, so that the first anode can avoid the light-transmitting area of the corresponding pixel driving circuit as much as possible, thereby increasing The light transmittance of the display substrate.
  • the first gap 451 further includes an edge connected with the anode compensation portion 1851E, an edge connected with the second extension portion 1751D, and an edge connected with the second gap 452.
  • the above-mentioned first notch 451 and the second notch 452 can form the above-mentioned notch area 450.
  • the area of the orthographic projection of the second notch 452 on the base substrate 110 is greater than 1/ of the area of the orthographic projection of the first connecting portion 1751B on the base substrate 110. 2.
  • the area of the second notch is relatively large, so that the display substrate can greatly reduce the overlap area of the first anode and the light-transmitting area of the pixel driving circuit, thereby improving the light transmittance.
  • the second anode 1752 includes a second body portion 1752A and a second connection portion 1752B, and the second connection portion 1752B is electrically connected to the pixel driving circuit 215 corresponding to the second anode 1752.
  • the orthographic projection of the second main body portion 1752A on the base substrate 110 covers the first node N1 of the pixel driving circuit 215 electrically connected to the second connecting portion 1752B.
  • the orthographic projection of the anode compensation part 1751E on the base substrate 110 covers the first node N1 of the pixel driving circuit 215 connected to the first connection part 1751B, the first anode and the second anode both cover the corresponding pixel driving The first node of the circuit, so that the load of the two is the same, which can improve the display quality.
  • the first connecting portion 1751B and the second connecting portion 1752B are arranged axisymmetrically about a symmetry axis parallel to the first direction; the first body portion 1751A and the second body portion
  • the 1752A can also be arranged axisymmetrically about the symmetry axis.
  • the first connecting portion 1751B is on the side of the first body portion 1751A away from the second body portion 1752A, and the second connecting portion 1752B is on the side of the second body portion 1752A away from the first body portion 1751A.
  • each pixel driving circuit 215 further includes a storage capacitor Cst and a light emission control line 133.
  • the storage capacitor Cst includes a first electrode plate CE1 arranged in a direction perpendicular to the base substrate 110.
  • the second electrode plate CE2; the first body portion 1751A is located on the side of the emission control line 133 of the pixel driving circuit 215 connected to the first connection portion 1751B away from the storage capacitor Cst, and the anode compensation portion 1751E is located on the emission control line 133 away from the first One side of the main body 1751A.
  • each pixel driving circuit 215 further includes a data line 152 and a power supply line 151.
  • the orthographic projection of the second electrode plate CE2 on the base substrate 110, the orthographic projection of the light-emitting control line 133 on the base substrate 110, the data line 152 and the power line 151 enclose a first spaced area 610
  • the orthographic projection of the first extension portion 1751C on the base substrate 110 covers an area of the first spacer region 610 that is less than 1/2 of the total area of the first spacer region 610.
  • the first interval area between the second electrode plate and the light-emitting control line is usually a light-transmitting area, because the orthographic projection of the first extension on the base substrate covers the area of the first interval area smaller than the first interval area. 1/2 of the total area of the spacer area, the display substrate can effectively reduce the overlap area of the first anode and the light-transmitting area of the corresponding pixel driving circuit, thereby improving the light transmittance of the display substrate.
  • the area covered by the orthographic projection of the first extension portion 1751C on the base substrate 110 may be less than 1/3 of the total area of the first interval area 610.
  • each pixel driving circuit 215 further includes an initialization signal line 141, and the light emission control line 133 in the pixel driving circuit 215 corresponding to the first anode 1751 is positive on the base substrate 110.
  • the projection, the orthographic projection of the initialization signal line 141 in the pixel drive circuit 215 corresponding to the second anode 1752 on the base substrate 110, the data line 152 and the power line 151 enclose the second spacer area 620, and the first anode 1751 is on the substrate
  • the area of the orthographic projection on the substrate 110 covering the second spacer region 620 is less than 2/3 of the total area of the second spacer region 620.
  • the second spacer area is usually a light-transmitting area. Since the orthographic projection of the first anode on the base substrate covers the area of the second spacer area less than 2/3 of the total area of the second spacer area, the display The substrate can effectively reduce the overlapping area of the light-transmitting area of the first anode and the corresponding pixel driving circuit, thereby improving the light transmittance of the display substrate.
  • the orthographic projection of the first anode 1751 on the base substrate 110 covers an area of the second spacer region 620 that is less than 1/2 of the total area of the second spacer region 620.
  • the display substrate 100 further includes a pixel defining layer 190 and a light emitting layer 180; the pixel defining layer 190 is located on the side of the anode layer 170 away from the base substrate 110, and the light emitting layer 180 is located on the anode layer 170. A side away from the base substrate 110.
  • the pixel defining layer 190 includes a plurality of openings 195, and the plurality of openings 195 are arranged in a one-to-one correspondence with the plurality of anodes 175, and each opening 195 partially exposes the corresponding anode 175;
  • the light emitting layer 180 includes a plurality of light emitting parts 185,
  • a plurality of openings 195 are arranged in one-to-one correspondence, and at least a part of each light-emitting portion 185 is located in the corresponding opening 195 and covers the exposed portion of the corresponding anode 175.
  • each opening group 1950 includes a first opening 1951 and a second opening 1952
  • the plurality of light-emitting parts 185 are divided into a plurality of light-emitting part groups.
  • each light-emitting part group 1850 includes a first light-emitting part 1851 and a second light-emitting part 1852; the orthographic projection of the first opening 1951 on the base substrate 110 falls within the orthographic projection of the first body part 1751A on the base substrate 110 Inside, at least a part of the first light-emitting portion 1851 is located in the first opening 1951 and covers the exposed portion of the first body portion 1751A.
  • the shape of the orthographic projection of the first body portion 1751A on the base substrate 110 is the same as that of the first opening 1951.
  • the shape of the orthographic projection on the base substrate 110 is similar.
  • the second light-emitting portion 1852 is located in the second opening 1952 and covers the exposed portion of the second body portion 1752A.
  • the orthographic projection of the second body portion 1752A on the base substrate 110 is The shape is similar to the shape of the orthographic projection of the second opening 1952 on the base substrate 110.
  • the third light-emitting portion 1853 is located in the third opening 1953 and covers the exposed portion of the third body portion 1753A.
  • the orthographic projection of the third body portion 1753A on the base substrate 110 is The shape is similar to the shape of the orthographic projection of the third opening 1953 on the base substrate 110.
  • the fourth light-emitting portion 1854 is located in the fourth opening 1954 and covers the exposed portion of the fourth body portion 1754A.
  • the orthographic projection of the fourth body portion 1754A on the base substrate 110 is The shape is similar to the shape of the orthographic projection of the fourth opening 1954 on the base substrate 110.
  • the first light-emitting part and the second light-emitting part are configured to emit light of the same color.
  • the first light-emitting part is configured to emit green light
  • the third light-emitting part is configured to emit red light
  • the fourth light-emitting part is configured to emit blue light.
  • the embodiments of the present disclosure include but are not limited to this.
  • the pixel circuit layer 210 includes a semiconductor layer 120 and a first gate layer 130; the semiconductor layer 120 is located on the base substrate 110, and the first gate layer 130 is located on the semiconductor layer 120 away from the substrate. One side of the substrate 110.
  • FIG. 4A-4D are schematic plan views of various functional film layers in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is an equivalent circuit diagram of a pixel driving circuit in a display substrate provided by an embodiment of the disclosure.
  • the semiconductor layer 120 includes a plurality of pixel driving units 125, which are arranged in one-to-one correspondence with the plurality of anodes 175; each pixel driving unit 125 includes a first unit 1251, a second unit 1252, and a third unit 1253. , The fourth cell 1254, the fifth cell 1255, the sixth cell 1256, and the seventh cell 1257.
  • the first cell 1251 includes a first channel region C1 and a first source region S1 located on both sides of the first channel region C1 and The first drain region D1
  • the second cell 1252 includes a second channel region C2, and a second source region S2 and a second drain region D2 located on both sides of the second channel region C2
  • the third cell 1253 includes a third channel region C2.
  • the fourth cell 1254 includes the fourth channel region C4 and located on both sides of the fourth channel region C4
  • the fourth source region S4 and the fourth drain region D4 includes a fifth channel region C5 and a fifth source region S5 and a fifth drain region D5 located on both sides of the fifth channel region C5
  • the sixth cell 1256 includes a sixth channel region C6 and a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6, and the seventh cell 1257 includes a seventh channel region C7 and The seventh source region S7 and the seventh drain region D7 on both sides of the seventh channel region C7.
  • the third source region S3, the first drain region D1, and the fifth source region S5 are connected to the first node N1, and the sixth drain region S6 and the third drain region D3 is connected, the first source region S1, the second drain region D2, and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 is connected to the seventh drain region D7.
  • the first gate layer 130 includes a reset signal line 131, a gate line 132, a first electrode block CE1 and a light emission control line 133, the reset signal line 131 and the seventh channel region C7 and The sixth channel region C6 overlaps with the seventh cell 1257 and the sixth cell 1256 to form the seventh thin film transistor T7 and the sixth thin film transistor T6.
  • the gate line 132 is connected to the third channel region C3 and the second channel region, respectively.
  • the first electrode block CE1 overlaps the first channel region C1 to form with the first cell 1251
  • the light emission control line 133 overlaps the fourth channel region C4 and the fifth channel region C5 to form the fourth thin film transistor T4 and the fifth thin film transistor T5 with the fourth cell 1254 and the fifth cell 1255;
  • the first thin film transistor T1 is a driving thin film transistor
  • the third thin film transistor T3 is a compensation thin film transistor.
  • the reset signal line, the gate line, and the light emission control line all extend in the first direction, and the reset signal line, the gate line, the first electrode block, and the light emission control line are arranged in the second direction.
  • the pixel circuit layer 210 includes: a second gate layer 140, which is located on the side of the first gate layer 130 away from the semiconductor layer 120; and the second gate layer 140 includes an initialization signal line 141 and a second gate layer.
  • the second electrode block CE2, the initialization signal line 141 is connected to the seventh source area S7 and the sixth source area S6, the orthographic projection of the second electrode block CE2 on the base substrate 110 is the same as the first electrode block CE1 on the base substrate 110 The orthographic projection on at least partially overlaps to form a storage capacitor Cst.
  • the second gate layer 140 further includes a conductive block 142.
  • the conductive block 142 may be connected to the power line, thereby reducing the resistance of the power line.
  • the orthographic projection of the conductive block 142 on the substrate 110 and the channel region of the compensation thin film transistor T3 at least partially overlap, thereby preventing light from directly irradiating the channel region of the compensation thin film transistor T3 and improving the stability of the compensation thin film transistor T3.
  • the pixel circuit layer 210 further includes a source and drain electrode layer 150, which is located on a side of the second gate layer 140 away from the first gate layer 130.
  • the source and drain electrode layer 150 includes data lines 152 and The power line 151, the second source region S2 is connected to the data line 152, and the fourth source region S4 is connected to the power line 151.
  • the source-drain electrode layer 210 further includes a first connection block 1541, a second connection block 1542 and a third connection block 1543.
  • the first connection block 1541 is used to connect the initialization signal line 141 to the sixth source region S6 and the seventh source region S7;
  • the second connection block 1542 is used to connect the third drain region D3 to the first electrode block CE1;
  • the third connecting block 1543 is connected to the fifth drain region D5, and can be used as a drain to connect to a corresponding anode.
  • the second connecting block 1542 includes a first terminal 1542A and a second terminal 1542B.
  • the first terminal 1542A is connected to the drain region D3 of the compensation thin film transistor T3, and the second terminal 1542B is connected to the first electrode block.
  • CE1 is connected, and the orthographic projection of the anode compensation part 1751E on the base substrate 110 covers the orthographic projection of the second end 1542B on the base substrate 110.
  • the second source region S2 is connected to the data line 152; the fourth source region S4 is connected to the power line 151.
  • the first cell 121, the second cell 122, the third cell 123, the fourth cell 124, the fifth cell 125, the sixth cell 126, and the seventh cell 127 of the semiconductor layer 120 can be connected to the reset signal line 131 and
  • the gate line 132 forms a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7.
  • a working mode of the pixel driving circuit shown in FIG. 5 will be schematically described below.
  • a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 through the seventh thin film transistor T7, thereby suppressing the Light emission caused by the residual current flowing through the anode of each sub-pixel.
  • the sixth thin film transistor T6 is turned on, and through the sixth thin film transistor T6 to the first gate of the first thin film transistor T1 and the storage
  • the first electrode block CE1 of the capacitor Cst is applied with the initialization voltage Vint, so that the first gate and the storage capacitor Cst are initialized. Initialization of the first gate can turn on the first thin film transistor T1.
  • the gate signal is transmitted to the gate line 132 and the data signal is transmitted to the data line 152
  • the second thin film transistor T2 and the third thin film transistor T3 are both turned on, and the second thin film transistor T2 and the third thin film transistor T3 are turned on.
  • the data voltage Vd is applied to the first gate.
  • the voltage applied to the first gate is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.
  • the power line 151 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1 so as to be less than the voltage applied to the two electrodes of the storage capacitor Cst.
  • the charge corresponding to the difference is stored in the storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.
  • both the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, so that the fourth thin film transistor T4 applies the driving voltage Vel to the fifth thin film transistor T5.
  • the driving voltage Vel passes through the first thin film transistor T1 which is turned on by the storage capacitor Cst, the corresponding driving voltage Vel and the voltage applied to the first gate through the storage capacitor Cst is the difference between the driving current Id and flows through the first thin film transistor In the first drain region D3 of T1, the driving current Id is applied to each sub-pixel through the fifth thin film transistor T5, so that the light-emitting layer of each sub-pixel emits light.
  • FIG. 6 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the second anode 1752 also includes a first supplementary portion 1752C.
  • the first supplementary portion 1752C protrudes from the second main body portion 1752A in a direction close to the first anode 1751.
  • the first supplementary portion 1752C is on the base substrate 110.
  • the orthographic projection above and the orthographic projection of the channel region of the compensation thin film transistor T3 in the pixel driving circuit 215 electrically connected to the second connecting portion 1752B on the base substrate 110 at least partially overlap.
  • the pixel driving circuit adopts a 7T1C pixel driving structure.
  • the stability of the driving thin film transistor T1 directly affects the long-term light-emitting stability of the organic light-emitting diode display device; in the charging phase, the driving thin film
  • the charging voltage on the gate of the transistor T1 is related to the state of the compensation thin film transistor T3.
  • thin film transistors are particularly sensitive to light. When the thin film transistor (especially the channel region) is exposed to light, the characteristics of the thin film transistor are likely to drift, which affects the normal operation of the pixel driving circuit.
  • the display substrate is provided with a first supplementary part on the second anode, and the orthographic projection of the first supplementary part on the base substrate is electrically connected to the second connecting part.
  • the channel region of the compensation thin film transistor in the pixel drive circuit is on the substrate
  • the orthographic projections on the substrate are at least partially overlapped. Therefore, the display substrate can block the channel region of the corresponding compensation thin film transistor through the first supplementary portion, thereby improving the stability and life of the compensation thin film transistor, thereby increasing The long-term luminescence stability and lifetime of the display substrate.
  • the channel region of the compensation thin film transistor T3 includes two channel regions and a common electrode between the two channel regions.
  • the compensation thin film transistor T3 may be a thin film transistor with a double gate structure, so that the reliability of the compensation thin film transistor can be improved.
  • the channel region of the compensation thin film transistor T3 includes a first channel region C31 and a second channel region C32 arranged at intervals, and the compensation thin film transistor T3 also includes a common channel region between the first channel region C31 and the second channel region C32. Electrode SE.
  • the orthographic projection of the common electrode SE of the compensation thin film transistor T3 on the base substrate 110 at least partially overlaps the first supplementary portion 1742C.
  • the first supplementary part can partially or completely shield the common electrode SE of the compensation thin film transistor T3, thereby further improving the stability and life of the compensation thin film transistor, and further improving the long-term light-emitting stability and life of the display substrate.
  • the third anode 1753 includes a third body portion 1753A and a third connection portion 1753B, and the third connection portion 1753B is electrically connected to the pixel driving circuit 215 corresponding to the third anode 1753
  • the fourth anode 1754 includes a fourth main body portion 1754A and a fourth connection portion 1754B, and the fourth connection portion 1754B is electrically connected to the pixel driving circuit 215 corresponding to the fourth anode 1754.
  • the fourth anode 1754 further includes a second supplementary portion 1754C, which protrudes from the fourth main body portion 1754A in a direction close to the second anode 1752; for example, the second supplementary portion 1754C is in the first In two directions, it is located on the side of the fourth connecting portion 1754B close to the fourth main body portion 1754A; the orthographic projection of the second supplementary portion 1754C on the base substrate 110 is compensated in the pixel driving circuit 215 electrically connected to the third connecting portion 1753B The orthographic projection of the channel region of the thin film transistor T3 on the base substrate 110 at least partially overlaps.
  • the display substrate can block the channel region of the compensation thin film transistor corresponding to the third anode through the second supplementary portion, thereby improving the stability and life of the compensation thin film transistor, and further improving the long-term light-emitting stability of the display substrate Sex and longevity.
  • the compensation thin film transistor T3 has a double gate structure, the channel region of the compensation thin film transistor T3 includes two channel regions and a common electrode between the two channel regions.
  • the fourth anode 1754 further includes a third supplementary portion 1754D, which protrudes from the fourth main body portion 1754A in a direction away from the second anode 1752, and the third supplementary portion 1754D is on the base substrate.
  • the orthographic projection on 110 and the orthographic projection of the channel region of the compensation thin film transistor T3 in the pixel driving circuit 215 electrically connected to the first connecting portion 1751B on the base substrate 110 at least partially overlap.
  • the display substrate can shield the channel region of the compensation thin film transistor corresponding to the first anode through the third supplementary portion, thereby improving the stability and life of the compensation thin film transistor, and further improving the long-term light-emitting stability of the display substrate Sex and longevity.
  • the compensation thin film transistor T3 has a double gate structure, the channel region of the compensation thin film transistor T3 includes two channel regions and a common electrode between the two channel regions.
  • FIG. 7 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the display device 800 includes the display substrate 100 of any one of the above. Therefore, the display device has beneficial effects corresponding to the beneficial effects of the display substrate, for example, the display device has a higher light transmittance.
  • the display device can improve the stability and life of the compensation thin film transistor, thereby improving the long-term light-emitting stability and life of the display substrate.
  • the display device may be an electronic product with a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.

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Abstract

一种显示基板和显示装置。该显示基板包括衬底基板、像素电路层和阳极层；像素电路层包括多个像素驱动电路，阳极层包括多个阳极；在各像素驱动电路中，多个阳极包括相对设置的第一阳极和第二阳极，第一阳极包括第一主体部和第一连接部，第一阳极还包括延伸部和阳极补偿部，阳极补偿部在衬底基板上的正投影覆盖与第一连接部相连的像素驱动电路的薄膜晶体管，阳极补偿部在远离第二中心线的一侧具有第一点，第一主体部在第一侧具有第二点，第一阳极与第一点和第二点的连线围成缺口区，缺口区的面积大于阳极补偿部的面积和第一连接部的面积中的至少之一。该显示基板可提高透光率。

Description

显示基板和显示装置
本申请要求于2020年04月26日递交的PCT专利申请第PCT/CN2020/086997号的优先权，在此全文引用上述PCT专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示技术因其具有自发光、广视角、广色域、高对比度、低功耗、高反应速度等优点已经越来越多地被应用于各种电子设备中。
另一方面，随着有机发光二极管显示技术的不断发展，人们对于有机发光二极管显示产品的功耗、色偏、亮度、稳定性等性能提出了更高的要求。
发明内容
本公开实施例提供一种显示基板和显示装置。该显示基板包括：衬底基板；像素电路层，在所述衬底基板上；阳极层，位于所述像素电路层远离所述衬底基板的一侧，所述像素电路层包括多个像素驱动电路，所述阳极层包括多个阳极，所述多个像素驱动电路与所述多个阳极一一对应设置，所述多个阳极包括沿第一方向和第二方向阵列排布的多个阳极组，各所述阳极组包括在所述第二方向上相对设置的第一阳极和第二阳极，所述第一阳极包括第一主体部和第一连接部，所述第一连接部与所述第一阳极对应的所述像素驱动电路电性相连，所述第一阳极还包括延伸部和阳极补偿部，所述阳极补偿部在所述衬底基板上的正投影覆盖与所述第一连接部相连的所述像素驱动电路中的一个薄膜晶体管，所述第一主体部和所述阳极补偿部在所述第一方向上至少部分交叠，所述阳极补偿部沿所述第二方向延伸的第一中心线位于所述第一主体部沿所述第二方向延伸的第二中心线的第一侧，所述阳极补偿部在远离所述第二中心线的一侧具有第一点，所述第一主体部在所述第一侧具有第二点，所述第一阳极与所述第一点和所述第二点的连线围成缺口区，所述缺口区的面积大于所述阳极 补偿部的面积和所述第一连接部的面积中的至少之一。该显示基板通过对第一阳极的形状进行设计，使得第一阳极的延伸部尽可能避开该显示基板的透光区域，从而可提高该显示基板的透光率。
本公开至少一个实施例提供一种显示基板，其包括：衬底基板；像素电路层，在所述衬底基板上；阳极层，位于所述像素电路层远离所述衬底基板的一侧，所述像素电路层包括多个像素驱动电路，所述阳极层包括多个阳极，所述多个像素驱动电路与所述多个阳极一一对应设置，所述多个阳极包括沿第一方向和第二方向阵列排布的多个阳极组，各所述阳极组包括在所述第二方向上相对设置的第一阳极和第二阳极，所述第一阳极包括第一主体部和第一连接部，所述第一连接部与所述第一阳极对应的所述像素驱动电路电性相连，所述第一阳极还包括延伸部和阳极补偿部，所述阳极补偿部在所述衬底基板上的正投影覆盖与所述第一连接部相连的所述像素驱动电路中的一个薄膜晶体管，所述第一主体部和所述阳极补偿部在所述第一方向上至少部分交叠，所述阳极补偿部沿所述第二方向延伸的第一中心线位于所述第一主体部沿所述第二方向延伸的第二中心线的第一侧，所述阳极补偿部在远离所述第二中心线的一侧具有第一点，所述第一主体部在所述第一侧具有第二点，所述第一阳极与所述第一点和所述第二点的连线围成缺口区，所述缺口区的面积大于所述阳极补偿部的面积和所述第一连接部的面积中的至少之一。
例如，在本公开一实施例提供的显示基板中，所述缺口区的面积大于所述阳极补偿部的面积和所述第一连接部的面积之和。
例如，在本公开一实施例提供的显示基板中，所述阳极补偿部位于所述第一主体部沿所述第二方向延伸的第二中心线的所述第一侧。
例如，在本公开一实施例提供的显示基板中，所述延伸部包括第一延伸部和第二延伸部，所述第一延伸部位于所述第一连接部远离所述第一主体部的一侧，所述第二延伸部分别与所述第一延伸部和所述阳极补偿部相连，所述第一延伸部位于所述第二延伸部远离所述阳极补偿部的一侧。
例如，在本公开一实施例提供的显示基板中，所述第一延伸部沿所述第二方向延伸的第三中心线位于所述第一主体部沿所述第二方向延伸的所述第二中心线的第二侧，所述第二侧与所述第一侧相反。
例如，在本公开一实施例提供的显示基板中，所述第一延伸部位于所述第一主体部沿所述第二方向延伸的所述第二中心线的所述第二侧。
例如，在本公开一实施例提供的显示基板中，所述缺口区在所述衬底基板上的正投影与所述第一阳极在所述衬底基板上的正投影不交叠。
例如，在本公开一实施例提供的显示基板中，所述第一连接部沿所述第二方向延伸的第四中心线位于所述第一主体部的所述第二中心线的所述第一侧。
例如，在本公开一实施例提供的显示基板中，各所述像素驱动电路包括驱动薄膜晶体管和补偿薄膜晶体管，所述驱动薄膜晶体管的漏极与所述补偿薄膜晶体管的源极连接至第一节点，所述阳极补偿部在所述衬底基板上的正投影覆盖与所述第一连接部相连的所述像素驱动电路的所述第一节点。
例如，在本公开一实施例提供的显示基板中，所述第一连接部在所述第一方向上的尺寸小于所述第一主体部在第一方向上的尺寸，所述第一延伸部在所述第一方向上的尺寸小于所述第一连接部在所述第一方向上的尺寸。
例如，在本公开一实施例提供的显示基板中，各所述阳极组还包括第三阳极和第四阳极；在各所述阳极组内，所述第一阳极和所述第二阳极组成阳极对，所述第三阳极、所述阳极对和所述第四阳极沿所述第一方向依次排列，所述第一阳极和所述第二阳极沿第二方向依次排列。
例如，在本公开一实施例提供的显示基板中，所述缺口区包括第一缺口，位于所述第一主体部和所述阳极补偿部之间，所述第一缺口在所述衬底基板上的正投影包括沿所述第二方向延伸的第一边缘和第二边缘，所述第一边缘与所述第一连接部在所述衬底基板上的正投影相接，所述第二边缘位于所述第一点和所述第二点的连线上。
例如，在本公开一实施例提供的显示基板中，所述第一缺口在所述衬底基板上的正投影的面积大于所述第一连接部在所述衬底基板上的正投影的面积的1/2。
例如，在本公开一实施例提供的显示基板中，所述缺口区还包括第二缺口，位于所述第一缺口与所述阳极补偿部之间，所述第二缺口在所述衬底基板上的正投影包括沿所述第二方向延伸的第四边缘和第五边缘，所述第四边缘与所述第一延伸部在所述衬底基板上的正投影相接，所述第五边缘也位于所述第一点和所述第二点的连线上。
例如，在本公开一实施例提供的显示基板中，所述第二缺口在所述衬底基板上的正投影的面积大于所述第一连接部在所述衬底基板上的正投影的面积的1/2。
例如，在本公开一实施例提供的显示基板中，所述第二阳极包括第二主体部和第二连接部，所述第二连接部与所述第二阳极对应的所述像素驱动电路电性相连，所述第二主体部在所述衬底基板上的正投影覆盖与所述第二连接部电性相连的所述像素驱动电路的所述第一节点，所述第一连接部和所述第二连接部关于平行于所述第一方向的对称轴呈轴对称设置，所述第一连接部在所述第一主体部远离所述第二主体部的一侧，所述第二连接部在所述第二主体部远离第一主体部的一侧。
例如，在本公开一实施例提供的显示基板中，所述第二阳极还包括第一增补部，所述第一增补部从所述第二主体部沿靠近所述第一阳极的方向凸出，所述第一增补部在所述衬底基板上的正投影与所述第二连接部电性相连的所述像素驱动电路中的所述补偿薄膜晶体管的沟道区在所述衬底基板上的正投影至少部分交叠。
例如，在本公开一实施例提供的显示基板中，各所述像素驱动电路还包括存储电容和发光控制线，所述存储电容包括沿垂直于所述衬底基板的方向设置的第一电极板和第二电极板，所述第一主体部位于与所述第一连接部相连的所述像素驱动电路中的所述发光控制线远离所述存储电容的一侧，所述阳极补偿部位于所述发光控制线远离所述第一主体部的一侧。
例如，在本公开一实施例提供的显示基板中，各所述像素驱动电路还包括数据线和电源线，在各所述像素驱动电路，所述第二电极板在所述衬底基板上的正投影、所述发光控制线在所述衬底基板上的正投影、所述数据线和所述电源线围成第一间隔区域，所述第一延伸部在所述衬底基板上的正投影覆盖所述第一间隔区域的面积小于所述第一间隔区域的总面积的1/2。
例如，在本公开一实施例提供的显示基板中，各所述像素驱动电路还包括初始化信号线，所述第一阳极对应的所述像素驱动电路中的所述发光控制线在所述衬底基板上的正投影、所述第二阳极对应的所述像素驱动电路中的所述初始化信号线在所述衬底基板上的正投影、所述数据线和所述电源线围成第二间隔区域，所述第一阳极在所述衬底基板上的正投影覆盖所述第二间隔区域的面积小于所述第二间隔区域的总面积的2/3。
例如，在本公开一实施例提供的显示基板中，所述第三阳极包括第三主体部和第三连接部，所述第三连接部与所述第三阳极对应的所述像素驱动电路电性相连；所述第四阳极包括第四主体部和第四连接部，所述第四连接部与所述 第四阳极对应的所述像素驱动电路电性相连。
例如，在本公开一实施例提供的显示基板中，所述第四阳极还包括第二增补部，从所述从第四主体部沿着靠近所述第二阳极的方向凸出，所述第二增补部在所述衬底基板上的正投影与所述第三连接部电性相连的所述像素驱动电路中的所述补偿薄膜晶体管的沟道区在所述衬底基板上的正投影至少部分交叠。
例如，在本公开一实施例提供的显示基板中，所述第四阳极还包括第三增补部，从所述从第四主体部沿着远离所述第二阳极的方向凸出，所述第三增补部在所述衬底基板上的正投影与所述第一连接部电性相连的所述像素驱动电路中的所述补偿薄膜晶体管的沟道区在所述衬底基板上的正投影至少部分交叠。
例如，本公开一实施例提供的显示基板还包括：像素限定层，位于所述阳极层远离所述衬底基板的一侧；以及发光层，位于所述阳极层远离所述衬底基板的一侧，所述像素限定层包括多个开口，所述多个开口与所述多个阳极一一对应设置，各所述开口部分暴露对应的所述阳极，所述发光层包括多个发光部，所述多个发光部与所述多个开口一一对应设置，各所述发光部的至少一部分位于对应的所述开口之中并覆盖对应的所述阳极被暴露的部分。
例如，在本公开一实施例提供的显示基板中，所述多个开口划分为多个开口组，各所述开口组包括第一开口和第二开口，所述多个发光部划分为多个发光部组，各所述发光部组包括第一发光部和第二发光部，所述第一开口在所述衬底基板上的正投影落入所述第一主体部在所述衬底基板上的正投影之内，所述第一发光部的至少一部分位于所述第一开口之中并覆盖所述第一主体部被暴露的部分，所述第一主体部在所述衬底基板上的正投影的形状与所述第一开口在所述衬底基板上的正投影的形状相似。
例如，在本公开一实施例提供的显示基板中，所述像素电路层包括：半导体层，位于所述衬底基板上；以及第一栅极层，位于所述半导体层远离所述衬底基板的一侧，所述半导体层包括多个像素驱动单元，与所述多个阳极一一对应设置，各所述像素驱动单元包括第一单元、第二单元、第三单元、第四单元、第五单元、第六单元和第七单元，所述第一单元包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区域，所述第二单元包括第二沟道区和位于所述第二沟道区两侧的第二源极区和第二漏极区域，所述第三单元包括第 三沟道区和位于所述第三沟道区两侧的第三源极区和第三漏极区域，所述第四单元包括第四沟道区和位于所述第四沟道区两侧的第四源极区和第四漏极区域，所述第五单元包括第五沟道区和位于所述第五沟道区两侧的第五源极区和第五漏极区域，所述第六单元包括第六沟道区和位于所述第六沟道区两侧的第六源极区和第六漏极区域，所述第七单元包括第七沟道区和位于所述第七沟道区两侧的第七源极区和第七漏极区域，所述第三源极区、所述第一漏极区和所述第五源极区连接至所述第一节点，所述第六漏极区和所述第三漏极区相连，所述第一源极区、所述第二漏极区和所述第四漏极区连接至第二节点，所述第五漏极区和所述第七漏极区相连，所述第一栅极层包括复位信号线、栅线、第一电极块和发光控制线，所述复位信号线与所述第七沟道区和所述第六沟道区交叠，以与所述第七单元和所述第六单元形成第七薄膜晶体管和第六薄膜晶体管，所述栅线分别与所述第三沟道区和所述第二沟道区交叠，以与所述第三单元和所述第二单元形成第三薄膜晶体管和第二薄膜晶体管，所述第一电极块与所述第一沟道区交叠，以与所述第一单元形成第一薄膜晶体管，所述发光控制线与所述四沟道区和所述第五沟道区交叠，以与所述第四单元和所述第五单元形成第四薄膜晶体管和第五薄膜晶体管，所述第一薄膜晶体管为所述驱动薄膜晶体管，所述第三薄膜晶体管为所述补偿薄膜晶体管。
例如，在本公开一实施例提供的显示基板中，所述复位信号线、栅线和发光控制线均沿所述第一方向延伸，所述复位信号线、所述栅线、所述第一电极块和所述发光控制线沿所述第二方向排列。
例如，在本公开一实施例提供的显示基板中，所述像素电路层包括：第二栅极层，位于所述第一栅极层远离所述半导体层的一侧；所述第二栅极层包括初始化信号线和第二电极块，所述初始化信号线与所述第七源极区和第六源极区相连，所述第二电极块在衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影至少部分重叠以形成存储电容。
例如，在本公开一实施例提供的显示基板中，所述像素电路层还包括：源漏电极层，位于所述第二栅极层远离所述第一栅极层的一侧，所述源漏电极层包括所述数据线和所述电源线，所述第二源极区与所述数据线相连，所述第四源极区与所述电源线相连。
例如，在本公开一实施例提供的显示基板中，所述源漏电极层还包括：连接块，包括第一端和第二端，所述第一端与所述补偿薄膜晶体管的漏极区相连， 所述第二端与所述第一电极块相连，所述阳极补偿部在所述衬底基板上的正投影覆盖所述第二端在所述衬底基板上的正投影。
本公开至少一个实施例还提供一种显示装置，其包括上述任一项的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一实施例提供的一种显示基板的平面示意图；
图2为本公开一实施例提供的一种显示基板沿图1中剖切线A-A的剖面示意图；
图3A为本公开一实施例提供的一种显示基板中阳极层的平面示意图；
图3B为本公开一实施例提供的一种显示基板中第一阳极和第二阳极的平面示意图；
图3C为本公开一实施例提供的另一种显示基板中阳极层的平面示意图；
图4A-4D为本公开一实施例提供的一种显示基板中各功能膜层的平面示意图；
图5为本公开一实施例提供的一种显示基板中像素驱动电路的等效电路图；
图6为本公开一实施例提供的另一种显示基板的平面示意图；以及
图7为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二” 以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
随着有机发光二极管显示面板的普及和应用，对于发光二极管显示面板的透光率的要求也越来越高。如何提升有机发光二极管显示面板的透光率已经成为目前亟待解决的问题。
本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板；像素电路层，在衬底基板上；阳极层，位于像素电路层远离衬底基板的一侧；像素电路层包括多个像素驱动电路，阳极层包括多个阳极，多个像素驱动电路与多个阳极一一对应设置，多个阳极包括沿第一方向和第二方向阵列排布的多个阳极组，各阳极组包括在所述第二方向上相对设置的第一阳极和第二阳极，第一阳极包括第一主体部和第一连接部，第一连接部与第一阳极对应的像素驱动电路电性相连，第一阳极还包括延伸部和阳极补偿部，阳极补偿部在衬底基板上的正投影覆盖与第一连接部相连的像素驱动电路中的一个薄膜晶体管，第一主体部和阳极补偿部在第一方向上至少部分交叠，阳极补偿部沿第二方向延伸的第一中心线位于第一主体部沿第二方向延伸的第二中心线的第一侧，阳极补偿部在远离第二中心线的一侧具有第一点，第一主体部在第一侧具有第二点，第一阳极与第一点和第二点的连线围成缺口区，缺口区的面积大于阳极补偿部的面积和第一连接部的面积中的至少之一。该显示基板通过对第一阳极的形状进行设计，使得第一阳极的延伸部尽可能避开该显示基板的透光区域，从而可提高该显示基板的透光率。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
图1为本公开一实施例提供的一种显示基板的平面示意图；图2为本公开一实施例提供的一种显示基板沿图1中剖切线A-A的剖面示意图；图3A为本公开一实施例提供的一种显示基板中阳极层的平面示意图；图3B为本公开一实施例提供的一种显示基板中第一阳极和第二阳极的平面示意图。
如图1、图2和图3A所示，该显示基板100包括衬底基板110、像素电路层210和阳极层170；像素电路层210设置在衬底基板110上，阳极层170设置在像素电路层210远离衬底基板的一侧。像素电路层210包括多个像素驱动 电路215，阳极层170包括多个阳极175，多个像素驱动电路215和多个阳极175一一对应设置，也就是说，一个像素驱动电路215对应一个阳极175，并且与对应的阳极175电性相连以为对应的阳极175提供驱动子像素进行发光的电信号。
如图1和图3A所示，多个阳极175包括沿第一方向和第二方向阵列排布的多个阳极组1750，各阳极组1750包括相对设置的第一阳极1751和第二阳极1752。第一阳极1751包括第一主体部1751A和第一连接部1751B，第一连接部1751B与第一阳极1751对应的像素驱动电路215电性相连，从而使得像素驱动电路215可通过第一连接部1751B向包括第一主体部1751A的第一阳极1751施加驱动子像素进行发光的电信号。
如图1、图3A和图3B所示，第一阳极1751还包括延伸部1751F和阳极补偿部1751E，阳极补偿部1751E在衬底基板110上的正投影覆盖与第一连接部1751B相连的像素驱动电路215中的一个薄膜晶体管，第一主体部1751A和阳极补偿部1751E在第一方向上至少部分交叠，阳极补偿部1751E沿第二方向延伸的第一中心线701位于第一主体部1751A沿第二方向延伸的第二中心线702的第一侧，阳极补偿部1751E在远离第二中心线702的一侧具有第一点P1，第一主体部1751A在第一侧具有第二点P2，第一阳极1751与第一点P1和第二点P2的连线P12围成缺口区450，缺口区450的面积大于阳极补偿部1751E的面积和第一连接部1751B的面积中的至少之一。
在本公开实施例提供的显示基板中，延伸部用于将阳极补偿部与第一连接部相连；阳极补偿部沿第二方向延伸的第一中心线位于第一主体部沿第二方向延伸的第二中心线的第一侧，缺口区的面积大于阳极补偿部的面积和第一连接部的面积中的至少之一，从而可降低延伸部与像素驱动电路的透光区域的重叠面积。由此，该第一阳极的设计可使得第一阳极的延伸部尽可能避开该显示基板的透光区域，从而可提高该显示基板的透光率。由于该显示基板具有较高的透光率，因此可在显示基板下方设置摄像头、指纹识别模组等感光装置。
在一些示例中，如图1和图3A所示，在缺口区450中，从该显示基板的衬底基板110到阳极层170之间的所有膜层中的至少两个的透过率大于90％。
在一些示例中，如图1和图3A所示，缺口区450的面积大于阳极补偿部1751E的面积和第一连接部1751B的面积之和。由此，该显示基板可进一步降低延伸部与像素驱动电路的透光区域的重叠面积，从而进一步提高该显示基板 的透光率。
在一些示例中，如图1和图3A所示，阳极补偿部1751E位于第一主体部1751A沿第二方向延伸的第二中心线的第一侧。也就是说，阳极补偿部1751E全部位于第一主体部1751A沿第二方向延伸的第二中心线的第一侧。
在一些示例中，如图1和图3A所示，缺口区450在衬底基板110上的正投影与第一阳极1751在衬底基板110上的正投影不交叠。也就是说，缺口区450并不属于第一阳极，而是第一阳极与第一点P1和第二点P2的连线P12围成的区域。
在一些示例中，如图1、图3A和图3B所示，阳极补偿部1751E的第一中心线701与第一主体部1751A的第二中心线702之间的距离大于等于阳极补偿部1751E在第一方向上的宽度的1/2。
在一些示例中，如图1、图3A和图3B所示，第一连接部1751B沿第二方向延伸的第四中心线703与第一主体部1751A的第二中心线702大致重合。需要说明的是，由于工艺精度的限制，上述的“大致重合”包括第四中心线和第二中心线完全重合的情况，也包括第四中心线和第二中心线之间的距离小于第一连接部在第一方向上的宽度的1/10的情况。当然，本公开实施例包括但不限于此，第一连接部沿第二方向延伸的第四中心线也可位于第一主体部的第一侧。
图3C为本公开一实施例提供的另一种显示基板中阳极层的平面示意图。如图3C所示，第一阳极1751的第一连接部1751B沿第二方向延伸的第四中心线703也位于第一主体部1751A沿第二方向延伸的第二中心线702的第一侧。也就是说，第四中心线703与阳极补偿部1751E沿第二方向延伸的第一中心线701位于第二中心线702的同侧。
例如，第一连接部1751B的第四中心线703位于第一中心线701远离第二中心线702的一侧。由此，该第一阳极可使得第一连接部也尽量避开该显示基板的透光区域，从而进一步提高该显示基板的透光率。
在一些示例中，如图1所示，各像素驱动电路215包括驱动薄膜晶体管T1和补偿薄膜晶体管T3，驱动薄膜晶体管T1的漏极D1与补偿薄膜晶体管T3的源极S3连接至第一节点N1。阳极补偿部1751E在衬底基板110上的正投影覆盖与第一连接部1751B相连的像素驱动电路215的第一节点N1，也就是说，阳极补偿部1751E在衬底基板110上的正投影和与第一连接部1751B相 连的像素驱动电路215的第一节点N1在衬底基板110上的正投影至少部分重叠。由于像素排列结构、第一阳极和第二阳极的形状和尺寸等因素，同属一个阳极对1758的第一阳极1751和第二阳极1752被配置为驱动子像素发出同样颜色的光，由于第二阳极1752的主体部覆盖了对应的像素驱动电路215的第一节点N1，而第一主体部1751没有覆盖对应的像素驱动电路215的第一节点N1，因此，通过在第一阳极1751增设上述的阳极补偿部1751E，并且使得阳极补偿部1751E在衬底基板110上的正投影覆盖与第一连接部1751B相连的像素驱动电路215的第一节点N1，可平衡第一阳极1751和对应的第一节点N1之间的负载和第二阳极1752和对应的第一节点N1之间的负载，从而可提高显示质量。
在一些示例中，如图1所示，延伸部1751F还包括第一延伸部1751C和第二延伸部1751D，第一延伸部1751C位于第一连接部1751B远离第一主体部1751A的一侧，第二延伸部1751D分别与第一延伸部1751C和阳极补偿部1751E相连，第一延伸部1751C位于第二延伸部1751D远离阳极补偿部1751E的一侧。由此，第一延伸部位于第一连接部远离第一主体部的一侧，此时，第一延伸部从第一连接部延伸出来而并非从第一主体部延伸出来，可减小第一阳极的面积；另外，第一延伸部位于第二延伸部远离阳极补偿部的一侧，可使得第一延伸部更靠近对应的像素驱动电路的边缘，降低第一延伸部与像素驱动电路的透光区域的重叠面积。由此，该第一阳极的设计可使得第一阳极的第一延伸部和第二延伸部尽可能避开该显示基板的透光区域，从而可提高该显示基板的透光率。
例如，如图1和图2所示，第一节点N1可为像素驱动电路215中与数据线152和电源线151同层设置的连接块1542。连接块1542的具体设置会在后面的分层示意图中进行详细描述。
在一些示例中，如图1和图3A所示，第一延伸部1751C沿第二方向延伸的第三中心线703位于第一主体部1751A沿第二方向延伸的第二中心线702的第二侧，第二侧与第一侧相反。由此，第一阳极可使得第一延伸部尽可能避开该显示基板的透光区域，从而可提高该显示基板的透光率。
在一些示例中，如图1和图3A所示，第一延伸部1751C位于第一主体部1751A沿第二方向延伸的第二中心线702的第二侧。也就是说，第一延伸部1751C全部位于第一主体部1751A沿第二方向延伸的第二中心线的第二侧，从 而可进一步减小第一延伸部与该显示基板的透光区域的重叠面积，从而进一步提高该显示基板的透光率。在一些示例中，如图1所示，第一连接部1751B在第一方向上的尺寸小于第一主体部1751A在第一方向上的尺寸，第一延伸部1751C在第一方向上的尺寸小于第一连接部1751B在第一方向上的尺寸，第一方向垂直于第一主体部1751A、第一连接部1751B和第一延伸部1751C的排列方向。如图1所示，第一阳极1751和第二阳极1752沿第二方向排列，第二方向与第一方向垂直，第一方向和第二方向均位于平行于衬底基板110的平面上。由此，第一延伸部1751C在第一方向上占据的面积较小，可降低第一延伸部与像素驱动电路的透光区域的重叠面积，从而可提高该显示基板的透光率。
在一些示例中，如图1和图3A所示，各阳极组1750还包括第三阳极1753和第四阳极1754；在各阳极组1750内，第一阳极1751和第二阳极1752组成阳极对1758；第三阳极1753、阳极对1758和第四阳极1754沿第一方向依次排列，第一阳极1751和第二阳极1752沿第二方向依次排列。也就是说，上述的第一方向可为第三阳极、阳极对和第四阳极的排列方向。
例如，上述的第一方向可为显示基板中子像素排列的行方向，即栅线的延伸方向。当然，本公开实施例包括但不限于此，上述的第一方向也可为子像素排列的列方向，即数据线的延伸方向。
在一些示例中，如图1、图3A和图3B所示，上述的缺口区450包括第一缺口451，位于第一主体部1751A和阳极补偿部1751E之间，第一缺口451在衬底基板110上的正投影包括沿第二方向延伸的第一边缘401和第二边缘402，第一边缘401与第一连接部1751B在衬底基板110上的正投影相接，第二边缘402位于第一点P1和第二点P2的连线P12上。也就是说，第一阳极1751在第一主体部1751A和阳极补偿部1751E之间存在缺口，而第一主体部1751A和阳极补偿部1751E之间的区域恰恰对应像素驱动电路的透光区域，因此，该显示基板可降低第一阳极与像素驱动电路的透光区域的重叠面积，从而可提高透光率。
例如，第一缺口451靠近第一主体部1751A的边缘与第一主体部1751A相接，第一缺口451远离第一主体部1751A的边缘与第一连接部1751B远离第一主体部1751A的边缘齐平。
在一些示例中，如图1、图3A和图3B，第一缺口451在衬底基板110上的正投影的面积大于第一连接部1751B在衬底基板110上的正投影的面积的 1/2。此时，第一缺口的面积较大，从而使得该显示基板可大大降低第一阳极与像素驱动电路的透光区域的重叠面积，从而可提高透光率。
在一些示例中，如图1、图3A和图3B，上述的缺口区450还包括第二缺口452，位于第一缺口451与阳极补偿部452之间，第二缺口452在衬底基板110上的正投影包括沿第二方向延伸的第四边缘404和第五边缘405，第四边缘404与第一延伸部1751C在衬底基板110上的正投影相接，第五边缘405也位于第一点P1和第二点P2的连线P12上。也就是说，第一阳极的第一延伸部相对于第一主体部的边缘向内缩了一定的距离，使得第一阳极可尽可能地避开对应的像素驱动电路的透光区域，从而增加了显示基板的透光率。
例如，第一缺口451还包括与阳极补偿部1851E相接的边缘、与第二延伸部1751D相接的边缘、以及与第二缺口452相接的边缘。此时，上述的第一缺口451和第二缺口452可组成上述的缺口区450。
在一些示例中，如图1、图3A和图3B，第二缺口452在衬底基板110上的正投影的面积大于第一连接部1751B在衬底基板110上的正投影的面积的1/2。此时，第二缺口的面积较大，从而使得该显示基板可大大降低第一阳极与像素驱动电路的透光区域的重叠面积，从而可提高透光率。
在一些示例中，如图1、图3A和图3B，第二阳极1752包括第二主体部1752A和第二连接部1752B，第二连接部1752B与第二阳极1752对应的像素驱动电路215电性相连，第二主体部1752A在衬底基板110上的正投影覆盖与第二连接部1752B电性相连的像素驱动电路215的第一节点N1。此时，由于阳极补偿部1751E在衬底基板110上的正投影覆盖与第一连接部1751B相连的像素驱动电路215的第一节点N1，因此第一阳极和第二阳极均覆盖对应的像素驱动电路的第一节点，从而使得两者的负载相同，从而可提高显示质量。
在一些示例中，如图1、图3A和图3B，第一连接部1751B和第二连接部1752B关于平行于第一方向的对称轴呈轴对称设置；第一主体部1751A和第二主体部1752A也可关于该对称轴呈轴对称设置。第一连接部1751B在第一主体部1751A远离第二主体部1752A的一侧，第二连接部1752B在第二主体部1752A远离第一主体部1751A的一侧。
在一些示例中，如图1和图2所示，各像素驱动电路215还包括存储电容Cst和发光控制线133，存储电容Cst包括沿垂直于衬底基板110的方向设置的第一电极板CE1和第二电极板CE2；第一主体部1751A位于与第一连接部 1751B相连的像素驱动电路215中的发光控制线133远离存储电容Cst的一侧，阳极补偿部1751E位于发光控制线133远离第一主体部1751A的一侧。
在一些示例中，如图1和图2所示，各像素驱动电路215还包括数据线152和电源线151。在各像素驱动电路215，第二电极板CE2在衬底基板110上的正投影、发光控制线133在衬底基板110上的正投影、数据线152和电源线151围成第一间隔区域610，第一延伸部1751C在衬底基板110上的正投影覆盖第一间隔区域610的面积小于第一间隔区域610的总面积的1/2。在该显示基板中，第二电极板和发光控制线之间的第一间隔区域通常为透光区域，由于第一延伸部在衬底基板上的正投影覆盖第一间隔区域的面积小于第一间隔区域的总面积的1/2，该显示基板可有效地降低第一阳极与对应的像素驱动电路的透光区域的重叠面积，从而可提高该显示基板的透光率。
例如，第一延伸部1751C在衬底基板110上的正投影覆盖第一间隔区域610的面积还可小于第一间隔区域610的总面积的1/3。
在一些示例中，如图1和图2所示，各像素驱动电路215还包括初始化信号线141，第一阳极1751对应的像素驱动电路215中的发光控制线133在衬底基板110上的正投影、第二阳极1752对应的像素驱动电路215中的初始化信号线141在衬底基板110上的正投影、数据线152和电源线151围成第二间隔区域620，第一阳极1751在衬底基板110上的正投影覆盖第二间隔区域620的面积小于第二间隔区域620的总面积的2/3。在该显示基板中，第二间隔区域通常为透光区域，由于第一阳极在衬底基板上的正投影覆盖第二间隔区域的面积小于第二间隔区域的总面积的2/3，该显示基板可有效地降低第一阳极与对应的像素驱动电路的透光区域的重叠面积，从而可提高该显示基板的透光率。
例如，第一阳极1751在衬底基板110上的正投影覆盖第二间隔区域620的面积小于第二间隔区域620的总面积的1/2。
在一些示例中，如图2所示，该显示基板100还包括像素限定层190和发光层180；像素限定层190位于阳极层170远离衬底基板110的一侧，发光层180位于阳极层170远离衬底基板110的一侧。像素限定层190包括多个开口195，多个开口195与多个阳极175一一对应设置，各开口195部分暴露对应的阳极175；发光层180包括多个发光部185，多个发光部185与多个开口195一一对应设置，各发光部185的至少一部分位于对应的开口195之中并覆盖对 应的阳极175被暴露的部分。
在一些示例中，如图3所示，多个开口195划分为多个开口组1950，各开口组1950包括第一开口1951和第二开口1952，多个发光部185划分为多个发光部组1850，各发光部组1850包括第一发光部1851和第二发光部1852；第一开口1951在衬底基板110上的正投影落入第一主体部1751A在衬底基板110上的正投影之内，第一发光部1851的至少一部分位于第一开口1951之中并覆盖第一主体部1751A被暴露的部分，第一主体部1751A在衬底基板110上的正投影的形状与第一开口1951在衬底基板110上的正投影的形状相似。
例如，如图3所示，第二发光部1852的至少一部分位于第二开口1952之中并覆盖第二主体部1752A被暴露的部分，第二主体部1752A在衬底基板110上的正投影的形状与第二开口1952在衬底基板110上的正投影的形状相似。
例如，如图3所示，第三发光部1853的至少一部分位于第三开口1953之中并覆盖第三主体部1753A被暴露的部分，第三主体部1753A在衬底基板110上的正投影的形状与第三开口1953在衬底基板110上的正投影的形状相似。
例如，如图3所示，第四发光部1854的至少一部分位于第四开口1954之中并覆盖第四主体部1754A被暴露的部分，第四主体部1754A在衬底基板110上的正投影的形状与第四开口1954在衬底基板110上的正投影的形状相似。
例如，第一发光部和第二发光部被配置为发同样的颜色光。
例如，第一发光部被配置为发绿光、第三发光部被配置为发红光、第四发光部被配置为发蓝光。当然，本公开实施例包括但不限于此。
在一些示例中，如图3所示，像素电路层210包括半导体层120和第一栅极层130；半导体层120位于衬底基板110上，第一栅极层130位于半导体层120远离衬底基板110的一侧。
图4A-4D为本公开一实施例提供的一种显示基板中各功能膜层的平面示意图。图5为本公开一实施例提供的一种显示基板中像素驱动电路的等效电路图。
如图4A和图5所示，半导体层120包括多个像素驱动单元125，与多个阳极175一一对应设置；各像素驱动单元125包括第一单元1251、第二单元1252、第三单元1253、第四单元1254、第五单元1255、第六单元1256和第七单元1257，第一单元1251包括第一沟道区C1和位于第一沟道区C1两侧的第一源极区S1和第一漏极区域D1，第二单元1252包括第二沟道区C2和位于第 二沟道区C2两侧的第二源极区S2和第二漏极区域D2，第三单元1253包括第三沟道区C3和位于第三沟道区C3两侧的第三源极区S3和第三漏极区域D3，第四单元1254包括第四沟道区C4和位于第四沟道区C4两侧的第四源极区S4和第四漏极区域D4，第五单元1255包括第五沟道区C5和位于第五沟道区C5两侧的第五源极区S5和第五漏极区域D5，第六单元1256包括第六沟道区C6和位于第六沟道区C6两侧的第六源极区S6和第六漏极区域D6，第七单元1257包括第七沟道区C7和位于第七沟道区C7两侧的第七源极区S7和第七漏极区域D7。
例如，如图4A和图5所示，第三源极区S3、第一漏极区D1和第五源极区S5连接至第一节点N1，第六漏极区S6和第三漏极区D3相连，第一源极区S1、第二漏极区D2和第四漏极区D4连接至第二节点N2，第五漏极区D5和第七漏极区D7相连。
例如，如图4B和图5所示，第一栅极层130包括复位信号线131、栅线132、第一电极块CE1和发光控制线133，复位信号线131与第七沟道区C7和第六沟道区C6交叠，以与第七单元1257和第六单元1256形成第七薄膜晶体管T7和第六薄膜晶体管T6，栅线132分别与第三沟道区C3和第二沟道区C2交叠，以与第三单元1253和第二单元1252形成第三薄膜晶体管T3和第二薄膜晶体管T2，第一电极块CE1与第一沟道区C1交叠，以与第一单元1251形成第一薄膜晶体管T1，发光控制线133与四沟道区C4和第五沟道区C5交叠，以与第四单元1254和第五单元1255形成第四薄膜晶体管T4和第五薄膜晶体管T5；第一薄膜晶体管T1为驱动薄膜晶体管，第三薄膜晶体管T3为补偿薄膜晶体管。
在一些示例中，复位信号线、栅线和发光控制线均沿第一方向延伸，复位信号线、栅线、第一电极块和发光控制线沿第二方向排列。
如图4C和图5所示，像素电路层210包括：第二栅极层140，位于第一栅极层130远离半导体层120的一侧；第二栅极层140包括初始化信号线141和第二电极块CE2，初始化信号线141与第七源极区S7和第六源极区S6相连，第二电极块CE2在衬底基板110上的正投影与第一电极块CE1在衬底基板110上的正投影至少部分重叠以形成存储电容Cst。
如图4C和图5所示，第二栅极层140还包括导电块142。例如，导电块142可与电源线相连，从而降低电源线的电阻。又例如，导电块142在衬底基 板110的正投影与补偿薄膜晶体管T3的沟道区至少部分重叠，从而防止光线直接照射补偿薄膜晶体管T3的沟道区，提高补偿薄膜晶体管T3的稳定性。
如图4D和图5所示，像素电路层210还包括：源漏电极层150，位于第二栅极层140远离第一栅极层130的一侧，源漏电极层150包括数据线152和电源线151，第二源极区S2与数据线152相连，第四源极区S4与电源线151相连。
如图4D和图5所示，源漏电极层210还包括第一连接块1541、第二连接块1542和第三连接块1543。第一连接块1541用于将初始化信号线141与第六源极区S6和第七源极区S7相连；第二连接块1542用于将第三漏极区D3与第一电极块CE1相连；第三连接块1543与第五漏极区D5相连，可作为漏极与对应的阳极相连。
如图4D和图5所示，第二连接块1542包括第一端1542A和第二端1542B，第一端1542A与补偿薄膜晶体管T3的漏极区D3相连，第二端1542B与第一电极块CE1相连，阳极补偿部1751E在衬底基板110上的正投影覆盖第二端1542B在衬底基板110上的正投影。
如图5所示，第二源极区S2与数据线152相连；第四源极区S4与电源线151相连。由此，半导体层120的第一单元121、第二单元122、第三单元123、第四单元124、第五单元125、第六单元126和第七单元127可与上述的复位信号线131和栅线132形成第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7。
下面将对图5所示的像素驱动电路的一种工作方式进行示意性描述。首先，当向复位信号线131传输复位信号并使得第七薄膜晶体管T7导通时，流经各个子像素的阳极的剩余电流通过第七薄膜晶体管T7放电到第六薄膜晶体管T6，从而可抑制由于流经各个子像素的阳极的剩余电流导致的发光。然后，当向复位信号线131传输复位信号并向初始化信号线141传输初始化信号时，第六薄膜晶体管T6导通，并且通过第六薄膜晶体管T6向第一薄膜晶体管T1的第一栅极和存储电容Cst的第一电极块CE1施加初始化电压Vint，使得第一栅极和存储电容Cst初始化。第一栅极初始化可使得第一薄膜晶体管T1导通。
随后，当向栅线132传输栅极信号并向数据线152传输数据信号时，第二薄膜晶体管T2和第第三薄膜晶体管T3都导通，通过第第二薄膜晶体管T2和 第三薄膜晶体管T3向第一栅极施加数据电压Vd。此时，施加到第一栅极的电压是补偿电压Vd+Vth，并且施加到第一栅极的补偿电压也被施加到存储电容Cst的第一电极块CE1。
随后，电源线151向存储电容Cst的第二电极块CE2施加驱动电压Vel，向第一电极块CE1施加补偿电压Vd+Vth，使得与分别施加到存储电容Cst的两个电极的电压之间的差对应的电荷存储在存储电容Cst中，第一薄膜晶体管T1导通达到预定时间。
随后，当向发光控制线133施加发射控制信号时，第四薄膜晶体管T4和第五薄膜晶体管T5都导通，使得第四薄膜晶体管T4向第五薄膜晶体管T5施加驱动电压Vel。驱动电压Vel穿过由存储电容Cst导通的第一薄膜晶体管T1时，对应的驱动电压Vel与通过存储电容Cst向第一栅极施加的电压之间的差驱动电流Id流经第一薄膜晶体管T1的第一漏极区D3，驱动电流Id通过第五薄膜晶体管T5施加到各个子像素，使得各个子像素的发光层发光。
图6为本公开一实施例提供的另一种显示基板的平面示意图。如图6所示，第二阳极1752还包括第一增补部1752C，第一增补部1752C从第二主体部1752A沿靠近第一阳极1751的方向凸出，第一增补部1752C在衬底基板110上的正投影与第二连接部1752B电性相连的像素驱动电路215中的补偿薄膜晶体管T3的沟道区在衬底基板110上的正投影至少部分交叠。
在本示例提供的显示基板中，像素驱动电路采用7T1C的像素驱动结构，在发光阶段，驱动薄膜晶体管T1的稳定性直接影响了有机发光二极管显示装置的长期发光稳定性；在充电阶段，驱动薄膜晶体管T1的栅极上的的充电电压与补偿薄膜晶体管T3的状态有关。通常，薄膜晶体管对光照特别敏感，当薄膜晶体管(特别是沟道区)受到光照时容易使得薄膜晶体管的特性产生漂移，影响像素驱动电路的正常工作。该显示基板在第二阳极增设第一增补部，并且第一增补部在衬底基板上的正投影与第二连接部电性相连的像素驱动电路中的补偿薄膜晶体管的沟道区在衬底基板上的正投影至少部分交叠，由此，该显示基板可通过第一增补部对对应的补偿薄膜晶体管的沟道区进行遮挡，从而可提高补偿薄膜晶体管的稳定性和寿命，进而可提高该显示基板的长期发光稳定性和寿命。
需要说明的是，当补偿薄膜晶体管T3为双栅结构时，上述补偿薄膜晶体管T3的沟道区包括两个沟道区和两个沟道区之间的共用电极。例如，如图2 所示，补偿薄膜晶体管T3可为双栅结构的薄膜晶体管，从而可提高补偿薄膜晶体管的可靠性。补偿薄膜晶体管T3的沟道区包括间隔设置的第一沟道区C31和第二沟道区C32，补偿薄膜晶体管T3还包括位于第一沟道区C31和第二沟道区C32之间的共用电极SE。补偿薄膜晶体管T3的共用电极SE在衬底基板110上的正投影与所述第一增补部1742C至少部分重叠。由此，第一增补部可对补偿薄膜晶体管T3的共用电极SE进行部分遮挡或完全遮挡，从而进一步提高补偿薄膜晶体管的稳定性和寿命，进而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图1和图6所示，第三阳极1753包括第三主体部1753A和第三连接部1753B，第三连接部1753B与第三阳极1753对应的像素驱动电路215电性相连；第四阳极1754包括第四主体部1754A和第四连接部1754B，第四连接部1754B与第四阳极1754对应的像素驱动电路215电性相连。
在一些示例中，如图6所示，第四阳极1754还包括第二增补部1754C，从第四主体部1754A沿着靠近第二阳极1752的方向凸出；例如，第二增补部1754C在第二方向上位于第四连接部1754B靠近第四主体部1754A的一侧；第二增补部1754C在衬底基板110上的正投影与第三连接部1753B电性相连的像素驱动电路215中的补偿薄膜晶体管T3的沟道区在衬底基板110上的正投影至少部分交叠。由此，该显示基板可通过第二增补部对第三阳极对应的补偿薄膜晶体管的沟道区进行遮挡，从而可提高补偿薄膜晶体管的稳定性和寿命，进而可提高该显示基板的长期发光稳定性和寿命。同样地，当补偿薄膜晶体管T3为双栅结构时，上述补偿薄膜晶体管T3的沟道区包括两个沟道区和两个沟道区之间的共用电极。
在一些示例中，如图6所示，第四阳极1754还包括第三增补部1754D，从第四主体部1754A沿着远离第二阳极1752的方向凸出，第三增补部1754D在衬底基板110上的正投影与第一连接部1751B电性相连的像素驱动电路215中的补偿薄膜晶体管T3的沟道区在衬底基板110上的正投影至少部分交叠。由此，该显示基板可通过第三增补部对第一阳极对应的补偿薄膜晶体管的沟道区进行遮挡，从而可提高补偿薄膜晶体管的稳定性和寿命，进而可提高该显示基板的长期发光稳定性和寿命。同样地，当补偿薄膜晶体管T3为双栅结构时，上述补偿薄膜晶体管T3的沟道区包括两个沟道区和两个沟道区之间的共用电极。
本公开至少一个实施例还提供一种显示装置。图7为本公开一实施例提供的一种显示装置的示意图。如图7所示，该显示装置800包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果，例如：该显示装置具有较高的透光率。另外，该显示装置可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
例如，该显示装置可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (31)

  1. 一种显示基板，包括：
    衬底基板；
    像素电路层，在所述衬底基板上；
    阳极层，位于所述像素电路层远离所述衬底基板的一侧，
    其中，所述像素电路层包括多个像素驱动电路，所述阳极层包括多个阳极，所述多个像素驱动电路与所述多个阳极一一对应设置，
    所述多个阳极包括沿第一方向和第二方向阵列排布的多个阳极组，各所述阳极组包括在所述第二方向上相对设置的第一阳极和第二阳极，所述第一阳极包括第一主体部和第一连接部，所述第一连接部与所述第一阳极对应的所述像素驱动电路电性相连，
    所述第一阳极还包括延伸部和阳极补偿部，所述阳极补偿部在所述衬底基板上的正投影覆盖与所述第一连接部相连的所述像素驱动电路中的一个薄膜晶体管，
    所述第一主体部和所述阳极补偿部在所述第一方向上至少部分交叠，所述阳极补偿部沿所述第二方向延伸的第一中心线位于所述第一主体部沿所述第二方向延伸的第二中心线的第一侧，所述阳极补偿部在远离所述第二中心线的一侧具有第一点，所述第一主体部在所述第一侧具有第二点，
    所述第一阳极与所述第一点和所述第二点的连线围成缺口区，所述缺口区的面积大于所述阳极补偿部的面积和所述第一连接部的面积中的至少之一。
  2. 根据权利要求1所述的显示基板，其中，所述缺口区的面积大于所述阳极补偿部的面积和所述第一连接部的面积之和。
  3. 根据权利要求1所述的显示基板，其中，所述阳极补偿部位于所述第一主体部沿所述第二方向延伸的第二中心线的所述第一侧。
  4. 根据权利要求1所述的显示基板，其中，所述延伸部包括第一延伸部和第二延伸部，所述第一延伸部位于所述第一连接部远离所述第一主体部的一侧，所述第二延伸部分别与所述第一延伸部和所述阳极补偿部相连，所述第一延伸部位于所述第二延伸部远离所述阳极补偿部的一侧。
  5. 根据权利要求4所述的显示基板，其中，所述第一延伸部沿所述第二方向延伸的第三中心线位于所述第一主体部沿所述第二方向延伸的所述第二 中心线的第二侧，所述第二侧与所述第一侧相反。
  6. 根据权利要求5所述的显示基板，其中，所述第一延伸部位于所述第一主体部沿所述第二方向延伸的所述第二中心线的所述第二侧。
  7. 根据权利要求1-6中任一项所述的显示基板，其中，所述缺口区在所述衬底基板上的正投影与所述第一阳极在所述衬底基板上的正投影不交叠。
  8. 根据权利要求1-6中任一项所述的显示基板，其中，所述第一连接部沿所述第二方向延伸的第四中心线位于所述第一主体部的所述第二中心线的所述第一侧。
  9. 根据权利要求1-6中任一项所述的显示基板，其中，各所述像素驱动电路包括驱动薄膜晶体管和补偿薄膜晶体管，所述驱动薄膜晶体管的漏极与所述补偿薄膜晶体管的源极连接至第一节点，
    所述阳极补偿部在所述衬底基板上的正投影覆盖与所述第一连接部相连的所述像素驱动电路的所述第一节点。
  10. 根据权利要求4-6中任一项所述的显示基板，其中，所述第一连接部在所述第一方向上的尺寸小于所述第一主体部在第一方向上的尺寸，所述第一延伸部在所述第一方向上的尺寸小于所述第一连接部在所述第一方向上的尺寸。
  11. 根据权利要求10所述的显示基板，其中，各所述阳极组还包括第三阳极和第四阳极；在各所述阳极组内，所述第一阳极和所述第二阳极组成阳极对，所述第三阳极、所述阳极对和所述第四阳极沿所述第一方向依次排列，所述第一阳极和所述第二阳极沿第二方向依次排列。
  12. 根据权利要求11所述的显示基板，其中，所述缺口区包括第一缺口，位于所述第一主体部和所述阳极补偿部之间，
    所述第一缺口在所述衬底基板上的正投影包括沿所述第二方向延伸的第一边缘和第二边缘，所述第一边缘与所述第一连接部在所述衬底基板上的正投影相接，所述第二边缘位于所述第一点和所述第二点的连线上。
  13. 根据权利要求12所述的显示基板，其中，所述第一缺口在所述衬底基板上的正投影的面积大于所述第一连接部在所述衬底基板上的正投影的面积的1/2。
  14. 根据权利要求12所述的显示基板，其中，所述缺口区还包括第二缺口，位于所述第一缺口与所述阳极补偿部之间，
    所述第二缺口在所述衬底基板上的正投影包括沿所述第二方向延伸的第四边缘和第五边缘，所述第四边缘与所述第一延伸部在所述衬底基板上的正投影相接，所述第五边缘也位于所述第一点和所述第二点的连线上。
  15. 根据权利要求14所述的显示基板，其中，所述第二缺口在所述衬底基板上的正投影的面积大于所述第一连接部在所述衬底基板上的正投影的面积的1/2。
  16. 根据权利要求1-15中任一项所述的显示基板，其中，所述第二阳极包括第二主体部和第二连接部，所述第二连接部与所述第二阳极对应的所述像素驱动电路电性相连，所述第二主体部在所述衬底基板上的正投影覆盖与所述第二连接部电性相连的所述像素驱动电路的所述第一节点，
    所述第一连接部和所述第二连接部关于平行于所述第一方向的对称轴呈轴对称设置，所述第一连接部在所述第一主体部远离所述第二主体部的一侧，所述第二连接部在所述第二主体部远离第一主体部的一侧。
  17. 根据权利要求16所述的显示基板，其中，所述第二阳极还包括第一增补部，所述第一增补部从所述第二主体部沿靠近所述第一阳极的方向凸出，
    所述第一增补部在所述衬底基板上的正投影与所述第二连接部电性相连的所述像素驱动电路中的所述补偿薄膜晶体管的沟道区在所述衬底基板上的正投影至少部分交叠。
  18. 根据权利要求1-17中任一项所述的显示基板，其中，各所述像素驱动电路还包括存储电容和发光控制线，所述存储电容包括沿垂直于所述衬底基板的方向设置的第一电极板和第二电极板，
    所述第一主体部位于与所述第一连接部相连的所述像素驱动电路中的所述发光控制线远离所述存储电容的一侧，所述阳极补偿部位于所述发光控制线远离所述第一主体部的一侧。
  19. 根据权利要求18所述的显示基板，其中，各所述像素驱动电路还包括数据线和电源线，在各所述像素驱动电路，所述第二电极板在所述衬底基板上的正投影、所述发光控制线在所述衬底基板上的正投影、所述数据线和所述电源线围成第一间隔区域，所述第一延伸部在所述衬底基板上的正投影覆盖所述第一间隔区域的面积小于所述第一间隔区域的总面积的1/2。
  20. 根据权利要求19所述的显示基板，其中，各所述像素驱动电路还包括初始化信号线，所述第一阳极对应的所述像素驱动电路中的所述发光控制线 在所述衬底基板上的正投影、所述第二阳极对应的所述像素驱动电路中的所述初始化信号线在所述衬底基板上的正投影、所述数据线和所述电源线围成第二间隔区域，所述第一阳极在所述衬底基板上的正投影覆盖所述第二间隔区域的面积小于所述第二间隔区域的总面积的2/3。
  21. 根据权利要求11-15中任一项所述的显示基板，其中，所述第三阳极包括第三主体部和第三连接部，所述第三连接部与所述第三阳极对应的所述像素驱动电路电性相连；
    所述第四阳极包括第四主体部和第四连接部，所述第四连接部与所述第四阳极对应的所述像素驱动电路电性相连。
  22. 根据权利要求21所述的显示基板，其中，所述第四阳极还包括第二增补部，从所述从第四主体部沿着靠近所述第二阳极的方向凸出，
    所述第二增补部在所述衬底基板上的正投影与所述第三连接部电性相连的所述像素驱动电路中的所述补偿薄膜晶体管的沟道区在所述衬底基板上的正投影至少部分交叠。
  23. 根据权利要求21所述的显示基板，其中，所述第四阳极还包括第三增补部，从所述从第四主体部沿着远离所述第二阳极的方向凸出，
    所述第三增补部在所述衬底基板上的正投影与所述第一连接部电性相连的所述像素驱动电路中的所述补偿薄膜晶体管的沟道区在所述衬底基板上的正投影至少部分交叠。
  24. 根据权利要求1-22中任一项所述的显示基板，还包括：
    像素限定层，位于所述阳极层远离所述衬底基板的一侧；以及
    发光层，位于所述阳极层远离所述衬底基板的一侧，
    其中，所述像素限定层包括多个开口，所述多个开口与所述多个阳极一一对应设置，各所述开口部分暴露对应的所述阳极，
    所述发光层包括多个发光部，所述多个发光部与所述多个开口一一对应设置，各所述发光部的至少一部分位于对应的所述开口之中并覆盖对应的所述阳极被暴露的部分。
  25. 根据权利要求24所述的显示基板，其中，所述多个开口划分为多个开口组，各所述开口组包括第一开口和第二开口，所述多个发光部划分为多个发光部组，各所述发光部组包括第一发光部和第二发光部，
    所述第一开口在所述衬底基板上的正投影落入所述第一主体部在所述衬 底基板上的正投影之内，所述第一发光部的至少一部分位于所述第一开口之中并覆盖所述第一主体部被暴露的部分，所述第一主体部在所述衬底基板上的正投影的形状与所述第一开口在所述衬底基板上的正投影的形状相似。
  26. 根据权利要求18-20中任一项所述的显示基板，其中，所述像素电路层包括：
    半导体层，位于所述衬底基板上；以及
    第一栅极层，位于所述半导体层远离所述衬底基板的一侧，
    其中，所述半导体层包括多个像素驱动单元，与所述多个阳极一一对应设置，各所述像素驱动单元包括第一单元、第二单元、第三单元、第四单元、第五单元、第六单元和第七单元，所述第一单元包括第一沟道区和位于所述第一沟道区两侧的第一源极区和第一漏极区域，所述第二单元包括第二沟道区和位于所述第二沟道区两侧的第二源极区和第二漏极区域，所述第三单元包括第三沟道区和位于所述第三沟道区两侧的第三源极区和第三漏极区域，所述第四单元包括第四沟道区和位于所述第四沟道区两侧的第四源极区和第四漏极区域，所述第五单元包括第五沟道区和位于所述第五沟道区两侧的第五源极区和第五漏极区域，所述第六单元包括第六沟道区和位于所述第六沟道区两侧的第六源极区和第六漏极区域，所述第七单元包括第七沟道区和位于所述第七沟道区两侧的第七源极区和第七漏极区域，
    所述第三源极区、所述第一漏极区和所述第五源极区连接至所述第一节点，所述第六漏极区和所述第三漏极区相连，所述第一源极区、所述第二漏极区和所述第四漏极区连接至第二节点，所述第五漏极区和所述第七漏极区相连，
    所述第一栅极层包括复位信号线、栅线、第一电极块和发光控制线，所述复位信号线与所述第七沟道区和所述第六沟道区交叠，以与所述第七单元和所述第六单元形成第七薄膜晶体管和第六薄膜晶体管，所述栅线分别与所述第三沟道区和所述第二沟道区交叠，以与所述第三单元和所述第二单元形成第三薄膜晶体管和第二薄膜晶体管，所述第一电极块与所述第一沟道区交叠，以与所述第一单元形成第一薄膜晶体管，所述发光控制线与所述四沟道区和所述第五沟道区交叠，以与所述第四单元和所述第五单元形成第四薄膜晶体管和第五薄膜晶体管，
    所述第一薄膜晶体管为所述驱动薄膜晶体管，所述第三薄膜晶体管为所述 补偿薄膜晶体管。
  27. 根据权利要求26所述的显示基板，其中，所述复位信号线、栅线和发光控制线均沿所述第一方向延伸，所述复位信号线、所述栅线、所述第一电极块和所述发光控制线沿所述第二方向排列。
  28. 根据权利要求26或27所述的显示基板，其中，所述像素电路层包括：
    第二栅极层，位于所述第一栅极层远离所述半导体层的一侧；
    其中，所述第二栅极层包括初始化信号线和第二电极块，所述初始化信号线与所述第七源极区和第六源极区相连，所述第二电极块在衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影至少部分重叠以形成存储电容。
  29. 根据权利要求28所述的显示基板，其中，所述像素电路层还包括：
    源漏电极层，位于所述第二栅极层远离所述第一栅极层的一侧，
    其中，所述源漏电极层包括所述数据线和所述电源线，所述第二源极区与所述数据线相连，所述第四源极区与所述电源线相连。
  30. 根据权利要求29所述的显示基板，其中，所述源漏电极层还包括：
    连接块，包括第一端和第二端，所述第一端与所述补偿薄膜晶体管的漏极区相连，所述第二端与所述第一电极块相连，
    其中，所述阳极补偿部在所述衬底基板上的正投影覆盖所述第二端在所述衬底基板上的正投影。
  31. 一种显示装置，包括根据权利要求1-30中任一项所述的显示基板。
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