WO2022056907A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022056907A1
WO2022056907A1 PCT/CN2020/116488 CN2020116488W WO2022056907A1 WO 2022056907 A1 WO2022056907 A1 WO 2022056907A1 CN 2020116488 W CN2020116488 W CN 2020116488W WO 2022056907 A1 WO2022056907 A1 WO 2022056907A1
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WIPO (PCT)
Prior art keywords
transistor
light
pixel
sub
reset
Prior art date
Application number
PCT/CN2020/116488
Other languages
English (en)
French (fr)
Inventor
孙开鹏
龙跃
魏锋
周宏军
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/116488 priority Critical patent/WO2022056907A1/zh
Priority to CN202080002042.2A priority patent/CN115066755A/zh
Priority to US17/419,814 priority patent/US11620953B2/en
Publication of WO2022056907A1 publication Critical patent/WO2022056907A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • the invention belongs to the field of display technology, and in particular relates to a display substrate and a display device.
  • AMOLED active matrix organic light emitting diode
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, which includes:
  • each of the plurality of pixel units includes a plurality of sub-pixels; each of the plurality of sub-pixels includes a pixel circuit;
  • An active semiconductor layer which includes a channel region and a source-drain doped region of each transistor in each of the pixel circuits, the pixel circuit at least includes a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first Reset transistors, light-emitting devices;
  • a first light-shielding pattern disposed on the side of the active semiconductor layer away from the substrate, and the orthographic projection of the first light-shielding pattern on the substrate covers the grooves of the first reset transistor and the threshold compensation transistor Orthographic projection of the track area on the substrate.
  • each of the pixel circuits further includes a second reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor;
  • the first reset transistor and the second reset transistor in each of the pixel circuits are approximately located on a straight line extending along the first direction;
  • the first light-emitting diode in each of the pixel circuits The control transistor and the second light emission control transistor are located approximately on a straight line extending along the first direction;
  • the threshold compensation transistor and the data writing transistor in each of the pixel circuits are located approximately on a straight line extending along the first direction;
  • the second reset transistor, the second light-emitting control transistor and the threshold compensation transistor in each pixel circuit are located approximately on a straight line extending along the second direction; the first reset transistor in each pixel circuit The reset transistor, the first light emission control transistor, and the data writing transistor are located approximately on a straight line extending in the second direction.
  • control electrode of the driving transistor includes a first side and a second side oppositely arranged along the second direction; for the pixel circuit of each sub-pixel, the first reset transistor, the second reset transistor, The first light emission control transistor and the second light emission control transistor are located on the first side; the threshold compensation transistor and the data writing transistor are located on the second side.
  • the light-emitting device in each of the pixel circuits includes a first electrode, a light-emitting layer, and a second electrode that are arranged in sequence on the side of the transistor in each of the pixel circuits away from the substrate; the first light-shielding pattern and the light-emitting
  • the first electrodes of the device are arranged in the same layer and have the same material.
  • the plurality of sub-pixels in each of the pixel units include first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels;
  • the first light-shielding pattern includes a first light-shielding portion, a second light-shielding portion, and a second light-shielding portion in each sub-pixel. a light-shielding part, a third light-shielding part, a fourth light-shielding part, a fifth light-shielding part, and a sixth light-shielding part;
  • the orthographic projection of the first light shielding portion on the substrate covers the orthographic projection of the channel region of the first reset transistor in the first color sub-pixel on the substrate; the second light shielding portion is on the substrate.
  • the orthographic projection of the threshold compensation transistor in the sub-pixel of the first color covers the orthographic projection of the channel region of the threshold compensation transistor in the sub-pixel of the first color on the substrate; the orthographic projection of the third light shielding portion on the substrate covers the sub-pixel of the second color.
  • An orthographic projection of the channel region of the reset transistor on the substrate; the orthographic projection of the fourth light shielding portion on the substrate covers the channel region of the threshold compensation transistor in the second color sub-pixel on the substrate orthographic projection on the substrate; the orthographic projection of the fifth light shielding portion on the substrate covers the orthographic projection of the channel region of the first reset transistor in the third color sub-pixel on the substrate; the sixth light shielding The orthographic projection of the portion on the substrate covers the orthographic projection of the channel region of the threshold compensation transistor in the third color sub-pixel on the substrate.
  • the first electrodes of the light-emitting devices in the pixel circuits of each of the second-color sub-pixels are approximately located on a straight line extending along the second direction; each of the first-color sub-pixels and the first electrode of the light emitting device in the pixel circuit of the sub-pixel of the second color is substantially located on a straight line extending along the second direction;
  • the first shading part and the third shading part in the unit are integral structures
  • the fifth light-shielding portion in the pixel units of the column is an integral structure; wherein, i is from 1 to N, and N is the number of the pixel units in each column; j is from 1 to M, and M is the number of the pixel units in each row. The number of pixel units.
  • the display substrate further includes:
  • a gate insulating layer disposed on the side of the active semiconductor layer away from the substrate;
  • the first conductive layer includes a second electrode plate of the storage capacitor, a scan extending along the first direction a signal line, a reset control signal line extending in the first direction, a light emission control signal line extending in the first direction, and the driving transistor, the data writing transistor, the threshold compensation transistor, the first a light-emitting control transistor, the second light-emitting control transistor, the control electrodes of the first reset transistor and the second reset transistor, and the control electrodes of the driving transistor are multiplexed as the second electrode of the storage capacitor;
  • a first insulating layer disposed on the side of the first conductive layer away from the gate insulating layer
  • a second conductive layer disposed on the side of the first insulating layer away from the first conductive layer; the second conductive layer includes a reset power signal line extending along the first direction and a first pole of the storage capacitor plate;
  • a second insulating layer disposed on the side of the second conductive layer away from the first insulating layer
  • the source-drain metal layer includes a power signal line extending along the second direction, extending along the second direction The data line, the first connection part, the second connection part and the third connection part;
  • the first connection portion is configured to connect the second electrode of the threshold compensation transistor and the control electrode of the drive transistor, and the second connection portion is configured to connect the reset power supply signal line and the second reset a first electrode of the transistor, the third connection part is configured to connect the first electrode of the light-emitting device and the second electrode of the second light-emitting control transistor;
  • the third connection part includes a first part and a second part, and the first part of the third connection part is connected to a via hole passing through the gate insulating layer, the first insulating layer and the second insulating layer.
  • the second electrode of the second light emission control transistor is electrically connected, and the second part of the third connection part is electrically connected to the first electrode of the light emitting device through a via hole penetrating the flat layer.
  • the second conductive layer further includes a second light-shielding pattern set in each of the sub-pixels; the second light-shielding pattern in each of the sub-pixels is orthographically projected on the substrate to cover the pixels in the sub-pixels
  • the channel region of the threshold compensation transistor of the circuit is orthographically projected on the substrate, and the second light shielding pattern is electrically connected to the first power signal line.
  • the first power signal line connected to each of the second shading patterns is the one with the closest distance in the first direction among the plurality of first power signal lines.
  • the display substrate further includes:
  • a gate insulating layer disposed on the side of the active semiconductor layer away from the substrate;
  • the first conductive layer includes a second electrode plate of the storage capacitor, a scan extending along the first direction a signal line, a reset control signal line extending in the first direction, a light emission control signal line extending in the first direction, and the driving transistor, the data writing transistor, the threshold compensation transistor, the first a light-emitting control transistor, the second light-emitting control transistor, the control electrodes of the first reset transistor and the second reset transistor, and the control electrodes of the driving transistor are multiplexed as the second electrode of the storage capacitor;
  • a first insulating layer disposed on the side of the first conductive layer away from the gate insulating layer
  • a second conductive layer disposed on the side of the first insulating layer away from the first conductive layer; the second conductive layer includes a reset power signal line extending along the first direction and a first pole of the storage capacitor plate;
  • a second insulating layer disposed on the side of the second conductive layer away from the first insulating layer
  • the source-drain metal layer includes a power signal line extending along the second direction, extending along the second direction the data lines and the first shading pattern.
  • the first light-shielding pattern includes a seventh light-shielding portion and an eighth light-shielding portion in each sub-pixel; the seventh light-shielding portion is orthographically projected on the substrate to cover the first portion of the pixel circuit in the sub-pixel where the seventh light-shielding portion is located.
  • the seven light-shielding parts are integrated with the power signal lines connected to the sub-pixels where they are located.
  • the display substrate further includes: a flat layer disposed between the source-drain metal layer and the first electrode of the light-emitting device;
  • the source-drain metal layer further includes: a first connection part, a second connection part and a third connection part;
  • the first connection portion is configured to connect the second electrode of the threshold compensation transistor and the control electrode of the drive transistor, and the second connection portion is configured to connect the reset power supply signal line and the second reset a first electrode of the transistor, the third connection part is configured to connect the first electrode of the light-emitting device and the second electrode of the second light-emitting control transistor;
  • the third connection part includes a first part and a second part, and the first part of the third connection part is connected to a via hole passing through the gate insulating layer, the first insulating layer and the second insulating layer.
  • the second electrode of the second light-emitting control transistor is electrically connected, and the second portion of the third connection portion is electrically connected to the first electrode of the light-emitting device through a via hole penetrating the flat layer;
  • the eighth light-shielding portion and the second connecting portion have an integral structure.
  • the second conductive layer further includes a second light-shielding pattern set in each of the sub-pixels; the second light-shielding pattern in each of the sub-pixels is orthographically projected on the substrate to cover the pixels in the sub-pixels
  • the channel region of the threshold compensation transistor of the circuit is orthographically projected on the substrate, and the second light shielding pattern is electrically connected to the first power signal line.
  • the first power signal line connected to each of the second shading patterns is the one with the closest distance in the first direction among the plurality of first power signal lines.
  • the first reset transistor and the threshold compensation transistor are both double-gate transistors.
  • an embodiment of the present disclosure provides a display device including any one of the above-mentioned display substrates.
  • FIG. 1 is a schematic structural diagram of an exemplary display substrate.
  • FIG. 2 is a schematic diagram of an exemplary pixel circuit.
  • FIG 3 is a cross-sectional view of an exemplary display substrate in which a second light-emitting control transistor is connected to a light-emitting device.
  • FIG. 4 is a layout diagram of each transistor position of a display substrate according to an embodiment of the disclosure.
  • FIG. 5 is a layout of a display substrate including a first light shielding pattern according to an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of an active semiconductor layer of a display substrate according to an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a first conductive layer of a display substrate according to an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a second conductive layer of a display substrate according to an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a source-drain metal layer of a display substrate according to an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a first electrode and a first light shielding pattern of a light emitting device of a display substrate according to an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of a source-drain metal layer of a display substrate according to an embodiment of the disclosure.
  • an embodiment of the present disclosure provides a display substrate, the display substrate includes: a substrate, a plurality of pixel units, an active layer semiconductor layer, and a first light-shielding pattern; wherein the plurality of pixel units are disposed on the substrate, They are arranged in an array, that is, arranged in multiple rows along the first direction and arranged into multiple columns along the second direction.
  • Each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit; the pixel circuit at least includes a driving transistor, a data writing transistor, a storage capacitor, a threshold compensation transistor, a first reset transistor, and a light-emitting device; in the embodiments of the present disclosure , the first reset transistor is configured to respond to the reset control signal, and initializes the storage capacitor through the reset power supply signal; the data writing transistor is configured to respond to the scan signal, write the data voltage signal to the first drive transistor of the storage capacitor.
  • the threshold compensation transistor is configured to respond to the scan signal to compensate the threshold voltage of the driving transistor; the driving transistor is configured to control the voltage of the light-emitting device according to the voltage of the first pole and the control pole Work.
  • the active semiconductor layer includes channel regions and source-drain doped regions of each transistor in each pixel circuit, and the first light shielding pattern is disposed on a portion of the active semiconductor layer away from the substrate.
  • the orthographic projection of the first light shielding pattern on the substrate covers the orthographic projection of the channel regions of the first reset transistor and the threshold compensation transistor on the substrate.
  • the orthographic projection of the first light shielding pattern on the substrate covers the orthographic projection of the channel regions of the first reset transistor and the threshold compensation transistor on the substrate , that is, the channel regions of the first reset transistor and the threshold compensation transistor are shielded by the first shading pattern, so the channel regions of the first reset transistor and the threshold compensation transistor T2 can be effectively prevented from being illuminated, which will affect the first reset.
  • the transistor and threshold compensate the switching characteristics of the transistor.
  • the substrate 101 in the display substrate is a flexible substrate, which may be a polyimide PI material.
  • the substrate 101 may also be a rigid material such as a glass substrate.
  • the first reset transistor and the threshold compensation transistor are designed as double-gate transistors in the embodiments of the present disclosure; and the first reset transistor is also used in the following description.
  • the threshold compensation transistor is used as an example for description, but the first reset transistor and the threshold compensation transistor may also be single-gate transistors, which are all within the protection scope of the embodiments of the present disclosure.
  • FIG. 5 is a layout of a display substrate including a first light-shielding pattern according to an embodiment of the present disclosure.
  • the first light-shielding pattern in an embodiment of the present disclosure is in the same layer as the first electrode of the light-emitting device. In this way, the overall thickness of the display substrate will not be increased, and the process steps will not be increased.
  • the structure of the display substrate according to the embodiment of the present disclosure will be described below with reference to specific examples.
  • FIG. 1 is a schematic structural diagram of an exemplary display substrate
  • FIG. 2 is a schematic diagram of an exemplary pixel circuit
  • the display substrate includes a base 101 on which a plurality of arrays are arranged
  • Each pixel unit 100 includes sub-pixels 10 of three colors, which are sub-pixels of a first color, sub-pixels of a second color, and sub-pixels of a third color.
  • the first color sub-pixel is a red sub-pixel
  • the second color sub-pixel is a green sub-pixel
  • the third color sub-pixel is a blue sub-pixel as an example for description. But not limited to this, the colors can be interchanged.
  • each sub-pixel is provided with a pixel circuit.
  • the pixel circuit in each sub-pixel may include a driving sub-circuit 3, a first light-emitting control sub-circuit 5, a second light-emitting control sub-circuit 6, a data writing sub-circuit 4, a storage sub-circuit 7, a threshold compensation sub-circuit 2, and a reset sub-circuit.
  • Circuit 1 and light-emitting device D are included in each sub-pixel circuit.
  • each pixel unit 100 includes sub-pixels 10 of three colors, and the number of sub-pixels 10 of three colors included in each pixel unit 100 is calculated limited. For example, taking the first color sub-pixels as red sub-pixels, the second color sub-pixels as green sub-pixels, and the third-color sub-pixels as blue sub-pixels, the number of red sub-pixels in each pixel unit 100 is 2 number, the number of green sub-pixels and blue sub-pixels; or, the number of green sub-pixels in each pixel unit 100 is 2, the number of red sub-pixels and blue sub-pixels; or, each pixel unit 100 The number of blue sub-pixels in is 2, and the number of red sub-pixels and green sub-pixels.
  • each pixel unit 100 includes sub-pixels 10 of four colors: red sub-pixel, green sub-pixel, blue sub-pixel, and white sub-pixel.
  • the first light-emitting control sub-circuit 5 is respectively connected to the first voltage terminal VDD and the first terminal of the driving sub-circuit 3, and is configured to turn on or off the connection between the driving sub-circuit and the first voltage terminal VDD
  • the second light-emitting control sub-circuit 6 is respectively electrically connected to the second end of the driving sub-circuit and the first electrode D1 of the light-emitting device D, and is configured to turn on or off the connection between the driving sub-circuit 3 and the light-emitting device D open.
  • the data writing sub-circuit 4 is electrically connected to the first end of the driving sub-circuit 3, and is configured to write the data signal into the storage sub-circuit 7 under the control of the scanning signal.
  • the storage sub-circuit 8 is respectively electrically connected to the control terminal of the driving sub-circuit 3 and the first voltage terminal VDD, and is configured to store data signals.
  • the threshold compensation sub-circuit 2 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 3 respectively, and is configured to perform threshold compensation on the driving sub-circuit 3 .
  • the reset sub-circuit 1 is electrically connected to the control terminal of the driving sub-circuit 3 and the first electrode D1 of the light-emitting device D, and is configured to control the control terminal of the driving sub-circuit 3 and the first electrode D1 of the light-emitting device D under the control of the reset control signal. Electrode D1 is reset.
  • the driving sub-circuit 3 includes a driving transistor T3, the control terminal of the driving sub-circuit 3 includes the control electrode of the driving transistor T3, the first terminal of the driving sub-circuit 3 includes the first electrode of the driving transistor T3, and the driving sub-circuit 3
  • the second terminal of the includes the second pole of the driving transistor T3.
  • the data writing subcircuit 4 includes a data writing transistor T4, the storage subcircuit 7 includes a storage capacitor Cst, the threshold compensation subcircuit 2 includes a threshold compensation transistor T2, the first light emission control subcircuit 5 includes a first light emission control transistor T5, and the second light emission control subcircuit 5 includes a first light emission control transistor T5.
  • the light emission control sub-circuit 6 includes a second light emission control transistor T6, and the reset sub-circuit 1 includes a first reset transistor T1 and a second reset transistor T7, wherein the reset control signal includes a first sub-reset control signal and a second sub-reset control signal.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type MOS transistors) as an example in detail.
  • the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first light-emitting control transistor T5, the first light-emitting Both the reset transistor T1 and the second reset transistor T7 and the like may be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (eg, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs. .
  • N-type transistors eg, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the control electrode is used as the gate of the transistor, one of the first electrode and the second electrode is used as the source electrode of the transistor, and the other is used as the transistor.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain of the transistor can be indistinguishable in physical structure.
  • the first electrode is directly described as the source electrode and the second electrode as the drain electrode, so all or part of the source electrodes of the transistors in the embodiments of the present disclosure are directly described. and drain are interchangeable as required.
  • the source of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the drain of the data writing transistor T4 is configured to be electrically connected to the data line Vd to receive a data signal, and the data writing transistor T4
  • the gate is configured to be electrically connected to the first scan signal line Ga1 to receive scan signals;
  • the first plate CC1 of the storage capacitor Cst is electrically connected to the first power supply terminal VDD, and the second plate of the storage capacitor Cst is connected to the drive transistor T3
  • the gate of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3, the drain of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the threshold compensation transistor T2 is configured as is electrically connected to the second scan signal line Ga2 to receive the compensation control signal;
  • the source of the first reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, and the drain of the first reset transistor T1 is
  • the two reset control signal lines Rst2 are electrically connected to receive the second sub-reset control signal; the source of the first light-emitting control transistor T5 is electrically connected to the first power supply terminal VDD, and the drain of the first light-emitting control transistor T5 is connected to the source of the driving transistor T3
  • the gate of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal;
  • the source of the second light-emitting control transistor T6 and the drain of the driving transistor T3 Electrically connected, the drain of the second light-emitting control transistor T6 is electrically connected to the first electrode D1 of the light-emitting device D, and the gate of the second light-emitting control transistor T6 is configured to be electrically connected to the second light-emitting control signal line EM2 to receive the second light-emitting control signal line EM2.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply terminal VSS can be a voltage source to output a constant first voltage
  • the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 may be electrically connected to the same signal line, such as the first scan signal line Ga1, to To receive the same signal (eg, scan signal), at this time, the display substrate may not be provided with the second scan signal line Ga2, thereby reducing the number of signal lines.
  • the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the gate of the data writing transistor T4 is electrically connected to the first scanning signal line Ga1, and the threshold The gate of the compensation transistor T2 is electrically connected to the second scan signal line Ga2, and the first scan signal line Ga1 and the second scan signal line Ga2 transmit the same signal.
  • the scan signal and the compensation control signal may also be different, so that the gate of the data writing transistor T4 and the threshold compensation transistor T2 can be controlled separately and independently, increasing the flexibility of controlling the pixel circuit.
  • the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 are electrically connected to the first scan signal line Ga1 as an example for description.
  • the first lighting control signal and the second lighting control signal may be the same, that is, the gate of the first lighting control transistor T5 and the gate of the second lighting control transistor T6 may be electrically connected to the same signal line, for example
  • the first light-emitting control signal line EM1 is used to receive the same signal (eg, the first light-emitting control signal).
  • the display substrate may not have the second light-emitting control signal line EM2 to reduce the number of signal lines.
  • the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 may also be electrically connected to different signal lines respectively, that is, the gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control transistor T5.
  • the gate of the second light emission control transistor T6 is electrically connected to the second light emission control signal line EM2
  • the signals transmitted by the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same.
  • first light-emitting control transistor T5 and the second light-emitting control transistor T6 are different types of transistors, for example, the first light-emitting control transistor T5 is a P-type transistor and the second light-emitting control transistor T6 is an N-type transistor
  • first lighting control signal and the second lighting control signal may also be different, which is not limited by the embodiment of the present disclosure.
  • the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both connected to the first light-emitting control line as an example for description.
  • the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T1 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, eg, the first reset The signal line Rst1 is controlled to receive the same signal (for example, the first sub-reset control signal).
  • the display substrate may not have the second reset control signal line Rst2 to reduce the number of signal lines.
  • the gate of the first reset transistor T1 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines respectively, that is, the gate of the first reset transistor T1 is electrically connected to the first reset control signal line Rst1 , the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the signals transmitted by the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same.
  • the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the scan signal line Ga to receive the scan signal as the second sub-reset control signal.
  • the source of the first reset transistor T1 and the source of the second reset transistor T7 are respectively connected to the first reset power terminal Vinit1 and the second reset power terminal Vinit2, and the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be It is a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same, for example, the source of the first reset transistor T1 and the source of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first reset signal and the first reset signal to control the gate of the driving transistor T3 and the first reset signal of the light-emitting element.
  • One electrode D1 can be reset, which is not limited in the present disclosure.
  • the source of the first reset transistor T1 and the source of the second reset transistor T7 may both be connected to the reset power signal line Init.
  • the specific structures of the subcircuits, such as the circuit, the storage subcircuit, the threshold compensation subcircuit, and the reset subcircuit, can be set according to actual application requirements, which are not specifically limited in the embodiments of the present disclosure.
  • the pixel circuit of the sub-pixel may be a structure including other numbers of transistors in addition to the 7T1C (ie, seven transistors and one capacitor) structure shown in FIG. 2 ,
  • a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure which is not limited in this embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view of an exemplary display substrate where the second light-emitting control transistor is connected to the light-emitting device D;
  • FIG. 4 is a layout of the positions of transistors in the display substrate according to an embodiment of the disclosure; the example shown in FIG. 4 Taking the pixel circuit of three sub-pixels in one pixel unit 100 as an example, and the position of each transistor of the pixel circuit included in one sub-pixel is illustrated, the components included in the pixel circuit in other sub-pixels are the same as the transistors included in the sub-pixel. location is roughly the same. As shown in FIG.
  • the pixel circuit of the sub-pixel includes a driving transistor T3, a data writing transistor T4, a threshold compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a first reset shown in FIG. 2.
  • FIG. 6 is a schematic diagram of an active semiconductor layer of a display substrate according to an embodiment of the disclosure; as shown in FIG. 6 , the active semiconductor layer may be formed by patterning a semiconductor material.
  • the active semiconductor layer can be used to fabricate the above-mentioned driving transistor T3, data writing transistor T4, threshold compensation transistor T2, first light-emitting control transistor T5, second light-emitting control transistor T6, first reset transistor T1 and second reset transistor T7. active layer.
  • the active semiconductor layer includes the active layer pattern (channel region) and doping region pattern (source-drain doping region) of each transistor of each sub-pixel, and the active layer pattern and doping pattern of each transistor in the same pixel circuit The area pattern is set as one.
  • the active semiconductor layer is disposed on the substrate 101, and a buffer layer 102 is formed between the substrate 101 and the active semiconductor layer.
  • the active layer may include an integrally formed low temperature polysilicon layer, a source region and a drain.
  • the regions may be conductive by doping or the like to achieve electrical connection of the structures. That is, the active semiconductor layer of each transistor of each sub-pixel 10 is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source regions and drain regions) and active regions. Layer pattern, the active layers of different transistors are separated by doping structures.
  • the active semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials and the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active semiconductor layers in the pixel circuits of the sub-pixels 10 of different colors arranged along the first direction X have no connection relationship and are disconnected from each other.
  • the active semiconductor layers in the pixel circuits of the sub-pixels 10 arranged along the second direction Y may be integrally disposed or disconnected from each other.
  • FIG. 4 also shows the scan signal line Ga (including the first scan signal line Ga1 and the second scan signal line Ga2 ), the reset control signal line Rst (including the first reset signal line Ga2 ) electrically connected to the pixel circuit 0121 of each color sub-pixel 10
  • the control signal line Rst1 and the second reset control signal line Rst2) the reset power signal line Init of the reset power supply terminal Vinit (including the first reset power supply signal line Init1 of the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2).
  • reset power signal line Init2 light emission control signal line EM (including first light emission control signal line EM1 and second light emission control signal line EM2), data line Vd, and power supply signal line VDD (including first power supply signal line VDD1 and second light emission control signal line EM2) power supply signal line VDD2).
  • the first power supply signal line VDD1 and the second power supply signal line VDD2 are electrically connected to each other.
  • the first scan signal line Ga1 and the second scan signal line Ga2 are the same scan signal line Ga, and the first reset power supply signal line Init1 and the second reset power supply signal line Init2 It is the same reset power signal line Init, the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same bit control signal line Rst, and the first light emission control signal line EM1 and the second light emission control signal line EM2 are the same.
  • a light-emitting control signal line EM but not limited to this.
  • the gate metal layer of the pixel circuit may include a first conductive layer and a second conductive layer.
  • a gate insulating layer 103 (the gate insulating layer 103 shown in FIG. 3 is formed on the above-mentioned active semiconductor layer, which is used to insulate the above-mentioned active semiconductor layer from the gate metal layer formed later.
  • FIG. 7 is this A schematic diagram of the first conductive layer of the display substrate of the disclosed embodiment, as shown in FIG.
  • the display substrate includes a first conductive layer, and the first conductive layer is disposed on the side of the gate insulating layer 103 away from the active semiconductor layer, So as to be insulated from the active semiconductor layer.
  • the first conductive layer can include the second plate CC2 of the storage capacitor Cst, the scanning signal line Ga, the reset control signal line Rst, the light emission control signal line EM, the driving transistor T3, the data writing transistor T4 , the gates of the threshold compensation transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, the first reset transistor T1 and the second reset transistor T7.
  • the gate of the data writing transistor T4 may be the portion where the scanning signal line Ga overlaps with the active semiconductor layer;
  • the gate of the first light-emitting control transistor T5 may be the light-emitting control signal line EM and the active semiconductor layer.
  • the gate of the second light-emitting control transistor T6 may be the second portion where the light-emitting control signal line EM overlaps with the active semiconductor layer; the gate of the first reset transistor T1 may be the reset control signal The first part where the line Rst overlaps with the active semiconductor layer, the gate of the second reset transistor T7 can be the second part where the reset control signal line Rst overlaps with the active semiconductor layer; the threshold compensation transistor T2 can be a double gate structure The thin film transistor, the first gate of the threshold compensation transistor T2 may be a portion where the scanning signal line Ga overlaps with the active semiconductor layer 310, and the second gate of the threshold compensation transistor T2 may be a protrusion protruding from the scanning signal line Ga The portion where the structure P overlaps with the active semiconductor layer. As shown in FIG. 4 , the gate of the driving transistor T3 can be the second plate CC2 of the storage capacitor Cst.
  • each dotted rectangle in FIG. 4 shows each portion where the first conductive layer and the active semiconductor layer overlap.
  • the active semiconductor layers on both sides of each channel region are conductorized by processes such as ion doping to form the source and drain electrodes of the respective transistors.
  • the scan signal line Ga, the reset control signal line Rst, and the light emission control signal line EM are arranged along the second direction Y.
  • the scan signal line Ga is located between the reset control signal line Rst and the light emission control signal line EM.
  • the drain CC2 of the storage capacitor Cst (ie, the gate of the driving transistor T3 ) is located between the scanning signal line Ga and the light emission control signal line EM.
  • the protruding structure P protruding from the scan signal line Ga is located on the side of the scan signal line Ga away from the light emission control signal line EM.
  • the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 are both located on the first side of the gate of the driving transistor T3, and the gate of the first reset transistor T1 Gate
  • the gate of the second reset transistor T7, the gate of the first light emission control transistor T5, and the gate of the second light emission control transistor T6 are all located on the second side of the gate of the driving transistor T3.
  • the first side and the second side of the gate of the driving transistor T3 of the pixel circuit of the sub-pixel 10 are opposite sides of the gate of the driving transistor T3 in the second direction Y .
  • the first side of the gate of the driving transistor T3 of the pixel circuit of the sub-pixel 10 may be the lower side of the gate of the driving transistor T3, and the driving of the pixel circuit of the sub-pixel 10
  • the second side of the gate of the transistor T3 may be the upper side of the gate of the drive transistor T3.
  • the lower side for example, the side of the display substrate for binding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor T3 is the side of the gate of the driving transistor T3 closer to the IC.
  • the upper side is the opposite side to the lower side, for example, the upper side is the side of the gate of the driving transistor T3 that is further away from the IC.
  • the gate of the second light-emitting control transistor T6, the gate of the second reset transistor T7, and the first gate of the threshold compensation transistor T2 are all located at the driving position
  • the third and fourth sides of the gate of the drive transistor T3 of the pixel circuit of the sub-pixel 10 are opposite sides of the gate of the drive transistor T3 in the first direction X .
  • FIG. 4 the third and fourth sides of the gate of the drive transistor T3 of the pixel circuit of the sub-pixel 10 are opposite sides of the gate of the drive transistor T3 in the first direction X .
  • the third side of the gate of the driving transistor T3 of the pixel circuit may be the left side of the gate of the driving transistor T3 of the pixel circuit
  • the fourth side of the gate of the driving transistor T3 of the pixel circuit may be It is the right side of the gate of the driving transistor T3 of the pixel circuit.
  • the left and right sides are opposite sides.
  • the data line Vd is on the right side of the first power signal line VDD1
  • the first power signal line VDD1 is on the right side of the first power signal line VDD1.
  • each pixel circuit may be the mirror structure shown in FIGS. 9A to 10 , that is, each layer structure of each pixel circuit is based on the channel region of the driving transistor T3, and the structures on the left and right sides are reversed. , so the above-mentioned relationship between the left and right sides can be reversed.
  • a first insulating layer 104 (the first insulating layer 104 shown in FIG. 3 is formed on the above-mentioned first conductive layer is used to insulate the above-mentioned first conductive layer from the subsequently formed second conductive layer.
  • Fig. 8 is a schematic diagram of the second conductive layer of the display substrate according to the embodiment of the present disclosure.
  • the second conductive layer of the pixel circuit includes the first plate CC1 of the storage capacitor Cst, the reset power supply signal, and the second conductive layer of the pixel circuit. Line Init, the second power signal line VDD2 and the second shading pattern S20.
  • the second power signal line VDD2 and the first plate CC1 of the storage capacitor Cst can be integrally formed, and the second power signal line VDD2 and the first plate CC1 of the storage capacitor Cst can be formed integrally.
  • the plate CC1 connects a plurality of first power supply signal lines VDD1 (described later) extending in the Z direction to form grid wiring to reduce resistance.
  • the source CC1 of the storage capacitor Cst is connected to the second
  • the plates CC2 are at least partially overlapped to form the storage capacitor Cst.
  • the active semiconductor layer between the two channel regions of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is vulnerable to surrounding circuits The voltage jumps due to the influence of the voltage, thereby affecting the leakage current of the threshold compensation transistor T2, thereby affecting the luminous brightness.
  • the second light shielding pattern S20 is designed to form a capacitor with the active semiconductor layer between the two channel regions of the threshold compensation transistor T2, and the second light shielding pattern S20 is designed to form a capacitor.
  • the pattern S20 may be connected to the first power supply signal line VDD1 to obtain a constant voltage, so the voltage of the active semiconductor layer in the floating state may be kept stable.
  • the second shading pattern S20 overlaps with the active semiconductor layer between the two channel regions of the dual-gate threshold compensation transistor T2, and can also prevent the active semiconductor layer between the two gates from being illuminated to change characteristics, such as preventing The voltage of this part of the active semiconductor layer is changed to prevent crosstalk.
  • the first power signal line VDD1 connected to each second light shielding pattern S20 is the one with the closest distance in the first direction X from the plurality of first power signal lines VDD1 .
  • the second light shielding pattern S20 for shielding the channel region of the threshold compensation transistor T2 in the second pixel circuit is connected to the first power supply signal line VDD1 on the left side, and the first power supply signal line VDD1 is also used to provide the first voltage for the first pixel circuit.
  • a second insulating layer 105 (the second insulating layer 105 shown in FIG. 3 ) is formed on the above-mentioned second conductive layer to insulate the above-mentioned second conductive layer from the source-drain metal layer formed subsequently .
  • 9 is a schematic diagram of a source-drain metal layer of a display substrate according to an embodiment of the disclosure.
  • the source-drain metal layer of the pixel circuit includes a data line Vd and a first power signal line VDD1 . Both the data line Vd and the first power signal line VDD1 extend in the Z direction.
  • the source-drain metal layer further includes a first connection part 21 , a second connection part 22 and a third connection part 23 .
  • FIG. 9 also shows exemplary locations of a plurality of vias through which the source-drain metal layer is connected to a plurality of film layers located between the source-drain metal layer and the substrate 101 .
  • the data line Vd is electrically connected to the drain of the data writing transistor T4 through the via hole 201 penetrating the gate insulating layer 103 , the first insulating layer 104 and the second insulating layer 105 .
  • the first power supply signal line VDD1 is electrically connected to the source of the first light emission control transistor T5 through the via hole 205 penetrating the gate insulating layer 103 , the first insulating layer 104 and the second insulating layer 105 .
  • the first power signal line VDD1 and the data line Vd are alternately arranged along the first direction X.
  • the first power supply signal line VDD1 is electrically connected to the second power supply signal line VDD2 (the first plate CC1 of the storage capacitor) through the via holes 203 and 204 penetrating the second insulating layer 105 .
  • the first power signal line VDD1 extends along the second direction Y, and the second power signal line VDD2 extends along the first direction X.
  • the first power supply signal line VDD1 and the second power supply signal line VDD2 are wired in a grid on the display substrate. That is to say, on the entire display substrate, the first power supply signal line VDD1 and the second power supply signal line VDD2 are arranged in a grid shape, so that the resistance of the signal line of the power supply terminal VDD is small and the voltage drop is low, thereby improving the power supply.
  • the first power signal line VDD1 is electrically connected to the second light shielding pattern S20 through the via hole 202 penetrating the second insulating layer 105 to provide a constant voltage to the second light shielding pattern S20.
  • One end of the first connection part 21 is electrically connected to the drain of the threshold compensation transistor T2 through the via hole 208 penetrating the gate insulating layer 103 , the first insulating layer 104 and the second insulating layer 105 , and the other end of the first connection part 21 is electrically connected to the drain of the threshold compensation transistor T2
  • the gate electrode of the driving transistor T3 ie, the drain electrode CC2 of the storage capacitor Cst
  • the third connection part 23 includes a first part and a second part, and the first part of the third connection part 23 communicates with the second light emission control through the via hole 210 penetrating the gate insulating layer 103 , the first insulating layer 104 and the second insulating layer 105 .
  • the drain of the transistor T6 is electrically connected.
  • a flattening layer 106 (the flattening layer 106 shown in FIG. 3 ) is formed on the above-mentioned source-drain metal layer to protect the above-mentioned source-drain metal layer.
  • the first electrode D1 of the light emitting device D is formed on the flat layer 106;
  • FIG. 10 is a schematic diagram of the first electrode D1 and the first light shielding pattern of the light emitting device D of the display substrate according to the embodiment of the disclosure. As shown in FIG.
  • the flat layer 106 includes a via hole 211, the first electrode D1 of the light emitting device D of each sub-pixel 10 can be arranged on the side of the flat layer 106 away from the base substrate, and the first electrode D1 of the light emitting device D is connected to the third through the via hole 211.
  • the second portion of the portion 23 is electrically connected to achieve electrical connection with the drain of the second light-emitting control transistor T6.
  • the light-emitting device D may be an organic electroluminescent diode OLED, or a diode LED.
  • the light-emitting device D is described as an organic electroluminescent diode OLED.
  • one of the first electrode and the second electrode of the light-emitting device D is the anode, and the other is the cathode.
  • the first electrode is the anode and the second electrode is the cathode as an example. describe.
  • the first light-shielding pattern and the anode are provided in the same layer and made of the same material, and the material of the anode should be a non-light-transmitting conductive material at this time.
  • the specific structure of the anode includes, but is not limited to, using a three-layer metal material of Ag/Al/Ag.
  • the size of the first electrode D1 of the light-emitting device D is different according to the different light-emitting colors of the light-emitting device D.
  • the anodes of the light-emitting devices D of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B are in an “inverted shape”, wherein the red sub-pixel 10
  • the anode D1 (R) of the light-emitting device D of the blue sub-pixel B and the anode D1 (B) of the light-emitting device D of the blue sub-pixel B are arranged along the second direction Y, and the anode D1 (G) of the light-emitting device D of the green sub-pixel G is located in the red sub-pixel G.
  • the area occupied by the anode D1 (R) of the light-emitting device D of the pixel 10 and the anode D1 (B) of the light-emitting device D of the blue sub-pixel B, and the area occupied by the anode D1 (G) of the light-emitting device D of the green sub-pixel G It is substantially the same as the anode D1 (R) of the light emitting device D of the red subpixel 10 and the anode D1 (B) of the light emitting device D of the blue subpixel B.
  • FIG. 5 is a layout of a display substrate including a first light-shielding pattern according to an embodiment of the present disclosure.
  • Two shading parts S12 , third shading parts S13 , fourth shading parts S14 , fifth shading parts S15 , and sixth shading parts S16 wherein the orthographic projection of the first shading part S11 on the substrate 101 covers the red sub-pixels 10
  • the orthographic projection of the channel region of the first reset transistor T1 on the substrate 101; the orthographic projection of the second light shielding portion S12 on the substrate 101 covers the positive projection of the channel region of the threshold compensation transistor T2 in the red sub-pixel 10 on the substrate 101.
  • the orthographic projection of the third light shielding portion S13 on the substrate 101 covers the channel region of the first reset transistor T1 in the green sub-pixel G; the orthographic projection of the fourth light-shielding portion S14 on the substrate 101 covers the green sub-pixel G
  • Orthographic projection; the orthographic projection of the sixth light shielding portion S16 on the substrate 101 covers the channel region of the threshold compensation transistor T2 in the blue sub-pixel B.
  • a first light shielding part S11 , a second light shielding part S12 , a third light shielding part S13 , and a fourth light shielding part are provided S14, the fifth shading part S15, and the sixth shading part S16, prevent the active semiconductor layer between the two gates from being illuminated to change the characteristics, for example, prevent the voltage of this part of the active semiconductor layer from changing to prevent crosstalk.
  • the first light shielding portion S11, the second light shielding portion S12, the third light shielding portion S13, the fourth light shielding portion S14, the fifth light shielding portion S15, the sixth light shielding portion S16 and the first electrode D1 of the light emitting device D are provided on the same level. That is, the first electrode D1 of the light emitting device D and the first light shielding portion S11, the second light shielding portion S12, the third light shielding portion S13, the fourth light shielding portion S14, the fifth light shielding portion S15, the Six shading parts S16, so no process steps will be added.
  • the first light-shielding portion S11 and the third light-shielding portion S13 in the pixel unit 100 located in the i-th row and the j+1-th column have an integrated structure.
  • the fifth light-shielding portion S15 in the pixel unit 100 in the j+1 column has an integrated structure; i is from 1 to N, where N is the number of pixel units 100 in each column; j is from 1 to M, and M is the pixel unit in each row number of 100.
  • Capacitance is formed by the first light shielding pattern and the active semiconductor layer between the two channel regions of the double gate transistor, the first light shielding pattern can be connected to the first electrode D1 to obtain a constant voltage, so the active semiconductor layer in a floating state
  • the voltage of the gate electrode can be kept stable, preventing the active semiconductor layer between the two gates from being illuminated to change the characteristics, for example, preventing the voltage of this part of the active semiconductor layer from changing, so as to prevent crosstalk.
  • a pixel-defining layer 107 is formed on the layer where the first electrode D1 of the light-emitting device D is located, and an opening is formed in the pixel-defining layer 107; the orthographic projection of the opening of the pixel-defining layer 107 on the substrate 101 is located at the corresponding first electrode In the orthographic projection on the substrate 101 of D1.
  • the orthographic projection of the opening of the pixel defining layer 107 on the substrate 101 is located within the orthographic projection of the corresponding light emitting layer D2 on the substrate 101 , that is, the light emitting layer D2 covers the opening of the pixel defining layer 107 .
  • the area of the light-emitting layer D2 is larger than the area of the corresponding opening of the pixel-defining layer 107 , that is, the light-emitting layer D2 includes at least the part covering the physical structure of the pixel-defining layer 107 in addition to the part inside the opening of the pixel-defining layer 107 , usually in the The physical structure of the pixel defining layer 107 at each boundary of the opening of the pixel defining layer 107 is covered with the light emitting layer D2.
  • the above description of the pattern of the light-emitting layer D2 is based on, for example, the patterned organic light-emitting layer D2 of each sub-pixel 10 formed by a fine metal mask (FMM) process.
  • FMM fine metal mask
  • the second electrode D3 of each light-emitting device D is formed on the substrate 101 on which the light-emitting layer D2 of each light-emitting device D is formed, wherein, if the first electrode D1 of the light-emitting device D is an anode, then the second electrode D3 is cathode.
  • a planar structure can be used, that is, the cathodes of the plurality of light-emitting devices D arranged in an array are integrated into one structure.
  • the above is a description of the structure when the first light shielding pattern and the first electrode D1 of the light emitting device D are disposed in the same layer in the display substrate according to the embodiment of the present disclosure.
  • the above descriptions are only some exemplary structures in the display substrate of the embodiment of the present disclosure, and do not constitute a limitation on the protection scope of the display substrate in the embodiment of the present disclosure. It should be understood that as long as the first electrode D1 of the light-emitting device D is located
  • the first light shielding pattern is provided on the same layer to shield the channel regions of the first reset transistor T1 and the threshold compensation transistor T2 in each pixel circuit, which are all within the protection scope of the embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of a source-drain metal layer of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 11 , an embodiment of the present disclosure also provides a display substrate.
  • the structure of the display substrate is substantially the same as that of the above-mentioned display substrate. The only thing is that the first light-shielding pattern in the display substrate is located in the source-drain metal layer, that is, the source-drain metal layer of the display substrate not only includes the above-mentioned data lines Vd extending along the second direction Y and extending along the second direction Y.
  • the first power supply signal line VDD1, the first connection part 21, the second connection part 22 and the third connection part 23 also include a first light shielding pattern.
  • the first light-shielding pattern includes a seventh light-shielding portion S17 and an eighth light-shielding portion S18 in each sub-pixel 10 .
  • the orthographic projection of the seventh light shielding portion S17 on the substrate 101 covers the orthographic projection of the channel region of the first reset transistor T1 on the substrate 101 .
  • the orthographic projection of the eighth light shielding portion S18 on the substrate 101 covers the orthographic projection of the channel region of the threshold compensation transistor T2 on the substrate 101 .
  • the seventh light shielding portion S17 in each sub-pixel 10 and the first power supply signal line VDD1 connected to the sub-pixel 10 are integrally formed.
  • the other end of the second connection portion 22 is electrically connected through the gate insulating layer 103 , the via hole 207 in the first insulating layer 104 and the second insulating layer 105 is electrically connected to the source of the second reset transistor T7.
  • the eighth light-shielding portion in each sub-pixel 10 is integrated with the second connection portion 22 in the sub-pixel 10 where it is located; that is, the reset power signal Vinit written on the reset power signal line Init is used as the eighth light-shielding portion Constant voltage signal of S18.
  • the seventh light-shielding part S17 and the eighth light-shielding part S18 are provided with constant voltages through the first power supply signal line VDD1 and the reset power supply signal line Init, respectively, so the voltage of the active semiconductor layer in the floating state can be kept stable, preventing the two
  • the active semiconductor layer between the gates of the first reset transistor T1 and the threshold compensation transistor T2 is illuminated to change its characteristics, for example, to prevent the voltage of the part of the active semiconductor layer from changing to prevent crosstalk.
  • the reason why the seventh light-shielding portion S17 in each sub-pixel 10 is integrated with the first power supply signal line VDD1 connected to the sub-pixel 10 is because, in some embodiments, the The two data lines Vd extending in the Y direction and the first power signal lines VDD1 extending in the second direction Y are alternately arranged, and the data lines Vd and the first power signal lines VDD1 connected to the sub-pixels 10 in the same column are located on the same side of the respective sub-pixels 10 (Fig.
  • the first power supply signal line VDD1 is located between the sub-pixel 10 and the data line to which it is connected, so that the seventh light shielding part in each sub-pixel 10 is blocked.
  • S17 and the first power supply signal line VDD1 connected to the sub-pixel 10 are integrally formed, which avoids the problem of short circuit between the seventh light shielding portion S17 and the data line.
  • the other structures of the display substrate of this structure can be the same as the structures of the above-mentioned display substrate, so they will not be described in detail here.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display device provided in this embodiment may be any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present invention.
  • the display device may also include various types of display devices, such as a liquid crystal display device, an organic electroluminescence (OLED) display device, and a mini diode (Mini LED) display device, which are not limited herein.
  • display devices such as a liquid crystal display device, an organic electroluminescence (OLED) display device, and a mini diode (Mini LED) display device, which are not limited herein.

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Abstract

一种显示基板及显示装置，包括：基底(101)，多个像素单元(100)，沿第一方向排布成多行、沿第二方向排布成多列，并设置在基底(101)上，且多个像素单元(100)中的每个包括多个子像素(10)；多个子像素(10)中的每个包括像素电路；有源半导体层，其包括各像素电路中的各晶体管的沟道区和源漏掺杂区，像素电路至少包括驱动晶体管(T3)、数据写入晶体管(T4)、存储电容(Cst)、阈值补偿晶体管(T2)、第一复位晶体管(T1)、发光器件；第一遮光图案，设置在有源半导体层背离基底(101)的一侧，第一遮光图案在基底(101)上的正投影覆盖第一复位晶体管(T1)和阈值补偿晶体管(T2)的沟道区在基底(101)上的正投影。

Description

显示基板及显示装置 技术领域
本发明属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
随着有机发光二极管显示技术，例如有源矩阵有机发光二极管(AMOLED)显示技术的发展，人们对显示效果的要求越来越高。因此，提供一种性能较优的显示装置是亟需要解决的技术问题。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示装置。
第一方面，本公开实施例提供一种显示基板，其包括：
基底，
多个像素单元，沿第一方向排布成多行、沿第二方向排布成多列，并设置在所述基底上，且所述多个像素单元中的每个包括多个子像素；所述多个子像素中的每个包括像素电路；
有源半导体层，其包括各所述像素电路中的各晶体管的沟道区和源漏掺杂区，所述像素电路至少包括驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一复位晶体管、发光器件；
第一遮光图案，设置在所述有源半导体层背离所述基底的一侧，所述第一遮光图案在所述基底上的正投影覆盖所述第一复位晶体管和所述阈值补偿晶体管的沟道区在基底上的正投影。
其中，各所述像素电路还包括第二复位晶体管、第一发光控制晶体管和第二发光控制晶体管；
对于位于同一行的各所述子像素而言，各所述像素电路中的第一复位晶 体管和第二复位晶体管大致位于沿第一方向延伸的直线上；各所述像素电路中的第一发光控制晶体管和第二发光控制晶体管大致位于沿第一方向延伸的直线上各所述像素电路中的阈值补偿晶体管和数据写入晶体管大致位于沿第一方向延伸的直线上；
对于位于同一列的各所述子像素而言，各像素电路中的第二复位晶体管、第二发光控制晶体管和阈值补偿晶体管大致位于沿第二方向延伸的直线上；各像素电路中的第一复位晶体管、第一发光控制晶体管和数据写入晶体管大致位于沿第二方向延伸的直线上。
其中，所述驱动晶体管的控制极包括沿第二方向相对设置的第一侧和第二侧；对于每个所述子像素的像素电路而言，所述第一复位晶体管、第二复位晶体管、第一发光控制晶体管和第二发光控制晶体管位于所述第一侧；所述阈值补偿晶体管和所述数据写入晶体管位于所述第二侧。
其中，各所述像素电路中的发光器件包括位于各所述像素电路中的晶体管背离基底一侧，依次设置的第一电极、发光层、第二电极；所述第一遮光图案与所述发光器件的第一电极同层设置且材料相同。
其中，各所述像素单元中的多个子像素包括第一颜色子像素、第二颜色子像素、第三颜色子像素；所述第一遮光图案包括每个子像素中的第一遮光部、第二遮光部、第三遮光部、第四遮光部、第五遮光部、第六遮光部；
所述第一遮光部在所述基底上的正投影覆盖第一颜色子像素中的第一复位晶体管的沟道区在所述基底上的正投影；所述第二遮光部在所述基底上的正投影覆盖第一颜色子像素中的阈值补偿晶体管的沟道区在所述基底上的正投影；所述第三遮光部在所述基底上的正投影覆盖第二颜色子像素中的第一复位晶体管的沟道区在所述基底上的正投影；所述第四遮光部在所述基底上的正投影覆盖所述第二颜色子像素中的阈值补偿晶体管的沟道区在所述基底上的正投影；所述第五遮光部在所述基底上的正投影覆盖第三颜色子像素中的第一复位晶体管的沟道区在所述基底上的正投影；所述第六遮光部在所述基底上的正投影覆盖第三颜色子像素中的阈值补偿晶体管的沟道区 在所述基底上的正投影。
其中，对于位于同一列的所述像素单元，各所述第二颜色子像素的像素电路中的发光器件的第一电极大致位于沿第二方向延伸的直线上；各所述第一颜色子像素和第二颜色子像素的像素电路中的发光器件的第一电极大致位于沿第二方向延伸的直线上；
位于第i行第j列的所述像素单元中的第三颜色子像素的发光器件的第一电极与该像素单元的第二遮光部，以及位于第i行第j+1列的所述像素单元中的第一遮光部和第三遮光部为一体结构；
位于第i行第j列的所述像素单元中的第二颜色子像素的发光器件的第一电极与该像素单元的第四遮光部和第六遮光部，以及位于第i行第j+1列的所述像素单元中的第五遮光部为一体结构；其中，i取1至N，N为每一列中所述像素单元的个数；j取1至M，M为每一行中所述像素单元的个数。
其中，所述显示基板还包括：
栅极绝缘层，设置在所述有源半导体层背离所述基底的一侧；
第一导电层，设置在所述栅极绝缘层背离所述有源半导体层的一侧；所述第一导电层包括所述存储电容的第二极板、沿所述第一方向延伸的扫描信号线、沿所述第一方向延伸的复位控制信号线、沿所述第一方向延伸的发光控制信号线以及所述驱动晶体管、所述数据写入晶体管、所述阈值补偿晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、所述第一复位晶体管和所述第二复位晶体管的控制极，所述驱动晶体管的控制极复用为所述存储电容的第二极；
第一绝缘层，设置在所述第一导电层背离所述栅极绝缘层的一侧；
第二导电层，设置在第一绝缘层背离所述第一导电层的一侧；所述第二导电层包括沿所述第一方向延伸的复位电源信号线以及所述存储电容的第一极板；
第二绝缘层，设置在所述第二导电层背离所述第一绝缘层的一侧；
源漏金属层，设置在所述第二绝缘层背离所述第二导电层的一侧；所述源漏金属层包括沿所述第二方向延伸的电源信号线、沿所述第二方向延伸的数据线、第一连接部、第二连接部以及第三连接部；
平坦层，设置在设置在所述源漏金属层和所述发光器件的第一电极之间；
所述第一连接部被配置为连接所述阈值补偿晶体管的第二极和所述驱动晶体管的控制极，所述第二连接部被配置为连接所述复位电源信号线和所述第二复位晶体管的第一极，所述第三连接部被配置为连接所述发光器件的第一电极与所述第二发光控制晶体管的第二极；
所述第三连接部包括第一部分和第二部分，所述第三连接部的第一部分通过贯穿所述栅极绝缘层、所述第一绝缘层和所述第二绝缘层中的过孔与所述第二发光控制晶体管的第二极电连接，所述第三连接部的第二部分通过贯穿所述平坦层的过孔与所述发光器件的第一电极电连接。
其中，所述第二导电层还包括各所述子像素中设置的第二遮光图案；各所述子像素中的第二遮光图案在所述基底上正投影覆盖该所述子像素中的像素电路的阈值补偿晶体管的沟道区在所述基底上正投影，且所述第二遮光图案与第一电源信号线电连接。
其中，每个所述第二遮光图案所连接的所述第一电源信号线为多条第一电源信号线中与之在第一方向上距离最近的一条。
其中，所述显示基板还包括：
栅极绝缘层，设置在所述有源半导体层背离所述基底的一侧；
第一导电层，设置在所述栅极绝缘层背离所述有源半导体层的一侧；所述第一导电层包括所述存储电容的第二极板、沿所述第一方向延伸的扫描信号线、沿所述第一方向延伸的复位控制信号线、沿所述第一方向延伸的发光控制信号线以及所述驱动晶体管、所述数据写入晶体管、所述阈值补偿晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、所述第一复位晶 体管和所述第二复位晶体管的控制极，所述驱动晶体管的控制极复用为所述存储电容的第二极；
第一绝缘层，设置在所述第一导电层背离所述栅极绝缘层的一侧；
第二导电层，设置在第一绝缘层背离所述第一导电层的一侧；所述第二导电层包括沿所述第一方向延伸的复位电源信号线以及所述存储电容的第一极板；
第二绝缘层，设置在所述第二导电层背离所述第一绝缘层的一侧；
源漏金属层，设置在所述第二绝缘层背离所述第二导电层的一侧；所述源漏金属层包括沿所述第二方向延伸的电源信号线、沿所述第二方向延伸的数据线以及所述第一遮光图案。
其中，所述第一遮光图案包括每个子像素中的第七遮光部和第八遮光部；所述第七遮光部在所述基底正投影覆盖其所在所述子像素中的像素电路的第一复位晶体管的沟道区在基底上的正投影；所述第七遮光部在所述基底正投影覆盖其所在所述子像素中的像素电路的阈值补偿晶体管的沟道区在基底上的正投影；
所述七遮光部与其所在所述子像素所连接的所述电源信号线为一体结构。
其中，所述显示基板还包括：平坦层，设置在设置在所述源漏金属层和所述发光器件的第一电极之间；
所述源漏金属层还包括：第一连接部、第二连接部以及第三连接部；
所述第一连接部被配置为连接所述阈值补偿晶体管的第二极和所述驱动晶体管的控制极，所述第二连接部被配置为连接所述复位电源信号线和所述第二复位晶体管的第一极，所述第三连接部被配置为连接所述发光器件的第一电极与所述第二发光控制晶体管的第二极；
所述第三连接部包括第一部分和第二部分，所述第三连接部的第一部分通过贯穿所述栅极绝缘层、所述第一绝缘层和所述第二绝缘层中的过孔与所 述第二发光控制晶体管的第二极电连接，所述第三连接部的第二部分通过贯穿所述平坦层的过孔与所述发光器件的第一电极电连接；
所述第八遮光部与所述第二连接部为一体结构。
其中，所述第二导电层还包括各所述子像素中设置的第二遮光图案；各所述子像素中的第二遮光图案在所述基底上正投影覆盖该所述子像素中的像素电路的阈值补偿晶体管的沟道区在所述基底上正投影，且所述第二遮光图案与第一电源信号线电连接。
其中，每个所述第二遮光图案所连接的所述第一电源信号线为多条第一电源信号线中与之在第一方向上距离最近的一条。
其中，所述第一复位晶体管和所述阈值补偿晶体管均为双栅晶体管。
第二方面，本公开实施例提供一种显示装置，其包括上述的任意一种显示基板。
附图说明
图1为一种示例性的显示基板的结构示意图。
图2为一种示例性的像素电路示意图。
图3为一种示例性的显示基板的中的第二发光控制晶体管与发光器件连接的截面图。
图4为本公开实施例的显示基板的各各晶体管位置的版图。
图5为本公开实施例的显示基板的包含第一遮光图案的版图。
图6为本公开实施例的显示基板的有源半导体层的示意图。
图7为本公开实施例的显示基板的第一导电层的示意图。
图8为本公开实施例的显示基板的第二导电层的示意图。
图9为本公开实施例的显示基板的源漏金属层的示意图。
图10为本公开实施例的显示基板的发光器件的第一电极和第一遮光图 案的示意图。
图11为本公开实施例的显示基板的源漏金属层的示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
第一方面，本公开实施例中提供一种显示基板，该显示基板其包括：基底、多个像素单元、有源层半导体层、第一遮光图案；其中，多个像素单元设置在基底上，并呈阵列排布，也即沿第一方向排布成多行、沿第二方向排布成多列。每个像素单元包括多个子像素，在每个子像素包括像素电路；像素电路至少包括驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一复位晶体管、发光器件；在本公开实施例中，第一复位晶体管被配置为响应于复位控制信号，并通过复位电源信号对存储电容进行初始化；数据写入晶体管被配置为响应于扫描信号，将数据电压信号写入存储电容的驱动晶体管的第一极，并通过存储电容进行存储；阈值补偿晶体管被配置为响应于扫描信号，以对驱动晶体管的阈值电压进行补偿；驱动晶体管被配置为根据其第一极和控制极的电压控制发光器件的工作。特别的是，在本公开实施例中，有源半导体层，其包括各像素电路中的各晶体管的沟道区和源漏掺杂 区，第一遮光图案设置在有源半导体层背离基底的一侧，第一遮光图案在基底上的正投影覆盖所述第一复位晶体管和阈值补偿晶体管的沟道区在基底上的正投影。
在本公开实施例中，由于在显示基板中设置第一遮光图案，且第一遮光图案在基底上的正投影覆盖所述第一复位晶体管和阈值补偿晶体管的沟道区在基底上的正投影，也即通过第一遮光图案对第一复位晶体管和阈值补偿晶体管的沟道区进行遮挡，因此可以有效的避免第一复位晶体管和阈值补偿晶体管T2的沟道区被光照，而影响第一复位晶体管和阈值补偿晶体管的开关特性。
在一些实施例中，该显示基板中的基底101采用柔性基底，具体可以为聚酰亚胺PI材质。当然，基底101也可以采用玻璃基底等刚性材质。
在一些实施例中，为了防止晶体管的漏电流对电路性能的影响，在本公开实施例中将第一复位晶体管和阈值补偿晶体管设计为双栅晶体管；而在下述描述中也是以第一复位晶体管和阈值补偿晶体管为例进行说明的，但第一复位晶体管和阈值补偿晶体管也可以采用单栅晶体管，均在本公开实施例的保护范围内。
在一些实施例中，图5为本公开实施例的显示基板的包含第一遮光图案的版图，如图5所示，本公开实施例中的第一遮光图案与发光器件的第一电极同层设置且材料相同；这样一来，并不会增加显示基板的整体厚度，也不会增加工艺步骤，以下结合具体示例对本公开实施例的显示基板的结构进行说明。
图1为一种示例性的显示基板结构示意图；图2为一种示例性的像素电路示意图；如图1-2所示，该显示基板包括基底101，在基底101上设置有多个呈阵列的像素单元100，每个像素单元100中包括三种颜色的子像素10，分别为第一颜色子像素、第二颜色子像素、第三颜色子像素。在本公开实施例中，以第一颜色子像素为红色子像素，第二颜色子像素为绿色子像素，第三颜色子像素为蓝色子像素为例进行描述。但不限于此，各颜色可以互换。 其中，各子像素中的设置有像素电路。各子像素中的像素电路可以包括驱动子电路3、第一发光控制子电路5、第二发光控制子电路6、数据写入子电路4、存储子电路7、阈值补偿子电路2、复位子电路1和发光器件D。
在此需要说明的是，在本公开实施例中每个像素单元100中包括三种颜色的子像素10，而对于每个像素单元100中所包含的三种颜色的子像素10的数量并进行限定。例如：以第一颜色子像素为红色子像素，第二颜色子像素为绿色子像素，第三颜色子像素为蓝色子像素为例，每个像素单元100中的红色子像素的数量为2个，绿色子像素和蓝色子像素的数量；或者，每个像素单元100中的绿色子像素的数量为2个，红色子像素和蓝色子像素的数量；亦或者，每个像素单元100中的蓝色子像素的数量为2个，红色子像素和绿色子像素的数量。当然，还需要说明的是，在本公开实施例中，每个像素单元100中的子像素10的颜色也局限于三种。例如，每个像素单元中包括红色子像素、绿色子像素、蓝色子像素、白色子像素四种颜色的子像素10。
其中，第一发光控制子电路5分别与第一电压端VDD以及驱动子电路3的第一端相连，且被配置为实现驱动子电路和第一电压端VDD之间的连接导通或断开，第二发光控制子电路6分别与驱动子电路的第二端和发光器件D的第一电极D1电连接，且被配置为实现驱动子电路3和发光器件D之间的连接导通或断开。数据写入子电路4与驱动子电路3的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储子电路7。存储子电路8分别与驱动子电路3的控制端和第一电压端VDD电连接，且被配置为存储数据信号。阈值补偿子电路2分别与驱动子电路3的控制端和第二端电连接，且被配置为对驱动子电路3进行阈值补偿。复位子电路1与驱动子电路3的控制端和发光器件D的第一电极D1电连接，且被配置为在复位控制信号的控制下对驱动子电路3的控制端和发光器件D的第一电极D1进行复位。
继续参照图1，驱动子电路3包括驱动晶体管T3，驱动子电路3的控制端包括驱动晶体管T3的控制极，驱动子电路3的第一端包括驱动晶体管T3的第一极，驱动子电路3的第二端包括驱动晶体管T3的第二极。数据写入 子电路4包括数据写入晶体管T4，存储子电路7包括存储电容Cst，阈值补偿子电路2包括阈值补偿晶体管T2，第一发光控制子电路5包括第一发光控制晶体管T5，第二发光控制子电路6包括第二发光控制晶体管T6，复位子电路1包括第一复位晶体管T1和第二复位晶体管T7，其中，复位控制信号包括第一子复位控制信号和第二子复位控制信号。
在此需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开的实施例中的一个或多个晶体管的功能。
另外，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。对于每个晶体管其均包括第一极、第二极和控制极；其中，控制极作为晶体管的栅极，第一极和第二极中的一者作为晶体管的源极，另一者作为晶体管的漏极；而晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中第一极为源极，第二极为漏极，所以本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
继续参照图2，数据写入晶体管T4源极的与驱动晶体管T3的源极电连接，数据写入晶体管T4的漏极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T4的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；存储电容Cst的第一极板CC1与第一电源端VDD电连接，存储电容Cst的第二极板与驱动晶体管T3的栅极电连接；阈值补偿晶体管T2的源 极与驱动晶体管T3的漏极电连接，阈值补偿晶体管T2的漏极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T1的源极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T1的漏极与驱动晶体管T3的栅极电连接，第一复位晶体管T1的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的源极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第二复位晶体管T7的漏极与发光器件D的第一电极D1电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T5的源极与第一电源端VDD电连接，第一发光控制晶体管T5的漏极与驱动晶体管T3的源极电连接，第一发光控制晶体管T5的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T6的源极与驱动晶体管T3的漏极电连接，第二发光控制晶体管T6的漏极与发光器件D的第一电极D1电连接，第二发光控制晶体管T6的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光器件D的第二电极D3与第二电源端VSS电连接。
例如，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图8所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
继续参照图2，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T4的栅极和阈值补偿晶体管T2的栅极可以电连接到同一条信号线，例如第一扫描信号线Ga1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线Ga2，减少信号线的数量。又例如，数据写入晶体管T4的栅极和阈值补偿晶体管T2的栅极也可以分别电连接至不同的信号线，即数据写入晶体管T4的栅极电连接到第一扫描信号线Ga1，阈值补 偿晶体管T2的栅极电连接到第二扫描信号线Ga2，而第一扫描信号线Ga1和第二扫描信号线Ga2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T4的栅极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。在本公开实施例中以数据写入晶体管T4的栅极和阈值补偿晶体管T2的栅极电连接第一扫描信号线Ga1为例进行说明。
继续参照图2，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T5的栅极电连接到第一发光控制信号线EM1，第二发光控制晶体管T6的栅极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T5和第二发光控制晶体管T6为不同类型的晶体管，例如，第一发光控制晶体管T5为P型晶体管，而第二发光控制晶体管T6为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。在本公开实施例中以第一发光控制晶体管T5和第二发光控制晶体管T6的栅极均连接第一发光控制线为例进行说明。
例如，第一子复位控制信号和第二子复位控制信号可以相同，即，第一复位晶体管T1的栅极和第二复位晶体管T7的栅极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第一复位晶体管T1的栅极和第二复位晶体管T7的栅极也可以分别电连接至不同的信号线，即第一复位晶体管T1的栅极电连接 到第一复位控制信号线Rst1，第二复位晶体管T7的栅极电连接到第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一子复位控制信号和第二子复位控制信号也可以不相同。
例如，在一些示例中，第二子复位控制信号可以与扫描信号相同，即第二复位晶体管T7的栅极可以电连接到扫描信号线Ga以接收扫描信号作为第二子复位控制信号。
例如，第一复位晶体管T1的源极和第二复位晶体管T7的源极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T1的源极和第二复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第一复位信号以对驱动晶体管T3的栅极和发光元件的第一电极D1进行复位即可，本公开对此不作限制。例如，第一复位晶体管T1的源极和第二复位晶体管T7的源极可以均连接至复位电源信号线Init。
需要说明的是，图2所示的像素电路中的驱动子电路、数据写入子电路、存储子电路、阈值补偿子电路和复位子电路仅为示意性的，驱动子电路、数据写入子电路、存储子电路、阈值补偿子电路和复位子电路等子电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
需要说明的是，在本公开实施例中，子像素的像素电路除了可以为图2所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图3为一种示例性的显示基板的中的第二发光控制晶体管与发光器件D连接的截面图；图4为本公开实施例的显示基板的各晶体管位置的版图；图 4所示的示例以一个像素单元100中的三个子像素的像素电路为例，且以一个子像素包括的像素电路的各晶体管的位置进行示意，其他子像素中像素电路包括的部件与该子像素包括的各晶体管的位置大致相同。如图4所示，该子像素的像素电路包括图2所示的驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1和第二复位晶体管T7、存储电容Cst。
例如，图6为本公开实施例的显示基板的有源半导体层的示意图；如图6所示，有源半导体层可采用半导体材料图案化形成。有源半导体层可用于制作上述的驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1和第二复位晶体管T7的有源层。有源半导体层包括各子像素的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源半导体层设置在基底101上，且在基底101和有源半导体层之间形成有缓冲层102，有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化以实现各结构的电连接。也就是每个子像素10的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，沿第一方向X排列的不同颜色子像素10的像素电路中的有源半导体层没有连接关系，彼此断开。沿第二方向Y排列的子像素10的像素电路中的有源半导体层可以为一体设置，也可以彼此断开。
图4还示出了电连接到各个颜色子像素10的像素电路0121的扫描信号线Ga(包括第一扫描信号线Ga1和第二扫描信号线Ga2)、复位控制信号线 Rst(包括第一复位控制信号线Rst1和第二复位控制信号线Rst2)、复位电源端Vinit的复位电源信号线Init(包括第一复位电源端Vinit1的第一复位电源信号线Init1以及第二复位电源端Vinit2的第二复位电源信号线Init2)、发光控制信号线EM(包括第一发光控制信号线EM1和第二发光控制信号线EM2)、数据线Vd以及电源信号线VDD(包括第一电源信号线VDD1以及第二电源信号线VDD2)。第一电源信号线VDD1和第二电源信号线VDD2彼此电连接。
需要说明的是，在图4所示的示例中，第一扫描信号线Ga1和第二扫描信号线Ga2为同一条扫描信号线Ga，第一复位电源信号线Init1和第二复位电源信号线Init2为同一条复位电源信号线Init，第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条位控制信号线Rst，第一发光控制信号线EM1和第二发光控制信号线EM2为同一条发光控制信号线EM，但不限于此。
例如，像素电路的栅极金属层可以包括第一导电层和第二导电层。在上述的有源半导体层上形成有栅极绝缘层103(图3所示的栅极绝缘层103，用于将上述的有源半导体层与后续形成的栅极金属层绝缘。图7为本公开实施例的显示基板的第一导电层的示意图，如图7所示，该显示基板包括的第一导电层，第一导电层设置在栅极绝缘层103远离有源半导体层的一侧，从而与有源半导体层绝缘。第一导电层可以包括存储电容Cst的第二极板CC2、扫描信号线Ga、复位控制信号线Rst、发光控制信号线EM以及驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T1和第二复位晶体管T7的栅极。
例如，如图4所示，数据写入晶体管T4的栅极可以为扫描信号线Ga与有源半导体层交叠的部分；第一发光控制晶体管T5的栅极可以为发光控制信号线EM与有源半导体层交叠的第一部分，第二发光控制晶体管T6的栅极可以为发光控制信号线EM与有源半导体层交叠的第二部分；第一复位晶体管T1的栅极可以为复位控制信号线Rst与有源半导体层交叠的第一部分， 第二复位晶体管T7的栅极可以为复位控制信号线Rst与有源半导体层交叠的第二部分；阈值补偿晶体管T2可为双栅结构的薄膜晶体管，阈值补偿晶体管T2的第一个栅极可为扫描信号线Ga与有源半导体层310交叠的部分，阈值补偿晶体管T2的第二个栅极可为从扫描信号线Ga突出的突出结构P与有源半导体层交叠的部分。如图4所示，驱动晶体管T3的栅极可为存储电容Cst的第二极板CC2。
需要说明的是，图4中的各虚线矩形框示出了第一导电层与有源半导体层交叠的各个部分。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化以形成各个晶体管的源极和漏极。
例如，如图4所示，扫描信号线Ga、复位控制信号线Rst和发光控制信号线EM沿第二方向Y排布。扫描信号线Ga位于复位控制信号线Rst和发光控制信号线EM之间。
例如，在第二方向Y上，存储电容Cst的漏极CC2(即驱动晶体管T3的栅极)位于扫描信号线Ga和发光控制信号线EM之间。从扫描信号线Ga突出的突出结构P位于扫描信号线Ga的远离发光控制信号线EM的一侧。
例如，如图4所示，在第二方向Y上，数据写入晶体管T4的栅极、阈值补偿晶体管T2的栅极均位于驱动晶体管T3的栅极的第一侧，第一复位晶体管T1的栅极第二复位晶体管T7的栅极、第一发光控制晶体管T5的栅极以及第二发光控制晶体管T6的栅极均位于驱动晶体管T3的栅极的第二侧。例如，图4所示的示例中，子像素10的像素电路的驱动晶体管T3的栅极的第一侧和第二侧为在第二方向Y上驱动晶体管T3的栅极的彼此相对的两侧。例如，如图4所示，在XZ面内，子像素10的像素电路的驱动晶体管T3的栅极的第一侧可以为驱动晶体管T3的栅极的下侧，子像素10的像素电路的驱动晶体管T3的栅极的第二侧可以为驱动晶体管T3的栅极的上侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管T3的栅极的下侧，为驱动晶体管T3的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如上侧为驱动晶体管T3的栅极的更远离IC的一侧。
在一些实施例中，如图4所示，在第一方向X上，第二发光控制晶体管T6的栅极、第二复位晶体管T7栅极、阈值补偿晶体管T2的第一个栅极均位于驱动晶体管T3的栅极的第三侧；第一发光控制晶体管T5的栅极、数据写入晶体管T4的栅极、第一复位晶体管T1的栅极和均位于驱动晶体管T3的栅极的第四侧。例如，图4所示的示例中，子像素10的像素电路的驱动晶体管T3的栅极的第三侧和第四侧为在第一方向X上驱动晶体管T3的栅极的彼此相对的两侧。例如，如图4所示，像素电路的驱动晶体管T3的栅极的第三侧可以为像素电路的驱动晶体管T3的栅极的左侧，像素电路的驱动晶体管T3的栅极的第四侧可以为像素电路的驱动晶体管T3的栅极的右侧。所述左侧和右侧为相对侧，例如与同一像素电路连接的数据线Vd和第一电源信号线VDD1中，数据线Vd在第一电源信号线VDD1右侧，第一电源信号线VDD1在数据线Vd左侧。
需要说明的是，各个像素电路的结构可以为图9A-图10所示的镜像结构，即各个像素电路的各层结构均以驱动晶体管T3的沟道区为基准，左右两侧的结构进行翻转，因此上述所述的左侧和右侧的关系可以是相反的。
例如，在上述的第一导电层上形成有第一绝缘层104(如图3所示的第一绝缘层104，用于将上述的第一导电层与后续形成的第二导电层绝缘。图8为本公开实施例的显示基板的第二导电层的示意图，如图8所示，该像素电路的第二导电层，第二导电层包括存储电容Cst的第一极板CC1、复位电源信号线Init、第二电源信号线VDD2以及第二遮光图案S20。第二电源信号线VDD2与存储电容Cst的第一极板CC1可一体形成，通过第二电源信号线VDD2与存储电容Cst的第一极板CC1，将在Z方向延伸的多条第一电源信号线VDD1(后续描述)进行连通，进而形成网格化布线，以降低电阻。存储电容Cst的源极CC1与存储电容Cst的第二极板CC2至少部分重叠以形成存储电容Cst。
在一些实施例中，如图8所示，双栅型阈值补偿晶体管T2两段沟道区之间的有源半导体层在阈值补偿晶体管T2关闭时处于浮置(floating)状态， 易受周围线路电压的影响而跳变，从而会影响阈值补偿晶体管T2的漏电流，进而影响发光亮度。为了保持阈值补偿晶体管T2两段沟道区之间的有源半导体层电压稳定，设计第二遮光图案S20与阈值补偿晶体管T2两段沟道区之间的有源半导体层形成电容，第二遮光图案S20可以连接至第一电源信号线VDD1以获得恒定电压，因此处于浮置状态的有源半导体层的电压可以保持稳定。第二遮光图案S20与双栅型阈值补偿晶体管T2两段沟道区之间的有源半导体层交叠，还可以防止两个栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
在一个示例中，如图4所示，每个第二遮光图案S20所连接的第一电源信号线VDD1为多条第一电源信号线VDD1中与之在第一方向X上距离最近的一条。例如：如图4所示，用于遮挡第二个像素电路中的阈值补偿晶体管T2的沟道区的第二遮光图案S20连接其左侧的第一电源信号线VDD1，该第一电源信号线VDD1还用于为第一个像素电路提供第一电压。
例如，在上述的第二导电层上形成有第二绝缘层105(如图3所示的第二绝缘层105)，用于将上述的第二导电层与后续形成的源漏极金属层绝缘。图9为本公开实施例的显示基板的源漏金属层的示意图，如图9所示，该像素电路的源漏极金属层，源漏极金属层包括数据线Vd以及第一电源信号线VDD1。上述数据线Vd以及第一电源信号线VDD1均沿Z方向延伸。
例如，源漏极金属层还包括第一连接部21、第二连接部22和第三连接部23。图9还示出了多个过孔的示例性位置，源漏金属层通过所示的多个过孔与位于该源漏金属层与基底101之间的多个膜层连接。例如，如图3、图9所示，数据线Vd通过贯穿栅极绝缘层103、第一绝缘层104和第二绝缘层105的过孔201与数据写入晶体管T4的漏极电连接。第一电源信号线VDD1通过贯穿栅极绝缘层103、第一绝缘层104和第二绝缘层105的过孔205与第一发光控制晶体管T5的源极电连接。第一电源信号线VDD1和数据线Vd沿第一方向X交替设置。第一电源信号线VDD1通过贯穿第二绝缘层105的过孔203、204与第二电源信号线VDD2(存储电容的第一极板CC1)电 连接。第一电源信号线VDD1沿第二方向Y延伸，第二电源信号线VDD2沿第一方向X延伸。第一电源信号线VDD1和第二电源信号线VDD2在显示基板上网格化布线。也就是说，在整个显示基板上，第一电源信号线VDD1和第二电源信号线VDD2呈网格状排列，从而电源端VDD的信号线的电阻较小、压降较低，进而可以提高电源端VDD提供的电源电压的稳定性和均匀性。第一电源信号线VDD1通过贯穿第二绝缘层105的过孔202与第二遮光图案S20电连接以为第二遮光图案S20提供恒定电压。第一连接部21的一端通过贯穿栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔208与阈值补偿晶体管T2的漏极电连接，第一连接部21的另一端通过贯穿第一绝缘层104和第二绝缘层105中的过孔209与驱动晶体管T3的栅极(即存储电容Cst的漏极CC2)电连接。第二连接部22的一端通过贯穿第二绝缘层105中的过孔206与复位电源信号线Init电连接，第二连接部22的另一端通过贯穿栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔207与第二复位晶体管T7的源极电连接。第三连接部23包括第一部分和第二部分，第三连接部23的第一部分通过贯穿栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔210与第二发光控制晶体管T6的漏极电连接。
例如，在上述的源漏极金属层上形成有平坦层106(如图3所示的平坦层106)用于保护上述的源漏极金属层。在平坦层106上形成发光器件D的第一电极D1；图10为本公开实施例的显示基板的发光器件D的第一电极D1和第一遮光图案的示意图，如图10所示，平坦层106包括过孔211，各个子像素10的发光器件D的第一电极D1可设置在平坦层106远离衬底基板的一侧，且发光器件D的第一电极D1通过过孔211与第三连接部23的第二部分电连接，以实现与第二发光控制晶体管T6的漏极电连接。
在一些实施例中，发光器件D可以为有机电致发光二极管OLED，也可以为二极管LED，在本公开实施例中是以发光器件D为有机电致发光二极管OLED进行说明的。其中，发光器件D的第一电极和第二电极中的一者为阳极，另一者则为阴极，在下述描述中为描述简便，以第一电极为阳极，第二 电极为阴极为例进行描述。同时应当理解的是，第一遮光图案与阳极同层设置且材料相同，此时该阳极的材料应当为非透光的导电材料。具体的阳极的结构包括但不限于采用由Ag/Al/Ag三层金属材料形成。
在一些实施例中，根据发光器件D的发光颜色不同，发光器件D的第一电极D1的尺寸各有不同。参照图10，其中，对于每个像素单元100而言，红色子像素R、绿色子像素G、蓝色子像素B的发光器件D的阳极呈“倒品字型”，其中，红色子像素10的发光器件D的阳极D1(R)和蓝色子像素B的发光器件D的阳极D1(B)沿第二方向Y排列，绿色子像素G的发光器件D的阳极D1(G)位于红色子像素10的发光器件D的阳极D1(R)和蓝色子像素B的发光器件D的阳极D1(B)的左侧，且绿色子像素G的发光器件D的阳极D1(G)所占面积与红色子像素10的发光器件D的阳极D1(R)和蓝色子像素B的发光器件D的阳极D1(B)大致相同。
在一些实施例中，图5为本公开实施例的显示基板的包含第一遮光图案的版图，如图5所示，第一遮光图案包括每个像素单元100中的第一遮光部S11、第二遮光部S12、第三遮光部S13、第四遮光部S14、第五遮光部S15、第六遮光部S16；其中，第一遮光部S11在基底101上的正投影覆盖红色子像素10中的第一复位晶体管T1的沟道区在基底101上的正投影；第二遮光部S12在基底101上的正投影覆盖红色子像素10中的阈值补偿晶体管T2的沟道区在基底101上的正投影；第三遮光部S13在基底101上的正投影覆盖绿色子像素G中的第一复位晶体管T1的沟道区；第四遮光部S14在基底101上的正投影覆盖绿色子像素G中的阈值补偿晶体管T2的沟道区在基底101上的正投影；第五遮光部S15在基底101上的正投影覆盖蓝色子像素B中的第一复位晶体管T1的沟道区在基底101上的正投影；第六遮光部S16在基底101上的正投影覆盖蓝色子像素B中的阈值补偿晶体管T2的沟道区。由于各个像素电路中的第一复位晶体管T1和阈值补偿晶体管T2采用双栅晶体管，在本公开实施例中设置第一遮光部S11、第二遮光部S12、第三遮光部S13、第四遮光部S14、第五遮光部S15、第六遮光部S16，防止两个栅极之 间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
在一个示例中，第一遮光部S11、第二遮光部S12、第三遮光部S13、第四遮光部S14、第五遮光部S15、第六遮光部S16与发光器件D的第一电极D1设置在同一层。也就是说，可以在一次工艺中形成发光器件D的第一电极D1和第一遮光部S11、第二遮光部S12、第三遮光部S13、第四遮光部S14、第五遮光部S15、第六遮光部S16，因此并不会增加工艺步骤。
参照图10，在一些实施例中，第i行第j列的像素单元100中的蓝色子像素B的发光器件D的阳极D1(B)与该像素单元100的第二遮光部S12，以及位于第i行第j+1列的像素单元100中的第一遮光部S11和第三遮光部S13为一体结构。第i行第j列的像素单元100中的绿色子像素G的发光器件D的阳极D1(B)与该像素单元100的第四遮光部S14和第六遮光部S16，以及位于第i行第j+1列的像素单元100中的第五遮光部S15为一体结构；i取1至N，N为每一列中像素单元100的个数；j取1至M，M为每一行中像素单元100的个数。通过第一遮光图案与双栅晶体管两段沟道区之间的有源半导体层形成电容，第一遮光图案可以连接至第一电极D1以获得恒定电压，因此处于浮置状态的有源半导体层的电压可以保持稳定，防止两个栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
例如，在上述发光器件D的第一电极D1所在层上形成像素限定层107在，像素限定层107中形成有开口；像素限定层107的开口在基底101上的正投影位于相应的第一电极D1的基底101上的正投影内。
例如，像素限定层107的开口在基底101上的正投影位于相应的发光层D2在基底101上的正投影内，即发光层D2覆盖了像素限定层107的开口。例如，发光层D2的面积大于对应的像素限定层107开口的面积，即发光层D2除位于像素限定层107开口内部的部分，至少还包括覆盖像素限定层107的实体结构上的部分，通常在像素限定层107开口的各个边界处的像素限定 层107的实体结构上均覆盖发光层D2。需要说明的是，以上对于发光层D2图案的描述，是基于例如精细金属掩模(FMM)工艺形成的图案化的各个子像素10的有机发光层D2，除了FMM制作工艺，也有一些发光层D2是采用开口掩模(open mask)工艺在整个显示区形成整体的膜层，其形状在基底101上的正投影是连续的，所以必然有位于像素限定层107开口内的部分和位于像素限定层107实体结构上的部分。
例如，在形成每个发光器件D的发光层D2的基底101上，形成各发光器件D的第二电极D3，其中，若发光器件D的第一电极D1为阳极，那么第二电极D3则为阴极。对于阴极可以采用面状结构，也即呈阵列排布的多个发光器件D的阴极为一体结构。
以上为本公开实施例的显示基板中的第一遮光图案与发光器件D的第一电极D1同层设置时的结构说明。当然上述描述只是本公开实施例显示基板中的一些示例性结构，并不构成对本公开实施例中显示基板的保护范围的限制，应当理解的是，只要是在发光器件D的第一电极D1所在层同层设置第一遮光图案，以对各个像素电路中的第一复位晶体管T1和阈值补偿晶体管T2的沟道区进行遮挡，均在本公开实施例的保护范围内。
图11为本公开实施例的显示基板的源漏金属层的示意图，如图11所示，在本公开实施例中还提供一种显示基板，该显示基板与上述显示基板的结构大致相同，区别仅在于，该显示基板中的第一遮光图案位于源漏金属层，也即该显示基板的源漏金属层中不仅包括上述的沿第二方向Y延伸的数据线Vd、沿第二方向Y延伸的第一电源信号线VDD1、第一连接部21、第二连接部22和第三连接部23，还包括第一遮光图案。
例如：第一遮光图案包括每个子像素10中的第七遮光部S17和第八遮光部S18。其中，第七遮光部S17在基底101上的正投影覆盖第一复位晶体管T1的沟道区在基底101上的正投影。
第八遮光部S18在基底101上正投影覆盖阈值补偿晶体管T2的沟道区在基底101上的正投影。
在一些实施例中，每个子像素10中的第七遮光部S17与该子像素10所连接的第一电源信号线VDD1为一体结构。在一些实施例中，由于第二连接部22的一端通过贯穿第二绝缘层105中的过孔406与复位电源信号线Init电连接，第二连接部22的另一端通过贯穿栅极绝缘层103、第一绝缘层104和第二绝缘层105中的过孔207与第二复位晶体管T7的源极电连接。每个子像素10中的第八遮光部则与其所在子像素10中的第二连接部22为一体结构；也就是说，将复位电源信号线Init上写入的复位电源信号Vinit作为第八遮光部S18的恒定电压信号。此时通过第一电源信号线VDD1和复位电源信号线Init分别为第七遮光部S17和第八遮光部S18提供恒定电压，因此处于浮置状态的有源半导体层的电压可以保持稳定，防止两个第一复位晶体管T1和阈值补偿晶体管T2的栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。
在此需要说明的是，之所以将每个子像素10中的第七遮光部S17与该子像素10所连接的第一电源信号线VDD1为一体结构是因为，在一些实施例中可以将沿第二方向Y延伸的数据线Vd、沿第二方向Y延伸的第一电源信号线VDD1交替设置，且连接同一列子像素10的数据线Vd和第一电源信号线VDD1位于各自子像素10的同一侧(图4均设置在子像素10的右侧)，而第一电源信号线VDD1位于其所连接的子像素10和数据线之间，这样一来，将每个子像素10中的第七遮光部S17与该子像素10所连接的第一电源信号线VDD1为一体结构，避免了第七遮光部S17与数据线之间出现短路的问题。
对于该种结构的显示基板的其他结构可以与上述显示基板的结构相同，故在此不再详细描述。
第二方面，本公开实施例还提供一种显示装置，包括上述显示基板。需要说明的是，本实施例提供的显示装置可以为：柔性可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域 的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
进一步地，显示装置还可以包括多种类型的显示装置，例如液晶显示装置，有机电致发光(OLED)显示装置，迷你二极管(Mini LED)显示装置，在此不做限定。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (16)

  1. 一种显示基板，其包括：
    基底；
    多个像素单元，沿第一方向排布成多行、沿第二方向排布成多列，并设置在所述基底上，且所述多个像素单元中的每个包括多个子像素；所述多个子像素中的每个包括像素电路；
    有源半导体层，其包括各所述像素电路中的各晶体管的沟道区和源漏掺杂区，所述像素电路至少包括驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一复位晶体管、发光器件；第一遮光图案，设置在所述有源半导体层背离所述基底的一侧，所述第一遮光图案在所述基底上的正投影覆盖所述第一复位晶体管和所述阈值补偿晶体管的沟道区在基底上的正投影。
  2. 根据权利要求1所述的显示基板，其中，各所述像素电路还包括第二复位晶体管、第一发光控制晶体管和第二发光控制晶体管；
    对于位于同一行的各所述子像素而言，各所述像素电路中的第一复位晶体管和第二复位晶体管大致位于沿第一方向延伸的直线上；各所述像素电路中的第一发光控制晶体管和第二发光控制晶体管大致位于沿第一方向延伸的直线上各所述像素电路中的阈值补偿晶体管和数据写入晶体管大致位于沿第一方向延伸的直线上；
    对于位于同一列的各所述子像素而言，各像素电路中的第二复位晶体管、第二发光控制晶体管和阈值补偿晶体管大致位于沿第二方向延伸的直线上；各像素电路中的第一复位晶体管、第一发光控制晶体管和数据写入晶体管大致位于沿第二方向延伸的直线上。
  3. 根据权利要求1或2所述的显示基板，其中，所述驱动晶体管的控制极包括沿第二方向相对设置的第一侧和第二侧；对于每个所述子像素的像素电路而言，所述第一复位晶体管、第二复位晶体管、第一发光控制晶体管和第二发光控制晶体管位于所述第一侧；所述阈值补偿晶体管和所述数据写 入晶体管位于所述第二侧。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，各所述像素电路中的发光器件包括位于各所述像素电路中的晶体管背离基底一侧，依次设置的第一电极、发光层、第二电极；所述第一遮光图案与所述发光器件的第一电极同层设置且材料相同。
  5. 根据权利要求4所述的显示基板，其中，各所述像素单元中的多个子像素包括第一颜色子像素、第二颜色子像素、第三颜色子像素；所述第一遮光图案包括每个子像素中的第一遮光部、第二遮光部、第三遮光部、第四遮光部、第五遮光部、第六遮光部；
    所述第一遮光部在所述基底上的正投影覆盖第一颜色子像素中的第一复位晶体管的沟道区在所述基底上的正投影；所述第二遮光部在所述基底上的正投影覆盖第一颜色子像素中的阈值补偿晶体管的沟道区在所述基底上的正投影；所述第三遮光部在所述基底上的正投影覆盖第二颜色子像素中的第一复位晶体管的沟道区在所述基底上的正投影；所述第四遮光部在所述基底上的正投影覆盖所述第二颜色子像素中的阈值补偿晶体管的沟道区在所述基底上的正投影；所述第五遮光部在所述基底上的正投影覆盖第三颜色子像素中的第一复位晶体管的沟道区在所述基底上的正投影；所述第六遮光部在所述基底上的正投影覆盖第三颜色子像素中的阈值补偿晶体管的沟道区在所述基底上的正投影。
  6. 根据权利要求5所述的显示基板，其中，对于位于同一列的所述像素单元，各所述第二颜色子像素的像素电路中的发光器件的第一电极大致位于沿第二方向延伸的直线上；各所述第一颜色子像素和第二颜色子像素的像素电路中的发光器件的第一电极大致位于沿第二方向延伸的直线上；
    位于第i行第j列的所述像素单元中的第三颜色子像素的发光器件的第一电极与该像素单元的第二遮光部，以及位于第i行第j+1列的所述像素单元中的第一遮光部和第三遮光部为一体结构；
    位于第i行第j列的所述像素单元中的第二颜色子像素的发光器件的第 一电极与该像素单元的第四遮光部和第六遮光部，以及位于第i行第j+1列的所述像素单元中的第五遮光部为一体结构；其中，i取1至N，N为每一列中所述像素单元的个数；j取1至M，M为每一行中所述像素单元的个数。
  7. 根据权利要求1-6中任一项所述的显示基板，其中，还包括：
    栅极绝缘层，设置在所述有源半导体层背离所述基底的一侧；
    第一导电层，设置在所述栅极绝缘层背离所述有源半导体层的一侧；所述第一导电层包括所述存储电容的第二极板、沿所述第一方向延伸的扫描信号线、沿所述第一方向延伸的复位控制信号线、沿所述第一方向延伸的发光控制信号线以及所述驱动晶体管、所述数据写入晶体管、所述阈值补偿晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、所述第一复位晶体管和所述第二复位晶体管的控制极，所述驱动晶体管的控制极复用为所述存储电容的第二极；
    第一绝缘层，设置在所述第一导电层背离所述栅极绝缘层的一侧；
    第二导电层，设置在第一绝缘层背离所述第一导电层的一侧；所述第二导电层包括沿所述第一方向延伸的复位电源信号线以及所述存储电容的第一极板；
    第二绝缘层，设置在所述第二导电层背离所述第一绝缘层的一侧；
    源漏金属层，设置在所述第二绝缘层背离所述第二导电层的一侧；所述源漏金属层包括沿所述第二方向延伸的电源信号线、沿所述第二方向延伸的数据线、第一连接部、第二连接部以及第三连接部；
    平坦层，设置在设置在所述源漏金属层和所述发光器件的第一电极之间；
    所述第一连接部被配置为连接所述阈值补偿晶体管的第二极和所述驱动晶体管的控制极，所述第二连接部被配置为连接复位电源信号线和所述第二复位晶体管的第一极，所述第三连接部被配置为连接所述发光器件的第一电极与所述第二发光控制晶体管的第二极；
    所述第三连接部包括第一部分和第二部分，所述第三连接部的第一部分 通过贯穿所述栅极绝缘层、所述第一绝缘层和所述第二绝缘层中的过孔与所述第二发光控制晶体管的第二极电连接，所述第三连接部的第二部分通过贯穿所述平坦层的过孔与所述发光器件的第一电极电连接。
  8. 根据权利要求7所述的显示基板，其中，所述第二导电层还包括各所述子像素中设置的第二遮光图案；各所述子像素中的第二遮光图案在所述基底上正投影覆盖该所述子像素中的像素电路的阈值补偿晶体管的沟道区在所述基底上正投影，且所述第二遮光图案与第一电源信号线电连接。
  9. 根据权利要求8所述的显示基板，其中，每个所述第二遮光图案所连接的所述第一电源信号线为多条第一电源信号线中与之在第一方向上距离最近的一条。
  10. 根据权利要求1-3中任一项所述的显示基板，其中，还包括：
    栅极绝缘层，设置在所述有源半导体层背离所述基底的一侧；
    第一导电层，设置在所述栅极绝缘层背离所述有源半导体层的一侧；所述第一导电层包括所述存储电容的第二极板、沿所述第一方向延伸的扫描信号线、沿所述第一方向延伸的复位控制信号线、沿所述第一方向延伸的发光控制信号线以及所述驱动晶体管、所述数据写入晶体管、所述阈值补偿晶体管、所述第一发光控制晶体管、所述第二发光控制晶体管、所述第一复位晶体管和所述第二复位晶体管的控制极，所述驱动晶体管的控制极复用为所述存储电容的第二极；
    第一绝缘层，设置在所述第一导电层背离所述栅极绝缘层的一侧；
    第二导电层，设置在第一绝缘层背离所述第一导电层的一侧；所述第二导电层包括沿所述第一方向延伸的复位电源信号线以及所述存储电容的第一极板；
    第二绝缘层，设置在所述第二导电层背离所述第一绝缘层的一侧；
    源漏金属层，设置在所述第二绝缘层背离所述第二导电层的一侧；所述源漏金属层包括沿所述第二方向延伸的电源信号线、沿所述第二方向延伸的数据线以及所述第一遮光图案。
  11. 根据权利要求10所述的显示基板，其中，所述第一遮光图案包括每个子像素中的第七遮光部和第八遮光部；所述第七遮光部在所述基底上的正投影覆盖其所在所述子像素中的像素电路的第一复位晶体管的沟道区在基底上的正投影；所述第七遮光部在所述基底上的正投影覆盖其所在所述子像素中的像素电路的阈值补偿晶体管的沟道区在基底上的正投影；
    所述七遮光部与其所在所述子像素所连接的所述电源信号线为一体结构。
  12. 根据权利要求10或11所述的显示基板，其中，还包括：
    平坦层，设置在所述源漏金属层和所述发光器件的第一电极之间；
    所述源漏金属层还包括：第一连接部、第二连接部以及第三连接部；
    所述第一连接部被配置为连接所述阈值补偿晶体管的第二极和所述驱动晶体管的控制极，所述第二连接部被配置为连接所述复位电源信号线和所述第二复位晶体管的第一极，所述第三连接部被配置为连接所述发光器件的第一电极与所述第二发光控制晶体管的第二极；
    所述第三连接部包括第一部分和第二部分，所述第三连接部的第一部分通过贯穿所述栅极绝缘层、所述第一绝缘层和所述第二绝缘层中的过孔与所述第二发光控制晶体管的第二极电连接，所述第三连接部的第二部分通过贯穿所述平坦层的过孔与所述发光器件的第一电极电连接；
    所述第八遮光部与所述第二连接部为一体结构。
  13. 根据权利要求10-12中任一项所述的显示基板，其中，所述第二导电层还包括各所述子像素中设置的第二遮光图案；各所述子像素中的第二遮光图案在所述基底上正投影覆盖该所述子像素中的像素电路的阈值补偿晶体管的沟道区在所述基底上正投影，且所述第二遮光图案与第一电源信号线电连接。
  14. 根据权利要求13所述的显示基板，其中，每个所述第二遮光图案所连接的所述第一电源信号线为多条第一电源信号线中与之在第一方向上距离最近的一条。
  15. 根据权利要求1-14中任一项所述的显示基板，其中，所述第一复位晶体管和所述阈值补偿晶体管均为双栅晶体管。
  16. 一种显示装置，其包括权利要求1-15中任一项所述的显示基板。
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