WO2022082500A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2022082500A1
WO2022082500A1 PCT/CN2020/122455 CN2020122455W WO2022082500A1 WO 2022082500 A1 WO2022082500 A1 WO 2022082500A1 CN 2020122455 W CN2020122455 W CN 2020122455W WO 2022082500 A1 WO2022082500 A1 WO 2022082500A1
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Prior art keywords
transistor
electrode
reset
electrically connected
light
Prior art date
Application number
PCT/CN2020/122455
Other languages
English (en)
French (fr)
Inventor
和玉鹏
周洋
黄耀
张鑫
王予
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002399.0A priority Critical patent/CN114651332B/zh
Priority to PCT/CN2020/122455 priority patent/WO2022082500A1/zh
Priority to US17/599,654 priority patent/US20220320196A1/en
Publication of WO2022082500A1 publication Critical patent/WO2022082500A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage

Definitions

  • the invention belongs to the field of display, and in particular relates to a display substrate and a display device.
  • a circle of redundant pixel circuits is arranged around the display area of the display substrate to ensure the etching accuracy and uniformity of the pixel circuits in the display area.
  • the space occupied by the redundant pixel circuit is relatively large, so it is difficult to realize the narrow frame of the panel.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, which can reduce the space occupied by redundant pixel circuits in the peripheral area. Therefore, if the display substrate forms a display panel, it is beneficial to realize a display device. narrow borders.
  • embodiments of the present disclosure provide a display substrate having a display area and a peripheral area surrounding the display area, wherein the display substrate includes:
  • a plurality of pixel circuits located on the substrate and arranged in the display area;
  • the number of transistors in each of the redundant pixel circuits is smaller than the number of transistors in the pixel circuits.
  • the display substrate provided by the embodiments of the present disclosure, since the number of transistors in the redundant pixel circuit is smaller than the number of transistors in the pixel circuit, the space occupied by the redundant pixel circuit located in the peripheral area can be reduced, thereby facilitating the realization of the display device. Narrow borders.
  • the redundant pixel circuit includes a drive transistor, a first light emission control transistor, a second light emission control transistor, a first reset transistor, and a storage capacitor; wherein,
  • the driving transistor is arranged on the side of the storage capacitor close to the substrate;
  • the first reset transistor is disposed on the side of the connection between the first light-emitting control transistor and the second light-emitting control transistor away from the storage capacitor.
  • the display substrate further includes:
  • a plurality of reset power signal lines extending from the display area to the peripheral area along the first direction, and located on the side of the film layer where the scanning signal lines are located away from the substrate;
  • a plurality of reset control signal lines extending from the display area to the peripheral area along the first direction, and arranged in the same layer as the scanning signal lines;
  • a plurality of light-emitting control signal lines extend from the display area to the peripheral area along the first direction, and are arranged in the same layer as the scanning signal lines;
  • the first pole of the first reset transistor is electrically connected to the reset power signal line
  • the control electrode of the first reset transistor is electrically connected to the reset control signal line
  • the control electrode of the first light emission control transistor is electrically connected to the light emission control signal line.
  • the display substrate further includes:
  • a plurality of power signal lines extending from the display area to the peripheral area along a second direction, the plurality of power signal lines and the plurality of data lines are arranged in the same layer and alternately; the first direction and the second direction intersect ;
  • the first pole of the storage capacitor is electrically connected to the power signal line, and the second pole of the storage capacitor is electrically connected to the control pole of the driving transistor;
  • the first electrode of the first light emission control transistor is electrically connected to the power signal line.
  • the display substrate further includes a first electrode; the first electrode is disposed on a side of the data line away from the substrate; wherein,
  • the second electrode of the first reset transistor is electrically connected to the first electrode
  • the second electrode of the second light emission control transistor is electrically connected to the first electrode.
  • each of the redundant pixel circuits further includes a first connection part, a second connection part and a third connection part which are provided in the same layer as the data line; the first connection part, the first connection part and the third connection part The second connection portion and the third connection portion are arranged along the second direction;
  • the first connection portion is configured to connect the reset power supply signal line and the first electrode of the first reset transistor
  • the second connection portion is configured to connect the gate electrode of the drive transistor
  • the third The connection portion is configured to connect the first electrode and the second electrode of the second light emission control transistor.
  • the display substrate further includes: an active semiconductor layer disposed on the substrate; the active semiconductor layer includes an active layer of each transistor in the pixel circuit and the redundant pixel circuit.
  • the active layers of the transistors in each of the redundant pixel circuits are integrally disposed.
  • the display substrate further includes:
  • a first conductive layer located on the side of the active semiconductor layer away from the substrate;
  • a gate insulating layer located between the active semiconductor layer and the first conductive layer;
  • the first conductive layer includes a plurality of second poles of the storage capacitor, a plurality of scan signal lines extending along the first direction, a plurality of reset control signal lines extending along the first direction, a plurality of edge the light-emitting control signal line extending in the first direction;
  • the first conductive layer further includes a plurality of the first light-emitting control transistors, a plurality of the second light-emitting control transistors, and a plurality of the first reset transistors gate.
  • the display substrate further includes:
  • a second conductive layer located on the side of the first conductive layer away from the gate insulating layer;
  • the second conductive layer includes a plurality of reset power signal lines extending along the first direction and a plurality of first poles of the storage capacitor.
  • the display substrate further includes:
  • a source-drain metal layer located on the side of the second conductive layer away from the first insulating layer
  • a second insulating layer is located between the source-drain metal layer and the second conductive layer;
  • the source-drain metal layer includes a plurality of power signal lines extending along the second direction, a plurality of data lines extending along the second direction, a plurality of first connection parts, a plurality of second connection parts and a plurality of third connection parts .
  • the display substrate further includes: a gate array integrated driver disposed on at least one side of the peripheral region away from the display region, the gate array integrated driver passing through the first leads penetrating the peripheral region , which is connected to the pixel circuit in the display area.
  • each of the pixel circuits includes a first light emission control transistor, a second light emission control transistor, a drive transistor, a data write transistor, a storage capacitor, a threshold compensation transistor, a first reset transistor, and a second reset transistor;
  • the first pole of the data writing transistor is electrically connected to the first pole of the driving transistor
  • the second pole of the data writing transistor is electrically connected to the data line to receive a data signal
  • the control of the data writing transistor The pole is electrically connected with the scanning signal line to receive the scanning signal
  • the first pole of the storage capacitor is electrically connected to the power signal line, and the second pole of the storage capacitor is electrically connected to the control pole of the driving transistor;
  • the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the threshold compensation transistor is electrically connected to the control electrode of the driving transistor, and the control electrode of the threshold compensation transistor is electrically connected to the control electrode of the driving transistor.
  • the scan signal lines are electrically connected to receive compensation control signals;
  • the first pole of the first reset transistor is electrically connected to the reset power supply signal line to receive the first reset signal
  • the second pole of the first reset transistor is electrically connected to the light emitting device
  • the control pole of the second reset transistor is electrically connected to the light emitting device.
  • the reset control signal line is electrically connected to receive the first reset control signal;
  • the first pole of the second reset transistor is electrically connected to a reset power signal line to receive a second reset signal
  • the second pole of the second reset transistor is electrically connected to the control pole of the driving transistor
  • the first reset the control electrode of the transistor is electrically connected with the reset control signal line to receive the second reset control signal
  • the first electrode of the first light-emitting control transistor is electrically connected to the power signal line
  • the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor
  • the first light-emitting control transistor is The control electrode is electrically connected to the light-emitting control signal line to receive the first light-emitting control signal
  • the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the second light-emitting control transistor is electrically connected to the light-emitting device, and the second electrode of the second light-emitting control transistor is electrically connected to the light-emitting device.
  • the control electrode is electrically connected with the light-emitting control signal line to receive the second light-emitting control signal.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic plan structure diagram of an embodiment of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2A is a circuit layout diagram of an arrangement of pixel circuits in a display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 2B is an equivalent circuit diagram of a pixel circuit in a display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 2C is a circuit layout diagram of a single pixel circuit in a display area of a display substrate according to an embodiment of the present disclosure.
  • 3A is a circuit layout diagram of redundant pixel circuit arrangement in a peripheral region of a display substrate according to an embodiment of the present disclosure.
  • FIG. 3B is a circuit layout diagram of a single redundant pixel circuit in a peripheral area of a display substrate according to an embodiment of the present disclosure.
  • 3C is a circuit diagram of a redundant pixel circuit in a display area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4A is an example of a layer structure diagram of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4B is a plan structure diagram of an active semiconductor layer of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4C is a plan structure diagram of a first conductive layer of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4D is a schematic diagram of a stacked structure of an active semiconductor layer and a first conductive layer of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4E is a plan structure diagram of a second conductive layer of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4F is a plan structure diagram of a source-drain metal layer of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4G is a schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4H is a plan structure diagram of a first electrode of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • 4I is a schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, a source-drain metal layer, and a first electrode of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is another embodiment of a layer structure diagram of a redundant pixel circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 6 is an embodiment of a layer structure diagram of a pixel circuit in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of positions of GOA, redundant pixel circuits, and pixel circuits in a display substrate provided by an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain electrodes of the used transistors are interchangeable under certain conditions, the source, The drain is indistinguishable from the description of the connection relationship. In the embodiment of the present invention, in order to distinguish the source electrode and the drain electrode of the transistor, one electrode is called the first electrode, the other electrode is called the second electrode, and the gate electrode is called the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, the transistors are described as P-type transistors.
  • the first pole is the source of the P-type transistor
  • the second pole is the drain of the P-type transistor
  • the gate is input with a low level, the source and drain are turned on, and the N-type is opposite. It is conceivable that the use of transistors as N-type transistors can be easily conceived by those skilled in the art without creative efforts, and thus also falls within the protection scope of the embodiments of the present invention.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polysilicon thin film transistors, etc. .
  • the source and drain of the transistor may be symmetrical in structure, so the source and drain of the transistor may be indistinguishable in physical structure.
  • one of the gate electrodes is directly described as the first electrode and the other electrode is the second electrode.
  • the first and second poles are interchangeable as required
  • first direction and the second direction in the following can be any direction, and the first direction and the second direction intersect, for example, the first direction can be the extension direction (such as the row direction) of the first side of the display substrate,
  • the second direction may be the extension direction (eg, the column direction) of the second side of the display substrate adjacent to the first side.
  • the first direction is hereinafter referred to as the row direction (X direction) parallel to the lower side of the display substrate.
  • the second direction is the column direction (Y direction) parallel to the right side of the display substrate
  • first direction and the second direction are perpendicular or approximately perpendicular to each other.
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
  • the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
  • an embodiment of the present disclosure provides a display substrate having a display area S1 and a peripheral area S2 surrounding the display area S1 .
  • the display panel includes a substrate 1, the display area S1 of the substrate 1 includes a plurality of pixel units, the pixel units include a plurality of sub-pixels, each sub-pixel includes a light-emitting device and a pixel circuit, and the pixel circuit is arranged on the side of the light-emitting device close to the substrate, that is, A plurality of pixel circuits 2 are arranged on the substrate 1, and the pixel circuits 2 are arranged in the display area S1.
  • the pixel circuit 2 In the process of fabricating the pixel circuit 2, since the film structure of the display area S1 of the substrate 1 and other areas outside the display area S1 are quite different, the pixel circuit 2 near the junction of the display area S1 and other areas has a large difference in film structure. Graphics are affected, which in turn affects the accuracy and uniformity of the pixel circuitry.
  • the pattern of the pixel circuit 2 is etched by a photolithography process, the path of reflection and diffraction of light at the pixel circuit 2 in the display area S1 is different from the path of reflection and diffraction of light at other areas outside the display area S1 Therefore, the pattern of the pixel circuit 2 near the junction of the display area S1 and other areas will cause etching errors (such as insufficient etching or excessive etching) due to the difference in the reflection and diffraction paths of light, which will cause the pixel circuit formed.
  • the difference between 2 and the pixel circuit 2 far from the junction is large, which in turn affects the uniformity of multiple pixel circuits 2 in the display area S1.
  • the display substrate also includes a plurality of redundant pixel circuits 3, redundant
  • the pixel circuit 3 is arranged on the substrate 1, and the redundant pixel circuit 3 is arranged in the peripheral area S2.
  • the arrangement of the redundant pixel circuit 3 is the same as that of the pixel circuit 2, and no light-emitting device is arranged on the redundant pixel circuit 3.
  • the pixel circuit 3 is only used as a transitional circuit structure, so that the film structure of the peripheral area of the display area S1 is roughly the same as that in the display area S1, so as to ensure the etching accuracy and uniformity of the pixel circuit 2 in the display area S1 .
  • the pixel circuit 2 includes multiple transistors and storage capacitors, the redundant pixel circuit 3 includes storage capacitors of multiple transistors, and the number of transistors in the redundant pixel circuit 3 is smaller than the number of transistors in the pixel circuit 2 .
  • the space occupied by the pixel circuit 3 can be redundant, so that the area of the peripheral region S2 can be reduced, which is conducive to realizing a narrower display device. Bordered.
  • peripheral area S2 is an area defined by the arrangement positions of the redundant pixel circuits 3 , that is, the peripheral area S2 is an area where a plurality of redundant pixel circuits 3 are arranged on the substrate 1 .
  • FIG. 2A is a circuit layout in which pixel circuits 2 are arranged on the substrate 1 in the display area S1.
  • a plurality of pixel circuits 2 are arranged on the substrate 1 and in the display area S1 along the first direction (ie, the X direction) and The second direction (ie, the Y direction) is repeatedly arranged, and each pixel circuit drives the light-emitting device for driving the sub-pixels in the pixel unit through a plurality of signal lines (described in detail later).
  • the pixel circuit 2 in the above-mentioned display area S1 may adopt various structures, for example, the pixel circuit 2 may include a structure of three transistors and one capacitor (3T1C), or a structure of seven transistors and one capacitor (7T1C), or a structure of 12 transistors The structure of one capacitor (12T1C), etc., taking the pixel circuit 2 including 7T1C as an example, specifically, the pixel circuit 2 includes a driving transistor T3, a data writing transistor T4, a storage capacitor Cstst, a threshold compensation transistor T2, and a first reset transistor. T7, a second reset transistor T1, a first light emission control transistor T5, and a second light emission control transistor T6.
  • FIG. 2B is a schematic circuit diagram of the pixel circuit 2 in the sub-pixel of the pixel unit in the display substrate provided by the embodiment of the present disclosure (the pixel circuit 2 includes 7T1C), and FIG. 2C is a single pixel in FIG. 2A.
  • the pixel circuit 2 includes a driving transistor T3, a data writing transistor T4, a storage capacitor Cst, a threshold compensation transistor T2, a first reset transistor T7, a second reset transistor T1, a first light-emitting control transistor T5, and a first reset transistor T5. Two light-emitting control transistors T6.
  • Each sub-pixel of the pixel unit further includes a light-emitting device (not shown in the figure), and the light-emitting device includes a first electrode, a light-emitting layer and a second electrode that are sequentially arranged on the substrate 1 .
  • the first electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3, and the second electrode of the data writing transistor T4 is configured to be electrically connected to the data line Data to receive the data signal
  • the control electrode of the data writing transistor T4 is configured to be electrically connected to the first scan signal line Scan1 to receive the scan signal
  • the first electrode of the storage capacitor Cst is electrically connected to the first power supply terminal ELVDD
  • the second electrode of the storage capacitor Cst is electrically connected to the first power supply terminal ELVDD.
  • the gate of the drive transistor T3 is electrically connected; the first pole of the threshold compensation transistor T2 is electrically connected to the second pole of the drive transistor T3, the second pole of the threshold compensation transistor T2 is electrically connected to the control pole of the drive transistor T3, and the threshold compensation transistor T2
  • the control electrode of the second reset transistor T1 is configured to be electrically connected to the second scan signal line Scan2 to receive the compensation control signal; the first electrode of the second reset transistor T1 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal.
  • the second electrodes of the two reset transistors T1 are electrically connected to the control electrodes of the driving transistors T3, and the control electrodes of the second reset transistors T1 are configured to be electrically connected to the first reset control signal line Rst1 to receive the first reset control signal;
  • the first reset The first electrode of the transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive a second reset signal, the second electrode of the first reset transistor T7 is electrically connected to the first electrode of the light emitting device OLED, and the first reset transistor T7
  • the control electrode is configured to be electrically connected to the second reset control signal line Rst2 to receive the second reset control signal;
  • the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power supply terminal ELVDD, and the first light-emitting control transistor T5 is electrically connected to the first power terminal ELVDD.
  • the second electrode is electrically connected to the first electrode of the driving transistor T3, and the control electrode of the first light-emitting control transistor T5 is configured to be electrically connected to the first light-emitting control signal line EM1 to receive the first light-emitting control signal; the second light-emitting control transistor T6
  • the first electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, the second electrode of the second light-emitting control transistor T5 is electrically connected to the first electrode of the light-emitting device OLED, and the control electrode of the second light-emitting control transistor T5 is configured to be connected with the first electrode of the second light-emitting control transistor T5.
  • the two light-emitting control signal lines EM2 are electrically connected to receive the second light-emitting control signal; the second electrode of the light-emitting device OLED is electrically connected to the second power supply terminal ELVSS.
  • one of the first power supply terminal ELVDD and the second power supply terminal ELVSS is a high voltage terminal, and the other is a low voltage terminal.
  • the first power supply terminal ELVDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power supply terminal ELVSS can be a voltage source to output a constant first voltage
  • the second voltage is a negative voltage, etc.
  • the second power supply terminal ELVSS may be grounded.
  • the scan signal and the compensation control signal may be the same, that is, the control electrode of the data writing transistor T4 and the control electrode of the threshold compensation transistor T2 may be electrically connected to the same signal line, for example, both are electrically connected to the first
  • the scanning signal line Scan1 is used to receive the same signal (eg, scanning signal).
  • the display substrate may not be provided with the second scanning signal line Scan2 to reduce the number of signal lines.
  • control electrode of the data writing transistor T4 and the control electrode of the threshold compensation transistor T2 may also be electrically connected to different signal lines respectively, that is, the control electrode of the data writing transistor T4 is electrically connected to the first scan signal line Scan1, and the threshold The control electrode of the compensation transistor T2 is electrically connected to the second scan signal line Scan2, and the signals transmitted by the first scan signal line Scan1 and the second scan signal line Scan2 are the same.
  • the scanning signal and the compensation control signal may also be different, so that the gate electrode of the data writing transistor T4 and the threshold compensation transistor T2 can be controlled separately and independently, thereby increasing the flexibility of controlling the pixel circuit.
  • the first light-emitting control signal and the second light-emitting control signal may be the same, that is, the control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T5 may be electrically connected to the same signal Lines, such as the first light-emitting control signal line EM1, receive the same signal (for example, the first light-emitting control signal).
  • the display substrate may not set the second light-emitting control signal line EM2 to reduce the number of signal lines.
  • control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T5 may also be electrically connected to different signal lines respectively, that is, the control electrode of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control transistor T5.
  • control signal line EM1 the control electrode of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2
  • the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 transmit the same signal.
  • first light-emitting control transistor T5 and the second light-emitting control transistor T5 are different types of transistors, for example, the first light-emitting control transistor T5 is a P-type transistor and the second light-emitting control transistor T5 is an N-type transistor
  • the first lighting control signal and the second lighting control signal may also be different, which is not limited by the embodiment of the present disclosure.
  • the first reset control signal and the second reset control signal may be the same, that is, the control electrode of the second reset transistor T1 and the control electrode of the first reset transistor T7 may be electrically connected to the same signal line, for example, the first reset control signal
  • the line Rst1 is used to receive the same signal (for example, the first sub-reset control signal).
  • the second reset control signal line Rst2 may not be provided on the display substrate to reduce the number of signal lines.
  • the control electrode of the second reset transistor T1 and the control electrode of the first reset transistor T7 may also be electrically connected to different signal lines respectively, that is, the control electrode of the second reset transistor T1 is electrically connected to the first reset control signal line Rst1.
  • the control electrode of the first reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the first reset control signal line Rst1 and the second reset control signal line Rst2 transmit the same signal. It should be noted that the first reset control signal and the second reset control signal may also be different.
  • the second reset control signal may be the same as the scan signal, that is, the control electrode of the first reset transistor T7 may be electrically connected to the scan signal line Scan to receive the scan signal as the second reset control signal.
  • the second pole of the second reset transistor T1 and the second pole of the first reset transistor T7 are respectively connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2, the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be a DC reference voltage terminal to output a constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same, for example, the source of the second reset transistor T1 and the source of the first reset transistor T7 are connected to the same reset power terminal.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first reset signal and the second reset signal to control the control electrode of the driving transistor T3 and the light emitting device OLED.
  • the first electrode only needs to be reset, which is not limited in this embodiment of the present disclosure.
  • the second pole of the second reset transistor T1 and the second pole of the first reset transistor T7 may both be connected to the reset power signal line Init, and connected to the reset power terminal Vinit through the reset power signal line Init.
  • FIG. 3A is a circuit layout of the redundant pixel circuit 3 arranged on the substrate 1 in FIG. 3A
  • FIG. 3B is a circuit layout of a single redundant pixel circuit 3 in FIG. 3A
  • FIG. 3C is an equivalent circuit schematic diagram of a single redundant pixel circuit 3 .
  • the redundant pixel circuit 3 is arranged in the peripheral area S2 around the display area S1. Taking FIG. 3B as the redundant pixel circuit 3 arranged at the rounded corner on the upper side, the redundant pixel circuit 3 in FIG. The upper part is cut off, and the number of transistors of the redundant pixel circuit 3 is less than that of the pixel circuit 2.
  • the redundant pixel circuit 3 may include a driving transistor T3, a first light-emitting control transistor T5, and a second light-emitting control transistor T6 , the first reset transistor T7 and the storage capacitor Cst, the drive transistor T3 is arranged on the side of the storage capacitor Cst close to the substrate 1, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are arranged on the first side of the storage capacitor Cst, such as Fig. In 3B, the first side is the lower side, and the first reset transistor T7 is disposed on the side of the connection line between the first light-emitting control transistor T5 and the second light-emitting control transistor T6 away from the storage capacitor Cst.
  • the upper side of the redundant pixel circuit 3 also retains part of the gate structure of the threshold compensation transistor T2 (shown as T2' in the figure), and the data writing transistor T4
  • the gate table structure shown as T4' in the figure, so T2 and T4 are not turned on, and T2 and T4 can also be completely cut off.
  • the specific redundant pixel circuit 3 needs to be set at the location.
  • the redundant pixel circuit 3 includes part of the circuit structure of the pixel circuit 2, so the redundant pixel circuit 3 occupies a smaller space than the pixel circuit 2, so that the area of the peripheral area S2 can be reduced, Further, it is beneficial to realize the narrowing of the frame of the display device. And because the redundant pixel circuit 3 has the circuit structure of the pixel circuit 2, the redundant pixel circuit 3 can reduce the difference between the display area S1 (the area where the pixel circuit 2 is located) and the area other than the display area S1, so as to ensure the pixel Uniformity of circuit 3. As shown in FIG.
  • the redundant pixel circuit 3 since the redundant pixel circuit 3 only retains the driving transistor T3, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the first reset transistor T7 and the storage capacitor Cst in the pixel circuit 2, the light-emitting control The transistor T5, the second light-emitting control transistor T6 and the data writing transistor T4 are disconnected, and the second electrode of the storage capacitor Cst and the control electrode of the driving transistor T3 are disconnected from the threshold compensation transistor T2.
  • the first pole of the storage capacitor Cst is electrically connected to the first power supply terminal ELVDD, and the second pole of the storage capacitor Cst is electrically connected to the control pole of the driving transistor T3; the first pole of the first reset transistor T7 is configured to be connected to the second
  • the reset power supply terminal Vinit2 is electrically connected to receive the second reset signal, and the control electrode of the first reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second reset control signal;
  • One pole is electrically connected to the first power supply terminal ELVDD, the second pole of the first light emitting control transistor T5 is electrically connected to the first pole of the driving transistor T3, and the control pole of the first light emitting control transistor T5 is configured to be connected to the first light emitting control signal
  • the structure of the redundant pixel circuit 3 can be changed according to the position to be set, that is, the structure of the redundant pixel circuit 3 can be changed according to the need.
  • the lower half of the pixel circuit 3 can also be cut off (eg, the structure of cutting off the light-emitting control transistor T5, the second light-emitting control transistor T6 and the first reset transistor T7), which is not limited here.
  • FIG. 4A is a schematic diagram of the layer structure of the redundant pixel circuit 3 in the peripheral area S2 of the display substrate provided by the embodiment of the present disclosure.
  • the display substrate provided by the embodiment of the present disclosure further includes: The source semiconductor layer 20, the first conductive layer 30 disposed on the side of the active semiconductor layer 20 away from the substrate 1, the gate insulating layer 21 disposed between the active semiconductor layer 20 and the first conductive layer 30, disposed on the first.
  • the second conductive layer 40 on the side of the conductive layer 30 away from the gate insulating layer 21 is disposed between the second conductive layer 40 and the first conductive layer 30.
  • the first insulating layer 31 is disposed on the second conductive layer 40 away from the first conductive layer 30.
  • the source-drain metal layer 50 on one side of the insulating layer 31 is disposed on the second insulating layer 41 between the source-drain metal layer 50 and the second conductive layer 40 .
  • the display substrate may also include a flat layer 51 disposed on the side of the source-drain metal layer 50 away from the substrate 1, and a first electrode 601 disposed on the side of the flat layer 51 away from the substrate, and the first electrode 601 is the pixel unit in the display area S1. Electrodes of light-emitting devices in sub-pixels.
  • FIG. 6 is a schematic diagram of the layer structure of the pixel circuit 2 in the display area S1 of the display substrate according to the embodiment of the present disclosure. Between the first electrode 601 and the substrate 1 , the layer structure and redundancy of the pixel circuit 2 are The layer structure of the pixel circuit is roughly the same.
  • the redundant pixel circuit 3 only has a partial structure of the pixel circuit 2 (only has the driving transistor T3, the first light-emitting control transistor T5, the second light-emitting The structure of the control transistor T6 and the first reset transistor T7), a light-emitting device 60 is provided on the side of the pixel circuit 2 away from the substrate, and the light-emitting device 60 includes a first electrode 601 and a second electrode arranged in sequence on the side of the flat layer 51 away from the substrate 1 602 and the light-emitting layer 603, a pixel defining layer 70 is provided between adjacent light-emitting devices 60 to define different sub-pixels.
  • the pixel definition layer 70 has an opening 001, and the opening 001 is the light-emitting region of the light-emitting device 60. Since the redundant pixel circuit 3 does not drive the light-emitting device to emit light, no light-emitting device is provided on the redundant pixel circuit 3, and no opening is provided. In some embodiments, as shown in FIG. 4A , the first electrode 601 of the light emitting device 6 may be retained on the side of the flat layer 51 of the redundant pixel circuit 3 away from the substrate 1 . In other embodiments, as shown in FIG.
  • the first electrode 601 of the light-emitting device 6 may be disposed on the side of the flat layer 51 of the redundant pixel circuit 3 away from the substrate 1, and the pixel definition layer 70 may be disposed on the side of the first electrode 601 away from the substrate 1, but not in the pixel definition layer 70. Make openings.
  • the following description will be given by taking an example where the flat layer 51 of the redundant pixel circuit 3 only has the first electrode 601 on the side away from the substrate 1 .
  • FIG. 4B shows a schematic plan view of the active semiconductor layer 20 of the redundant pixel circuit 3 in the display substrate.
  • the active semiconductor layer 20 may be formed by patterning a semiconductor material.
  • the active semiconductor layer 20 can be used to form the active layers of the first light-emitting control transistor T5 , the second light-emitting control transistor T6 and the first reset transistor T7 of the pixel circuit 20 .
  • the active semiconductor layer 310 includes an active layer pattern (channel region) and a doping region pattern (source-drain doping region) of each transistor in each redundant pixel circuit 3 .
  • each transistor eg, the driving transistor T3, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 in the same redundant pixel circuit 3
  • the active layers are integrally arranged, that is, the active layers of the driving transistor T3, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 in the same redundant pixel circuit 3 are connected.
  • the active layer of the above-mentioned transistor may include a low temperature polysilicon layer formed integrally, and the source region and the drain region may be conductive by doping or the like to realize electrical connection of each structure. That is, the active semiconductor layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon, and each transistor in the same pixel circuit includes a pattern of doped regions (ie, source and drain regions) and an active layer. pattern, and the active layers of different transistors are separated by doping structures.
  • the active semiconductor layer 20 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that, the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active layers in the redundant pixel circuits 3 arranged along the first direction (X direction) in the pixel unit have no connection relationship and are disconnected from each other.
  • the active layers in the redundant pixel circuits 3 arranged along the second direction (Y direction) may be integrally arranged, or may be disconnected from each other.
  • 4C-FIG. 4F further illustrate the scan signal line Scan (including the first scan signal line Scan1 and the second scan signal line Scan2), the reset control signal line Rst (including the first reset control signal line Rst1 and the second scan signal line Scan2), which are further included in the display substrate.
  • Two reset control signal lines Rst2) the reset power signal line Init of the reset power terminal Vinit (including the first reset power signal line Init1 of the first reset power terminal Vinit1 and the second reset power signal line Init2 of the second reset power terminal Vinit2) , a light-emitting control signal line EM (including a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2), a data line Data, a power supply signal line VDD and a sub-power supply signal line VDD'.
  • a plurality of scan signal lines Scan, a plurality of reset power signal lines Init, a plurality of reset control signal lines Rst, and a plurality of light emission control signal lines EM are located along the first direction (X direction).
  • the above-mentioned signal lines extends from the display area S1 to the peripheral area S2, that is to say, the above-mentioned signal lines are arranged through the display area S1 and the peripheral area S2, and in the display area S1, the above-mentioned signal lines are connected to the corresponding transistors and/or storage capacitors of the pixel circuit 2, In the peripheral area S2 , the above-mentioned signal lines are connected to the transistors and/or storage or capacitors corresponding to the redundant pixel circuits 3 .
  • the redundant pixel circuit 3 the same as the pixel circuit 2, the first electrode of the first reset transistor T7 and the reset power supply signal line Init are electrically connected to the reset power supply terminal Vinit, and the control electrode of the first reset transistor T7 is connected to the reset control signal line.
  • Rst is electrically connected, and the control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM.
  • a plurality of data lines Data and a plurality of power signal lines VDD extend from the display area S1 to the peripheral area S2 along the second direction. That is to say, the above-mentioned signal lines are arranged through the display area S1 and the peripheral area S2. In the display area S1, the above-mentioned signal lines are connected to the transistors and/or storage capacitors corresponding to the pixel circuit 2, and in the peripheral area S2, the above-mentioned signal lines are connected to the redundant The transistor and/storage or capacitor corresponding to the pixel circuit 3.
  • the sub power signal line VDD' is connected to the power signal line VDD.
  • the transistors in the redundant pixel circuit 3 and the pixel circuit 2 are connected to the reset power supply terminal Vinit through the reset power supply signal line Init.
  • the first pole of the storage capacitor Cst and the power supply signal line VDD are electrically connected to the first power supply terminal ELVDD, and the second pole of the storage capacitor Cst is connected to the drive
  • the control electrode of the transistor T3 is connected to the first electrode of the first light-emitting control transistor T5 and the power signal line VDD is electrically connected to the first power supply terminal ELVDD.
  • the redundant pixel circuit 3 further includes a first electrode 601 disposed on the side of the flat layer 51 away from the substrate 1.
  • the redundant pixel circuit 3 is connected with the pixel circuit 2 is the same, the second electrode of the first reset transistor T5 is electrically connected to the first electrode 601 , and the second electrode of the second light emission control transistor T6 is electrically connected to the first electrode 601 .
  • the first scan signal line Scan1 and the second scan signal line Scan2 are the same scan signal line Scan
  • the first reset power supply signal line Init1 and the second reset power supply signal Line Init2 is the same reset power signal line Init
  • the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same bit control signal line Rst
  • the first light emission control signal line EM1 and the second light emission control signal line EM2 It is the same light-emitting control signal line EM, but not limited to this.
  • the first light-emitting control signal and the second light-emitting control signal in the redundant pixel circuit 3 may be the same, that is, the control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T5 may be electrically connected.
  • control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T5 may also be electrically connected to different signal lines respectively, that is, the control electrode of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control transistor T5.
  • control signal line EM1 the control electrode of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2
  • the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 transmit the same signal.
  • first light-emitting control transistor T5 and the second light-emitting control transistor T5 are different types of transistors, for example, the first light-emitting control transistor T5 is a P-type transistor and the second light-emitting control transistor T5 is an N-type transistor
  • the first lighting control signal and the second lighting control signal may also be different, which is not limited by the embodiment of the present disclosure.
  • FIG. 4 shows a schematic plan view of the first conductive layer 30 .
  • the first conductive layer 30 is disposed on the side of the active semiconductor layer 20 away from the substrate 1, and there is a gate insulating layer 21 between the first conductive layer 30 and the active semiconductor layer 20, so that the first conductive layer 30 is connected to the active semiconductor layer 20.
  • Layer 20 is insulating.
  • the first conductive layer 30 may include the second pole CC2 of the storage capacitor Cst, a scan signal line Scan, a reset control signal line Rst, and an emission control signal line EM, that is, a plurality of scan signal lines Scan and a plurality of reset control signal lines.
  • the first conductive layer 30 further includes a first light emitting control transistor T5, a second light emitting control transistor T6, a first reset transistor T7 and the control electrode (ie the gate electrode), for example, as shown in FIG. 4D, 4D is a schematic view of stacking the active semiconductor layer 20 shown in FIG. 4B and the first conductive layer 30 shown in FIG. 4C , and omitting the gate insulating layer 21 .
  • the control electrode G1 of the first light-emitting control transistor T5 may be the portion where the light-emitting control signal line EM and the active semiconductor layer 20 overlap
  • the control electrode G2 of the second light-emitting control transistor T6 may be the light-emitting control signal line EM and the active semiconductor layer. 20 overlapped part
  • the control electrode G3 of the first reset transistor T7 may be the part where the reset control signal line Rst overlaps with the active semiconductor layer 20
  • the control electrode G4 of the driving transistor T3 may be the second electrode CC2 of the storage capacitor Cst .
  • each dotted rectangle in FIG. 4B shows each portion where the first conductive layer 30 overlaps with the active semiconductor layer 20 .
  • the active semiconductor layers on both sides of each channel region are conductorized by processes such as ion doping to form the first and second electrodes of the respective transistors.
  • the scan signal line Scan, the reset control signal line Rst, and the light emission control signal line EM are arranged in the second direction (Y direction).
  • the scan signal line Scan is located between the reset control signal line Rst and the light emission control signal line EM.
  • the second pole CC2 ie, the lower pole plate of the storage capacitor Cst is located between the scan signal line Scan and the light emission control signal line EM.
  • FIG. 4E shows a schematic plan view of the second conductive layer 40 .
  • the second conductive layer 40 is disposed on the side of the first conductive layer 30 away from the substrate 1 , and there is a first insulating layer 31 between the first conductive layer 30 and the second conductive layer 40 , and the first insulating layer 31 makes the first conductive layer 30 It is insulated from the second conductive layer 40 .
  • the second conductive layer 40 includes the first pole CC1 of the storage capacitor Cst, the reset power supply signal line Init, the sub-power supply signal line VDD′, and the light shielding portion S. As shown in FIG.
  • the second pole CC2 located on the first conductive layer 30 and the first pole CC1 located on the second conductive layer 40 at least partially overlap in a direction perpendicular to the substrate 1 to form a storage capacitor Cst.
  • the sub-power signal line VDD' (shown by the dotted box in FIG. 4E ) and the first pole CC1 of the storage capacitor Cst can be integrally formed, so that the sub-power signal line VDD' extends along the first direction, and the sub-power signal line VDD' and the capacitor
  • the first pole CC1 of C connects a plurality of power supply signal lines VDD extending in the second direction (Y direction) to form a grid wiring to reduce resistance.
  • the threshold compensation transistor T2 in the pixel circuit 2 in the display area S2, the threshold compensation transistor T2 is in a floating state when it is turned off, and is easily affected by the surrounding line voltage and jumps, thus affecting the threshold compensation transistor T2 leakage current, which in turn affects the luminous brightness.
  • the light shielding part S is designed to form a capacitor with the active semiconductor layer between the two channels of the threshold compensation transistor T2, and the light shielding part S can be connected to the power supply
  • the signal line VDD obtains a constant voltage, so the voltage of the active semiconductor layer in the floating state can be kept stable.
  • the light-shielding portion S overlaps with the active semiconductor layer between the two channels of the threshold compensation transistor T2, which can also prevent the active semiconductor layer between the two gates from being illuminated to change the characteristics, such as preventing this part of the active semiconductor layer. voltage changes to prevent crosstalk.
  • the redundant pixel circuit 3 in the peripheral area S2 the redundant pixel circuit 3 does not include the threshold compensation transistor T2, but in the process of fabricating the second conductive layer 40, in order to ensure the uniformity of etching, in the redundant pixel circuit 3 It also has a light shielding part S in it.
  • the light shielding portion S is located on at least one side between the first electrode C11 of the storage electrode Cst and the reset power supply signal line Init.
  • FIG. 4F shows a schematic plan view of the source-drain metal layer 50 .
  • the source-drain metal layer 50 is disposed on the side of the second conductive layer 40 away from the substrate 1 , and there is a second insulating layer 41 between the second conductive layer 40 and the source-drain metal layer 50 , and the second insulating layer 41 makes the source-drain metal layer 50 It is insulated from the second conductive layer 40 .
  • the source-drain metal layer 50 includes a data line Data and a power signal line VDD.
  • the data line Data and the power signal line VDD both extend along the second direction (Y direction).
  • a plurality of data lines Data are arranged on the side of the reset power signal line Init away from the scanning signal line Scan, a plurality of power signal lines VDD and a plurality of data lines Data are arranged in the same layer, and in the first direction (X direction), the power supply The signal line VDD and the data line Data are alternately arranged.
  • the source-drain metal layer 50 further includes a first connection part A1 , a second connection part A2 and a third connection part A3 .
  • the first connection portion A1, the second connection portion A2 and the third connection portion A3 are repeatedly arranged in the source-drain metal layer 50 along the second direction (Y direction), and the second connection portion A2 is configured to connect the control of the driving transistor T3
  • the pole ie, the second pole CC2 of the storage capacitor Cst
  • the second connection part A2 is configured to connect the reset power signal line Init and the first pole of the first reset transistor T7
  • the third connection part A3 is configured to connect the first pole of the first reset transistor T7.
  • FIG. 4F also shows exemplary locations of a plurality of vias in the source-drain metal layer 50 passing through the illustrated plurality of vias and a plurality of vias located between the source-drain metal layer 50 and the substrate 1 .
  • Membrane connection As shown in FIG. 4F , the differently filled vias indicate that the source-drain metal layer 50 is connected to different film layers therethrough. For example, the vias filled in white indicate that the source-drain metal layer 50 is connected to the active semiconductor layer 20 shown in FIG. 4B through these vias, and the vias filled with slanted lines indicate that the source-drain metal layer 50 is connected to FIG. 4C through these vias In the first conductive layer 30 shown, the black filled vias indicate that the source-drain metal layer 50 is connected to the second conductive layer 40 shown in FIG. 4E through these vias.
  • FIG. 4G is the active semiconductor layer 20 shown in FIG. 4B
  • the first conductive layer 30 shown in FIG. 4C
  • 4F shows a schematic view of a stack of source-drain metal layers 50 stacked on top of each other (each insulating layer is omitted).
  • the data line Data passes through the via hole 06 penetrating the gate insulating layer 21, the first insulating layer 31 and the second insulating layer 41 and the second electrode of the data writing transistor T4 Electrically connected, in the redundant pixel circuit 3 in the peripheral area S2, although the redundant pixel circuit 3 does not have a data writing transistor T4, during the punching process, in order to improve the uniformity of punching in the pixel circuit 2 , a via hole 06 is also formed in the source-drain metal layer 50 of the redundant pixel circuit 3 .
  • the number and position of each via hole in the film layer of the redundant pixel circuit 3 are the same as the number and position of each via hole in the pixel circuit 2, but the redundant pixel circuit 3 only uses part of the via hole, the following It is mentioned in the description that the via holes electrically connecting the threshold compensation transistor T2, the second reset transistor T1, and the data writing transistor T4 are only used in the pixel circuit 2 in the display area S1, and exist in the redundant pixel circuit 3 but are not implemented. electrical connection.
  • the power signal line VDD is electrically connected to the first electrode of the first light emission control transistor T5 through the via hole 09 penetrating the gate insulating layer 21 , the first insulating layer 31 and the second insulating layer 41 .
  • the power signal line VDD and the data line Data are alternately arranged along the first direction.
  • the power signal line VDD is electrically connected to the sub power signal line VDD' (the first pole CC1 of the storage capacitor Cst) through the via hole 08 penetrating the second insulating layer 41, and the power signal line VDD extends along the second direction (Y direction).
  • the power supply signal line VDD' extends in the first direction (X direction), so that the power supply signal line VDD and the sub power supply signal line VDD' are wired in a grid on the base 1 of the display substrate.
  • the power signal line VDD and the sub-power signal line VDD' are arranged in a grid shape, so that the resistance of the signal line of the first power supply terminal ELVDD is small and the voltage drop is low. Further, the stability and uniformity of the power supply voltage provided by the first power supply terminal ELVDD can be improved.
  • the power signal line VDD is electrically connected to the light shielding portion S through the via hole 07 penetrating the second insulating layer 41 , so that the power signal line VDD can provide a constant voltage to the light shielding portion S.
  • One end of the first connection portion A1 is electrically connected to the reset power supply signal line Init through the via hole 05 in the second insulating layer 41 , and the other end of the first connection portion A1 is electrically connected through the gate insulating layer 21 , the first insulating layer 31 and the reset power supply signal line Init.
  • the via hole 04 in the second insulating layer 41 is electrically connected to the first electrode of the first reset transistor T7.
  • One end of the second connection part A2 is electrically connected to the second electrode of the threshold compensation transistor T2 through the via hole 02 penetrating the gate insulating layer 21 , the first insulating layer 31 and the second insulating layer 41 , and the other end of the second connection part A2 is electrically connected to the second electrode of the threshold compensation transistor T2
  • One end is electrically connected to the gate electrode of the driving transistor T3 through a via hole 01 penetrating through the first insulating layer 31 and the second insulating layer 41 .
  • One end of the third connection portion A3 is electrically connected to the second electrode of the second light emission control transistor T6 through the via hole 03 penetrating through the gate insulating layer 21 , the first insulating layer 31 and the second insulating layer 41 .
  • a flat layer 51 (for protecting the above-mentioned source/drain metal layer 50 is formed on the above-mentioned source/drain metal layer 50 .
  • the flat layer 50 includes a The hole 011, the first electrode 601 of the light-emitting element 6 of the sub-pixel in the pixel unit can be arranged on the side of the flat layer 50 away from the substrate 1, and the first electrode 601 of the light-emitting element 6 is connected to the third connection part A3 through the via hole 011 The other end is electrically connected to realize the connection between the second light-emitting control transistor T6 and the first electrode 601.
  • the position of the orthographic projection of the via hole 011 in the flat layer 51 on the source-drain metal layer 50 is located on the third connection portion A3 (FIG. 4F the position shown in the dashed box).
  • FIG. 4I is the active semiconductor layer 20 shown in FIG. 4B , the first conductive layer 30 shown in FIG. 4C , and the second conductive layer 40 shown in FIG. 4E . 4.
  • the source-drain metal layer 50 shown in FIG. 4F and the first electrode 406 shown in FIG. 4H are stacked together.
  • a first electrode 601 of the light-emitting device 6 is also disposed on the side of the source-drain metal layer 50 away from the substrate 1, wherein each pixel unit may include a plurality of sub-pixels, in the display area S1, each sub-pixel corresponds to a light-emitting device, and in the display area S1, each sub-pixel corresponds to a light-emitting device. In the peripheral area S2, each sub-pixel corresponds to a first electrode. For example, as shown in FIG.
  • each pixel unit includes a first-color sub-pixel, a second-color sub-pixel group and The third color sub-pixel, each second color sub-pixel group includes two second-color sub-pixels arranged along the second direction (Y direction), the light-emitting device of the first-color sub-pixel corresponds to the first-color first electrode 6011, The light emitting device of the sub-pixel of the second color corresponds to the first electrode 6012 of the second color, and the light emitting device of the sub-pixel of the third color corresponds to the first electrode 6013 of the third color.
  • the orthographic projection of each first color first electrode 6011 on the substrate 1 is located within the orthographic projection of the data line Data on the substrate 1 .
  • the orthographic projection of the second color first electrode 6012 on the substrate 1 overlaps with the orthographic projection of the data line Data and the first connection portion A1 on the substrate 1 .
  • the first electrode 6011 of the first color overlaps with the power signal line VDD, the data line Data and the third connection part A3, and the power signal line VDD and the third connection part A3 are located on both sides of the data line Data .
  • the second color first electrode 6012 overlaps with the data line Data, the power signal line VDD, the first connecting part A1 and the third connecting part A3, and the center of the second color first electrode 6012
  • the line overlaps with the third connection A3; in a direction perpendicular to its 1. along the direction perpendicular to the substrate 1.
  • the first electrode 6013 of the third color overlaps with the data line Data, the power signal line VDD, the second connection part A2, the first connection part A1 and the third connection part A3, and the data line Data is located on one side of the center line,
  • the second connecting portion A2 is located on the other side of the center line.
  • the redundant pixel circuit 3 is further provided with a pixel definition layer 70 on the first electrode 601 , the film layer shown in 4I can be fabricated on the side of the first electrode 601 away from the substrate 1 . Pixel definition layer 70 .
  • the display substrate further includes a Gate Drive on Array
  • the GOA is disposed on at least one side of the peripheral area S2 away from the display area S1, and the plurality of signal lines are formed by the GOA
  • the located area extends to the peripheral area S2 , and then extends from the peripheral area S2 to the display area S1 , connecting the pixel circuit 2 and the redundant pixel circuit 3 .
  • the signal lines may include a reset power signal line Init, an emission control signal line EM, a scan signal line Scan, a reset control signal line Rst, etc.
  • the reset power signal line Init may be electrically connected to the first pole of the first reset control transistor T1 and the first electrode of the second reset transistor T7
  • the light-emitting control signal line EM can be electrically connected to the control electrode of the first light-emitting control transistor T5 and the control electrode of the second light-emitting control transistor T6
  • the scan signal line Scan can be electrically connected to the threshold compensation transistor
  • the reset control signal line Rst may be electrically connected to the control electrode of the first reset transistor T7 and the control electrode of the second reset transistor T1.
  • a plurality of signal lines pass through the gaps between the adjacent redundant pixel circuits 3 in the peripheral area S2 and are connected to the pixel circuits 2 in the display area S1. Since the space occupied by the redundant pixel circuits 3 is reduced, the peripheral area S2 The density of the redundant pixel circuits 3 is reduced, so multiple signal lines can be led to the pixel circuits 2 through the gaps between the multiple redundant pixel circuits 3, and it can be avoided that the redundant pixel circuits 3 are too dense to cause multiple signal lines. A short circuit occurs between them.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display substrate.
  • the display device provided in this embodiment may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention.
  • the display device may also include various types of display devices, such as a liquid crystal display device, an organic electroluminescence (OLED) display device, and a mini diode (Mini LED) display device, which are not limited herein.
  • display devices such as a liquid crystal display device, an organic electroluminescence (OLED) display device, and a mini diode (Mini LED) display device, which are not limited herein.

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Abstract

本发明提供一种显示基板及显示装置，属于显示技术领域。本发明提供的一种显示基板，该显示基板具有显示区，和围绕显示区的周边区，该显示基板包括基底，多个像素电路，位于基底上，且设置在显示区中，多个冗余像素电路，位于基底上，且设置在周边区中；其中，每个冗余像素电路中晶体管的数量，小于像素电路中晶体管的数量。由于冗余像素电路中晶体管的数量小于像素电路中晶体管的数量，因此能够减小位于周边区的冗余像素电路所占空间，从而有利于实现显示装置的窄边框化。

Description

显示基板和显示装置 技术领域
本发明属于显示领域，具体涉及一种显示基板和显示装置。
背景技术
通常在制作显示基板的过程中，会在显示基板的显示区周围设置一圈冗余像素电路，以保证制作显示区内的像素电路的刻蚀准确性和均一性。但冗余像素电路所占据的空间较大，因此难以实现面板的窄边框化。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板，其能够减少周边区的冗余像素电路所占空间，因此若显示基板形成显示面板，有利于实现显示装置的窄边框化。
第一方面，本公开实施例提供一种显示基板，该显示基板具有显示区，和围绕所述显示区的周边区，其中，包括：
基底；
多个像素电路，位于所述基底上，且设置在所述显示区中；
多个冗余像素电路，位于所述基底上，且设置在所述周边区中；其中，
每个所述冗余像素电路中晶体管的数量，小于所述像素电路中晶体管的数量。
本公开实施例提供的显示基板，由于冗余像素电路中晶体管的数量小于像素电路中晶体管的数量，因此能够减小位于周边区的冗余像素电路所占的空间，从而有利于实现显示装置的窄边框化。
在一些示例中，所述冗余像素电路包括驱动晶体管、第一发光控制晶体 管、第二发光控制晶体管、第一复位晶体管和存储电容；其中，
所述驱动晶体管设置在所述存储电容靠近所述基底一侧；
所述第一复位晶体管设置在所述第一发光控制晶体管和所述第二发光控制晶体管之间的连线背离所述存储电容一侧。
在一些示例中，所述显示基板还包括：
多条扫描信号线，沿第一方向由显示区延伸至周边区，且设置在所述基底上；
多条复位电源信号线，沿第一方向由显示区延伸至周边区，且位于所述扫描信号线所在膜层背离所述基底一侧；
多条复位控制信号线，沿第一方向由显示区延伸至周边区，且与所述扫描信号线同层设置；
多条发光控制信号线，沿第一方向由显示区延伸至周边区，且与所述扫描信号线同层设置；其中，
所述第一复位晶体管的第一极与所述复位电源信号线电连接；
所述第一复位晶体管的控制极与所述复位控制信号线电连接；
所述第一发光控制晶体管的控制极与所述发光控制信号线电连接。
在一些示例中，所述显示基板还包括：
多条数据线，沿第二方向由显示区延伸至周边区，且设置在所述复位电源信号线背离所述扫描信号线一侧；
多条电源信号线，沿第二方向由显示区延伸至周边区，所述多条电源信号线与所述多条数据线同层且交替设置；所述第一方向和所述第二方向相交；其中
所述存储电容的第一极与所述电源信号线电连接，所述存储电容的第二极与所述驱动晶体管的控制极电连接；
所述第一发光控制晶体管的第一极与所述电源信号线电连接。
在一些示例中，所述显示基板还包括第一电极；所述第一电极设置在所述数据线背离所述基底一侧；其中，
所述第一复位晶体管的第二极与所述第一电极电连接；
所述第二发光控制晶体管的第二极与所述第一电极电连接。
在一些示例中，每个所述冗余像素电路中还包括与所述数据线同层设置的第一连接部、第二连接部和第三连接部；所述第一连接部、所述第二连接部和所述第三连接部沿所述第二方向排列；
所述第一连接部被配置为连接所述复位电源信号线和所述第一复位晶体管的第一极，所述第二连接部被配置为连接所述驱动晶体管的控制极，所述第三连接部被配置为连接所述第一电极与所述第二发光控制晶体管的第二极。
在一些示例中，所述显示基板还包括：有源半导体层，设置在所述基底上；所述有源半导体层包括所述像素电路和所述冗余像素电路中各晶体管的有源层。
在一些示例中，每个所述冗余像素电路中各晶体管的有源层一体设置。
在一些示例中，所述显示基板还包括：
第一导电层，位于所述有源半导体层远离所述基底的一侧；
栅极绝缘层，位于所述有源半导体层与所述第一导电层之间；其中，
所述第一导电层包括多个所述存储电容的第二极、多条沿所述第一方向延伸的扫描信号线、多条沿所述第一方向延伸的复位控制信号线、多条沿所述第一方向延伸的发光控制信号线；
所述周边区内，每个冗余像素电路中，所述第一导电层还包括多个所述第一发光控制晶体管、多个所述第二发光控制晶体管、多个所述第一复位晶体管的栅极。
在一些示例中，所述显示基板还包括：
第二导电层，位于所述第一导电层远离所述栅极绝缘层的一侧；
第一绝缘层，位于所述第二导电层与所述第一导电层之间；其中，
所述第二导电层包括多条沿所述第一方向延伸的复位电源信号线、多个所述存储电容的第一极。
在一些示例中，所述显示基板还包括：
源漏金属层，位于所述第二导电层远离所述第一绝缘层一侧；
第二绝缘层，位于所述源漏金属层与所述第二导电层之间；其中，
所述源漏金属层包括多条沿第二方向延伸的电源信号线、多条沿第二方向延伸的数据线、多个第一连接部、多个第二连接部以及多个第三连接部。
在一些示例中，显示基板还包括：栅极阵列集成驱动，设置在所述周边区的背离所述显示区的至少一侧，所述栅极阵列集成驱动通过贯穿所述周边区的第一引线，连接所述显示区中的像素电路。
在一些示例中，每个所述像素电路包括第一发光控制晶体管、第二发光控制晶体管、驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一复位晶体管和第二复位晶体管；
所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极与数据线电连接以接收数据信号，所述数据写入晶体管的控制极与扫描信号线电连接以接收扫描信号；
所述存储电容的第一极与电源信号线电连接，所述存储电容的第二极与所述驱动晶体管的控制极电连接；
所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的控制极电连接，所述阈值补偿晶体管的控制极与所述扫描信号线电连接以接收补偿控制信号；
所述第一复位晶体管的第一极与复位电源信号线电连接以接收第一复位信号，所述第一复位晶体管的第二极与发光器件电连接，所述第二复位晶 体管的控制极与所述复位控制信号线电连接以接收第一复位控制信号；
所述第二复位晶体管的第一极与复位电源信号线电连接以接收第二复位信号，所述第二复位晶体管的第二极与所述驱动晶体管的控制极电连接，所述第一复位晶体管的控制极与复位控制信号线电连接以接收第二复位控制信号；
所述第一发光控制晶体管的第一极与所述电源信号线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的控制极与所述发光控制信号线电连接以接收第一发光控制信号；
所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件电连接，所述第二发光控制晶体管的控制极与所述发光控制信号线电连接以接收第二发光控制信号。
第二方面，本公开实施例还提供一种显示装置，包括上述显示基板。
附图说明
图1为本公开实施例提供的显示基板的一种实施例的平面结构简图。
图2A为本公开实施例提供的显示基板的显示区中像素电路排列的电路版图。
图2B为本公开实施例提供的显示基板的显示区中像素电路的等效电路图。
图2C为本公开实施例提供的显示基板的显示区中单个像素电路的电路版图。
图3A为本公开实施例提供的显示基板的周边区中冗余像素电路排列的电路版图。
图3B为本公开实施例提供的显示基板的周边区中单个冗余像素电路的 电路版图。
图3C为本公开实施例提供的显示基板的显示区中冗余像素电路的电路图。
图4A为本公开实施例提供的显示基板中冗余像素电路的层结构图的一种实施例。
图4B为本公开实施例提供的显示基板中冗余像素电路的有源半导体层的平面结构图。
图4C为本公开实施例提供的显示基板中冗余像素电路的第一导电层的平面结构图。
图4D为本公开实施例提供的显示基板中冗余像素电路的有源半导体层和第一导电层的叠层结构示意图。
图4E为本公开实施例提供的显示基板中冗余像素电路的第二导电层的平面结构图。
图4F为本公开实施例提供的显示基板中冗余像素电路的源漏金属层的平面结构图。
图4G为本公开实施例提供的显示基板中冗余像素电路的有源半导体层、第一导电层、第二导电层、源漏金属层的叠层结构示意图。
图4H为本公开实施例提供的显示基板中冗余像素电路的第一电极的平面结构图。
图4I为本公开实施例提供的显示基板中冗余像素电路的有源半导体层、第一导电层、第二导电层、源漏金属层、第一电极的叠层结构示意图。
图5为本公开实施例提供的显示基板中冗余像素电路的层结构图的另一种实施例。
图6为本公开实施例提供的显示基板中像素电路的层结构图的一种实施例。
图7为本公开实施例提供的显示基板中GOA、冗余像素电路、像素电路的位置示意图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅是本发明的部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是为了便于对本发明实施例的内容的理解。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极在一定条件下是可以互换的，所以其源极、漏极从连接关系的描述上是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型 和P型，以下实施例中是以晶体管为P型晶体管进行说明的。当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，栅极输入低电平时，源漏极导通，N型相反。可以想到的是采用晶体管为N型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的
需要说明的是，下文中的第一方向和第二方向可以为任意方向，第一方向和第二方向相交，例如第一方向可以为显示基板的第一侧的延伸方向(例如行方向)，第二方向可以为显示基板与第一侧相邻的第二侧的延伸方向(例如列方向)，为了便于描述，下文中以第一方向为平行于显示基板的下侧的行方向(X方向)，第二方向为平行于显示基板的右侧的列方向(Y方向)，第一方向和第二方向互相垂直或近似垂直为例进行说明。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了元件的区的具体形状，但并不是旨在限制性的。
第一方面，如图1所示，本公开实施例提供一种显示基板，该显示基板具有显示区S1，和围绕显示区S1的周边区S2。该显示面板包括基底1，基底1的显示区S1中包括多个像素单元，像素单元包括多个子像素，每个子像素包括发光器件和像素电路，像素电路设置在发光器件靠近基底一侧，也 即基底1上设置有多个像素电路2，且像素电路2设置在显示区S1中。在制作像素电路2的过程中，由于基底1的显示区S1内，与显示区S1以外的其他区域的膜层结构差异较大，因此靠近显示区S1与其他区域的交界处的像素电路2的图形会受到影响，进而影响到像素电路的准确性和均一性。例如，若通过光刻工艺刻蚀像素电路2的图形，光在显示区S1内的像素电路2处产生反射和衍射的路径，与光在显示区S1以外的其他区域处产生反射与衍射的路径不同，从而靠近显示区S1与其他区域的交接处的像素电路2的图形会由于光的反射和衍射路径的差异而产生刻蚀误差(例如刻蚀不足或刻蚀过度)，使形成的像素电路2与远离交界处的像素电路2的差异较大，进而影响显示区S1内多个像素电路2的均一性，因此，为了解决上述问题，通常在显示区S1的周围(即周边区S2)设置多个冗余(dummy)像素电路3进行过渡，以减小基底1上显示区S1和显示区S1外的区域的差异，也就是说，显示基板还包括多个冗余像素电路3，冗余像素电路3设置在基底1上，且冗余像素电路3设置在周边区S2中，冗余像素电路3的排布方式与像素电路2相同，冗余像素电路3上不设置发光器件，冗余像素电路3仅作为过渡的电路结构，使显示区S1的周边区域的膜层结构与显示区域S1中的膜层结构大致相同，以保证显示区S1内像素电路2的刻蚀准确性和均一性。其中，像素电路2包括多个晶体管和存储电容，冗余像素电路3包括多个晶体管的存储电容，冗余像素电路3中晶体管的数量，小于像素电路2中晶体管的数量。由于冗余像素电路3中晶体管的数量小于像素电路2中晶体管的数量，因此能够冗余像素电路3所占的空间，从而能够使周边区S2的面积减小，进而有利于实现显示装置的窄边框化。
需要说明的是，周边区S2是由冗余像素电路3的排布位置所限定出的区域，也即周边区S2即为基底1上设置有多个冗余像素电路3的区域。
如图2A所示，图2A为显示区S1内像素电路2在基底1上排列的电路 版图，多个像素电路2在基底1上且在显示区S1内沿第一方向(即X方向)和第二方向(即Y方向)重复排列，通过多条信号线(后续详述)每个像素电路驱动用于驱动像素单元中的子像素的发光器件。
上述显示区S1中的像素电路2可以采用多种结构，例如像素电路2可以包括3个晶体管1个电容(3T1C)的结构，或7个晶体管1个电容(7T1C)的结构，或12个晶体管1个电容(12T1C)的结构等，以像素电路2包括7T1C为例，具体的，像素电路2包括驱动晶体管T3、数据写入晶体管T4、存储存储电容Cstst、阈值补偿晶体管T2、第一复位晶体管T7、第二复位晶体管T1、第一发光控制晶体管T5以及第二发光控制晶体管T6。
如图2B-2C所述，图2B为本公开实施例提供的显示基板中，像素单元的子像素内，像素电路2的电路示意图(像素电路2包括7T1C)，图2C为图2A中单个像素电路2的电路版图。如图2B所示，像素电路2包括驱动晶体管T3、数据写入晶体管T4、存储存储电容Cst、阈值补偿晶体管T2、第一复位晶体管T7、第二复位晶体管T1、第一发光控制晶体管T5以及第二发光控制晶体管T6。像素单元的每个子像素内还包括发光器件(图中未示出)，发光器件包括依次设置在基底1上的第一电极、发光层和第二电极。
例如，如图2B所示，数据写入晶体管T4的第一极与驱动晶体管T3的第一极电连接，数据写入晶体管T4的第二极被配置为与数据线Data电连接以接收数据信号，数据写入晶体管T4的控制极被配置为与第一扫描信号线Scan1电连接以接收扫描信号；存储电容Cst的第一极与第一电源端ELVDD电连接，存储电容Cst的第二极与驱动晶体管T3的控制极电连接；阈值补偿晶体管T2的第一极与驱动晶体管T3的第二极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的控制极电连接，阈值补偿晶体管T2的控制极被配置为与第二扫描信号线Scan2电连接以接收补偿控制信号；第二复位晶体管T1的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信 号，第二复位晶体管T1的第二极与驱动晶体管T3的控制极电连接，第二复位晶体管T1的控制极被配置为与第一复位控制信号线Rst1电连接以接收第一复位控制信号；第一复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第一复位晶体管T7的第二极与发光器件OLED的第一电极电连接，第一复位晶体管T7的控制极被配置为与第二复位控制信号线Rst2电连接以接收第二复位控制信号；第一发光控制晶体管T5的第一极与第一电源端ELVDD电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接，第一发光控制晶体管T5的控制极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的第二极与发光器件OLED的第一电极电连接，第二发光控制晶体管T5的控制极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光器件OLED的第二电极与第二电源端ELVSS电连接。
例如，第一电源端ELVDD和第二电源端ELVSS之一为高压端，另一个为低压端。例如，如图2B所示的实施例中，第一电源端ELVDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端ELVSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端ELVSS可以接地。
例如，如图2B所示，扫描信号和补偿控制信号可以相同，即，数据写入晶体管T4的控制极和阈值补偿晶体管T2的控制极可以电连接到同一条信号线，例如都电连接第一扫描信号线Scan1，以接收相同的信号(例如，扫描信号)，此时，显示基板可以不设置第二扫描信号线Scan2，减少信号线的数量。又例如，数据写入晶体管T4的控制极和阈值补偿晶体管T2的控制极也可以分别电连接至不同的信号线，即数据写入晶体管T4的控制极电连接到第一扫描信号线Scan1，阈值补偿晶体管T2的控制极电连接到第二扫描信 号线Scan2，而第一扫描信号线Scan1和第二扫描信号线Scan2传输的信号相同。
需要说明的是，扫描信号和补偿控制信号也可以不相同，从而使得数据写入晶体管T4的控制极和阈值补偿晶体管T2可以被分开单独控制，增加控制像素电路的灵活性。
例如，如图2B所示，第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T5的控制极和第二发光控制晶体管T5的控制极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T5的控制极和第二发光控制晶体管T5的控制极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T5的控制极电连接到第一发光控制信号线EM1，第二发光控制晶体管T5的控制极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输的信号相同。
需要说明的是，当第一发光控制晶体管T5和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T5为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，第一复位控制信号和第二复位控制信号可以相同，即，第二复位晶体管T1的控制极和第一复位晶体管T7的控制极可以电连接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)，此时，显示基板可以不设置第二复位控制信号线Rst2，减少信号线的数量。又例如，第二复位晶体管T1的控制极和第一复位晶体管T7的控制极也可以分别电连接至不同的信号线，即第二复位晶体管T1的控制极电连接到第一复位控制信号线Rst1，第一复位晶体管T7的控制极电连接到 第二复位控制信号线Rst2，而第一复位控制信号线Rst1和第二复位控制信号线Rst2传输的信号相同。需要说明的是，第一复位控制信号和第二复位控制信号也可以不相同。
例如，在一些示例中，第二复位控制信号可以与扫描信号相同，即第一复位晶体管T7的控制极可以电连接到扫描信号线Scan以接收扫描信号作为第二复位控制信号。
例如，第二复位晶体管T1的第二极和第一复位晶体管T7的第二极分别连接到第一复位电源端Vinit1和第二复位电源端Vinit2，第一复位电源端Vinit1和第二复位电源端Vinit2可以为直流参考电压端，以输出恒定的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第二复位晶体管T1的源极和第一复位晶体管T7的源极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T3的控制极和发光器件OLED的第一电极进行复位即可，本公开实施例对此不作限制。例如，第二复位晶体管T1的第二极和第一复位晶体管T7的第二极可以均连接至复位电源信号线Init，通过复位电源信号线Init连接至复位电源端Vinit。
如图1、图3A-图3C所示，图3A为图3A为冗余像素电路3在基底1上排列的电路版图，图3B为图3A中单个冗余像素电路3的电路版图的一种实施例，图3C为单个冗余像素电路3等效的电路示意图。冗余像素电路3围绕显示区S1设置在周边区S2中，以图3B为设置在上侧的圆角处的冗余像素电路3为了，图3B中的冗余像素电路3将像素电路2的上半部分切除，冗余像素电路3的晶体管的数量少于像素电路2的晶体管的数量，例如，冗余像素电路3可以包括驱动晶体管T3、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7和存储电容Cst，驱动晶体管T3设置在 存储电容Cst靠近基底1一侧，第一发光控制晶体管T5和第二发光控制晶体管T6设置在存储电容Cst的第一侧，例如图3B中第一侧为下侧，第一复位晶体管T7设置在第一发光控制晶体管T5和第二发光控制晶体管T6之间的连线背离存储电容Cst一侧。图3B所示的冗余像素电路3的实施例中，冗余像素电路3的上侧还保留了部分阈值补偿晶体管T2的栅极结构(图中T2＇所示)，以及数据写入晶体管T4的栅极表结构(图中T4＇所示)，因此T2、T4不导通，也可以将T2、T4全切除，具体的冗余像素电路3需要设置的位置来设置。参见图2C和图3B，也即冗余像素电路3包含像素电路2的部分电路结构，因此冗余像素电路3相比像素电路2占用的空间更小，从而能够减小周边区S2的面积，进而有利于实现显示装置的窄边框化。且由于冗余像素电路3具有像素电路2的电路结构，因此冗余像素带你来3可以减少显示区S1(像素电路2所在区域)与显示区S1以外的区域的差异性，从而能够保证像素电路3的均一性。如图3C所示，由于冗余像素电路3仅保留像素电路2中的驱动晶体管T3、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7和存储电容Cst，因此发光控制晶体管T5、第二发光控制晶体管T6和数据写入晶体管T4断开，存储电容Cst的第二极、驱动晶体管T3的控制极与阈值补偿晶体管T2断开。其中，存储电容Cst的第一极与第一电源端ELVDD电连接，存储电容Cst的第二极与驱动晶体管T3的控制极电连接；第一复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第一复位晶体管T7的控制极被配置为与第二复位控制信号线Rst2电连接以接收第二复位控制信号；第一发光控制晶体管T5的第一极与第一电源端ELVDD电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接，第一发光控制晶体管T5的控制极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控 制晶体管T6的控制极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号。
需要说明的是，冗余像素电路3的结构可以根据需要设置的位置改变，也即冗余像素电路3切除的结构可以根据需要改变，例如若冗余像素电路3设置在靠近显示区S1的下侧的周边区S2中，也可以将像素电路3的下半部分切除(例如切除掉发光控制晶体管T5、第二发光控制晶体管T6和第一复位晶体管T7的结构)，在此不做限定。
如图4A所示，图4A为本公开实施例提供的显示基板在周边区S2内冗余像素电路3的层结构示意图，本公开实施例提供的显示基板还包括，设置在基底1上的有源半导体层20，设置在有源半导体层20远离基底1的一侧的第一导电层30，设置在有源半导体层20与第一导电层30之间栅极绝缘层21，设置在第一导电层30远离栅极绝缘层21的一侧的第二导电层40，设置在第二导电层40与第一导电层30之间第一绝缘层31，设置在第二导电层40远离第一绝缘层31一侧的源漏金属层50，设置在源漏金属层50与第二导电层40之间第二绝缘层41。显示基板还可以包括设置在源漏金属层50背离基底1一侧的平坦层51，设置在平坦层51背离基底一侧的第一电极601，第一电极601为显示区S1中像素单元中的子像素中的发光器件的电极。
如图6所示，图6为本公开实施例提供的显示基板在显示区S1内像素电路2的层结构示意图，在第一电极601与基底1之间，像素电路2的层结构与冗余像素电路的层结构大致相同，至在每个膜层的平面结构图上，冗余像素电路3仅具有像素电路2的部分结构(仅具有驱动晶体管T3、第一发光控制晶体管T5、第二发光控制晶体管T6和第一复位晶体管T7的结构)，在像素电路2背离基底一侧具有发光器件60，发光器件60包括依次设置在平坦层51背离基底1一侧的第一电极601、第二电极602和发光层603，相邻的发光器件60之间具有像素定义层70，以限定出不同的子像素。像素定义 层70具有开口001,开口001即为发光器件60的发光区。由于冗余像素电路3不用驱动发光器件发光，因此冗余像素电路3之上不设置发光器件，也不进行开口。在一些实施例中，如图4A所示，可以冗余像素电路3的平坦层51背离基底1一侧保留发光器件6的第一电极601，在另一些实施例中，如图5所示，也可以在冗余像素电路3的平坦层51背离基底1一侧设置发光器件6的第一电极601，再在第一电极601背离基底1一侧设置像素定义层70，但不在像素定义层70上制作开口。为了便于说明，以下皆以冗余像素电路3的平坦层51背离基底1一侧仅具有第一电极601为例进行说明。
例如，如图4B所示，图4B示出了该显示基板中冗余像素电路3的有源半导体层20的平面结构示意图。有源半导体层20可采用半导体材料图案化形成。有源半导体层20可用于制作上述像素电路20的第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7的有源层。有源半导体层310包括各冗余像素电路3中的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)。
在一些实施例中，有源半导体层310中，同一冗余像素电路3中的各晶体管(例如驱动晶体管T3、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7)的有源层一体设置，即同一冗余像素电路3中的驱动晶体管T3、第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7的有源层相连。
需要说明的是，上述晶体管的有源层可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化以实现各结构的电连接。也就是每个子像素的各晶体管的有源半导体层为由p-硅形成的整体图案，且同一像素电路中的各晶体管包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，有源半导体层20可采用非晶硅、多晶硅、氧化物半导体材料等 制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，如图4B所示，像素单元中沿第一方向(X方向)排列的冗余像素电路3中的有源层没有连接关系，彼此断开。沿第二方向(Y方向)排列的冗余像素电路3中的有源层可以为一体设置，也可以彼此断开。
图4C-图4F还示出显示基板还包括的扫描信号线Scan(包括第一扫描信号线Scan1和第二扫描信号线Scan2)、复位控制信号线Rst(包括第一复位控制信号线Rst1和第二复位控制信号线Rst2)、复位电源端Vinit的复位电源信号线Init(包括第一复位电源端Vinit1的第一复位电源信号线Init1以及第二复位电源端Vinit2的第二复位电源信号线Init2)、发光控制信号线EM(包括第一发光控制信号线EM1和第二发光控制信号线EM2)、数据线Data以及电源信号线VDD还有子电源信号线VDD＇。
具体地，如图3C、4C-4E所示，多条扫描信号线Scan、多条复位电源信号线Init、多条复位控制信号线Rst以及多条发光控制信号线EM沿第一方向(X方向)由显示区S1延伸至周边区S2，也就是说，上述信号线贯穿显示区S1和周边区S2设置，在显示区S1，上述信号线连接至像素电路2对应的晶体管和/或存储电容，在周边区S2，上述信号线连接至冗余像素电路3对应的晶体管和/存储或电容。在冗余像素电路3中，与像素电路2相同，第一复位晶体管T7的第一极与复位电源信号线Init电连接至复位电源端Vinit，第一复位晶体管T7的控制极与复位控制信号线Rst电连接，第一发光控制晶体管T5的控制极与发光控制信号线EM电连接。
进一步地，如图3C、4C-4E所示，多条数据线Data、多条电源信号线VDD沿第二方向由显示区S1延伸至周边区S2。也就是说，上述信号线贯穿显示区S1和周边区S2设置，在显示区S1，上述信号线连接至像素电路2对应的晶体管和/或存储电容，在周边区S2，上述信号线连接至冗余像素电 路3对应的晶体管和/存储或电容。子电源信号线VDD＇与电源信号线VDD相连。冗余像素电路3以及像素电路2中的晶体管通过复位电源信号线Init连接复位电源端Vinit。如图3C所示，在冗余像素电路3中，与像素电路2相同，存储电容Cst的第一极与电源信号线VDD电连接至第一电源端ELVDD，存储电容Cst的第二极与驱动晶体管T3的控制极相连，第一发光控制晶体管T5的第一极与电源信号线VDD电连接至第一电源端ELVDD。
在一些实施例中，如图4A、4C-4E所示，冗余像素电路3还包括设置在平坦层51背离基底1一侧的第一电极601，在冗余像素电路3中，与像素电路2相同，第一复位晶体管T5的第二极与第一电极601电连接，第二发光控制晶体管T6的第二极与第一电极601电连接。
需要说明的是，在图4B-4F所示的示例中，第一扫描信号线Scan1和第二扫描信号线Scan2为同一条扫描信号线Scan，第一复位电源信号线Init1和第二复位电源信号线Init2为同一条复位电源信号线Init，第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条位控制信号线Rst，第一发光控制信号线EM1和第二发光控制信号线EM2为同一条发光控制信号线EM，但不限于此。
同上述像素电路2，冗余像素电路3中的第一发光控制信号和第二发光控制信号可以相同，即，第一发光控制晶体管T5的控制极和第二发光控制晶体管T5的控制极可以电连接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)，此时，显示基板可以不设置第二发光控制信号线EM2，减少信号线的数量。又例如，第一发光控制晶体管T5的控制极和第二发光控制晶体管T5的控制极也可以分别电连接至不同的信号线，即，第一发光控制晶体管T5的控制极电连接到第一发光控制信号线EM1，第二发光控制晶体管T5的控制极电连接到第二发光控制信号线EM2，而第一发光控制信号线EM1和第二发光控制信号线EM2传输 的信号相同。
需要说明的是，当第一发光控制晶体管T5和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T5为P型晶体管，而第二发光控制晶体管T5为N型晶体管时，第一发光控制信号和第二发光控制信号也可以不相同，本公开的实施例对此不作限制。
例如，如图4C所示，图4示出第一导电层30的平面结构示意图。第一导电层30设置在有源半导体层20背离基底1一侧，且第一导电层30与有源半导体层20之间具有栅极绝缘层21，从而使第一导电层30与有源半导体层20绝缘。第一导电层30可以包括存储电容Cst的第二极CC2、扫描信号线Scan、复位控制信号线Rst、发光控制信号线EM，也就是说，多条扫描信号线Scan，多条复位控制信号线Rst，多条发光控制信号线EM同层设置。在周边区S2内，第一导电层30还包括第一发光控制晶体管T5、第二发光控制晶体管T6、第一复位晶体管T7和的控制极(即栅极)，例如，如图4D所示，图4D为将图4B所示的有源半导体层20与图4C所示的第一导电层30相叠，且省略栅极绝缘层21的层叠示意图。第一发光控制晶体管T5的控制极G1可以为发光控制信号线EM与有源半导体层20交叠的部分，第二发光控制晶体管T6的控制极G2可以为发光控制信号线EM与有源半导体层20交叠的部分，第一复位晶体管T7的控制极G3可以为复位控制信号线Rst与有源半导体层20交叠的部分，驱动晶体管T3的控制极G4可以为存储电容Cst的第二极CC2。
需要说明的是，图4B中的各虚线矩形框示出了第一导电层30与有源半导体层20交叠的各个部分。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化以形成各个晶体管的第一极和第二极。
例如，如图4C所示，扫描信号线Scan、复位控制信号线Rst和发光控 制信号线EM沿第二方向(Y方向)排布。扫描信号线Scan位于复位控制信号线Rst和发光控制信号线EM之间。
例如，如图4C所示，在第二方向(Y方向)上，存储电容Cst的第二极CC2(即下极板)位于扫描信号线Scan和发光控制信号线EM之间。
例如，如图4E所示，图4E示出第二导电层40的平面结构示意图。第二导电层40设置在第一导电层30背离基底1一侧，且第一导电层30和第二导电层40之间具有第一绝缘层31，第一绝缘层31使第一导电层30和第二导电层40绝缘。参见图4E，第二导电层40包括存储电容Cst的第一极CC1、复位电源信号线Init、子电源信号线VDD'以及遮光部S。位于第一导电层30的第二极CC2与位于第二导电层40的第一极CC1在垂直于基底1的方向上至少部分重叠，形成存储电容Cst。子电源信号线VDD'(图4E中虚线框所示)与存储电容Cst的第一极CC1可一体形成，从而子电源信号线VDD’沿第一方向延伸，通过子电源信号线VDD'与电容C的第一极CC1，将在第二方向(Y方向)延伸的多条电源信号线VDD进行连通，进而形成网格化布线，以降低电阻。
例如，如图2C所示，在显示区S2中的像素电路2，阈值补偿晶体管T2关闭时处于浮置(floating)状态，易受周围线路电压的影响而跳变，从而会影响阈值补偿晶体管T2的漏电流，进而影响发光亮度。为了保持阈值补偿晶体管T2两段沟道之间的有源半导体层电压稳定，设计遮光部S与阈值补偿晶体管T2两段沟道之间的有源半导体层形成电容，遮光部S可以连接至电源信号线VDD以获得恒定电压，因此处于浮置状态的有源半导体层的电压可以保持稳定。遮光部S与阈值补偿晶体管T2两段沟道之间的有源半导体层交叠，还可以防止两个栅极之间的有源半导体层被光照而改变特性，例如防止该部分有源半导体层的电压发生变化，以防止产生串扰。在周边区S2的冗余像素电路3中，冗余像素电路3不包含阈值补偿晶体管T2，但在制作 第二导电层40的过程中，为了保证刻蚀的均一性，在冗余像素电路3中也具有遮光部S。遮光部S位于存储电极Cst的第一极C11与复位电源信号线Init之间的至少一侧。
例如，如图4F所示，图4F示出源漏金属层50的平面结构示意图。源漏金属层50设置在第二导电层40背离基底1一侧，且第二导电层40和源漏金属层50之间具有第二绝缘层41，第二绝缘层41使源漏金属层50和第二导电层40绝缘。源漏金属层50包括数据线Data以及电源信号线VDD。上述数据线Data以及电源信号线VDD均沿第二方向(Y方向)延伸。也即多条数据线Data设置在复位电源信号线Init背离扫描信号线Scan一侧，多条电源信号线VDD与多条数据线Data同层设置，且在第一方向(X方向)上，电源信号线VDD与数据线Data交替设置。
例如，如图4F所示，源漏金属层50还包括第一连接部A1、第二连接部A2和第三连接部A3。第一连接部A1、第二连接部A2和第三连接部A3在源漏极金属层50沿第二方向(Y方向)重复排列，第二连接部A2的被配置为连接驱动晶体管T3的控制极(即存储电容Cst的第二极CC2)电连接，第二连接部A2被配置为连接复位电源信号线Init和第一复位晶体管T7的第一极，第三连接部A3被配置为连接第一电极与第二发光控制晶体管T6的第二极。
图4F还示出了源漏金属层50中多个过孔的示例性位置，源漏金属层50通过所示的多个过孔与位于该源漏金属层50与基底1之间的多个膜层连接。如图4F所示，不同填充的过孔表示源漏金属层50通过其连接至不同膜层。例如，白色填充的过孔表示源漏金属层50通过这些过孔连接至图4B所示的有源半导体层20，斜线填充的过孔表示源漏金属层50通过这些过孔连接至图4C所示的第一导电层30，黑色填充的过孔表示源漏金属层50通过这些过孔连接至图4E所示的第二导电层40。
例如，如4A-4C、4E-4G所示，其中，图4G为图4B所示的有源半导体层20、图4C所示的第一导电层30、图4E所示的第二导电层40、图4F所示的源漏金属层50相叠的叠层示意图(省略各绝缘层)。在显示区S1中的像素电路2的膜层中，数据线Data通过贯穿栅极绝缘层21、第一绝缘层31和第二绝缘层41的过孔06与数据写入晶体管T4的第二极电连接，在周边区S2中的冗余像素电路3中，虽冗余像素电路3中不具有数据写入晶体管T4，但在进行打孔工艺时，为了提高像素电路2中打孔的均一性，在冗余像素电路3的源漏金属层50中也制作了过孔06。也就是说，在冗余像素电路3的膜层中的各个过孔的数量与位置，与像素电路2中各个过孔的数量与位置相同，但冗余像素电路3只使用部分过孔，以下描述中提到电连接阈值补偿晶体管T2、第二复位晶体管T1、数据写入晶体管T4的过孔皆仅在显示区S1中的像素电路2中使用，在冗余像素电路3中存在但不进行电连接。电源信号线VDD通过贯穿栅极绝缘层21、第一绝缘层31和第二绝缘层41的过孔09与第一发光控制晶体管T5的第一极电连接。电源信号线VDD和数据线Data沿第一方向交替设置。电源信号线VDD通过贯穿第二绝缘层41的过孔08与子电源信号线VDD'(存储电容Cst的第一极CC1)电连接，电源信号线VDD沿第二方向(Y方向)延伸，子电源信号线VDD'沿第一方向(X方向)延伸，从而电源信号线VDD和子电源信号线VDD'在显示基板的基底1上网格化布线。也就是说，在整个显示基板的及其1上，电源信号线VDD和子电源信号线VDD'呈网格状排列，从而使得第一电源端ELVDD的信号线的电阻较小、压降较低，进而可以提高第一电源端ELVDD提供的电源电压的稳定性和均匀性。电源信号线VDD通过贯穿第二绝缘层41的过孔07与遮光部S电连接，从而电源信号线VDD能够为遮光部S提供恒定电压。第一连接部A1的一端通过贯穿第二绝缘层41中的过孔05与复位电源信号线Init电连接，第一连接部A1的另一端通过贯穿栅极绝缘层21、第一绝缘层 31和第二绝缘层41中的过孔04与第一复位晶体管T7的第一极电连接。第二连接部A2的一端通过贯穿栅极绝缘层21、第一绝缘层31和第二绝缘层41中的过孔02与阈值补偿晶体管T2的第二极电连接，第二连接部A2的另一端通过贯穿第一绝缘层31和第二绝缘层41中的过孔01与驱动晶体管T3的控极电连接。第三连接部A3的一端通过贯穿栅极绝缘层21、第一绝缘层31和第二绝缘层41中的过孔03与第二发光控制晶体管T6的第二极电连接。
在一些示例中，如图4A所示，在上述的源漏金属层50上形成有平坦层51(用于保护上述的源漏金属层50。如图4F所示，平坦层50中包括具有过孔011，像素单元中的子像素的发光元件6的第一电极601可设置在平坦层50远离基底1的一侧，且发光元件6的第一电极601通过过孔011与第三连接部A3的另一端电连接，以实现第二发光控制晶体管T6与第一电极601连接。平坦层51中过孔011在源漏金属层50上的正投影的位置位于第三连接部A3上(图4F中虚线框所示位置)。
在一些示例中，如图4A、4H-4I所示，图4I为图4B所示的有源半导体层20、图4C所示的第一导电层30、图4E所示的第二导电层40、图4F所示的源漏金属层50、图4H所示的第一电极406相叠的叠层图。在源漏金属层50背离基底1一侧还设置了发光器件6的第一电极601，其中，每个像素单元可以包括多个子像素，在显示区S1中，每个子像素对应一个发光器件，在周边区S2中，每个子像素对应一个第一电极，例如，如图4H所示，每个像素单元包括沿第一方向(X方向)排列的第一颜色子像素、第二颜色子像素组和第三颜色子像素，每个第二颜色子像素组包括沿第二方向(Y方向)排列的两个第二颜色子像素，第一颜色子像素的发光器件对应第一颜色第一电极6011，第二颜色子像素的发光器件对应第二颜色第一电极6012，第三颜色子像素的发光器件对应第三颜色第一电极6013。参见图4I，各第一颜色第一电极6011基底1上的正投影位于数据线Data在基底1上的正投影内。第 二颜色第一电极6012沿第二方向延伸的中心线正下方没有源漏金属层50。第二颜色第一电极6012在基底1上的正投影与数据线Data和第一连接部A1在基底1上的正投影均有交叠。例如，4I所示，第一颜色第一电极6011与电源信号线VDD、数据线Data以及第三连接部A3均有交叠，电源信号线VDD和第三连接部A3位于数据线Data的两侧。垂直于基底1的方向，第二颜色第一电极6012与数据线Data、电源信号线VDD、第一连接部A1以及第三连接部A3均有交叠，且第二颜色第一电极6012的中心线与第三连接部A3有交叠；沿垂直于及其1的方向。沿垂直于基底1的方向。第三颜色第一电极6013与数据线Data、电源信号线VDD、第二连接部A2、第一连接部A1以及第三连接部A3均有交叠，且数据线Data位于中心线的一侧，第二连接部A2位于中心线另一侧。
例如，如图5所示，若冗余像素电路3在第一电极601上还设置有像素定义层70，则在4I所示的膜层上，可以在第一电极601背离基底1一侧制作像素定义层70。
在一些实施例中，如图7所示，显示基板还包括栅极阵列集成驱动(Gate Drive on Array)，GOA设置在周边区S2的背离显示区S1的至少一侧，多条信号线由GOA所在区域延伸至周边区S2，再由周边区S2延伸至显示区S1，连接像素电路2和冗余像素电路3。具体地，信号线可以包括复位电源信号线Init、发光控制信号线EM、扫描信号线Scan、复位控制信号线Rst等，其中复位电源信号线Init可以电连接第一复位控制晶体管T1的第一极和第二复位晶体管T7的第一极；发光控制信号线EM可以电连接第一发光控制晶体管T5的控制极和第二发光控制晶体管T6的控制极；扫描信号线Scan可以电连接至阈值补偿晶体管T2的控制极和数据写入晶体管T4的控制极；复位控制信号线Rst可以电连接至第一复位晶体管T7的控制极和第二复位晶体管T1的控制极。当然，多条信号线的具体结构不仅限于上述结构，以上仅为一 种示例性的结构，不对本发明构成限制。多条信号线穿过周边区S2相邻的冗余像素电路3之间的缝隙，连接至显示区S1中像素电路2，由于冗余像素电路3所占的空间减小，从而周边区S2中冗余像素电路3的密度减小，因此多条信号线可以通过多个冗余像素电路3之间的缝隙引至像素电路2，并且可以避免由于冗余像素电路3太密集导致多条信号线之间发生短路。
第二方面，本公开实施例还提供一种显示装置，包括上述显示基板。需要说明的是，本实施例提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
进一步地，显示装置还可以包括多种类型的显示装置，例如液晶显示装置，有机电致发光(OLED)显示装置，迷你二极管(Mini LED)显示装置，在此不做限定。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (14)

  1. 一种显示基板，该显示基板具有显示区，和围绕所述显示区的周边区，其中，包括：
    基底；
    多个像素电路，位于所述基底上，且设置在所述显示区中；
    多个冗余像素电路，位于所述基底上，且设置在所述周边区中；其中，
    每个所述冗余像素电路中晶体管的数量，小于所述像素电路中晶体管的数量。
  2. 根据权利要求1所述的显示基板，其中，所述冗余像素电路包括驱动晶体管、第一发光控制晶体管、第二发光控制晶体管、第一复位晶体管和存储电容；其中，
    所述驱动晶体管设置在所述存储电容靠近所述基底一侧；
    所述第一发光控制晶体管，所述第二发光控制晶体管设置在所述存储电容的第一侧；
    所述第一复位晶体管设置在所述第一发光控制晶体管和所述第二发光控制晶体管之间的连线背离所述存储电容一侧。
  3. 根据权利要求2所述的显示基板，其中，所述显示基板还包括：
    多条扫描信号线，沿第一方向由显示区延伸至周边区，且设置在所述基底上；
    多条复位电源信号线，沿第一方向由显示区延伸至周边区，且位于所述扫描信号线所在膜层背离所述基底一侧；
    多条复位控制信号线，沿第一方向由显示区延伸至周边区，且与所述扫描信号线同层设置；
    多条发光控制信号线，沿第一方向由显示区延伸至周边区，且与所述扫 描信号线同层设置；其中，
    所述第一复位晶体管的第一极与所述复位电源信号线电连接；
    所述第一复位晶体管的控制极与所述复位控制信号线电连接；
    所述第一发光控制晶体管的控制极与所述发光控制信号线电连接。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板还包括：
    多条数据线，沿第二方向由显示区延伸至周边区，且设置在所述复位电源信号线背离所述扫描信号线一侧；
    多条电源信号线，沿第二方向由显示区延伸至周边区，所述多条电源信号线与所述多条数据线同层且交替设置；所述第一方向和所述第二方向相交；其中
    所述存储电容的第一极与所述电源信号线电连接，所述存储电容的第二极与所述驱动晶体管的控制极电连接；
    所述第一发光控制晶体管的第一极与所述电源信号线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板还包括第一电极；所述第一电极设置在所述数据线背离所述基底一侧；其中，
    所述第一复位晶体管的第二极与所述第一电极电连接；
    所述第二发光控制晶体管的第二极与所述第一电极电连接。
  6. 根据权利要求5所述的显示基板，其中，每个所述冗余像素电路中还包括与所述数据线同层设置的第一连接部、第二连接部和第三连接部；所述第一连接部、所述第二连接部和所述第三连接部沿所述第二方向排列；
    所述第一连接部被配置为连接所述复位电源信号线和所述第一复位晶体管的第一极，所述第二连接部被配置为连接所述驱动晶体管的控制极，所述第三连接部被配置为连接所述第一电极与所述第二发光控制晶体管的第二极。
  7. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：有源半导体层，设置在所述基底上；所述有源半导体层包括所述像素电路和所述冗余像素电路中各晶体管的有源层。
  8. 根据权利要求7所述的显示基板，其中，每个所述冗余像素电路中各晶体管的有源层一体设置。
  9. 根据权利要求7所述的显示基板，其中，所述显示基板还包括：
    第一导电层，位于所述有源半导体层远离所述基底的一侧；
    栅极绝缘层，位于所述有源半导体层与所述第一导电层之间；其中，
    所述第一导电层包括多个所述存储电容的第二极、多条沿所述第一方向延伸的扫描信号线、多条沿所述第一方向延伸的复位控制信号线、多条沿所述第一方向延伸的发光控制信号线；
    所述周边区内，每个冗余像素电路中，所述第一导电层还包括多个所述第一发光控制晶体管、多个所述第二发光控制晶体管、多个所述第一复位晶体管的栅极。
  10. 根据权利要求8所述的显示基板，其中，所述显示基板还包括：
    第二导电层，位于所述第一导电层远离所述栅极绝缘层的一侧；
    第一绝缘层，位于所述第二导电层与所述第一导电层之间；其中，
    所述第二导电层包括多条沿所述第一方向延伸的复位电源信号线、多个所述存储电容的第一极。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：
    源漏金属层，位于所述第二导电层远离所述第一绝缘层一侧；
    第二绝缘层，位于所述源漏金属层与所述第二导电层之间；其中，
    所述源漏金属层包括多条沿第二方向延伸的电源信号线、多条沿第二方向延伸的数据线、多个第一连接部、多个第二连接部以及多个第三连接部。
  12. 根据权利要求1所述的显示基板，其中，还包括：栅极阵列集成驱动，设置在所述周边区背离所述显示区至少一侧，所述栅极阵列集成驱动通过贯穿所述周边区的第一引线，连接所述显示区中的像素电路。
  13. 根据权利要求1-12任一项所述的显示基板，其中，每个所述像素电路包括第一发光控制晶体管、第二发光控制晶体管、驱动晶体管、数据写入晶体管、存储电容、阈值补偿晶体管、第一复位晶体管和第二复位晶体管；
    所述数据写入晶体管的第一极与所述驱动晶体管的第一极电连接，所述数据写入晶体管的第二极与数据线电连接以接收数据信号，所述数据写入晶体管的控制极与扫描信号线电连接以接收扫描信号；
    所述存储电容的第一极与电源信号线电连接，所述存储电容的第二极与所述驱动晶体管的控制极电连接；
    所述阈值补偿晶体管的第一极与所述驱动晶体管的第二极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的控制极电连接，所述阈值补偿晶体管的控制极与所述扫描信号线电连接以接收补偿控制信号；
    所述第一复位晶体管的第一极与复位电源信号线电连接以接收第一复位信号，所述第一复位晶体管的第二极与发光器件电连接，所述第二复位晶体管的控制极与所述复位控制信号线电连接以接收第一复位控制信号；
    所述第二复位晶体管的第一极与复位电源信号线电连接以接收第二复位信号，所述第二复位晶体管的第二极与所述驱动晶体管的控制极电连接，所述第一复位晶体管的控制极与复位控制信号线电连接以接收第二复位控制信号；
    所述第一发光控制晶体管的第一极与所述电源信号线电连接，所述第一 发光控制晶体管的第二极与所述驱动晶体管的第一极电连接，所述第一发光控制晶体管的控制极与所述发光控制信号线电连接以接收第一发光控制信号；
    所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件电连接，所述第二发光控制晶体管的控制极与所述发光控制信号线电连接以接收第二发光控制信号。
  14. 一种显示装置，其中，包括1-13任一所述的显示基板。
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