WO2021218030A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021218030A1
WO2021218030A1 PCT/CN2020/118962 CN2020118962W WO2021218030A1 WO 2021218030 A1 WO2021218030 A1 WO 2021218030A1 CN 2020118962 W CN2020118962 W CN 2020118962W WO 2021218030 A1 WO2021218030 A1 WO 2021218030A1
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WIPO (PCT)
Prior art keywords
pixel
sub
base substrate
electrode
orthographic projection
Prior art date
Application number
PCT/CN2020/118962
Other languages
English (en)
French (fr)
Inventor
刘彪
都蒙蒙
马宏伟
舒晓青
张振华
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from PCT/CN2020/086997 external-priority patent/WO2021217295A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/430,675 priority Critical patent/US20220052147A1/en
Priority to CN202080002176.4A priority patent/CN113853684A/zh
Priority to EP20931708.0A priority patent/EP4145527A1/en
Publication of WO2021218030A1 publication Critical patent/WO2021218030A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • AMOLED Active-matrix organic light emitting diode
  • some embodiments of the present disclosure provide a display substrate.
  • the display substrate includes: a base substrate and a plurality of sub-pixels.
  • the sub-pixel includes a pixel electrode and an effective light-emitting area.
  • the pixel electrode includes an interconnected main body part and a connection part.
  • the main body has the same shape as the effective light-emitting area, and at least a part of the boundary of the main body and the pixel electrode overlaps.
  • the plurality of sub-pixels include at least one first sub-pixel and one second sub-pixel with the same emission color. The closest first sub-pixel and the second sub-pixel are arranged along a second direction.
  • the areas of the orthographic projection of the two pixel electrodes of the first sub-pixel and the second sub-pixel on the base substrate are different.
  • Two orthographic projections of the connecting portion and the main body portion of at least one of the first sub-pixel and the second sub-pixel on a straight line extending in the first direction do not overlap at least partially.
  • the orthographic projection of the pixel electrode of the second sub-pixel on a straight line extending in the second direction is located within the orthographic projection of the pixel electrode of the first sub-pixel on the same straight line.
  • the second direction intersects the first direction, and the angle between the two is in the range of 80°-100°.
  • the main body portion includes a first side, a second side, and a third side that are sequentially connected; the third side extends along the second direction.
  • the connecting portion is connected to the second side and has an interval with the first side.
  • the connecting line from any point on the first side to any point on the edge of the connecting portion extending in the second direction and away from the third side in the first direction is connected to the main body portion
  • the area enclosed by the connecting portion is a notch area.
  • the display substrate further includes a plurality of layers between the base substrate and the pixel electrode; the plurality of layers includes at least one metal pattern. Along a direction perpendicular to the base substrate, in each layer from the base substrate to the pixel electrode, at least a part of the notch area does not overlap with the metal pattern.
  • the display substrate further includes a plurality of layers between the base substrate and the pixel electrode; the plurality of layers includes a semiconductor pattern and at least one metal pattern. Along the direction perpendicular to the base substrate, in each layer from the base substrate to the pixel electrode, at least part of the notch area is not related to the semiconductor pattern and the metal pattern. overlap.
  • connection part of the pixel electrode in the first sub-pixel includes a curved part and a compensation part connected to the curved part.
  • the compensation part extends along the second direction.
  • the curved portion is connected to the second side, and there is an interval between the curved portion and the first side.
  • the ratio of the area of the notch area to the two orthographic projections of the curved portion on the base substrate ranges from 0.2 to 5.
  • the maximum dimension of the compensation portion along the first direction is greater than the maximum dimension of the curved portion along the first direction.
  • the maximum dimension of the connecting portion of the pixel electrode in the second sub-pixel along the second direction is less than or equal to the largest dimension along the second direction of the curved portion of the pixel electrode in the first sub-pixel. The maximum dimension of the direction.
  • the sub-pixel further includes a pixel circuit.
  • the pixel circuit includes a driving transistor.
  • the orthographic projection of the metal pattern with the same potential as the control electrode of the driving transistor on the base substrate is the first projection.
  • the overlapping area of the orthographic projection of the pixel electrode on the base substrate and the first projection in the first sub-pixel is the first area.
  • the overlapping area of the orthographic projection of the pixel electrode on the base substrate and the first projection in the second sub-pixel is the second area.
  • the ratio of the first area to the second area ranges from 0.8 to 1.2.
  • the display substrate further includes: a first gate metal layer located between the base substrate and the pixel electrode, and a first gate metal layer located between the first gate metal layer and the pixel electrode The first metal layer.
  • the metal pattern having the same potential as the control electrode of the driving transistor includes: a first electrode of the capacitor located in the first gate metal layer, and a first transfer electrode located in the first metal layer.
  • the overlapping area of the pixel electrode of the first sub-pixel and the first electrode of the capacitor on the base substrate is smaller than the area of the pixel electrode of the second sub-pixel and the first electrode of the capacitor.
  • the overlapping area of the orthographic projection on the base substrate; and the overlapping area of the pixel electrode of the first sub-pixel and the orthographic projection of the first transfer electrode on the base substrate is greater than The overlapping area of the pixel electrode of the second sub-pixel and the orthographic projection of the first transfer electrode on the base substrate.
  • the display substrate further includes: a plurality of signal lines extending along the first direction.
  • the orthographic projection of the pixel electrode of the first sub-pixel on the base substrate overlaps the orthographic projection of the at least three signal lines in the same layer on the base substrate.
  • the at least three signal lines in the same layer include: at least one gate scan signal line, at least one light emission control signal line, and at least one reset control signal line.
  • the display substrate further includes: a first insulating layer and a plurality of connection electrodes.
  • the first insulating layer is located between the pixel electrode and the connection electrode, and has a plurality of first via holes.
  • the pixel electrode is correspondingly coupled to the connection electrode through the first via hole.
  • the sub-pixel also includes a pixel circuit. A plurality of the pixel circuits are arranged in the first direction to form a row, and the pixel circuits are arranged in the second direction to form a column.
  • the orthographic projections of the plurality of first via holes corresponding to the plurality of pixel circuits in the same row on the base substrate are arranged along a first straight line.
  • the effective light-emitting area of the first sub-pixel and the effective light-emitting area of the second sub-pixel are respectively located on two sides of the first straight line. side.
  • the display substrate further includes: a second insulating layer and a plurality of driving electrodes.
  • the second insulating layer is located between the connecting electrode and the driving electrode, and has a plurality of second via holes.
  • the connecting electrode is correspondingly coupled to the driving electrode through the second via hole.
  • the first via hole and the second via hole corresponding to the same connecting electrode have an interval between the orthographic projections on the base substrate.
  • the orthographic projections of the plurality of second via holes corresponding to the plurality of pixel circuits in the same row on the base substrate are arranged along a second straight line.
  • the distance between the orthographic projection of any one of the first via hole and the second via hole on the base substrate to the effective light-emitting area of the corresponding sub-pixel is greater than 2 ⁇ m.
  • the shape and area of the orthographic projection of the first via hole and the second via hole on the base substrate are substantially the same.
  • the orthographic projections of the first via holes and the second via holes corresponding to the same connection electrode on the base substrate are arranged along a third straight line.
  • the shape of the orthographic projection of the driving electrode and the connecting electrode on the base substrate is approximately the same, and the orthographic projection area of the connecting electrode on the base substrate is larger than that of the driving electrode.
  • the orthographic projection area of the electrode on the base substrate is approximately the same, and the orthographic projection area of the connecting electrode on the base substrate is larger than that of the driving electrode.
  • the orthographic projection of the driving electrode on the base substrate is located within the orthographic projection of the connecting electrode on the base substrate, and a part of the boundary of the two orthographic projections overlaps or substantially overlaps.
  • the orthographic projection of the connecting electrode on the base substrate and the orthographic projection of the driving electrode on the base substrate have non-overlapping portions, and the first via is in the The orthographic projection on the base substrate overlaps the non-overlapping portion.
  • the display substrate further includes a semiconductor pattern layer and a third insulating layer.
  • the semiconductor pattern layer is located between the base substrate and the driving electrode.
  • the third insulating layer is located between the driving electrode and the semiconductor pattern layer, and has a plurality of third via holes.
  • the driving electrode is coupled to a corresponding part of the semiconductor pattern layer through the third via hole.
  • the third via hole, the second via hole, and the first via hole corresponding to the same drive electrode are located between two of the three orthographic projections on the base substrate interval.
  • the orthographic projection of any one of the first via hole and the second via hole on the base substrate to the third via hole on the base substrate The value range of the minimum interval between the orthographic projections is 0.8 ⁇ m ⁇ 10 ⁇ m.
  • the minimum interval between the orthographic projection of the first via hole and the second via hole on the base substrate ranges from 1 ⁇ m to 10 ⁇ m.
  • the display substrate further includes a plurality of data lines.
  • the data line and the driving electrode are arranged in the same layer.
  • the third insulating layer also has a plurality of fourth via holes.
  • the data line is connected to the corresponding pixel circuit through the fourth via hole.
  • the data line extends along the second direction, and the data line includes a plurality of protrusions protruding toward the corresponding pixel circuit in the first direction.
  • the overlap area between the orthographic projection of the fourth via on the base substrate and the orthographic projection of the protrusion on the base substrate is the area where the fourth via is located. 70%-100% of the orthographic projection area on the base substrate.
  • the display substrate further includes a plurality of power signal lines.
  • the plurality of power signal lines includes at least one first power signal line.
  • the first power signal line and the connecting electrode are arranged in the same layer.
  • the first power signal line includes a plurality of first sub power signal lines extending in the first direction and a plurality of second sub power signal lines extending in the second direction.
  • the first sub-power signal line and the second sub-power signal line are interconnected. There is an interval between the two effective light-emitting regions of the first sub-pixel and the second sub-pixel that are closest to each other.
  • the orthographic projection of the first sub-power signal line on the base substrate passes through the interval between the two effective light-emitting regions of the first sub-pixel and the second sub-pixel.
  • At least one of the second sub-power signal lines has at least one break.
  • the orthographic projection of the virtual connection line between the two end points in the second direction of the fracture on the base substrate passes through the two effective sub-pixels of the first sub-pixel and the second sub-pixel.
  • the second sub-power signal line with the fracture does not intersect with the two effective light-emitting areas of the first sub-pixel and the second sub-pixel, and the orthographic projection of the interval on the base substrate. Stacked.
  • the plurality of power signal lines further includes a plurality of second power signal lines.
  • the second power signal line extends along the second direction.
  • the display substrate further includes a second insulating layer and a plurality of driving electrodes
  • the second power signal line and the driving electrodes are provided in the same layer.
  • the second insulating layer also has a plurality of fifth via holes. The second sub-power signal line is correspondingly coupled to the second power signal line through the fifth via hole.
  • the orthographic projection of the second power signal line and the second sub-power signal line coupled thereto on the base substrate at least partially overlap.
  • the orthographic projection of the second power signal line on the base substrate and the effective light-emitting area of any one of the first sub-pixel and the second sub-pixel on the base substrate The projection part overlaps.
  • the orthographic projection of the plurality of fifth via holes located in the same row along the first direction on the base substrate is located on a fourth straight line extending along the first direction.
  • the distance from the orthographic projection of the fifth via on the base substrate to the orthographic projection of any one of the effective light-emitting areas on the base substrate is greater than 2.5 um.
  • the first sub-pixel and the second sub-pixel that are closest to each other form a sub-pixel pair.
  • One sub-pixel group includes one first-color sub-pixel, one said sub-pixel pair, and one third-color sub-pixel that are sequentially arranged along the first direction.
  • the sub-pixel pair is configured to emit light of the second color.
  • the center of the orthographic projection of at least one of the first effective light-emitting area of the first color sub-pixel and the third effective light-emitting area of the third color sub-pixel on the base substrate is located in the corresponding first
  • a sub-power signal line is in the orthographic projection on the base substrate.
  • the two second sub-power signal lines located on both sides of the first effective light-emitting area of the first color sub-pixel and adjacent to the first effective light-emitting area are separated from the first effective light-emitting area.
  • the distances between the center lines of the effective light-emitting areas extending along the second direction are not equal.
  • the display substrate further includes a plurality of pads and a plurality of supporting parts arranged on the same layer as the first power signal line.
  • the cushion block extends along the second direction.
  • the spacer block is located between the first effective light-emitting area and the second sub-power signal line, and is correspondingly coupled to the second sub-power signal line through the support portion.
  • the distance between the second sub-power signal line coupled to the pad and the center line of the first effective light-emitting area extending along the second direction is greater than the other one and the first effective light-emitting area.
  • the pad block is also correspondingly coupled to the first sub-power signal line.
  • the shape of the cushion block is substantially elongated.
  • the center of the orthographic projection of the spacer block on the base substrate is located within the orthographic projection of the first sub-power signal line coupled with the spacer on the base substrate.
  • the orthographic projection of the two effective light-emitting areas of the first sub-pixel and the second sub-pixel on the base substrate to the two effective light-emitting areas between the two effective light-emitting areas The value range of the ratio of the two distances of the orthographic projection of the first sub-power signal line on the base substrate is 0.9-1.1.
  • a display device in another aspect, includes the display substrate as described in any of the above embodiments.
  • FIG. 1 is a schematic structural diagram of a display device according to some embodiments of the present disclosure
  • FIG. 2A is an enlarged schematic diagram of a display substrate in the M0 area according to some embodiments of the present disclosure
  • 2B is a schematic diagram of a structure of a sub-pixel group in some embodiments of the present disclosure.
  • 2C is a schematic diagram of the distribution of a kind of sub-pixels on a base substrate according to some embodiments of the present disclosure
  • Fig. 3 is a schematic structural diagram of a pixel circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of the structure of each pixel electrode in a sub-pixel group according to some embodiments of the present disclosure
  • Fig. 5 is an enlarged schematic diagram of a display substrate in the M1 area according to some embodiments of the present disclosure
  • FIG. 6A 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, FIG. 6F, FIG. 6G, FIG. 6H, and FIG.
  • 6E' is a schematic diagram of the position between the via holes in the first metal layer and the second interlayer insulating layer 140 according to some embodiments of the present disclosure
  • 6G' is a schematic diagram of the position between the second metal layer and the via hole in the first flat layer 122 in some embodiments of the present disclosure
  • 6H' is a schematic diagram of the position between the second metal layer and the via hole in the second flat layer 121 according to some embodiments of the present disclosure
  • FIG. 6I' is a schematic diagram of the position between the second metal layer and the pixel electrode layer in some embodiments of the present disclosure
  • Fig. 7A is a partial schematic diagram of a display substrate according to some embodiments of the present disclosure.
  • Fig. 7B is a schematic cross-sectional view along the AA' direction of a display substrate according to some embodiments of the present disclosure
  • Fig. 7C is a schematic cross-sectional view along the BB' direction of a display substrate according to some embodiments of the present disclosure
  • Fig. 7D is a schematic cross-sectional view of a display substrate along the CC' direction according to some embodiments of the present disclosure
  • FIG. 7E is a schematic cross-sectional view along the D-E-F-G-H direction of a display substrate according to some embodiments of the present disclosure.
  • 7F is a schematic cross-sectional view along the L-M-N direction of a display substrate according to some embodiments of the present disclosure.
  • 7G is a schematic cross-sectional view along the R-S-T direction of a display substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of a position between a first via hole, a second via hole, a third via hole and a pixel electrode in some embodiments of the present disclosure
  • FIG. 9 is a schematic diagram of a position between a pixel electrode of a first sub-pixel and an adjacent pixel electrode in some embodiments of the present disclosure.
  • the directional terms such as “upper”, “lower”, “left” and “right” may include but are not limited to the directions defined relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be Relative concepts, they are used for relative description and clarification, which can be changed correspondingly according to the changes in the orientation of the parts in the drawings.
  • first”, “second” and other ordinal numbers are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first”, “second”, etc. may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • Approximately or “approximately” as used herein includes the stated value and the average value within the acceptable deviation range of a specific value, wherein the acceptable deviation range can be determined by the measurement error and the specific amount considered by those of ordinary skill in the art.
  • the measurement-related errors (such as the limitations of the measurement system) are determined.
  • each layer in the figure is enlarged to clearly illustrate the relative position between the layers.
  • the expression includes not only the case where it is “directly” above the other part, but also the case where there are other layers in between.
  • the embodiment of the present disclosure provides a display device.
  • the display device is, for example, a mobile phone, a tablet, a computer, a smart wearable product (for example, a smart watch, a smart bracelet), a portable electronic device, a virtual reality (Virtual Reality, VR) terminal, and augmented reality (Augmented Reality, AR) terminal, etc.
  • VR Virtual Reality
  • AR Augmented Reality
  • the display device 01 takes the display device 01 as a mobile phone as shown in FIG. 1 as an example.
  • the display device 01 at least includes a housing 11 and a display substrate 10 installed in the housing 11.
  • the housing 11 is usually provided with a receiving cavity (not shown in FIG. 1) capable of accommodating a printed circuit board (PCB), a battery, a camera, and other components.
  • PCB printed circuit board
  • FIG. 2A is an enlarged schematic view of the display substrate 10 in FIG. 1 in the M0 area.
  • FIG. 2B is a schematic diagram of the structure of a sub-pixel group in the display substrate 10. 2A and 2B, taking the display substrate 10 as an AMOLED display substrate as an example for description, but it is not limited to this.
  • the display substrate 10 includes a base substrate 100 and a plurality of sub-pixel groups 200 located on the base substrate 100.
  • Each sub-pixel group may be composed of a plurality of sub-pixels, and each sub-pixel includes a pixel electrode and an effective light-emitting area.
  • each sub-pixel group 200 includes one first-color sub-pixel 210, one second-color sub-pixel pair 220, and one third-color sub-pixel 230 arranged in a first direction (the X direction shown in the figure).
  • the second color sub-pixel pair 220 includes a first sub-pixel 22-1 and a second sub-pixel 22-2 that are arranged in a second direction (the Z direction shown in the figure) and emit light in the same color.
  • the effective light-emitting area of the first color sub-pixel 210 is the first effective light-emitting area 2100.
  • the effective light-emitting area of the first sub-pixel 22-1 is the first sub-effective light-emitting area 2201
  • the effective light-emitting area of the second sub-pixel 22-2 is the second sub-effective light-emitting area 2202.
  • the effective light-emitting area of the third color sub-pixel 230 is the third effective light-emitting area 2300.
  • the pixel electrode of the aforementioned sub-pixel includes an interconnected main body portion and a connection portion.
  • the pixel electrode 211 of the first color sub-pixel 210 includes an interconnected body portion 2111 and a connecting portion 2112;
  • the pixel electrode 221- of the first sub-pixel 22-1 in the second color sub-pixel pair 220 1 includes an interconnected main body portion 221-11 and a connection portion 221-12;
  • the pixel electrode 221-2 of the second sub-pixel 22-2 in the second color sub-pixel pair 220 includes an interconnected main body portion 221-21 and a connection Section 221-22;
  • the pixel electrode 231 of the third color sub-pixel 230 includes a main body portion 2311 and a connecting portion 2312 that are interconnected.
  • the main body of each pixel electrode and the effective light-emitting area of the sub-pixel to which it belongs are roughly the same in shape, and the main body overlaps at least part of the boundary of the pixel electrode.
  • the multiple sub-pixels on the base substrate 100 at least include a first sub-pixel 22-1 and a second sub-pixel 22-2 with the same light-emitting color. .
  • the areas of the orthographic projection of the two pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 on the base substrate 100 are different.
  • the two orthographic projections of the connecting portion and the main body portion of at least one of the first sub-pixel 22-1 and the second sub-pixel 22-2 on a straight line extending in the first direction (for example, the X direction) are at least partially disjoint Stacked.
  • the orthographic projection of the pixel electrode of the second sub-pixel 22-2 on a straight line extending in the second direction is located within the orthographic projection of the pixel electrode of the first sub-pixel 22-1 on the same straight line.
  • the second direction intersects the first direction, and the value range of the angle between the two is 80°-100°.
  • a plurality of sub-pixels with the same light-emitting color adopts two different structures as shown in the first sub-pixel 22-1 and the second sub-pixel 22-2.
  • the first sub-pixel 22-1 and the second sub-pixel 22-2 can be designed.
  • the shape of the pixel electrode in the second sub-pixel 22-2 effectively simplifies the overall layout design of the pixel circuit in the display substrate 10 on the basis of increasing the distribution density of the sub-pixels, so as to increase the light transmittance of the display substrate 10.
  • the display substrate 10 adopts the structure shown in FIG. 2A as an example for detailed description.
  • a plurality of sub-pixel groups 200 are arranged along a first direction (for example, the X direction) to form a sub-pixel row.
  • the plurality of sub-pixel rows are arranged in the second direction (for example, the Z direction), and any two adjacent sub-pixel groups in the plurality of sub-pixel rows are misaligned in the first direction, that is, any two adjacent sub-pixel rows have a certain offset along the first direction. Shift. Therefore, in any two adjacent sub-pixel rows, the sub-pixels configured to emit light of the same color are not aligned in the second direction.
  • the sub-pixel groups located in odd-numbered rows are arranged in the same manner, and the sub-pixel groups located in even-numbered rows are arranged in the same manner.
  • the offset of two adjacent sub-pixel rows in the first direction is approximately half of the size of the sub-pixel group 200 in the first direction.
  • the size of the sub-pixel group 200 in the first direction is the pitch of the sub-pixel group 200 in the first direction.
  • the pitch here refers to the distance between the centers of the effective light-emitting regions of two first-color sub-pixels 210 in two adjacent sub-pixel groups 200 in the first direction.
  • the center of the effective light-emitting area refers to the geometric center of its orthographic projection shape on the base substrate.
  • the shape of the orthographic projection of the effective light-emitting area on the base substrate 100 is roughly a regular pattern, such as a symmetrical pattern.
  • the center involved in some embodiments of the present disclosure refers to its geometric center for a regular shape; for an irregular shape it refers to its approximate geometric center, for example, it is simulated to be more similar to the irregular shape High regular shape, and then the geometric center of the simulated shape as the center of the irregular shape.
  • the first direction and the second direction intersect, and the included angle may range from 80° to 100°.
  • the first direction and the second direction are respectively two directions perpendicular to each other in the same plane.
  • the plane is a plane where the sub-pixels are arranged, that is, a plane parallel to the base substrate 100.
  • the above-mentioned sub-pixel group serves as a repeating unit, and its repetition only refers to the repetition of the arrangement of the sub-pixels, and other structures may be different or the same.
  • the repetition means that the approximate position, shape, and size are about the same.
  • the shape may be slightly different, such as openings in different positions.
  • the first color sub-pixel 210 is the red sub-pixel R.
  • the first subpixel 22-1 and the second subpixel 22-2 in the second color subpixel pair 220 correspond to green subpixels G1 and G2.
  • the third color sub-pixel 230 is the blue sub-pixel B. But it is not limited to this, and the color of each color sub-pixel can be interchanged.
  • each sub-pixel includes a light-emitting device 0220 and a pixel circuit 0221 coupled to the light-emitting device 0220.
  • the pixel circuit 0221 can drive the light emitting device 0220 to emit light.
  • the light-emitting device 0220 generally includes an anode, a light-emitting layer, and a cathode that are sequentially stacked.
  • the electrode coupled to the pixel circuit 0221 in the light-emitting device 0220 appears as a pixel electrode of a corresponding sub-pixel, and the electrode is, for example, an anode.
  • the pixel electrode is an anode as an example for description.
  • the pixel circuit 0221 includes a driving circuit 0222, a first light emission control circuit 0223, a second light emission control circuit 0224, a data writing circuit 0225, a storage circuit 0226, a threshold compensation circuit 0227, and a reset circuit 0228.
  • the driving circuit 0222 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current for driving the light-emitting device 0220 to emit light.
  • the first light emission control circuit 0223 is respectively coupled to the first voltage terminal VDD and the first terminal of the driving circuit 0222, and is configured to realize the on or off of the connection between the driving circuit 0222 and the first voltage terminal VDD.
  • the second light emitting control circuit 0224 is respectively coupled to the second end of the driving circuit 0222 and the anode of the light emitting device 0220, and is configured to realize the connection between the driving circuit 0222 and the light emitting device 0220 to be turned on or off.
  • the data writing circuit 0225 is coupled to the first end of the driving circuit 0222, and is configured to write the data signal into the storage circuit 0226 under the control of the gate scan signal.
  • the storage circuit 0226 is respectively coupled to the control terminal of the driving circuit 0222 and the first voltage terminal VDD, and is configured to store data signals.
  • the threshold compensation circuit 0227 is respectively coupled to the control terminal of the driving circuit 0222 and the second terminal of the driving circuit 0222, and is configured to perform threshold compensation on the driving circuit 0222.
  • the reset circuit 0228 is coupled to the control terminal of the driving circuit 0222 and the anode of the light emitting device 0220, and is configured to reset the control terminal of the driving circuit 0222 and the anode of the light emitting device 0220 under the control of the reset control signal.
  • the driving circuit 0222 includes a driving transistor T1.
  • the control terminal of the driving circuit 0222 is the control terminal of the driving transistor T1
  • the first terminal of the driving circuit 0222 is the first terminal of the driving transistor T1
  • the second terminal of the driving circuit 0222 is the second terminal of the driving transistor T1.
  • the data writing circuit 0225 includes a data writing transistor T2.
  • the storage circuit 0226 includes a capacitor C.
  • the threshold compensation circuit 0227 includes a compensation transistor T3.
  • the first light emission control circuit 0223 includes a first light emission control transistor T4.
  • the second light emission control circuit 0224 includes a second light emission control transistor T5.
  • the reset circuit 0228 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.
  • the first pole of the data writing transistor T2 is coupled to the first pole of the driving transistor T1, the second pole of the data writing transistor T2 is configured to be coupled to the data line Vd to receive a data signal, and the data writing transistor T2 is controlled
  • the pole is configured to be coupled to the first gate scan signal line Ga1 to receive a scan signal.
  • the first electrode of the capacitor C is coupled to the first voltage terminal VDD, and the second electrode of the capacitor C is coupled to the control electrode of the driving transistor T1.
  • the first electrode of the compensation transistor T3 is coupled to the second electrode of the driving transistor T1, the second electrode of the compensation transistor T3 is coupled to the control electrode of the driving transistor T1, and the control electrode of the compensation transistor T3 is configured to communicate with the second gate scanning signal
  • the line Ga2 is coupled to receive the compensation control signal.
  • the first electrode of the first reset transistor T6 is configured to be coupled to the first reset power terminal Vinit1 to receive the first reset signal
  • the second electrode of the first reset transistor T6 is coupled to the control electrode of the driving transistor T1
  • the first reset The control electrode of the transistor T6 is configured to be coupled to the first reset control signal line Rst1 to receive the first sub-reset control signal.
  • the first electrode of the second reset transistor T7 is configured to be coupled to the second reset power terminal Vinit2 to receive the second reset signal
  • the second electrode of the second reset transistor T7 is coupled to the first electrode of the light emitting device 0220
  • the control electrode of the reset transistor T7 is configured to be coupled to the second reset control signal line Rst2 to receive the second sub-reset control signal.
  • the first electrode of the first light emission control transistor T4 is coupled to the first voltage terminal VDD
  • the second electrode of the first light emission control transistor T4 is coupled to the first electrode of the driving transistor T1
  • the control electrode of the first light emission control transistor T4 is It is configured to be coupled to the first light emission control signal line EM1 to receive the first light emission control signal.
  • the first electrode of the second light-emission control transistor T5 is coupled to the second electrode of the driving transistor T1
  • the second electrode of the second light-emission control transistor T5 is coupled to the anode of the light-emitting device 0220
  • the control electrode of the second light-emission control transistor T5 is It is configured to be coupled to the second light emission control signal line EM2 to receive the second light emission control signal.
  • the cathode of the light emitting device 0220 is coupled to the second voltage terminal VSS.
  • one of the first voltage terminal VDD and the second voltage terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first voltage terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second voltage terminal VSS is a voltage source to output a constant second voltage
  • the second voltage is a negative voltage or the like.
  • the first voltage terminal VDD is a power signal line
  • the power signal line is, for example, a first power signal line and a second power signal line that are located in different layers and are interconnected.
  • the second voltage terminal VSS is grounded.
  • the scan signal and the compensation control signal may be the same.
  • control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 are coupled to the same signal line, such as the first gate scan signal line Ga1, to receive the same signal (eg, scan signal).
  • the second gate scanning signal line Ga2 may not be provided in the display substrate to reduce the total number of signal lines.
  • control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 are respectively coupled to different signal lines, that is, the control electrode of the data writing transistor T2 is coupled to the first gate scanning signal line Ga1, and the compensation transistor The control electrode of T3 is coupled to the second gate scanning signal line Ga2, and the first gate scanning signal line Ga1 and the second gate scanning signal line Ga2 both transmit the same signal.
  • the scan signal and the compensation control signal are different, so that the control electrode of the data writing transistor T2 and the control electrode of the compensation transistor T3 can be controlled separately, thereby increasing the control flexibility of the pixel circuit.
  • the first lighting control signal and the second lighting control signal are the same.
  • control electrode of the first light emission control transistor T4 and the control electrode of the second light emission control transistor T5 are coupled to the same signal line, such as the first light emission control signal line EM1, to receive the same signal (for example, the first light emission control signal line EM1). Luminous control signal).
  • the second light emission control signal line EM2 may not be provided in the display substrate to reduce the total number of signal lines.
  • control electrode of the first light-emission control transistor T4 and the control electrode of the second light-emission control transistor T5 are respectively coupled to different signal lines.
  • the control electrode of the first light emission control transistor T4 is coupled to the first light emission control signal line EM1
  • the control electrode of the second light emission control transistor T5 is coupled to the second light emission control signal line EM2
  • the first light emission control signal line EM1 and the second light emission control signal line EM2 The light emission control signal line EM2 transmits the same signal.
  • the first light-emission control transistor T4 and the second light-emission control transistor T5 are different types of transistors.
  • the first light-emission control transistor T4 is a P-type transistor
  • the second light-emission control transistor T5 is an N-type transistor.
  • the first light-emitting control signal and the second light-emitting control signal are different, which is not limited in the embodiment of the present disclosure.
  • the first sub-reset control signal and the second sub-reset control signal are the same.
  • control electrode of the first reset transistor T6 and the control electrode of the second reset transistor T7 are coupled to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (for example, the first sub-reset control signal).
  • the second reset control signal line Rst2 may not be provided in the display substrate to reduce the total number of signal lines.
  • control electrode of the first reset transistor T6 and the control electrode of the second reset transistor T7 are respectively coupled to different signal lines.
  • the control electrode of the first reset transistor T6 is coupled to the first reset control signal line Rst1
  • the control electrode of the second reset transistor T7 is coupled to the second reset control signal line Rst2
  • the signal line Rst2 transmits the same signal.
  • the first sub-reset control signal and the second sub-reset control signal may also be different.
  • the second sub-reset control signal may be the same as the scan signal.
  • the control electrode of the second reset transistor T7 may be coupled to the first gate scan signal line Ga1 to receive the scan signal Ga1 as the second sub-reset control signal.
  • the first reset power terminal Vinit1 coupled to the first pole of the first reset transistor T6 and the second reset power terminal Vinit2 coupled to the first pole of the second reset transistor T7 may be a DC reference voltage terminal to output Constant DC reference voltage.
  • the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same.
  • the first pole of the first reset transistor T6 and the first pole of the second reset transistor T7 are connected to the same reset power terminal.
  • the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide a first reset signal and a second reset signal to control the control electrode of the driving transistor T1 and the light emitting device 0220.
  • the anode can be reset, which is not limited in the embodiment of the present disclosure.
  • the first pole of the first reset transistor T6 and the first pole of the second reset transistor T7 may be connected to the reset power signal line Init, respectively.
  • the specific structures of the circuit 0225, the storage circuit 0226, the threshold compensation circuit 0227, and the reset circuit 0228 can be set according to actual application requirements, which are not specifically limited in the embodiment of the present disclosure.
  • transistors can be classified into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure describe the technical solutions of the present disclosure in detail by taking the transistor as a P-type transistor (for example, a P-type MOS transistor) as an example. That is, in the description of the embodiments of the present disclosure, the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset The transistor T7 etc. may all be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.
  • N-type transistors for example, N-type MOS transistors
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the first pole and the second pole of the transistor can be symmetrical in structure, so the first pole and the second pole can be indistinguishable in physical structure.
  • the gate of the transistor is its control electrode
  • the first electrode is one of the source or the drain
  • the second electrode is the other of the source or the drain.
  • the first pole and the second pole of all or part of the transistors can be interchanged as required.
  • the pixel circuit 0221 may be a structure including other numbers of transistors, in addition to the 7T1C (that is, seven transistors and one capacitor) structure shown in FIG. 3, such as 7T2C.
  • the structure, the 6T1C structure, the 6T2C structure, or the 9T2C structure is not limited in the embodiment of the present disclosure.
  • the pixel electrode of the light-emitting device 0220 is coupled to the pixel circuit 0221, and its shape can be designed according to actual needs, so as to optimize the wiring design of the pixel circuit 0221 and ensure that each sub-pixel has a higher distribution density, thereby improving the display of the display device. Effect.
  • the pixel electrode in at least two sub-pixels of the sub-pixel group 200, for example, the first sub-pixel 22-1 and the second sub-pixel 22- in the second color sub-pixel pair 220 In 2, the pixel electrode includes an interconnected main body part and a connection part.
  • the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second-color sub-pixel pair 220 are: the first sub-pixel 22-1 and the second sub-pixel 22-2 that are closest to each other.
  • a sub-pixel 22-1 and a second sub-pixel 22-2, and the first sub-pixel 22-1 and the second sub-pixel 22-2 are arranged along the second direction.
  • the shape of the aforementioned main body is approximately the same as the shape of the effective light-emitting area of the light emitting device 0220 where it is located.
  • Part of the edge of the main body is the corresponding edge of the pixel electrode, that is, the main body coincides with part of the boundary of the pixel electrode.
  • a notch is provided at the part where the connecting part connects with the main body part.
  • the main body portion includes a first side, a second side, and a third side that are sequentially connected, wherein the third side extends along the second direction; the second side is connected to the connecting portion, and the first side and the connecting portion are spaced apart, That is, the first side is not connected to the connecting part.
  • the area enclosed by the main body and the connecting portion is the notch.
  • the area is the notch area.
  • the first side, the second side, and the third side can be straight sides or folded sides; it is distinguished by whether they are connected to the connecting portion.
  • the pixel electrode of each sub-pixel in FIG. 2B has the same structure as the pixel electrode of the same-color sub-pixel in FIG. 4, but its shape is slightly different.
  • the shape of the connecting portion of each pixel electrode in FIG. 2B is relatively regular; the shape of the connecting portion of each pixel electrode in FIG. 4 has a larger curvature.
  • the embodiment of the present disclosure does not limit this.
  • the pixel electrode 221-1 of the first sub-pixel 22-1 includes a main body portion 221-11 and a connecting portion 221-12.
  • the connecting portion 221-12 includes a bending portion 2-1 connected to the main body portion 221-11, and a compensating portion 2-2 connected to the bending portion 2-1.
  • the main body part 221-11, the bending part 2-1 and the compensation part 2-2 are an integral structure.
  • the compensation portion 2-2 extends in the second direction.
  • the maximum dimension D2max of the compensation portion 2-2 in the first direction is greater than the maximum dimension D1max of the curved portion 2-1 in the first direction.
  • the curved portion 2-1 is located between the main body portion 221-11 and the compensating portion 2-2, and the transition point interconnected with the main body portion 221-11 and the compensating portion 2-2 can be smoothly processed.
  • the maximum dimension of the bent portion 2-1 in the first direction is its cross-sectional dimension in the first direction. In this way, the curved portion 2-1 may have a smaller line width than the compensation portion 2-2.
  • the main body portion 221-11 includes a first side a2-1, a second side b2-1, and a third side c2-1 that are sequentially connected.
  • the third side c2-1 extends along the Z direction
  • the second side b2-1 is connected to the curved portion 2-1 in the connecting portion 221-12, and there is a space between the first side a2-1 and the connecting portion 221-12.
  • the connecting line from any point on the first side a2-1 to any point on the edge of the connecting portion 221-12 extending in the Z direction and away from the third side c2-1 in the X direction is connected to the main body portion 221-11 and
  • the area enclosed by the portion 221-12 is the notch area 221-13.
  • the connecting portion 221-12 extends along the Z direction and is away from any point on the edge of the third side c2-1 in the X direction, for example, the curved portion 2-1 is connected to the compensation portion 2-2 and is in the X direction.
  • the line width of the above-mentioned curved portion 2-1 is small, which helps to ensure that the orthographic projection area of the notch area 221-13 on the base substrate 100 is large.
  • the ratio of the orthographic projection area of the notch area 221-13 on the base substrate 100 to the orthographic projection area of the curved portion 2-1 on the base substrate 100 may range from 0.2 to 5.
  • the ratio of the orthographic projection area of the notch area 221-13 on the base substrate 100 to the orthographic projection area of the curved portion 2-1 on the base substrate 100 is one of 0.2, 1.5, 3, and 5. In this way, providing the notch area 221-13 with a larger area in the first sub-pixel 22-1 can avoid disposing a metal pattern in the notch area 221-13, thereby better improving the light transmittance of the display substrate 10.
  • the pixel electrode 221-2 of the second sub-pixel 22-2 and the pixel electrode 221-1 of the first sub-pixel 22-1 have different orthographic projection areas on the base substrate 100, and the corresponding structures of the two are different.
  • two orthographic projections of the connecting portion and the main body portion of at least one of the first sub-pixel 22-1 and the second sub-pixel 22-2 on a straight line extending in the first direction do not at least partially overlap.
  • the pixel electrode 221-2 of the second sub-pixel 22-2 includes a main body portion 221-21 and a connecting portion 221-22.
  • the main body part 221-21 and the connecting part 221-22 are an integral structure.
  • the main body 221-21 includes a first side a2-2, a second side b2-2, and a third side c2-2 that are sequentially connected, wherein the third side c2-2 extends along the Z direction, and the second side b2-2 It is connected to the connecting portion 221-22, and there is an interval between the first side a2-2 and the connecting portion 221-22.
  • At least one side edge of the connecting portion 221-22 may be bent, for example, the edge of the connecting portion 221-22 away from the third side c2-2 in the X direction is bent.
  • the part 221-21 and the connecting part 221-22 enclose a notch area 221-23.
  • disposing the notch area 221-23 in the second sub-pixel 22-2 can avoid disposing a metal pattern in the notch area 221-23, thereby further improving the light transmittance of the display substrate 10.
  • the maximum size of the connecting portion 221-22 of the pixel electrode 221-2 in the second sub-pixel 22-2 in the second direction is smaller than or equal to the first sub-pixel 22-
  • the maximum size of the bent portion 2-1 of the pixel electrode 221-1 in 1 in the second direction are substantially the same.
  • the size of the pixel electrode 221-2 in the second sub-pixel 22-2 in the second direction is smaller than the size of the pixel electrode 221-1 in the first sub-pixel 22-1 in the same direction.
  • the second color sub-pixel pair 220 of the second row R2 is the same as the second color sub-pixel pair 220 of the first row R1.
  • the two-color sub-pixel pair 220 is misaligned along the first direction (for example, the X direction).
  • the connecting portion 221-12 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second-color sub-pixel pair 220 in the second row R2 extends to the corresponding phase in the second-color sub-pixel pair 220 in the first row R1. Between the pixel electrodes 221-2 of two adjacent second sub-pixels 22-2.
  • the curved portion 2-1 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second-color sub-pixel pair 220 in the second row R2 and the second-color sub-pixel pair 220 in the second-color sub-pixel pair 220 in the first row R1 The connecting portion 221-22 of the pixel electrode 221-2 of the sub-pixel 22-2 is substantially located on a straight line extending in the first direction.
  • the compensation portion 2-2 of the pixel electrode 221-1 of the first sub-pixel 22-1 in the second color sub-pixel pair 220 in the second row R2 is located in the corresponding adjacent second color sub-pixel pair 220 in the first row R1 Between the main body portions 221-21 of the pixel electrodes 221-2 of the two second sub-pixels 22-2.
  • the orthographic projection of the pixel electrode 221-2 of the second sub-pixel 22-2 in the second-color sub-pixel pair 220 in the first row R1 on a straight line extending in the second direction is located in the second row R2.
  • the pixel electrode 221-1 of the first sub-pixel 22-1 in the color sub-pixel pair 220 is in an orthographic projection on the same straight line.
  • the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 adopt the above-mentioned design, which is beneficial to the first sub-pixel group 200 in the space corresponding to the first sub-pixel group 200.
  • Four pixel circuits 0221 are arranged in parallel in the direction. Therefore, on the basis of increasing the distribution density of sub-pixels, the overall layout design of the pixel circuit 0221 in the display substrate 10 can be simplified.
  • the pixel electrode 211 of the first color sub-pixel 210 and the pixel electrode 231 of the third color sub-pixel 230 may also refer to the structure design of the pixel electrode 221-2 in the second sub-pixel 22-2.
  • the pixel electrode 211 of the first color sub-pixel 210 includes a main body portion 2111 and a connecting portion 2112 that are interconnected.
  • the main body 2111 and the connecting part 2112 are an integral structure.
  • the main body 2111 includes a first side a1-1, a second side b1-1, and a third side c1-1 that are sequentially connected, wherein the third side c1-1 extends along the Z direction, and the second side b1-1 is connected to The portion 2112 is connected, and there is a gap between the first side a1-1 and the connecting portion 2112.
  • At least one side edge of the connecting portion 2112 may be bent, for example, the edge of the connecting portion 2112 away from the third side c1-1 in the X direction may be bent.
  • a connecting line from any point on the first side a1-1 of the main body 2111 to any point on the edge of the connecting portion 2112 extending in the Z direction and away from the third side c1-1 in the X direction, connected to the main body 2111 The part 2112 encloses a notch area 2113.
  • the pixel electrode 231 of the third color sub-pixel 230 includes a main body portion 2311 and a connecting portion 2312 that are interconnected.
  • the main body portion 2311 and the connecting portion 2312 are an integral structure.
  • the main body 2311 includes a first side a3-1, a second side b3-1, and a third side c3-1 that are sequentially connected, wherein the third side c3-1 extends along the Z direction, and the second side b3-1 is connected to the The portion 2312 is connected, and there is an interval between the first side a3-1 and the connecting portion 2312.
  • the edge of at least one side of the connecting portion 2312 may be bent, for example, the edge of the connecting portion 2312 away from the third side c3-1 in the X direction is bent.
  • the connecting line from any point on the first side b3-1 of the main body portion 2311 to any point on the edge of the connecting portion 2312 extending in the Z direction and away from the third side c1-1 in the X direction, connected to the main body portion 2311 The portion 2312 encloses a notch area 2313.
  • the notch area 2113 is provided in the first color sub-pixel 210 and the notch area 2313 is provided in the third color sub-pixel 230, which can further increase the light transmittance of the display substrate 10.
  • the connecting portion 2112 in the first color sub-pixel 210 is located on the side of the main body 2111 close to the second color sub-pixel pair 220.
  • the areas of the anodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are different.
  • the connecting portions 221-12 and 221-22 of the second color sub-pixel pair 220 are respectively located on the side of the main body part away from the first color sub-pixel 210.
  • the projection of the connection portion and the main body portion of at least one of the first sub-pixel 22-1 and the second sub-pixel 22-2 on a straight line extending in the first direction does not overlap at least partially.
  • the orthographic projection of the connecting portion 2312 in the third color sub-pixel 230 on a straight line extending in the first direction is within the orthographic projection of the main body portion 2311 on the same straight line.
  • the center line of the third effective light-emitting area 2300 of the third color sub-pixel 230 in the second direction passes through the main body portion 2311 and the connecting portion 2312 thereof.
  • each sub-pixel group 200 the shape of the main body of the pixel electrode of each sub-pixel is approximately the same as the shape of the corresponding effective light-emitting area, and the orthographic projection area of the main body of the pixel electrode of each sub-pixel on the base substrate 100 is larger than that of the corresponding The orthographic projection area of the effective light-emitting area on the base substrate 100.
  • the geometric center of the main body of the pixel electrode of each sub-pixel roughly coincides with the geometric center of the corresponding effective light-emitting area.
  • the main body portion 2111 of the pixel electrode 211 of the first color sub-pixel 210 and the main body portion 2311 of the pixel electrode 231 of the third color sub-pixel 230 are approximately hexagonal or elliptical in shape, and in the second color sub-pixel pair 220
  • the shapes of the main body portions of the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 are approximately pentagonal, circular, or drop-shaped.
  • the plurality of pixel circuits 0221 are arranged in a first direction to form a row, and arranged in a second direction to form a column.
  • Each transistor in the pixel circuit 0221 adopts a top gate structure, and some of the transistors may also have a double gate structure, such as the compensation transistor T3 and the first reset transistor T6. But it is not limited to this.
  • the structure of each layer in the display substrate 10 will be schematically described. In the case that the transistor adopts other structures, the structure of each layer in the display substrate 10 can be adjusted accordingly.
  • FIG. 5 is a schematic diagram of a top view structure of a plurality of sub-pixels in some embodiments of the present disclosure.
  • 6A to 6I are schematic diagrams of partial layer top view structures in the sub-pixel fabrication process, in which the first color sub-pixel 210, the second sub-pixel 22-2 and the third-color sub-pixel 230 in the second color sub-pixel pair 220 And four adjacent pixel circuits corresponding to the first sub-pixel 22-1 in another second-color sub-pixel pair 220 that are adjacent and staggered. The positions are illustrated, and the positions of the components included in the pixel circuit 0221 in the other sub-pixels and the transistors included in the sub-pixel are approximately the same.
  • the display substrate 10 generally includes a plurality of layers between the base substrate 100 and the pixel electrode, and the plurality of layers includes at least one metal layer and at least one insulating layer. Please understand the structure of each layer in the display substrate 10 in conjunction with the layers shown in FIGS. 7A to 7G.
  • the embodiment of the present disclosure illustrates the layer structure of a display substrate 10 in cross section, but is not limited to this. According to different pixel circuit structures, the layer structure of the display substrate 10 can also be adaptively modified.
  • the pixel circuit 0221 includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first light-emission control transistor T4, a second light-emission control transistor T5, a first reset transistor T6, and a Two reset transistor T7 and capacitor C; wherein, the position of the capacitor C and the driving transistor T1 overlaps, which is not marked to indicate.
  • FIG. 6A shows a top view structure of a semiconductor pattern layer 310 in the display substrate 10.
  • the semiconductor pattern layer 310 may be formed by patterning a semiconductor material.
  • the semiconductor pattern layer 310 can be used to make the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7.
  • the semiconductor pattern layer 310 includes the active layer pattern (channel region) and doped region pattern (source and drain doped region) of each transistor of each sub-pixel, and the active layer pattern and doping of each transistor in the same pixel circuit The area pattern is set in one piece.
  • the active layer may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region can be obtained by conducting doping or the like.
  • the active layer of each transistor of each sub-pixel is an overall pattern formed of p-silicon.
  • Each transistor in the same pixel circuit includes a doped region pattern (that is, a source region and a drain region) and an active layer pattern, and the active layers of different transistors are separated by the doped structure.
  • the semiconductor pattern layer 310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, and the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active semiconductor layers in the pixel circuits of the sub-pixels of different colors arranged in the first direction have no connection relationship and are disconnected from each other.
  • the active semiconductor layers in the pixel circuits of the sub-pixels arranged in the second direction may be integrally provided, or may be disconnected from each other.
  • FIG. 6B shows a top view structure of a first gate metal layer 320 in the display substrate 10.
  • the first gate metal layer 320 is a patterned metal film.
  • a gate insulating layer 160 is formed on the semiconductor pattern layer 310.
  • the first gate metal layer 320 is located on the gate insulating layer 160 and insulated from the semiconductor pattern layer 310.
  • the first gate metal layer 320 is used to make the aforementioned driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second The gate of each transistor of the reset transistor T7 and the first pole CC1 of the capacitor C are reset.
  • the scan signal line Ga (including the first gate scan signal line Ga1 and the second gate scan signal line Ga2) coupled to the gate of each transistor in the pixel circuit 0221, the reset control signal line Rst (including the first reset control The signal line Rst1 and the second reset control signal line Rst2), the light-emission control signal line EM (including the first light-emission control signal line EM1 and the second light-emission control signal line EM2) and other signal lines may also be formed by the first gate metal layer 320 Production formation.
  • the first gate scan signal line Ga1 and the second gate scan signal line Ga2 are the same signal line Ga, and the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same signal line Rst.
  • the one light emission control signal line EM1 and the second light emission control signal line EM2 are the same signal line EM, but are not limited thereto.
  • the display substrate 10 further includes: a plurality of signal lines extending along the first direction.
  • the orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 on the base substrate overlaps the orthographic projection of the at least three signal lines in the same layer on the base substrate 100.
  • the reset control signal line, the gate scan signal line, and the light emission control signal line are arranged in the same layer, and all three extend in the first direction and are arranged in the second direction.
  • the orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 on the base substrate overlaps the orthographic projection of a reset control signal line, a gate scan signal line, and a light emission control signal line on the base substrate 100 .
  • the gate of the data writing transistor T2 may be a portion where the scan signal line Ga overlaps the semiconductor pattern layer 310.
  • the gate of the first light emission control transistor T4 may be the first part where the light emission control signal line EM overlaps the semiconductor pattern layer 310
  • the gate of the second light emission control transistor T5 may be the light emission control signal line EM overlaps the semiconductor pattern layer 310 The second part.
  • the gate of the first reset transistor T6 is the first part where the reset control signal line Rst overlaps with the semiconductor pattern layer 310.
  • the gate of the second reset transistor T7 is the second part where the reset control signal line Rst overlaps with the semiconductor pattern layer 310.
  • the threshold compensation transistor T3 may be a thin film transistor with a double-gate structure, the first gate of the threshold compensation transistor T3 may be the part where the scan signal line Ga overlaps the semiconductor pattern layer 310, and the second gate of the threshold compensation transistor T3 may be It is a portion where the protruding structure P protruding from the scanning signal line Ga overlaps with the semiconductor pattern layer 310. It can be understood with reference to FIG. 3 that the gate of the driving transistor T1 may be the first electrode CC1 of the capacitor C.
  • the portion of the semiconductor pattern layer 310 that is directly opposite to the gate of the transistor is the channel of the transistor, and the semiconductor pattern portions on both sides of each channel are conductive through processes such as ion doping, and can be used as corresponding transistors.
  • the first pole and the second pole are conductive through processes such as ion doping, and can be used as corresponding transistors.
  • the scan signal line Ga, the reset control signal line Rst, and the light emission control signal line EM are arranged in the first direction (X direction).
  • the scanning signal line Ga is located between the reset control signal line Rst and the light emission control signal line EM.
  • the first pole CC1 of the capacitor C that is, the gate of the driving transistor T1 is located between the scanning signal line Ga and the light emission control signal line EM.
  • the protruding structure P protruding from the scanning signal line Ga is located on the side of the scanning signal line Ga away from the light emission control signal line EM.
  • the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all located on the first side of the gate of the driving transistor T1.
  • the gate of the first light emission control transistor T4 and the gate of the second light emission control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the first side and the second side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the second direction.
  • the first side of the gate of the driving transistor T1 may be the upper side of the gate of the driving transistor T1
  • the second side of the gate of the driving transistor T1 may be the lower side of the gate of the driving transistor T1 .
  • the side of the display substrate for bonding the IC is the lower side of the display substrate
  • the lower side of the gate of the driving transistor T1 is the side closer to the IC.
  • the upper side of the gate of the driving transistor T1 is the opposite side to the lower side thereof, for example, the gate of the driving transistor T1 is the side farther from the IC.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the threshold value compensation transistor T3 is One gate, the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the first direction X.
  • the third side of the gate of the driving transistor T1 may be the left side of the gate of the driving transistor T1
  • the fourth side of the gate of the driving transistor T1 may be the left side of the gate of the driving transistor T1.
  • the right side of the gate is
  • the structure of the pixel circuit 0221 may be a mirror image structure of the structure shown in FIG. 6B, that is, each layer structure of the pixel circuit 0221 is based on the channel region of the driving transistor T1, and the left and right sides of the structure are reversed. Therefore, the relationship between the left side and the right side of the aforementioned gate may be reversed.
  • FIG. 6C shows a top view structure of a second gate metal layer 330 in the display substrate 10.
  • the second gate metal layer 330 is a patterned metal film.
  • a first interlayer insulating layer 150 is formed on the aforementioned first gate metal layer 320.
  • the second gate metal layer 330 is located on the first interlayer insulating layer 150 and insulated from the first gate metal layer 320.
  • the second gate metal layer 330 is used to fabricate the second pole CC2 of the capacitor C, the reset power signal line Init, and the light shielding portion S.
  • the orthographic projection of the second pole CC2 of the capacitor C and the first pole CC1 of the capacitor C on the base substrate 100 at least partially overlap to form the capacitor C.
  • the second pole CC2 of the capacitor C is provided with an opening, and the orthographic projection of the opening on the base substrate 100 is located within the orthographic projection of the first pole CC1 of the capacitor C on the base substrate 100;
  • the orthographic projection of the part other than the opening in the diode CC2 on the base substrate 100 overlaps with the orthographic projection of the first pole CC1 of the capacitor C on the base substrate 100.
  • the second electrode CC2 of the capacitor C is made of the second gate metal layer 330.
  • interconnecting the second pole CC2 of each capacitor C can reduce the resistance of the corresponding metal connection in the second gate metal layer 330, thereby reducing the voltage drop of the power supply voltage ( IR DROP).
  • the compensation transistor T3 adopts a double-gate transistor, and the semiconductor pattern part between the two channels of the compensation transistor T3 is in a floating state when the compensation transistor T3 is turned off, and is susceptible to jump due to the influence of the surrounding line voltage. Change, which will affect the leakage current of the compensation transistor T3, and then affect the light-emitting brightness.
  • the light shielding part S and the semiconductor pattern part located between the two channels of the compensation transistor T3 are designed to form a capacitor, and the light shielding part S is connected to the first
  • the second power signal line can obtain a constant voltage, so as to ensure that the voltage of the semiconductor pattern part in the floating state can be kept stable.
  • the orthographic projection of the light shielding portion S on the base substrate 100 overlaps with the orthographic projection of the semiconductor pattern part located between the two channels of the compensation transistor T3 on the base substrate 100, which can also prevent the semiconductor pattern part from being damaged by light. There is a problem of changes in electrical characteristics.
  • the second interlayer insulating layer 140 and the first metal layer are sequentially stacked and formed on the second gate metal layer 330 in a direction away from the base substrate 100.
  • FIG. 6D shows a top view structure of a first metal layer 340 in the display substrate 10.
  • FIG. 6E shows the distribution of a plurality of via holes required for electrical connection between the first metal layer 340 and the semiconductor pattern layer 310, the first gate metal layer 320, and the second gate metal layer 330.
  • FIG. 6E' shows the relative position between the first metal layer 340 and each via hole in FIG. 6E.
  • the first metal layer 340 is a patterned metal film.
  • the first metal layer 340 can be used to fabricate the data line Vd, the second power signal line 500, the first transfer electrode 341, the second transfer electrode 342, and the driving electrode 343.
  • the data line Vd and the second power signal line 500 both extend in the second direction, and there is an interval between the data line Vd and the second power signal line 500 corresponding to the same pixel circuit 0221.
  • the data line Vd passes through the through hole 381 passing through the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 and the data writing transistor
  • the second pole T2-2 of T2 is electrically connected.
  • the second power signal line 500 is electrically connected to the first electrode T4-1 of the first light-emitting control transistor T4 through a via 382 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 .
  • the second power signal line 500 and the data line Vd are alternately arranged along the first direction.
  • the second power signal line 500 is electrically connected to the second pole CC2 of the capacitor C through a via 3831 penetrating the second interlayer insulating layer 140.
  • the second power signal line 500 is electrically connected to the light shielding portion S through a via hole 3832 penetrating the second interlayer insulating layer 140 to provide a constant voltage to the light shielding portion S.
  • One end of the first transfer electrode 341 is electrically connected to the second electrode of the compensation transistor T3 through a via hole 384 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140.
  • the other end of the first transfer electrode 341 is electrically connected to the gate of the driving transistor T1 (that is, the first electrode CC1 of the capacitor C) through the via hole 385 in the first interlayer insulating layer 150 and the second interlayer insulating layer 140. connect.
  • One end of the second transfer electrode 342 is electrically connected to the reset power signal line Init through a via hole 386 penetrating through the second interlayer insulating layer 140.
  • the other end of the second transfer electrode 342 is electrically connected to the first electrode of the second reset transistor T7 through a via 387 penetrating through the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 .
  • the driving electrode 343 is electrically connected to the second electrode of the second light emitting control transistor T5 through a via 388 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140.
  • the data line Vd includes a body 610 extending in the second direction, and a convex portion 620 protruding toward the corresponding pixel circuit 0221 in the first direction.
  • the overlapping area of the orthographic projection of the via 381 on the base substrate 100 and the orthographic projection of the protrusion 620 on the base substrate 100 may be the orthographic projection of the via 381 on the base substrate 100 70%-100% of the area, such as 70%, 80% or 100%. That is to say, the electrical connection between the data line Vd and the pixel circuit 0221 is mainly realized by the electrical connection between the convex portion 620 and the pixel circuit 0221. In this way, when the line width of the data line Vd body 610 is narrow, the protrusion 620 can be used to ensure a good electrical connection between the data line Vd and the pixel circuit 0221.
  • a passivation layer 123 and a first flat layer 122 may be stacked and formed on the first metal layer 340 in a direction away from the base substrate 100 in order to insulate and protect the first metal layer 340. But it is not limited to this.
  • the positions of the passivation layer 123 and the first flat layer 122 may be interchanged; or, the side of the first metal layer 340 away from the base substrate 100 is only provided with the first flat layer 122 without the passivation layer 123.
  • FIG. 6F shows a top view structure of a second metal layer 350 in the display substrate 10.
  • FIG. 6G shows the distribution of a plurality of via holes required for electrical connection between the second metal layer 350 and the first metal layer 340.
  • FIG. 6G' shows the relative position between the second metal layer 350 and each via hole in FIG. 6G.
  • the second metal layer 350 is a patterned metal film. The second metal layer 350 can be used to make the first power signal line 400 and the connection electrode 450.
  • the connecting electrode 450 is arranged in a one-to-one correspondence with the driving electrode 343 in the first metal layer 340, and the connecting electrode 450 is electrically connected to the driving electrode 343 through a via 352 penetrating the first planar layer 122 and the passivation layer 123.
  • FIG. 6H shows the distribution of a plurality of via holes in the second flat layer 121.
  • FIG. 6H' shows the relative position between the via holes in the second metal layer 350 and the second flat layer 121.
  • FIG. 6I shows the distribution of the pixel electrodes in the pixel electrode layer 360.
  • FIG. 6I' shows the positional relationship among the pixel electrode layer 360, the second metal layer 350, the first via hole H1, and the second via hole H2.
  • the first via hole H1 is a via hole 1210 passing through the second flat layer 121.
  • the second via hole H2 is a via hole 352 penetrating the first flat layer 122 and the passivation layer 123.
  • the pixel electrode layer 360 is a patterned metal film.
  • the pixel electrode layer 360 can be used to fabricate pixel electrodes in each sub-pixel. According to the arrangement of the sub-pixels in the aforementioned sub-pixel group 200, the structure of the pixel electrode in each sub-pixel is as described above.
  • the pixel electrode is electrically connected to the connection electrode 450 through a via hole 1210 penetrating through the second flat layer 121.
  • the orthographic projection of the first via H1 corresponding to the plurality of pixel circuits in the same row along the first direction on the base substrate 100 is along the first straight line L1 extended arrangement.
  • the orthographic projections of the plurality of second via holes H2 corresponding to the plurality of pixel circuits located in the same row along the first direction on the base substrate 100 are arranged along the second straight line L2.
  • the effective light-emitting area 2201 of the first sub-pixel 22-1 and the effective light-emitting area 2202 of the second sub-pixel 22-2 corresponding to the multiple pixel circuits located in the same row along the first direction are respectively located on both sides of the first straight line L1 .
  • the first via hole H1 and the second via hole H2 corresponding to the same connecting electrode 450 have an interval D2 between the orthographic projections on the base substrate. In this way, in the process of making the second via hole H2, the connecting electrode 450 and the first via hole H1, the orthographic projection of the first via hole H1 and the second via hole H2 on the base substrate 100 can be avoided.
  • the second metal layer 350 is recessed at the second via hole H2, the second flat layer 121 cannot be completely etched, and the pixel electrode layer 360 is recessed at the first via hole H1 Etc.; so as to help ensure the flatness of the pixel electrode in the pixel electrode layer 360, and the electrical connection performance between the pixel electrode and the connection electrode 450, so as to improve the display effect of the display substrate.
  • the passivation layer 123 and the first flat layer 122 are sequentially stacked and formed on the surface of each transistor away from the base substrate, and the second via hole H2 penetrates the first flat layer 122 and the passivation layer 123, which has Certain hole depth.
  • the second metal layer 350 is easily recessed at the second via hole H2.
  • the second flat layer 121 is formed on the surface of the second metal layer 350 away from the base substrate 100, and it is usually difficult for the second flat layer 121 to completely fill the recess of the second metal layer 350 at the second via hole H2.
  • the orthographic projections of the first via hole H1 and the second via hole H2 formed in the second flat layer 121 on the base substrate 100 overlap, it is easy to cause the pixel electrode in the subsequent pixel electrode layer 360 A serious sinking problem occurs at the first via hole H1.
  • the first via hole H1 and the second via hole H2 with an interval D2 between the orthographic projections on the base substrate the above problem can be effectively improved.
  • the orthographic projection of the first via H1 corresponding to the plurality of pixel circuits located in the same column in the second direction on the base substrate 100 is along the third straight line L3 arrangement.
  • the orthographic projection of the first via H1 on the base substrate 100 and the orthographic projection of the second via H2 on the base substrate 100 corresponding to the same connecting electrode 450 are arranged along the third straight line L3.
  • the first through-holes H1 and the second through-holes H2 are arranged in an array in the display substrate 10, which is convenient to manufacture, and is also conducive to simplifying the layout design of the corresponding mask.
  • the orthographic projection of the first via H1 on the base substrate 100 and the orthographic projection of the second via H2 on the base substrate 100 have substantially the same shape and area.
  • the shape of the first via hole H1 and the second via hole H2 can be a regular rectangle or a circle, so as to facilitate determining the overlap between the connection electrode 450 and the pixel electrode, and between the connection electrode 450 and the driving electrode 343.
  • the connection area is to ensure that the connection line between the pixel electrode and the pixel circuit (for example, the connection electrode 450 and the driving electrode 343) has a small resistance value.
  • the orthographic projection of the connection electrode 450 on the base substrate 100 and the orthographic projection of the driving electrode 343 on the base substrate 100 have substantially the same shape.
  • the area of the orthographic projection of the connecting electrode 450 on the base substrate 100 is larger than the area of the orthographic projection of the driving electrode 343 on the base substrate 100.
  • the orthographic projection of the driving electrode 343 on the base substrate 100 is located within the orthographic projection of the corresponding connecting electrode 450 on the base substrate 100, and a part of the boundary of the two orthographic projections overlaps or substantially overlaps.
  • the orthographic projection of the connecting electrode 450 on the base substrate 100 and the orthographic projection of the driving electrode 343 on the base substrate 100 have non-overlapping portions, and the orthographic projection of the first via hole H1 on the base substrate 100 is similar to the above
  • the non-overlapping part has an overlap. Therefore, it is convenient to arrange the first through holes H1 and the second through holes H2 in a straight line along the first direction and the second direction, and reasonably improve the space utilization rate of the display substrate, so that the display substrate has higher light transmission. Rate.
  • the second poles of the two light-emitting control transistors T5 are electrically connected. Taking the through hole 388 in the gate insulating layer 160, the first interlayer insulating layer 150 and the second interlayer insulating layer 140 as the third through hole H3, the third through hole corresponding to the same driving electrode 343 H3, the second via hole H2, and the first via hole H1 have an interval between two of the three orthographic projections on the base substrate 100.
  • the distance B1 between the orthographic projection of any one of the first via hole H1 and the second via hole H2 on the base substrate 100 to the effective light-emitting area of the corresponding sub-pixel is greater than 2 ⁇ m, and its value range is, for example, :2 ⁇ m ⁇ 20 ⁇ m.
  • the distance B1 between the orthographic projection of any one of the first via hole H1 and the second via hole H2 on the base substrate 100 to the effective light-emitting area K of the corresponding sub-pixel is greater than Or equal to 2.5 ⁇ m.
  • the minimum interval of is greater than 0.8 ⁇ m, and its value range is, for example, 0.8 ⁇ m to 10 ⁇ m.
  • the minimum distance between the orthographic projection of the first via hole H1 and the second via hole H2 on the base substrate 100 is greater than 1 ⁇ m, and its value range is, for example, 1 ⁇ m-10 ⁇ m. For example, as shown in FIG.
  • the minimum distance B2 between the orthographic projection of the first via hole H1 on the base substrate 100 and the orthographic projection of the corresponding second via hole H2 on the base substrate 100 is 1.2 ⁇ m; the minimum distance B3 between the orthographic projection of the second via H2 on the base substrate 100 and the orthographic projection of the corresponding third via H3 on the base substrate 100 is 0.9 ⁇ m.
  • the first via hole H1 and the second via hole H2 are arranged along a straight line in the second direction, and the orthographic projection of the first via hole H1 on the base substrate 100 to the corresponding third via hole H3 on the substrate
  • the minimum interval between orthographic projections on the substrate 100 is 2.1 ⁇ m (0.9 ⁇ m+1.2 ⁇ m).
  • the first metal layer 340 is recessed at the third via hole H3, the passivation layer 123 and the first flat layer 122 cannot be completely etched, and the connection electrode 450 is in the second via hole H2. It is helpful to ensure the flatness of the connecting electrode 450 and the electrical connection performance between the connecting electrode 450 and the driving electrode 343, so as to improve the display effect of the display substrate.
  • the orthographic projection shape of the third via hole H3 on the base substrate 100 may be substantially the same as the shape of the aforementioned first via hole H1 and the second via hole H2.
  • the shape of the third via hole H3 can be a regular rectangle or a circle.
  • the orthographic projections of the third via holes H3 corresponding to the plurality of pixel circuits located in the same column along the second direction on the base substrate 100 are arranged along the same straight line.
  • the orthographic projections of the third via holes H3 corresponding to the plurality of pixel circuits located in the same row along the first direction on the base substrate 100 are arranged along the same straight line.
  • the plurality of third via holes H3 are arranged in an array in the display substrate 10, which is not only convenient for manufacturing, but also beneficial to realize the connection between the second via hole H2 and the first via hole H1.
  • the design of the relative distribution position between the two can reasonably improve the space utilization rate of the display substrate, so that the display substrate has a higher light transmittance.
  • the via hole 381 penetrating the gate insulating layer 160, the first interlayer insulating layer 150, and the second interlayer insulating layer 140 is the fourth via hole H4.
  • the orthographic projections on the base substrate 100 of the fourth via holes H4 corresponding to a plurality of pixel circuits located in the same column in the second direction can extend along the same straight line to facilitate manufacturing and reasonably improve the space utilization rate of the display substrate.
  • the display substrate has a higher light transmittance.
  • the first power signal line 400 includes a plurality of first sub-power signal lines 410 extending in a first direction and a plurality of second sub-power signal lines extending in a second direction.
  • the first sub power signal line 410 and the second sub power signal line 420 are interconnected. That is, the first power signal lines 400 are distributed in a grid pattern.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 passes through the interval between the effective light-emitting area of the first sub-pixel 22-1 and the effective light-emitting area of the second sub-pixel 22-2. That is to say, in the same second color sub-pixel pair 220, the effective light-emitting area interval between the first sub-pixel 22-1 and the second sub-pixel 22-2 is positive on the straight line extending in the second direction. There is no overlap between the projection and the orthographic projection of the effective light-emitting area in the second color sub-pixel pair on the same straight line.
  • At least one of the first effective light-emitting area 2100 of the first color sub-pixel 210 and the third effective light-emitting area 2300 of the third color sub-pixel 230 is located at the center of the orthographic projection on the base substrate 100.
  • a sub-power signal line 410 is in the orthographic projection on the base substrate 100. That is, the first sub-power signal line 410 may serve as the symmetric center of the first effective light-emitting area 2100 and the third effective light-emitting area 2300, so that the first effective light-emitting area 2100 and the third effective light-emitting area 2300 are located in the first sub-power source.
  • the portions on both sides of the signal line 410 have the same application environment, so as to ensure that the light intensity emitted by the first effective light-emitting area 2100 and the third effective light-emitting area 2300 is uniform, so as to improve the color shift.
  • the ratio of the two distances between the orthographic projection of a sub-power signal line 410 on the base substrate 100 ranges from 0.9 to 1.1. That is, in the same second color sub-pixel pair 220, the first sub-effective light-emitting area 2201 of the first sub-pixel 22-1 and the second sub-effective light-emitting area 2202 of the second sub-pixel 22-2 to the same
  • the distance of one sub-power signal line 410 is approximately the same.
  • the first sub-effective light-emitting area 2201 of the first sub-pixel 22-1 and the second sub-effective light-emitting area 2202 of the second sub-pixel 22-2 are symmetrically arranged with the first sub power signal line 410 as the center.
  • the two effective light-emitting regions in the second color sub-pixel pair 220 not only have the same light-emitting area, but also have a consistent application environment relative to the first sub-power signal line 410 to improve the color shift.
  • At least one second sub-power signal line 420 has a break 421, that is, the second sub-power signal line 420 is not a continuous signal line.
  • the second sub-power signal line 420 includes a plurality of signal line segments that are disconnected from each other. Along the extending direction, the interval between any two adjacent signal line segments is the above-mentioned break 421.
  • the effective light-emitting area and the interval between the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are located at the fracture 421.
  • the orthographic projection of the second sub-power signal line 420 on the base substrate 100 does not penetrate the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2, and the spacing thereof is on the front of the base substrate 100. projection.
  • the orthographic projection of the virtual connection line between the two end points in the second direction of the fracture 421 on the base substrate 100, the effective light-emitting area that penetrates the first sub-pixel 22-1 and the second sub-pixel 22-2, and the The interval is in the orthographic projection of the base substrate 100.
  • the second sub-power signal line 420 with the cutout 421 does not overlap with the two effective light-emitting regions in the pair of corresponding second-color sub-pixels and the orthographic projection of the spacing on the base substrate.
  • the orthographic projection of the first power signal line 400 on the base substrate 100 is in contrast to the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220.
  • the orthographic projection on the base substrate 100 has no overlap. That is, the orthographic projection of the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 on the base substrate 100 can be compared with the second sub-power signal line 420.
  • the orthographic projection of the corresponding fracture 421 on the base substrate 100 overlaps, but there is no overlap with the orthographic projection of the first sub-power signal line 410 and the second sub-power signal line 420 on the base substrate 100.
  • the extension directions of the second sub power signal line 420 and the second power signal line 500 are the same.
  • the second sub power signal line 420 is electrically connected to the second power signal line 500 through a via 352 penetrating the first flat layer 122 and the passivation layer 123.
  • the second power signal line 500 and the first power signal line 400 can be connected in parallel to reduce the resistance of the metal connection in the second metal layer 350, thereby reducing the voltage drop of the power supply voltage (IRDROP).
  • the orthographic projections on the base substrate 100 of the second power signal line 500 and the second sub power signal line 420 coupled thereto at least partially overlap.
  • the orthographic projection of the second power signal line 500 on the base substrate 100 and the effective light-emitting areas of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 are on the base substrate 100
  • the orthographic projections partially overlap.
  • the orthographic projection of the second sub power signal line 420 on the base substrate 100 is within the orthographic projection of the second power signal line 500 on the base substrate 100.
  • the second power signal line 500 may roughly overlap with the part of the second sub power signal line 420 except for the break 421, but the line width of the second sub power signal line 420 is partially adjusted without being connected to the second power signal line 500.
  • the width of the second sub power signal line 420 in the first direction is slightly different.
  • the second sub power signal line 420 is in the corresponding position.
  • the width at the position of some color sub-pixels is reduced.
  • the width of the second power signal line 500 in the first direction at different positions in the extending direction thereof is slightly different.
  • the wider part of the second power signal line 500 and the second sub-power signal line 420 is consistent.
  • the via hole 352 penetrating the first flat layer 122 and the passivation layer 123 is the fifth via hole H5
  • the fifth via holes H5 located in the same row along the first direction are
  • the orthographic projection on the base substrate 100 may be arranged along the fourth straight line L4.
  • the distance from the orthographic projection of the fifth via hole H5 on the base substrate 100 to the orthographic projection of any effective light-emitting area on the base substrate 100 is greater than 2.5 um.
  • two second sub-power signal lines 420 located on both sides of the first effective light-emitting area 2100 of the first color sub-pixel 210 and adjacent to the first effective light-emitting area 2100 are separated from the first effective light-emitting area
  • the distances between the center lines of the 2100 extending in the second direction are not equal.
  • the second sub-power signal line 420 is adjacent to the first effective light-emitting area 2100 in the first direction and the distance from the center line of the first effective light-emitting area 2100 extending in the second direction is greater than that of the other one and the first effective light-emitting area.
  • the area 2100 is adjacent to the second sub-power signal line 420 in the first direction.
  • the display substrate 10 further includes a plurality of pad blocks 430 arranged on the same layer as the first power signal line 400 and a plurality of support portions 440 arranged on the same layer as the pad blocks 430.
  • the aforementioned second metal layer 350 can also be used to make the spacer 430 and the supporting portion 440.
  • the spacer 430 extends along the second direction and is correspondingly coupled to the first sub power signal line 410.
  • the spacer 430 is located between the first effective light-emitting area 2100 and the second sub-power signal line 420.
  • the spacer 430 may adopt a long structure extending in the second direction.
  • Two ends of the cushion block 430 in the second direction are respectively coupled to the second sub-power signal line through the support portion 440 to form a closed ring structure.
  • the center of the orthographic projection of the spacer block 430 on the base substrate 100 is located within the orthographic projection of the first sub-power signal line 410 on the base substrate 100. That is, the first sub power signal line 410 may be the center of symmetry of the pad block 430.
  • the distance from the first effective light-emitting area 2100 to the pad block 430 and the second sub-power signal line 420 located on both sides of the first effective light-emitting area 2100 is approximately the same in the first direction. For example, the ratio of the two distances ranges from 0.9 to 1.1. It can be ensured that the two sides of the first effective light-emitting area 2100 have a relatively consistent application environment, and the intensity of the light emitted by the first effective light-emitting area 2100 is uniform, which is beneficial to improve the color shift.
  • the spacer block 430 is electrically connected to the first power signal line 400, which can prevent the spacer block 430 from being in a floating state, thereby affecting the normal operation of the light emitting device 0220.
  • the orthographic projection of the spacer block 430 on the base substrate 100 and the orthographic projection of the first effective light-emitting area 2100 on the substrate substrate do not overlap, which can prevent the spacer 430 from affecting the display of the first color sub-pixel 210.
  • the orthographic projections of the spacer block 430 and the pixel electrode 211 of the first color sub-pixel 210 on the base substrate 100 do not overlap, or the overlapping area of the two is small, which is beneficial to reduce color shift.
  • the size of the spacer 430 in the second direction is greater than the size of the spacer 430 in the first direction.
  • the size of the spacer 430 along the second direction is smaller than the size of the first effective light-emitting area 2100 along the same direction.
  • the size of the spacer 430 in the second direction can be designed to be smaller than the size of the first effective light-emitting area in the same direction, so as to improve the light transmittance of the display substrate .
  • each film layer from the base substrate 100 to the pixel electrode layer 360 at least a portion of the notch area of the pixel electrode is in contact with each metal layer.
  • the metal patterns are not overlapped, so that the light transmittance of the partial area is greater than 60%.
  • each film layer from the base substrate 100 to the pixel electrode layer 360 at least part of the notch area is connected to the metal patterns and semiconductor patterns in each metal layer. None of the semiconductor patterns in the layers overlap, so that the light transmittance of this partial area is greater than 70%.
  • the light-transmitting part of the notch area can be used to reflect light, so as to realize the detection of fingerprint lines.
  • the fingerprint detection technology under the optical screen usually uses the light emitted by the display substrate 10 as the light source.
  • the fingerprint sensor is usually arranged on the non-display side of the display substrate, for example, it may be located on the side of the light emitting device 0220 close to the base substrate 100 to realize the under-screen fingerprint. Detection function.
  • the light emitted by each sub-pixel can be used for display and as light for fingerprint detection under the screen, and the side of the sub-pixel away from the base substrate 100 can also be provided with a top film layer for placing a finger.
  • the fingerprint sensor that collects the fingerprint image can be arranged on the same side of the display substrate 10 as each sub-pixel, and the fingerprint sensor is arranged on the side of the light-emitting device 0220 in each sub-pixel close to the base substrate 100 for detecting the Reflected light reflected by fingerprints on the surface.
  • the fingerprint sensor may include a plurality of detection units arranged in an array.
  • the film layers such as the top film and the base substrate are transparent, and a light-transmitting area is provided between adjacent sub-pixels so that the reflected light of the fingerprint on the surface of the top film can be It is incident on the fingerprint sensor to obtain a fingerprint image.
  • the anode of the light-emitting device of each sub-pixel easily affects the light transmittance, which in turn affects the sensitivity of fingerprint detection. Therefore, providing notches in the pixel electrodes of the light-emitting device can effectively increase the light transmittance in the display substrate.
  • the metal having the same potential as the control electrode of the driving transistor T1 includes: A first electrode CC1 of the capacitor C in a gate metal layer 320 and a first transfer electrode 341 in the first metal layer 340.
  • the pixel electrode of the first sub-pixel 22-1 is on the base substrate 100
  • the overlapped projection area of the orthographic projection and the first projection is the first area
  • the orthographic projection of the pixel electrode in the second sub-pixel 22-2 on the base substrate 100 and the overlapped projection area of the first projection is the second Area
  • the value range of the area ratio between the first area and the second area can be 0.8 to 1.2. That is, the first area and the second area are approximately the same.
  • the orthographic projection of the first pole CC1 of the capacitor C on the base substrate 100 in each pixel circuit partially overlaps the orthographic projection of the first transfer electrode 341 on the base substrate 100, and the first sub-pixel 22-1 and The two pixel electrodes in the second sub-pixel 22-2 have different shapes. Therefore, optionally, the pixel electrode 221-1 of the first sub-pixel 22-1 and the first electrode CC1 of the capacitor C are both on the base substrate.
  • the overlapping area of the orthographic projection on the base substrate 100 is smaller than the overlapping area of the orthographic projection of the pixel electrode 221-2 of the second sub-pixel 22-2 and the first electrode CC1 of the capacitor C on the base substrate 100; and, The overlapping area of the orthographic projection of the pixel electrode 221-1 of the first sub-pixel 22-1 and the first transfer electrode 341 on the base substrate 100 is larger than that of the pixel electrode 221-2 of the second sub-pixel 22-2 The area overlapped with the orthographic projection of the first transfer electrode 341 on the base substrate 100.
  • the compensation portion 2-2 of the pixel electrode 221-1 of the first sub-pixel 22-1 includes: a first compensation portion 2- electrically connected to the curved portion 2-1 21, and a second compensating part 2-22 located on a side of the first compensating part 2-21 away from the curved part 2-1 and electrically connected to the first compensating part 2-21.
  • the first compensation portion 2-21 and the second compensation portion 2-22 may adopt a long strip structure extending in the second direction.
  • the orthographic projection of the second compensation portion 2-22 on the base substrate 100 and the orthographic projection of the first pole CC1 of the capacitor C on the base substrate 100 do not overlap.
  • the size of the second compensation portion 2-22 in the first direction is smaller than the size of the first compensation portion 2-21 in the same direction, which is conducive to obtaining more light-transmissive areas in the display substrate 10, so as to improve the display substrate 10. Light transmittance.
  • the compensation portion 2-2 of the pixel electrode 221-1 in the first sub-pixel 22-1 is located at the pixel electrode 231 of the adjacent third-color sub-pixel 230 and the first color Between the pixel electrodes 211 of the sub-pixel 210.
  • the first distance W1 from the second compensation portion 2-22 to the pixel electrode 231 of the third color sub-pixel 230 in the first direction may be equal to the second distance W1 from the second compensation portion 2-22 to the pixel electrode 211 of the first color sub-pixel 210 in the first direction.
  • the distance W2 is approximately the same.
  • the third distance W3 from the first compensation portion 2-21 to the pixel electrode 231 of the third color sub-pixel 230 in the first direction can be compared to the fourth distance W3 from the pixel electrode 211 of the first color sub-pixel 210 in the first direction.
  • the distance W4 is approximately the same.
  • the first distance W1 is greater than the third distance W3, and the second distance W2 is greater than the fourth distance W4.
  • the ratio of the second distance W2 to the first distance W1 ranges from 0.9 to 1.1.
  • the value range of the first distance W1 is 4.5 ⁇ m to 6.5 ⁇ m, which is 5.47 ⁇ m, for example.
  • the second distance W2 has a value range of 4.5 ⁇ m to 6.5 ⁇ m, which is, for example, 5.73 ⁇ m.
  • the ratio of the fourth distance W4 to the third distance W3 ranges from 0.9 to 1.1.
  • the value range of the third distance W3 is 2.5 ⁇ m ⁇ 4.0 ⁇ m, which is 3.0 ⁇ m, for example.
  • the second distance W2 has a value range of 2.5 ⁇ m to 4.0 ⁇ m, which is, for example, 3.0 ⁇ m.
  • each sub-pixel in the display substrate 10 is as described above.
  • the light-shielding area can be reduced, so as to increase the light transmittance of the display substrate.
  • the area of the effective light-emitting area of each sub-pixel remains unchanged, the area of the effective light-emitting area and the pixel electrode is increased by changing the shape of the part of the pixel electrode outside the effective light-emitting area, such as the connecting portion.
  • the influence of the pixel electrode on the light shielding can be reduced, thereby improving the light transmittance of the display substrate.
  • the area ratio of the first effective light-emitting region 2100 to the pixel electrode 211 ranges from 53% to 55%.
  • the area ratio of the first sub-effective light-emitting area 2201 and the pixel electrode 221-1 ranges from 43.5% to 48%, and the second sub-effective light-emitting area 2202 and the pixel electrode 221-2 are The area ratio ranges from 43.5% to 48%.
  • the area ratio of the third effective light-emitting region 2300 to the pixel electrode 231 ranges from 67.5% to 69%.
  • the area ratio of the first effective light-emitting region 2100 to the pixel electrode 211 is 54.9%.
  • the area ratio of the first sub-effective light-emitting region 2201 to the pixel electrode 221-1 is 47%
  • the area ratio of the second sub-effective light-emitting region 2202 to the pixel electrode 221-2 is 47%.
  • the area ratio of the third effective light-emitting region 2300 to the pixel electrode 231 is 68.3%. Therefore, it is possible to ensure that the display substrate 10 as a whole has a good light transmittance, thereby improving the sensitivity of fingerprint detection.
  • the area ratio of the first effective light-emitting area 2100, the effective light-emitting area of the second color sub-pixel pair 220, and the third effective light-emitting area 2300 is approximately 1:1.27:1.47.
  • the area ratio of the pixel electrode 211 in the first color sub-pixel 210, the pixel electrode in the second color sub-pixel pair 220, and the pixel electrode 231 in the third color sub-pixel 230 is approximately 1:1.48:1.18.
  • the "area ratio" refers to the ratio of the area of the orthographic projection on the base substrate.
  • FIG. 7A Some embodiments of the present disclosure also illustrate a cross-sectional example of multiple partial regions in a display substrate 10.
  • FIG. 7B is a schematic cross-sectional view along the AA' direction of the display substrate 10 shown in FIG. 7A.
  • FIG. 7C is a schematic cross-sectional view along the BB' direction of the display substrate 10 shown in FIG. 7A.
  • FIG. 7D is a schematic cross-sectional view of the display substrate 10 shown in FIG. 7A along the CC' direction.
  • FIG. 7E is a schematic cross-sectional view along the D-E-F-G-H direction of the display substrate 10 shown in FIG. 7A.
  • FIG. 7B is a schematic cross-sectional view along the AA' direction of the display substrate 10 shown in FIG. 7A.
  • FIG. 7C is a schematic cross-sectional view along the BB' direction of the display substrate 10 shown in FIG. 7A.
  • FIG. 7D is a schematic cross-sectional view of the display substrate 10
  • FIG. 7F is a schematic cross-sectional view along the L-M-N direction in the display substrate 10 shown in FIG. 7A.
  • FIG. 7G is a schematic cross-sectional view along the R-S-T direction of the display substrate 10 shown in FIG. 7A. Please understand with reference to FIGS. 6A to 6I and FIGS. 7A to 7G below.
  • FIGS. 7B to 7G are all based on the passivation layer 123 and the first flat layer 122 formed between the first metal layer 340 and the second metal layer 350, and the first flat layer 122 is located on the passivation layer.
  • the side of the chemical layer 123 away from the base substrate 100 is taken as an example. But it is not limited to this.
  • the display substrate 10 further includes a pixel defining layer 130 on the pixel electrode layer 360.
  • the pixel defining layer 130 has a plurality of openings for defining effective light-emitting regions of the sub-pixels.
  • the light-emitting device 0220 includes an anode, a light-emitting layer, and a cathode that are sequentially stacked.
  • the anode of the light emitting device 0220 is coupled to the pixel circuit 0221.
  • the opening in the pixel defining layer 130 exposes the anode of the light emitting device 0220.
  • At least part of the light-emitting layer of the light-emitting device 0220 is located in the opening, and the cathode is located on the side of the pixel defining layer 130 facing the base substrate.
  • the portion of the light-emitting layer in contact with the anode can emit light under the voltage drive of the anode and the cathode to form an effective light-emitting area.
  • the “effective light-emitting area” may refer to a two-dimensional planar area, which is parallel to the base substrate 100. It should be noted that due to process reasons, the size of the opening of the pixel defining layer 130 away from the base substrate 100 is slightly larger than the size of the part close to the base substrate 100, or from the side close to the base substrate 100 to far away from the base substrate 100. The size of one side is gradually increasing, so the size of the effective light-emitting area may be slightly different from the size of the opening in the pixel defining layer 130 at different positions, but the overall area shape and size are basically the same.
  • the orthographic projection of the effective light-emitting area on the base substrate 100 roughly coincides with the orthographic projection of the corresponding opening in the pixel defining layer 130 on the base substrate 100.
  • the orthographic projection of the effective light-emitting area on the base substrate 100 completely falls within the orthographic projection of the corresponding opening in the pixel defining layer 130 on the base substrate 100, and the shapes of the two are similar, and the effective light-emitting area is on the base substrate 100.
  • the orthographic projection area of is slightly smaller than the orthographic projection area of the corresponding opening in the pixel defining layer 130 on the base substrate 100.
  • the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 have a space therebetween.
  • the “space” refers to the physical part of the pixel defining layer 130 between the two openings defined by the pixel defining layer 130.
  • the distance between the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 along the second direction is smaller than that of the first effective light-emitting area 2100 along the second direction.
  • the size of the interval along the second direction is smaller than the size of the third effective light-emitting area 2300 along the second direction.
  • the size of the first effective light-emitting area 2100 is larger than the size of the third effective light-emitting area 2300.
  • the size of the first effective light-emitting area 2100 may be 45-49 micrometers, for example, 47 micrometers; the size of the third effective light-emitting area 2300 may be 38-42 micrometers, for example, it may be 40 micrometers.
  • the shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are substantially the same.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 and the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are between the two centers of the two orthographic projections on the base substrate 100 The ratio of the distance between them is 0.9 to 1.1.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 and the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are two of the two orthographic projections on the base substrate 100.
  • the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 are symmetrically distributed with respect to the first sub-power signal line 410, which is beneficial to ensure the second color sub-pixel pair.
  • the environment of the first sub-pixel 22-1 and the second sub-pixel 22-2 included in 220 are consistent. But it is not limited to this.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 can also be closer to one of the second color sub-pixel pairs 220.
  • the orthographic projection of the first sub-power signal line 410 on the base substrate 100 and the pixel electrodes of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the second color sub-pixel pair 220 do not overlap.
  • the center of the above-mentioned orthographic projection refers to the geometric center of the orthographic projection shape.
  • the shape of the orthographic projection of the effective light-emitting area on the base substrate is determined by the shape of the effective light-emitting area.
  • the shape of the effective light-emitting area and the corresponding shape of the opening of the pixel defining layer 130 are roughly same.
  • the shape of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 includes a pentagon, a circle, or a drop shape.
  • FIG. 7A the shape of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 included in the second color sub-pixel pair 220 includes a pentagon, a circle, or a drop shape.
  • FIG. 7A schematically shows that the shapes of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are pentagons, which include a set of parallel opposite sides (parallel to the second direction) and one The vertical side (parallel to the first direction), the vertical side is perpendicular to a set of parallel opposite sides, two of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 in each second color sub-pixel pair 220
  • the vertical sides are adjacent to each other.
  • the first sub power signal line 410 is located between the two vertical sides and passes through the midpoint of the shortest line between the two vertical sides.
  • the shape of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 in FIG. 7A includes strictly an angle formed by two line segments
  • the first sub-effective light-emitting area 2201 The shape of the boundary between the two line segments of the second sub-effective light-emitting area 2202 may be rounded corners, such as a circle or a drop shape. That is, on the basis of the aforementioned pentagonal shape, the corners of the first sub-effective light-emitting area 2201 and the second sub-effective light-emitting area 2202 are rounded. For example, when the opening of the pixel defining layer 130 is formed, the corners of the opening may be rounded, so that the shape of the formed effective light-emitting area may be rounded.
  • FIG. 7B A partial cross-section of the second color sub-pixel pair 220 is shown in FIG. 7B.
  • the light-emitting layer 223 and the cathode layer 222 are sequentially laminated and formed on the surface of the pixel defining layer 130 away from the base substrate 100, and are in contact with the pixel electrode 221 exposed by the corresponding opening in the pixel defining layer 130 connect.
  • Some embodiments of the present disclosure are described by taking as an example the first sub-pixel 22-1 included in the second color sub-pixel pair 220 and the light-emitting layer 223 in the second sub-pixel 22-2 being integrated, for example, the same second color sub-pixel
  • the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the pixel pair 220 is a connected integral film layer, that is, the first sub-pixel 22-1 and the second sub-pixel 22-2 emit light
  • the layer 223 is a continuous and complete pattern, or the orthographic projection of the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 in the same second color sub-pixel pair 220 on the base substrate 100 It is continuous and complete, and the light-emitting layer 223 of the first sub-pixel 22-1 and the second sub-pixel 22-2 can be manufactured through an opening. But it is not limited to this.
  • FIG. 7C and FIG. 7D A partial cross-section of the first color sub-pixel 210 is shown in FIG. 7C and FIG. 7D.
  • the light-emitting layer 213 and the cathode layer 212 are sequentially laminated and formed on the surface of the pixel defining layer 130 away from the base substrate 100, and are in contact with the pixel electrode 211 exposed by the corresponding opening in the pixel defining layer 130 .
  • FIG. 7E Another partial cross-section of the first color sub-pixel 210 is shown in FIG. 7E.
  • the pixel electrode 211 is electrically connected to the connection electrode 450 through the via hole 1210 penetrating the second flat layer 121.
  • the connection electrode 450 is electrically connected to the driving electrode 343 through the via hole 351 penetrating the first planar layer 122 and the passivation layer 123.
  • the driving electrode 343 is electrically connected to the second electrode T5-2 of the second light-emitting control transistor through a via hole 388 penetrating the second interlayer insulating layer 140, the first interlayer insulating layer 150, and the gate insulating layer 160.
  • the orthographic projections of the via 1210, the via 351, and the via 388 on the base substrate 100 do not overlap, and there is a space between them.
  • the partial cross-section of the third color sub-pixel 230 is shown in FIG. 7F.
  • the orthographic projection of the pixel electrode 231 on the base substrate 100 and the orthographic projection of the first sub-power signal line 410 on the base substrate 100 partially overlap.
  • the light-emitting layer 233 and the cathode layer 232 are sequentially laminated and formed on the surface of the pixel defining layer 130 away from the base substrate 100, and are in contact with the pixel electrode 231 exposed by the corresponding opening in the pixel defining layer 130.
  • the partial cross-section of the first sub-pixel 22-1 is shown in FIG. 7G.
  • the pixel electrode 221-1 includes a main body portion 221-11, a curved portion 2-21, and a compensation portion 2-22.
  • the light-emitting layer 223-1 and the cathode layer 222-1 are sequentially laminated and formed on the surface of the pixel defining layer 130 away from the base substrate 100, and correspond to the main body portion 221-1 of the pixel electrode 221-1 exposed in the corresponding opening in the pixel defining layer 130. 11Contact connection. In the cross-section along the R-S direction of FIG.
  • the second sub-power signal line 420 in the first power signal line 400 may be electrically connected to the second power signal line 500 through a via 352 penetrating the first planar layer 122 and the passivation layer 123.
  • the second power signal line 500 may be electrically connected to the first electrode T4-1 of the first light-emitting control transistor through the via hole 382 penetrating the second interlayer insulating layer 140, the first interlayer insulating layer 150, and the gate insulating layer 160. connect.
  • the gate insulating layer 160, the first interlayer insulating layer 150, the second interlayer insulating layer 160, the passivation layer 123, the first flat layer 122, and the second flat layer 121 are multiple insulating layers, Used to insulate and protect the corresponding conductive layer, such as a metal layer or a semiconductor layer.
  • the gate insulating layer 160, the first interlayer insulating layer 150, the second interlayer insulating layer 160, and the passivation layer 123 are made of inorganic insulating materials, such as silicon nitride or silicon oxide.
  • the first flat layer 122 and the second flat layer 121 are made of an organic insulating material, such as an organic insulating resin.
  • Another embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the display device can avoid the occurrence of color shift as much as possible, and can also apply fingerprint detection technology, and the display device has high fingerprint detection sensitivity.

Abstract

本申请提供一种显示基板及显示装置。所述显示基板，包括：衬底基板和多个子像素。子像素包括像素电极和有效发光区。像素电极包括互连的主体部和连接部。主体部与有效发光区的形状相同，且主体部与像素电极的至少部分边界重合。多个子像素至少包括发光颜色相同的一个第一子像素和一个第二子像素。距离最近的第一子像素和第二子像素沿第二方向排列。第一子像素和第二子像素的两个像素电极在衬底基板上的正投影的面积不同。第一子像素和第二子像素中的至少一个子像素的连接部和主体部在沿第一方向延伸的直线上的两个正投影至少部分不交叠。第二子像素的像素电极在沿第二方向延伸的直线上的正投影，位于第一子像素的像素电极在同一直线上的正投影内。

Description

显示基板及显示装置
本申请要求于2020年4月26日递交的国际申请号为PCT/CN2020/086997的PCT申请、以及于2020年9月10日递交的国际申请号为PCT/CN2020/114623的PCT申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有源矩阵有机发光二极管(Active-matrix organic light emitting diode，简称AMOLED)显示基板因具有自发光、广色域、高对比度、可柔性化以及高响应等优势，在显示装置中得到了广泛的应用。
目前，在AMOLED显示基板中像素分部密度日渐提升的趋势下，AMOLED显示基板中像素的尺寸逐渐减小，使得像素的可设计空间有限。在此基础上，合理优化像素电路的结构及其制作工艺，有利于提升AMOLED显示基板所在显示装置的显示效果。
发明内容
一方面，本公开一些实施例提供一种显示基板。所述显示基板，包括：衬底基板和多个子像素。所述子像素包括像素电极和有效发光区。所述像素电极包括互连的主体部和连接部。所述主体部与所述有效发光区的形状相同，且所述主体部与所述像素电极的至少部分边界重合。多个所述子像素至少包括发光颜色相同的一个第一子像素和一个第二子像素。距离最近的所述第一子像素和所述第二子像素沿第二方向排列。所述第一子像素和所述第二子像素的两个像素电极在所述衬底基板上的正投影的面积不同。所述第一子像素和所述第二子像素中的至少一个子像素的连接部和主体部在沿第一方向延伸的直线上的两个正投影至少部分不交叠。所述第二子像素的像素电极在沿第二方向延伸的直线上的正投影，位于所述第一子像素的像素电极在同一直线上的正投影内。所述第二方向与所述第一方向相交，二者夹角的取值范围为80°～100°。
在一些实施例中，所述主体部包括顺次连接的第一边、第二边和第三边；所述第三边沿所述第二方向延伸。所述连接部与所述第二边连接，且与所述第一边之间具有间隔。从所述第一边上的任一点到所述连接部的沿所述第二方向延伸且在所述第一方向上远离所述第三边的边缘上任一点的连接直线，与所述主体部、所述连接部围成的区域为凹口区。
在一些实施例中，所述显示基板还包括位于所述衬底基板和所述像素电极之间的多个层；所述多个层中包括至少一个金属图案。沿垂直于所述衬底基板的方向，从所述衬底基板到所述像素电极之间的各个层中，所述凹口区的至少部分区域与所述金属图案没有交叠。
在另一些实施例中，所述的显示基板还包括位于所述衬底基板和所述像素电极之间的多个层；所述多个层中包括半导体图案和至少一个金属图案。沿垂直于所述衬底基板的方向，从所述衬底基板到所述像素电极之间的各个层中，所述凹口区的至少部分区域与所述半导体图案、所述金属图案均没有交叠。
在一些实施例中，所述第一子像素中像素电极的连接部包括：弯曲部、以及与所述弯曲部连接的补偿部。所述补偿部沿所述第二方向延伸。所述弯曲部与所述第二边连接，所述弯曲部与所述第一边之间具有间隔。
在一些实施例中，所述凹口区与所述弯曲部在所述衬底基板上的两个正投影的面积之比的取值范围为0.2～5。
在一些实施例中，所述补偿部的沿所述第一方向的最大尺寸大于所述弯曲部的沿所述第一方向的最大尺寸。
在一些实施例中，所述第二子像素中像素电极的连接部的沿所述第二方向的最大尺寸，小于或等于所述第一子像素中像素电极的弯曲部的沿所述第二方向的最大尺寸。
在一些实施例中，所述子像素还包括像素电路。所述像素电路包括驱动晶体管。与所述驱动晶体管的控制极的电位相同的金属图案在所述衬底基板上的正投影为第一投影。所述第一子像素中像素电极在所述衬底基板上的正投影和所述第一投影交叠的面积为第一面积。所述第二子像素中像素电极在所述衬底基板上的正投影和所述第一投影交叠的面积为第二面积。所述第一面积和所述第二面积之比的取值范围为：0.8～1.2。
在一些实施例中，所述显示基板还包括：位于所述衬底基板和所述像素电极之间的第一栅金属层，以及位于所述第一栅金属层和所述像素电极之间的第一金属层。与所述驱动晶体管的控制极的电位相同的金属图案，包括：位于所述第一栅金属层中的电容器的第一极，以及位于所述第一金属层中的第一转接电极。
所述第一子像素的像素电极与所述电容器的第一极在所述衬底基板上的正投影交叠的面积，小于所述第二子像素的像素电极与所述电容器的第一极在所述衬底基板上的正投影交叠的面积；且，所述第一子像素的像素电极与所述第一转接电极在所述衬底基板上的正投影交叠的面积，大于所述第二子像素的像素电极与所述第一转接电极在所述衬底基板上的正投影交叠的面积。
在一些实施例中，所述显示基板还包括：多条沿所述第一方向延伸的信号线。所述第一子像素的像素电极在所述衬底基板上的正投影与位于同一层的至少三条信号线在所述衬底基板上的正投影交叠。
在一些实施例中，所述位于同一层的至少三条信号线，包括：至少一条栅扫描信号线、至少一条发光控制信号线、以及至少一条复位控制信号线。
在一些实施例中，所述显示基板，还包括：第一绝缘层和多个连接电极。所述第一绝缘层位于所述像素电极和所述连接电极之间，且具有多个第一导通孔。所述像素电极通过所述第一导通孔与所述连接电极对应耦接。所述子像素还包括像素电路。多个所述像素电路沿所述第一方向排列构成排，沿所述第二方向排列构成列。同一排的多个所述像素电路对应的多个所述第一导通孔在所述衬底基板上的正投影沿第一直线排列。在所述同一排的多个所述像素电路对应的多个子像素中，所述第一子像素的有效发光区与所述第二子像素的有效发光区分别位于所述第一直线的两侧。
在一些实施例中，所述显示基板，还包括：第二绝缘层和多个驱动电极。所述第二绝缘层位于所述连接电极和所述驱动电极之间，且具有多个第二导通孔。所述连接电极通过所述第二导通孔与所述驱动电极对应耦接。同一个所述连接电极对应的所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影之间具有间隔。
在一些实施例中，同一排的多个所述像素电路对应的多个所述第二导通孔在所述衬底基板上的正投影沿第二直线排列。
在一些实施例中，所述第一导通孔和所述第二导通孔中任一在所述衬底基板上的正投影至对应子像素的有效发光区之间的距离大于2μm。
在一些实施例中，所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影的形状及面积大致相同。同一个所述连接电极对应的所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影沿第三直线排列。
在一些实施例中，所述驱动电极和所述连接电极在所述衬底基板上的正投影的形状大致相同，且所述连接电极在所述衬底基板上的正投影面积大于所述驱动电极在所述衬底基板上的正投影面积。
在一些实施例中，所述驱动电极在所述衬底基板上的正投影位于所述连接电极在所述衬底基板上的正投影内，且二者正投影的一部分边界重合或大致重合。
在一些实施例中，所述连接电极在所述衬底基板上的正投影与所述驱动电极在所述衬底基板的正投影具有非交叠部分，所述第一导通孔在所述衬底基板上的正投影与所述非交叠部分交叠。
在一些实施例中，所述显示基板还包括半导体图案层和第三绝缘层。所述半导体图案层位于所述衬底基板和所述驱动电极之间。所述第三绝缘层位于所述驱动电极和所述半导体图案层之间，且具有多个第三导通孔。所述驱动电极通过所述第三导通孔与所述半导体图案层中对应的部分耦接。同一个所述驱动电极对应的所述第三导通孔、所述第二导通孔和所述第一导通孔在所述衬底基板上的三个正投影中的两两之间具有间隔。
在一些实施例中，所述第一导通孔和所述第二导通孔中任一在所述衬底基板上的正投影、至所述第三导通孔在所述衬底基板上的正投影之间最小间隔的取值范围为：0.8μm～10μm。所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影之间最小间隔的取值范围为：1μm～10μm。
在一些实施例中，所述显示基板还包括多条数据线。所述数据线与所述驱动电极同层设置。所述第三绝缘层还具有多个第四导通孔。所述数据线通过第四导通孔与对应的像素电路连接。所述数据线沿所述第二方向延伸，且所述数据线包括在所述第一方向上向对应的像素电路凸起的多个凸起部。所述第四导通孔在所述衬底基板上的正投影与所述凸起部在所述衬底基板上的正投影之间的交叠面积，为所述第四导通孔在所述衬底基板上的正投影面积的70％-100％。
在一些实施例中，所述显示基板还包括多条电源信号线。多条所述电源信号线包括至少一条第一电源信号线。所述第一电源信号线与所述连接电极同层设置。所述第一电源信号线包括多条沿所述第一方向延伸的第一子电源信号线以及多条沿所述第二方向延伸的第二子电源信号线。所述第一子电源信号线与所述第二子电源信号线互连。 距离最近的所述第一子像素和所述第二子像素的两个有效发光区之间具有间隔。所述第一子电源信号线在所述衬底基板上的正投影，穿过所述第一子像素和所述第二子像素的两个有效发光区之间的间隔处。至少一条所述第二子电源信号线具有至少一个断口。所述断口的在所述第二方向上的两个端点之间的虚拟连线在所述衬底基板上的正投影，贯穿所述第一子像素和所述第二子像素的两个有效发光区以及所述间隔在所述衬底基板上的正投影。具有所述断口的所述第二子电源信号线与所述第一子像素和所述第二子像素的两个有效发光区以及所述间隔在所述衬底基板上的正投影均没有交叠。
在一些实施例中，多条所述电源信号线还包括多条第二电源信号线。所述第二电源信号线沿所述第二方向延伸。在所述显示基板还包括第二绝缘层和多个驱动电极的情况下，所述第二电源信号线与所述驱动电极同层设置。所述第二绝缘层还具有多个第五导通孔。所述第二子电源信号线通过所述第五导通孔与所述第二电源信号线对应耦接。
所述第二电源信号线和与其耦接的所述第二子电源信号线在所述衬底基板上的正投影至少部分交叠。所述第二电源信号线在所述衬底基板上的正投影，与所述第一子像素和所述第二子像素中任一子像素的有效发光区在所述衬底基板上的正投影部分交叠。
在一些实施例中，沿所述第一方向位于同排的多个所述第五导通孔在所述衬底基板上的正投影位于沿所述第一方向延伸的第四直线上。所述第五导通孔在所述衬底基板的正投影到任一所述有效发光区在所述衬底基板的正投影的距离大于2.5um。
在一些实施例中，距离最近的所述第一子像素和第二子像素构成子像素对。一个子像素组包括沿所述第一方向依次排列的一个第一颜色子像素、一个所述子像素对以及一个第三颜色子像素。所述子像素对被配置为出射第二颜色光线。所述第一颜色子像素的第一有效发光区和所述第三颜色子像素的第三有效发光区中的至少一者在所述衬底基板上的正投影的中心位于对应的所述第一子电源信号线在所述衬底基板上的正投影内。
在一些实施例中，位于所述第一颜色子像素的第一有效发光区两侧且与所述第一有效发光区相邻的两条所述第二子电源信号线，距离所述第一有效发光区的沿所述第二方向延伸的中心线的距离不相等。所述显示基板还包括与所述第一电源信号线同层设置的多个垫块和多个支撑部。所述垫块沿所述第二方向延伸。所述垫块位于所述第一有效发光区和所述第二子电源信号线之间，且通过所述支撑部与所述第二子电源信号线对应耦接。与所述垫块耦接的所述第二子电源信号线与所述第一有效发光区的沿所述第二方向延伸的中心线之间的距离，大于另一条与所述第一有效发光区相邻的第二子电源信号线至所述中心线之间的距离。所述垫块还与所述第一子电源信号线对应耦接。
在一些实施例中，所述垫块的形状大致为长条形。所述垫块在所述衬底基板上的正投影的中心位于与其耦接的所述第一子电源信号线在所述衬底基板上的正投影内。
在一些实施例中，所述第一子像素和所述第二子像素的两个有效发光区在所述衬底基板上的正投影，至位于所述两个有效发光区之间的所述第一子电源信号线在所述衬底基板上的正投影的两个距离之比的取值范围为0.9～1.1。
另一方面，提供一种显示装置。所述显示装置，包括如上任一些实施例中所述的显示基板。
附图说明
为了更清楚地说明本公开一些实施例中的技术方案，下面将对一些实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为根据本公开一些实施例中的一种显示装置的结构示意图；
图2A为根据本公开一些实施例中的一种显示基板在M0区域的放大示意图；
图2B为根据本公开一些实施例中的一种子像素组的结构示意图；
图2C为根据本公开一些实施例中的一种子像素在衬底基板上的分布示意图；
图3为根据本公开一些实施例中的一种像素电路的结构示意图；
图4为根据本公开一些实施例中的一种子像素组中各像素电极的结构示意图；
图5为根据本公开一些实施例中的一种显示基板在M1区域的放大示意图；
图6A、图6B、图6C、图6D、图6E、图6F、图6G、图6H和图6I为根据本公开一些实施例中的一种显示基板在其制备过程中不同层的俯视示意图；
图6E’为根据本公开一些实施例中的第一金属层与第二层间绝缘层140中的导通孔之间的位置示意图；
图6G’为根据本公开一些实施例中的第二金属层与第一平坦层122中的导通孔之间的位置示意图；
图6H’为根据本公开一些实施例中的第二金属层与第二平坦层121中的导通孔之间的位置示意图；
图6I’为根据本公开一些实施例中的第二金属层与像素电极层之间的位置示意图；
图7A为根据本公开一些实施例中的一种显示基板的局部示意图；
图7B为根据本公开一些实施例中的一种显示基板的沿AA’向的剖面示意图；
图7C为根据本公开一些实施例中的一种显示基板的沿BB’向的剖面示意图；
图7D为根据本公开一些实施例中的一种显示基板的沿CC’向的剖面示意图；
图7E为根据本公开一些实施例中的一种显示基板的沿D-E-F-G-H向的剖面示意图；
图7F为根据本公开一些实施例中的一种显示基板的沿L-M-N向的剖面示意图；
图7G为根据本公开一些实施例中的一种显示基板的沿R-S-T向的剖面示意图；
图8为根据本公开一些实施例中的一种第一导通孔、第二导通孔、第三导通孔和像素电极之间的位置示意图；
图9为根据本公开一些实施例中的一种第一子像素的像素电极与相邻像素电极之间的位置示意图。
具体实施方式
下面将结合本公开一些实施例中的附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的一些实施例，本领域普通技术人员所能获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
术语“第一”、“第二”等序数仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
本文中“近似”或“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围可以由本领域普通技术人员考虑到的测量误差以及与特定量的测量相关的误差(例如测量系统的局限性)所确定。
此外，为了清楚地表示附图中的多个层和区域，放大了图示中各层的厚度，以对各层之间的相对位置进行清楚示意。当表述为层、薄膜、区域、板等的部分位于其他部分“上方”或“上”时，该表述不仅包括“直接”在其他部分上方的情况，还包括其中间存在有其他层的情况。
本公开实施例提供一种显示装置。该显示装置例如为手机(mobile phone)、平板 电脑(pad)、电脑、智能穿戴产品(例如，智能手表、智能手环)、便携式电子设备、虚拟现实(Virtual Reality，简称VR)终端、增强现实(Augmented Reality，简称AR)终端等。本公开实施例对上述显示装置的具体形式不做特殊限制。
下面结合附图对本公开实施例提供的显示装置进行详细描述。
为了方便说明，以下以显示装置01为如图1所示的手机为例。在此情况下，显示装置01至少包括壳体11以及安装在壳体11内的显示基板10。壳体11内通常还设有能够容纳印刷电路板(Printed Circuit Board，简称PCB)、电池、摄像头等元件的容纳腔(图1中未示出)。
图2A为图1中的显示基板10在M0区域的放大示意图。图2B为显示基板10中一个子像素组的结构示意图。以下结合图2A和图2B，以显示基板10为AMOLED显示基板为例进行说明，但并不仅限于此。
在一些实施例中，如图2A和图2B所示，显示基板10包括衬底基板100以及位于衬底基板100上的多个子像素组200。每个子像素组可以由多个子像素构成，且每个子像素均包括像素电极和有效发光区。例如，每个子像素组200包括沿第一方向(图中所示的X方向)排列的一个第一颜色子像素210、一个第二颜色子像素对220以及一个第三颜色子像素230。第二颜色子像素对220包括沿第二方向(图中所示的Z方向)排列且发光颜色相同的第一子像素22-1和第二子像素22-2。第一颜色子像素210的有效发光区为第一有效发光区2100。第二颜色子像素220中的第一子像素22-1的有效发光区为第一子有效发光区2201，第二子像素22-2的有效发光区为第二子有效发光区2202。第三颜色子像素230的有效发光区为第三有效发光区2300。
上述子像素的像素电极包括互连的主体部和连接部。例如图2B中所示，第一颜色子像素210的像素电极211包括互连的主体部2111和连接部2112；第二颜色子像素对220中的第一子像素22-1的像素电极221-1包括互连的主体部221-11和连接部221-12；第二颜色子像素对220中的第二子像素22-2的像素电极221-2包括互连的主体部221-21和连接部221-22；第三颜色子像素230的像素电极231包括互连的主体部2311和连接部2312。结合图2B理解，各像素电极的主体部与其所属子像素的有效发光区的形状大致相同，且该主体部与像素电极的至少部分边界重合。
请结合图2B理解，在一些实施例中，如图2C所示，衬底基板100上的多个子像素至少包括发光颜色相同的一个第一子像素22-1和一个第二子像素22-2。该第一子像素22-1和第二子像素22-2的两个像素电极在衬底基板100上的正投影的面积不同。第一子像素22-1和第二子像素22-2中的至少一个子像素的连接部和主体部在沿第一方向(例如X方向)延伸的直线上的两个正投影至少部分不交叠。第二子像素22-2的像素电极在沿第二方向(例如Z方向)延伸的直线上的正投影，位于第一子像素22-1的像素电极在同一直线上的正投影内。此处，第二方向与第一方向相交，且二者夹角的取值范围为80°～100°。本公开实施例中，发光颜色相同的多个子像素采用如第一子像素22-1和第二子像素22-2所示的两种不同的结构，可以通过设计第一子像素22-1和第二子像素22-2中像素电极的形状，在提升子像素分布密度的基础上，有效简化显示基板10中像素电路整体的版图设计，以提升显示基板10的光透过率。
为了方便说明，以下以显示基板10采用了图2A中所示的结构为例进行详述。
请继续参阅图2A，多个子像素组200沿第一方向(例如X方向)排列形成子像素排。多个子像素排沿第二方向(例如Z方向)排列，且多个子像素排中任相邻两排的子像素组沿第一方向错位，即，任相邻的两个子像素排沿第一方向有一定的偏移量。因此，在任相邻的两个子像素排中，被配置为出射相同颜色光的子像素在第二方向上并不是对齐的。以第二颜色子像素对220的排列为例，如图2A所示，在沿第二方向相邻的任两排第二颜色子像素对220中，第二排R2的第二颜色子像素对220与第一排R1的第二颜色子像素对220沿第一方向错位，第一排R1和第二排R2沿第二方向排列。
此外，在一些示例中，以第一方向为行方向，位于奇数行的子像素排中的子像素组的排列方式相同，位于偶数行的子像素排中的子像素组的排列方式相同。
可选的，相邻的两个子像素排在第一方向上的偏移量大致为子像素组200在第一方向上的尺寸的一半。例如，子像素组200在第一方向上的尺寸为子像素组200在第一方向上的节距。这里的节距指在第一方向上相邻两个子像素组200中的两个第一颜色子像素210的有效发光区的中心之间的距离。这里有效发光区的中心指其在衬底基板上的正投影形状的几何中心。有效发光区在衬底基板100上的正投影形状大致为规则图形，例如对称图形。
此外，可以理解的是，本公开一些实施例中所涉及的中心，对于规则形状是指其几何中心；对于不规则形状是指其近似的几何中心，例如模拟出与该不规则形状相似度较高的规则形状，然后以模拟形状的几何中心为该不规则形状的中心。
上述第一方向和第二方向相交，其夹角的取值范围可以为80°～100°。例如，第一方向和第二方向分别为在同一平面内相互垂直的两个方向。例如，该平面为各子像素进行排列的平面，也即与衬底基板100平行的平面。
上述子像素组作为一个重复单元，其重复仅指子像素排列的重复，其他结构可以不相同也可以相同。此外，该重复是指大概的位置和形状、大小差不多即可。在有些情况下，为了布线或者开孔的需要，形状可能略有不同，如在不同的位置有开孔。
在一些示例中，第一颜色子像素210为红色子像素R。第二颜色子像素对220中的第一子像素22-1和第二子像素22-2对应为绿色子像素G1和G2。第三颜色子像素230为蓝色子像素B。但不限于此，各颜色子像素的颜色可以互换。
可以理解的是，请参阅图3，在AMOLED显示基板或与其类似的主动发光式显示基板中，各子像素均包括发光器件0220以及与发光器件0220耦接的像素电路0221。像素电路0221能够驱动发光器件0220发光。发光器件0220通常包括依次层叠设置的阳极、发光层和阴极。发光器件0220中与像素电路0221耦接的电极表现为对应子像素的像素电极，该电极例如为阳极。以下以像素电极是阳极为例进行说明。
示例的，如图3中所示，像素电路0221包括驱动电路0222、第一发光控制电路0223、第二发光控制电路0224、数据写入电路0225、存储电路0226、阈值补偿电路0227和复位电路0228。驱动电路0222包括控制端、第一端和第二端，且被配置为对发光器件0220提供驱动其发光的驱动电流。
第一发光控制电路0223与第一电压端VDD、驱动电路0222的第一端分别耦接，且被配置为实现驱动电路0222和第一电压端VDD之间的连接导通或断开。第二发光 控制电路0224与驱动电路0222的第二端、发光器件0220的阳极分别耦接，且被配置为实现驱动电路0222和发光器件0220之间的连接导通或断开。数据写入电路0225与驱动电路0222的第一端耦接，且被配置为在栅扫描信号的控制下将数据信号写入存储电路0226。存储电路0226与驱动电路0222的控制端、第一电压端VDD分别耦接，且被配置为存储数据信号。阈值补偿电路0227与驱动电路0222的控制端、驱动电路0222的第二端分别耦接，且被配置为对驱动电路0222进行阈值补偿。复位电路0228与驱动电路0222的控制端、发光器件0220的阳极耦接，且配置为在复位控制信号的控制下对驱动电路0222的控制端和发光器件0220的阳极进行复位。
可选的，如图3所示，驱动电路0222包括驱动晶体管T1。驱动电路0222的控制端为驱动晶体管T1的控制极，驱动电路0222的第一端为驱动晶体管T1的第一极，驱动电路0222的第二端为驱动晶体管T1的第二极。数据写入电路0225包括数据写入晶体管T2。存储电路0226包括电容器C。阈值补偿电路0227包括补偿晶体管T3。第一发光控制电路0223包括第一发光控制晶体管T4。第二发光控制电路0224包括第二发光控制晶体管T5。复位电路0228包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
数据写入晶体管T2的第一极与驱动晶体管T1的第一极耦接，数据写入晶体管T2的第二极被配置为与数据线Vd耦接以接收数据信号，数据写入晶体管T2的控制极被配置为与第一栅扫描信号线Ga1耦接以接收扫描信号。电容器C的第一极与第一电压端VDD耦接，电容器C的第二极与驱动晶体管T1的控制极耦接。补偿晶体管T3的第一极与驱动晶体管T1的第二极耦接，补偿晶体管T3的第二极与驱动晶体管T1的控制极耦接，补偿晶体管T3的控制极被配置为与第二栅扫描信号线Ga2耦接以接收补偿控制信号。第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1耦接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的控制极耦接，第一复位晶体管T6的控制极被配置为与第一复位控制信号线Rst1耦接以接收第一子复位控制信号。第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2耦接以接收第二复位信号，第二复位晶体管T7的第二极与发光器件0220的第一电极耦接，第二复位晶体管T7的控制极被配置为与第二复位控制信号线Rst2耦接以接收第二子复位控制信号。第一发光控制晶体管T4的第一极与第一电压端VDD耦接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极耦接，第一发光控制晶体管T4的控制极被配置为与第一发光控制信号线EM1耦接以接收第一发光控制信号。第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极耦接，第二发光控制晶体管T5的第二极与发光器件0220的阳极耦接，第二发光控制晶体管T5的控制极被配置为与第二发光控制信号线EM2耦接以接收第二发光控制信号。发光器件0220的阴极与第二电压端VSS耦接。
此处，第一电压端VDD和第二电压端VSS中的一者为高压端，另一者为低压端。例如，第一电压端VDD为电压源以输出恒定的第一电压，第一电压为正电压。第二电压端VSS为电压源以输出恒定的第二电压，第二电压为负电压等。或者，还例如，第一电压端VDD为电源信号线，该电源信号线例如为位于不同层且互连的第一电源信号线和第二电源信号线。第二电压端VSS接地。
在一些示例中，扫描信号和补偿控制信号可以相同。
可选的，数据写入晶体管T2的控制极和补偿晶体管T3的控制极耦接到同一条信号线，例如第一栅扫描信号线Ga1，以接收相同的信号(例如，扫描信号)。这样显示基板中可以不设置第二栅扫描信号线Ga2，以减少信号线的总数量。
可选的，数据写入晶体管T2的控制极和补偿晶体管T3的控制极分别耦接至不同的信号线，即数据写入晶体管T2的控制极耦接到第一栅扫描信号线Ga1，补偿晶体管T3的控制极耦接到第二栅扫描信号线Ga2，第一栅扫描信号线Ga1和第二栅扫描信号线Ga2二者传输相同的信号。
在另一些示例中，扫描信号和补偿控制信号不相同，以使得数据写入晶体管T2的控制极和补偿晶体管T3的控制极可以被分开单独控制，从而增加像素电路的控制灵活性。
同理，在一些示例中，第一发光控制信号和第二发光控制信号相同。
可选的，第一发光控制晶体管T4的控制极和第二发光控制晶体管T5的控制极耦接到同一条信号线，例如第一发光控制信号线EM1，以接收相同的信号(例如，第一发光控制信号)。这样显示基板中可以不设置第二发光控制信号线EM2，以减少信号线的总数量。
可选的，第一发光控制晶体管T4的控制极和第二发光控制晶体管T5的控制极分别耦接至不同的信号线。第一发光控制晶体管T4的控制极耦接到第一发光控制信号线EM1，第二发光控制晶体管T5的控制极耦接到第二发光控制信号线EM2，第一发光控制信号线EM1和第二发光控制信号线EM2传输相同的信号。
在另一些示例中，第一发光控制晶体管T4和第二发光控制晶体管T5为不同类型的晶体管，例如，第一发光控制晶体管T4为P型晶体管，而第二发光控制晶体管T5为N型晶体管。第一发光控制信号和第二发光控制信号不相同，本公开的实施例对此不作限制。
同理，在一些示例中，第一子复位控制信号和第二子复位控制信号相同。
可选的，第一复位晶体管T6的控制极和第二复位晶体管T7的控制极耦接到同一条信号线，例如第一复位控制信号线Rst1，以接收相同的信号(例如，第一子复位控制信号)。这样显示基板中可以不设置第二复位控制信号线Rst2，以减少信号线的总数量。
可选的，第一复位晶体管T6的控制极和第二复位晶体管T7的控制极分别耦接至不同的信号线。第一复位晶体管T6的控制极耦接到第一复位控制信号线Rst1，第二复位晶体管T7的控制极耦接到第二复位控制信号线Rst2，第一复位控制信号线Rst1和第二复位控制信号线Rst2传输相同的信号。
在另一些示例中，第一子复位控制信号和第二子复位控制信号也可以不相同。
此外，在一些示例中，第二子复位控制信号可以与扫描信号相同。例如第二复位晶体管T7的控制极可以耦接到第一栅扫描信号线Ga1以接收扫描信号Ga1作为第二子复位控制信号。
此外，第一复位晶体管T6的第一极耦接的第一复位电源端Vinit1、和第二复位晶体管T7的第一极耦接的第二复位电源端Vinit2，可以为直流参考电压端，以输出恒定 的直流参考电压。第一复位电源端Vinit1和第二复位电源端Vinit2可以相同，例如第一复位晶体管T6的第一极和第二复位晶体管T7的第一极连接到同一复位电源端。第一复位电源端Vinit1和第二复位电源端Vinit2可以为高压端，也可以为低压端，只要其能够提供第一复位信号和第二复位信号以对驱动晶体管T1的控制极和发光器件0220的阳极进行复位即可，本公开实施例对此不作限制。例如，第一复位晶体管T6的第一极和第二复位晶体管T7的第一极可以分别连接至复位电源信号线Init。
需要说明的是，图3所示的像素电路0221中的驱动电路0222、数据写入电路0225、存储电路0226、阈值补偿电路0227和复位电路0228仅为示意性的，驱动电路0222、数据写入电路0225、存储电路0226、阈值补偿电路0227和复位电路0228等电路的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不作具体限定。
例如，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管。为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型MOS晶体管)为例详细阐述了本公开的技术方案。也就是说，在本公开实施例的描述中，驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型MOS晶体管)实现本公开实施例中的一个或多个晶体管的功能。
需要说明的是，本公开实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的第一极、第二极在结构上可以是对称的，所以其第一极、第二极在物理结构上可以是没有区别的。在本公开实施例中，晶体管的栅极为其控制极，第一极为源极或漏极中的一者，第二极为源极或漏极中的另一者。本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
需要说明的是，在本公开实施例中，像素电路0221除了可以为图3所示的7T1C(即七个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
发光器件0220的像素电极与像素电路0221耦接，其形状可以根据实际需求设计，以便于优化像素电路0221的布线设计，并确保各子像素具有较高的分布密度，从而能够提升显示装置的显示效果。
在一些实施例中，请参阅图2B和图4，在子像素组200的至少两个子像素中，例如第二颜色子像素对220中的第一子像素22-1和第二子像素22-2中，像素电极包括互连的主体部和连接部。第二颜色子像素对220中的第一子像素22-1和第二子像素22-2为：多个第一子像素22-1和多个第二子像素22-2中距离最近的第一子像素22-1和第二子像素22-2，且该第一子像素22-1和第二子像素22-2沿第二方向排列。
前述主体部的形状与其所在的发光器件0220的有效发光区的形状大致相同，主体部的部分边缘为像素电极的对应边缘，也即主体部与其像素电极的部分边界重合。连接部与主体部连接的部分设置有凹口。例如，主体部包括顺次连接的第一边、第二边和第三边，其中，第三边沿第二方向延伸；第二边与连接部连接，第一边与连接部之间具有间隔，也即第一边不与连接部连接。这样从第一边上的任一点到连接部的沿第 二方向延伸且在第一方向上远离第三边的边缘上任一点的连接直线，与主体部、连接部围成的区域为凹口所在的区域，即凹口区。此处，第一边、第二边和第三边可以为直边，也可以为折边；以其是否与连接部连接作为区分。
图2B中各子像素的像素电极与图4中同颜色子像素的像素电极的结构相同，不过其形状略有不同。例如，图2B中各像素电极的连接部的形状较为规则；图4中各像素电极的连接部的形状具有较大的弯曲弧度。本公开实施例对此不作限定。
示例的，如图2B和图4所示，在第二颜色子像素对220中，第一子像素22-1的像素电极221-1包括主体部221-11和连接部221-12。该连接部221-12包括：与其主体部221-11连接的弯曲部2-1，以及与弯曲部2-1连接的补偿部2-2。主体部221-11、弯曲部2-1和补偿部2-2为一体结构。补偿部2-2沿第二方向延伸。补偿部2-2的沿第一方向的最大尺寸D2max大于弯曲部2-1的沿第一方向的最大尺寸D1max。此处，弯曲部2-1位于主体部221-11和补偿部2-2之间，其与主体部221-11、补偿部2-2互连的过渡处可以圆滑处理。弯曲部2-1的沿第一方向的最大尺寸为其沿第一方向的截面尺寸。如此，与补偿部2-2相比，弯曲部2-1可以具有更小的线宽。
在第一子像素22-1中，主体部221-11包括顺次连接的第一边a2-1、第二边b2-1和第三边c2-1。第三边c2-1沿Z方向延伸，第二边b2-1与连接部221-12中的弯曲部2-1连接，第一边a2-1与连接部221-12之间具有间隔。从第一边a2-1上的任一点到连接部221-12的沿Z方向延伸且在X方向上远离第三边c2-1的边缘上任一点的连接直线，与主体部221-11、连接部221-12围成的区域为凹口区221-13。
此处，连接部221-12的沿Z方向延伸且在X方向上远离第三边c2-1的边缘上任一点，例如为弯曲部2-1的与补偿部2-2连接且在X方向上远离第三边c2-1的端点；或者为补偿部2-2的在X方向上远离第三边c2-1的自由端的端点；但并不限于此。
上述弯曲部2-1的线宽较小，有利于确保凹口区221-13在衬底基板100上的正投影面积较大。在一些示例中，凹口区221-13在衬底基板100上的正投影面积与弯曲部2-1在衬底基板100上的正投影面积之比的取值范围可以为0.2～5。例如，凹口区221-13在衬底基板100上的正投影面积与弯曲部2-1在衬底基板100上的正投影面积之比为0.2、1.5、3和5中的一者。如此，在第一子像素22-1中设置面积较大的凹口区221-13，可以避免在凹口区221-13设置金属图案，从而较好的提高显示基板10的透光率。
第二子像素22-2的像素电极221-2与第一子像素22-1的像素电极221-1二者在衬底基板100上的正投影面积不同，二者的结构对应不同。例如，第一子像素22-1和第二子像素22-2中的至少一个子像素的连接部和主体部在沿第一方向延伸的直线上的两个正投影至少部分不交叠。
示例的，如图2B和图4中所示，第二子像素22-2的像素电极221-2包括主体部221-21和连接部221-22。主体部221-21和连接部221-22为一体结构。主体部221-21包括顺次连接的第一边a2-2、第二边b2-2和第三边c2-2，其中，第三边c2-2沿Z方向延伸，第二边b2-2与连接部221-22连接，第一边a2-2与连接部221-22之间具有间隔。连接部221-22的至少一侧边缘可以弯曲设置，例如连接部221-22的在X方向上远离第三边c2-2的边缘弯曲设置。从主体部221-21的第一边a2-2上的任一点到连接部221-22的沿Z方向延伸且在X方向上远离第三边c2-1的边缘上任一点的连接直线， 与主体部221-21、连接部221-22围成凹口区221-23。同理，在第二子像素22-2中设置凹口区221-23，可以避免在该凹口区221-23设置金属图案，从而进一步提高显示基板10的透光率。
可选的，请继续参阅图2B和图4，第二子像素22-2中像素电极221-2的连接部221-22在第二方向上的最大尺寸，小于或等于第一子像素22-1中像素电极221-1的弯曲部2-1在第二方向上的最大尺寸。如此，在第二子像素22-2中的像素电极221-2的主体部221-21与第一子像素22-1中的像素电极221-1的主体部221-11的尺寸大致相同的情况下，第二子像素22-2中像素电极221-2在第二方向上的尺寸、小于第一子像素22-1中像素电极221-1在同一方向上的尺寸。
请结合图2A理解，在沿第二方向(例如Z方向)相邻的任两排第二颜色子像素对220中，第二排R2的第二颜色子像素对220与第一排R1的第二颜色子像素对220沿第一方向(例如X方向)错位。第二排R2的第二颜色子像素对220中的第一子像素22-1的像素电极221-1的连接部221-12延伸位于第一排R1的第二颜色子像素对220中对应相邻的两个第二子像素22-2的像素电极221-2之间。例如，第二排R2的第二颜色子像素对220中第一子像素22-1的像素电极221-1的弯曲部2-1与第一排R1的第二颜色子像素对220中第二子像素22-2的像素电极221-2的连接部221-22大致位于沿第一方向延伸的一条直线上。第二排R2的第二颜色子像素对220中第一子像素22-1的像素电极221-1的补偿部2-2位于第一排R1的第二颜色子像素对220中对应相邻的两个第二子像素22-2的像素电极221-2的主体部221-21之间。这样，第一排R1的第二颜色子像素对220中的第二子像素22-2的像素电极221-2在沿第二方向延伸的直线上的正投影、位于第二排R2的第二颜色子像素对220中的第一子像素22-1的像素电极221-1在同一直线上的正投影内。
请结合图5理解，第二颜色子像素对220中第一子像素22-1和第二子像素22-2的像素电极采用如上设计，利于在每个子像素组200对应的空间内沿第一方向并列排布四个像素电路0221。从而能够在提升子像素分布密度的基础上，简化显示基板10中像素电路0221整体的版图设计。
在一些实施例中，第一颜色子像素210的像素电极211和第三颜色子像素230的像素电极231，也可以参照上述第二子像素22-2中像素电极221-2的结构设计。
例如，如图2B和图4所示，第一颜色子像素210的像素电极211包括互连的主体部2111和连接部2112。主体部2111和连接部2112为一体结构。主体部2111包括顺次连接的第一边a1-1、第二边b1-1和第三边c1-1，其中，第三边c1-1沿Z方向延伸，第二边b1-1与连接部2112连接，第一边a1-1与连接部2112之间具有间隔。连接部2112的至少一侧的边缘可以弯曲设置，例如连接部2112的在X方向上远离第三边c1-1的边缘弯曲设置。从主体部2111的第一边a1-1上的任一点到连接部2112的沿Z方向延伸且在X方向上远离第三边c1-1的边缘上任一点的连接直线，与主体部2111、连接部2112围成凹口区2113。
例如，如图2B和图4所示，第三颜色子像素230的像素电极231包括互连的主体部2311和连接部2312。主体部2311和连接部2312为一体结构。主体部2311包括顺次连接的第一边a3-1、第二边b3-1和第三边c3-1，其中，第三边c3-1沿Z方向延 伸，第二边b3-1与连接部2312连接，第一边a3-1与连接部2312之间具有间隔。连接部2312的至少一侧的边缘可以弯曲设置，例如连接部2312的在X方向上远离第三边c3-1的边缘弯曲设置。从主体部2311的第一边b3-1上的任一点到连接部2312的沿Z方向延伸且在X方向上远离第三边c1-1的边缘上任一点的连接直线，与主体部2311、连接部2312围成凹口区2313。
由此，在第一颜色子像素210中设置凹口区2113，在第三颜色子像素230中设置凹口区2313，还可以进一步的提高显示基板10的透光率。
此外，如图2B所示，每个子像素组200中，第一颜色子像素210中的连接部2112位于其主体部2111的靠近第二颜色子像素对220的一侧。第二颜色子像素对220中第一子像素22-1和第二子像素22-2的阳极的面积不同。第二颜色子像素对220中的连接部221-12和221-22分别位于其主体部的远离第一颜色子像素210的一侧。例如，第一子像素22-1和第二子像素22-2中的至少一个子像素的连接部和主体部在沿第一方向延伸的直线上的投影至少部分不交叠。第三颜色子像素230中的连接部2312在沿第一方向延伸的直线上的正投影位于其主体部2311在同一直线上的正投影内。例如，第三颜色子像素230的第三有效发光区2300的沿第二方向的中心线穿过其主体部2311和连接部2312。
每个子像素组200中，各子像素的像素电极的主体部的形状与对应有效发光区的形状大致相同，且各子像素的像素电极的主体部在衬底基板100上的正投影面积大于对应有效发光区在衬底基板100上的正投影面积。例如，各子像素的像素电极的主体部的几何中心与对应有效发光区的几何中心大致重合。例如，第一颜色子像素210的像素电极211的主体部2111和第三颜色子像素230的像素电极231的主体部2311的形状大致为六边形或者椭圆形，第二颜色子像素对220中第一子像素22-1和第二子像素22-2的像素电极的主体部的形状大致为五边形、圆形或者水滴形。
在一些实施例中，多个像素电路0221沿第一方向排列构成排，沿第二方向排列构成列。像素电路0221中的各晶体管采用顶栅结构，且其中的部分晶体管还可以为双栅结构，例如补偿晶体管T3和第一复位晶体管T6。但并不仅限于此。以下以此为例，对显示基板10中的各层结构进行示意说明。在晶体管采用其他结构的情况下，显示基板10中的各层结构可以据此作适应性调整。
图5为本公开一些实施例中多个子像素俯视结构的示意图。图6A～图6I为子像素制作过程中部分层俯视结构的示意图，其中以第一颜色子像素210、第二颜色子像素对220中的第二子像素22-2、第三颜色子像素230以及相邻错行的另一个第二颜色子像素对220中的第一子像素22-1对应的四个相邻的像素电路为例，且以一个子像素包括的像素电路0221的各晶体管的位置进行示意，其他子像素中像素电路0221包括的部件与该子像素包括的各晶体管的位置大致相同。
此外，显示基板10通常包括位于衬底基板100和像素电极之间的多个层，该多个层包括至少一个金属层以及至少一个绝缘层。显示基板10中的各层结构，请结合图7A～图7G中所示的层理解。本公开实施例对一种显示基板10的层结构进行了剖面示意，但并限于此。根据像素电路结构的不同，显示基板10的层结构也可以做适应性变型。
如5所示，像素电路0221包括如图4所示的驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7和电容器C；其中，电容器C与驱动晶体管T1的位置存在交叠，未标记示意。
图6A示出了显示基板10中一种半导体图案层310的俯视结构。半导体图案层310可采用半导体材料图案化形成。半导体图案层310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7中的有源层。半导体图案层310包括各子像素的各晶体管的有源层图案(沟道区)和掺杂区图案(源漏掺杂区)，且同一像素电路中的各晶体管的有源层图案和掺杂区图案一体设置。
需要说明的是，有源层可以包括一体形成的低温多晶硅层，其源极区域和漏极区域可以通过掺杂等进行导体化获得。由此，每个子像素的各晶体管的有源层为由p-硅形成的整体图案。同一像素电路中的各晶体管均包括掺杂区图案(即源极区域和漏极区域)和有源层图案，不同晶体管的有源层之间由掺杂结构隔开。
例如，半导体图案层310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，沿第一方向排列的不同颜色子像素的像素电路中的有源半导体层没有连接关系，彼此断开。沿第二方向排列的子像素的像素电路中的有源半导体层可以为一体设置，也可以彼此断开。
图6B示出了显示基板10中一种第一栅金属层320的俯视结构。第一栅金属层320为图案化的金属薄膜。半导体图案层310上形成有栅极绝缘层160。第一栅金属层320位于栅极绝缘层160上，与半导体图案层310绝缘设置。
示例的，第一栅金属层320用于制作上述的驱动晶体管T1、数据写入晶体管T2、补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7各晶体管中的栅极，以及电容器C的第一极CC1。
此处，与像素电路0221中各晶体管的栅极耦接的扫描信号线Ga(包括第一栅扫描信号线Ga1和第二栅扫描信号线Ga2)、复位控制信号线Rst(包括第一复位控制信号线Rst1和第二复位控制信号线Rst2)、发光控制信号线EM(包括第一发光控制信号线EM1和第二发光控制信号线EM2)等信号线，也可以由该第一栅金属层320制作形成。
在一些示例中，第一栅扫描信号线Ga1和第二栅扫描信号线Ga2为同一条信号线Ga，第一复位控制信号线Rst1和第二复位控制信号线Rst2为同一条信号线Rst，第一发光控制信号线EM1和第二发光控制信号线EM2为同一条信号线EM，但不限于此。
示例的，显示基板10还包括：多条沿第一方向延伸的信号线。第一子像素22-1的像素电极221-1在衬底基板上的正投影与位于同一层的至少三条信号线在衬底基板100上的正投影交叠。例如，复位控制信号线、栅扫描信号线和发光控制信号线同层设置，三者均沿第一方向延伸，并沿第二方向排列。第一子像素22-1的像素电极221-1在衬底基板上的正投影与一条复位控制信号线、一条栅扫描信号线和一条发光控制信号线在衬底基板100上的正投影交叠。
示例的，如图6B中的各虚线框所示，数据写入晶体管T2的栅极可以为扫描信号线Ga与半导体图案层310交叠的部分。第一发光控制晶体管T4的栅极可以为发光控制信号线EM与半导体图案层310交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线EM与半导体图案层310交叠的第二部分。第一复位晶体管T6的栅极为复位控制信号线Rst与半导体图案层310交叠的第一部分。第二复位晶体管T7的栅极为复位控制信号线Rst与半导体图案层310交叠的第二部分。阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为扫描信号线Ga与半导体图案层310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从扫描信号线Ga突出的突出结构P与半导体图案层310交叠的部分。结合图3理解可知，驱动晶体管T1的栅极可为电容器C的第一极CC1。
需要说明的是，半导体图案层310中与晶体管的栅极正对的部分为晶体管的沟道，每个沟道的两侧的半导体图案部分通过离子掺杂等工艺导体化后，可以作为对应晶体管的第一极和第二极。
此外，例如图6B中所示，扫描信号线Ga、复位控制信号线Rst和发光控制信号线EM沿第一方向(X方向)排列。扫描信号线Ga位于复位控制信号线Rst和发光控制信号线EM之间。这样对于每个像素电路0221，在第二方向上，电容器C的第一极CC1(即驱动晶体管T1的栅极)位于扫描信号线Ga和发光控制信号线EM之间。从扫描信号线Ga突出的突出结构P位于扫描信号线Ga的远离发光控制信号线EM的一侧。数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧。第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。
此处，驱动晶体管T1的栅极的第一侧和第二侧为在第二方向上驱动晶体管T1的栅极的彼此相对的两侧。例如，在XZ面内，驱动晶体管T1的栅极的第一侧可以为驱动晶体管T1的栅极的上侧，驱动晶体管T1的栅极的第二侧可以为驱动晶体管T1的栅极的下侧。可选的，显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管T1的栅极的下侧为其更靠近IC的一侧。驱动晶体管T1的栅极的上侧为其下侧的相对侧，例如为驱动晶体管T1的栅极的更远离IC的一侧。
对于每个像素电路0221，在第一方向上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。此处，驱动晶体管T1的栅极的第三侧和第四侧为在第一方向X上驱动晶体管T1的栅极的彼此相对的两侧。例如，在图6B所示的XZ面内，驱动晶体管T1的栅极的第三侧可以为驱动晶体管T1的栅极的左侧，驱动晶体管T1的栅极的第四侧可以为驱动晶体管T1的栅极的右侧。
需要补充的是，像素电路0221的结构可以为图6B所示结构的镜像结构，即像素电路0221的各层结构均以驱动晶体管T1的沟道区为基准，进行左右两侧结构的翻转。因此，上述栅极的左侧和右侧的关系可以是相反的。
图6C示出了显示基板10中一种第二栅金属层330的俯视结构。第二栅金属层 330为图案化的金属薄膜。前述的第一栅金属层320上形成有第一层间绝缘层150。第二栅金属层330位于第一层间绝缘层150上，与第一栅金属层320绝缘设置。
示例的，第二栅金属层330用于制作电容器C的第二极CC2、复位电源信号线Init以及遮光部S。电容器C的第二极CC2与电容器C的第一极CC1在衬底基板100上的正投影至少部分重叠，以形成电容器C。可选的，电容器C的第二极CC2上设有开口，该开口在衬底基板100上的正投影位于电容器C的第一极CC1在衬底基板100上的正投影内；电容器C的第二极CC2中开口以外的部分在衬底基板100上的正投影与电容器C的第一极CC1在衬底基板100上的正投影部分交叠。
此外，示例的，如图6C中所示，电容器C的第二极CC2由第二栅金属层330制作形成。这样，在同一排的像素电路0221中，将各电容器C的第二极CC2互连，可以减小第二栅金属层330中对应金属连线的电阻，从而能够减小电源电压的电压降(IR DROP)。
此外，在一些示例中，补偿晶体管T3采用双栅型晶体管，其两个沟道之间的半导体图案部分在补偿晶体管T3关闭时处于浮置(floating)状态，易受周围线路电压的影响而跳变，从而会影响补偿晶体管T3的漏电流，进而影响发光亮度。为了保持补偿晶体管T3的两个沟道之间的半导体图案部分电压稳定，设计遮光部S与位于补偿晶体管T3的两个沟道之间的半导体图案部分形成电容器，并利用遮光部S连接至第二电源信号线，可以获得恒定电压，从而确保处于浮置状态的半导体图案部分的电压可以保持稳定。遮光部S在衬底基板100上的正投影与位于补偿晶体管T3的两个沟道之间的半导体图案部分在衬底基板100上的正投影交叠，还可以防止该半导体图案部分因光照而出现电学特性改变的问题。
示例的，第二栅金属层330上沿远离衬底基板100的方向依次层叠形成有第二层间绝缘层140和第一金属层。图6D示出了显示基板10中一种第一金属层340的俯视结构。图6E示出了第一金属层340与半导体图案层310、第一栅金属层320、第二栅金属层330之间实现电连接所需的多个导通孔的分布。图6E’示出了第一金属层340和图6E中各导通孔之间的相对位置。第一金属层340为图案化的金属薄膜。第一金属层340可用于制作数据线Vd、第二电源信号线500、第一转接电极341、第二转接电极342以及驱动电极343。数据线Vd和第二电源信号线500均沿第二方向延伸，且同一个像素电路0221对应的数据线Vd和第二电源信号线500之间具有间隔。
如图6D、图6E和图6E’中所示，数据线Vd通过贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140的导通孔381与数据写入晶体管T2的第二极T2-2电连接。第二电源信号线500通过贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140的导通孔382与第一发光控制晶体管T4的第一极T4-1电连接。第二电源信号线500和数据线Vd沿第一方向交替设置。第二电源信号线500通过贯穿第二层间绝缘层140的导通孔3831与电容器C的第二极CC2电连接。第二电源信号线500通过贯穿第二层间绝缘层140的导通孔3832与遮光部S电连接，以向遮光部S提供恒定电压。第一转接电极341的一端通过贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140中的导通孔384与补偿晶体管T3的第二极电连接。第一转接电极341的另一端通过贯穿第一层间绝缘层150和第二层间绝缘层140中的导通孔 385与驱动晶体管T1的栅极(即电容器C的第一极CC1)电连接。第二转接电极342的一端通过贯穿第二层间绝缘层140中的导通孔386与复位电源信号线Init电连接。第二转接电极342的另一端通过贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140中的导通孔387与第二复位晶体管T7的第一极电连接。驱动电极343通过贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140中的导通孔388与第二发光控制晶体管T5的第二极电连接。
在一些示例中，如图6E’中所示，数据线Vd包括沿第二方向延伸的本体610，以及在第一方向上向对应的像素电路0221凸起的凸部620。可选的，导通孔381在衬底基板100上的正投影与凸部620在衬底基板100上的正投影的交叠面积，可以为导通孔381在衬底基板100上的正投影面积的70％～100％，例如为70％、80％或100％。这也就是说，数据线Vd与像素电路0221的电连接，主要是通过其凸部620与像素电路0221的电连接实现。如此，可以在数据线Vd本体610的线宽较窄的情况下，利用凸部620确保数据线Vd与像素电路0221之间实现良好的电连接。
示例的，第一金属层340上沿远离衬底基板100的方向可以依次层叠形成有钝化层123和第一平坦层122，以对第一金属层340进行绝缘保护。但并不限于此。例如，钝化层123和第一平坦层122的位置可以互换；或者，第一金属层340的远离衬底基板100的一侧仅设置第一平坦层122，而没有钝化层123。
以下以第一金属层340上层叠形成有钝化层123和第一平坦层122，且第一平坦层122位于钝化层123的远离衬底基板100的一侧为例进行说明。
示例的，第一平坦层122上形成有第二金属层。图6F示出了显示基板10中一种第二金属层350的俯视结构。图6G示出了第二金属层350与第一金属层340之间实现电连接所需的多个导通孔的分布。图6G’示出了第二金属层350和图6G中各导通孔之间的相对位置。第二金属层350为图案化的金属薄膜。第二金属层350可用于制作第一电源信号线400和连接电极450。连接电极450与第一金属层340中的驱动电极343一一对应地设置，且连接电极450通过贯穿第一平坦层122和钝化层123的导通孔352与驱动电极343电连接。
示例的，第二金属层350上沿远离衬底基板100的方向依次层叠形成有第二平坦层121和像素电极层360。图6H示出了第二平坦层121中多个导通孔的分布。图6H’示出了第二金属层350和第二平坦层121中的各导通孔之间的相对位置。图6I示出了像素电极层360中各像素电极的分布。图6I’示出了像素电极层360、第二金属层350以及第一导通孔H1、第二导通孔H2之间的位置关系。此处，第一导通孔H1为贯穿第二平坦层121中的导通孔1210。第二导通孔H2为贯穿第一平坦层122和钝化层123的导通孔352。像素电极层360为图案化的金属薄膜。像素电极层360可用于制作各子像素中的像素电极。按照前述子像素组200中各子像素的排列，各子像素中像素电极的结构如前所述。像素电极通过贯穿第二平坦层121中的导通孔1210与连接电极450电连接。
在一些实施例中，请结合图2A和图6I’理解，沿第一方向位于同一排的多个像素电路对应的第一导通孔H1在衬底基板100上的正投影沿第一直线L1延伸排列。沿第一方向位于同一排的多个像素电路对应的多个第二导通孔H2在衬底基板100上的正 投影沿第二直线L2延伸排列。沿第一方向位于同一排的多个像素电路对应的第一子像素22-1的有效发光区2201和第二子像素22-2的有效发光区2202，分别位于第一直线L1的两侧。同一个连接电极450对应的第一导通孔H1和第二导通孔H2在衬底基板上的正投影之间具有间隔D2。如此，在制作第二导通孔H2、连接电极450和第一导通孔H1的过程中，可以避免因第一导通孔H1和第二导通孔H2在衬底基板100上的正投影有交叠而出现如下问题，例如：第二金属层350在第二导通孔H2处凹陷，第二平坦层121不能被完全刻蚀，以及像素电极层360在第一导通孔H1处凹陷等；从而有利于确保像素电极层360中像素电极的平坦度，以及像素电极与连接电极450之间的电连接性能，以提升显示基板的显示效果。
需要补充的是，钝化层123和第一平坦层122依次层叠形成在各晶体管的远离衬底基板的表面上，第二导通孔H2贯穿第一平坦层122和钝化层123，其具有一定的孔深。在形成第二金属层350后，第二金属层350容易在第二导通孔H2处凹陷。第二平坦层121形成在第二金属层350的远离衬底基板100的表面上，第二平坦层121通常难以完全填平第二金属层350在第二导通孔H2处的凹陷。由此，若形成在第二平坦层121中的第一导通孔H1与第二导通孔H2在衬底基板100上的正投影有交叠，容易导致后续像素电极层360中的像素电极在第一导通孔H1处出现较为严重的下沉问题。本公开实施例通过设置第一导通孔H1和第二导通孔H2在衬底基板上的正投影之间具有间隔D2，可以有效改善如上问题。
此外，如图2A和图6I’中所示，可选的，沿第二方向位于同一列的多个像素电路对应的第一导通孔H1在衬底基板100上的正投影沿第三直线L3排列。可选的，同一个连接电极450对应的第一导通孔H1在衬底基板100上的正投影和第二导通孔H2在衬底基板100上的正投影沿第三直线L3排列。如此，第一导通孔H1和第二导通孔H2在显示基板10中呈阵列状分布，方便制作，也有利于简化相应掩膜板的版图设计。
可以理解的是，在一些示例中，第一导通孔H1在衬底基板100上的正投影和第二导通孔H2在衬底基板100上的正投影的形状和面积大致相同。此处，第一导通孔H1和第二导通孔H2的形状可以采用规则的矩形或圆形，从而方便于确定连接电极450与像素电极、以及连接电极450与驱动电极343之间的搭接面积，以保障像素电极与像素电路之间的连接线(例如连接电极450与驱动电极343)具有较小的电阻值。
在一些实施例中，连接电极450在衬底基板100上的正投影和驱动电极343在衬底基板100上的正投影的形状大致相同。可选的，连接电极450在衬底基板100上的正投影的面积大于驱动电极343在衬底基板100上的正投影面积。例如，驱动电极343在衬底基板100上的正投影位于对应的连接电极450在衬底基板100上的正投影内，且二者正投影的一部分边界重合或大致重合。例如，连接电极450在衬底基板100上的正投影与驱动电极343在衬底基板100的正投影具有非交叠部分，第一导通孔H1在衬底基板100上的正投影与所述非交叠部分具有交叠。从而方便于沿第一方向和第二方向在一条直线上排列第一导通孔H1和第二导通孔H2，合理提升显示基板的空间利用率，以使得显示基板具有较高的光透光率。
在一些实施例中，请结合图6I’和图8理解，驱动电极343通过贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140中的导通孔388与第二发光控制晶体 管T5的第二极电连接。以该贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140中的导通孔388为第三导通孔H3，同一个驱动电极343对应的第三导通孔H3、第二导通孔H2和第一导通孔H1在衬底基板100上的三个正投影中的两两之间具有间隔。
可选的，第一导通孔H1和第二导通孔H2中任一在衬底基板100上的正投影至对应子像素的有效发光区之间距离B1大于2μm，其取值范围例如为：2μm～20μm。示例的，如图8中所示，第一导通孔H1和第二导通孔H2中任一在衬底基板100上的正投影至对应子像素的有效发光区K之间的距离B1大于或等于2.5μm。
可选的，第一导通孔H1和第二导通孔H2中至少一者在衬底基板100上的正投影、至对应第三导通孔H3在衬底基板100上的正投影之间的最小间隔大于0.8μm，其取值范围例如为：0.8μm～10μm。第一导通孔H1和第二导通孔H2在衬底基板100上的正投影之间的最小间隔大于1μm，其取值范围例如为：1μm～10μm。示例的，如图8中所示，第一导通孔H1在衬底基板100上的正投影至对应第二导通孔H2在衬底基板100上的正投影之间的最小间隔B2为1.2μm；第二导通孔H2在衬底基板100上的正投影至对应第三导通孔H3在衬底基板100上的正投影之间的最小间隔B3为0.9μm。第一导通孔H1和第二导通孔H2在第二方向上沿一条直线延伸排列，第一导通孔H1在衬底基板100上的正投影至对应第三导通孔H3在衬底基板100上的正投影之间的最小间隔为2.1μm(0.9μm+1.2μm)。
在制作第三导通孔H3、驱动电极343和第二导通孔H2的过程中，可以避免因第二导通孔H2和第三导通孔H3在衬底基板100上的正投影有交叠而出现如下问题，例如：第一金属层340在第三导通孔H3处凹陷，钝化层123和第一平坦层122不能被完全刻蚀，以及连接电极450在第二导通孔H2处凹陷等；从而有利于确保连接电极450的平坦度，以及连接电极450与驱动电极343之间的电连接性能，以提升显示基板的显示效果。
此外，可选的，第三导通孔H3在衬底基板100上的正投影形状可以与前述第一导通孔H1、第二导通孔H2的形状大致相同。例如，第三导通孔H3的形状可以采用规则的矩形或圆形。
可选的，沿第二方向位于同一列的多个像素电路对应的第三导通孔H3在衬底基板100上的正投影沿同一直线延伸排列。
可选的，沿第一方向位于同一排的多个像素电路对应的第三导通孔H3在衬底基板100上的正投影沿同一直线延伸排列。
如此，在一些实施例中，多个第三导通孔H3在显示基板10中呈阵列状分布，不仅方便于制作，也利于实现其与第二导通孔H2、第一导通孔H1之间相对分布位置的设计，以合理提升显示基板的空间利用率，使得显示基板具有较高的光透光率。
此外，在一些实施例中，以贯穿栅极绝缘层160、第一层间绝缘层150和第二层间绝缘层140的导通孔381为第四导通孔H4。沿第二方向位于同一列的多个像素电路对应的第四导通孔H4在衬底基板100上的正投影可以沿同一直线延伸排列，以方便制作，并合理提升显示基板的空间利用率，使得显示基板具有较高的光透光率。
在一些实施例中，如图6G’中所示，第一电源信号线400包括多条沿第一方向延 伸的第一子电源信号线410以及多条沿第二方向延伸的第二子电源信号线420。第一子电源信号线410与第二子电源信号线420互连。也即，第一电源信号线400呈网格状分布。
请结合图5和图6G’理解，同一个第二颜色子像素对220中，第一子像素22-1的有效发光区和第二子像素22-2的有效发光区之间具有间隔。第一子电源信号线410在衬底基板100上的正投影，穿过第一子像素22-1的有效发光区和第二子像素22-2的有效发光区之间的间隔。这也就是说，在同一个第二颜色子像素对220中，第一子像素22-1和第二子像素22-2之间有效发光区的间隔在沿第二方向延伸的直线上的正投影、与该第二颜色子像素对中有效发光区在同一直线上的正投影无交叠。
在一些示例中，第一颜色子像素210的第一有效发光区2100和第三颜色子像素230的第三有效发光区2300中的至少一者在衬底基板100上的正投影的中心位于第一子电源信号线410在衬底基板100上的正投影内。也即，第一子电源信号线410可以作为第一有效发光区2100和第三有效发光区2300的对称中心，以使得第一有效发光区2100和第三有效发光区2300中位于第一子电源信号线410两侧的部分具有相一致的应用环境，从而确保第一有效发光区2100和第三有效发光区2300出射的光线强度均一化，以改善色偏。
在一些示例中，同一个第二颜色子像素对220中的第一子像素22-1和第二子像素22-2的两个有效发光区在衬底基板上的正投影，至对应的第一子电源信号线410在衬底基板100上的正投影之间的两个距离之比的取值范围为0.9～1.1。也即，在同一个第二颜色子像素对220中，第一子像素22-1的第一子有效发光区2201和第二子像素22-2的第二子有效发光区2202至同一条第一子电源信号线410的距离大致相同。例如，第一子像素22-1的第一子有效发光区2201和第二子像素22-2的第二子有效发光区2202以第一子电源信号线410为中心对称设置。这样第二颜色子像素对220中的两个有效发光区不仅具有相同的出光面积，还可以相对于第一子电源信号线410具有相一致的应用环境，以改善色偏。
至少一条第二子电源信号线420具有断口421，即第二子电源信号线420不是连续的信号线。第二子电源信号线420包括彼此断开的多个信号线段，沿其延伸方向，任相邻的两个信号线段之间的间隔即为上述断口421。第二颜色子像素对220中第一子像素22-1和第二子像素22-2的有效发光区及其间隔位于该断口421处。例如，第二子电源信号线420在衬底基板100上的正投影、不贯穿第一子像素22-1和第二子像素22-2的有效发光区及其间隔在衬底基板100的正投影。断口421的在第二方向上的两个端点之间的虚拟连线在衬底基板100上的正投影、贯穿第一子像素22-1和第二子像素22-2的有效发光区及其间隔在衬底基板100的正投影。
可选的，具有断口421的第二子电源信号线420与对应第二颜色子像素对中的两个有效发光区及其间隔在衬底基板上的正投影均没有交叠。
可选的，第一电源信号线400在衬底基板100上的正投影，与第二颜色子像素对220中第一子像素22-1和第二子像素22-2的有效发光区在衬底基板100上的正投影无交叠。也即，第二颜色子像素对220中第一子像素22-1和第二子像素22-2的有效发光区在衬底基板100上的正投影，可以与第二子电源信号线420中对应断口421在 衬底基板100上的正投影有交叠，但与第一子电源信号线410、第二子电源信号线420的实体部分在衬底基板100上的正投影均无交叠。如此有利于提高第二颜色子像素对220中位于有效发光区内且位于像素电极的远离衬底基板100一侧的的膜层的平坦性，从而尽量避免第二颜色子像素对220在显示时发生色偏。
此外，第二子电源信号线420和第二电源信号线500的延伸方向相同。第二子电源信号线420通过贯穿第一平坦层122和钝化层123的导通孔352与第二电源信号线500电连接。从而可以实现第二电源信号线500与第一电源信号线400的并联，以减小第二金属层350中金属连线的电阻，从而能够减小电源电压的电压降(IR DROP)。
可选的，第二电源信号线500和与其耦接的第二子电源信号线420在衬底基板100上的正投影至少部分交叠。第二电源信号线500在衬底基板100上的正投影，与第二颜色子像素对220中第一子像素22-1和第二子像素22-2的有效发光区在衬底基板100上的正投影部分重叠。例如，第二子电源信号线420在衬底基板100上的正投影位于第二电源信号线500在衬底基板100上的正投影内。例如，第二电源信号线500可以与第二子电源信号线420的除了断口421以外的部分大致重合，但第二子电源信号线420的线宽有部分调整而未与第二电源信号线500完全重合，例如，第二电源信号线500与第二子电源信号线420交叠部分的面积占第二电源信号线500在衬底基板100上正投影面积的70％以上。
可选的，第二子电源信号线420在其延伸方向上的不同位置处，第二子电源信号线420在第一方向上的宽度略有不同，例如，第二子电源信号线420在对应某些颜色子像素的位置处的宽度减小。同理，第二电源信号线500在其延伸方向上的不同位置处的沿第一方向上的宽度略有不同。
在一些示例中，第二电源信号线500和第二子电源信号线420中线宽较宽的部分相一致。请结合图6G’理解，这样以贯穿第一平坦层122和钝化层123的导通孔352为第五导通孔H5，沿第一方向位于同一排的多个第五导通孔H5在衬底基板100上的正投影可以沿第四直线L4排列。此外，第五导通孔H5在衬底基板100的正投影到任一有效发光区在衬底基板100的正投影的距离大于2.5um。
在一些实施例中，位于第一颜色子像素210的第一有效发光区2100两侧且与第一有效发光区2100相邻的两条第二子电源信号线420，距离该第一有效发光区2100的沿第二方向延伸的中心线的距离不相等。例如，第二子电源信号线420与第一有效发光区2100在第一方向上相邻且距离第一有效发光区2100的沿第二方向延伸的中心线的距离大于另一条与第一有效发光区2100在第一方向上相邻的第二子电源信号线420。
基于此，显示基板10还包括与第一电源信号线400同层设置的多个垫块430，以及与垫块430同层设置的多个支撑部440。前述的第二金属层350还可以用于制作垫块430和支撑部440。垫块430沿第二方向延伸，且与第一子电源信号线410对应耦接。垫块430位于第一有效发光区2100与第二子电源信号线420之间。垫块430可以采用沿第二方向延伸的长条结构。垫块430沿第二方向的两端分别通过支撑部440与第二子电源信号线对应耦接，形成封闭的环状结构。可选的，垫块430在衬底基板100上的正投影的中心位于第一子电源信号线410在衬底基板100上的正投影内。也即，第一子电源信号线410可以为垫块430的对称中心。第一有效发光区2100在第一方向 上至分别位于其两侧的垫块430和第二子电源信号线420的距离大致相同，例如二者距离之比的取值范围为0.9～1.1，从而可以确保第一有效发光区2100的两侧具有较为一致的应用环境，第一有效发光区2100出射的光线强度均一化，有利于改善色偏。
此外，垫块430与第一电源信号线400电连接，可以防止垫块430处于浮置(floating)状态，进而影响发光器件0220的正常工作。
可选的，垫块430在衬底基板100上的正投影与第一有效发光区2100在衬底基板上的正投影无交叠，可以防止垫块430影响第一颜色子像素210的显示。
可选的，垫块430与第一颜色子像素210的像素电极211在衬底基板100上的正投影没有交叠，或者两者交叠的面积很小，有利于减少色偏。
可选的，垫块430沿第二方向的尺寸大于其沿第一方向的尺寸。垫块430沿第二方向的尺寸小于第一有效发光区2100沿同一方向上的尺寸。本公开实施例中的显示基板应用于屏下指纹检测时，垫块430沿第二方向的尺寸可以设计的小于第一有效发光区在同一方向上的尺寸，以提高显示基板的光透过率。
在一些实施例中，沿垂直于衬底基板100的方向，从衬底基板100到像素电极层360之间的各个膜层中，像素电极的凹口区的至少部分区域与各金属层中的金属图案均没有交叠，以使得该部分区域的光透过率大于60％。
可选的，沿垂直于衬底基板100的方向，从衬底基板100到像素电极层360之间的各个膜层中，凹口区的至少部分区域与各金属层中的金属图案、半导体图案层中的半导体图案都没有交叠，以使得该部分区域的光透过率大于70％。
如此，在显示基板10应用于光学屏下指纹检测时，可以利用凹口区的透光部分进行光线的反射，以便于实现指纹纹路的探测。需要说明的是，显示基板10中还可以存在有其他可透光的区域，例如：沿垂直于衬底基板100的方向，任一不与显示基板中10的各金属层存在交叠的区域。本公开实施例对此不再详述。
光学屏下指纹检测技术通常采用显示基板10发出的光作为光源，指纹传感器通常设置在显示基板的非显示侧，例如可以位于发光器件0220的靠近衬底基板100的一侧，以实现屏下指纹检测功能。
例如，各子像素发出的光可以用于显示以及作为屏下指纹检测的光，子像素远离衬底基板100的一侧还可以设置用于放置手指的顶膜层。采集指纹图像的指纹传感器可以与各子像素设置于显示基板10的同一侧，且指纹传感器设置于各子像素中发光器件0220的靠近衬底基板100的一侧，用于检测从顶膜层的表面的指纹反射的反射光。指纹传感器可以包括多个阵列排布的检测单元。为了实现屏下指纹检测功能，上述顶层膜和衬底基板等膜层的至少部分是透明的，并且相邻的子像素之间设置有透光区域，以使顶层膜表面的指纹的反射光可以入射到指纹传感器上，以获取指纹图像。由于各子像素的发光器件的阳极容易影响光透过率，进而影响到指纹检测的灵敏度。因此，在发光器件的像素电极中设置凹口，可以有效提升显示基板中的光透过率。
需要补充的是，在一些实施例中，在第一子像素22-1和第二子像素22-2的两个像素电路中，与驱动晶体管T1的控制极的电位相同的金属包括：位于第一栅金属层320中的电容器C的第一极CC1，以及位于第一金属层340中的第一转接电极341。以每个像素电路中电容器C的第一极CC1和第一转接电极341在衬底基板100上的 正投影为第一投影，第一子像素22-1的像素电极在衬底基板100上的正投影和该第一投影交叠的投影面积为第一面积，第二子像素22-2中像素电极在衬底基板100上的正投影和该第一投影交叠的投影面积为第二面积，则第一面积和第二面积的面积比的取值范围可以为：0.8～1.2。也即，第一面积和第二面积大致相同。如此，有利于确保第一子像素22-1和第二子像素22-2的两个像素电路的负载相一致，从而避免出现第一子像素22-1和第二子像素22-2出光亮度不均匀的问题。
由于每个像素电路中电容器C的第一极CC1在衬底基板100上的正投影和第一转接电极341在衬底基板100上的正投影部分重叠，且第一子像素22-1和第二子像素22-2中的两个像素电极的形状不同，因此，可选的，第一子像素22-1的像素电极221-1与电容器C的第一极CC1二者在衬底基板100上的正投影交叠的面积，小于第二子像素22-2的像素电极221-2与电容器C的第一极CC1二者在衬底基板100上的正投影交叠的面积；且，第一子像素22-1的像素电极221-1与第一转接电极341二者在衬底基板100上的正投影交叠的面积，大于第二子像素22-2的像素电极221-2与第一转接电极341二者在衬底基板100上的正投影交叠的面积。
此外，在一些实施例中，如图9所示，第一子像素22-1的像素电极221-1的补偿部2-2包括：与弯曲部2-1电连接的第一补偿部2-21，以及位于第一补偿部2-21的远离弯曲部2-1的一侧且与第一补偿部2-21电连接的第二补偿部2-22。第一补偿部2-21和第二补偿部2-22可以采用沿第二方向延伸的长条状结构。第二补偿部2-22在衬底基板100上的正投影与电容器C的第一极CC1在衬底基板100上的正投影无交叠。第二补偿部2-22在第一方向上的尺寸小于第一补偿部2-21在同方向上的尺寸，有利于在显示基板10中获得更多的可透光区域，以提升显示基板10的光透过率。
此外，如图9所示，在一些示例中，第一子像素22-1中像素电极221-1的补偿部2-2位于相邻的第三颜色子像素230的像素电极231和第一颜色子像素210的像素电极211之间。第二补偿部2-22在第一方向上至第三颜色子像素230的像素电极231的第一距离W1，可以与其在第一方向上至第一颜色子像素210的像素电极211的第二距离W2大致相同。第一补偿部2-21在第一方向上至第三颜色子像素230的像素电极231的第三距离W3，可以与其在第一方向上至第一颜色子像素210的像素电极211的第四距离W4大致相同。第一距离W1大于第三距离W3，第二距离W2大于第四距离W4。例如，第二距离W2与第一距离W1之比的取值范围为0.9～1.1。示例的，第一距离W1的取值范围为4.5μm～6.5μm，其例如为5.47μm。第二距离W2的取值范围为4.5μm～6.5μm，其例如为5.73μm。第四距离W4与第三距离W3之比的取值范围为0.9～1.1。示例的，第三距离W3的取值范围为2.5μm～4.0μm，其例如为3.0μm。第二距离W2的取值范围为2.5μm～4.0μm，其例如为3.0μm。
显示基板10中各子像素的结构如上所述。在一些实施例中，通过减小各子像素中的位于有效发光区以外区域的电极面积，可以减小光线遮挡的面积，以提高显示基板的光透过率。例如，在保证各子像素的有效发光区的面积不变的情况下，通过改变像素电极中位于有效发光区以外区域的部分例如连接部的形状，也即，提升有效发光区与像素电极的面积比，可以减少像素电极对光线遮挡的影响，从而提升显示基板的光透过率。
示例的，第一颜色子像素210中，第一有效发光区2100与像素电极211的面积比的取值范围为53％～55％。第二颜色子像素对220中，第一子有效发光区2201和像素电极221-1的面积比的取值范围为43.5％～48％，第二子有效发光区2202和像素电极221-2的面积比的取值范围为43.5％～48％。第三颜色子像素230中，第三有效发光区2300与像素电极231的面积比的取值范围为67.5％～69％。例如，第一颜色子像素210中，第一有效发光区2100与像素电极211的面积比为54.9％。第二颜色子像素对220中，第一子有效发光区2201和像素电极221-1的面积比为47％，第二子有效发光区2202和像素电极221-2的面积比为47％。第三颜色子像素230中，第三有效发光区2300与像素电极231的面积比为68.3％。从而可以确保显示基板10整体具有良好的光透过率，进而提高指纹检测的灵敏度。
此外，可选的，第一有效发光区2100、第二颜色子像素对220的有效发光区以及第三有效发光区2300的面积比大致为1：1.27：1.47。第一颜色子像素210中的像素电极211、第二颜色子像素对220中的像素电极以及第三颜色子像素230中的像素电极231的面积比大致为1：1.48：1.18。此处，“面积比”是指在衬底基板上的正投影的面积之比。
为了清楚的说明本公开一些实施例中显示基板10的层结构，请参阅图7A，本公开一些实施例还对一种显示基板10中的多个局部区域进行了剖面示例。图7B为图7A所示的显示基板10中一种沿AA’向的剖面示意图。图7C为图7A所示的显示基板10中一种沿BB’向的剖面示意图。图7D为图7A所示的显示基板10中一种沿CC’向的剖面示意图。图7E为图7A所示的显示基板10中一种沿D-E-F-G-H向的剖面示意图。图7F为图7A所示的显示基板10中一种沿L-M-N向的剖面示意图。图7G为图7A所示的显示基板10中一种沿R-S-T向的剖面示意图。以下请结合图6A～图6I，以及图7A～图7G理解。
此处，图7B～图7G中的剖面图，均是以第一金属层340和第二金属层350之间形成有钝化层123和第一平坦层122、且第一平坦层122位于钝化层123的远离衬底基板100的一侧为例进行的示意。但不限于此。
请结合图7B～图7G理解，显示基板10还包括位于像素电极层360上的像素界定层130。像素界定层130具有多个用于限定子像素的有效发光区的开口。发光器件0220包括依次层叠设置的阳极、发光层以及阴极。该发光器件0220的阳极与像素电路0221耦接。像素界定层130中的开口暴露发光器件0220的阳极。发光器件0220的发光层的至少部分位于该开口内，且阴极位于像素界定层130面向衬底基板的一侧。当后续发光器件0220的发光层形成在像素界定层130的开口中时，发光层与阳极接触的部分能够在阳极和阴极的电压驱动下发光以形成有效发光区。
此处，“有效发光区”可以指二维的平面区域，该平面区域平行于衬底基板100。需要说明的是，像素界定层130的开口由于工艺原因，其远离衬底基板100的部分尺寸略大于靠近衬底基板100部分的尺寸，或者从靠近衬底基板100一侧到远离衬底基板100一侧的方向上呈现尺寸逐渐增加的形态，因此有效发光区的尺寸与像素界定层130中开口的不同位置的尺寸可能略有不同，但其整体区域形状和尺寸基本相当。例如，有效发光区在衬底基板100上的正投影与像素界定层130中对应开口在衬底基板100 上的正投影大致重合。例如，有效发光区在衬底基板100上的正投影完全落在像素界定层130中对应开口在衬底基板100上的正投影内，且二者形状相似，有效发光区在衬底基板100上的正投影面积相比像素界定层130中对应开口在衬底基板100上的正投影面积略小。
如图7A中所示，第二颜色子像素对220包括的第一子有效发光区2201和第二子有效发光区2202之间具有间隔。该“间隔”指像素界定层130限定的两个开口之间的像素界定层130的实体部分。
此外，在同一个第二颜色子像素对220中，第一子有效发光区2201和第二子有效发光区2202之间的间隔沿第二方向的尺寸小于第一有效发光区2100沿第二方向的尺寸，且该间隔沿第二方向的尺寸小于第三有效发光区2300沿第二方向的尺寸。
可选的，沿第二方向，第一有效发光区2100的尺寸大于第三有效发光区2300的尺寸。例如，第一有效发光区2100的尺寸可以为45～49微米，例如，可以为47微米；第三有效发光区2300的尺寸可以为38～42微米，例如，可以为40微米。
在一些示例中，如图7A所示，第一子有效发光区2201和第二子有效发光区2202的形状大致相同。第一子电源信号线410在衬底基板100上的正投影与第一子有效发光区2201、第二子有效发光区2202二者在衬底基板100上的两个正投影的两个中心之间的距离之比为0.9～1.1。例如，第一子电源信号线410在衬底基板100上的正投影与第一子有效发光区2201、第二子有效发光区2202二者在衬底基板100上的两个正投影的两个中心之间的距离大致相等。由此，第二颜色子像素对220包括的第一子有效发光区2201、第二子有效发光区2202二者相对于第一子电源信号线410对称分布，有利于确保第二颜色子像素对220包括的第一子像素22-1和第二子像素22-2的环境一致性。但并不限于此，例如，第一子电源信号线410在衬底基板100上的正投影也可以更靠近第二颜色子像素对220中之一。此外，可选的，第一子电源信号线410在衬底基板100上的正投影与第二颜色子像素对220中的第一子像素22-1和第二子像素22-2的像素电极在衬底基板100上的正投影不重叠。
上述正投影的中心指正投影形状的几何中心，有效发光区在衬底基板上的正投影的形状由有效发光区的形状决定，有效发光区的形状与其对应的像素界定层130的开口的形状大致相同。
例如，如图7A所示，第二颜色子像素对220包括的第一子有效发光区2201和第二子有效发光区2202的形状包括五边形、圆形或者水滴形。例如，图7A示意性的示出第一子有效发光区2201和第二子有效发光区2202的形状为五边形，五边形包括一组平行的对边(平行于第二方向)以及一条垂直边(平行于第一方向)，垂直边与一组平行的对边垂直，每个第二颜色子像素对220中的第一子有效发光区2201和第二子有效发光区2202的两条垂直边相邻设置。例如，第一子电源信号线410位于上述两条垂直边之间，且穿过上述两条垂直边之间的最短连线的中点。
此外，虽然在图7A中的第一子有效发光区2201和第二子有效发光区2202的形 状包括严格的由两条线段形成的角，但在一些实施例中，第一子有效发光区2201和第二子有效发光区2202的两条线段的交界形状可以均为圆角图形，例如圆形或者水滴形。也就是，在上述五边形形状的基础上，第一子有效发光区2201和第二子有效发光区2202的角被倒圆。例如，形成像素界定层130的开口时，开口的角落处的部分则可能会形成圆角形状，以使得形成的有效发光区的形状可能为圆角形状。
第二颜色子像素对220的一种局部剖面如图7B中所示。在第二颜色子像素对220中，发光层223和阴极层222依次层叠形成在像素界定层130的远离衬底基板100的表面上，并与像素界定层130中对应开口暴露的像素电极221接触连接。本公开一些实施例以第二颜色子像素对220包括的第一子像素22-1和第二子像素22-2中的发光层223是一体的为例进行描述，例如同一个第二颜色子像素对220中第一子像素22-1和第二子像素22-2的发光层223是连起来的整体膜层，即该第一子像素22-1和第二子像素22-2的发光层223是一个连续的完整的图形，或者同一个第二颜色子像素对220中的第一子像素22-1和第二子像素22-2的发光层223在衬底基板100上的正投影是连续完整的，该第一子像素22-1和第二子像素22-2的发光层223可以通过一个开口制作获得。但不限于此，例如，同一个第二颜色子像素对200包括的第一子像素22-1和第二子像素22-2的发光层也可以是分离的。
第一颜色子像素210的一种局部剖面如图7C和图7D中所示。在第一颜色子像素210中，发光层213和阴极层212依次层叠形成在像素界定层130的远离衬底基板100的表面上，并与像素界定层130中对应开口暴露的像素电极211接触连接。
第一颜色子像素210的又一种局部剖面如图7E中所示。在第一颜色子像素210中，像素电极211通过贯穿第二平坦层121的导通孔1210与连接电极450电连接。连接电极450通过贯穿第一平坦层122和钝化层123的导通孔351与驱动电极343电连接。驱动电极343通过贯穿第二层间绝缘层140、第一层间绝缘层150和栅极绝缘层160的导通孔388，与第二发光控制晶体管的第二极T5-2电连接。导通孔1210、导通孔351和导通孔388在衬底基板100上的正投影不交叠，且两两之间具有间隔。
第三颜色子像素230的局部剖面如图7F中所示。在第三颜色子像素230中，像素电极231在衬底基板100上的正投影与第一子电源信号线410在衬底基板100上的正投影部分重叠。发光层233和阴极层232依次层叠形成在像素界定层130的远离衬底基板100的表面上，并与像素界定层130中对应开口暴露的像素电极231接触连接。
第一子像素22-1的局部剖面如图7G中所示。在第一子像素22-1中，像素电极221-1包括主体部221-11、弯曲部2-21和补偿部2-22。发光层223-1和阴极层222-1依次层叠形成在像素界定层130的远离衬底基板100的表面上，并与像素界定层130中对应开口暴露的像素电极221-1的主体部221-11接触连接。在图7A的沿R-S向的剖面中，像素电极221-1的主体部221-11与弯曲部2-21之间，以及弯曲部2-21和补偿部2-22之间，均具有间隔。第一电源信号线400中的第二子电源信号线420，可以通过贯穿第一平坦层122和钝化层123的导通孔352与第二电源信号线500电连接。第二电源信号线500可以通过贯穿第二层间绝缘层140、第一层间绝缘层150和栅极绝缘层160的导通孔382，与第一发光控制晶体管的第一极T4-1电连接。
上述一些实施例中，栅极绝缘层160、第一层间绝缘层150、第二层间绝缘层160、 钝化层123、第一平坦层122和第二平坦层121等多层绝缘层，用于绝缘保护对应的导电层，例如金属层或半导体层。可选的，栅极绝缘层160、第一层间绝缘层150、第二层间绝缘层160以及钝化层123采用无机绝缘材料制作形成，例如氮化硅或氧化硅。第一平坦层122和第二平坦层121采用有机绝缘材料制作形成，例如有机绝缘树脂。
本公开另一实施例提供一种显示装置，包括上述任一显示基板。该显示装置可以尽量避免色偏现象的发生，也可以应用指纹检测技术，且该显示装置具有较高的指纹检测灵敏度。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种显示基板，包括：
    衬底基板；
    多个子像素，所述子像素包括像素电极和有效发光区；所述像素电极包括互连的主体部和连接部；所述主体部与所述有效发光区的形状相同，且所述主体部与所述像素电极的至少部分边界重合；多个所述子像素至少包括发光颜色相同的一个第一子像素和一个第二子像素；距离最近的所述第一子像素和所述第二子像素沿第二方向排列；
    其中，所述第一子像素和所述第二子像素的两个像素电极在所述衬底基板上的正投影的面积不同；所述第一子像素和所述第二子像素中的至少一个子像素的连接部和主体部在沿第一方向延伸的直线上的两个正投影至少部分不交叠；
    所述第二子像素的像素电极在沿所述第二方向延伸的直线上的正投影，位于所述第一子像素的像素电极在同一直线上的正投影内；
    所述第二方向与所述第一方向相交，且二者夹角的取值范围为80°～100°。
  2. 根据权利要求1所述的显示基板，其中，
    所述主体部包括顺次连接的第一边、第二边和第三边；所述第三边沿所述第二方向延伸；
    所述连接部与所述第二边连接，且与所述第一边之间具有间隔；
    从所述第一边上的任一点到所述连接部的沿所述第二方向延伸且在所述第一方向上远离所述第三边的边缘上任一点的连接直线，与所述主体部、所述连接部围成的区域为凹口区。
  3. 根据权利要求2所述的显示基板，还包括位于所述衬底基板和所述像素电极之间的多个层；所述多个层中包括至少一个金属图案；
    其中，沿垂直于所述衬底基板的方向，从所述衬底基板到所述像素电极之间的各个层中，所述凹口区的至少部分区域与所述金属图案没有交叠。
  4. 根据权利要求2所述的显示基板，还包括位于所述衬底基板和所述像素电极之间的多个层；所述多个层中包括半导体图案和至少一个金属图案；
    其中，沿垂直于所述衬底基板的方向，从所述衬底基板到所述像素电极之间的各个层中，所述凹口区的至少部分区域与所述半导体图案、所述金属图案均没有交叠。
  5. 根据权利要求2所述的显示基板，其中，所述第一子像素中像素电极的连接部包括：弯曲部、以及与所述弯曲部连接的补偿部；
    所述补偿部沿所述第二方向延伸；所述弯曲部与所述第二边连接；所述弯曲部与所述第一边之间具有间隔。
  6. 根据权利要求5所述的显示基板，其中，所述凹口区与所述弯曲部在所述衬底基板上的两个正投影的面积之比的取值范围为0.2～5。
  7. 根据权利要求5所述的显示基板，其中，所述补偿部的沿所述第一方向的最大尺寸大于所述弯曲部的沿所述第一方向的最大尺寸。
  8. 根据权利要求5所述的显示基板，其中，所述第二子像素中像素电极的连接部的沿所述第二方向的最大尺寸，小于或等于所述第一子像素中像素电极的弯曲部的沿所述第二方向的最大尺寸。
  9. 根据权利要求1所述的显示基板，其中，所述子像素还包括像素电路；所述像素电路包括驱动晶体管；
    与所述驱动晶体管的控制极的电位相同的金属图案在所述衬底基板上的正投影为第一投影；所述第一子像素中像素电极在所述衬底基板上的正投影和所述第一子像素对应的第一投影交叠的面积为第一面积；所述第二子像素中像素电极在所述衬底基板上的正投影和所述第二子像素对应的第一投影交叠的面积为第二面积；所述第一面积和所述第二面积之比的取值范围为：0.8～1.2。
  10. 根据权利要求9所述的显示基板，还包括：位于所述衬底基板和所述像素电极之间的第一栅金属层，以及位于所述第一栅金属层和所述像素电极之间的第一金属层；
    与所述驱动晶体管的控制极的电位相同的金属图案，包括：位于所述第一栅金属层中的电容器的第一极，以及位于所述第一金属层中的第一转接电极；
    其中，所述第一子像素的像素电极与对应的所述电容器的第一极在所述衬底基板上的正投影交叠的面积，小于所述第二子像素的像素电极与对应的所述电容器的第一极在所述衬底基板上的正投影交叠的面积；且，所述第一子像素的像素电极与对应的所述第一转接电极在所述衬底基板上的正投影交叠的面积，大于所述第二子像素的像素电极与对应的所述第一转接电极在所述衬底基板上的正投影交叠的面积。
  11. 根据权利要求1～10中任一项所述的显示基板，还包括：多条沿所述第一方向延伸的信号线；所述第一子像素的像素电极在所述衬底基板上的正投影与位于同一层的至少三条信号线在所述衬底基板上的正投影交叠。
  12. 根据权利要求11所述的显示基板，其中，所述位于同一层的至少三条信号线，包括：至少一条栅扫描信号线、至少一条发光控制信号线、以及至少一条复位控制信号线。
  13. 根据权利要求1～12中任一项所述的显示基板，还包括：第一绝缘层和多个连接电极；所述第一绝缘层位于所述像素电极和所述连接电极之间，且具有多个第一导通孔；所述像素电极通过所述第一导通孔与所述连接电极对应耦接；
    所述子像素还包括像素电路；多个所述像素电路沿所述第一方向排列构成排，沿所述第二方向排列构成列；
    其中，同一排的多个所述像素电路对应的多个所述第一导通孔在所述衬底基板上的正投影沿第一直线排列；在所述同一排的多个所述像素电路对应的多个子像素中，所述第一子像素的有效发光区与所述第二子像素的有效发光区分别位于所述第一直线的两侧。
  14. 根据权利要求13所述的显示基板，还包括：第二绝缘层和多个驱动电极；
    所述第二绝缘层位于所述连接电极和所述驱动电极之间，且具有多个第二导通孔；所述连接电极通过所述第二导通孔与所述驱动电极对应耦接；
    其中，同一个所述连接电极对应的所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影之间具有间隔。
  15. 根据权利要求14所述的显示基板，其中，同一排的多个所述像素电路对应的多个所述第二导通孔在所述衬底基板上的正投影沿第二直线排列。
  16. 根据权利要求14所述的显示基板，其中，所述第一导通孔和所述第二导通孔中任一在所述衬底基板上的正投影至对应子像素的有效发光区之间的距离大于2μm。
  17. 根据权利要求14～16中任一项所述的显示基板，其中，所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影的形状及面积大致相同；
    同一个所述连接电极对应的所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影沿第三直线排列。
  18. 根据权利要求17所述的显示基板，其中，所述驱动电极和所述连接电极在所述衬底基板上的正投影的形状大致相同，且所述连接电极在所述衬底基板上的正投影面积大于所述驱动电极在所述衬底基板上的正投影面积。
  19. 根据权利要求18所述的显示基板，其中，所述驱动电极在所述衬底基板上的正投影位于所述连接电极在所述衬底基板上的正投影内，且二者正投影的一部分边界重合或大致重合。
  20. 根据权利要求19所述的显示基板，其中，所述连接电极在所述衬底基板上的正投影与所述驱动电极在所述衬底基板的正投影具有非交叠部分，所述第一导通孔在所述衬底基板上的正投影与所述非交叠部分交叠。
  21. 根据权利要求14～20中任一项所述的显示基板，还包括：半导体图案层和第三绝缘层；所述半导体图案层位于所述衬底基板和所述驱动电极之间；所述第三绝缘层位于所述驱动电极和所述半导体图案层之间，且具有多个第三导通孔；所述驱动电极通过所述第三导通孔与所述半导体图案层中对应的部分耦接；
    其中，同一个所述驱动电极对应的所述第三导通孔、所述第二导通孔和所述第一导通孔在所述衬底基板上的三个正投影中的两两之间具有间隔。
  22. 根据权利要求21所述的显示基板，其中，
    所述第一导通孔和所述第二导通孔中任一在所述衬底基板上的正投影、至所述第三导通孔在所述衬底基板上的正投影之间最小间隔的取值范围为：0.8μm～10μm；
    所述第一导通孔和所述第二导通孔在所述衬底基板上的正投影之间最小间隔的取值范围为：1μm～10μm。
  23. 根据权利要求22所述的显示基板，还包括多条数据线；所述数据线与所述驱动电极同层设置；所述第三绝缘层还具有多个第四导通孔；所述数据线通过第四导通孔与对应的像素电路连接；
    所述数据线沿所述第二方向延伸，且所述数据线包括在所述第一方向上向对应的像素电路凸起的多个凸起部；所述第四导通孔在所述衬底基板上的正投影与所述凸起部在所述衬底基板上的正投影之间的交叠面积，为所述第四导通孔在所述衬底基板上的正投影面积的70％-100％。
  24. 根据权利要求14～23中任一项所述的显示基板，还包括多条电源信号线；多条所述电源信号线包括至少一条第一电源信号线；所述第一电源信号线与所述连接电极同层设置；
    所述第一电源信号线包括多条沿所述第一方向延伸的第一子电源信号线以及多条沿所述第二方向延伸的第二子电源信号线；所述第一子电源信号线与所述第二子电源信号线互连；
    距离最近的所述第一子像素和所述第二子像素的两个有效发光区之间具有间隔；所述第一子电源信号线在所述衬底基板上的正投影，穿过所述第一子像素和所述第二子像素的两个有效发光区之间的间隔处；
    至少一条所述第二子电源信号线具有至少一个断口；所述断口的在所述第二方向上的两个端点之间的虚拟连线在所述衬底基板上的正投影，贯穿所述第一子像素和所述第二子像素的两个有效发光区以及所述间隔在所述衬底基板上的正投影；
    具有所述断口的所述第二子电源信号线与所述第一子像素和所述第二子像素的两个有效发光区、以及所述间隔在所述衬底基板上的正投影均没有交叠。
  25. 根据权利要求24所述的显示基板，其中，多条所述电源信号线还包括多条第二电源信号线；所述第二电源信号线沿所述第二方向延伸；
    在所述显示基板还包括第二绝缘层和多个驱动电极的情况下，所述第二电源信号线与所述驱动电极同层设置；所述第二绝缘层还具有多个第五导通孔；所述第二子电源信号线通过所述第五导通孔与所述第二电源信号线对应耦接；
    所述第二电源信号线和与其耦接的所述第二子电源信号线在所述衬底基板上的正投影至少部分交叠；所述第二电源信号线在所述衬底基板上的正投影，与所述第一子像素和所述第二子像素中任一子像素的有效发光区在所述衬底基板上的正投影部分交叠。
  26. 根据权利要求25所述的显示基板，其中，沿所述第一方向位于同排的多个所述第五导通孔在所述衬底基板上的正投影位于沿所述第一方向延伸的第四直线上；
    所述第五导通孔在所述衬底基板的正投影到任一所述有效发光区在所述衬底基板的正投影的距离大于2.5um。
  27. 根据权利要求24～26中任一项所述的显示基板，其中，距离最近的所述第一子像素和第二子像素构成子像素对；
    一个子像素组包括沿所述第一方向依次排列的一个第一颜色子像素、一个所述子像素对以及一个第三颜色子像素；所述子像素对被配置为出射第二颜色光线；
    所述第一颜色子像素的第一有效发光区和所述第三颜色子像素的第三有效发光区中的至少一者在所述衬底基板上的正投影的中心位于对应的所述第一子电源信号线在所述衬底基板上的正投影内。
  28. 根据权利要求27所述的显示基板，其中，位于所述第一颜色子像素的第一有效发光区两侧且与所述第一有效发光区相邻的两条所述第二子电源信号线，距离所述第一有效发光区的沿所述第二方向延伸的中心线的距离不相等；
    所述显示基板还包括与所述第一电源信号线同层设置的多个垫块和多个支撑部；所述垫块沿所述第二方向延伸；所述垫块位于所述第一有效发光区和所述第二子电源信号线之间，且通过所述支撑部与所述第二子电源信号线对应耦接；与所述垫块耦接的所述第二子电源信号线与所述第一有效发光区的沿所述第二方向延伸的中心线之间的距离，大于另一条与所述第一有效发光区相邻的第二子电源信号线至所述中心线之间的距离；所述垫块还与所述第一子电源信号线对应耦接。
  29. 根据权利要求28所述的显示基板，其中，所述垫块的形状大致为长条形；所述垫块在所述衬底基板上的正投影的中心位于与其耦接的所述第一子电源信号线在所 述衬底基板上的正投影内。
  30. 根据权利要求27所述的显示基板，其中，所述第一子像素和所述第二子像素的两个有效发光区在所述衬底基板上的正投影，至位于所述两个有效发光区之间的所述第一子电源信号线在所述衬底基板上的正投影的两个距离之比的取值范围为0.9～1.1。
  31. 一种显示装置，包括权利要求1-30中任一项所述的显示基板。
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CN110265458A (zh) * 2019-06-27 2019-09-20 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板及显示装置

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CN114779537A (zh) * 2022-03-29 2022-07-22 厦门天马微电子有限公司 显示面板及显示装置
CN114779537B (zh) * 2022-03-29 2024-01-09 厦门天马微电子有限公司 显示面板及显示装置
WO2023231737A1 (zh) * 2022-05-31 2023-12-07 京东方科技集团股份有限公司 显示基板及显示装置
CN115346443A (zh) * 2022-09-06 2022-11-15 武汉天马微电子有限公司 显示面板和显示装置
CN115346443B (zh) * 2022-09-06 2024-01-30 武汉天马微电子有限公司 显示面板和显示装置

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