WO2022193315A1 - 触控显示基板及其制备方法、触控显示装置 - Google Patents

触控显示基板及其制备方法、触控显示装置 Download PDF

Info

Publication number
WO2022193315A1
WO2022193315A1 PCT/CN2021/081887 CN2021081887W WO2022193315A1 WO 2022193315 A1 WO2022193315 A1 WO 2022193315A1 CN 2021081887 W CN2021081887 W CN 2021081887W WO 2022193315 A1 WO2022193315 A1 WO 2022193315A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
touch
pin
sub
pin area
Prior art date
Application number
PCT/CN2021/081887
Other languages
English (en)
French (fr)
Inventor
刘果
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/630,517 priority Critical patent/US20230359300A1/en
Priority to PCT/CN2021/081887 priority patent/WO2022193315A1/zh
Priority to CN202180000536.1A priority patent/CN115668111A/zh
Publication of WO2022193315A1 publication Critical patent/WO2022193315A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a touch display substrate, a method for manufacturing the same, and a touch display device.
  • OLED Organic Light Emitting Diode
  • TFTs thin film transistors
  • An embodiment of the present disclosure provides a touch display substrate, including an effective area and a first peripheral area and a second peripheral area located around the effective area, wherein: the effective area includes a substrate and a display stacked on the substrate A unit and a touch unit, the display unit includes a plurality of data lines, a plurality of gate lines and a plurality of sub-pixels, the touch control unit includes a plurality of touch electrodes and a touch lead connected to the touch electrodes; the The first peripheral area includes a gate driving circuit connected to the plurality of gate lines; the second peripheral area includes a first binding area for binding the driving chip and a first binding area located far from the first binding area.
  • the first binding area includes a first gate drive circuit pin area and a first touch pin area
  • the second binding area includes a second gate driving circuit pin area electrically connected with the first gate driving circuit pin area, and a second touch pin area electrically connected with the first touch pin area
  • the second peripheral area further includes a touch test lead connecting the first touch pin area and the second touch pin area, and connecting the first gate driving circuit pin area and the second gate driving circuit pin and the orthographic projection of the array test leads on the substrate does not overlap with the orthographic projection of the touch test leads on the substrate.
  • the first binding area includes a first side edge, a second side edge opposite to the first side edge, and a connection between the first side edge and the second side edge
  • the third side and the fourth side the first side is located on the side close to the effective area, the second side is located on the side away from the effective area
  • the first gate driving circuit pin The area includes a first sub-gate driving circuit pin area, the first sub-gate driving circuit pin area is located on the side close to the first side, and the first sub-gate driving circuit pin area is disposed close to the third side or the fourth side
  • the first touch pin area includes a first sub-touch pin area, and the first sub-touch pin area is located close to the first touch pin area.
  • Three sides or one side of the fourth side, and the distance between the first sub-touch pin area and the second side is smaller than the distance between the first sub-gate driving circuit pin area and the second side. the distance between the second sides.
  • the first binding area further includes an input pin area and a first output pin area, wherein the input pin area is disposed close to the second side, and the first output pin area is The pin area is disposed close to the first side.
  • the first output pin area includes a first sub-output pin area and a void area on one side of the first sub-output pin area; the first binding area further includes a plurality of A first touch wire is connected to the touch electrodes in the effective area after extending from the first sub-touch pin area and passing through the void area.
  • the first binding area further includes a plurality of virtual pins, and the virtual pins are set at any one or more of the following positions: the first sub-touch pin area, at least one one side or both sides of the first touch leads.
  • the first sub-touch pin area includes a plurality of first touch pins, and one or more of the plurality of first touch pins are associated with the first touch pins. Lead connections.
  • the plurality of first touch pins includes two or more columns, and the first touch pins in each column and the first touch pins in adjacent columns They are staggered in the first direction.
  • the first touch pins in a plane perpendicular to the touch display substrate, include: a first metal layer disposed on the substrate, a first metal layer disposed on the first metal layer Two metal layers and a third metal layer disposed on the second metal layer; in a plane perpendicular to the touch display substrate, the first touch leads include: a first metal layer disposed on the base Floor.
  • the second binding area includes a fifth side, a sixth side opposite the fifth side, and a connection between the fifth side and the sixth side the seventh side and the eighth side, the fifth side is located on the side close to the first binding area, the sixth side is located on the side away from the first binding area;
  • the The second gate driving circuit pin area includes a third sub-gate driving circuit pin area, the second touch pin area includes a third sub-touch pin area; the third sub-gate driving circuit leads The foot area and the third sub-touch pin area are located on the side of the second binding area close to the seventh side, and between the third sub-gate drive circuit pin area and the seventh side The distance is smaller than the distance between the third sub-touch pin area and the seventh side.
  • the second binding area further includes a power supply pin area, wherein the power supply pin area is located in the third sub-gate driving circuit pin area and the third sub-touch between the pin areas.
  • the touch display substrate further includes a first power line and a second power line, the first power line extends from the power pin area to the effective area, the second power line
  • the power supply line extends from the power supply pin area to the first peripheral area; the orthographic projection of the array test lead on the substrate, and one of the first power supply line and the second power supply line or A plurality of orthographic projections on the substrate contain overlapping regions.
  • the second peripheral region includes a first region and a second region, the first region is located between the second bonding region and the second region, and the array test leads The distance from the touch test lead in the first area is smaller than the distance between the array test lead and the touch test lead in the second area.
  • an orthographic projection of one or more of the first power line and the second power line on the substrate is located where the array test leads are located. between the orthographic projection on the substrate and the orthographic projection of the touch test lead on the substrate.
  • An embodiment of the present disclosure further provides a touch display device, including the touch display substrate according to any one of the above.
  • An embodiment of the present disclosure also provides a method for manufacturing a touch display substrate, the touch display substrate includes an effective area, and a first peripheral area and a second peripheral area located around the effective area, the second peripheral area includes a In the first binding area for binding the driver chip and the second binding area on the side of the first binding area away from the effective area and used for binding the flexible circuit board, the first binding area includes a first binding area.
  • the preparation method includes: forming touch test leads and array test leads in the second peripheral area, wherein the touch The control test leads are connected to the first touch pin area and the second touch pin area, and the array test leads are connected to the first gate drive circuit pin area and the second gate drive circuit pin area, and the orthographic projection of the array test leads on the substrate does not overlap with the orthographic projection of the touch test leads on the substrate.
  • FIG. 1 is a schematic structural diagram of a touch display substrate according to an embodiment of the disclosure
  • Fig. 2 is the cross-sectional structure schematic diagram of the effective area in Fig. 1;
  • FIG. 3 is one of the schematic structural diagrams of the first binding area and the second binding area in FIG. 1;
  • FIG. 4 is the second schematic diagram of the structure of the first binding area and the second binding area in FIG. 1;
  • FIG. 5 is an enlarged schematic view of the touch pin area in FIG. 3 or FIG. 4;
  • FIG. 6 is a schematic cross-sectional structure diagram of the BB region in FIG. 5;
  • FIG. 7 is a schematic structural diagram of a touch area of a touch display substrate according to an embodiment of the disclosure.
  • FIG. 8 is a schematic structural diagram of a display area of a touch display substrate according to an embodiment of the disclosure.
  • FIG. 9 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 10 is a third schematic structural diagram of a first binding area and a second binding area according to an embodiment of the present disclosure.
  • FIG. 11 is a fourth schematic structural diagram of a first binding area and a second binding area according to an embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
  • connection includes a case where constituent elements are connected together by means of an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
  • TDDI Touch and Display Driver Integration
  • FIG. 1 is a schematic plan view of a touch display substrate according to an exemplary embodiment of the present disclosure.
  • the touch display substrate includes a base, an active area (AA) 100 disposed on the base, and an active area located on the base.
  • the effective area 100 includes a substrate (not shown in the figure), a display unit (not shown in the figure) and a touch control unit (not shown in the figure) stacked on the substrate, and the display unit includes a plurality of data lines (not shown in the figure), a plurality of gate lines (not shown in the figure) and a plurality of sub-pixels (not shown in the figure), the touch control unit includes a plurality of touch electrodes (not shown in the figure) and a touch control unit Touch traces connected to electrodes (not shown in the figure).
  • the effective area can be either the touch area of the touch unit or the display area of the display unit.
  • the touch area and the display area in the following description are both Refers to the effective area.
  • the second peripheral area 200 includes a first binding area 230 and a second binding area 240 located on the side of the first binding area 230 away from the effective area 100 .
  • the first binding area 230 is used for binding the driver chip, and the second binding area 240
  • the binding area 240 is used for binding a flexible printed circuit board (Flexible Printed Circuit, FPC), and provides driving signals for the pixel array in the display unit through the FPC and the driving chip, so as to realize image display and touch control.
  • FPC Flexible Printed Circuit
  • the display unit may include a driving circuit layer 102 disposed on a substrate 101 , a light emitting element 103 disposed on a side of the driving circuit layer 102 away from the substrate 101 , and a The light-emitting element 103 is far from the encapsulation layer 104 on the side of the substrate 101 .
  • the display unit may include other film layers, such as spacer columns, etc., which are not limited in this disclosure.
  • the substrate 101 may be a flexible substrate, or it may be a rigid substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be made of polymer.
  • the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • PI imide
  • PET polyethylene terephthalate
  • surface-treated soft polymer film the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit, and FIG. 2 takes the example of including one driving transistor and one storage capacitor in each sub-pixel for illustration.
  • the driving circuit layer 102 of each sub-pixel may include: a first insulating layer disposed on the substrate; an active layer disposed on the first insulating layer; and a second insulating layer covering the active layer The gate electrode and the first capacitor electrode arranged on the second insulating layer; the third insulating layer covering the gate electrode and the first capacitor electrode; the second capacitor electrode arranged on the third insulating layer; The fourth insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are provided with via holes, and the via holes expose the active layer; the source electrode and the drain electrode arranged on the fourth insulating layer, the source electrode and the The drain electrodes are respectively connected with the active layer through via holes; the flat layer covering the aforementioned
  • the light emitting element 103 may include an anode, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the anode is arranged on the flat layer, and is connected to the drain electrode of the driving transistor through the via hole opened on the flat layer;
  • the pixel definition layer is arranged on the anode and the flat layer, and a pixel opening is arranged on the pixel definition layer, and the pixel opening exposes the anode;
  • the organic The light-emitting layer is at least partially arranged in the pixel opening, and the organic light-emitting layer is connected to the anode;
  • the cathode is arranged on the organic light-emitting layer, and the cathode is connected to the organic light-emitting layer;
  • the encapsulation layer 104 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of The organic material, the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting element 103 .
  • the organic light-emitting layer of the OLED light-emitting element may include an emission layer (Emitting Layer, referred to as EML), and a hole injection layer (Hole Injection Layer, referred to as HIL), a hole transport layer (Hole Transport Layer, HTL for short), Hole Block Layer (HBL), Electron Block Layer (EBL), Electron Injection Layer (EIL), Electron Transport Layer (EIL) one or more film layers in ETL).
  • EML emission layer
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL Hole Block Layer
  • EBL Electron Block Layer
  • EIL Electron Injection Layer
  • EIL Electron Transport Layer
  • the light-emitting layers of OLED light-emitting elements of different colors are different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light emitting layer can use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light emitting layer can use a common layer.
  • any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer may be fabricated by one process (one evaporation process or one inkjet printing process), However, isolation is achieved by the surface step difference of the formed film layer or by means of surface treatment.
  • any one or more of the hole injection layer, hole transport layer, electron injection layer and electron transport layer corresponding to adjacent sub-pixels may be isolated.
  • the organic light-emitting layer may be formed by using a fine metal mask (FMM, Fine Metal Mask) or an open mask (Open Mask) evaporation deposition, or by using an inkjet process.
  • FMM fine metal mask
  • Open Mask Open Mask
  • the touch control unit may include a buffer layer 105 disposed on the side of the encapsulation layer 104 away from the substrate 101 , and disposed on the buffer layer 105 .
  • the touch electrode layer 106 on the side of the layer 105 away from the substrate 101 is disposed on the protective layer 107 on the side of the touch electrode layer 106 away from the substrate 101 .
  • a plurality of touch electrodes and touch traces may be disposed on the touch electrode layer 106 at the same layer.
  • the buffer layer 105 may adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite Floor.
  • the touch electrode layer 106 can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals
  • the protective layer 109 can be made of an organic material.
  • FIG. 3 and FIG. 4 are schematic diagrams of two structures of the first binding area 230 and the second binding area 240 in FIG. 1 .
  • the first bonding area 230 includes a first gate driving circuit pin area 231 for transmitting the driving signal of the driving chip to the gate driving circuit and a first gate driving circuit pin area 231 for sensing the touch electrodes The touch signal is transmitted to the first touch pin area 232 of the driver chip.
  • the second binding area 240 includes a second gate driving circuit pin area 241 for testing a plurality of gate lines and a second touch pin area 243 for testing a plurality of touch electrodes.
  • the second peripheral area 200 further includes touch test leads 236 for connecting the first touch pin area 232 and the second touch pin area 243, and for connecting the first gate driving circuit pin area 231 and the second touch pin area 231.
  • touch test leads 236 There are two array test leads 235 in the pin area 241 of the gate driving circuit, and the orthographic projection of the array test leads 235 on the substrate and the orthographic projection of the touch test leads 236 on the substrate do not overlap.
  • FIG. 3 and FIG. 4 do not illustrate all the touch test leads 236 and the array test leads 235 , but only illustrate Some of the touch test leads 236 and the array test leads 235 are shown, that is, the numbers of the touch test leads 236 and the array test leads 235 shown in FIGS. 3 and 4 do not represent the actual touch test leads 236 and array test leads. 235 quantity.
  • the orthographic projection of the array test leads 235 on the substrate and the orthographic projection of the touch test leads 236 on the substrate do not overlap, thereby avoiding the need for touch wiring and grid array wiring.
  • the problem of signal crosstalk caused by lines crossing each other improves touch performance.
  • the first binding area 230 includes a first side 2301 , a second side 2302 opposite to the first side 2301 , and a second side 2302 connected to the first side 2301
  • the third side 2303 and the fourth side 2304 between the second side 2302 and the first side 2301 are located on the side close to the effective area 100
  • the second side 2302 is located on the side away from the effective area 100 .
  • the first gate driving circuit pin area 231 includes a first sub gate driving circuit pin area 2311 and a second sub gate driving circuit pin area 2312 , the first sub-gate driving circuit pin area 2311 and the second sub-gate driving circuit pin area 2312 are located on the side close to the first side 2301, and the first sub-gate driving circuit pin area 2311 is close to the third The side 2303 is disposed, and the pin area 2312 of the second sub-gate driving circuit is disposed close to the fourth side 2304 .
  • the first touch pin area 232 includes a first sub touch pin area 2321 and a second sub touch pin area 2322 .
  • the first sub touch pin area 2322 The pin area 2321 is located on the side close to the third side 2303
  • the second sub-touch pin area 2322 is located on the side close to the fourth side 2304 .
  • the distance between the first sub-touch pin area 2321 and the second side edge 2302 is smaller than the distance between the first sub-gate driving circuit pin area 2311 and the second side 2302 .
  • the distance between the side edges 2302 ; the distance between the second sub-touch pin area 2322 and the second side edge 2302 is smaller than the distance between the second sub-gate driving circuit pin area 2312 and the second side edge 2302 .
  • the second binding area 240 includes a fifth side 2401 , a sixth side 2402 opposite to the fifth side 2401 , and a sixth side 2402 connected to the fifth side 2401
  • the seventh side 2403 and the eighth side 2404 between the sixth side 2402, the fifth side 2401 is located on the side close to the first binding area 230, and the sixth side 2402 is located away from the first binding area 230 side.
  • the second gate driving circuit pin area 241 includes a third sub-gate driving circuit pin area 2411 and a fourth sub-gate driving circuit pin area 2412
  • the second touch pin area 243 includes a third sub-touch pin area
  • the foot area 2431 and the fourth sub-touch pin area 2432 , the third sub-gate drive circuit pin area 2411 and the third sub-touch pin area 2431 are located at a portion of the second binding area 240 close to the seventh side 2403 .
  • the distance between the third sub-gate drive circuit pin area 2411 and the seventh side 2403 is smaller than the distance between the third sub-touch pin area 2431 and the seventh side 2403;
  • the fourth sub-gate The driving circuit pin area 2412 and the fourth sub-touch pin area 2432 are located on the side of the second bonding area 240 close to the eighth side 2404, and the fourth sub-gate driving circuit pin area 2412 and the eighth side
  • the distance between 2404 is smaller than the distance between the fourth sub-touch pin area 2432 and the eighth side 2404 .
  • the second binding area 240 further includes a power supply pin area 242 , wherein the power supply pin area 242 includes a first sub power supply pin area 2421 and a second sub power supply The pin area 2422, the first sub-power pin area 2421 is arranged between the third sub-gate drive circuit pin area 2411 and the third sub-touch pin area 2431, and the second sub-power pin area 2422 is arranged in the first sub-power pin area 2422. Between the four sub-gate driving circuit pin areas 2412 and the fourth sub-touch pin area 2432 .
  • the second binding area 240 further includes a power pin area 242 , wherein the power pin area 242 includes a first sub-power pin area 2421 and a second sub-power pin area 2421
  • the power supply pin area 2422, the first sub power supply pin area 2421 is arranged on the side of the third sub gate drive circuit pin area 2411 close to the seventh side 2403, and the second sub power supply pin area 2422 is arranged in the fourth sub
  • the gate driving circuit pin area 2412 is close to the side of the eighth side 2404 .
  • the first binding area 230 further includes an input pin area 233 and a first output pin area 234 , wherein the input pin area 233 is close to the second side 2302 is arranged, the first output pin area 234 is arranged close to the first side 2301, and the first output pin area 234 is arranged in the first sub-gate driving circuit pin area 2311 and the second sub-gate driving circuit pin area between 2312.
  • the first output pin area 234 includes a first sub output pin area 2341 , a second sub output pin area 2342 , and a first sub output pin area 2342 . 2341 and the gap area between the second sub-output pin area 2342 (not shown in the figure).
  • the first binding area 230 further includes a plurality of first touch leads 2381 and a plurality of second touch leads 2382. After the first touch leads 2381 extend from the first sub-touch pin area 2321 and pass through the gap area, It is connected to the touch electrodes 300 of the active area 100 ; the second touch leads 2382 are connected to the touch electrodes 300 of the active area 100 after extending from the second sub-touch pin area 2322 and passing through the gap area.
  • FIGS. 3 and 4 do not illustrate all the first touch leads 2381 and the second touch leads 2381 and 2382 .
  • the control lead 2382 only one of the first touch lead 2381 and the second touch lead 2382 is shown, that is, the first touch lead 2381 and the second touch lead 2382 shown in FIG. 3 and FIG. 4 .
  • the number of does not represent the actual number of the first touch leads 2381 and the second touch leads 2382 .
  • FIG. 5 is an enlarged schematic structural diagram of the touch pin area in FIG. 3 or FIG. 4 .
  • the first sub-touch pin area 2321 includes a plurality of first touch pins 23211 , and one or more of the plurality of first touch pins 23211 is associated with the first touch pin area 23211 .
  • a touch lead 2381 is connected.
  • the second sub-touch pin area 2322 includes a plurality of second touch pins (not shown in FIG. 5 ), and one or more of the plurality of second touch pins are associated with the first touch pins.
  • the two touch leads 2382 are connected.
  • the first binding area 230 further includes a plurality of virtual pins 23212, and the plurality of virtual pins 23212 can be set at any one or more of the following positions: the first sub-touch The pin area 2321 , the second sub-touch pin area 2322 , one or both sides of the plurality of first touch leads 2381 , and one or both sides of the plurality of second touch leads 2382 .
  • the first touch pins 23211 that are not connected to the first touch leads 2381 and the second touch pins that are not connected to the second touch leads 2382 constitute dummy pins, and the dummy pins are not Introduce electrical signals.
  • the driver chip or the FPC can be flatly bound on the touch display panel, and the wiring will not be crushed during the binding process.
  • the plurality of first touch pins 23211 includes two or more columns, and the first touch pins of each column and the first touch pins of adjacent columns are The feet are staggered in the first direction D1.
  • the plurality of second touch pins includes two or more columns, and the second touch pins of each column and the second touch pins of adjacent columns are in the first direction D1 presented in a staggered arrangement.
  • the bonding pitch (Margin) of each pin in the first direction is increased, so that the first The two sides of a touch pin or the second touch pin have more space for routing leads, so as to avoid a short circuit of multiple wires connected to the first touch pin or the second touch pin, resulting in abnormal display.
  • FIG. 6 is a schematic cross-sectional structure diagram of the BB region in FIG. 5 .
  • the first touch pins and the second touch pins both include: a first metal layer disposed on the substrate 101 M1, a second metal layer M2 disposed on the first metal layer M1, and a third metal layer M3 disposed on the second metal layer M2.
  • both the first touch lead and the second touch lead include: a first metal layer M1 disposed on the substrate 101 .
  • the first metal layer M1 may be disposed in the same layer as the first gate metal layer and/or the second gate metal layer of the active area.
  • the second metal layer M2 may be provided in the same layer as the source-drain metal layer of the active region.
  • the third metal layer M3 may be disposed on the same layer as the touch electrode layer in the active area.
  • the display unit may be a liquid crystal display unit or an OLED display unit or the like. This disclosure does not limit this.
  • the touch area includes a plurality of touch electrodes 300 arranged regularly.
  • the touch electrodes 300 may be rectangular and arranged in a matrix of M rows*N columns .
  • the touch area 100 may be divided into N electrode areas 110 and N lead areas 120 , the electrode areas 110 and the lead areas 120 are strip-shaped extending along the second direction D2 , the strip-shaped electrode areas 110 and the strip-shaped lead areas 120 are alternately arranged along the first direction D1, that is, except for the electrode regions and lead regions at the edge, one lead region 120 is arranged between two electrode regions 110, and one electrode region 110 is arranged between two lead regions 120.
  • Each electrode area 110 includes M touch electrodes 300 arranged in sequence along the second direction D2
  • each lead area 120 includes M touch traces 310 arranged in sequence along the first direction D1, and each touch trace 310
  • the first end is connected to a touch electrode 300, and the second end extends to the second peripheral area 200 along the second direction D2.
  • the touch electrodes 300 may have a regular pattern of about 4mm*4mm or 5mm*5mm, and the regular pattern may be a rectangle, a diamond, a triangle, a polygon, or the like.
  • the touch of a human finger will cause the self-capacitance of the corresponding touch electrode to change, and the external control device can determine the position of the finger according to the change of the capacitance of the touch electrode.
  • the second peripheral area 200 may include a wiring lead-out area 210 , a bending area 220 , The first binding area 230 and the second binding area 240 .
  • the lead-out area 210 can be provided with a plurality of broken lines, the first ends of the plurality of broken lines are respectively connected with the plurality of touch wires 310 in the touch area, and the second ends extend toward the bending area 220 and are respectively connected with the bending area 220 .
  • a plurality of connection lines provided in the area 220 are connected.
  • the bending area 220 is configured to bend the first binding area 230 and the second binding area 240 of the second peripheral area 200 to the back of the touch area 100 .
  • the first binding area 230 may be provided with a touch and display driver integration (Touch and Display Driver Integration, TDDI for short) circuit, a plurality of output lines and a plurality of input lines, and the TDDI circuit is used to control the touch and display functions.
  • the second binding area 240 can be set with a plurality of pins (PINs), the TDDI circuit is connected to some of the plurality of pins through a plurality of input lines, and the plurality of pins are configured to be bound to a flexible circuit board (FPC). Connect with external control device.
  • the first touch pin area includes a plurality of touch pins (not shown in FIG. 7 ), and the plurality of touch pins are connected to the aforementioned first touch leads 2381 or the second touch pins
  • the lead 2382 , the first touch lead 2381 and the second touch lead 2382 are respectively connected with a plurality of touch wires 310 in the active area, through the first touch wire 2381 or the second touch wire 2382 and the touch wire 310 Connect to the touch electrodes in the touch area.
  • the second touch pin area includes a plurality of touch test pins (not shown in FIG. 7 ), and the plurality of touch test pins are respectively associated with the plurality of touch test pins in the first touch pin area. touch pins are connected to test the touch electrodes.
  • the display area includes a plurality of sub-pixels 1 for displaying, each sub-pixel 1 is the smallest point that can independently emit light of the desired brightness and color, usually a plurality of sub-pixels 1 Pixel 1 can form a "pixel” that can display light of any color and brightness, and each "pixel" is a "dot" in the image to be displayed.
  • the display area is also provided with lead lines for providing driving signals for the sub-pixels 1 , such as data lines 81 for providing data signals (data voltages) for the sub-pixels 1 .
  • lead lines for providing driving signals for the sub-pixels 1 , such as data lines 81 for providing data signals (data voltages) for the sub-pixels 1 .
  • other leads such as gate lines 82 and gate lines 83 are also provided in the display area.
  • the first peripheral region 201 includes a gate driving circuit 2011 that is electrically connected to the plurality of gate lines 82 and is configured to connect to the plurality of gate lines 82 Provides gate drive signals.
  • the first peripheral region 201 further includes a gate driver circuit 2012 , which is electrically connected to the plurality of gate lines 83 and is configured to provide feedback to the plurality of control electrodes.
  • the pole line 83 provides the gate drive signal.
  • the sub-pixels 1 in the display area are arranged in a matrix, that is, arranged in multiple rows and columns.
  • the data lines 81 are parallel to the column direction, and each data line 81 is electrically connected to a column of sub-pixels 1;
  • the gate lines 82 are parallel to the row direction, and each gate line 82 is electrically connected to a row of sub-pixels 1;
  • the control electrode line They are all parallel to the row direction, and each control electrode line 83 is electrically connected to a row of sub-pixels 1 .
  • each data line 81 writes the data signal into each sub-pixel 1 electrically connected to the gate line 82 (for example, a row of sub-pixel 1), and stores the data signal in the storage capacitor Cst for the sub-pixel 1 to store in the storage capacitor Cst.
  • the remaining time of the frame is displayed according to the stored data signal.
  • the gate line 83 is used to control whether the sub-pixel 1 can emit light.
  • row and column are two opposite directions, and the two may be perpendicular to each other.
  • row direction is the horizontal direction (left and right direction)
  • column direction is the vertical direction (up and down direction) as an example for description 'But it should be understood that the horizontal and vertical directions are not restrictions on “row” and “column”, and “row” and “column” are not necessarily related to the placement position of the display unit.
  • each sub-pixel 1 is provided with a pixel circuit for making the sub-pixel 1 emit light.
  • the structure of the pixel circuit is a 7T1C structure, which includes a first transistor T1, a second transistor T2, a driving transistor T3 (third transistor), a fourth transistor T4, a fifth transistor T5, and a sixth transistor.
  • Transistor T6 seventh transistor T7, storage capacitor Cst, organic light emitting diode OLED, first reset terminal Reset, second reset terminal Reset', initialization terminal Vinit, gate line terminal Gate, data line terminal Data, control electrode line Terminal EM, positive terminal VDD, negative terminal VSS and other structures; wherein, each transistor can be a P-type transistor (eg PMOS) or an N-type transistor (eg NMOS).
  • the positive terminal VDD is electrically connected to the positive signal source (for example, connected through the positive wire)
  • the negative terminal VSS is electrically connected to the negative signal source (for example, the cathode layer of the organic light emitting diode OLED (as shown in Figure 2) is directly connected to the negative signal source)
  • the gate line end EM is connected to the gate line 83
  • the gate line end Gate is connected to the gate line 82
  • the data line end Data is connected to the data line 81 ; other terminals are also electrically connected to corresponding signal sources.
  • the driving transistor T3 by writing an appropriate data signal to the source of the driving transistor T3, the current flowing through the driving transistor T3 can be controlled, thereby controlling the organic light emitting diode OLED to emit light with corresponding brightness to realize the display of the sub-pixel 1.
  • the first gate driving circuit pin area 231 includes a plurality of gate array pins 2310, and the plurality of gate array pins 2310 are respectively connected with the gate driving lines 237 ( The connection line is not shown in the figure), the gate driving line 237 extends to the first peripheral region 201 and is connected to the gate driving circuit 2011 in the first peripheral region 201, and the gate driving circuit 2011 includes a plurality of shift register units , each shift register unit is connected to a gate line 82 in the display area, and provides gate driving signals for each row of sub-pixels 1 in the pixel array.
  • the gate driving line (not shown in the figure) may be connected to the gate driving circuit 2012 in the first peripheral region 201, and the gate driving circuit 2012 includes a plurality of shift register units, each of which shifts
  • the bit register unit is connected to a gate line 83 in the display area, and provides gate drive signals for each row of sub-pixels 1 in the pixel array.
  • the first output pin area 234 includes a plurality of data pins 2340, and the plurality of data pins 2340 are respectively connected with a plurality of data lines 81 in the display area (not shown in the figure). Connecting lines are shown) to provide data driving signals for each column of sub-pixels 1 in the pixel array.
  • the input pin area 233 includes a plurality of first input pins 2330 , and at least one of the plurality of first input pins 2330 is connected to the first input pin 2330 in the second binding area 240 .
  • the two output pins 2440 are connected (connection lines are not shown in the figure).
  • the power supply pin area 242 includes a plurality of power supply pins 2420 , and the plurality of power supply pins 2420 are respectively connected to the display area 100 and the plurality of pins in the first peripheral area 201 .
  • the power lines include a first power line 2423 and a second power line 2424 .
  • the first power line 2423 may be a positive voltage power line (ELVDD)
  • the second power line 2424 may be a negative voltage power line (ELVSS).
  • the first power line 2423 is located in the display area 100 and is electrically connected to the plurality of sub-pixels 1
  • the second power line 2424 is located in the first peripheral area 201 and surrounds the display area 100 .
  • the array test leads 235 may be arranged in the same layer as one or more layers of the first gate metal layer and the second gate metal layer, and the touch test The lead 236 may be disposed in the same layer as the source-drain metal layer.
  • the first power line 2423 and the second power line 2424 may be disposed in the same layer as the source-drain metal layer.
  • the orthographic projection of the array test leads 235 on the substrate includes an overlap with the orthographic projection of one or more of the first power line 2423 and the second power line 2424 on the substrate area.
  • the second peripheral area 200 includes a first area A1 and a second area A2, the first area A1 is located between the second binding area 240 and the second area A2, and the array
  • the distance between the test leads 235 and the touch test leads 236 in the first area A1 is smaller than the distance between the array test leads 235 and the touch test leads 236 in the second area A2.
  • the orthographic projection of one or more of the first power supply lines 2423 and the second power supply lines 2424 on the substrate is located on the substrate of the array test leads 235 between the orthographic projection on the substrate and the orthographic projection of the touch test leads 236 on the substrate.
  • the second gate driving circuit pin area 241 includes a plurality of gate test pins 2410, which are respectively connected with the first gate driving circuit.
  • the plurality of gate array pins 2310 in the pin area 231 are electrically connected (connection lines are not shown in the figure) for testing a plurality of gate lines or a plurality of gate lines.
  • the second touch pin area 243 includes a plurality of touch test pins 2430 , and the plurality of touch test pins 2430 are respectively connected to the first sub-touch pin area 2321 .
  • the plurality of first touch pins 23211 in the sub-touch pin area 2322 or the plurality of second touch pins 23221 in the second sub-touch pin area 2322 are electrically connected (connecting lines are not shown in the figure) for control electrode for testing.
  • the second output pin area 244 includes a plurality of second output pins 2440, and the plurality of second output pins 2440 are respectively connected with the plurality of first input pins 2330 ( The connecting lines are not shown in the figure).
  • a plurality of first input pins 2330 are arranged along the second side edge 2302 , that is, the distance between each first input pin 2330 and the second side edge 2302 is smaller than the first input pin 2330 Input the distance between the pin 2330 and the first side 2301 .
  • a plurality of data pins 2340 and a plurality of gate array pins 2310 are arranged along the first side 2301, and a plurality of gate array pins 2310 are arranged at a plurality of data
  • the pins 2340 are on both sides of the first direction D1.
  • the plurality of first touch pins 23211 are arranged along the third side 2303
  • the plurality of second touch pins 23221 are arranged along the fourth side 2304 .
  • each of the pins in the power pin area 242 , the second gate driving circuit pin area 241 , the second touch pin area 243 and the second output pin area 244 The feet may be arranged in a line along the first direction D1.
  • FIG. 10 does not show all the first touch pins 23211 , the second touch pins 23221 , The data pin 2340, the first input pin 2330, the gate test pin 2410, the power supply pin 2420, the touch test pin 2430 and the second output pin 2440, only some of the first touch pins are shown.
  • test pin 23211, second touch pin 23221, data pin 2340, first input pin 2330, gate test pin 2410, power supply pin 2420, touch test pin 2430 and second output pin 2440 namely The first touch pin 23211, the second touch pin 23221, the data pin 2340, the first input pin 2330, the gate test pin 2410, the power supply pin 2420, the touch
  • the numbers of the test pins 2430 and the second output pins 2440 do not represent the actual first touch pins 23211 , the second touch pins 23221 , the data pins 2340 , the first input pins 2330 , and the gate test pins 2410, the number of power pins 2420, touch test pins 2430 and second output pins 2440.
  • the following is an exemplary description through the preparation process of the touch display substrate.
  • the "patterning process” mentioned in this disclosure includes photoresist coating, mask exposure, development, etching, stripping photoresist and other treatments, for organic materials, including Processes such as coating organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spraying, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings are not limited in the present disclosure.
  • “Film” refers to a thin film made of a material on a substrate by deposition, coating or other processes.
  • the "thin film” may also be referred to as a "layer”. If the "thin film” needs a patterning process in the whole manufacturing process, it is called a "thin film” before the patterning process, and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are simultaneously formed through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the touch display substrate.
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A is the same as the boundary of the orthographic projection of B.
  • the projected boundaries overlap.
  • a substrate 101 is prepared on a glass carrier.
  • the substrate 101 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer films, and the first and second inorganic materials
  • the material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: firstly coating a layer of polyimide on a glass carrier, and curing to form a film Then a first flexible (PI1) layer is formed; then a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then an amorphous layer is deposited on the first barrier layer A silicon film to form an amorphous silicon (a-si) layer covering the first barrier layer; then a layer of polyimide is coated on the amorphous silicon layer, and a second flexible (PI2) layer is formed after curing into a film; Then, a barrier film is deposited on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer to complete the preparation of the substrate 101 .
  • the substrate 101 may be a rigid substrate.
  • the second peripheral region includes the first insulating layer disposed on the substrate 101 .
  • the first gate metal layer pattern includes at least a first gate electrode and a first capacitor electrode, and the first gate electrode and the first capacitor electrode are formed in the effective area 100 .
  • the second peripheral region includes a first insulating layer disposed on the substrate 101 and a second insulating layer disposed on the first insulating layer.
  • the second gate metal layer and the first metal layer pattern, the second gate metal layer pattern includes at least a second capacitor electrode, and the first metal layer includes a first touch lead 2381, a second touch lead 2382, an array test lead 235 and The touch test lead 236, the second capacitive electrode is formed in the effective area 100, the position of the second capacitive electrode corresponds to the position of the first capacitive electrode, the first touch lead 2381, the second touch lead 2382, the array test lead 235 and touch test leads 236 are formed in the second peripheral region 200 .
  • the first touch leads 2381 are used to connect the touch pins of the first touch pin area 2321 and the touch electrodes of the active area
  • the second touch leads 2382 are used to connect the touch pins of the second touch pin area 2322
  • the pins and the touch electrodes of the active area; the touch test leads 236 are used to connect the touch pin area 232 and the second touch pin area 243
  • the array test leads 235 are used to connect the first gate drive circuit pin area 231 and the second gate driving circuit pin area 241, and the orthographic projection of the array test leads 235 on the substrate does not overlap with the orthographic projection of the touch test leads 236 on the substrate.
  • the first metal layer also includes a pattern of the first metal layer in each of the pins forming the second peripheral region.
  • Each via hole includes at least two first active via holes.
  • two first active vias are formed in the active area 100, the fourth insulating layer, the third insulating layer and the second insulating layer in the two first active vias are etched away, The surface of the first active layer is exposed.
  • the two first active via holes are used to connect the source electrode and the drain electrode formed subsequently with the first active layer, respectively.
  • the source electrode and the drain electrode are formed in the active region 100 and are respectively connected to the first active layer through the first active via hole.
  • the second metal layer is formed in the first bonding region 230 and the second bonding region 240, and includes patterns of the second metal layer in each of the pins constituting the second peripheral region.
  • a first flat film of organic material is coated to form a first flat (PLN) layer covering the effective area.
  • PPN first flat
  • An anode via hole is formed on a flat layer, the anode via hole is formed in the effective area, and the first flat layer in the anode via hole is removed to expose the surface of the drain electrode of the driving transistor.
  • the driving structure layer pattern is prepared on the substrate.
  • the first active layer, the first gate electrode, the source electrode and the drain electrode form a driving transistor in the pixel driving circuit
  • the first capacitor electrode and the second capacitor electrode form a storage capacitor in the pixel driving circuit.
  • the light emitting element pattern may include an anode, a pixel definition (PDL) layer, a spacer pillar (PS), an organic light emitting layer, and a cathode.
  • the anode is arranged on the first flat layer, and is connected to the drain electrode of the driving transistor through the via hole opened on the first flat layer;
  • the pixel definition layer is arranged on the anode and the flat layer, the pixel definition layer is provided with a pixel opening, and the pixel opening is exposed
  • the organic light-emitting layer is at least partially arranged in the pixel opening, and the organic light-emitting layer is connected with the anode;
  • the cathode is arranged on the organic light-emitting layer, and the cathode is connected with the organic light-emitting layer;
  • the organic light-emitting layer is driven by the anode and the cathode to emit light of a corresponding color .
  • the encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, wherein the first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials.
  • a fourth metal thin film is deposited, and the fourth metal thin film is patterned through a patterning process to form a touch electrode layer and a third metal layer pattern.
  • the touch electrode layer includes a plurality of touch electrodes and a plurality of touch wires.
  • the third metal layer includes a pattern of the third metal layer in each of the pins constituting the second peripheral region.
  • each lead in the second peripheral area is formed by stacking a first metal layer, a second metal layer and a third metal layer in sequence, the first metal layer is connected to the second metal layer, and the second metal layer is connected to the second metal layer.
  • the layer is connected to the third metal layer, and all pins (including virtual pins and non-virtual pins, virtual pins are pins that do not introduce electrical signals, and non-virtual pins are pins that introduce electrical signals) at the same height. , so as to ensure that the driver chip or the FPC can be flatly bound on the touch display panel.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) Any one or more of them may be a single layer, multiple layers or composite layers.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer are called the gate insulating (GI) layer
  • the fourth insulating layer is called the layer interstitial insulating (ILD) layer.
  • the first metal film, the second metal film, the third metal film and the fourth metal film can be made of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo).
  • Any one or more of the above metals, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb) can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti, etc. .
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene polythiophene and other materials
  • the orthographic projection of the array test leads on the substrate and the orthographic projection of the touch test leads on the substrate in the exemplary embodiment of the present disclosure are different from each other. By overlapping, the problem of signal crosstalk caused by the intersection of the touch trace and the gate array trace is avoided, and the touch performance is improved.
  • the structure of the touch display substrate and the manufacturing process thereof according to the exemplary embodiment of the present disclosure are merely illustrative.
  • the corresponding structures may be changed and patterning processes may be increased or decreased according to actual needs, which is not limited in the present disclosure.
  • the present disclosure also provides a preparation method of a touch display substrate, the touch display substrate includes an effective area, a first peripheral area and a second peripheral area located around the effective area, and the second peripheral area includes a drive for binding a first binding area of the chip and a second binding area located on the side of the first binding area away from the effective area and used for binding the flexible circuit board, the first binding area includes a gate drive circuit pin area and a first binding area
  • the first binding area includes a gate drive circuit pin area and a first binding area
  • the touch pin area, the second binding area includes a second gate drive circuit pin area electrically connected to the first gate drive circuit pin area, and a second contact pin area electrically connected to the first touch pin area control pin area;
  • the preparation method includes:
  • a touch test lead and an array test lead are formed in the second peripheral area, wherein the touch test lead is connected to the first touch pin area and the second touch lead area, and the array test lead is connected to the first gate driving circuit pin area and the second gate driving circuit pin area, and the orthographic projection of the array test leads on the substrate does not overlap with the orthographic projection of the touch test leads on the substrate.
  • the touch display substrate on a plane perpendicular to the touch display substrate, includes a base, an active layer disposed on the base, a first insulating layer disposed on the active layer, a first insulating layer disposed on the first a first gate metal layer on the insulating layer, a second insulating layer on the first gate metal layer, a second gate metal layer on the second insulating layer, and a third insulating layer on the second gate metal layer layer and a source-drain metal layer disposed on the third insulating layer;
  • the array test leads are arranged on the same layer as one or more of the first gate metal layer and the second gate metal layer, and the touch test leads are arranged on the same layer as the source-drain metal layer.
  • Exemplary embodiments of the present disclosure further provide a touch display device including the touch display substrate of the foregoing embodiments.
  • the touch display device of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the touch display device may be a wearable display device, which can be worn on the human body in some ways, such as a smart watch, a smart bracelet, and the like.

Abstract

一种触控显示基板及其制备方法、触控显示装置，触控显示基板包括有效区域（100）、第一周边区（201）和第二周边区（200），第二周边区（200）包括用于绑定驱动芯片的第一绑定区（230）和位于第一绑定区（230）远离有效区域（100）一侧并用于绑定柔性线路板的第二绑定区（240）；第一绑定区（230）包括第一栅极驱动电路引脚区（231）和第一触控引脚区（232）；第二绑定区（240）包括与所述第一栅极驱动电路引脚区（231）电连接的第二栅极驱动电路引脚区（241），以及与所述第一触控引脚区（232）电连接的第二触控引脚区（243）；第二周边区（200）还包括连接第一触控引脚区（232）和第二触控引脚区（243）的触控测试引线（236），以及连接第一栅极驱动电路引脚区（231）和第二栅极驱动电路引脚区（241）的阵列测试引线（235），且阵列测试引线（235）在基底（101）上的正投影与触控测试引线（236）在基底（101）上的正投影不交叠。

Description

触控显示基板及其制备方法、触控显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种触控显示基板及其制备方法、触控显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光元件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种触控显示基板，包括有效区域以及位于有效区域周边的第一周边区和第二周边区，其中：所述有效区域包括基底以及叠设在所述基底上的显示单元和触控单元，所述显示单元包括多条数据线、多条栅线和多个子像素，所述触控单元包括多个触控电极以及与所述触控电极连接的触控引线；所述第一周边区包括与所述多条栅线连接的栅极驱动电路；所述第二周边区包括用于绑定驱动芯片的第一绑定区和位于所述第一绑定区远离所述有效区域一侧并用于绑定柔性线路板的第二绑定区；所述第一绑定区包括第一栅极驱动电路引脚区和第一触控引脚区；所述第二绑定区包括与所述第一栅极驱动电路引脚区电连接的第二栅极驱动电路引脚区，以及与所述第一触控引脚区电连接的第二触控引脚区；所述第二周边区还包括连接第一触控引脚区和第二触控引脚区的触控测试引线，以及连接第一栅极驱动电路引脚区和第二栅极驱动电路引脚区的阵列测试引线，且阵列测试引线在基 底上的正投影与触控测试引线在基底上的正投影不交叠。
在示例性实施例中，所述第一绑定区包括第一侧边、与所述第一侧边相对的第二侧边以及连接于所述第一侧边与第二侧边之间的第三侧边和第四侧边，第一侧边位于靠近所述有效区域的一侧，所述第二侧边位于远离所述有效区域的一侧；所述第一栅极驱动电路引脚区包括第一子栅极驱动电路引脚区，所述第一子栅极驱动电路引脚区位于靠近所述第一侧边的一侧，且所述第一子栅极驱动电路引脚区靠近所述第三侧边或所述第四侧边设置；所述第一触控引脚区包括第一子触控引脚区，所述第一子触控引脚区位于靠近所述第三侧边或所述第四侧边的一侧，且所述第一子触控引脚区与所述第二侧边之间的距离小于所述第一子栅极驱动电路引脚区与所述第二侧边之间的距离。
在示例性实施例中，所述第一绑定区还包括输入引脚区和第一输出引脚区，其中，所述输入引脚区靠近所述第二侧边设置，所述第一输出引脚区靠近所述第一侧边设置。
在示例性实施例中，所述第一输出引脚区包括第一子输出引脚区以及位于所述第一子输出引脚区一侧的空隙区；所述第一绑定区还包括多根第一触控引线，所述第一触控引线从所述第一子触控引脚区延伸并穿过所述空隙区后，与所述有效区域的触控电极连接。
在示例性实施例中，所述第一绑定区还包括多个虚拟引脚，所述虚拟引脚设置在以下任意一个或多个位置：所述第一子触控引脚区、至少一根所述第一触控引线的一侧或两侧。
在示例性实施例中，所述第一子触控引脚区包括多个第一触控引脚，多个所述第一触控引脚中的一个或多个与所述第一触控引线连接。
在示例性实施例中，所述多个第一触控引脚包括两列或两列以上，且每一列的所述第一触控引脚与相邻列的所述第一触控引脚在第一方向上呈交错排列。
在示例性实施例中，在垂直于触控显示基板的平面内，所述第一触控引脚包括：设置在基底上的第一金属层、设置在所述第一金属层之上的第二金 属层以及设置在所述第二金属层之上的第三金属层；在垂直于触控显示基板的平面内，所述第一触控引线包括：设置在所述基底上的第一金属层。
在示例性实施例中，所述第二绑定区包括第五侧边、与所述第五侧边相对的第六侧边以及连接于所述第五侧边与第六侧边之间的第七侧边和第八侧边，所述第五侧边位于靠近所述第一绑定区的一侧，所述第六侧边位于远离所述第一绑定区的一侧；所述第二栅极驱动电路引脚区包括第三子栅极驱动电路引脚区，所述第二触控引脚区包括第三子触控引脚区；所述第三子栅极驱动电路引脚区和第三子触控引脚区位于所述第二绑定区靠近第七侧边的一侧，且所述第三子栅极驱动电路引脚区与所述第七侧边之间的距离小于所述第三子触控引脚区与所述第七侧边之间的距离。
在示例性实施例中，所述第二绑定区还包括电源引脚区，其中，所述电源引脚区位于所述第三子栅极驱动电路引脚区以及所述第三子触控引脚区之间。
在示例性实施例中，所述的触控显示基板还包括第一电源线和第二电源线，所述第一电源线从所述电源引脚区延伸至所述有效区域，所述第二电源线从所述电源引脚区延伸至所述第一周边区；所述阵列测试引线在所述基底上的正投影，与所述第一电源线和所述第二电源线中的一个或多个在所述基底上的正投影包含重叠区域。
在示例性实施例中，所述第二周边区包括第一区和第二区，所述第一区位于所述第二绑定区与所述第二区之间，且所述阵列测试引线与所述触控测试引线在所述第一区之间的距离小于所述阵列测试引线与所述触控测试引线在所述第二区之间的距离。
在示例性实施例中，在所述第一区，所述第一电源线和所述第二电源线中的一个或多个在所述基底上的正投影，位于所述阵列测试引线在所述基底上的正投影与所述触控测试引线在所述基底上的正投影之间。
本公开实施例还提供了一种触控显示装置，包括如以上任一项所述的触控显示基板。
本公开实施例还提供了一种触控显示基板的制备方法，所述触控显示基 板包括有效区域以及位于有效区域周边的第一周边区和第二周边区，所述第二周边区包括用于绑定驱动芯片的第一绑定区和位于所述第一绑定区远离所述有效区域一侧并用于绑定柔性线路板的第二绑定区，所述第一绑定区包括第一栅极驱动电路引脚区和第一触控引脚区，所述第二绑定区包括与所述第一栅极驱动电路引脚区电连接的第二栅极驱动电路引脚区，以及与所述第一触控引脚区电连接的第二触控引脚区；所述制备方法包括：在所述第二周边区形成触控测试引线和阵列测试引线，其中，所述触控测试引线连接所述第一触控引脚区和所述第二触控引脚区，所述阵列测试引线连接所述第一栅极驱动电路引脚区和所述第二栅极驱动电路引脚区，且所述阵列测试引线在基底上的正投影与所述触控测试引线在基底上的正投影不交叠。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开实施例一种触控显示基板的结构示意图；
图2为图1中有效区域的剖面结构示意图；
图3为图1中第一绑定区和第二绑定区的结构示意图之一；
图4为图1中第一绑定区和第二绑定区的结构示意图之二；
图5为图3或图4中触控引脚区的放大结构示意图；
图6为图5中BB区域的剖面结构示意图；
图7为本公开实施例一种触控显示基板的触控区域的结构示意图；
图8为本公开实施例一种触控显示基板的显示区域的结构示意图；
图9为本公开实施例一种像素驱动电路的结构示意图；
图10为本公开实施例第一绑定区和第二绑定区的结构示意图之三；
图11为本公开实施例第一绑定区和第二绑定区的结构示意图之四。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
目前，智能手机的触控和显示功能都由两块芯片独立控制，而OLED触控与显示驱动器集成(Touch and Display Driver Integration，TDDI)产品最大的特点是把触控芯片与显示芯片整合进单一芯片中。TDDI带来的是一种统一的系统架构，原有的系统架构因为显示与触控芯片是分离的，可能会导致一些显示噪声的存在，而TDDI由于实现了统一的控制，在噪声的管理方面会有更好的效果。
但是，在OLED TDDI产品的绑定区域设计中，如果按照常规的排布方式排布引脚，会发生触控走线和栅极阵列(GOA)走线相互交叉的问题，进 而使得栅极阵列信号对触控信号产生干扰，降低了触控性能。
图1为本公开示例性实施例一种触控显示基板的平面结构示意图，如图1所示，该触控显示基板包括基底、设置在基底上的有效区域(AA)100、以及位于有效区域100周边的第一周边区201和第二周边区200。
其中，有效区域100包括基底(图中未示出)以及叠设在基底上的显示单元(图中未示出)和触控单元(图中未示出)，显示单元包括多条数据线(图中未示出)、多条栅线(图中未示出)和多个子像素(图中未示出)，触控单元包括多个触控电极(图中未示出)以及与触控电极连接的触控走线(图中未示出)。本实施例中，对于叠设的显示单元和触控单元，有效区域既可以是触控单元的触控区域，也可以是显示单元的显示区域，以下描述中的触控区域和显示区域均是指有效区域。
第二周边区200包括第一绑定区230，以及位于第一绑定区230远离有效区域100一侧的第二绑定区240，第一绑定区230用于绑定驱动芯片，第二绑定区240用于绑定柔性印刷线路板(Flexible Printed Circuit，FPC)，通过FPC与驱动芯片为显示单元中的像素阵列提供驱动信号，实现图像显示与触控。
图2为本公开示例性实施例一种触控显示基板的有效区域的剖面结构示意图，其中，该触控显示基板包括显示单元以及设置在显示单元上的触控单元，显示单元示意了三个子像素的结构。如图2所示，在垂直于触控显示基板的平面上，显示单元可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光元件103以及设置在发光元件103远离基底101一侧的封装层104。在一些可能的实现方式中，显示单元可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材 料可以采用非晶硅(a-si)。
在示例性实施方式中，每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图2中以每个子像素中包括一个驱动晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每个子像素的驱动电路层102可以包括：设置在基底上的第一绝缘层；设置在第一绝缘层上的有源层；覆盖有源层的第二绝缘层；设置在第二绝缘层上的栅电极和第一电容电极；覆盖栅电极和第一电容电极的第三绝缘层；设置在第三绝缘层上的第二电容电极；覆盖第二电容电极的第四绝缘层，第二绝缘层、第三绝缘层和第四绝缘层上开设有过孔，过孔暴露出有源层；设置在第四绝缘层上的源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接；覆盖前述结构的平坦层，平坦层上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极组成驱动晶体管，第一电容电极和第二电容电极组成存储电容。
在示例性实施方式中，发光元件103可以包括阳极、像素定义层、有机发光层和阴极。阳极设置在平坦层上，通过平坦层上开设的过孔与驱动晶体管的漏电极连接；像素定义层设置在阳极和平坦层上，像素定义层上设置有像素开口，像素开口暴露出阳极；有机发光层至少部分设置在像素开口内，有机发光层与阳极连接；阴极设置在有机发光层上，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件103。
在示例性实施方式中，OLED发光元件的有机发光层可以包括发光层(Emitting Layer，简称EML)，以及包括空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、空穴阻挡层(Hole Block Layer，简称HBL)、电子阻挡层(Electron Block Layer，简称EBL)、电子注入层(Electron Injection Layer，简称EIL)、电子传输层(Electron Transport Layer，简称ETL)中的一个或多个膜层。在阳极和阴极 的电压驱动下，利用有机材料的发光特性根据需要的灰度发光。
在示例性实施方式中，不同颜色的OLED发光元件的发光层不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在示例性实施方式中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，但通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在示例性实施方式中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在示例性实施方式中，如图2所示，在垂直于触控显示基板的平面上，触控单元可以包括设置在封装层104远离基底101一侧的缓冲(Buffer)层105，设置在缓冲层105远离基底101一侧的触控电极层106，设置在触控电极层106远离基底101一侧的保护层107。多个触控电极和触控走线可以同层设置在触控电极层106。
在示例性实施方式中，缓冲层105可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。触控电极层106可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，保护层109可以采用有机材料。
图3和图4为图1中的第一绑定区230和第二绑定区240的两种结构示意图。如图3或图4所示，第一绑定区230包括用于将驱动芯片的驱动信号传输至栅极驱动电路的第一栅极驱动电路引脚区231和用于将触控电极感测的触控信号传输至驱动芯片的第一触控引脚区232。第二绑定区240包括用于对多条栅线进行测试的第二栅极驱动电路引脚区241和用于对多个触控电极进行测试的第二触控引脚区243。
第二周边区200还包括用于连接第一触控引脚区232和第二触控引脚区243的触控测试引线236，以及用于连接第一栅极驱动电路引脚区231和第二栅极驱动电路引脚区241的阵列测试引线235，且阵列测试引线235在基底上的正投影与触控测试引线236在基底上的正投影不交叠。
由于触控测试引线236、阵列测试引线235的数量需要根据实际的触控显示基板的分辨率确定，图3和图4并未示意出所有的触控测试引线236、阵列测试引线235，仅示意出了其中的部分触控测试引线236、阵列测试引线235，即图3和图4示意出的触控测试引线236、阵列测试引线235的数量并不代表实际触控测试引线236、阵列测试引线235的数量。
本公开实施例中的触控显示基板，通过使得阵列测试引线235在基底上的正投影与触控测试引线236在基底上的正投影不交叠，避免了触控走线和栅极阵列走线相互交叉引起信号串扰的问题，提高了触控性能。
在示例性实施方式中，如图3或图4所示，第一绑定区230包括第一侧边2301、与第一侧边2301相对的第二侧边2302以及连接于第一侧边2301与第二侧边2302之间的第三侧边2303和第四侧边2304，第一侧边2301位于靠近有效区域100的一侧，第二侧边2302位于远离有效区域100的一侧。
在示例性实施方式中，如图3或图4所示，第一栅极驱动电路引脚区231包括第一子栅极驱动电路引脚区2311和第二子栅极驱动电路引脚区2312，第一子栅极驱动电路引脚区2311和第二子栅极驱动电路引脚区2312位于靠近第一侧边2301的一侧，且第一子栅极驱动电路引脚区2311靠近第三侧边2303设置，第二子栅极驱动电路引脚区2312靠近第四侧边2304设置。
在示例性实施方式中，如图3或图4所示，第一触控引脚区232包括第一子触控引脚区2321和第二子触控引脚区2322，第一子触控引脚区2321位于靠近第三侧边2303的一侧，第二子触控引脚区2322位于靠近第四侧边2304的一侧。
在示例性实施方式中，如图3或图4所示，第一子触控引脚区2321与第二侧边2302之间的距离小于第一子栅极驱动电路引脚区2311与第二侧边2302之间的距离；第二子触控引脚区2322与第二侧边2302之间的距离小于 第二子栅极驱动电路引脚区2312与第二侧边2302之间的距离。
在示例性实施方式中，如图3或图4所示，第二绑定区240包括第五侧边2401、与第五侧边2401相对的第六侧边2402以及连接于第五侧边2401与第六侧边2402之间的第七侧边2403和第八侧边2404，第五侧边2401位于靠近第一绑定区230的一侧，第六侧边2402位于远离第一绑定区230的一侧。
第二栅极驱动电路引脚区241包括第三子栅极驱动电路引脚区2411和第四子栅极驱动电路引脚区2412，第二触控引脚区243包括第三子触控引脚区2431和第四子触控引脚区2432，第三子栅极驱动电路引脚区2411和第三子触控引脚区2431位于第二绑定区240靠近第七侧边2403的一侧，且第三子栅极驱动电路引脚区2411与第七侧边2403之间的距离小于第三子触控引脚区2431与第七侧边2403之间的距离；第四子栅极驱动电路引脚区2412和第四子触控引脚区2432位于第二绑定区240靠近第八侧边2404的一侧，且第四子栅极驱动电路引脚区2412与第八侧边2404之间的距离小于第四子触控引脚区2432与第八侧边2404之间的距离。
在一种示例性实施方式中，如图3所示，第二绑定区240还包括电源引脚区242，其中，电源引脚区242包括第一子电源引脚区2421和第二子电源引脚区2422，第一子电源引脚区2421设置在第三子栅极驱动电路引脚区2411和第三子触控引脚区2431之间，第二子电源引脚区2422设置在第四子栅极驱动电路引脚区2412和第四子触控引脚区2432之间。
在另一种示例性实施方式中，如图4所示，第二绑定区240还包括电源引脚区242，其中，电源引脚区242包括第一子电源引脚区2421和第二子电源引脚区2422，第一子电源引脚区2421设置在第三子栅极驱动电路引脚区2411靠近第七侧边2403的一侧，第二子电源引脚区2422设置在第四子栅极驱动电路引脚区2412靠近第八侧边2404的一侧。
在示例性实施方式中，如图3或图4所示，第一绑定区230还包括输入引脚区233和第一输出引脚区234，其中，输入引脚区233靠近第二侧边2302设置，第一输出引脚区234靠近第一侧边2301设置，且第一输出引脚 区234设置在第一子栅极驱动电路引脚区2311和第二子栅极驱动电路引脚区2312之间。
在示例性实施方式中，如图3或图4所示，第一输出引脚区234包括第一子输出引脚区2341、第二子输出引脚区2342以及位于第一子输出引脚区2341和第二子输出引脚区2342之间的空隙区(图中未示出)。
第一绑定区230还包括多根第一触控引线2381和多根第二触控引线2382，第一触控引线2381从第一子触控引脚区2321延伸并穿过空隙区后，与有效区域100的触控电极300连接；第二触控引线2382从第二子触控引脚区2322延伸并穿过空隙区后，与有效区域100的触控电极300连接。
由于第一触控引线2381、第二触控引线2382的数量需要根据实际的触控显示基板的分辨率确定，图3和图4并未示意出所有的第一触控引线2381、第二触控引线2382，仅示意出了其中的一根第一触控引线2381和一根第二触控引线2382，即图3和图4示意出的第一触控引线2381、第二触控引线2382的数量并不代表实际第一触控引线2381、第二触控引线2382的数量。
图5为图3或图4中触控引脚区的放大结构示意图。在示例性实施方式中，如图5所示，第一子触控引脚区2321包括多个第一触控引脚23211，多个第一触控引脚23211中的一个或多个与第一触控引线2381连接。
在示例性实施方式中，第二子触控引脚区2322包括多个第二触控引脚(图5中未示出)，多个第二触控引脚中的一个或多个与第二触控引线2382连接。
在示例性实施方式中，如图5所示，第一绑定区230还包括多个虚拟引脚23212，多个虚拟引脚23212可以设置在以下任意一个或多个位置：第一子触控引脚区2321、第二子触控引脚区2322、多根第一触控引线2381的一侧或两侧、多根第二触控引线2382的一侧或两侧。
本实施例中，没有与第一触控引线2381连接的第一触控引脚23211以及没有与第二触控引线2382连接的第二触控引脚都构成了虚拟引脚，虚拟引脚未引入电信号。通过设置虚拟引脚23212，使得驱动芯片或FPC可以平整地绑定在触控显示面板上，且绑定过程中，不会压坏走线。
在示例性实施方式中，如图5所示，多个第一触控引脚23211包括两列或两列以上，且每一列的第一触控引脚与相邻列的第一触控引脚在第一方向D1上呈交错排列。
在示例性实施方式中，多个第二触控引脚包括两列或两列以上，且每一列的第二触控引脚与相邻列的第二触控引脚在第一方向D1上呈交错排列。
通过使相邻列的第一触控引脚或第二触控引脚在第一方向上呈交错排列，增加了每个引脚在第一方向上的绑定间距(Margin)，以使得第一触控引脚或第二触控引脚的两侧用于布设引线的空间更大，避免连接第一触控引脚或第二触控引脚的多条导线发生短路，引起显示异常。
图6为图5中BB区域的剖面结构示意图。在示例性实施方式中，如图6所示，在垂直于触控显示基板的平面内，第一触控引脚和第二触控引脚均包括：设置在基底101上的第一金属层M1、设置在第一金属层M1之上的第二金属层M2以及设置在第二金属层M2之上的第三金属层M3。
在示例性实施方式中，如图6所示，在垂直于触控显示基板的平面内，第一触控引线和第二触控引线均包括：设置在基底101上的第一金属层M1。
在示例性实施例中，第一金属层M1可以与有效区域的第一栅金属层和/或第二栅金属层同层设置。第二金属层M2可以与有效区域的源漏金属层同层设置。第三金属层M3可以与有效区域的触控电极层同层设置。
在示例性实施方式中，显示单元可以为液晶显示单元或OLED显示单元等。本公开对此不做限制。
在示例性实施方式中，如图7所示，触控区域包括规则排布的多个触控电极300，示例性的，触控电极300可以为矩形，以M行*N列的矩阵方式排列。触控区域100可以被划分为N个电极区110和N个引线区120，电极区110和引线区120为沿第二方向D2延伸的条形状，条形状的电极区110和条形状的引线区120沿第一方向D1交替设置，即除边缘位置的电极区和引线区外，一个引线区120设置在两个电极区110之间，一个电极区110设置在两个引线区120之间。每个电极区110包括沿第二方向D2依次设置的 M个触控电极300，每个引线区120包括沿第一方向D1依次设置的M条触控走线310，每条触控走线310的第一端与一个触控电极300连接，第二端沿第二方向D2延伸到第二周边区200。
在示例性实施方式中，触控电极300可以为约4mm*4mm或5mm*5mm的规则图案，规则图案可以是矩形、菱形、三角形或多边形等。工作时，人手指的触控会导致相应触控电极的自电容发生变化，外部控制装置可以根据触控电极的电容变化来判断手指的位置。
在示例性实施方式中，如图7所示，沿着第二方向D2(即远离触控区域的方向)，第二周边区200可以包括依次设置的走线引出区210、弯折区220、第一绑定区230和第二绑定区240。走线引出区210可以设置多条折线，多条折线的第一端分别与触控区域的多条触控走线310相应连接，第二端向弯折区220方向延伸，并分别与弯折区220中设置的多条连接线连接。弯折区220配置为使第二周边区200的第一绑定区230和第二绑定区240弯折到触控区域100的背面。第一绑定区230可以设置触控与显示驱动器集成(Touch and Display Driver Integration，简称TDDI)电路、多条输出线和多条输入线，TDDI电路用于对触控和显示功能进行控制。第二绑定区240可以设置多个引脚(PIN)，TDDI电路通过多条输入线与多个引脚中的部分引脚连接，多个引脚配置为通过绑定柔性电路板(FPC)与外部控制装置连接。
在示例性实施方式中，第一触控引脚区包括多个触控引脚(图7中未示出)，多个触控引脚连接前述的第一触控引线2381或第二触控引线2382，第一触控引线2381和第二触控引线2382分别与有效区域的多条触控走线310连接，通过第一触控引线2381或第二触控引线2382、触控走线310与触控区域中的触控电极连接。
在示例性实施方式中，第二触控引脚区包括多个触控测试引脚(图7中未示出)，多个触控测试引脚分别与第一触控引脚区中的多个触控引脚连接，用于对触控电极进行测试。
在示例性实施方式中，如图8所示，显示区域包括多个用于进行显示的子像素1，每个子像素1为能独立发出所需亮度和颜色的光的最小的点，通 常多个子像素1可组成一个能显示任意颜色亮度的光的“像素”，每个“像素”为待显示图像中的一个“点”。
显示区域中还设有用于为子像素1提供驱动信号的引线，如用于为子像素1提供数据信号(数据电压)的数据线81。在一些实施例中，显示区域中还设有栅极线82、控制极线83等其它引线。
在一些示例性实施例中，如图8所示，第一周边区201包括栅极驱动电路2011，栅极驱动电路2011与多条栅线82电连接，并被配置为向多条栅线82提供栅极驱动信号。
在一些示例性实施例中，如图8所示，第一周边区201还包括控制极驱动电路2012，控制极驱动电路2012与多条控制极线83电连接，并被配置为向多条控制极线83提供控制极驱动信号。
在一些示例性实施例中，显示区域中的各子像素1排成矩阵，即排成多行、多列。而数据线81均平行于列方向，且每条数据线81电连接一列子像素1；栅极线82均平行于行方向，且每条栅极线82电连接一行子像素1；控制极线均平行于行方向，且每条控制极线83电连接一行子像素1。
由此，在显示每帧画面时，可轮流(分时)向各栅极线82通入导通信号(可使晶体管导通的信号)，在每条栅极线82通入导通信号时，各数据线81将数据信号分别写入与该栅极线82电连接的各子像素1(如一行子像素1)，并将数据信号存储在存储电容Cst中，以供该子像素1在该帧的剩余时间根据存储的数据信号进行显示。而控制极线83则用于控制子像素1是否可发光。
其中，“行”、“列”是两个相对的方向，二者可相互垂直，在部分附图中，以行方向为横向(左右方向)，列方向为纵向(上下方向)为例进行说明‘但应当理解，横向、纵向不是对“行”、“列”的限制，“行”、“列”也与显示单元的放置位置没有必然关系。
在一些实施例中，每个子像素1中设有像素电路，用于使子像素1发光。
示例性的，像素电路的结构可参照图9，为7T1C结构，其包括第一晶 体管T1、第二晶体管T2、驱动晶体管T3(第三晶体管)、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、存储电容Cst、有机发光二极管OLED、第一重置端Reset、第二重置端Reset’、初始化端Vinit、栅极线端Gate、数据线端Data、控制极线端EM、正极端VDD、负极端VSS等结构；其中，各晶体管可均为P型晶体管(如PMOS)或N型晶体管(如NMOS)。
其中，正极端VDD电连接正极信号源(如通过正极线连接)，负极端VSS电连接电负极信号源(如有机发光二极管OLED的阴极层(如图2所示)直接连接负极信号源)，控制极线端EM连接控制极线83，栅极线端Gate连接栅极线82，数据线端Data连接数据线81；其它各端也均电连接相应的信号源。
以上像素电路中，通过向驱动晶体管T3的源极写入合适的数据信号，即可控制流过驱动晶体管T3的电流，从而控制有机发光二极管OLED以相应的亮度发光，实现子像素1的显示。
当然，子像素1和像素电路的具体结构并不限于以上方式。
在示例性实施方式中，如图10所示，第一栅极驱动电路引脚区231包括多个栅极阵列引脚2310，多个栅极阵列引脚2310分别与栅极驱动线237连接(图中未示出连接线)，栅极驱动线237延伸至第一周边区201，并与第一周边区201中的栅极驱动电路2011连接，栅极驱动电路2011包括多个移位寄存器单元，每个移位寄存器单元连接显示区域内的一条栅线82，为像素阵列内的每行子像素1提供栅极驱动信号。在示例性实施方式中，控制极驱动线(图中未示出)可以与第一周边区201中的控制极驱动电路2012连接，控制极驱动电路2012包括多个移位寄存器单元，每个移位寄存器单元连接显示区域内的一条控制极线83，为像素阵列内的每行子像素1提供控制极驱动信号。
在示例性实施方式中，如图10所示，第一输出引脚区234包括多个数据引脚2340，多个数据引脚2340分别与显示区域中的多条数据线81连接(图中未示出连接线)，为像素阵列内的各列子像素1提供数据驱动信号。
在示例性实施方式中，如图10所示，输入引脚区233包括多个第一输入引脚2330，多个第一输入引脚2330中的至少一个与第二绑定区240中的第二输出引脚2440连接(图中未示出连接线)。
在示例性实施方式中，如图10和图11所示，电源引脚区242包括多个电源引脚2420，多个电源引脚2420分别与显示区域100以及第一周边区201中的多根电源线连接。电源线包括第一电源线2423和第二电源线2424。示例性的，第一电源线2423可以为正电压电源线(ELVDD)，第二电源线2424可以为负电压电源线(ELVSS)。在一种示例性实施例中，第一电源线2423，位于显示区域100，且与多个子像素1电连接，第二电源线2424位于第一周边区201且围绕显示区域100。
在示例性实施方式中，如图11所示，为减小信号串扰，阵列测试引线235可以与第一栅金属层和第二栅金属层中的一层或多层同层设置，触控测试引线236可以与源漏金属层同层设置。
在示例性实施方式中，如图11所示，第一电源线2423和第二电源线2424可以与源漏金属层同层设置。
在示例性实施方式中，如图11所示，阵列测试引线235在基底上的正投影，与第一电源线2423和第二电源线2424中的一个或多个在基底上的正投影包含重叠区域。
在示例性实施方式中，如图11所示，第二周边区200包括第一区A1和第二区A2，第一区A1位于第二绑定区240与第二区A2之间，且阵列测试引线235与触控测试引线236在第一区A1之间的距离小于阵列测试引线235与触控测试引线236在第二区A2之间的距离。
在示例性实施例中，如图11所示，在第一区A1，第一电源线2423和第二电源线2424中的一个或多个在基底上的正投影，位于阵列测试引线235在基底上的正投影与触控测试引线236在基底上的正投影之间。
在示例性实施方式中，如图10所示，第二栅极驱动电路引脚区241包括多个栅极测试引脚2410，多个栅极测试引脚2410分别与第一栅极驱动电路引脚区231中的多个栅极阵列引脚2310电连接(图中未示出连接线)，用于 对多条栅线或多条控制极线进行测试。
在示例性实施方式中，如图10所示，第二触控引脚区243包括多个触控测试引脚2430，多个触控测试引脚2430分别与第一子触控引脚区2321中的多个第一触控引脚23211或第二子触控引脚区2322中的多个第二触控引脚23221电连接(图中未示出连接线)，用于对多个触控电极进行测试。
在示例性实施方式中，如图10所示，第二输出引脚区244包括多个第二输出引脚2440，多个第二输出引脚2440分别与多个第一输入引脚2330连接(图中未示出连接线)。
在示例性实施方式中，如图10所示，多个第一输入引脚2330沿第二侧边2302设置，即每个第一输入引脚2330与第二侧边2302的距离小于该第一输入引脚2330与第一侧边2301的距离。
在示例性实施方式中，如图10所示，多个数据引脚2340和多个栅极阵列引脚2310沿第一侧边2301设置，且多个栅极阵列引脚2310设置在多个数据引脚2340沿第一方向D1的两侧。
在示例性实施方式中，如图10所示，多个第一触控引脚23211沿第三侧边2303设置，多个第二触控引脚23221沿第四侧边2304设置。
在示例性实施方式中，如图10所示，电源引脚区242、第二栅极驱动电路引脚区241、第二触控引脚区243和第二输出引脚区244中的各个引脚可以沿第一方向D1排列成一行。
由于栅极阵列引脚2310、第一触控引脚23211、第二触控引脚23221、数据引脚2340、第一输入引脚2330、栅极测试引脚2410、电源引脚2420、触控测试引脚2430和第二输出引脚2440的数量需要根据实际的触控显示基板的分辨率确定，图10并未示意出所有的第一触控引脚23211、第二触控引脚23221、数据引脚2340、第一输入引脚2330、栅极测试引脚2410、电源引脚2420、触控测试引脚2430和第二输出引脚2440，仅示意出了其中的部分第一触控引脚23211、第二触控引脚23221、数据引脚2340、第一输入引脚2330、栅极测试引脚2410、电源引脚2420、触控测试引脚2430和第二输出引脚2440，即图3和图4示意出的第一触控引脚23211、第二触控引脚23221、 数据引脚2340、第一输入引脚2330、栅极测试引脚2410、电源引脚2420、触控测试引脚2430和第二输出引脚2440的数量并不代表实际第一触控引脚23211、第二触控引脚23221、数据引脚2340、第一输入引脚2330、栅极测试引脚2410、电源引脚2420、触控测试引脚2430和第二输出引脚2440的数量。
下面通过触控显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于触控显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
(1)在玻璃载板上制备基底101。在示例性实施方式中，基底101可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1) 层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底101的制备。
在示例性实施方式中，基底101可以是硬质基底。
(2)在基底101上依次沉积第一绝缘薄膜和有源层薄膜，通过图案化工艺对有源层薄膜进行图案化处理，形成覆盖整个基底101的第一绝缘层，以及设置在第一绝缘层上的有源层图案。本次图案化工艺后，第二周边区包括设置在基底101上的第一绝缘层。
(3)依次沉积第二绝缘薄膜和第一金属薄膜，通过图案化工艺对第一金属薄膜进行图案化处理，形成覆盖有源层图案的第二绝缘层，以及设置在第二绝缘层上的第一栅金属层图案，第一栅金属层图案至少包括第一栅电极、和第一电容电极，第一栅电极和第一电容电极形成在有效区域100。本次图案化工艺后，第二周边区包括设置在基底101上的第一绝缘层以及设置在第一绝缘层上的第二绝缘层。
(4)依次沉积第三绝缘薄膜和第二金属薄膜，通过图案化工艺对第二金属薄膜进行图案化处理，形成覆盖第一栅金属层的第三绝缘层，以及设置在第三绝缘层上的第二栅金属层和第一金属层图案，第二栅金属层图案至少包括第二电容电极，第一金属层包括第一触控引线2381、第二触控引线2382、阵列测试引线235和触控测试引线236，第二电容电极形成在有效区域100，第二电容电极的位置与第一电容电极的位置相对应，第一触控引线2381、第二触控引线2382、阵列测试引线235和触控测试引线236形成在第二周边区200。第一触控引线2381用于连接第一触控引脚区2321的触控引脚与有效区域的触控电极，第二触控引线2382用于连接第二触控引脚区2322的触控引脚与有效区域的触控电极；触控测试引线236用于连接触控引脚区232和第二触控引脚区243，阵列测试引线235用于连接第一栅极驱动电路引脚区231和第二栅极驱动电路引脚区241，且阵列测试引线235在基底上的正投影与触控测试引线236在基底上的正投影不交叠。第一金属层还包括构成 第二周边区的各个引脚中的第一金属层的图案。
(5)沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化处理，形成覆盖第二栅金属层的第四绝缘层图案，第四绝缘层上开设有多个过孔，多个过孔至少包括两个第一有源过孔。
在示例性实施方式中，两个第一有源过孔形成在有效区域100，两个第一有源过孔内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的表面。两个第一有源过孔用于使后续形成的源电极和漏电极分别与第一有源层连接。
(6)沉积第三金属薄膜，通过图案化工艺对第三金属薄膜进行图案化处理，在第四绝缘层上形成第一源漏金属层和第二金属层图案，第一源漏金属层至少包括源电极和漏电极。源电极和漏电极形成在有效区域100，分别通过第一有源过孔与第一有源层连接。
第二金属层形成在第一绑定区230和第二绑定区240，包括构成第二周边区的各个引脚中的第二金属层的图案。
(7)在形成前述图案的基底上，涂覆一层有机材料的第一平坦薄膜，形成覆盖有效区域的第一平坦(PLN)层，通过掩膜、曝光、显影的图案化工艺，在第一平坦层上形成有阳极过孔，阳极过孔形成在有效区域，阳极过孔内的第一平坦层被去掉，暴露出驱动晶体管的漏电极的表面。
至此，在基底上制备完成驱动结构层图案。在有效区域，第一有源层、第一栅电极、源电极和漏电极组成像素驱动电路中的驱动晶体管，第一电容电极和第二电容电极组成像素驱动电路中的存储电容。
(8)在形成前述图案的基底上，形成有效区域的发光元件图案。在示例性实施方式中，发光元件图案可以包括阳极、像素定义(PDL)层、隔垫柱(PS)、有机发光层、阴极。阳极设置在第一平坦层上，通过第一平坦层上开设的过孔与驱动晶体管的漏电极连接；像素定义层设置在阳极和平坦层上，像素定义层上设置有像素开口，像素开口暴露出阳极；有机发光层至少部分设置在像素开口内，有机发光层与阳极连接；阴极设置在有机发光层上，阴极与有机发光层连接；有机发光层在阳极和阴极驱动下出射相应颜色 的光线。
(9)在形成前述图案的基底上，形成封装层图案。封装层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层采用无机材料，第二封装层采用有机材料。
(10)在形成前述图案的基底上，沉积第四金属薄膜，通过图案化工艺对第四金属薄膜进行图案化，形成触控电极层和第三金属层图案。在有效区域100，触控电极层包括多个触控电极和多条触控走线。在第二周边区200，第三金属层包括构成第二周边区的各个引脚中的第三金属层的图案。在示例性实施例中，第二周边区的各个引脚由第一金属层、第二金属层和第三金属层依次叠加而成，第一金属层与第二金属层相连接，第二金属层与第三金属层相连接，所有引脚(包括虚拟引脚与非虚拟引脚，虚拟引脚即未引入电信号的引脚，非虚拟引脚即引入电信号的引脚)的高度一致，从而保证驱动芯片或FPC可以平整地绑定在触控显示面板上。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层。第一金属薄膜、第二金属薄膜、第三金属薄膜和第四金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
通过本公开示例性实施例触控显示基板的结构及其制备过程可以看出，本公开示例性实施例通过使得阵列测试引线在基底上的正投影与触控测试引线在基底上的正投影不交叠，避免了触控走线和栅极阵列走线相互交叉引起信号串扰的问题，提高了触控性能。
本公开示例性实施例触控显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，本公开在此不做限定。
本公开还提供了一种触控显示基板的制备方法，所述触控显示基板包括有效区域以及位于有效区域周边的第一周边区和第二周边区，第二周边区包括用于绑定驱动芯片的第一绑定区和位于第一绑定区远离有效区域一侧并用于绑定柔性线路板的第二绑定区，第一绑定区包括一栅极驱动电路引脚区和第一触控引脚区，第二绑定区包括与第一栅极驱动电路引脚区电连接的第二栅极驱动电路引脚区，以及与第一触控引脚区电连接的第二触控引脚区；所述制备方法包括：
在第二周边区形成触控测试引线和阵列测试引线，其中，触控测试引线连接第一触控引脚区和第二触控引脚区，阵列测试引线连接第一栅极驱动电路引脚区和第二栅极驱动电路引脚区，且阵列测试引线在基底上的正投影与触控测试引线在基底上的正投影不交叠。
在示例性实施例中，在垂直于触控显示基板的平面上，触控显示基板包括基底、设置在基底上的有源层、设置在有源层上的第一绝缘层、设置在第一绝缘层上的第一栅金属层、设置在第一栅金属层上的第二绝缘层、设置在第二绝缘层上的第二栅金属层、设置在第二栅金属层上的第三绝缘层以及设置在第三绝缘层上的源漏金属层；
阵列测试引线与第一栅金属层和第二栅金属层中的一层或多层同层设置，触控测试引线与源漏金属层同层设置。
本公开示例性实施例还提供了一种触控显示装置，包括前述实施例的触控显示基板。本公开触控显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。在示例性实施方式中，触控显示装置可以为穿戴式显示装置，能通过某些方式佩戴在人体上，如智能手表、智能手环等。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以 得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种触控显示基板，包括有效区域以及位于有效区域周边的第一周边区和第二周边区，其中：
    所述有效区域包括基底以及叠设在所述基底上的显示单元和触控单元，所述显示单元包括多条数据线、多条栅线和多个子像素，所述触控单元包括多个触控电极以及与所述触控电极连接的触控引线；
    所述第一周边区包括与所述多条栅线连接的栅极驱动电路；
    所述第二周边区包括用于绑定驱动芯片的第一绑定区和位于所述第一绑定区远离所述有效区域一侧并用于绑定柔性线路板的第二绑定区；
    所述第一绑定区包括第一栅极驱动电路引脚区和第一触控引脚区；
    所述第二绑定区包括与所述第一栅极驱动电路引脚区电连接的第二栅极驱动电路引脚区，以及与所述第一触控引脚区电连接的第二触控引脚区；
    所述第二周边区还包括连接第一触控引脚区和第二触控引脚区的触控测试引线，以及连接第一栅极驱动电路引脚区和第二栅极驱动电路引脚区的阵列测试引线，且阵列测试引线在基底上的正投影与触控测试引线在基底上的正投影不交叠。
  2. 根据权利要求1所述的触控显示基板，其中，所述第一绑定区包括第一侧边、与所述第一侧边相对的第二侧边以及连接于所述第一侧边与第二侧边之间的第三侧边和第四侧边，第一侧边位于靠近所述有效区域的一侧，所述第二侧边位于远离所述有效区域的一侧；
    所述第一栅极驱动电路引脚区包括第一子栅极驱动电路引脚区，所述第一子栅极驱动电路引脚区位于靠近所述第一侧边的一侧，且所述第一子栅极驱动电路引脚区靠近所述第三侧边或所述第四侧边设置；
    所述第一触控引脚区包括第一子触控引脚区，所述第一子触控引脚区位于靠近所述第三侧边或所述第四侧边的一侧，且所述第一子触控引脚区与所述第二侧边之间的距离小于所述第一子栅极驱动电路引脚区与所述第二侧边 之间的距离。
  3. 根据权利要求2所述的触控显示基板，其中，所述第一绑定区还包括输入引脚区和第一输出引脚区，其中，所述输入引脚区靠近所述第二侧边设置，所述第一输出引脚区靠近所述第一侧边设置。
  4. 根据权利要求3所述的触控显示基板，其中，所述第一输出引脚区包括第一子输出引脚区以及位于所述第一子输出引脚区一侧的空隙区；
    所述第一绑定区还包括多根第一触控引线，所述第一触控引线从所述第一子触控引脚区延伸并穿过所述空隙区后，与所述有效区域的触控电极连接。
  5. 根据权利要求4所述的触控显示基板，其中，所述第一绑定区还包括多个虚拟引脚，所述虚拟引脚设置在以下任意一个或多个位置：所述第一子触控引脚区、至少一根所述第一触控引线的一侧或两侧。
  6. 根据权利要求4所述的触控显示基板，其中，所述第一子触控引脚区包括多个第一触控引脚，多个所述第一触控引脚中的一个或多个与所述第一触控引线连接。
  7. 根据权利要求6所述的触控显示基板，其中，所述多个第一触控引脚包括两列或两列以上，且每一列的所述第一触控引脚与相邻列的所述第一触控引脚在第一方向上呈交错排列。
  8. 根据权利要求6所述的触控显示基板，其中，在垂直于触控显示基板的平面内，所述第一触控引脚包括：设置在基底上的第一金属层、设置在所述第一金属层之上的第二金属层以及设置在所述第二金属层之上的第三金属层；
    在垂直于触控显示基板的平面内，所述第一触控引线包括：设置在所述基底上的第一金属层。
  9. 根据权利要求1所述的触控显示基板，其中，所述第二绑定区包括第 五侧边、与所述第五侧边相对的第六侧边以及连接于所述第五侧边与第六侧边之间的第七侧边和第八侧边，所述第五侧边位于靠近所述第一绑定区的一侧，所述第六侧边位于远离所述第一绑定区的一侧；
    所述第二栅极驱动电路引脚区包括第三子栅极驱动电路引脚区，所述第二触控引脚区包括第三子触控引脚区；
    所述第三子栅极驱动电路引脚区和第三子触控引脚区位于所述第二绑定区靠近第七侧边的一侧，且所述第三子栅极驱动电路引脚区与所述第七侧边之间的距离小于所述第三子触控引脚区与所述第七侧边之间的距离。
  10. 根据权利要求9所述的触控显示基板，其中，所述第二绑定区还包括电源引脚区，其中，所述电源引脚区位于所述第三子栅极驱动电路引脚区以及所述第三子触控引脚区之间。
  11. 根据权利要求10所述的触控显示基板，还包括第一电源线和第二电源线，所述第一电源线从所述电源引脚区延伸至所述有效区域，所述第二电源线从所述电源引脚区延伸至所述第一周边区；
    所述阵列测试引线在所述基底上的正投影，与所述第一电源线和所述第二电源线中的一个或多个在所述基底上的正投影包含重叠区域。
  12. 根据权利要求11所述的触控显示基板，其中，所述第二周边区包括第一区和第二区，所述第一区位于所述第二绑定区与所述第二区之间，且所述阵列测试引线与所述触控测试引线在所述第一区之间的距离小于所述阵列测试引线与所述触控测试引线在所述第二区之间的距离。
  13. 根据权利要求12所述的触控显示基板，其中，在所述第一区，所述第一电源线和所述第二电源线中的一个或多个在所述基底上的正投影，位于所述阵列测试引线在所述基底上的正投影与所述触控测试引线在所述基底上的正投影之间。
  14. 一种触控显示装置，包括如权利要求1至权利要求13任一项所述的触控显示基板。
  15. 一种触控显示基板的制备方法，所述触控显示基板包括有效区域以及位于有效区域周边的第一周边区和第二周边区，所述第二周边区包括用于绑定驱动芯片的第一绑定区和位于所述第一绑定区远离所述有效区域一侧并用于绑定柔性线路板的第二绑定区，所述第一绑定区包括第一栅极驱动电路引脚区和第一触控引脚区，所述第二绑定区包括与所述第一栅极驱动电路引脚区电连接的第二栅极驱动电路引脚区，以及与所述第一触控引脚区电连接的第二触控引脚区；所述制备方法包括：
    在所述第二周边区形成触控测试引线和阵列测试引线，其中，所述触控测试引线连接所述第一触控引脚区和所述第二触控引脚区，所述阵列测试引线连接所述第一栅极驱动电路引脚区和所述第二栅极驱动电路引脚区，且所述阵列测试引线在基底上的正投影与所述触控测试引线在基底上的正投影不交叠。
PCT/CN2021/081887 2021-03-19 2021-03-19 触控显示基板及其制备方法、触控显示装置 WO2022193315A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/630,517 US20230359300A1 (en) 2021-03-19 2021-03-19 Touch Display Substrate, Manufacturing Method Therefor, and Touch Display Device
PCT/CN2021/081887 WO2022193315A1 (zh) 2021-03-19 2021-03-19 触控显示基板及其制备方法、触控显示装置
CN202180000536.1A CN115668111A (zh) 2021-03-19 2021-03-19 触控显示基板及其制备方法、触控显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/081887 WO2022193315A1 (zh) 2021-03-19 2021-03-19 触控显示基板及其制备方法、触控显示装置

Publications (1)

Publication Number Publication Date
WO2022193315A1 true WO2022193315A1 (zh) 2022-09-22

Family

ID=83321442

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/081887 WO2022193315A1 (zh) 2021-03-19 2021-03-19 触控显示基板及其制备方法、触控显示装置

Country Status (3)

Country Link
US (1) US20230359300A1 (zh)
CN (1) CN115668111A (zh)
WO (1) WO2022193315A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106292025A (zh) * 2015-06-12 2017-01-04 群创光电股份有限公司 触控显示装置
CN108415601A (zh) * 2018-03-12 2018-08-17 京东方科技集团股份有限公司 布线结构及其制造方法、显示装置
CN111090358A (zh) * 2019-11-29 2020-05-01 武汉华星光电技术有限公司 触控显示面板及其制作方法
CN111414099A (zh) * 2019-01-08 2020-07-14 瑞鼎科技股份有限公司 电容式触控面板
WO2020189894A1 (ko) * 2019-03-19 2020-09-24 주식회사 하이딥 디스플레이 장치
CN112035013A (zh) * 2020-08-31 2020-12-04 京东方科技集团股份有限公司 触控面板及其制备方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106292025A (zh) * 2015-06-12 2017-01-04 群创光电股份有限公司 触控显示装置
CN108415601A (zh) * 2018-03-12 2018-08-17 京东方科技集团股份有限公司 布线结构及其制造方法、显示装置
CN111414099A (zh) * 2019-01-08 2020-07-14 瑞鼎科技股份有限公司 电容式触控面板
WO2020189894A1 (ko) * 2019-03-19 2020-09-24 주식회사 하이딥 디스플레이 장치
CN111090358A (zh) * 2019-11-29 2020-05-01 武汉华星光电技术有限公司 触控显示面板及其制作方法
CN112035013A (zh) * 2020-08-31 2020-12-04 京东方科技集团股份有限公司 触控面板及其制备方法、显示装置

Also Published As

Publication number Publication date
US20230359300A1 (en) 2023-11-09
CN115668111A (zh) 2023-01-31

Similar Documents

Publication Publication Date Title
WO2022057491A1 (zh) 显示基板及其制备方法、显示装置
WO2023241490A1 (zh) 显示基板和显示装置
WO2022179189A1 (zh) 显示基板及其制备方法、显示装置
WO2023000125A1 (zh) 显示基板及其制备方法、显示装置
US20240081115A1 (en) Display substrate, manufacturing method thereof, and display device
WO2022160491A1 (zh) 显示基板及其制备方法、显示装置
WO2022021207A1 (zh) 显示基板及其制备方法、显示装置
WO2023004763A1 (zh) 显示基板及其制备方法、显示装置
WO2022241747A1 (zh) 显示基板及其制备方法、显示装置
WO2022227005A1 (zh) 显示基板及其制备方法、显示装置
US20220320228A1 (en) Display Substrate and Manufacturing Method Thereof, and Display Apparatus
WO2022082631A1 (zh) 显示基板及其制备方法、显示装置
WO2022193315A1 (zh) 触控显示基板及其制备方法、触控显示装置
WO2023115457A1 (zh) 显示基板及其驱动方法、显示装置
WO2022236680A9 (zh) 显示面板及其制备方法、显示触控装置
WO2023092473A1 (zh) 显示基板及其制备方法、显示装置
WO2023226050A1 (zh) 显示基板及其制备方法、显示装置
US20230180521A1 (en) Display Substrate, Preparation Method thereof, and Display Apparatus
WO2023000215A1 (zh) 显示基板及显示装置
WO2023178612A1 (zh) 显示基板及其制备方法、显示装置
WO2023279333A1 (zh) 显示基板及显示装置
WO2022252230A1 (zh) 显示基板和显示装置
WO2023230912A1 (zh) 显示基板及其制备方法、显示装置
WO2022227478A1 (zh) 一种显示基板及其制作方法、显示装置
WO2022170547A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21930904

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 18.01.2024)